1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
272 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
273 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
274 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
275 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
276 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
277 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
278 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
279 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
280 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
281 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
282 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
283 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
286 // Implicitly promote a 32-bit scalar to a vector.
287 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
288 (COPY_TO_REGCLASS FR32:$src, VR128)>;
289 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
290 (COPY_TO_REGCLASS FR32:$src, VR128)>;
291 // Implicitly promote a 64-bit scalar to a vector.
292 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
293 (COPY_TO_REGCLASS FR64:$src, VR128)>;
294 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
295 (COPY_TO_REGCLASS FR64:$src, VR128)>;
297 // Bitcasts between 128-bit vector types. Return the original type since
298 // no instruction is needed for the conversion
299 let Predicates = [HasSSE2] in {
300 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
304 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
309 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
314 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
319 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
324 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
328 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
329 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
332 // Bitcasts between 256-bit vector types. Return the original type since
333 // no instruction is needed for the conversion
334 let Predicates = [HasAVX] in {
335 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
339 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
344 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
349 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
354 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
359 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
363 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
364 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
367 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
368 // This is expanded by ExpandPostRAPseudos.
369 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
371 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
372 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
373 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
374 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
377 //===----------------------------------------------------------------------===//
378 // AVX & SSE - Zero/One Vectors
379 //===----------------------------------------------------------------------===//
381 // Alias instruction that maps zero vector to pxor / xorp* for sse.
382 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
383 // swizzled by ExecutionDepsFix to pxor.
384 // We set canFoldAsLoad because this can be converted to a constant-pool
385 // load of an all-zeros value if folding it would be beneficial.
386 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
388 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
389 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
392 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
394 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
395 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
396 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
399 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
400 // and doesn't need it because on sandy bridge the register is set to zero
401 // at the rename stage without using any execution unit, so SET0PSY
402 // and SET0PDY can be used for vector int instructions without penalty
403 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
404 isPseudo = 1, Predicates = [HasAVX] in {
405 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
406 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
409 let Predicates = [HasAVX] in
410 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
412 let Predicates = [HasAVX2] in {
413 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
414 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
415 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
416 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
419 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
420 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
421 let Predicates = [HasAVX1Only] in {
422 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
423 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
424 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
426 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 // We set canFoldAsLoad because this can be converted to a constant-pool
440 // load of an all-ones value if folding it would be beneficial.
441 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
443 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
444 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
445 let Predicates = [HasAVX2] in
446 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
447 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
451 //===----------------------------------------------------------------------===//
452 // SSE 1 & 2 - Move FP Scalar Instructions
454 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
455 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
456 // is used instead. Register-to-register movss/movsd is not modeled as an
457 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
458 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
459 //===----------------------------------------------------------------------===//
461 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
462 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
463 [(set VR128:$dst, (vt (OpNode VR128:$src1,
464 (scalar_to_vector RC:$src2))))],
467 // Loading from memory automatically zeroing upper bits.
468 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
469 PatFrag mem_pat, string OpcodeStr> :
470 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
471 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
472 [(set RC:$dst, (mem_pat addr:$src))],
476 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
477 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
479 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
480 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
483 // For the disassembler
484 let isCodeGenOnly = 1 in {
485 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
486 (ins VR128:$src1, FR32:$src2),
487 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
490 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
491 (ins VR128:$src1, FR64:$src2),
492 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
497 let canFoldAsLoad = 1, isReMaterializable = 1 in {
498 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
500 let AddedComplexity = 20 in
501 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
505 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
506 "movss\t{$src, $dst|$dst, $src}",
507 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
509 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
510 "movsd\t{$src, $dst|$dst, $src}",
511 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
515 let Constraints = "$src1 = $dst" in {
516 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
517 "movss\t{$src2, $dst|$dst, $src2}">, XS;
518 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
519 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
521 // For the disassembler
522 let isCodeGenOnly = 1 in {
523 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
524 (ins VR128:$src1, FR32:$src2),
525 "movss\t{$src2, $dst|$dst, $src2}", [],
526 IIC_SSE_MOV_S_RR>, XS;
527 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
528 (ins VR128:$src1, FR64:$src2),
529 "movsd\t{$src2, $dst|$dst, $src2}", [],
530 IIC_SSE_MOV_S_RR>, XD;
534 let canFoldAsLoad = 1, isReMaterializable = 1 in {
535 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
537 let AddedComplexity = 20 in
538 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
541 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
542 "movss\t{$src, $dst|$dst, $src}",
543 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
544 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
545 "movsd\t{$src, $dst|$dst, $src}",
546 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
549 let Predicates = [HasAVX] in {
550 let AddedComplexity = 15 in {
551 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
552 // MOVS{S,D} to the lower bits.
553 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
554 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
555 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
556 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
557 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
558 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
559 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
560 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
562 // Move low f32 and clear high bits.
563 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
564 (SUBREG_TO_REG (i32 0),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
567 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
568 (SUBREG_TO_REG (i32 0),
569 (VMOVSSrr (v4i32 (V_SET0)),
570 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
573 let AddedComplexity = 20 in {
574 // MOVSSrm zeros the high parts of the register; represent this
575 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
576 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
577 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
578 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
579 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
580 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
581 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
583 // MOVSDrm zeros the high parts of the register; represent this
584 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
585 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
586 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
587 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
588 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
589 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
590 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
591 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
592 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
593 def : Pat<(v2f64 (X86vzload addr:$src)),
594 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
596 // Represent the same patterns above but in the form they appear for
598 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
599 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
600 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
601 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
602 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
603 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
604 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
605 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
606 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
608 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
609 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
610 (SUBREG_TO_REG (i32 0),
611 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
613 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
614 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
615 (SUBREG_TO_REG (i64 0),
616 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
618 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
619 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
620 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
622 // Move low f64 and clear high bits.
623 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
624 (SUBREG_TO_REG (i32 0),
625 (VMOVSDrr (v2f64 (V_SET0)),
626 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
628 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
629 (SUBREG_TO_REG (i32 0),
630 (VMOVSDrr (v2i64 (V_SET0)),
631 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
633 // Extract and store.
634 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
636 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
637 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
639 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
641 // Shuffle with VMOVSS
642 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
643 (VMOVSSrr (v4i32 VR128:$src1),
644 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
645 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
646 (VMOVSSrr (v4f32 VR128:$src1),
647 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
650 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
651 (SUBREG_TO_REG (i32 0),
652 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
653 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
655 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
656 (SUBREG_TO_REG (i32 0),
657 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
658 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
661 // Shuffle with VMOVSD
662 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
663 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
664 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
665 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
666 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
667 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
668 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
669 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
673 (SUBREG_TO_REG (i32 0),
674 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
675 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
677 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
678 (SUBREG_TO_REG (i32 0),
679 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
680 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
684 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
685 // is during lowering, where it's not possible to recognize the fold cause
686 // it has two uses through a bitcast. One use disappears at isel time and the
687 // fold opportunity reappears.
688 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
689 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
690 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
691 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
692 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
693 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
694 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
695 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
698 let Predicates = [UseSSE1] in {
699 let AddedComplexity = 15 in {
700 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
701 // MOVSS to the lower bits.
702 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
703 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
704 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
705 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
706 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
707 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
710 let AddedComplexity = 20 in {
711 // MOVSSrm already zeros the high parts of the register.
712 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
713 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
714 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
715 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
716 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
717 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
720 // Extract and store.
721 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
723 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
725 // Shuffle with MOVSS
726 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
727 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
728 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
729 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
732 let Predicates = [UseSSE2] in {
733 let AddedComplexity = 15 in {
734 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
735 // MOVSD to the lower bits.
736 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
737 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
740 let AddedComplexity = 20 in {
741 // MOVSDrm already zeros the high parts of the register.
742 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
743 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
744 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
745 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
746 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
747 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
748 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
749 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
750 def : Pat<(v2f64 (X86vzload addr:$src)),
751 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
754 // Extract and store.
755 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
757 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
759 // Shuffle with MOVSD
760 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
761 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
762 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
763 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
764 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
765 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
766 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
767 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
769 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
770 // is during lowering, where it's not possible to recognize the fold cause
771 // it has two uses through a bitcast. One use disappears at isel time and the
772 // fold opportunity reappears.
773 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
774 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
775 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
776 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
777 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
778 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
779 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
780 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
783 //===----------------------------------------------------------------------===//
784 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
785 //===----------------------------------------------------------------------===//
787 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
788 X86MemOperand x86memop, PatFrag ld_frag,
789 string asm, Domain d,
791 bit IsReMaterializable = 1> {
792 let neverHasSideEffects = 1 in
793 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
794 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
795 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
796 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
797 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
798 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
801 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
802 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
804 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
805 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
807 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
808 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
810 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
811 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
814 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
815 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
817 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
818 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
820 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
821 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
823 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
824 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
826 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
827 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
829 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
830 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
832 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
833 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
835 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
836 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
839 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
840 "movaps\t{$src, $dst|$dst, $src}",
841 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
842 IIC_SSE_MOVA_P_MR>, VEX;
843 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
844 "movapd\t{$src, $dst|$dst, $src}",
845 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
846 IIC_SSE_MOVA_P_MR>, VEX;
847 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
848 "movups\t{$src, $dst|$dst, $src}",
849 [(store (v4f32 VR128:$src), addr:$dst)],
850 IIC_SSE_MOVU_P_MR>, VEX;
851 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
852 "movupd\t{$src, $dst|$dst, $src}",
853 [(store (v2f64 VR128:$src), addr:$dst)],
854 IIC_SSE_MOVU_P_MR>, VEX;
855 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
856 "movaps\t{$src, $dst|$dst, $src}",
857 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
858 IIC_SSE_MOVA_P_MR>, VEX;
859 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
860 "movapd\t{$src, $dst|$dst, $src}",
861 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
862 IIC_SSE_MOVA_P_MR>, VEX;
863 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
864 "movups\t{$src, $dst|$dst, $src}",
865 [(store (v8f32 VR256:$src), addr:$dst)],
866 IIC_SSE_MOVU_P_MR>, VEX;
867 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
868 "movupd\t{$src, $dst|$dst, $src}",
869 [(store (v4f64 VR256:$src), addr:$dst)],
870 IIC_SSE_MOVU_P_MR>, VEX;
873 let isCodeGenOnly = 1 in {
874 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
876 "movaps\t{$src, $dst|$dst, $src}", [],
877 IIC_SSE_MOVA_P_RR>, VEX;
878 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
880 "movapd\t{$src, $dst|$dst, $src}", [],
881 IIC_SSE_MOVA_P_RR>, VEX;
882 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
884 "movups\t{$src, $dst|$dst, $src}", [],
885 IIC_SSE_MOVU_P_RR>, VEX;
886 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
888 "movupd\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVU_P_RR>, VEX;
890 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
892 "movaps\t{$src, $dst|$dst, $src}", [],
893 IIC_SSE_MOVA_P_RR>, VEX;
894 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
896 "movapd\t{$src, $dst|$dst, $src}", [],
897 IIC_SSE_MOVA_P_RR>, VEX;
898 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
900 "movups\t{$src, $dst|$dst, $src}", [],
901 IIC_SSE_MOVU_P_RR>, VEX;
902 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
904 "movupd\t{$src, $dst|$dst, $src}", [],
905 IIC_SSE_MOVU_P_RR>, VEX;
908 let Predicates = [HasAVX] in {
909 def : Pat<(v8i32 (X86vzmovl
910 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
911 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
912 def : Pat<(v4i64 (X86vzmovl
913 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
914 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
915 def : Pat<(v8f32 (X86vzmovl
916 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
917 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
918 def : Pat<(v4f64 (X86vzmovl
919 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
920 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
924 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
925 (VMOVUPSYmr addr:$dst, VR256:$src)>;
926 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
927 (VMOVUPDYmr addr:$dst, VR256:$src)>;
929 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
930 "movaps\t{$src, $dst|$dst, $src}",
931 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
933 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
934 "movapd\t{$src, $dst|$dst, $src}",
935 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
937 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
938 "movups\t{$src, $dst|$dst, $src}",
939 [(store (v4f32 VR128:$src), addr:$dst)],
941 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
942 "movupd\t{$src, $dst|$dst, $src}",
943 [(store (v2f64 VR128:$src), addr:$dst)],
947 let isCodeGenOnly = 1 in {
948 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
949 "movaps\t{$src, $dst|$dst, $src}", [],
951 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
952 "movapd\t{$src, $dst|$dst, $src}", [],
954 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
955 "movups\t{$src, $dst|$dst, $src}", [],
957 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
958 "movupd\t{$src, $dst|$dst, $src}", [],
962 let Predicates = [HasAVX] in {
963 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
964 (VMOVUPSmr addr:$dst, VR128:$src)>;
965 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
966 (VMOVUPDmr addr:$dst, VR128:$src)>;
969 let Predicates = [UseSSE1] in
970 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
971 (MOVUPSmr addr:$dst, VR128:$src)>;
972 let Predicates = [UseSSE2] in
973 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
974 (MOVUPDmr addr:$dst, VR128:$src)>;
976 // Use vmovaps/vmovups for AVX integer load/store.
977 let Predicates = [HasAVX] in {
978 // 128-bit load/store
979 def : Pat<(alignedloadv2i64 addr:$src),
980 (VMOVAPSrm addr:$src)>;
981 def : Pat<(loadv2i64 addr:$src),
982 (VMOVUPSrm addr:$src)>;
984 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
985 (VMOVAPSmr addr:$dst, VR128:$src)>;
986 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
987 (VMOVAPSmr addr:$dst, VR128:$src)>;
988 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
989 (VMOVAPSmr addr:$dst, VR128:$src)>;
990 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
991 (VMOVAPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
993 (VMOVUPSmr addr:$dst, VR128:$src)>;
994 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
995 (VMOVUPSmr addr:$dst, VR128:$src)>;
996 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
999 (VMOVUPSmr addr:$dst, VR128:$src)>;
1001 // 256-bit load/store
1002 def : Pat<(alignedloadv4i64 addr:$src),
1003 (VMOVAPSYrm addr:$src)>;
1004 def : Pat<(loadv4i64 addr:$src),
1005 (VMOVUPSYrm addr:$src)>;
1006 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1007 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1008 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1009 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1010 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1011 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1012 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1013 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1014 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1015 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1016 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1017 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1018 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1019 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1020 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1021 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1023 // Special patterns for storing subvector extracts of lower 128-bits
1024 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1025 def : Pat<(alignedstore (v2f64 (extract_subvector
1026 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1027 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1028 def : Pat<(alignedstore (v4f32 (extract_subvector
1029 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1030 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1031 def : Pat<(alignedstore (v2i64 (extract_subvector
1032 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1033 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1034 def : Pat<(alignedstore (v4i32 (extract_subvector
1035 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1036 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1037 def : Pat<(alignedstore (v8i16 (extract_subvector
1038 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1039 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1040 def : Pat<(alignedstore (v16i8 (extract_subvector
1041 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1042 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1044 def : Pat<(store (v2f64 (extract_subvector
1045 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1046 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1047 def : Pat<(store (v4f32 (extract_subvector
1048 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1049 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1050 def : Pat<(store (v2i64 (extract_subvector
1051 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1052 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1053 def : Pat<(store (v4i32 (extract_subvector
1054 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1055 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1056 def : Pat<(store (v8i16 (extract_subvector
1057 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1058 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1059 def : Pat<(store (v16i8 (extract_subvector
1060 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1061 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 // Use movaps / movups for SSE integer load / store (one byte shorter).
1065 // The instructions selected below are then converted to MOVDQA/MOVDQU
1066 // during the SSE domain pass.
1067 let Predicates = [UseSSE1] in {
1068 def : Pat<(alignedloadv2i64 addr:$src),
1069 (MOVAPSrm addr:$src)>;
1070 def : Pat<(loadv2i64 addr:$src),
1071 (MOVUPSrm addr:$src)>;
1073 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1074 (MOVAPSmr addr:$dst, VR128:$src)>;
1075 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1076 (MOVAPSmr addr:$dst, VR128:$src)>;
1077 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1078 (MOVAPSmr addr:$dst, VR128:$src)>;
1079 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1080 (MOVAPSmr addr:$dst, VR128:$src)>;
1081 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1082 (MOVUPSmr addr:$dst, VR128:$src)>;
1083 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1084 (MOVUPSmr addr:$dst, VR128:$src)>;
1085 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1086 (MOVUPSmr addr:$dst, VR128:$src)>;
1087 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1088 (MOVUPSmr addr:$dst, VR128:$src)>;
1091 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1092 // bits are disregarded. FIXME: Set encoding to pseudo!
1093 let neverHasSideEffects = 1 in {
1094 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1095 "movaps\t{$src, $dst|$dst, $src}", [],
1096 IIC_SSE_MOVA_P_RR>, VEX;
1097 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1098 "movapd\t{$src, $dst|$dst, $src}", [],
1099 IIC_SSE_MOVA_P_RR>, VEX;
1100 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1101 "movaps\t{$src, $dst|$dst, $src}", [],
1103 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1104 "movapd\t{$src, $dst|$dst, $src}", [],
1108 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1109 // bits are disregarded. FIXME: Set encoding to pseudo!
1110 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1111 let isCodeGenOnly = 1 in {
1112 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1113 "movaps\t{$src, $dst|$dst, $src}",
1114 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1115 IIC_SSE_MOVA_P_RM>, VEX;
1116 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1117 "movapd\t{$src, $dst|$dst, $src}",
1118 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1119 IIC_SSE_MOVA_P_RM>, VEX;
1121 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1122 "movaps\t{$src, $dst|$dst, $src}",
1123 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1125 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1126 "movapd\t{$src, $dst|$dst, $src}",
1127 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1131 //===----------------------------------------------------------------------===//
1132 // SSE 1 & 2 - Move Low packed FP Instructions
1133 //===----------------------------------------------------------------------===//
1135 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1136 SDNode psnode, SDNode pdnode, string base_opc,
1137 string asm_opr, InstrItinClass itin> {
1138 def PSrm : PI<opc, MRMSrcMem,
1139 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1140 !strconcat(base_opc, "s", asm_opr),
1143 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1144 itin, SSEPackedSingle>, TB;
1146 def PDrm : PI<opc, MRMSrcMem,
1147 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1148 !strconcat(base_opc, "d", asm_opr),
1149 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1150 (scalar_to_vector (loadf64 addr:$src2)))))],
1151 itin, SSEPackedDouble>, TB, OpSize;
1154 let AddedComplexity = 20 in {
1155 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1156 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1157 IIC_SSE_MOV_LH>, VEX_4V;
1159 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1160 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1161 "\t{$src2, $dst|$dst, $src2}",
1165 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1166 "movlps\t{$src, $dst|$dst, $src}",
1167 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1168 (iPTR 0))), addr:$dst)],
1169 IIC_SSE_MOV_LH>, VEX;
1170 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1171 "movlpd\t{$src, $dst|$dst, $src}",
1172 [(store (f64 (vector_extract (v2f64 VR128:$src),
1173 (iPTR 0))), addr:$dst)],
1174 IIC_SSE_MOV_LH>, VEX;
1175 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1176 "movlps\t{$src, $dst|$dst, $src}",
1177 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1178 (iPTR 0))), addr:$dst)],
1180 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1181 "movlpd\t{$src, $dst|$dst, $src}",
1182 [(store (f64 (vector_extract (v2f64 VR128:$src),
1183 (iPTR 0))), addr:$dst)],
1186 let Predicates = [HasAVX] in {
1187 // Shuffle with VMOVLPS
1188 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1189 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1190 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1191 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1193 // Shuffle with VMOVLPD
1194 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1195 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1196 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1197 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1200 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1202 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1203 def : Pat<(store (v4i32 (X86Movlps
1204 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1205 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1206 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1208 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1209 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1211 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1214 let Predicates = [UseSSE1] in {
1215 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1216 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1217 (iPTR 0))), addr:$src1),
1218 (MOVLPSmr addr:$src1, VR128:$src2)>;
1220 // Shuffle with MOVLPS
1221 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1222 (MOVLPSrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1224 (MOVLPSrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(X86Movlps VR128:$src1,
1226 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1227 (MOVLPSrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (MOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1236 (MOVLPSmr addr:$src1, VR128:$src2)>;
1239 let Predicates = [UseSSE2] in {
1240 // Shuffle with MOVLPD
1241 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1242 (MOVLPDrm VR128:$src1, addr:$src2)>;
1243 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1244 (MOVLPDrm VR128:$src1, addr:$src2)>;
1247 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1249 (MOVLPDmr addr:$src1, VR128:$src2)>;
1250 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1252 (MOVLPDmr addr:$src1, VR128:$src2)>;
1255 //===----------------------------------------------------------------------===//
1256 // SSE 1 & 2 - Move Hi packed FP Instructions
1257 //===----------------------------------------------------------------------===//
1259 let AddedComplexity = 20 in {
1260 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1261 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1262 IIC_SSE_MOV_LH>, VEX_4V;
1264 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1265 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1266 "\t{$src2, $dst|$dst, $src2}",
1270 // v2f64 extract element 1 is always custom lowered to unpack high to low
1271 // and extract element 0 so the non-store version isn't too horrible.
1272 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1273 "movhps\t{$src, $dst|$dst, $src}",
1274 [(store (f64 (vector_extract
1275 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1276 (bc_v2f64 (v4f32 VR128:$src))),
1277 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1278 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1279 "movhpd\t{$src, $dst|$dst, $src}",
1280 [(store (f64 (vector_extract
1281 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1282 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1283 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1284 "movhps\t{$src, $dst|$dst, $src}",
1285 [(store (f64 (vector_extract
1286 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1287 (bc_v2f64 (v4f32 VR128:$src))),
1288 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1289 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1290 "movhpd\t{$src, $dst|$dst, $src}",
1291 [(store (f64 (vector_extract
1292 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1293 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1295 let Predicates = [HasAVX] in {
1297 def : Pat<(X86Movlhps VR128:$src1,
1298 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1299 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1300 def : Pat<(X86Movlhps VR128:$src1,
1301 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1302 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1304 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1305 // is during lowering, where it's not possible to recognize the load fold
1306 // cause it has two uses through a bitcast. One use disappears at isel time
1307 // and the fold opportunity reappears.
1308 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1309 (scalar_to_vector (loadf64 addr:$src2)))),
1310 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1313 let Predicates = [UseSSE1] in {
1315 def : Pat<(X86Movlhps VR128:$src1,
1316 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1317 (MOVHPSrm VR128:$src1, addr:$src2)>;
1318 def : Pat<(X86Movlhps VR128:$src1,
1319 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1320 (MOVHPSrm VR128:$src1, addr:$src2)>;
1323 let Predicates = [UseSSE2] in {
1324 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1325 // is during lowering, where it's not possible to recognize the load fold
1326 // cause it has two uses through a bitcast. One use disappears at isel time
1327 // and the fold opportunity reappears.
1328 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1329 (scalar_to_vector (loadf64 addr:$src2)))),
1330 (MOVHPDrm VR128:$src1, addr:$src2)>;
1333 //===----------------------------------------------------------------------===//
1334 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1335 //===----------------------------------------------------------------------===//
1337 let AddedComplexity = 20 in {
1338 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1339 (ins VR128:$src1, VR128:$src2),
1340 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1342 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1345 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1346 (ins VR128:$src1, VR128:$src2),
1347 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1349 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1353 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1354 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1355 (ins VR128:$src1, VR128:$src2),
1356 "movlhps\t{$src2, $dst|$dst, $src2}",
1358 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1360 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1361 (ins VR128:$src1, VR128:$src2),
1362 "movhlps\t{$src2, $dst|$dst, $src2}",
1364 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1368 let Predicates = [HasAVX] in {
1370 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1371 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1372 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1373 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1376 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1377 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1380 let Predicates = [UseSSE1] in {
1382 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1383 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1384 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1385 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1388 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1389 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1392 //===----------------------------------------------------------------------===//
1393 // SSE 1 & 2 - Conversion Instructions
1394 //===----------------------------------------------------------------------===//
1396 def SSE_CVT_PD : OpndItins<
1397 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1400 def SSE_CVT_PS : OpndItins<
1401 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1404 def SSE_CVT_Scalar : OpndItins<
1405 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1408 def SSE_CVT_SS2SI_32 : OpndItins<
1409 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1412 def SSE_CVT_SS2SI_64 : OpndItins<
1413 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1416 def SSE_CVT_SD2SI : OpndItins<
1417 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1420 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1421 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1422 string asm, OpndItins itins> {
1423 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1424 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1426 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1427 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1431 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1432 X86MemOperand x86memop, string asm, Domain d,
1434 let neverHasSideEffects = 1 in {
1435 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1438 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1443 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1444 X86MemOperand x86memop, string asm> {
1445 let neverHasSideEffects = 1 in {
1446 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1447 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1449 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1450 (ins DstRC:$src1, x86memop:$src),
1451 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1452 } // neverHasSideEffects = 1
1455 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1456 "cvttss2si\t{$src, $dst|$dst, $src}",
1459 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1460 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1462 XS, VEX, VEX_W, VEX_LIG;
1463 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1464 "cvttsd2si\t{$src, $dst|$dst, $src}",
1467 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1468 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1470 XD, VEX, VEX_W, VEX_LIG;
1472 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1473 // register, but the same isn't true when only using memory operands,
1474 // provide other assembly "l" and "q" forms to address this explicitly
1475 // where appropriate to do so.
1476 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1477 XS, VEX_4V, VEX_LIG;
1478 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1479 XS, VEX_4V, VEX_W, VEX_LIG;
1480 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1481 XD, VEX_4V, VEX_LIG;
1482 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1483 XD, VEX_4V, VEX_W, VEX_LIG;
1485 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1486 (VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
1487 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1488 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1490 let Predicates = [HasAVX] in {
1491 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1492 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1493 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1494 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1495 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1496 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1497 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1498 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1500 def : Pat<(f32 (sint_to_fp GR32:$src)),
1501 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1502 def : Pat<(f32 (sint_to_fp GR64:$src)),
1503 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1504 def : Pat<(f64 (sint_to_fp GR32:$src)),
1505 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1506 def : Pat<(f64 (sint_to_fp GR64:$src)),
1507 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1510 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1511 "cvttss2si\t{$src, $dst|$dst, $src}",
1512 SSE_CVT_SS2SI_32>, XS;
1513 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1514 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1515 SSE_CVT_SS2SI_64>, XS, REX_W;
1516 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1517 "cvttsd2si\t{$src, $dst|$dst, $src}",
1519 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1520 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1521 SSE_CVT_SD2SI>, XD, REX_W;
1522 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1523 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1524 SSE_CVT_Scalar>, XS;
1525 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1526 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1527 SSE_CVT_Scalar>, XS, REX_W;
1528 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1529 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1530 SSE_CVT_Scalar>, XD;
1531 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1532 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1533 SSE_CVT_Scalar>, XD, REX_W;
1535 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1536 // and/or XMM operand(s).
1538 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1539 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1540 string asm, OpndItins itins> {
1541 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1542 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1543 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1544 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1545 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1546 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>;
1549 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1550 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1551 PatFrag ld_frag, string asm, OpndItins itins,
1553 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1555 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1556 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1557 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1559 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1560 (ins DstRC:$src1, x86memop:$src2),
1562 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1563 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1564 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1568 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1569 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si{l}",
1570 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1571 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1572 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si{q}",
1573 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1575 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1576 sdmem, sse_load_f64, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1577 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1578 sdmem, sse_load_f64, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1581 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1582 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1583 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1584 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1585 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1586 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1588 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1589 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1590 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1591 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1592 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1593 SSE_CVT_Scalar, 0>, XD,
1596 let Constraints = "$src1 = $dst" in {
1597 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1598 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1599 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1600 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1601 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1602 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1603 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1604 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1605 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1606 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1607 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1608 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1613 // Aliases for intrinsics
1614 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1615 ssmem, sse_load_f32, "cvttss2si",
1616 SSE_CVT_SS2SI_32>, XS, VEX;
1617 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1618 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1619 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1621 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1622 sdmem, sse_load_f64, "cvttsd2si",
1623 SSE_CVT_SD2SI>, XD, VEX;
1624 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1625 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1626 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1628 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1629 ssmem, sse_load_f32, "cvttss2si",
1630 SSE_CVT_SS2SI_32>, XS;
1631 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1632 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1633 "cvttss2si{q}", SSE_CVT_SS2SI_64>, XS, REX_W;
1634 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1635 sdmem, sse_load_f64, "cvttsd2si",
1637 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1638 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1639 "cvttsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1641 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1642 ssmem, sse_load_f32, "cvtss2si{l}",
1643 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1644 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1645 ssmem, sse_load_f32, "cvtss2si{q}",
1646 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1648 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1649 ssmem, sse_load_f32, "cvtss2si{l}",
1650 SSE_CVT_SS2SI_32>, XS;
1651 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1652 ssmem, sse_load_f32, "cvtss2si{q}",
1653 SSE_CVT_SS2SI_64>, XS, REX_W;
1655 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1656 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1657 SSEPackedSingle, SSE_CVT_PS>,
1658 TB, VEX, Requires<[HasAVX]>;
1659 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1660 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1661 SSEPackedSingle, SSE_CVT_PS>,
1662 TB, VEX, Requires<[HasAVX]>;
1664 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1665 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1666 SSEPackedSingle, SSE_CVT_PS>,
1667 TB, Requires<[UseSSE2]>;
1671 // Convert scalar double to scalar single
1672 let neverHasSideEffects = 1 in {
1673 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1674 (ins FR64:$src1, FR64:$src2),
1675 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1676 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1678 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1679 (ins FR64:$src1, f64mem:$src2),
1680 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1681 [], IIC_SSE_CVT_Scalar_RM>,
1682 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1685 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1688 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1689 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1690 [(set FR32:$dst, (fround FR64:$src))],
1691 IIC_SSE_CVT_Scalar_RR>;
1692 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1693 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1694 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1695 IIC_SSE_CVT_Scalar_RM>,
1697 Requires<[UseSSE2, OptForSize]>;
1699 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1700 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1701 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1703 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1704 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
1705 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1706 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1707 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1708 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1709 VR128:$src1, sse_load_f64:$src2))],
1710 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
1712 let Constraints = "$src1 = $dst" in {
1713 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1714 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1715 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1717 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1718 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>;
1719 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1720 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1721 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1722 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1723 VR128:$src1, sse_load_f64:$src2))],
1724 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>;
1727 // Convert scalar single to scalar double
1728 // SSE2 instructions with XS prefix
1729 let neverHasSideEffects = 1 in {
1730 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1731 (ins FR32:$src1, FR32:$src2),
1732 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1733 [], IIC_SSE_CVT_Scalar_RR>,
1734 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1736 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1737 (ins FR32:$src1, f32mem:$src2),
1738 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1739 [], IIC_SSE_CVT_Scalar_RM>,
1740 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1743 def : Pat<(f64 (fextend FR32:$src)),
1744 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1745 def : Pat<(fextend (loadf32 addr:$src)),
1746 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1748 def : Pat<(extloadf32 addr:$src),
1749 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1750 Requires<[HasAVX, OptForSize]>;
1751 def : Pat<(extloadf32 addr:$src),
1752 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1753 Requires<[HasAVX, OptForSpeed]>;
1755 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1756 "cvtss2sd\t{$src, $dst|$dst, $src}",
1757 [(set FR64:$dst, (fextend FR32:$src))],
1758 IIC_SSE_CVT_Scalar_RR>, XS,
1759 Requires<[UseSSE2]>;
1760 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1761 "cvtss2sd\t{$src, $dst|$dst, $src}",
1762 [(set FR64:$dst, (extloadf32 addr:$src))],
1763 IIC_SSE_CVT_Scalar_RM>, XS,
1764 Requires<[UseSSE2, OptForSize]>;
1766 // extload f32 -> f64. This matches load+fextend because we have a hack in
1767 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1769 // Since these loads aren't folded into the fextend, we have to match it
1771 def : Pat<(fextend (loadf32 addr:$src)),
1772 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1773 def : Pat<(extloadf32 addr:$src),
1774 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1776 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1777 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1778 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1780 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1781 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
1782 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1783 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1784 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1786 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1787 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
1788 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1789 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1790 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1791 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1793 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1794 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>;
1795 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1796 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1797 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1799 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1800 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>;
1803 // Convert packed single/double fp to doubleword
1804 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvtps2dq\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1807 IIC_SSE_CVT_PS_RR>, VEX;
1808 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1809 "cvtps2dq\t{$src, $dst|$dst, $src}",
1811 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1812 IIC_SSE_CVT_PS_RM>, VEX;
1813 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1814 "cvtps2dq\t{$src, $dst|$dst, $src}",
1816 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1817 IIC_SSE_CVT_PS_RR>, VEX;
1818 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1819 "cvtps2dq\t{$src, $dst|$dst, $src}",
1821 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1822 IIC_SSE_CVT_PS_RM>, VEX;
1823 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1824 "cvtps2dq\t{$src, $dst|$dst, $src}",
1825 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1827 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1828 "cvtps2dq\t{$src, $dst|$dst, $src}",
1830 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1834 // Convert Packed Double FP to Packed DW Integers
1835 let Predicates = [HasAVX] in {
1836 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1837 // register, but the same isn't true when using memory operands instead.
1838 // Provide other assembly rr and rm forms to address this explicitly.
1839 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1840 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1841 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1845 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1846 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1847 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1848 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1850 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
1853 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1854 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1856 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX;
1857 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1858 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1860 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1862 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1863 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1866 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1867 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1869 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1871 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1872 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1873 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1876 // Convert with truncation packed single/double fp to doubleword
1877 // SSE2 packed instructions with XS prefix
1878 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1879 "cvttps2dq\t{$src, $dst|$dst, $src}",
1881 (int_x86_sse2_cvttps2dq VR128:$src))],
1882 IIC_SSE_CVT_PS_RR>, VEX;
1883 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1884 "cvttps2dq\t{$src, $dst|$dst, $src}",
1885 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1886 (memopv4f32 addr:$src)))],
1887 IIC_SSE_CVT_PS_RM>, VEX;
1888 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1889 "cvttps2dq\t{$src, $dst|$dst, $src}",
1891 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1892 IIC_SSE_CVT_PS_RR>, VEX;
1893 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1894 "cvttps2dq\t{$src, $dst|$dst, $src}",
1895 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1896 (memopv8f32 addr:$src)))],
1897 IIC_SSE_CVT_PS_RM>, VEX;
1899 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 "cvttps2dq\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1903 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1904 "cvttps2dq\t{$src, $dst|$dst, $src}",
1906 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1909 let Predicates = [HasAVX] in {
1910 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1911 (VCVTDQ2PSrr VR128:$src)>;
1912 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1913 (VCVTDQ2PSrm addr:$src)>;
1915 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1916 (VCVTDQ2PSrr VR128:$src)>;
1917 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1918 (VCVTDQ2PSrm addr:$src)>;
1920 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1921 (VCVTTPS2DQrr VR128:$src)>;
1922 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1923 (VCVTTPS2DQrm addr:$src)>;
1925 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1926 (VCVTDQ2PSYrr VR256:$src)>;
1927 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1928 (VCVTDQ2PSYrm addr:$src)>;
1930 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1931 (VCVTTPS2DQYrr VR256:$src)>;
1932 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1933 (VCVTTPS2DQYrm addr:$src)>;
1936 let Predicates = [UseSSE2] in {
1937 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1938 (CVTDQ2PSrr VR128:$src)>;
1939 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1940 (CVTDQ2PSrm addr:$src)>;
1942 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1943 (CVTDQ2PSrr VR128:$src)>;
1944 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1945 (CVTDQ2PSrm addr:$src)>;
1947 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1948 (CVTTPS2DQrr VR128:$src)>;
1949 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1950 (CVTTPS2DQrm addr:$src)>;
1953 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1954 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1956 (int_x86_sse2_cvttpd2dq VR128:$src))],
1957 IIC_SSE_CVT_PD_RR>, VEX;
1959 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1960 // register, but the same isn't true when using memory operands instead.
1961 // Provide other assembly rr and rm forms to address this explicitly.
1964 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
1965 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
1966 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1967 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
1968 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1969 (memopv2f64 addr:$src)))],
1970 IIC_SSE_CVT_PD_RM>, VEX;
1973 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1974 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1976 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
1977 IIC_SSE_CVT_PD_RR>, VEX;
1978 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1979 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1981 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
1982 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1983 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
1984 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
1986 let Predicates = [HasAVX] in {
1987 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
1988 (VCVTTPD2DQYrr VR256:$src)>;
1989 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
1990 (VCVTTPD2DQYrm addr:$src)>;
1991 } // Predicates = [HasAVX]
1993 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1994 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1995 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1997 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1998 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1999 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2000 (memopv2f64 addr:$src)))],
2003 // Convert packed single to packed double
2004 let Predicates = [HasAVX] in {
2005 // SSE2 instructions without OpSize prefix
2006 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2007 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2008 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2009 IIC_SSE_CVT_PD_RR>, TB, VEX;
2010 let neverHasSideEffects = 1, mayLoad = 1 in
2011 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2012 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2013 IIC_SSE_CVT_PD_RM>, TB, VEX;
2014 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2015 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2017 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2018 IIC_SSE_CVT_PD_RR>, TB, VEX;
2019 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2020 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2022 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2023 IIC_SSE_CVT_PD_RM>, TB, VEX;
2026 let Predicates = [UseSSE2] in {
2027 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2028 "cvtps2pd\t{$src, $dst|$dst, $src}",
2029 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2030 IIC_SSE_CVT_PD_RR>, TB;
2031 let neverHasSideEffects = 1, mayLoad = 1 in
2032 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2033 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2034 IIC_SSE_CVT_PD_RM>, TB;
2037 // Convert Packed DW Integers to Packed Double FP
2038 let Predicates = [HasAVX] in {
2039 let neverHasSideEffects = 1, mayLoad = 1 in
2040 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2041 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2043 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
2047 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2048 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2050 (int_x86_avx_cvtdq2_pd_256
2051 (bitconvert (memopv2i64 addr:$src))))]>, VEX;
2052 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2053 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2055 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX;
2058 let neverHasSideEffects = 1, mayLoad = 1 in
2059 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2060 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2062 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2063 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2064 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2067 // AVX 256-bit register conversion intrinsics
2068 let Predicates = [HasAVX] in {
2069 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2070 (VCVTDQ2PDYrr VR128:$src)>;
2071 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2072 (VCVTDQ2PDYrm addr:$src)>;
2073 } // Predicates = [HasAVX]
2075 // Convert packed double to packed single
2076 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2077 // register, but the same isn't true when using memory operands instead.
2078 // Provide other assembly rr and rm forms to address this explicitly.
2079 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2080 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2081 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2082 IIC_SSE_CVT_PD_RR>, VEX;
2085 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2086 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2087 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2088 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2090 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2091 IIC_SSE_CVT_PD_RM>, VEX;
2094 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2095 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2097 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2098 IIC_SSE_CVT_PD_RR>, VEX;
2099 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2100 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2102 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2103 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2104 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2105 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2107 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2108 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2109 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2111 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2112 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2114 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2118 // AVX 256-bit register conversion intrinsics
2119 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2120 // whenever possible to avoid declaring two versions of each one.
2121 let Predicates = [HasAVX] in {
2122 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2123 (VCVTDQ2PSYrr VR256:$src)>;
2124 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2125 (VCVTDQ2PSYrm addr:$src)>;
2127 // Match fround and fextend for 128/256-bit conversions
2128 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2129 (VCVTPD2PSYrr VR256:$src)>;
2130 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2131 (VCVTPD2PSYrm addr:$src)>;
2133 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2134 (VCVTPS2PDrr VR128:$src)>;
2135 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2136 (VCVTPS2PDYrr VR128:$src)>;
2137 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2138 (VCVTPS2PDYrm addr:$src)>;
2141 let Predicates = [UseSSE2] in {
2142 // Match fextend for 128 conversions
2143 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2144 (CVTPS2PDrr VR128:$src)>;
2147 //===----------------------------------------------------------------------===//
2148 // SSE 1 & 2 - Compare Instructions
2149 //===----------------------------------------------------------------------===//
2151 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2152 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2153 Operand CC, SDNode OpNode, ValueType VT,
2154 PatFrag ld_frag, string asm, string asm_alt,
2156 def rr : SIi8<0xC2, MRMSrcReg,
2157 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2158 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2160 def rm : SIi8<0xC2, MRMSrcMem,
2161 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2162 [(set RC:$dst, (OpNode (VT RC:$src1),
2163 (ld_frag addr:$src2), imm:$cc))],
2166 // Accept explicit immediate argument form instead of comparison code.
2167 let neverHasSideEffects = 1 in {
2168 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2169 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2170 IIC_SSE_ALU_F32S_RR>;
2172 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2173 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2174 IIC_SSE_ALU_F32S_RM>;
2178 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2179 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2180 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2182 XS, VEX_4V, VEX_LIG;
2183 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2184 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2185 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2186 SSE_ALU_F32S>, // same latency as 32 bit compare
2187 XD, VEX_4V, VEX_LIG;
2189 let Constraints = "$src1 = $dst" in {
2190 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2191 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2192 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2194 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2195 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2196 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2197 SSE_ALU_F32S>, // same latency as 32 bit compare
2201 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2202 Intrinsic Int, string asm, OpndItins itins> {
2203 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2204 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2205 [(set VR128:$dst, (Int VR128:$src1,
2206 VR128:$src, imm:$cc))],
2208 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2209 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2210 [(set VR128:$dst, (Int VR128:$src1,
2211 (load addr:$src), imm:$cc))],
2215 // Aliases to match intrinsics which expect XMM operand(s).
2216 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2217 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2220 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2221 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2222 SSE_ALU_F32S>, // same latency as f32
2224 let Constraints = "$src1 = $dst" in {
2225 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2226 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2228 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2229 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2230 SSE_ALU_F32S>, // same latency as f32
2235 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2236 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2237 ValueType vt, X86MemOperand x86memop,
2238 PatFrag ld_frag, string OpcodeStr, Domain d> {
2239 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2240 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2241 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2242 IIC_SSE_COMIS_RR, d>;
2243 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2244 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2245 [(set EFLAGS, (OpNode (vt RC:$src1),
2246 (ld_frag addr:$src2)))],
2247 IIC_SSE_COMIS_RM, d>;
2250 let Defs = [EFLAGS] in {
2251 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2252 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2253 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2254 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2256 let Pattern = []<dag> in {
2257 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2258 "comiss", SSEPackedSingle>, TB, VEX,
2260 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2261 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2265 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2266 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2267 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2268 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2270 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2271 load, "comiss", SSEPackedSingle>, TB, VEX;
2272 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2273 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2274 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2275 "ucomiss", SSEPackedSingle>, TB;
2276 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2277 "ucomisd", SSEPackedDouble>, TB, OpSize;
2279 let Pattern = []<dag> in {
2280 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2281 "comiss", SSEPackedSingle>, TB;
2282 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2283 "comisd", SSEPackedDouble>, TB, OpSize;
2286 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2287 load, "ucomiss", SSEPackedSingle>, TB;
2288 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2289 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2291 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2292 "comiss", SSEPackedSingle>, TB;
2293 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2294 "comisd", SSEPackedDouble>, TB, OpSize;
2295 } // Defs = [EFLAGS]
2297 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2298 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2299 Operand CC, Intrinsic Int, string asm,
2300 string asm_alt, Domain d> {
2301 def rri : PIi8<0xC2, MRMSrcReg,
2302 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2303 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2304 IIC_SSE_CMPP_RR, d>;
2305 def rmi : PIi8<0xC2, MRMSrcMem,
2306 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2307 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2308 IIC_SSE_CMPP_RM, d>;
2310 // Accept explicit immediate argument form instead of comparison code.
2311 let neverHasSideEffects = 1 in {
2312 def rri_alt : PIi8<0xC2, MRMSrcReg,
2313 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2314 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2315 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2316 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2317 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2321 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2322 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2323 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2324 SSEPackedSingle>, TB, VEX_4V;
2325 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2326 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2327 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2328 SSEPackedDouble>, TB, OpSize, VEX_4V;
2329 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2330 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2331 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2332 SSEPackedSingle>, TB, VEX_4V;
2333 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2334 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2335 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2336 SSEPackedDouble>, TB, OpSize, VEX_4V;
2337 let Constraints = "$src1 = $dst" in {
2338 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2339 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2340 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2341 SSEPackedSingle>, TB;
2342 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2343 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2344 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2345 SSEPackedDouble>, TB, OpSize;
2348 let Predicates = [HasAVX] in {
2349 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2350 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2351 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2352 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2353 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2354 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2355 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2356 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2358 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2359 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2360 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2361 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2362 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2363 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2364 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2365 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2368 let Predicates = [UseSSE1] in {
2369 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2370 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2371 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2372 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2375 let Predicates = [UseSSE2] in {
2376 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2377 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2378 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2379 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2382 //===----------------------------------------------------------------------===//
2383 // SSE 1 & 2 - Shuffle Instructions
2384 //===----------------------------------------------------------------------===//
2386 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2387 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2388 ValueType vt, string asm, PatFrag mem_frag,
2389 Domain d, bit IsConvertibleToThreeAddress = 0> {
2390 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2391 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2392 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2393 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2394 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2395 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2396 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2397 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2398 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2401 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2402 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2403 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2404 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2405 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2406 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2407 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2408 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2409 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2410 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2411 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2412 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2414 let Constraints = "$src1 = $dst" in {
2415 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2416 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2417 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2419 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2420 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2421 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2425 let Predicates = [HasAVX] in {
2426 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2427 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2428 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2429 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2430 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2432 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2433 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2434 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2435 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2436 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2439 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2440 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2441 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2442 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2443 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2445 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2446 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2447 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2448 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2449 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2452 let Predicates = [UseSSE1] in {
2453 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2454 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2455 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2456 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2457 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2460 let Predicates = [UseSSE2] in {
2461 // Generic SHUFPD patterns
2462 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2463 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2464 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2465 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2466 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2469 //===----------------------------------------------------------------------===//
2470 // SSE 1 & 2 - Unpack Instructions
2471 //===----------------------------------------------------------------------===//
2473 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2474 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2475 PatFrag mem_frag, RegisterClass RC,
2476 X86MemOperand x86memop, string asm,
2478 def rr : PI<opc, MRMSrcReg,
2479 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2481 (vt (OpNode RC:$src1, RC:$src2)))],
2483 def rm : PI<opc, MRMSrcMem,
2484 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2486 (vt (OpNode RC:$src1,
2487 (mem_frag addr:$src2))))],
2491 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2492 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2493 SSEPackedSingle>, TB, VEX_4V;
2494 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2495 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2496 SSEPackedDouble>, TB, OpSize, VEX_4V;
2497 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2498 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2499 SSEPackedSingle>, TB, VEX_4V;
2500 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2501 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2502 SSEPackedDouble>, TB, OpSize, VEX_4V;
2504 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2505 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2506 SSEPackedSingle>, TB, VEX_4V;
2507 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2508 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2509 SSEPackedDouble>, TB, OpSize, VEX_4V;
2510 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2511 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2512 SSEPackedSingle>, TB, VEX_4V;
2513 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2514 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2515 SSEPackedDouble>, TB, OpSize, VEX_4V;
2517 let Constraints = "$src1 = $dst" in {
2518 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2519 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2520 SSEPackedSingle>, TB;
2521 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2522 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2523 SSEPackedDouble>, TB, OpSize;
2524 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2525 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2526 SSEPackedSingle>, TB;
2527 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2528 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2529 SSEPackedDouble>, TB, OpSize;
2530 } // Constraints = "$src1 = $dst"
2532 let Predicates = [HasAVX1Only] in {
2533 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2534 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2535 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2536 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2537 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2538 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2539 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2540 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2542 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2543 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2544 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2545 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2546 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2547 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2548 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2549 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2552 let Predicates = [HasAVX] in {
2553 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2554 // problem is during lowering, where it's not possible to recognize the load
2555 // fold cause it has two uses through a bitcast. One use disappears at isel
2556 // time and the fold opportunity reappears.
2557 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2558 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2561 let Predicates = [UseSSE2] in {
2562 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2563 // problem is during lowering, where it's not possible to recognize the load
2564 // fold cause it has two uses through a bitcast. One use disappears at isel
2565 // time and the fold opportunity reappears.
2566 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2567 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2570 //===----------------------------------------------------------------------===//
2571 // SSE 1 & 2 - Extract Floating-Point Sign mask
2572 //===----------------------------------------------------------------------===//
2574 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2575 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2577 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2578 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2579 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2580 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2581 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2582 IIC_SSE_MOVMSK, d>, REX_W;
2585 let Predicates = [HasAVX] in {
2586 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2587 "movmskps", SSEPackedSingle>, TB, VEX;
2588 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2589 "movmskpd", SSEPackedDouble>, TB,
2591 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2592 "movmskps", SSEPackedSingle>, TB, VEX;
2593 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2594 "movmskpd", SSEPackedDouble>, TB,
2597 def : Pat<(i32 (X86fgetsign FR32:$src)),
2598 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2599 def : Pat<(i64 (X86fgetsign FR32:$src)),
2600 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2601 def : Pat<(i32 (X86fgetsign FR64:$src)),
2602 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2603 def : Pat<(i64 (X86fgetsign FR64:$src)),
2604 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2607 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2608 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2609 SSEPackedSingle>, TB, VEX;
2610 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2611 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2612 SSEPackedDouble>, TB,
2614 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2615 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2616 SSEPackedSingle>, TB, VEX;
2617 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2618 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2619 SSEPackedDouble>, TB,
2623 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2624 SSEPackedSingle>, TB;
2625 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2626 SSEPackedDouble>, TB, OpSize;
2628 def : Pat<(i32 (X86fgetsign FR32:$src)),
2629 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2630 Requires<[UseSSE1]>;
2631 def : Pat<(i64 (X86fgetsign FR32:$src)),
2632 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2633 Requires<[UseSSE1]>;
2634 def : Pat<(i32 (X86fgetsign FR64:$src)),
2635 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2636 Requires<[UseSSE2]>;
2637 def : Pat<(i64 (X86fgetsign FR64:$src)),
2638 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2639 Requires<[UseSSE2]>;
2641 //===---------------------------------------------------------------------===//
2642 // SSE2 - Packed Integer Logical Instructions
2643 //===---------------------------------------------------------------------===//
2645 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2647 /// PDI_binop_rm - Simple SSE2 binary operator.
2648 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2649 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2650 X86MemOperand x86memop,
2652 bit IsCommutable = 0,
2654 let isCommutable = IsCommutable in
2655 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2656 (ins RC:$src1, RC:$src2),
2658 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2659 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2660 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2661 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2662 (ins RC:$src1, x86memop:$src2),
2664 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2665 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2666 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2667 (bitconvert (memop_frag addr:$src2)))))],
2670 } // ExeDomain = SSEPackedInt
2672 // These are ordered here for pattern ordering requirements with the fp versions
2674 let Predicates = [HasAVX] in {
2675 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2676 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2677 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2678 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2679 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2680 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2681 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2682 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2685 let Constraints = "$src1 = $dst" in {
2686 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2687 i128mem, SSE_BIT_ITINS_P, 1>;
2688 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2689 i128mem, SSE_BIT_ITINS_P, 1>;
2690 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2691 i128mem, SSE_BIT_ITINS_P, 1>;
2692 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2693 i128mem, SSE_BIT_ITINS_P, 0>;
2694 } // Constraints = "$src1 = $dst"
2696 let Predicates = [HasAVX2] in {
2697 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2698 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2699 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2700 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2701 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2702 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2703 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2704 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2707 //===----------------------------------------------------------------------===//
2708 // SSE 1 & 2 - Logical Instructions
2709 //===----------------------------------------------------------------------===//
2711 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2713 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2714 SDNode OpNode, OpndItins itins> {
2715 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2716 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2719 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2720 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2723 let Constraints = "$src1 = $dst" in {
2724 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2725 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2728 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2729 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2734 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2735 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2737 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2739 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2742 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2743 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2746 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2748 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2750 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2751 // are all promoted to v2i64, and the patterns are covered by the int
2752 // version. This is needed in SSE only, because v2i64 isn't supported on
2753 // SSE1, but only on SSE2.
2754 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2755 !strconcat(OpcodeStr, "ps"), f128mem, [],
2756 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2757 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2759 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2760 !strconcat(OpcodeStr, "pd"), f128mem,
2761 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2762 (bc_v2i64 (v2f64 VR128:$src2))))],
2763 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2764 (memopv2i64 addr:$src2)))], 0>,
2766 let Constraints = "$src1 = $dst" in {
2767 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2768 !strconcat(OpcodeStr, "ps"), f128mem,
2769 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2770 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2771 (memopv2i64 addr:$src2)))]>, TB;
2773 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2774 !strconcat(OpcodeStr, "pd"), f128mem,
2775 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2776 (bc_v2i64 (v2f64 VR128:$src2))))],
2777 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2778 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2782 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2784 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2786 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2787 !strconcat(OpcodeStr, "ps"), f256mem,
2788 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2789 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2790 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2792 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2793 !strconcat(OpcodeStr, "pd"), f256mem,
2794 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2795 (bc_v4i64 (v4f64 VR256:$src2))))],
2796 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2797 (memopv4i64 addr:$src2)))], 0>,
2801 // AVX 256-bit packed logical ops forms
2802 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2803 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2804 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2805 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2807 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2808 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2809 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2810 let isCommutable = 0 in
2811 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2813 //===----------------------------------------------------------------------===//
2814 // SSE 1 & 2 - Arithmetic Instructions
2815 //===----------------------------------------------------------------------===//
2817 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2820 /// In addition, we also have a special variant of the scalar form here to
2821 /// represent the associated intrinsic operation. This form is unlike the
2822 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2823 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2825 /// These three forms can each be reg+reg or reg+mem.
2828 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2830 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2833 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2834 OpNode, FR32, f32mem,
2835 itins.s, Is2Addr>, XS;
2836 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2837 OpNode, FR64, f64mem,
2838 itins.d, Is2Addr>, XD;
2841 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2844 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2845 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2847 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2848 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2852 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2855 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2856 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2858 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2859 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2863 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2866 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2867 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2868 itins.s, Is2Addr>, XS;
2869 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2870 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2871 itins.d, Is2Addr>, XD;
2874 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2877 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2878 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2879 SSEPackedSingle, itins.s, Is2Addr>,
2882 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2883 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2884 SSEPackedDouble, itins.d, Is2Addr>,
2888 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2890 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2891 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2892 SSEPackedSingle, itins.s, 0>, TB;
2894 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2895 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2896 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2899 // Binary Arithmetic instructions
2900 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2901 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2903 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2904 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2906 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2907 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2909 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2910 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2913 let isCommutable = 0 in {
2914 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2915 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2917 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2918 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2920 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2921 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2923 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2924 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2926 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2927 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2929 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2930 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2931 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2932 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2934 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2935 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2937 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2938 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2939 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2940 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2944 let Constraints = "$src1 = $dst" in {
2945 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2946 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2947 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2948 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2949 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2950 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2952 let isCommutable = 0 in {
2953 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2954 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2955 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2956 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2957 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2958 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2959 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2960 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2961 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2962 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2963 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2964 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2965 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2966 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2970 let isCodeGenOnly = 1 in {
2971 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
2973 defm VMAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P, 0>,
2974 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>, VEX_4V;
2975 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
2977 defm VMINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P, 0>,
2978 basic_sse12_fp_binop_p_y<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>, VEX_4V;
2979 let Constraints = "$src1 = $dst" in {
2980 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>,
2981 basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2982 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>,
2983 basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2988 /// In addition, we also have a special variant of the scalar form here to
2989 /// represent the associated intrinsic operation. This form is unlike the
2990 /// plain scalar form, in that it takes an entire vector (instead of a
2991 /// scalar) and leaves the top elements undefined.
2993 /// And, we have a special variant form for a full-vector intrinsic form.
2995 def SSE_SQRTP : OpndItins<
2996 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2999 def SSE_SQRTS : OpndItins<
3000 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
3003 def SSE_RCPP : OpndItins<
3004 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3007 def SSE_RCPS : OpndItins<
3008 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3011 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3012 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3013 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3014 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3015 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3016 [(set FR32:$dst, (OpNode FR32:$src))]>;
3017 // For scalar unary operations, fold a load into the operation
3018 // only in OptForSize mode. It eliminates an instruction, but it also
3019 // eliminates a whole-register clobber (the load), so it introduces a
3020 // partial register update condition.
3021 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3022 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3023 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3024 Requires<[UseSSE1, OptForSize]>;
3025 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3026 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3027 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3028 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3029 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3030 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3033 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3034 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3035 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3036 !strconcat(OpcodeStr,
3037 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3038 let mayLoad = 1 in {
3039 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3040 !strconcat(OpcodeStr,
3041 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3042 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3043 (ins VR128:$src1, ssmem:$src2),
3044 !strconcat(OpcodeStr,
3045 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3049 /// sse1_fp_unop_p - SSE1 unops in packed form.
3050 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3052 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3053 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3054 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3055 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3056 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3057 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3060 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3061 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3063 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3064 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3065 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3067 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3068 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3069 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3073 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3074 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3075 Intrinsic V4F32Int, OpndItins itins> {
3076 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3077 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3078 [(set VR128:$dst, (V4F32Int VR128:$src))],
3080 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3081 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3082 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3086 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3087 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3088 Intrinsic V4F32Int, OpndItins itins> {
3089 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3090 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3091 [(set VR256:$dst, (V4F32Int VR256:$src))],
3093 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3094 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3095 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3099 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3100 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3101 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3102 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3103 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3104 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3105 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3106 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3107 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3108 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3109 Requires<[UseSSE2, OptForSize]>;
3110 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3111 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3112 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3113 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3114 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3115 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3118 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3119 let hasSideEffects = 0 in
3120 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3121 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3122 !strconcat(OpcodeStr,
3123 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3124 let mayLoad = 1 in {
3125 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3126 !strconcat(OpcodeStr,
3127 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3128 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3129 (ins VR128:$src1, sdmem:$src2),
3130 !strconcat(OpcodeStr,
3131 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3135 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3136 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3137 SDNode OpNode, OpndItins itins> {
3138 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3139 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3140 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3141 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3142 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3143 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3146 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3147 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3149 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3150 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3151 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3153 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3154 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3155 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3159 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3160 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3161 Intrinsic V2F64Int, OpndItins itins> {
3162 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3163 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3164 [(set VR128:$dst, (V2F64Int VR128:$src))],
3166 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3167 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3168 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3172 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3173 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3174 Intrinsic V2F64Int, OpndItins itins> {
3175 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3176 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3177 [(set VR256:$dst, (V2F64Int VR256:$src))],
3179 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3180 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3181 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3185 let Predicates = [HasAVX] in {
3187 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3188 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3190 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3191 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3192 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3193 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3194 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3196 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3198 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3200 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3204 // Reciprocal approximations. Note that these typically require refinement
3205 // in order to obtain suitable precision.
3206 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3207 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3208 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3209 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3211 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3214 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3215 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3216 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3217 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3219 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3223 def : Pat<(f32 (fsqrt FR32:$src)),
3224 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3225 def : Pat<(f32 (fsqrt (load addr:$src))),
3226 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3227 Requires<[HasAVX, OptForSize]>;
3228 def : Pat<(f64 (fsqrt FR64:$src)),
3229 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3230 def : Pat<(f64 (fsqrt (load addr:$src))),
3231 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3232 Requires<[HasAVX, OptForSize]>;
3234 def : Pat<(f32 (X86frsqrt FR32:$src)),
3235 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3236 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3237 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3238 Requires<[HasAVX, OptForSize]>;
3240 def : Pat<(f32 (X86frcp FR32:$src)),
3241 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3242 def : Pat<(f32 (X86frcp (load addr:$src))),
3243 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3244 Requires<[HasAVX, OptForSize]>;
3246 let Predicates = [HasAVX] in {
3247 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3248 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3249 (COPY_TO_REGCLASS VR128:$src, FR32)),
3251 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3252 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3254 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3255 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3256 (COPY_TO_REGCLASS VR128:$src, FR64)),
3258 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3259 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3261 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3262 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3263 (COPY_TO_REGCLASS VR128:$src, FR32)),
3265 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3266 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3268 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3269 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3270 (COPY_TO_REGCLASS VR128:$src, FR32)),
3272 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3273 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3277 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3279 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3280 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3281 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3283 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3284 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3286 // Reciprocal approximations. Note that these typically require refinement
3287 // in order to obtain suitable precision.
3288 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3290 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3291 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3293 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3295 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3296 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3298 // There is no f64 version of the reciprocal approximation instructions.
3300 //===----------------------------------------------------------------------===//
3301 // SSE 1 & 2 - Non-temporal stores
3302 //===----------------------------------------------------------------------===//
3304 let AddedComplexity = 400 in { // Prefer non-temporal versions
3305 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3306 (ins f128mem:$dst, VR128:$src),
3307 "movntps\t{$src, $dst|$dst, $src}",
3308 [(alignednontemporalstore (v4f32 VR128:$src),
3310 IIC_SSE_MOVNT>, VEX;
3311 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3312 (ins f128mem:$dst, VR128:$src),
3313 "movntpd\t{$src, $dst|$dst, $src}",
3314 [(alignednontemporalstore (v2f64 VR128:$src),
3316 IIC_SSE_MOVNT>, VEX;
3318 let ExeDomain = SSEPackedInt in
3319 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3320 (ins f128mem:$dst, VR128:$src),
3321 "movntdq\t{$src, $dst|$dst, $src}",
3322 [(alignednontemporalstore (v2i64 VR128:$src),
3324 IIC_SSE_MOVNT>, VEX;
3326 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3327 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3329 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3330 (ins f256mem:$dst, VR256:$src),
3331 "movntps\t{$src, $dst|$dst, $src}",
3332 [(alignednontemporalstore (v8f32 VR256:$src),
3334 IIC_SSE_MOVNT>, VEX;
3335 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3336 (ins f256mem:$dst, VR256:$src),
3337 "movntpd\t{$src, $dst|$dst, $src}",
3338 [(alignednontemporalstore (v4f64 VR256:$src),
3340 IIC_SSE_MOVNT>, VEX;
3341 let ExeDomain = SSEPackedInt in
3342 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3343 (ins f256mem:$dst, VR256:$src),
3344 "movntdq\t{$src, $dst|$dst, $src}",
3345 [(alignednontemporalstore (v4i64 VR256:$src),
3347 IIC_SSE_MOVNT>, VEX;
3350 let AddedComplexity = 400 in { // Prefer non-temporal versions
3351 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3352 "movntps\t{$src, $dst|$dst, $src}",
3353 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3355 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3356 "movntpd\t{$src, $dst|$dst, $src}",
3357 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3360 let ExeDomain = SSEPackedInt in
3361 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3362 "movntdq\t{$src, $dst|$dst, $src}",
3363 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3366 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3367 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3369 // There is no AVX form for instructions below this point
3370 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3371 "movnti{l}\t{$src, $dst|$dst, $src}",
3372 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3374 TB, Requires<[HasSSE2]>;
3375 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3376 "movnti{q}\t{$src, $dst|$dst, $src}",
3377 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3379 TB, Requires<[HasSSE2]>;
3382 //===----------------------------------------------------------------------===//
3383 // SSE 1 & 2 - Prefetch and memory fence
3384 //===----------------------------------------------------------------------===//
3386 // Prefetch intrinsic.
3387 let Predicates = [HasSSE1] in {
3388 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3389 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3390 IIC_SSE_PREFETCH>, TB;
3391 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3392 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3393 IIC_SSE_PREFETCH>, TB;
3394 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3395 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3396 IIC_SSE_PREFETCH>, TB;
3397 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3398 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3399 IIC_SSE_PREFETCH>, TB;
3403 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3404 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3405 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3407 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3408 // was introduced with SSE2, it's backward compatible.
3409 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3411 // Load, store, and memory fence
3412 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3413 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3414 TB, Requires<[HasSSE1]>;
3415 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3416 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3417 TB, Requires<[HasSSE2]>;
3418 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3419 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3420 TB, Requires<[HasSSE2]>;
3422 def : Pat<(X86SFence), (SFENCE)>;
3423 def : Pat<(X86LFence), (LFENCE)>;
3424 def : Pat<(X86MFence), (MFENCE)>;
3426 //===----------------------------------------------------------------------===//
3427 // SSE 1 & 2 - Load/Store XCSR register
3428 //===----------------------------------------------------------------------===//
3430 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3431 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3432 IIC_SSE_LDMXCSR>, VEX;
3433 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3434 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3435 IIC_SSE_STMXCSR>, VEX;
3437 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3438 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3440 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3441 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3444 //===---------------------------------------------------------------------===//
3445 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3446 //===---------------------------------------------------------------------===//
3448 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3450 let neverHasSideEffects = 1 in {
3451 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3452 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3454 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3455 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3458 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3459 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3461 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3462 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3466 let isCodeGenOnly = 1 in {
3467 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3468 "movdqa\t{$src, $dst|$dst, $src}", [],
3471 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3472 "movdqa\t{$src, $dst|$dst, $src}", [],
3475 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3476 "movdqu\t{$src, $dst|$dst, $src}", [],
3479 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3480 "movdqu\t{$src, $dst|$dst, $src}", [],
3485 let canFoldAsLoad = 1, mayLoad = 1 in {
3486 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3487 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3489 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3490 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3492 let Predicates = [HasAVX] in {
3493 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3494 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3496 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3497 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3502 let mayStore = 1 in {
3503 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3504 (ins i128mem:$dst, VR128:$src),
3505 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3507 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3508 (ins i256mem:$dst, VR256:$src),
3509 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3511 let Predicates = [HasAVX] in {
3512 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3513 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3515 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3516 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3521 let neverHasSideEffects = 1 in
3522 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3523 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3525 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3526 "movdqu\t{$src, $dst|$dst, $src}",
3527 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3530 let isCodeGenOnly = 1 in {
3531 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3532 "movdqa\t{$src, $dst|$dst, $src}", [],
3535 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3536 "movdqu\t{$src, $dst|$dst, $src}",
3537 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3540 let canFoldAsLoad = 1, mayLoad = 1 in {
3541 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3542 "movdqa\t{$src, $dst|$dst, $src}",
3543 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3545 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3546 "movdqu\t{$src, $dst|$dst, $src}",
3547 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3549 XS, Requires<[UseSSE2]>;
3552 let mayStore = 1 in {
3553 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3554 "movdqa\t{$src, $dst|$dst, $src}",
3555 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3557 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3558 "movdqu\t{$src, $dst|$dst, $src}",
3559 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3561 XS, Requires<[UseSSE2]>;
3564 // Intrinsic forms of MOVDQU load and store
3565 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3566 "vmovdqu\t{$src, $dst|$dst, $src}",
3567 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3569 XS, VEX, Requires<[HasAVX]>;
3571 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3572 "movdqu\t{$src, $dst|$dst, $src}",
3573 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3575 XS, Requires<[UseSSE2]>;
3577 } // ExeDomain = SSEPackedInt
3579 let Predicates = [HasAVX] in {
3580 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3581 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3584 //===---------------------------------------------------------------------===//
3585 // SSE2 - Packed Integer Arithmetic Instructions
3586 //===---------------------------------------------------------------------===//
3588 def SSE_PMADD : OpndItins<
3589 IIC_SSE_PMADD, IIC_SSE_PMADD
3592 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3594 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3595 RegisterClass RC, PatFrag memop_frag,
3596 X86MemOperand x86memop,
3598 bit IsCommutable = 0,
3600 let isCommutable = IsCommutable in
3601 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3602 (ins RC:$src1, RC:$src2),
3604 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3605 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3606 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3607 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3608 (ins RC:$src1, x86memop:$src2),
3610 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3611 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3612 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3616 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3617 string OpcodeStr, SDNode OpNode,
3618 SDNode OpNode2, RegisterClass RC,
3619 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3620 ShiftOpndItins itins,
3622 // src2 is always 128-bit
3623 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3624 (ins RC:$src1, VR128:$src2),
3626 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3627 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3628 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3630 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3631 (ins RC:$src1, i128mem:$src2),
3633 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3634 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3635 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3636 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3637 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3638 (ins RC:$src1, i32i8imm:$src2),
3640 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3641 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3642 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3645 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3646 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3647 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3648 PatFrag memop_frag, X86MemOperand x86memop,
3650 bit IsCommutable = 0, bit Is2Addr = 1> {
3651 let isCommutable = IsCommutable in
3652 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3653 (ins RC:$src1, RC:$src2),
3655 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3656 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3657 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3658 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3659 (ins RC:$src1, x86memop:$src2),
3661 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3662 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3663 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3664 (bitconvert (memop_frag addr:$src2)))))]>;
3666 } // ExeDomain = SSEPackedInt
3668 // 128-bit Integer Arithmetic
3670 let Predicates = [HasAVX] in {
3671 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3672 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3674 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3675 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3676 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3677 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3678 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3679 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3680 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3681 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3682 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3683 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3684 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3685 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3686 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3687 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3688 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3689 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3690 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3691 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3695 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3696 VR128, memopv2i64, i128mem,
3697 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3698 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3699 VR128, memopv2i64, i128mem,
3700 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3701 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3702 VR128, memopv2i64, i128mem,
3703 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3704 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3705 VR128, memopv2i64, i128mem,
3706 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3707 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3708 VR128, memopv2i64, i128mem,
3709 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3710 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3711 VR128, memopv2i64, i128mem,
3712 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3713 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3714 VR128, memopv2i64, i128mem,
3715 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3716 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3717 VR128, memopv2i64, i128mem,
3718 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3719 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3720 VR128, memopv2i64, i128mem,
3721 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3722 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3723 VR128, memopv2i64, i128mem,
3724 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3725 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3726 VR128, memopv2i64, i128mem,
3727 SSE_PMADD, 1, 0>, VEX_4V;
3728 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3729 VR128, memopv2i64, i128mem,
3730 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3731 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3732 VR128, memopv2i64, i128mem,
3733 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3734 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3735 VR128, memopv2i64, i128mem,
3736 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3737 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3738 VR128, memopv2i64, i128mem,
3739 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3740 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3741 VR128, memopv2i64, i128mem,
3742 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3743 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3744 VR128, memopv2i64, i128mem,
3745 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3746 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3747 VR128, memopv2i64, i128mem,
3748 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3751 let Predicates = [HasAVX2] in {
3752 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3753 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3754 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3755 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3756 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3757 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3758 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3759 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3760 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3761 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3762 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3763 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3764 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3765 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3766 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3767 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3768 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3769 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3770 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3771 VR256, memopv4i64, i256mem,
3772 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3775 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3776 VR256, memopv4i64, i256mem,
3777 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3778 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3779 VR256, memopv4i64, i256mem,
3780 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3781 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3782 VR256, memopv4i64, i256mem,
3783 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3784 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3785 VR256, memopv4i64, i256mem,
3786 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3787 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3788 VR256, memopv4i64, i256mem,
3789 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3790 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3791 VR256, memopv4i64, i256mem,
3792 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3793 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3794 VR256, memopv4i64, i256mem,
3795 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3796 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3797 VR256, memopv4i64, i256mem,
3798 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3799 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3800 VR256, memopv4i64, i256mem,
3801 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3802 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3803 VR256, memopv4i64, i256mem,
3804 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3805 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3806 VR256, memopv4i64, i256mem,
3807 SSE_PMADD, 1, 0>, VEX_4V;
3808 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3809 VR256, memopv4i64, i256mem,
3810 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3811 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3812 VR256, memopv4i64, i256mem,
3813 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3814 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3815 VR256, memopv4i64, i256mem,
3816 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3817 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3818 VR256, memopv4i64, i256mem,
3819 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3820 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3821 VR256, memopv4i64, i256mem,
3822 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3823 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3824 VR256, memopv4i64, i256mem,
3825 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3826 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3827 VR256, memopv4i64, i256mem,
3828 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3831 let Constraints = "$src1 = $dst" in {
3832 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3833 i128mem, SSE_INTALU_ITINS_P, 1>;
3834 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3835 i128mem, SSE_INTALU_ITINS_P, 1>;
3836 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3837 i128mem, SSE_INTALU_ITINS_P, 1>;
3838 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3839 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3840 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3841 i128mem, SSE_INTMUL_ITINS_P, 1>;
3842 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3843 i128mem, SSE_INTALU_ITINS_P>;
3844 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3845 i128mem, SSE_INTALU_ITINS_P>;
3846 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3847 i128mem, SSE_INTALU_ITINS_P>;
3848 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3849 i128mem, SSE_INTALUQ_ITINS_P>;
3850 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3851 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3854 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3855 VR128, memopv2i64, i128mem,
3856 SSE_INTALU_ITINS_P>;
3857 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3858 VR128, memopv2i64, i128mem,
3859 SSE_INTALU_ITINS_P>;
3860 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3861 VR128, memopv2i64, i128mem,
3862 SSE_INTALU_ITINS_P>;
3863 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3864 VR128, memopv2i64, i128mem,
3865 SSE_INTALU_ITINS_P>;
3866 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3867 VR128, memopv2i64, i128mem,
3868 SSE_INTALU_ITINS_P, 1>;
3869 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3870 VR128, memopv2i64, i128mem,
3871 SSE_INTALU_ITINS_P, 1>;
3872 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3873 VR128, memopv2i64, i128mem,
3874 SSE_INTALU_ITINS_P, 1>;
3875 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3876 VR128, memopv2i64, i128mem,
3877 SSE_INTALU_ITINS_P, 1>;
3878 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3879 VR128, memopv2i64, i128mem,
3880 SSE_INTMUL_ITINS_P, 1>;
3881 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3882 VR128, memopv2i64, i128mem,
3883 SSE_INTMUL_ITINS_P, 1>;
3884 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3885 VR128, memopv2i64, i128mem,
3887 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3888 VR128, memopv2i64, i128mem,
3889 SSE_INTALU_ITINS_P, 1>;
3890 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3891 VR128, memopv2i64, i128mem,
3892 SSE_INTALU_ITINS_P, 1>;
3893 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3894 VR128, memopv2i64, i128mem,
3895 SSE_INTALU_ITINS_P, 1>;
3896 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3897 VR128, memopv2i64, i128mem,
3898 SSE_INTALU_ITINS_P, 1>;
3899 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3900 VR128, memopv2i64, i128mem,
3901 SSE_INTALU_ITINS_P, 1>;
3902 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3903 VR128, memopv2i64, i128mem,
3904 SSE_INTALU_ITINS_P, 1>;
3905 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3906 VR128, memopv2i64, i128mem,
3907 SSE_INTALU_ITINS_P, 1>;
3909 } // Constraints = "$src1 = $dst"
3911 //===---------------------------------------------------------------------===//
3912 // SSE2 - Packed Integer Logical Instructions
3913 //===---------------------------------------------------------------------===//
3915 let Predicates = [HasAVX] in {
3916 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3917 VR128, v8i16, v8i16, bc_v8i16,
3918 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3919 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3920 VR128, v4i32, v4i32, bc_v4i32,
3921 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3922 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3923 VR128, v2i64, v2i64, bc_v2i64,
3924 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3926 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3927 VR128, v8i16, v8i16, bc_v8i16,
3928 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3929 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3930 VR128, v4i32, v4i32, bc_v4i32,
3931 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3932 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3933 VR128, v2i64, v2i64, bc_v2i64,
3934 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3936 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3937 VR128, v8i16, v8i16, bc_v8i16,
3938 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3939 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3940 VR128, v4i32, v4i32, bc_v4i32,
3941 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3943 let ExeDomain = SSEPackedInt in {
3944 // 128-bit logical shifts.
3945 def VPSLLDQri : PDIi8<0x73, MRM7r,
3946 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3947 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3949 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3951 def VPSRLDQri : PDIi8<0x73, MRM3r,
3952 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3953 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3955 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3957 // PSRADQri doesn't exist in SSE[1-3].
3959 } // Predicates = [HasAVX]
3961 let Predicates = [HasAVX2] in {
3962 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3963 VR256, v16i16, v8i16, bc_v8i16,
3964 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3965 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3966 VR256, v8i32, v4i32, bc_v4i32,
3967 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3968 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3969 VR256, v4i64, v2i64, bc_v2i64,
3970 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3972 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3973 VR256, v16i16, v8i16, bc_v8i16,
3974 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3975 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3976 VR256, v8i32, v4i32, bc_v4i32,
3977 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3978 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3979 VR256, v4i64, v2i64, bc_v2i64,
3980 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3982 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3983 VR256, v16i16, v8i16, bc_v8i16,
3984 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3985 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3986 VR256, v8i32, v4i32, bc_v4i32,
3987 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3989 let ExeDomain = SSEPackedInt in {
3990 // 256-bit logical shifts.
3991 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3992 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3993 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3995 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3997 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3998 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3999 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4001 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4003 // PSRADQYri doesn't exist in SSE[1-3].
4005 } // Predicates = [HasAVX2]
4007 let Constraints = "$src1 = $dst" in {
4008 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4009 VR128, v8i16, v8i16, bc_v8i16,
4010 SSE_INTSHIFT_ITINS_P>;
4011 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4012 VR128, v4i32, v4i32, bc_v4i32,
4013 SSE_INTSHIFT_ITINS_P>;
4014 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4015 VR128, v2i64, v2i64, bc_v2i64,
4016 SSE_INTSHIFT_ITINS_P>;
4018 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4019 VR128, v8i16, v8i16, bc_v8i16,
4020 SSE_INTSHIFT_ITINS_P>;
4021 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4022 VR128, v4i32, v4i32, bc_v4i32,
4023 SSE_INTSHIFT_ITINS_P>;
4024 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4025 VR128, v2i64, v2i64, bc_v2i64,
4026 SSE_INTSHIFT_ITINS_P>;
4028 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4029 VR128, v8i16, v8i16, bc_v8i16,
4030 SSE_INTSHIFT_ITINS_P>;
4031 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4032 VR128, v4i32, v4i32, bc_v4i32,
4033 SSE_INTSHIFT_ITINS_P>;
4035 let ExeDomain = SSEPackedInt in {
4036 // 128-bit logical shifts.
4037 def PSLLDQri : PDIi8<0x73, MRM7r,
4038 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4039 "pslldq\t{$src2, $dst|$dst, $src2}",
4041 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4042 def PSRLDQri : PDIi8<0x73, MRM3r,
4043 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4044 "psrldq\t{$src2, $dst|$dst, $src2}",
4046 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4047 // PSRADQri doesn't exist in SSE[1-3].
4049 } // Constraints = "$src1 = $dst"
4051 let Predicates = [HasAVX] in {
4052 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4053 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4054 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4055 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4056 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4057 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4059 // Shift up / down and insert zero's.
4060 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4061 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4062 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4063 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4066 let Predicates = [HasAVX2] in {
4067 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4068 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4069 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4070 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4073 let Predicates = [UseSSE2] in {
4074 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4075 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4076 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4077 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4078 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4079 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4081 // Shift up / down and insert zero's.
4082 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4083 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4084 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4085 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4088 //===---------------------------------------------------------------------===//
4089 // SSE2 - Packed Integer Comparison Instructions
4090 //===---------------------------------------------------------------------===//
4092 let Predicates = [HasAVX] in {
4093 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4094 VR128, memopv2i64, i128mem,
4095 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4096 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4097 VR128, memopv2i64, i128mem,
4098 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4099 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4100 VR128, memopv2i64, i128mem,
4101 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4102 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4103 VR128, memopv2i64, i128mem,
4104 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4105 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4106 VR128, memopv2i64, i128mem,
4107 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4108 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4109 VR128, memopv2i64, i128mem,
4110 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4113 let Predicates = [HasAVX2] in {
4114 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4115 VR256, memopv4i64, i256mem,
4116 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4117 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4118 VR256, memopv4i64, i256mem,
4119 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4120 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4121 VR256, memopv4i64, i256mem,
4122 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4123 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4124 VR256, memopv4i64, i256mem,
4125 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4126 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4127 VR256, memopv4i64, i256mem,
4128 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4129 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4130 VR256, memopv4i64, i256mem,
4131 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4134 let Constraints = "$src1 = $dst" in {
4135 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4136 VR128, memopv2i64, i128mem,
4137 SSE_INTALU_ITINS_P, 1>;
4138 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4139 VR128, memopv2i64, i128mem,
4140 SSE_INTALU_ITINS_P, 1>;
4141 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4142 VR128, memopv2i64, i128mem,
4143 SSE_INTALU_ITINS_P, 1>;
4144 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4145 VR128, memopv2i64, i128mem,
4146 SSE_INTALU_ITINS_P>;
4147 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4148 VR128, memopv2i64, i128mem,
4149 SSE_INTALU_ITINS_P>;
4150 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4151 VR128, memopv2i64, i128mem,
4152 SSE_INTALU_ITINS_P>;
4153 } // Constraints = "$src1 = $dst"
4155 //===---------------------------------------------------------------------===//
4156 // SSE2 - Packed Integer Pack Instructions
4157 //===---------------------------------------------------------------------===//
4159 let Predicates = [HasAVX] in {
4160 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4161 VR128, memopv2i64, i128mem,
4162 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4163 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4164 VR128, memopv2i64, i128mem,
4165 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4166 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4167 VR128, memopv2i64, i128mem,
4168 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4171 let Predicates = [HasAVX2] in {
4172 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4173 VR256, memopv4i64, i256mem,
4174 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4175 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4176 VR256, memopv4i64, i256mem,
4177 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4178 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4179 VR256, memopv4i64, i256mem,
4180 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4183 let Constraints = "$src1 = $dst" in {
4184 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4185 VR128, memopv2i64, i128mem,
4186 SSE_INTALU_ITINS_P>;
4187 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4188 VR128, memopv2i64, i128mem,
4189 SSE_INTALU_ITINS_P>;
4190 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4191 VR128, memopv2i64, i128mem,
4192 SSE_INTALU_ITINS_P>;
4193 } // Constraints = "$src1 = $dst"
4195 //===---------------------------------------------------------------------===//
4196 // SSE2 - Packed Integer Shuffle Instructions
4197 //===---------------------------------------------------------------------===//
4199 let ExeDomain = SSEPackedInt in {
4200 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4201 def ri : Ii8<0x70, MRMSrcReg,
4202 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4203 !strconcat(OpcodeStr,
4204 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4205 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4207 def mi : Ii8<0x70, MRMSrcMem,
4208 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4209 !strconcat(OpcodeStr,
4210 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4212 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4217 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4218 def Yri : Ii8<0x70, MRMSrcReg,
4219 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4220 !strconcat(OpcodeStr,
4221 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4222 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4223 def Ymi : Ii8<0x70, MRMSrcMem,
4224 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4225 !strconcat(OpcodeStr,
4226 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4228 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4229 (i8 imm:$src2))))]>;
4231 } // ExeDomain = SSEPackedInt
4233 let Predicates = [HasAVX] in {
4234 let AddedComplexity = 5 in
4235 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4237 // SSE2 with ImmT == Imm8 and XS prefix.
4238 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4240 // SSE2 with ImmT == Imm8 and XD prefix.
4241 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4243 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4244 (VPSHUFDmi addr:$src1, imm:$imm)>;
4245 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4246 (VPSHUFDri VR128:$src1, imm:$imm)>;
4249 let Predicates = [HasAVX2] in {
4250 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4251 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4252 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4255 let Predicates = [UseSSE2] in {
4256 let AddedComplexity = 5 in
4257 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4259 // SSE2 with ImmT == Imm8 and XS prefix.
4260 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4262 // SSE2 with ImmT == Imm8 and XD prefix.
4263 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4265 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4266 (PSHUFDmi addr:$src1, imm:$imm)>;
4267 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4268 (PSHUFDri VR128:$src1, imm:$imm)>;
4271 //===---------------------------------------------------------------------===//
4272 // SSE2 - Packed Integer Unpack Instructions
4273 //===---------------------------------------------------------------------===//
4275 let ExeDomain = SSEPackedInt in {
4276 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4277 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4278 def rr : PDI<opc, MRMSrcReg,
4279 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4281 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4282 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4283 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4285 def rm : PDI<opc, MRMSrcMem,
4286 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4288 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4289 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4290 [(set VR128:$dst, (OpNode VR128:$src1,
4291 (bc_frag (memopv2i64
4296 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4297 SDNode OpNode, PatFrag bc_frag> {
4298 def Yrr : PDI<opc, MRMSrcReg,
4299 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4300 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4301 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4302 def Yrm : PDI<opc, MRMSrcMem,
4303 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4304 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4305 [(set VR256:$dst, (OpNode VR256:$src1,
4306 (bc_frag (memopv4i64 addr:$src2))))]>;
4309 let Predicates = [HasAVX] in {
4310 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4311 bc_v16i8, 0>, VEX_4V;
4312 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4313 bc_v8i16, 0>, VEX_4V;
4314 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4315 bc_v4i32, 0>, VEX_4V;
4316 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4317 bc_v2i64, 0>, VEX_4V;
4319 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4320 bc_v16i8, 0>, VEX_4V;
4321 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4322 bc_v8i16, 0>, VEX_4V;
4323 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4324 bc_v4i32, 0>, VEX_4V;
4325 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4326 bc_v2i64, 0>, VEX_4V;
4329 let Predicates = [HasAVX2] in {
4330 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4332 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4334 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4336 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4339 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4341 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4343 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4345 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4349 let Constraints = "$src1 = $dst" in {
4350 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4352 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4354 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4356 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4359 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4361 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4363 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4365 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4368 } // ExeDomain = SSEPackedInt
4370 //===---------------------------------------------------------------------===//
4371 // SSE2 - Packed Integer Extract and Insert
4372 //===---------------------------------------------------------------------===//
4374 let ExeDomain = SSEPackedInt in {
4375 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4376 def rri : Ii8<0xC4, MRMSrcReg,
4377 (outs VR128:$dst), (ins VR128:$src1,
4378 GR32:$src2, i32i8imm:$src3),
4380 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4381 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4383 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4384 def rmi : Ii8<0xC4, MRMSrcMem,
4385 (outs VR128:$dst), (ins VR128:$src1,
4386 i16mem:$src2, i32i8imm:$src3),
4388 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4389 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4391 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4392 imm:$src3))], IIC_SSE_PINSRW>;
4396 let Predicates = [HasAVX] in
4397 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4398 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4399 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4400 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4401 imm:$src2))]>, TB, OpSize, VEX;
4402 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4403 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4404 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4405 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4406 imm:$src2))], IIC_SSE_PEXTRW>;
4409 let Predicates = [HasAVX] in {
4410 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4411 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4412 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4413 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4414 []>, TB, OpSize, VEX_4V;
4417 let Constraints = "$src1 = $dst" in
4418 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4420 } // ExeDomain = SSEPackedInt
4422 //===---------------------------------------------------------------------===//
4423 // SSE2 - Packed Mask Creation
4424 //===---------------------------------------------------------------------===//
4426 let ExeDomain = SSEPackedInt in {
4428 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4429 "pmovmskb\t{$src, $dst|$dst, $src}",
4430 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4431 IIC_SSE_MOVMSK>, VEX;
4432 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4433 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4435 let Predicates = [HasAVX2] in {
4436 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4437 "pmovmskb\t{$src, $dst|$dst, $src}",
4438 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4439 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4440 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4443 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4444 "pmovmskb\t{$src, $dst|$dst, $src}",
4445 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4448 } // ExeDomain = SSEPackedInt
4450 //===---------------------------------------------------------------------===//
4451 // SSE2 - Conditional Store
4452 //===---------------------------------------------------------------------===//
4454 let ExeDomain = SSEPackedInt in {
4457 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4458 (ins VR128:$src, VR128:$mask),
4459 "maskmovdqu\t{$mask, $src|$src, $mask}",
4460 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4461 IIC_SSE_MASKMOV>, VEX;
4463 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4464 (ins VR128:$src, VR128:$mask),
4465 "maskmovdqu\t{$mask, $src|$src, $mask}",
4466 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4467 IIC_SSE_MASKMOV>, VEX;
4470 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4471 "maskmovdqu\t{$mask, $src|$src, $mask}",
4472 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4475 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4476 "maskmovdqu\t{$mask, $src|$src, $mask}",
4477 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4480 } // ExeDomain = SSEPackedInt
4482 //===---------------------------------------------------------------------===//
4483 // SSE2 - Move Doubleword
4484 //===---------------------------------------------------------------------===//
4486 //===---------------------------------------------------------------------===//
4487 // Move Int Doubleword to Packed Double Int
4489 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4490 "movd\t{$src, $dst|$dst, $src}",
4492 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4494 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4495 "movd\t{$src, $dst|$dst, $src}",
4497 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4500 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4501 "mov{d|q}\t{$src, $dst|$dst, $src}",
4503 (v2i64 (scalar_to_vector GR64:$src)))],
4504 IIC_SSE_MOVDQ>, VEX;
4505 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4506 "mov{d|q}\t{$src, $dst|$dst, $src}",
4507 [(set FR64:$dst, (bitconvert GR64:$src))],
4508 IIC_SSE_MOVDQ>, VEX;
4510 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4511 "movd\t{$src, $dst|$dst, $src}",
4513 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4514 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4515 "movd\t{$src, $dst|$dst, $src}",
4517 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4519 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4520 "mov{d|q}\t{$src, $dst|$dst, $src}",
4522 (v2i64 (scalar_to_vector GR64:$src)))],
4524 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4525 "mov{d|q}\t{$src, $dst|$dst, $src}",
4526 [(set FR64:$dst, (bitconvert GR64:$src))],
4529 //===---------------------------------------------------------------------===//
4530 // Move Int Doubleword to Single Scalar
4532 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4533 "movd\t{$src, $dst|$dst, $src}",
4534 [(set FR32:$dst, (bitconvert GR32:$src))],
4535 IIC_SSE_MOVDQ>, VEX;
4537 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4538 "movd\t{$src, $dst|$dst, $src}",
4539 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4542 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4543 "movd\t{$src, $dst|$dst, $src}",
4544 [(set FR32:$dst, (bitconvert GR32:$src))],
4547 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4548 "movd\t{$src, $dst|$dst, $src}",
4549 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4552 //===---------------------------------------------------------------------===//
4553 // Move Packed Doubleword Int to Packed Double Int
4555 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4556 "movd\t{$src, $dst|$dst, $src}",
4557 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4558 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4559 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4560 (ins i32mem:$dst, VR128:$src),
4561 "movd\t{$src, $dst|$dst, $src}",
4562 [(store (i32 (vector_extract (v4i32 VR128:$src),
4563 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4565 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4566 "movd\t{$src, $dst|$dst, $src}",
4567 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4568 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4569 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4570 "movd\t{$src, $dst|$dst, $src}",
4571 [(store (i32 (vector_extract (v4i32 VR128:$src),
4572 (iPTR 0))), addr:$dst)],
4575 //===---------------------------------------------------------------------===//
4576 // Move Packed Doubleword Int first element to Doubleword Int
4578 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4579 "vmov{d|q}\t{$src, $dst|$dst, $src}",
4580 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4583 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4585 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4586 "mov{d|q}\t{$src, $dst|$dst, $src}",
4587 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4591 //===---------------------------------------------------------------------===//
4592 // Bitcast FR64 <-> GR64
4594 let Predicates = [HasAVX] in
4595 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4596 "vmovq\t{$src, $dst|$dst, $src}",
4597 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4599 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4600 "mov{d|q}\t{$src, $dst|$dst, $src}",
4601 [(set GR64:$dst, (bitconvert FR64:$src))],
4602 IIC_SSE_MOVDQ>, VEX;
4603 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4604 "movq\t{$src, $dst|$dst, $src}",
4605 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4606 IIC_SSE_MOVDQ>, VEX;
4608 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4609 "movq\t{$src, $dst|$dst, $src}",
4610 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4612 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4613 "mov{d|q}\t{$src, $dst|$dst, $src}",
4614 [(set GR64:$dst, (bitconvert FR64:$src))],
4616 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4617 "movq\t{$src, $dst|$dst, $src}",
4618 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4621 //===---------------------------------------------------------------------===//
4622 // Move Scalar Single to Double Int
4624 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4625 "movd\t{$src, $dst|$dst, $src}",
4626 [(set GR32:$dst, (bitconvert FR32:$src))],
4627 IIC_SSE_MOVD_ToGP>, VEX;
4628 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4629 "movd\t{$src, $dst|$dst, $src}",
4630 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4631 IIC_SSE_MOVDQ>, VEX;
4632 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4633 "movd\t{$src, $dst|$dst, $src}",
4634 [(set GR32:$dst, (bitconvert FR32:$src))],
4636 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4637 "movd\t{$src, $dst|$dst, $src}",
4638 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4641 //===---------------------------------------------------------------------===//
4642 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4644 let AddedComplexity = 15 in {
4645 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4646 "movd\t{$src, $dst|$dst, $src}",
4647 [(set VR128:$dst, (v4i32 (X86vzmovl
4648 (v4i32 (scalar_to_vector GR32:$src)))))],
4649 IIC_SSE_MOVDQ>, VEX;
4650 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4651 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4652 [(set VR128:$dst, (v2i64 (X86vzmovl
4653 (v2i64 (scalar_to_vector GR64:$src)))))],
4657 let AddedComplexity = 15 in {
4658 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4659 "movd\t{$src, $dst|$dst, $src}",
4660 [(set VR128:$dst, (v4i32 (X86vzmovl
4661 (v4i32 (scalar_to_vector GR32:$src)))))],
4663 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4664 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4665 [(set VR128:$dst, (v2i64 (X86vzmovl
4666 (v2i64 (scalar_to_vector GR64:$src)))))],
4670 let AddedComplexity = 20 in {
4671 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4672 "movd\t{$src, $dst|$dst, $src}",
4674 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4675 (loadi32 addr:$src))))))],
4676 IIC_SSE_MOVDQ>, VEX;
4677 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4678 "movd\t{$src, $dst|$dst, $src}",
4680 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4681 (loadi32 addr:$src))))))],
4685 let Predicates = [HasAVX] in {
4686 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4687 let AddedComplexity = 20 in {
4688 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4689 (VMOVZDI2PDIrm addr:$src)>;
4690 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4691 (VMOVZDI2PDIrm addr:$src)>;
4693 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4694 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4695 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4696 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4697 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4698 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4699 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4702 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4703 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4704 (MOVZDI2PDIrm addr:$src)>;
4705 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4706 (MOVZDI2PDIrm addr:$src)>;
4709 // These are the correct encodings of the instructions so that we know how to
4710 // read correct assembly, even though we continue to emit the wrong ones for
4711 // compatibility with Darwin's buggy assembler.
4712 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4713 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4714 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4715 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4716 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4717 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4718 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4719 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4720 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4721 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4722 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4723 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4725 //===---------------------------------------------------------------------===//
4726 // SSE2 - Move Quadword
4727 //===---------------------------------------------------------------------===//
4729 //===---------------------------------------------------------------------===//
4730 // Move Quadword Int to Packed Quadword Int
4732 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4733 "vmovq\t{$src, $dst|$dst, $src}",
4735 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4736 VEX, Requires<[HasAVX]>;
4737 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4738 "movq\t{$src, $dst|$dst, $src}",
4740 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4742 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4744 //===---------------------------------------------------------------------===//
4745 // Move Packed Quadword Int to Quadword Int
4747 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4748 "movq\t{$src, $dst|$dst, $src}",
4749 [(store (i64 (vector_extract (v2i64 VR128:$src),
4750 (iPTR 0))), addr:$dst)],
4751 IIC_SSE_MOVDQ>, VEX;
4752 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4753 "movq\t{$src, $dst|$dst, $src}",
4754 [(store (i64 (vector_extract (v2i64 VR128:$src),
4755 (iPTR 0))), addr:$dst)],
4758 //===---------------------------------------------------------------------===//
4759 // Store / copy lower 64-bits of a XMM register.
4761 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4762 "movq\t{$src, $dst|$dst, $src}",
4763 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4764 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4765 "movq\t{$src, $dst|$dst, $src}",
4766 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4769 let AddedComplexity = 20 in
4770 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4771 "vmovq\t{$src, $dst|$dst, $src}",
4773 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4774 (loadi64 addr:$src))))))],
4776 XS, VEX, Requires<[HasAVX]>;
4778 let AddedComplexity = 20 in
4779 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4780 "movq\t{$src, $dst|$dst, $src}",
4782 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4783 (loadi64 addr:$src))))))],
4785 XS, Requires<[UseSSE2]>;
4787 let Predicates = [HasAVX], AddedComplexity = 20 in {
4788 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4789 (VMOVZQI2PQIrm addr:$src)>;
4790 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4791 (VMOVZQI2PQIrm addr:$src)>;
4792 def : Pat<(v2i64 (X86vzload addr:$src)),
4793 (VMOVZQI2PQIrm addr:$src)>;
4796 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4797 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4798 (MOVZQI2PQIrm addr:$src)>;
4799 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4800 (MOVZQI2PQIrm addr:$src)>;
4801 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4804 let Predicates = [HasAVX] in {
4805 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4806 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4807 def : Pat<(v4i64 (X86vzload addr:$src)),
4808 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4811 //===---------------------------------------------------------------------===//
4812 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4813 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4815 let AddedComplexity = 15 in
4816 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4817 "vmovq\t{$src, $dst|$dst, $src}",
4818 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4820 XS, VEX, Requires<[HasAVX]>;
4821 let AddedComplexity = 15 in
4822 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4823 "movq\t{$src, $dst|$dst, $src}",
4824 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4826 XS, Requires<[UseSSE2]>;
4828 let AddedComplexity = 20 in
4829 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4830 "vmovq\t{$src, $dst|$dst, $src}",
4831 [(set VR128:$dst, (v2i64 (X86vzmovl
4832 (loadv2i64 addr:$src))))],
4834 XS, VEX, Requires<[HasAVX]>;
4835 let AddedComplexity = 20 in {
4836 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4837 "movq\t{$src, $dst|$dst, $src}",
4838 [(set VR128:$dst, (v2i64 (X86vzmovl
4839 (loadv2i64 addr:$src))))],
4841 XS, Requires<[UseSSE2]>;
4844 let AddedComplexity = 20 in {
4845 let Predicates = [HasAVX] in {
4846 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4847 (VMOVZPQILo2PQIrm addr:$src)>;
4848 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4849 (VMOVZPQILo2PQIrr VR128:$src)>;
4851 let Predicates = [UseSSE2] in {
4852 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4853 (MOVZPQILo2PQIrm addr:$src)>;
4854 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4855 (MOVZPQILo2PQIrr VR128:$src)>;
4859 // Instructions to match in the assembler
4860 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4861 "movq\t{$src, $dst|$dst, $src}", [],
4862 IIC_SSE_MOVDQ>, VEX, VEX_W;
4863 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4864 "movq\t{$src, $dst|$dst, $src}", [],
4865 IIC_SSE_MOVDQ>, VEX, VEX_W;
4866 // Recognize "movd" with GR64 destination, but encode as a "movq"
4867 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4868 "movd\t{$src, $dst|$dst, $src}", [],
4869 IIC_SSE_MOVDQ>, VEX, VEX_W;
4871 // Instructions for the disassembler
4872 // xr = XMM register
4875 let Predicates = [HasAVX] in
4876 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4877 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4878 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4879 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4881 //===---------------------------------------------------------------------===//
4882 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4883 //===---------------------------------------------------------------------===//
4884 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4885 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4886 X86MemOperand x86memop> {
4887 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4888 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4889 [(set RC:$dst, (vt (OpNode RC:$src)))],
4891 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4892 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4893 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4897 let Predicates = [HasAVX] in {
4898 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4899 v4f32, VR128, memopv4f32, f128mem>, VEX;
4900 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4901 v4f32, VR128, memopv4f32, f128mem>, VEX;
4902 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4903 v8f32, VR256, memopv8f32, f256mem>, VEX;
4904 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4905 v8f32, VR256, memopv8f32, f256mem>, VEX;
4907 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4908 memopv4f32, f128mem>;
4909 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4910 memopv4f32, f128mem>;
4912 let Predicates = [HasAVX] in {
4913 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4914 (VMOVSHDUPrr VR128:$src)>;
4915 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4916 (VMOVSHDUPrm addr:$src)>;
4917 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4918 (VMOVSLDUPrr VR128:$src)>;
4919 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4920 (VMOVSLDUPrm addr:$src)>;
4921 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4922 (VMOVSHDUPYrr VR256:$src)>;
4923 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4924 (VMOVSHDUPYrm addr:$src)>;
4925 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4926 (VMOVSLDUPYrr VR256:$src)>;
4927 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4928 (VMOVSLDUPYrm addr:$src)>;
4931 let Predicates = [UseSSE3] in {
4932 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4933 (MOVSHDUPrr VR128:$src)>;
4934 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4935 (MOVSHDUPrm addr:$src)>;
4936 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4937 (MOVSLDUPrr VR128:$src)>;
4938 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4939 (MOVSLDUPrm addr:$src)>;
4942 //===---------------------------------------------------------------------===//
4943 // SSE3 - Replicate Double FP - MOVDDUP
4944 //===---------------------------------------------------------------------===//
4946 multiclass sse3_replicate_dfp<string OpcodeStr> {
4947 let neverHasSideEffects = 1 in
4948 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4949 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4950 [], IIC_SSE_MOV_LH>;
4951 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4952 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4955 (scalar_to_vector (loadf64 addr:$src)))))],
4959 // FIXME: Merge with above classe when there're patterns for the ymm version
4960 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4961 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4962 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4963 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4964 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4965 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4968 (scalar_to_vector (loadf64 addr:$src)))))]>;
4971 let Predicates = [HasAVX] in {
4972 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4973 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4976 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4978 let Predicates = [HasAVX] in {
4979 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4980 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4981 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4982 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4983 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4984 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4985 def : Pat<(X86Movddup (bc_v2f64
4986 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4987 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4990 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4991 (VMOVDDUPYrm addr:$src)>;
4992 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4993 (VMOVDDUPYrm addr:$src)>;
4994 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4995 (VMOVDDUPYrm addr:$src)>;
4996 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4997 (VMOVDDUPYrr VR256:$src)>;
5000 let Predicates = [UseSSE3] in {
5001 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5002 (MOVDDUPrm addr:$src)>;
5003 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5004 (MOVDDUPrm addr:$src)>;
5005 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5006 (MOVDDUPrm addr:$src)>;
5007 def : Pat<(X86Movddup (bc_v2f64
5008 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5009 (MOVDDUPrm addr:$src)>;
5012 //===---------------------------------------------------------------------===//
5013 // SSE3 - Move Unaligned Integer
5014 //===---------------------------------------------------------------------===//
5016 let Predicates = [HasAVX] in {
5017 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5018 "vlddqu\t{$src, $dst|$dst, $src}",
5019 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5020 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5021 "vlddqu\t{$src, $dst|$dst, $src}",
5022 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5024 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5025 "lddqu\t{$src, $dst|$dst, $src}",
5026 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5029 //===---------------------------------------------------------------------===//
5030 // SSE3 - Arithmetic
5031 //===---------------------------------------------------------------------===//
5033 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5034 X86MemOperand x86memop, OpndItins itins,
5036 def rr : I<0xD0, MRMSrcReg,
5037 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5039 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5040 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5041 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5042 def rm : I<0xD0, MRMSrcMem,
5043 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5045 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5046 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5047 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5050 let Predicates = [HasAVX] in {
5051 let ExeDomain = SSEPackedSingle in {
5052 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5053 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5054 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5055 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5057 let ExeDomain = SSEPackedDouble in {
5058 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5059 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5060 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5061 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5064 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5065 let ExeDomain = SSEPackedSingle in
5066 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5067 f128mem, SSE_ALU_F32P>, TB, XD;
5068 let ExeDomain = SSEPackedDouble in
5069 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5070 f128mem, SSE_ALU_F64P>, TB, OpSize;
5073 //===---------------------------------------------------------------------===//
5074 // SSE3 Instructions
5075 //===---------------------------------------------------------------------===//
5078 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5079 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5080 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5082 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5083 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5084 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5086 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5088 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5089 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5090 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5091 IIC_SSE_HADDSUB_RM>;
5093 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5094 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5095 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5097 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5098 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5099 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5101 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5103 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5105 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5106 IIC_SSE_HADDSUB_RM>;
5109 let Predicates = [HasAVX] in {
5110 let ExeDomain = SSEPackedSingle in {
5111 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5112 X86fhadd, 0>, VEX_4V;
5113 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5114 X86fhsub, 0>, VEX_4V;
5115 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5116 X86fhadd, 0>, VEX_4V;
5117 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5118 X86fhsub, 0>, VEX_4V;
5120 let ExeDomain = SSEPackedDouble in {
5121 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5122 X86fhadd, 0>, VEX_4V;
5123 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5124 X86fhsub, 0>, VEX_4V;
5125 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5126 X86fhadd, 0>, VEX_4V;
5127 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5128 X86fhsub, 0>, VEX_4V;
5132 let Constraints = "$src1 = $dst" in {
5133 let ExeDomain = SSEPackedSingle in {
5134 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5135 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5137 let ExeDomain = SSEPackedDouble in {
5138 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5139 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5143 //===---------------------------------------------------------------------===//
5144 // SSSE3 - Packed Absolute Instructions
5145 //===---------------------------------------------------------------------===//
5148 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5149 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5150 Intrinsic IntId128> {
5151 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5153 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5154 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5157 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5159 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5162 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5166 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5167 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5168 Intrinsic IntId256> {
5169 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5171 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5172 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5175 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5177 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5180 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5183 let Predicates = [HasAVX] in {
5184 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5185 int_x86_ssse3_pabs_b_128>, VEX;
5186 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5187 int_x86_ssse3_pabs_w_128>, VEX;
5188 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5189 int_x86_ssse3_pabs_d_128>, VEX;
5192 let Predicates = [HasAVX2] in {
5193 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5194 int_x86_avx2_pabs_b>, VEX;
5195 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5196 int_x86_avx2_pabs_w>, VEX;
5197 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5198 int_x86_avx2_pabs_d>, VEX;
5201 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5202 int_x86_ssse3_pabs_b_128>;
5203 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5204 int_x86_ssse3_pabs_w_128>;
5205 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5206 int_x86_ssse3_pabs_d_128>;
5208 //===---------------------------------------------------------------------===//
5209 // SSSE3 - Packed Binary Operator Instructions
5210 //===---------------------------------------------------------------------===//
5212 def SSE_PHADDSUBD : OpndItins<
5213 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5215 def SSE_PHADDSUBSW : OpndItins<
5216 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5218 def SSE_PHADDSUBW : OpndItins<
5219 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5221 def SSE_PSHUFB : OpndItins<
5222 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5224 def SSE_PSIGN : OpndItins<
5225 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5227 def SSE_PMULHRSW : OpndItins<
5228 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5231 /// SS3I_binop_rm - Simple SSSE3 bin op
5232 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5233 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5234 X86MemOperand x86memop, OpndItins itins,
5236 let isCommutable = 1 in
5237 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5238 (ins RC:$src1, RC:$src2),
5240 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5241 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5242 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5244 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5245 (ins RC:$src1, x86memop:$src2),
5247 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5250 (OpVT (OpNode RC:$src1,
5251 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5254 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5255 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5256 Intrinsic IntId128, OpndItins itins,
5258 let isCommutable = 1 in
5259 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5260 (ins VR128:$src1, VR128:$src2),
5262 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5263 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5264 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5266 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5267 (ins VR128:$src1, i128mem:$src2),
5269 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5270 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5272 (IntId128 VR128:$src1,
5273 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5276 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5277 Intrinsic IntId256> {
5278 let isCommutable = 1 in
5279 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5280 (ins VR256:$src1, VR256:$src2),
5281 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5282 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5284 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5285 (ins VR256:$src1, i256mem:$src2),
5286 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5288 (IntId256 VR256:$src1,
5289 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5292 let ImmT = NoImm, Predicates = [HasAVX] in {
5293 let isCommutable = 0 in {
5294 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5295 memopv2i64, i128mem,
5296 SSE_PHADDSUBW, 0>, VEX_4V;
5297 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5298 memopv2i64, i128mem,
5299 SSE_PHADDSUBD, 0>, VEX_4V;
5300 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5301 memopv2i64, i128mem,
5302 SSE_PHADDSUBW, 0>, VEX_4V;
5303 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5304 memopv2i64, i128mem,
5305 SSE_PHADDSUBD, 0>, VEX_4V;
5306 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5307 memopv2i64, i128mem,
5308 SSE_PSIGN, 0>, VEX_4V;
5309 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5310 memopv2i64, i128mem,
5311 SSE_PSIGN, 0>, VEX_4V;
5312 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5313 memopv2i64, i128mem,
5314 SSE_PSIGN, 0>, VEX_4V;
5315 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5316 memopv2i64, i128mem,
5317 SSE_PSHUFB, 0>, VEX_4V;
5318 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5319 int_x86_ssse3_phadd_sw_128,
5320 SSE_PHADDSUBSW, 0>, VEX_4V;
5321 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5322 int_x86_ssse3_phsub_sw_128,
5323 SSE_PHADDSUBSW, 0>, VEX_4V;
5324 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5325 int_x86_ssse3_pmadd_ub_sw_128,
5326 SSE_PMADD, 0>, VEX_4V;
5328 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5329 int_x86_ssse3_pmul_hr_sw_128,
5330 SSE_PMULHRSW, 0>, VEX_4V;
5333 let ImmT = NoImm, Predicates = [HasAVX2] in {
5334 let isCommutable = 0 in {
5335 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5336 memopv4i64, i256mem,
5337 SSE_PHADDSUBW, 0>, VEX_4V;
5338 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5339 memopv4i64, i256mem,
5340 SSE_PHADDSUBW, 0>, VEX_4V;
5341 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5342 memopv4i64, i256mem,
5343 SSE_PHADDSUBW, 0>, VEX_4V;
5344 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5345 memopv4i64, i256mem,
5346 SSE_PHADDSUBW, 0>, VEX_4V;
5347 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5348 memopv4i64, i256mem,
5349 SSE_PHADDSUBW, 0>, VEX_4V;
5350 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5351 memopv4i64, i256mem,
5352 SSE_PHADDSUBW, 0>, VEX_4V;
5353 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5354 memopv4i64, i256mem,
5355 SSE_PHADDSUBW, 0>, VEX_4V;
5356 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5357 memopv4i64, i256mem,
5358 SSE_PHADDSUBW, 0>, VEX_4V;
5359 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5360 int_x86_avx2_phadd_sw>, VEX_4V;
5361 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5362 int_x86_avx2_phsub_sw>, VEX_4V;
5363 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5364 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5366 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5367 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5370 // None of these have i8 immediate fields.
5371 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5372 let isCommutable = 0 in {
5373 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5374 memopv2i64, i128mem, SSE_PHADDSUBW>;
5375 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5376 memopv2i64, i128mem, SSE_PHADDSUBD>;
5377 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5378 memopv2i64, i128mem, SSE_PHADDSUBW>;
5379 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5380 memopv2i64, i128mem, SSE_PHADDSUBD>;
5381 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5382 memopv2i64, i128mem, SSE_PSIGN>;
5383 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5384 memopv2i64, i128mem, SSE_PSIGN>;
5385 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5386 memopv2i64, i128mem, SSE_PSIGN>;
5387 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5388 memopv2i64, i128mem, SSE_PSHUFB>;
5389 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5390 int_x86_ssse3_phadd_sw_128,
5392 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5393 int_x86_ssse3_phsub_sw_128,
5395 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5396 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5398 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5399 int_x86_ssse3_pmul_hr_sw_128,
5403 //===---------------------------------------------------------------------===//
5404 // SSSE3 - Packed Align Instruction Patterns
5405 //===---------------------------------------------------------------------===//
5407 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5408 let neverHasSideEffects = 1 in {
5409 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5410 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5412 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5414 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5415 [], IIC_SSE_PALIGNR>, OpSize;
5417 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5418 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5420 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5422 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5423 [], IIC_SSE_PALIGNR>, OpSize;
5427 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5428 let neverHasSideEffects = 1 in {
5429 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5430 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5432 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5435 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5436 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5438 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5443 let Predicates = [HasAVX] in
5444 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5445 let Predicates = [HasAVX2] in
5446 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5447 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5448 defm PALIGN : ssse3_palign<"palignr">;
5450 let Predicates = [HasAVX2] in {
5451 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5452 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5453 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5454 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5455 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5456 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5457 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5458 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5461 let Predicates = [HasAVX] in {
5462 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5463 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5464 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5465 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5466 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5467 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5468 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5469 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5472 let Predicates = [UseSSSE3] in {
5473 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5474 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5475 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5476 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5477 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5478 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5479 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5480 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5483 //===---------------------------------------------------------------------===//
5484 // SSSE3 - Thread synchronization
5485 //===---------------------------------------------------------------------===//
5487 let usesCustomInserter = 1 in {
5488 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5489 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5490 Requires<[HasSSE3]>;
5493 let Uses = [EAX, ECX, EDX] in
5494 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5495 TB, Requires<[HasSSE3]>;
5496 let Uses = [ECX, EAX] in
5497 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5498 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5499 TB, Requires<[HasSSE3]>;
5501 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5502 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5504 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5505 Requires<[In32BitMode]>;
5506 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5507 Requires<[In64BitMode]>;
5509 //===----------------------------------------------------------------------===//
5510 // SSE4.1 - Packed Move with Sign/Zero Extend
5511 //===----------------------------------------------------------------------===//
5513 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5514 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5515 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5516 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5518 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5519 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5521 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5525 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5527 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5528 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5529 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5531 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5532 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5533 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5536 let Predicates = [HasAVX] in {
5537 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5539 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5541 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5543 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5545 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5547 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5551 let Predicates = [HasAVX2] in {
5552 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5553 int_x86_avx2_pmovsxbw>, VEX;
5554 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5555 int_x86_avx2_pmovsxwd>, VEX;
5556 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5557 int_x86_avx2_pmovsxdq>, VEX;
5558 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5559 int_x86_avx2_pmovzxbw>, VEX;
5560 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5561 int_x86_avx2_pmovzxwd>, VEX;
5562 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5563 int_x86_avx2_pmovzxdq>, VEX;
5566 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5567 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5568 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5569 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5570 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5571 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5573 let Predicates = [HasAVX] in {
5574 // Common patterns involving scalar load.
5575 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5576 (VPMOVSXBWrm addr:$src)>;
5577 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5578 (VPMOVSXBWrm addr:$src)>;
5580 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5581 (VPMOVSXWDrm addr:$src)>;
5582 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5583 (VPMOVSXWDrm addr:$src)>;
5585 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5586 (VPMOVSXDQrm addr:$src)>;
5587 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5588 (VPMOVSXDQrm addr:$src)>;
5590 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5591 (VPMOVZXBWrm addr:$src)>;
5592 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5593 (VPMOVZXBWrm addr:$src)>;
5595 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5596 (VPMOVZXWDrm addr:$src)>;
5597 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5598 (VPMOVZXWDrm addr:$src)>;
5600 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5601 (VPMOVZXDQrm addr:$src)>;
5602 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5603 (VPMOVZXDQrm addr:$src)>;
5606 let Predicates = [UseSSE41] in {
5607 // Common patterns involving scalar load.
5608 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5609 (PMOVSXBWrm addr:$src)>;
5610 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5611 (PMOVSXBWrm addr:$src)>;
5613 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5614 (PMOVSXWDrm addr:$src)>;
5615 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5616 (PMOVSXWDrm addr:$src)>;
5618 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5619 (PMOVSXDQrm addr:$src)>;
5620 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5621 (PMOVSXDQrm addr:$src)>;
5623 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5624 (PMOVZXBWrm addr:$src)>;
5625 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5626 (PMOVZXBWrm addr:$src)>;
5628 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5629 (PMOVZXWDrm addr:$src)>;
5630 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5631 (PMOVZXWDrm addr:$src)>;
5633 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5634 (PMOVZXDQrm addr:$src)>;
5635 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5636 (PMOVZXDQrm addr:$src)>;
5639 let Predicates = [HasAVX2] in {
5640 let AddedComplexity = 15 in {
5641 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5642 (VPMOVZXDQYrr VR128:$src)>;
5643 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5644 (VPMOVZXWDYrr VR128:$src)>;
5647 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5648 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5651 let Predicates = [HasAVX] in {
5652 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5653 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5656 let Predicates = [UseSSE41] in {
5657 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5658 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5662 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5663 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5664 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5665 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5667 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5668 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5670 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5674 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5676 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5677 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5678 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5680 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5681 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5683 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5687 let Predicates = [HasAVX] in {
5688 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5690 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5692 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5694 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5698 let Predicates = [HasAVX2] in {
5699 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5700 int_x86_avx2_pmovsxbd>, VEX;
5701 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5702 int_x86_avx2_pmovsxwq>, VEX;
5703 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5704 int_x86_avx2_pmovzxbd>, VEX;
5705 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5706 int_x86_avx2_pmovzxwq>, VEX;
5709 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5710 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5711 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5712 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5714 let Predicates = [HasAVX] in {
5715 // Common patterns involving scalar load
5716 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5717 (VPMOVSXBDrm addr:$src)>;
5718 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5719 (VPMOVSXWQrm addr:$src)>;
5721 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5722 (VPMOVZXBDrm addr:$src)>;
5723 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5724 (VPMOVZXWQrm addr:$src)>;
5727 let Predicates = [UseSSE41] in {
5728 // Common patterns involving scalar load
5729 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5730 (PMOVSXBDrm addr:$src)>;
5731 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5732 (PMOVSXWQrm addr:$src)>;
5734 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5735 (PMOVZXBDrm addr:$src)>;
5736 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5737 (PMOVZXWQrm addr:$src)>;
5740 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5741 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5742 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5743 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5745 // Expecting a i16 load any extended to i32 value.
5746 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5747 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5748 [(set VR128:$dst, (IntId (bitconvert
5749 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5753 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5755 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5756 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5757 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5759 // Expecting a i16 load any extended to i32 value.
5760 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5761 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5762 [(set VR256:$dst, (IntId (bitconvert
5763 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5767 let Predicates = [HasAVX] in {
5768 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5770 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5773 let Predicates = [HasAVX2] in {
5774 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5775 int_x86_avx2_pmovsxbq>, VEX;
5776 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5777 int_x86_avx2_pmovzxbq>, VEX;
5779 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5780 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5782 let Predicates = [HasAVX] in {
5783 // Common patterns involving scalar load
5784 def : Pat<(int_x86_sse41_pmovsxbq
5785 (bitconvert (v4i32 (X86vzmovl
5786 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5787 (VPMOVSXBQrm addr:$src)>;
5789 def : Pat<(int_x86_sse41_pmovzxbq
5790 (bitconvert (v4i32 (X86vzmovl
5791 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5792 (VPMOVZXBQrm addr:$src)>;
5795 let Predicates = [UseSSE41] in {
5796 // Common patterns involving scalar load
5797 def : Pat<(int_x86_sse41_pmovsxbq
5798 (bitconvert (v4i32 (X86vzmovl
5799 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5800 (PMOVSXBQrm addr:$src)>;
5802 def : Pat<(int_x86_sse41_pmovzxbq
5803 (bitconvert (v4i32 (X86vzmovl
5804 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5805 (PMOVZXBQrm addr:$src)>;
5808 //===----------------------------------------------------------------------===//
5809 // SSE4.1 - Extract Instructions
5810 //===----------------------------------------------------------------------===//
5812 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5813 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5814 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5815 (ins VR128:$src1, i32i8imm:$src2),
5816 !strconcat(OpcodeStr,
5817 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5818 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5820 let neverHasSideEffects = 1, mayStore = 1 in
5821 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5822 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5823 !strconcat(OpcodeStr,
5824 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5827 // There's an AssertZext in the way of writing the store pattern
5828 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5831 let Predicates = [HasAVX] in {
5832 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5833 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5834 (ins VR128:$src1, i32i8imm:$src2),
5835 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5838 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5841 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5842 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5843 let neverHasSideEffects = 1, mayStore = 1 in
5844 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5845 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5846 !strconcat(OpcodeStr,
5847 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5850 // There's an AssertZext in the way of writing the store pattern
5851 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5854 let Predicates = [HasAVX] in
5855 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5857 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5860 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5861 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5862 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5863 (ins VR128:$src1, i32i8imm:$src2),
5864 !strconcat(OpcodeStr,
5865 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5867 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5868 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5869 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5870 !strconcat(OpcodeStr,
5871 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5872 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5873 addr:$dst)]>, OpSize;
5876 let Predicates = [HasAVX] in
5877 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5879 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5881 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5882 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5883 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5884 (ins VR128:$src1, i32i8imm:$src2),
5885 !strconcat(OpcodeStr,
5886 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5888 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5889 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5890 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5891 !strconcat(OpcodeStr,
5892 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5893 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5894 addr:$dst)]>, OpSize, REX_W;
5897 let Predicates = [HasAVX] in
5898 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5900 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5902 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5904 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5905 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5906 (ins VR128:$src1, i32i8imm:$src2),
5907 !strconcat(OpcodeStr,
5908 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5910 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5912 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5913 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5914 !strconcat(OpcodeStr,
5915 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5916 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5917 addr:$dst)]>, OpSize;
5920 let ExeDomain = SSEPackedSingle in {
5921 let Predicates = [HasAVX] in {
5922 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5923 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5924 (ins VR128:$src1, i32i8imm:$src2),
5925 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5928 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5931 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5932 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5935 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5937 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5940 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5941 Requires<[UseSSE41]>;
5943 //===----------------------------------------------------------------------===//
5944 // SSE4.1 - Insert Instructions
5945 //===----------------------------------------------------------------------===//
5947 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5948 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5949 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5951 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5953 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5955 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5956 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5957 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5959 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5961 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5963 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5964 imm:$src3))]>, OpSize;
5967 let Predicates = [HasAVX] in
5968 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5969 let Constraints = "$src1 = $dst" in
5970 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5972 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5973 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5974 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5976 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5978 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5980 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5982 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5983 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5985 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5987 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5989 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5990 imm:$src3)))]>, OpSize;
5993 let Predicates = [HasAVX] in
5994 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5995 let Constraints = "$src1 = $dst" in
5996 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5998 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5999 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6000 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6002 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6004 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6006 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6008 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6009 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6011 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6013 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6015 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6016 imm:$src3)))]>, OpSize;
6019 let Predicates = [HasAVX] in
6020 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6021 let Constraints = "$src1 = $dst" in
6022 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6024 // insertps has a few different modes, there's the first two here below which
6025 // are optimized inserts that won't zero arbitrary elements in the destination
6026 // vector. The next one matches the intrinsic and could zero arbitrary elements
6027 // in the target vector.
6028 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6029 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6030 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6032 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6034 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6036 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6038 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6039 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6041 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6043 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6045 (X86insrtps VR128:$src1,
6046 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6047 imm:$src3))]>, OpSize;
6050 let ExeDomain = SSEPackedSingle in {
6051 let Predicates = [HasAVX] in
6052 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6053 let Constraints = "$src1 = $dst" in
6054 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6057 //===----------------------------------------------------------------------===//
6058 // SSE4.1 - Round Instructions
6059 //===----------------------------------------------------------------------===//
6061 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6062 X86MemOperand x86memop, RegisterClass RC,
6063 PatFrag mem_frag32, PatFrag mem_frag64,
6064 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6065 let ExeDomain = SSEPackedSingle in {
6066 // Intrinsic operation, reg.
6067 // Vector intrinsic operation, reg
6068 def PSr : SS4AIi8<opcps, MRMSrcReg,
6069 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6070 !strconcat(OpcodeStr,
6071 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6072 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6075 // Vector intrinsic operation, mem
6076 def PSm : SS4AIi8<opcps, MRMSrcMem,
6077 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6078 !strconcat(OpcodeStr,
6079 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6081 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6083 } // ExeDomain = SSEPackedSingle
6085 let ExeDomain = SSEPackedDouble in {
6086 // Vector intrinsic operation, reg
6087 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6088 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6089 !strconcat(OpcodeStr,
6090 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6091 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6094 // Vector intrinsic operation, mem
6095 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6096 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6097 !strconcat(OpcodeStr,
6098 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6100 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6102 } // ExeDomain = SSEPackedDouble
6105 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6108 Intrinsic F64Int, bit Is2Addr = 1> {
6109 let ExeDomain = GenericDomain in {
6111 def SSr : SS4AIi8<opcss, MRMSrcReg,
6112 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6114 !strconcat(OpcodeStr,
6115 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6116 !strconcat(OpcodeStr,
6117 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6120 // Intrinsic operation, reg.
6121 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6122 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6124 !strconcat(OpcodeStr,
6125 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6126 !strconcat(OpcodeStr,
6127 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6128 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6131 // Intrinsic operation, mem.
6132 def SSm : SS4AIi8<opcss, MRMSrcMem,
6133 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6135 !strconcat(OpcodeStr,
6136 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6137 !strconcat(OpcodeStr,
6138 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6140 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6144 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6145 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6147 !strconcat(OpcodeStr,
6148 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6149 !strconcat(OpcodeStr,
6150 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6153 // Intrinsic operation, reg.
6154 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6155 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6157 !strconcat(OpcodeStr,
6158 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6159 !strconcat(OpcodeStr,
6160 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6161 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6164 // Intrinsic operation, mem.
6165 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6166 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6168 !strconcat(OpcodeStr,
6169 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6170 !strconcat(OpcodeStr,
6171 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6173 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6175 } // ExeDomain = GenericDomain
6178 // FP round - roundss, roundps, roundsd, roundpd
6179 let Predicates = [HasAVX] in {
6181 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6182 memopv4f32, memopv2f64,
6183 int_x86_sse41_round_ps,
6184 int_x86_sse41_round_pd>, VEX;
6185 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6186 memopv8f32, memopv4f64,
6187 int_x86_avx_round_ps_256,
6188 int_x86_avx_round_pd_256>, VEX;
6189 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6190 int_x86_sse41_round_ss,
6191 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6193 def : Pat<(ffloor FR32:$src),
6194 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6195 def : Pat<(f64 (ffloor FR64:$src)),
6196 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6197 def : Pat<(f32 (fnearbyint FR32:$src)),
6198 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6199 def : Pat<(f64 (fnearbyint FR64:$src)),
6200 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6201 def : Pat<(f32 (fceil FR32:$src)),
6202 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6203 def : Pat<(f64 (fceil FR64:$src)),
6204 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6205 def : Pat<(f32 (frint FR32:$src)),
6206 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6207 def : Pat<(f64 (frint FR64:$src)),
6208 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6209 def : Pat<(f32 (ftrunc FR32:$src)),
6210 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6211 def : Pat<(f64 (ftrunc FR64:$src)),
6212 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6215 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6216 memopv4f32, memopv2f64,
6217 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6218 let Constraints = "$src1 = $dst" in
6219 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6220 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6222 def : Pat<(ffloor FR32:$src),
6223 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6224 def : Pat<(f64 (ffloor FR64:$src)),
6225 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6226 def : Pat<(f32 (fnearbyint FR32:$src)),
6227 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6228 def : Pat<(f64 (fnearbyint FR64:$src)),
6229 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6230 def : Pat<(f32 (fceil FR32:$src)),
6231 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6232 def : Pat<(f64 (fceil FR64:$src)),
6233 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6234 def : Pat<(f32 (frint FR32:$src)),
6235 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6236 def : Pat<(f64 (frint FR64:$src)),
6237 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6238 def : Pat<(f32 (ftrunc FR32:$src)),
6239 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6240 def : Pat<(f64 (ftrunc FR64:$src)),
6241 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6243 //===----------------------------------------------------------------------===//
6244 // SSE4.1 - Packed Bit Test
6245 //===----------------------------------------------------------------------===//
6247 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6248 // the intel intrinsic that corresponds to this.
6249 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6250 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6251 "vptest\t{$src2, $src1|$src1, $src2}",
6252 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6254 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6255 "vptest\t{$src2, $src1|$src1, $src2}",
6256 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6259 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6260 "vptest\t{$src2, $src1|$src1, $src2}",
6261 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6263 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6264 "vptest\t{$src2, $src1|$src1, $src2}",
6265 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6269 let Defs = [EFLAGS] in {
6270 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6271 "ptest\t{$src2, $src1|$src1, $src2}",
6272 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6274 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6275 "ptest\t{$src2, $src1|$src1, $src2}",
6276 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6280 // The bit test instructions below are AVX only
6281 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6282 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6283 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6284 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6285 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6286 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6287 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6288 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6292 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6293 let ExeDomain = SSEPackedSingle in {
6294 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6295 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6297 let ExeDomain = SSEPackedDouble in {
6298 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6299 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6303 //===----------------------------------------------------------------------===//
6304 // SSE4.1 - Misc Instructions
6305 //===----------------------------------------------------------------------===//
6307 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6308 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6309 "popcnt{w}\t{$src, $dst|$dst, $src}",
6310 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6312 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6313 "popcnt{w}\t{$src, $dst|$dst, $src}",
6314 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6315 (implicit EFLAGS)]>, OpSize, XS;
6317 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6318 "popcnt{l}\t{$src, $dst|$dst, $src}",
6319 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6321 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6322 "popcnt{l}\t{$src, $dst|$dst, $src}",
6323 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6324 (implicit EFLAGS)]>, XS;
6326 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6327 "popcnt{q}\t{$src, $dst|$dst, $src}",
6328 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6330 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6331 "popcnt{q}\t{$src, $dst|$dst, $src}",
6332 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6333 (implicit EFLAGS)]>, XS;
6338 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6339 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6340 Intrinsic IntId128> {
6341 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6343 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6344 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6345 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6347 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6350 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6353 let Predicates = [HasAVX] in
6354 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6355 int_x86_sse41_phminposuw>, VEX;
6356 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6357 int_x86_sse41_phminposuw>;
6359 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6360 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6361 Intrinsic IntId128, bit Is2Addr = 1> {
6362 let isCommutable = 1 in
6363 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6364 (ins VR128:$src1, VR128:$src2),
6366 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6367 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6368 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6369 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6370 (ins VR128:$src1, i128mem:$src2),
6372 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6373 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6375 (IntId128 VR128:$src1,
6376 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6379 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6380 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6381 Intrinsic IntId256> {
6382 let isCommutable = 1 in
6383 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6384 (ins VR256:$src1, VR256:$src2),
6385 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6386 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6387 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6388 (ins VR256:$src1, i256mem:$src2),
6389 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6391 (IntId256 VR256:$src1,
6392 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6395 let Predicates = [HasAVX] in {
6396 let isCommutable = 0 in
6397 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6399 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6401 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6403 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6405 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6407 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6409 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6411 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6413 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6415 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6419 let Predicates = [HasAVX2] in {
6420 let isCommutable = 0 in
6421 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6422 int_x86_avx2_packusdw>, VEX_4V;
6423 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6424 int_x86_avx2_pmins_b>, VEX_4V;
6425 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6426 int_x86_avx2_pmins_d>, VEX_4V;
6427 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6428 int_x86_avx2_pminu_d>, VEX_4V;
6429 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6430 int_x86_avx2_pminu_w>, VEX_4V;
6431 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6432 int_x86_avx2_pmaxs_b>, VEX_4V;
6433 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6434 int_x86_avx2_pmaxs_d>, VEX_4V;
6435 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6436 int_x86_avx2_pmaxu_d>, VEX_4V;
6437 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6438 int_x86_avx2_pmaxu_w>, VEX_4V;
6439 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6440 int_x86_avx2_pmul_dq>, VEX_4V;
6443 let Constraints = "$src1 = $dst" in {
6444 let isCommutable = 0 in
6445 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6446 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6447 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6448 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6449 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6450 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6451 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6452 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6453 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6454 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6457 /// SS48I_binop_rm - Simple SSE41 binary operator.
6458 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6459 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6460 X86MemOperand x86memop, bit Is2Addr = 1> {
6461 let isCommutable = 1 in
6462 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6463 (ins RC:$src1, RC:$src2),
6465 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6466 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6467 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6468 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6469 (ins RC:$src1, x86memop:$src2),
6471 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6472 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6474 (OpVT (OpNode RC:$src1,
6475 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6478 let Predicates = [HasAVX] in {
6479 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6480 memopv2i64, i128mem, 0>, VEX_4V;
6481 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6482 memopv2i64, i128mem, 0>, VEX_4V;
6484 let Predicates = [HasAVX2] in {
6485 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6486 memopv4i64, i256mem, 0>, VEX_4V;
6487 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6488 memopv4i64, i256mem, 0>, VEX_4V;
6491 let Constraints = "$src1 = $dst" in {
6492 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6493 memopv2i64, i128mem>;
6494 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6495 memopv2i64, i128mem>;
6498 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6499 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6500 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6501 X86MemOperand x86memop, bit Is2Addr = 1> {
6502 let isCommutable = 1 in
6503 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6504 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6506 !strconcat(OpcodeStr,
6507 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6508 !strconcat(OpcodeStr,
6509 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6510 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6512 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6513 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6515 !strconcat(OpcodeStr,
6516 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6517 !strconcat(OpcodeStr,
6518 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6521 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6525 let Predicates = [HasAVX] in {
6526 let isCommutable = 0 in {
6527 let ExeDomain = SSEPackedSingle in {
6528 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6529 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6530 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6531 int_x86_avx_blend_ps_256, VR256, memopv8f32, f256mem, 0>, VEX_4V;
6533 let ExeDomain = SSEPackedDouble in {
6534 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6535 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6536 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6537 int_x86_avx_blend_pd_256, VR256, memopv4f64, f256mem, 0>, VEX_4V;
6539 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6540 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6541 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6542 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6544 let ExeDomain = SSEPackedSingle in
6545 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6546 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6547 let ExeDomain = SSEPackedDouble in
6548 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6549 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6550 let ExeDomain = SSEPackedSingle in
6551 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6552 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6555 let Predicates = [HasAVX2] in {
6556 let isCommutable = 0 in {
6557 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6558 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6559 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6560 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6564 let Constraints = "$src1 = $dst" in {
6565 let isCommutable = 0 in {
6566 let ExeDomain = SSEPackedSingle in
6567 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6568 VR128, memopv4f32, f128mem>;
6569 let ExeDomain = SSEPackedDouble in
6570 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6571 VR128, memopv2f64, f128mem>;
6572 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6573 VR128, memopv2i64, i128mem>;
6574 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6575 VR128, memopv2i64, i128mem>;
6577 let ExeDomain = SSEPackedSingle in
6578 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6579 VR128, memopv4f32, f128mem>;
6580 let ExeDomain = SSEPackedDouble in
6581 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6582 VR128, memopv2f64, f128mem>;
6585 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6586 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6587 RegisterClass RC, X86MemOperand x86memop,
6588 PatFrag mem_frag, Intrinsic IntId> {
6589 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6590 (ins RC:$src1, RC:$src2, RC:$src3),
6591 !strconcat(OpcodeStr,
6592 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6593 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6594 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6596 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6597 (ins RC:$src1, x86memop:$src2, RC:$src3),
6598 !strconcat(OpcodeStr,
6599 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6601 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6603 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6606 let Predicates = [HasAVX] in {
6607 let ExeDomain = SSEPackedDouble in {
6608 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6609 memopv2f64, int_x86_sse41_blendvpd>;
6610 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6611 memopv4f64, int_x86_avx_blendv_pd_256>;
6612 } // ExeDomain = SSEPackedDouble
6613 let ExeDomain = SSEPackedSingle in {
6614 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6615 memopv4f32, int_x86_sse41_blendvps>;
6616 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6617 memopv8f32, int_x86_avx_blendv_ps_256>;
6618 } // ExeDomain = SSEPackedSingle
6619 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6620 memopv2i64, int_x86_sse41_pblendvb>;
6623 let Predicates = [HasAVX2] in {
6624 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6625 memopv4i64, int_x86_avx2_pblendvb>;
6628 let Predicates = [HasAVX] in {
6629 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6630 (v16i8 VR128:$src2))),
6631 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6632 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6633 (v4i32 VR128:$src2))),
6634 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6635 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6636 (v4f32 VR128:$src2))),
6637 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6638 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6639 (v2i64 VR128:$src2))),
6640 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6641 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6642 (v2f64 VR128:$src2))),
6643 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6644 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6645 (v8i32 VR256:$src2))),
6646 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6647 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6648 (v8f32 VR256:$src2))),
6649 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6650 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6651 (v4i64 VR256:$src2))),
6652 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6653 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6654 (v4f64 VR256:$src2))),
6655 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6657 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6659 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6660 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6662 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6664 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6666 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6667 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6669 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6670 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6672 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6675 let Predicates = [HasAVX2] in {
6676 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6677 (v32i8 VR256:$src2))),
6678 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6679 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6681 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6684 /// SS41I_ternary_int - SSE 4.1 ternary operator
6685 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6686 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6687 X86MemOperand x86memop, Intrinsic IntId> {
6688 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6689 (ins VR128:$src1, VR128:$src2),
6690 !strconcat(OpcodeStr,
6691 "\t{$src2, $dst|$dst, $src2}"),
6692 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6695 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6696 (ins VR128:$src1, x86memop:$src2),
6697 !strconcat(OpcodeStr,
6698 "\t{$src2, $dst|$dst, $src2}"),
6701 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6705 let ExeDomain = SSEPackedDouble in
6706 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
6707 int_x86_sse41_blendvpd>;
6708 let ExeDomain = SSEPackedSingle in
6709 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
6710 int_x86_sse41_blendvps>;
6711 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
6712 int_x86_sse41_pblendvb>;
6714 // Aliases with the implicit xmm0 argument
6715 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6716 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
6717 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6718 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
6719 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6720 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
6721 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6722 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
6723 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6724 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
6725 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6726 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
6728 let Predicates = [UseSSE41] in {
6729 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6730 (v16i8 VR128:$src2))),
6731 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6732 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6733 (v4i32 VR128:$src2))),
6734 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6735 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6736 (v4f32 VR128:$src2))),
6737 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6738 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6739 (v2i64 VR128:$src2))),
6740 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6741 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6742 (v2f64 VR128:$src2))),
6743 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6745 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6747 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6748 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6750 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6751 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6753 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6757 let Predicates = [HasAVX] in
6758 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6759 "vmovntdqa\t{$src, $dst|$dst, $src}",
6760 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6762 let Predicates = [HasAVX2] in
6763 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6764 "vmovntdqa\t{$src, $dst|$dst, $src}",
6765 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6767 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6768 "movntdqa\t{$src, $dst|$dst, $src}",
6769 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6772 //===----------------------------------------------------------------------===//
6773 // SSE4.2 - Compare Instructions
6774 //===----------------------------------------------------------------------===//
6776 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6777 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6778 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6779 X86MemOperand x86memop, bit Is2Addr = 1> {
6780 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6781 (ins RC:$src1, RC:$src2),
6783 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6784 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6785 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6787 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6788 (ins RC:$src1, x86memop:$src2),
6790 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6791 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6793 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6796 let Predicates = [HasAVX] in
6797 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6798 memopv2i64, i128mem, 0>, VEX_4V;
6800 let Predicates = [HasAVX2] in
6801 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6802 memopv4i64, i256mem, 0>, VEX_4V;
6804 let Constraints = "$src1 = $dst" in
6805 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6806 memopv2i64, i128mem>;
6808 //===----------------------------------------------------------------------===//
6809 // SSE4.2 - String/text Processing Instructions
6810 //===----------------------------------------------------------------------===//
6812 // Packed Compare Implicit Length Strings, Return Mask
6813 multiclass pseudo_pcmpistrm<string asm> {
6814 def REG : PseudoI<(outs VR128:$dst),
6815 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6816 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6818 def MEM : PseudoI<(outs VR128:$dst),
6819 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6820 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6821 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6824 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6825 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6826 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
6829 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6830 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6831 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6832 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6834 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6835 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6836 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6839 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6840 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6841 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6842 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6844 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6845 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6846 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6849 // Packed Compare Explicit Length Strings, Return Mask
6850 multiclass pseudo_pcmpestrm<string asm> {
6851 def REG : PseudoI<(outs VR128:$dst),
6852 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6853 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6854 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6855 def MEM : PseudoI<(outs VR128:$dst),
6856 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6857 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6858 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6861 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6862 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6863 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
6866 let Predicates = [HasAVX],
6867 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6868 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6869 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6870 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6872 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6873 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6874 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6877 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6878 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6879 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6880 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6882 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6883 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6884 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6887 // Packed Compare Implicit Length Strings, Return Index
6888 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
6889 multiclass SS42AI_pcmpistri<string asm> {
6890 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6891 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6892 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6895 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6896 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6897 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6902 let Predicates = [HasAVX] in
6903 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
6904 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
6906 // Packed Compare Explicit Length Strings, Return Index
6907 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6908 multiclass SS42AI_pcmpestri<string asm> {
6909 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6910 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6911 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6914 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6915 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6916 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6921 let Predicates = [HasAVX] in
6922 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
6923 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
6925 //===----------------------------------------------------------------------===//
6926 // SSE4.2 - CRC Instructions
6927 //===----------------------------------------------------------------------===//
6929 // No CRC instructions have AVX equivalents
6931 // crc intrinsic instruction
6932 // This set of instructions are only rm, the only difference is the size
6934 let Constraints = "$src1 = $dst" in {
6935 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6936 (ins GR32:$src1, i8mem:$src2),
6937 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6939 (int_x86_sse42_crc32_32_8 GR32:$src1,
6940 (load addr:$src2)))]>;
6941 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6942 (ins GR32:$src1, GR8:$src2),
6943 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6945 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6946 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6947 (ins GR32:$src1, i16mem:$src2),
6948 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6950 (int_x86_sse42_crc32_32_16 GR32:$src1,
6951 (load addr:$src2)))]>,
6953 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6954 (ins GR32:$src1, GR16:$src2),
6955 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6957 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6959 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6960 (ins GR32:$src1, i32mem:$src2),
6961 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6963 (int_x86_sse42_crc32_32_32 GR32:$src1,
6964 (load addr:$src2)))]>;
6965 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6966 (ins GR32:$src1, GR32:$src2),
6967 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6969 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6970 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6971 (ins GR64:$src1, i8mem:$src2),
6972 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6974 (int_x86_sse42_crc32_64_8 GR64:$src1,
6975 (load addr:$src2)))]>,
6977 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6978 (ins GR64:$src1, GR8:$src2),
6979 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6981 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6983 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6984 (ins GR64:$src1, i64mem:$src2),
6985 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6987 (int_x86_sse42_crc32_64_64 GR64:$src1,
6988 (load addr:$src2)))]>,
6990 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6991 (ins GR64:$src1, GR64:$src2),
6992 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6994 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6998 //===----------------------------------------------------------------------===//
6999 // AES-NI Instructions
7000 //===----------------------------------------------------------------------===//
7002 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7003 Intrinsic IntId128, bit Is2Addr = 1> {
7004 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7005 (ins VR128:$src1, VR128:$src2),
7007 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7008 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7009 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7011 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7012 (ins VR128:$src1, i128mem:$src2),
7014 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7015 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7017 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7020 // Perform One Round of an AES Encryption/Decryption Flow
7021 let Predicates = [HasAVX, HasAES] in {
7022 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7023 int_x86_aesni_aesenc, 0>, VEX_4V;
7024 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7025 int_x86_aesni_aesenclast, 0>, VEX_4V;
7026 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7027 int_x86_aesni_aesdec, 0>, VEX_4V;
7028 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7029 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7032 let Constraints = "$src1 = $dst" in {
7033 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7034 int_x86_aesni_aesenc>;
7035 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7036 int_x86_aesni_aesenclast>;
7037 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7038 int_x86_aesni_aesdec>;
7039 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7040 int_x86_aesni_aesdeclast>;
7043 // Perform the AES InvMixColumn Transformation
7044 let Predicates = [HasAVX, HasAES] in {
7045 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7047 "vaesimc\t{$src1, $dst|$dst, $src1}",
7049 (int_x86_aesni_aesimc VR128:$src1))]>,
7051 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7052 (ins i128mem:$src1),
7053 "vaesimc\t{$src1, $dst|$dst, $src1}",
7054 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7057 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7059 "aesimc\t{$src1, $dst|$dst, $src1}",
7061 (int_x86_aesni_aesimc VR128:$src1))]>,
7063 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7064 (ins i128mem:$src1),
7065 "aesimc\t{$src1, $dst|$dst, $src1}",
7066 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7069 // AES Round Key Generation Assist
7070 let Predicates = [HasAVX, HasAES] in {
7071 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7072 (ins VR128:$src1, i8imm:$src2),
7073 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7075 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7077 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7078 (ins i128mem:$src1, i8imm:$src2),
7079 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7081 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7084 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7085 (ins VR128:$src1, i8imm:$src2),
7086 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7088 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7090 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7091 (ins i128mem:$src1, i8imm:$src2),
7092 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7094 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7097 //===----------------------------------------------------------------------===//
7098 // PCLMUL Instructions
7099 //===----------------------------------------------------------------------===//
7101 // AVX carry-less Multiplication instructions
7102 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7103 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7104 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7106 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7108 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7109 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7110 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7111 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7112 (memopv2i64 addr:$src2), imm:$src3))]>;
7114 // Carry-less Multiplication instructions
7115 let Constraints = "$src1 = $dst" in {
7116 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7117 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7118 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7120 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7122 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7123 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7124 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7125 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7126 (memopv2i64 addr:$src2), imm:$src3))]>;
7127 } // Constraints = "$src1 = $dst"
7130 multiclass pclmul_alias<string asm, int immop> {
7131 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7132 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7134 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7135 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7137 def : InstAlias<!strconcat("vpclmul", asm,
7138 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7139 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7141 def : InstAlias<!strconcat("vpclmul", asm,
7142 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7143 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7145 defm : pclmul_alias<"hqhq", 0x11>;
7146 defm : pclmul_alias<"hqlq", 0x01>;
7147 defm : pclmul_alias<"lqhq", 0x10>;
7148 defm : pclmul_alias<"lqlq", 0x00>;
7150 //===----------------------------------------------------------------------===//
7151 // SSE4A Instructions
7152 //===----------------------------------------------------------------------===//
7154 let Predicates = [HasSSE4A] in {
7156 let Constraints = "$src = $dst" in {
7157 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7158 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7159 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7160 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7161 imm:$idx))]>, TB, OpSize;
7162 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7163 (ins VR128:$src, VR128:$mask),
7164 "extrq\t{$mask, $src|$src, $mask}",
7165 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7166 VR128:$mask))]>, TB, OpSize;
7168 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7169 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7170 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7171 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7172 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7173 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7174 (ins VR128:$src, VR128:$mask),
7175 "insertq\t{$mask, $src|$src, $mask}",
7176 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7177 VR128:$mask))]>, XD;
7180 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7181 "movntss\t{$src, $dst|$dst, $src}",
7182 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7184 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7185 "movntsd\t{$src, $dst|$dst, $src}",
7186 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7189 //===----------------------------------------------------------------------===//
7191 //===----------------------------------------------------------------------===//
7193 //===----------------------------------------------------------------------===//
7194 // VBROADCAST - Load from memory and broadcast to all elements of the
7195 // destination operand
7197 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7198 X86MemOperand x86memop, Intrinsic Int> :
7199 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7200 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7201 [(set RC:$dst, (Int addr:$src))]>, VEX;
7203 // AVX2 adds register forms
7204 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7206 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7207 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7208 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7210 let ExeDomain = SSEPackedSingle in {
7211 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7212 int_x86_avx_vbroadcast_ss>;
7213 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7214 int_x86_avx_vbroadcast_ss_256>;
7216 let ExeDomain = SSEPackedDouble in
7217 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7218 int_x86_avx_vbroadcast_sd_256>;
7219 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7220 int_x86_avx_vbroadcastf128_pd_256>;
7222 let ExeDomain = SSEPackedSingle in {
7223 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7224 int_x86_avx2_vbroadcast_ss_ps>;
7225 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7226 int_x86_avx2_vbroadcast_ss_ps_256>;
7228 let ExeDomain = SSEPackedDouble in
7229 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7230 int_x86_avx2_vbroadcast_sd_pd_256>;
7232 let Predicates = [HasAVX2] in
7233 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7234 int_x86_avx2_vbroadcasti128>;
7236 let Predicates = [HasAVX] in
7237 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7238 (VBROADCASTF128 addr:$src)>;
7241 //===----------------------------------------------------------------------===//
7242 // VINSERTF128 - Insert packed floating-point values
7244 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7245 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7246 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7247 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7250 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7251 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7252 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7256 let Predicates = [HasAVX] in {
7257 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7259 (VINSERTF128rr VR256:$src1, VR128:$src2,
7260 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7261 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7263 (VINSERTF128rr VR256:$src1, VR128:$src2,
7264 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7266 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7268 (VINSERTF128rm VR256:$src1, addr:$src2,
7269 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7270 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7272 (VINSERTF128rm VR256:$src1, addr:$src2,
7273 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7276 let Predicates = [HasAVX1Only] in {
7277 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7279 (VINSERTF128rr VR256:$src1, VR128:$src2,
7280 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7281 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7283 (VINSERTF128rr VR256:$src1, VR128:$src2,
7284 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7285 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7287 (VINSERTF128rr VR256:$src1, VR128:$src2,
7288 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7289 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7291 (VINSERTF128rr VR256:$src1, VR128:$src2,
7292 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7294 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7296 (VINSERTF128rm VR256:$src1, addr:$src2,
7297 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7298 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7299 (bc_v4i32 (memopv2i64 addr:$src2)),
7301 (VINSERTF128rm VR256:$src1, addr:$src2,
7302 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7303 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7304 (bc_v16i8 (memopv2i64 addr:$src2)),
7306 (VINSERTF128rm VR256:$src1, addr:$src2,
7307 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7308 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7309 (bc_v8i16 (memopv2i64 addr:$src2)),
7311 (VINSERTF128rm VR256:$src1, addr:$src2,
7312 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7315 //===----------------------------------------------------------------------===//
7316 // VEXTRACTF128 - Extract packed floating-point values
7318 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7319 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7320 (ins VR256:$src1, i8imm:$src2),
7321 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7324 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7325 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7326 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7331 let Predicates = [HasAVX] in {
7332 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7333 (v4f32 (VEXTRACTF128rr
7334 (v8f32 VR256:$src1),
7335 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7336 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7337 (v2f64 (VEXTRACTF128rr
7338 (v4f64 VR256:$src1),
7339 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7341 def : Pat<(alignedstore (v4f32 (vextractf128_extract:$ext (v8f32 VR256:$src1),
7342 (iPTR imm))), addr:$dst),
7343 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7344 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7345 def : Pat<(alignedstore (v2f64 (vextractf128_extract:$ext (v4f64 VR256:$src1),
7346 (iPTR imm))), addr:$dst),
7347 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7348 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7351 let Predicates = [HasAVX1Only] in {
7352 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7353 (v2i64 (VEXTRACTF128rr
7354 (v4i64 VR256:$src1),
7355 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7356 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7357 (v4i32 (VEXTRACTF128rr
7358 (v8i32 VR256:$src1),
7359 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7360 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7361 (v8i16 (VEXTRACTF128rr
7362 (v16i16 VR256:$src1),
7363 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7364 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7365 (v16i8 (VEXTRACTF128rr
7366 (v32i8 VR256:$src1),
7367 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7369 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7370 (iPTR imm))), addr:$dst),
7371 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7372 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7373 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7374 (iPTR imm))), addr:$dst),
7375 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7376 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7377 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7378 (iPTR imm))), addr:$dst),
7379 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7380 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7381 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7382 (iPTR imm))), addr:$dst),
7383 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7384 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7387 //===----------------------------------------------------------------------===//
7388 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7390 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7391 Intrinsic IntLd, Intrinsic IntLd256,
7392 Intrinsic IntSt, Intrinsic IntSt256> {
7393 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7394 (ins VR128:$src1, f128mem:$src2),
7395 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7396 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7398 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7399 (ins VR256:$src1, f256mem:$src2),
7400 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7401 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7403 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7404 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7405 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7406 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7407 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7408 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7409 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7410 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7413 let ExeDomain = SSEPackedSingle in
7414 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7415 int_x86_avx_maskload_ps,
7416 int_x86_avx_maskload_ps_256,
7417 int_x86_avx_maskstore_ps,
7418 int_x86_avx_maskstore_ps_256>;
7419 let ExeDomain = SSEPackedDouble in
7420 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7421 int_x86_avx_maskload_pd,
7422 int_x86_avx_maskload_pd_256,
7423 int_x86_avx_maskstore_pd,
7424 int_x86_avx_maskstore_pd_256>;
7426 //===----------------------------------------------------------------------===//
7427 // VPERMIL - Permute Single and Double Floating-Point Values
7429 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7430 RegisterClass RC, X86MemOperand x86memop_f,
7431 X86MemOperand x86memop_i, PatFrag i_frag,
7432 Intrinsic IntVar, ValueType vt> {
7433 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7434 (ins RC:$src1, RC:$src2),
7435 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7436 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7437 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7438 (ins RC:$src1, x86memop_i:$src2),
7439 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7440 [(set RC:$dst, (IntVar RC:$src1,
7441 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7443 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7444 (ins RC:$src1, i8imm:$src2),
7445 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7446 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7447 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7448 (ins x86memop_f:$src1, i8imm:$src2),
7449 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7451 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7454 let ExeDomain = SSEPackedSingle in {
7455 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7456 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7457 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7458 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7460 let ExeDomain = SSEPackedDouble in {
7461 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7462 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7463 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7464 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7467 let Predicates = [HasAVX] in {
7468 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7469 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7470 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7471 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7472 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7474 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7475 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7476 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7478 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7479 (VPERMILPDri VR128:$src1, imm:$imm)>;
7480 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7481 (VPERMILPDmi addr:$src1, imm:$imm)>;
7484 //===----------------------------------------------------------------------===//
7485 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7487 let ExeDomain = SSEPackedSingle in {
7488 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7489 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7490 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7491 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7492 (i8 imm:$src3))))]>, VEX_4V;
7493 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7494 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7495 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7496 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7497 (i8 imm:$src3)))]>, VEX_4V;
7500 let Predicates = [HasAVX] in {
7501 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7502 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7503 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7504 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7505 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7508 let Predicates = [HasAVX1Only] in {
7509 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7510 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7511 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7512 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7513 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7514 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7515 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7516 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7518 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7519 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7520 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7521 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7522 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7523 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7524 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7525 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7526 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7527 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7528 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7529 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7532 //===----------------------------------------------------------------------===//
7533 // VZERO - Zero YMM registers
7535 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7536 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7537 // Zero All YMM registers
7538 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7539 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7541 // Zero Upper bits of YMM registers
7542 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7543 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7546 //===----------------------------------------------------------------------===//
7547 // Half precision conversion instructions
7548 //===----------------------------------------------------------------------===//
7549 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7550 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7551 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7552 [(set RC:$dst, (Int VR128:$src))]>,
7554 let neverHasSideEffects = 1, mayLoad = 1 in
7555 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7556 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7559 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7560 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7561 (ins RC:$src1, i32i8imm:$src2),
7562 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7563 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7565 let neverHasSideEffects = 1, mayStore = 1 in
7566 def mr : Ii8<0x1D, MRMDestMem, (outs),
7567 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7568 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7572 let Predicates = [HasAVX, HasF16C] in {
7573 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7574 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7575 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7576 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7579 //===----------------------------------------------------------------------===//
7580 // AVX2 Instructions
7581 //===----------------------------------------------------------------------===//
7583 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7584 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7585 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7586 X86MemOperand x86memop> {
7587 let isCommutable = 1 in
7588 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7589 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7590 !strconcat(OpcodeStr,
7591 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7592 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7594 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7595 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7596 !strconcat(OpcodeStr,
7597 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7600 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7604 let isCommutable = 0 in {
7605 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7606 VR128, memopv2i64, i128mem>;
7607 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7608 VR256, memopv4i64, i256mem>;
7611 //===----------------------------------------------------------------------===//
7612 // VPBROADCAST - Load from memory and broadcast to all elements of the
7613 // destination operand
7615 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7616 X86MemOperand x86memop, PatFrag ld_frag,
7617 Intrinsic Int128, Intrinsic Int256> {
7618 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7619 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7620 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7621 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7622 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7624 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7625 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7626 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7627 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7628 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7629 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7631 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7634 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7635 int_x86_avx2_pbroadcastb_128,
7636 int_x86_avx2_pbroadcastb_256>;
7637 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7638 int_x86_avx2_pbroadcastw_128,
7639 int_x86_avx2_pbroadcastw_256>;
7640 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7641 int_x86_avx2_pbroadcastd_128,
7642 int_x86_avx2_pbroadcastd_256>;
7643 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7644 int_x86_avx2_pbroadcastq_128,
7645 int_x86_avx2_pbroadcastq_256>;
7647 let Predicates = [HasAVX2] in {
7648 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7649 (VPBROADCASTBrm addr:$src)>;
7650 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7651 (VPBROADCASTBYrm addr:$src)>;
7652 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7653 (VPBROADCASTWrm addr:$src)>;
7654 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7655 (VPBROADCASTWYrm addr:$src)>;
7656 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7657 (VPBROADCASTDrm addr:$src)>;
7658 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7659 (VPBROADCASTDYrm addr:$src)>;
7660 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7661 (VPBROADCASTQrm addr:$src)>;
7662 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7663 (VPBROADCASTQYrm addr:$src)>;
7665 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
7666 (VPBROADCASTBrr VR128:$src)>;
7667 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
7668 (VPBROADCASTBYrr VR128:$src)>;
7669 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
7670 (VPBROADCASTWrr VR128:$src)>;
7671 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
7672 (VPBROADCASTWYrr VR128:$src)>;
7673 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
7674 (VPBROADCASTDrr VR128:$src)>;
7675 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
7676 (VPBROADCASTDYrr VR128:$src)>;
7677 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
7678 (VPBROADCASTQrr VR128:$src)>;
7679 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
7680 (VPBROADCASTQYrr VR128:$src)>;
7681 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
7682 (VBROADCASTSSrr VR128:$src)>;
7683 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
7684 (VBROADCASTSSYrr VR128:$src)>;
7685 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
7686 (VPBROADCASTQrr VR128:$src)>;
7687 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
7688 (VBROADCASTSDYrr VR128:$src)>;
7690 // Provide fallback in case the load node that is used in the patterns above
7691 // is used by additional users, which prevents the pattern selection.
7692 let AddedComplexity = 20 in {
7693 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7694 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7695 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7696 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7697 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7698 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
7700 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7701 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7702 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7703 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7704 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7705 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
7709 // AVX1 broadcast patterns
7710 let Predicates = [HasAVX1Only] in {
7711 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7712 (VBROADCASTSSYrm addr:$src)>;
7713 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7714 (VBROADCASTSDYrm addr:$src)>;
7715 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7716 (VBROADCASTSSrm addr:$src)>;
7719 let Predicates = [HasAVX] in {
7720 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7721 (VBROADCASTSSYrm addr:$src)>;
7722 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7723 (VBROADCASTSDYrm addr:$src)>;
7724 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7725 (VBROADCASTSSrm addr:$src)>;
7727 // Provide fallback in case the load node that is used in the patterns above
7728 // is used by additional users, which prevents the pattern selection.
7729 let AddedComplexity = 20 in {
7730 // 128bit broadcasts:
7731 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7732 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
7733 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7734 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7735 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
7736 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
7737 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7738 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7739 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
7740 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
7742 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7743 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
7744 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7745 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7746 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
7747 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
7748 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7749 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7750 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
7751 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
7755 //===----------------------------------------------------------------------===//
7756 // VPERM - Permute instructions
7759 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7761 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7762 (ins VR256:$src1, VR256:$src2),
7763 !strconcat(OpcodeStr,
7764 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7766 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7767 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7768 (ins VR256:$src1, i256mem:$src2),
7769 !strconcat(OpcodeStr,
7770 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7772 (OpVT (X86VPermv VR256:$src1,
7773 (bitconvert (mem_frag addr:$src2)))))]>,
7777 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7778 let ExeDomain = SSEPackedSingle in
7779 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7781 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7783 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7784 (ins VR256:$src1, i8imm:$src2),
7785 !strconcat(OpcodeStr,
7786 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7788 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7789 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7790 (ins i256mem:$src1, i8imm:$src2),
7791 !strconcat(OpcodeStr,
7792 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7794 (OpVT (X86VPermi (mem_frag addr:$src1),
7795 (i8 imm:$src2))))]>, VEX;
7798 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7799 let ExeDomain = SSEPackedDouble in
7800 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7802 //===----------------------------------------------------------------------===//
7803 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7805 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7806 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7807 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7808 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7809 (i8 imm:$src3))))]>, VEX_4V;
7810 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7811 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7812 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7813 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7814 (i8 imm:$src3)))]>, VEX_4V;
7816 let Predicates = [HasAVX2] in {
7817 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7818 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7819 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7820 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7821 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7822 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7824 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7826 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7827 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7828 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7829 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7830 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7832 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7836 //===----------------------------------------------------------------------===//
7837 // VINSERTI128 - Insert packed integer values
7839 let neverHasSideEffects = 1 in {
7840 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7841 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7842 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7845 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7846 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7847 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7851 let Predicates = [HasAVX2] in {
7852 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7854 (VINSERTI128rr VR256:$src1, VR128:$src2,
7855 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7856 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7858 (VINSERTI128rr VR256:$src1, VR128:$src2,
7859 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7860 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7862 (VINSERTI128rr VR256:$src1, VR128:$src2,
7863 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7864 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7866 (VINSERTI128rr VR256:$src1, VR128:$src2,
7867 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7869 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7871 (VINSERTI128rm VR256:$src1, addr:$src2,
7872 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7873 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7874 (bc_v4i32 (memopv2i64 addr:$src2)),
7876 (VINSERTI128rm VR256:$src1, addr:$src2,
7877 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7878 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7879 (bc_v16i8 (memopv2i64 addr:$src2)),
7881 (VINSERTI128rm VR256:$src1, addr:$src2,
7882 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7883 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7884 (bc_v8i16 (memopv2i64 addr:$src2)),
7886 (VINSERTI128rm VR256:$src1, addr:$src2,
7887 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7890 //===----------------------------------------------------------------------===//
7891 // VEXTRACTI128 - Extract packed integer values
7893 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7894 (ins VR256:$src1, i8imm:$src2),
7895 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7897 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7899 let neverHasSideEffects = 1, mayStore = 1 in
7900 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7901 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7902 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7904 let Predicates = [HasAVX2] in {
7905 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7906 (v2i64 (VEXTRACTI128rr
7907 (v4i64 VR256:$src1),
7908 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7909 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7910 (v4i32 (VEXTRACTI128rr
7911 (v8i32 VR256:$src1),
7912 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7913 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7914 (v8i16 (VEXTRACTI128rr
7915 (v16i16 VR256:$src1),
7916 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7917 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7918 (v16i8 (VEXTRACTI128rr
7919 (v32i8 VR256:$src1),
7920 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7922 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7923 (iPTR imm))), addr:$dst),
7924 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7925 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7926 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7927 (iPTR imm))), addr:$dst),
7928 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7929 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7930 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7931 (iPTR imm))), addr:$dst),
7932 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7933 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7934 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7935 (iPTR imm))), addr:$dst),
7936 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7937 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7940 //===----------------------------------------------------------------------===//
7941 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7943 multiclass avx2_pmovmask<string OpcodeStr,
7944 Intrinsic IntLd128, Intrinsic IntLd256,
7945 Intrinsic IntSt128, Intrinsic IntSt256> {
7946 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7947 (ins VR128:$src1, i128mem:$src2),
7948 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7949 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7950 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7951 (ins VR256:$src1, i256mem:$src2),
7952 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7953 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7954 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7955 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7956 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7957 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7958 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7959 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7960 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7961 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7964 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7965 int_x86_avx2_maskload_d,
7966 int_x86_avx2_maskload_d_256,
7967 int_x86_avx2_maskstore_d,
7968 int_x86_avx2_maskstore_d_256>;
7969 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7970 int_x86_avx2_maskload_q,
7971 int_x86_avx2_maskload_q_256,
7972 int_x86_avx2_maskstore_q,
7973 int_x86_avx2_maskstore_q_256>, VEX_W;
7976 //===----------------------------------------------------------------------===//
7977 // Variable Bit Shifts
7979 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7980 ValueType vt128, ValueType vt256> {
7981 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7982 (ins VR128:$src1, VR128:$src2),
7983 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7985 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7987 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7988 (ins VR128:$src1, i128mem:$src2),
7989 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7991 (vt128 (OpNode VR128:$src1,
7992 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7994 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7995 (ins VR256:$src1, VR256:$src2),
7996 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7998 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8000 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8001 (ins VR256:$src1, i256mem:$src2),
8002 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8004 (vt256 (OpNode VR256:$src1,
8005 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8009 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8010 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8011 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8012 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8013 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8015 //===----------------------------------------------------------------------===//
8016 // VGATHER - GATHER Operations
8017 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8018 X86MemOperand memop128, X86MemOperand memop256> {
8019 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8020 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8021 !strconcat(OpcodeStr,
8022 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8024 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8025 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8026 !strconcat(OpcodeStr,
8027 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8028 []>, VEX_4VOp3, VEX_L;
8031 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
8032 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8033 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8034 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8035 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8036 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8037 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8038 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8039 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;