1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
22 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
23 [SDNPCommutative, SDNPAssociative]>;
24 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
25 [SDNPCommutative, SDNPAssociative]>;
26 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
28 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
30 def X86s2vec : SDNode<"X86ISD::S2VEC",
31 SDTypeProfile<1, 1, []>, []>;
32 def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
33 SDTypeProfile<1, 1, []>, []>;
34 def X86pextrw : SDNode<"X86ISD::PEXTRW",
35 SDTypeProfile<1, 2, []>, []>;
36 def X86pinsrw : SDNode<"X86ISD::PINSRW",
37 SDTypeProfile<1, 3, []>, []>;
39 //===----------------------------------------------------------------------===//
40 // SSE pattern fragments
41 //===----------------------------------------------------------------------===//
43 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
44 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
46 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
47 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
48 def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
49 def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
50 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
51 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
53 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
54 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
55 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
56 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
57 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
58 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
60 def fp32imm0 : PatLeaf<(f32 fpimm), [{
61 return N->isExactlyValue(+0.0);
64 def PSxLDQ_imm : SDNodeXForm<imm, [{
65 // Transformation function: imm >> 3
66 return getI32Imm(N->getValue() >> 3);
69 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
71 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
72 return getI8Imm(X86::getShuffleSHUFImmediate(N));
75 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
77 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
78 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
81 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
83 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
84 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
87 def SSE_splat_mask : PatLeaf<(build_vector), [{
88 return X86::isSplatMask(N);
89 }], SHUFFLE_get_shuf_imm>;
91 def SSE_splat_v2_mask : PatLeaf<(build_vector), [{
92 return X86::isSplatMask(N);
95 def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
96 return X86::isMOVLHPSMask(N);
99 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
100 return X86::isMOVHLPSMask(N);
103 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
104 return X86::isMOVHPMask(N);
107 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
108 return X86::isMOVLPMask(N);
111 def MOVS_shuffle_mask : PatLeaf<(build_vector), [{
112 return X86::isMOVSMask(N);
115 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
116 return X86::isMOVSHDUPMask(N);
119 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
120 return X86::isMOVSLDUPMask(N);
123 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
124 return X86::isUNPCKLMask(N);
127 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
128 return X86::isUNPCKHMask(N);
131 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
132 return X86::isUNPCKL_v_undef_Mask(N);
135 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isPSHUFDMask(N);
137 }], SHUFFLE_get_shuf_imm>;
139 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isPSHUFHWMask(N);
141 }], SHUFFLE_get_pshufhw_imm>;
143 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isPSHUFLWMask(N);
145 }], SHUFFLE_get_pshuflw_imm>;
147 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
148 return X86::isPSHUFDMask(N);
149 }], SHUFFLE_get_shuf_imm>;
151 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
152 return X86::isSHUFPMask(N);
153 }], SHUFFLE_get_shuf_imm>;
155 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
156 return X86::isSHUFPMask(N);
157 }], SHUFFLE_get_shuf_imm>;
159 //===----------------------------------------------------------------------===//
160 // SSE scalar FP Instructions
161 //===----------------------------------------------------------------------===//
163 // Instruction templates
164 // SSI - SSE1 instructions with XS prefix.
165 // SDI - SSE2 instructions with XD prefix.
166 // PSI - SSE1 instructions with TB prefix.
167 // PDI - SSE2 instructions with TB and OpSize prefixes.
168 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
169 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
170 // S3I - SSE3 instructions with TB and OpSize prefixes.
171 // S3SI - SSE3 instructions with XS prefix.
172 // S3DI - SSE3 instructions with XD prefix.
173 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
174 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
175 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
176 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
177 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
178 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
179 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
180 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
181 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
182 : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasSSE1]> {
183 let Pattern = pattern;
185 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
186 : X86Inst<o, F, Imm8, ops, asm>, TB, OpSize, Requires<[HasSSE2]> {
187 let Pattern = pattern;
189 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
190 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
191 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
192 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
193 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
194 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
196 //===----------------------------------------------------------------------===//
197 // Helpers for defining instructions that directly correspond to intrinsics.
198 class SS_Intr<bits<8> o, string asm, Intrinsic IntId>
199 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
200 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
201 class SS_Intm<bits<8> o, string asm, Intrinsic IntId>
202 : SSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
203 [(set VR128:$dst, (v4f32 (IntId (load addr:$src))))]>;
204 class SD_Intr<bits<8> o, string asm, Intrinsic IntId>
205 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
206 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
207 class SD_Intm<bits<8> o, string asm, Intrinsic IntId>
208 : SDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
209 [(set VR128:$dst, (v2f64 (IntId (load addr:$src))))]>;
211 class SS_Intrr<bits<8> o, string asm, Intrinsic IntId>
212 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
213 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
214 class SS_Intrm<bits<8> o, string asm, Intrinsic IntId>
215 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
216 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
217 class SD_Intrr<bits<8> o, string asm, Intrinsic IntId>
218 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
219 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
220 class SD_Intrm<bits<8> o, string asm, Intrinsic IntId>
221 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
222 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
224 class PS_Intr<bits<8> o, string asm, Intrinsic IntId>
225 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
226 [(set VR128:$dst, (IntId VR128:$src))]>;
227 class PS_Intm<bits<8> o, string asm, Intrinsic IntId>
228 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
229 [(set VR128:$dst, (IntId (loadv4f32 addr:$src)))]>;
230 class PD_Intr<bits<8> o, string asm, Intrinsic IntId>
231 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
232 [(set VR128:$dst, (IntId VR128:$src))]>;
233 class PD_Intm<bits<8> o, string asm, Intrinsic IntId>
234 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
235 [(set VR128:$dst, (IntId (loadv2f64 addr:$src)))]>;
237 class PS_Intrr<bits<8> o, string asm, Intrinsic IntId>
238 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
239 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
240 class PS_Intrm<bits<8> o, string asm, Intrinsic IntId>
241 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
242 [(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))]>;
243 class PD_Intrr<bits<8> o, string asm, Intrinsic IntId>
244 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
245 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
246 class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
247 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
248 [(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
250 class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
251 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
252 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
253 class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
254 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
255 [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
256 (loadv4f32 addr:$src2))))]>;
257 class S3_Intrr<bits<8> o, string asm, Intrinsic IntId>
258 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
259 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
260 class S3_Intrm<bits<8> o, string asm, Intrinsic IntId>
261 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
262 [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
263 (loadv2f64 addr:$src2))))]>;
265 // Some 'special' instructions
266 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
267 "#IMPLICIT_DEF $dst",
268 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
269 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
270 "#IMPLICIT_DEF $dst",
271 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
273 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
274 // scheduler into a branch sequence.
275 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
276 def CMOV_FR32 : I<0, Pseudo,
277 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
278 "#CMOV_FR32 PSEUDO!",
279 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
280 def CMOV_FR64 : I<0, Pseudo,
281 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
282 "#CMOV_FR64 PSEUDO!",
283 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
284 def CMOV_V4F32 : I<0, Pseudo,
285 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
286 "#CMOV_V4F32 PSEUDO!",
288 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
289 def CMOV_V2F64 : I<0, Pseudo,
290 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
291 "#CMOV_V2F64 PSEUDO!",
293 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
294 def CMOV_V2I64 : I<0, Pseudo,
295 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
296 "#CMOV_V2I64 PSEUDO!",
298 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
302 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
303 "movss {$src, $dst|$dst, $src}", []>;
304 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
305 "movss {$src, $dst|$dst, $src}",
306 [(set FR32:$dst, (loadf32 addr:$src))]>;
307 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
308 "movsd {$src, $dst|$dst, $src}", []>;
309 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
310 "movsd {$src, $dst|$dst, $src}",
311 [(set FR64:$dst, (loadf64 addr:$src))]>;
313 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
314 "movss {$src, $dst|$dst, $src}",
315 [(store FR32:$src, addr:$dst)]>;
316 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
317 "movsd {$src, $dst|$dst, $src}",
318 [(store FR64:$src, addr:$dst)]>;
320 // Arithmetic instructions
321 let isTwoAddress = 1 in {
322 let isCommutable = 1 in {
323 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
324 "addss {$src2, $dst|$dst, $src2}",
325 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
326 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
327 "addsd {$src2, $dst|$dst, $src2}",
328 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
329 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
330 "mulss {$src2, $dst|$dst, $src2}",
331 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
332 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
333 "mulsd {$src2, $dst|$dst, $src2}",
334 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
337 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
338 "addss {$src2, $dst|$dst, $src2}",
339 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
340 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
341 "addsd {$src2, $dst|$dst, $src2}",
342 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
343 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
344 "mulss {$src2, $dst|$dst, $src2}",
345 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
346 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
347 "mulsd {$src2, $dst|$dst, $src2}",
348 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
350 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
351 "divss {$src2, $dst|$dst, $src2}",
352 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
353 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
354 "divss {$src2, $dst|$dst, $src2}",
355 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
356 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
357 "divsd {$src2, $dst|$dst, $src2}",
358 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
359 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
360 "divsd {$src2, $dst|$dst, $src2}",
361 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
363 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
364 "subss {$src2, $dst|$dst, $src2}",
365 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
366 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
367 "subss {$src2, $dst|$dst, $src2}",
368 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
369 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
370 "subsd {$src2, $dst|$dst, $src2}",
371 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
372 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
373 "subsd {$src2, $dst|$dst, $src2}",
374 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
377 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
378 "sqrtss {$src, $dst|$dst, $src}",
379 [(set FR32:$dst, (fsqrt FR32:$src))]>;
380 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
381 "sqrtss {$src, $dst|$dst, $src}",
382 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
383 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
384 "sqrtsd {$src, $dst|$dst, $src}",
385 [(set FR64:$dst, (fsqrt FR64:$src))]>;
386 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
387 "sqrtsd {$src, $dst|$dst, $src}",
388 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
390 def RSQRTSSr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
391 "rsqrtss {$src, $dst|$dst, $src}", []>;
392 def RSQRTSSm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
393 "rsqrtss {$src, $dst|$dst, $src}", []>;
394 def RCPSSr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
395 "rcpss {$src, $dst|$dst, $src}", []>;
396 def RCPSSm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
397 "rcpss {$src, $dst|$dst, $src}", []>;
399 let isTwoAddress = 1 in {
400 def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
401 "maxss {$src2, $dst|$dst, $src2}", []>;
402 def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
403 "maxss {$src2, $dst|$dst, $src2}", []>;
404 def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
405 "maxsd {$src2, $dst|$dst, $src2}", []>;
406 def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
407 "maxsd {$src2, $dst|$dst, $src2}", []>;
408 def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
409 "minss {$src2, $dst|$dst, $src2}", []>;
410 def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
411 "minss {$src2, $dst|$dst, $src2}", []>;
412 def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
413 "minsd {$src2, $dst|$dst, $src2}", []>;
414 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
415 "minsd {$src2, $dst|$dst, $src2}", []>;
418 // Aliases to match intrinsics which expect XMM operand(s).
419 let isTwoAddress = 1 in {
420 let isCommutable = 1 in {
421 def Int_ADDSSrr : SS_Intrr<0x58, "addss {$src2, $dst|$dst, $src2}",
423 def Int_ADDSDrr : SD_Intrr<0x58, "addsd {$src2, $dst|$dst, $src2}",
424 int_x86_sse2_add_sd>;
425 def Int_MULSSrr : SS_Intrr<0x59, "mulss {$src2, $dst|$dst, $src2}",
427 def Int_MULSDrr : SD_Intrr<0x59, "mulsd {$src2, $dst|$dst, $src2}",
428 int_x86_sse2_mul_sd>;
431 def Int_ADDSSrm : SS_Intrm<0x58, "addss {$src2, $dst|$dst, $src2}",
433 def Int_ADDSDrm : SD_Intrm<0x58, "addsd {$src2, $dst|$dst, $src2}",
434 int_x86_sse2_add_sd>;
435 def Int_MULSSrm : SS_Intrm<0x59, "mulss {$src2, $dst|$dst, $src2}",
437 def Int_MULSDrm : SD_Intrm<0x59, "mulsd {$src2, $dst|$dst, $src2}",
438 int_x86_sse2_mul_sd>;
440 def Int_DIVSSrr : SS_Intrr<0x5E, "divss {$src2, $dst|$dst, $src2}",
442 def Int_DIVSSrm : SS_Intrm<0x5E, "divss {$src2, $dst|$dst, $src2}",
444 def Int_DIVSDrr : SD_Intrr<0x5E, "divsd {$src2, $dst|$dst, $src2}",
445 int_x86_sse2_div_sd>;
446 def Int_DIVSDrm : SD_Intrm<0x5E, "divsd {$src2, $dst|$dst, $src2}",
447 int_x86_sse2_div_sd>;
449 def Int_SUBSSrr : SS_Intrr<0x5C, "subss {$src2, $dst|$dst, $src2}",
451 def Int_SUBSSrm : SS_Intrm<0x5C, "subss {$src2, $dst|$dst, $src2}",
453 def Int_SUBSDrr : SD_Intrr<0x5C, "subsd {$src2, $dst|$dst, $src2}",
454 int_x86_sse2_sub_sd>;
455 def Int_SUBSDrm : SD_Intrm<0x5C, "subsd {$src2, $dst|$dst, $src2}",
456 int_x86_sse2_sub_sd>;
459 def Int_SQRTSSr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}",
460 int_x86_sse_sqrt_ss>;
461 def Int_SQRTSSm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}",
462 int_x86_sse_sqrt_ss>;
463 def Int_SQRTSDr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}",
464 int_x86_sse2_sqrt_sd>;
465 def Int_SQRTSDm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}",
466 int_x86_sse2_sqrt_sd>;
468 def Int_RSQRTSSr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}",
469 int_x86_sse_rsqrt_ss>;
470 def Int_RSQRTSSm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}",
471 int_x86_sse_rsqrt_ss>;
472 def Int_RCPSSr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}",
474 def Int_RCPSSm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}",
477 let isTwoAddress = 1 in {
478 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}",
480 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}",
482 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
483 int_x86_sse2_max_sd>;
484 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
485 int_x86_sse2_max_sd>;
486 def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}",
488 def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}",
490 def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}",
491 int_x86_sse2_min_sd>;
492 def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}",
493 int_x86_sse2_min_sd>;
496 // Conversion instructions
497 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
498 "cvttss2si {$src, $dst|$dst, $src}",
499 [(set R32:$dst, (fp_to_sint FR32:$src))]>;
500 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
501 "cvttss2si {$src, $dst|$dst, $src}",
502 [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
503 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
504 "cvttsd2si {$src, $dst|$dst, $src}",
505 [(set R32:$dst, (fp_to_sint FR64:$src))]>;
506 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
507 "cvttsd2si {$src, $dst|$dst, $src}",
508 [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
509 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
510 "cvtsd2ss {$src, $dst|$dst, $src}",
511 [(set FR32:$dst, (fround FR64:$src))]>;
512 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
513 "cvtsd2ss {$src, $dst|$dst, $src}",
514 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
515 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
516 "cvtsi2ss {$src, $dst|$dst, $src}",
517 [(set FR32:$dst, (sint_to_fp R32:$src))]>;
518 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
519 "cvtsi2ss {$src, $dst|$dst, $src}",
520 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
521 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
522 "cvtsi2sd {$src, $dst|$dst, $src}",
523 [(set FR64:$dst, (sint_to_fp R32:$src))]>;
524 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
525 "cvtsi2sd {$src, $dst|$dst, $src}",
526 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
528 // SSE2 instructions with XS prefix
529 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
530 "cvtss2sd {$src, $dst|$dst, $src}",
531 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
533 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
534 "cvtss2sd {$src, $dst|$dst, $src}",
535 [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
538 // Match intrinsics which expect XMM operand(s).
539 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
540 "cvtss2si {$src, $dst|$dst, $src}",
541 [(set R32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
542 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
543 "cvtss2si {$src, $dst|$dst, $src}",
544 [(set R32:$dst, (int_x86_sse_cvtss2si
545 (loadv4f32 addr:$src)))]>;
546 def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
547 "cvtsd2si {$src, $dst|$dst, $src}",
548 [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
549 def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
550 "cvtsd2si {$src, $dst|$dst, $src}",
551 [(set R32:$dst, (int_x86_sse2_cvtsd2si
552 (loadv2f64 addr:$src)))]>;
554 // Aliases for intrinsics
555 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
556 "cvttss2si {$src, $dst|$dst, $src}",
557 [(set R32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
558 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
559 "cvttss2si {$src, $dst|$dst, $src}",
560 [(set R32:$dst, (int_x86_sse_cvttss2si
561 (loadv4f32 addr:$src)))]>;
562 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
563 "cvttsd2si {$src, $dst|$dst, $src}",
564 [(set R32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
565 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
566 "cvttsd2si {$src, $dst|$dst, $src}",
567 [(set R32:$dst, (int_x86_sse2_cvttsd2si
568 (loadv2f64 addr:$src)))]>;
570 let isTwoAddress = 1 in {
571 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
572 (ops VR128:$dst, VR128:$src1, R32:$src2),
573 "cvtsi2ss {$src2, $dst|$dst, $src2}",
574 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
576 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
577 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
578 "cvtsi2ss {$src2, $dst|$dst, $src2}",
579 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
580 (loadi32 addr:$src2)))]>;
583 // Comparison instructions
584 let isTwoAddress = 1 in {
585 def CMPSSrr : SSI<0xC2, MRMSrcReg,
586 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
587 "cmp${cc}ss {$src, $dst|$dst, $src}",
589 def CMPSSrm : SSI<0xC2, MRMSrcMem,
590 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
591 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
592 def CMPSDrr : SDI<0xC2, MRMSrcReg,
593 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
594 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
595 def CMPSDrm : SDI<0xC2, MRMSrcMem,
596 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
597 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
600 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
601 "ucomiss {$src2, $src1|$src1, $src2}",
602 [(X86cmp FR32:$src1, FR32:$src2)]>;
603 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
604 "ucomiss {$src2, $src1|$src1, $src2}",
605 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
606 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
607 "ucomisd {$src2, $src1|$src1, $src2}",
608 [(X86cmp FR64:$src1, FR64:$src2)]>;
609 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
610 "ucomisd {$src2, $src1|$src1, $src2}",
611 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
613 // Aliases to match intrinsics which expect XMM operand(s).
614 let isTwoAddress = 1 in {
615 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
616 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
617 "cmp${cc}ss {$src, $dst|$dst, $src}",
618 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
619 VR128:$src, imm:$cc))]>;
620 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
621 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
622 "cmp${cc}ss {$src, $dst|$dst, $src}",
623 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
624 (load addr:$src), imm:$cc))]>;
625 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
626 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
627 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
628 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
629 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
630 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
633 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
634 "ucomiss {$src2, $src1|$src1, $src2}",
635 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
636 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
637 "ucomiss {$src2, $src1|$src1, $src2}",
638 [(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
639 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
640 "ucomisd {$src2, $src1|$src1, $src2}",
641 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
642 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
643 "ucomisd {$src2, $src1|$src1, $src2}",
644 [(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
646 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
647 "comiss {$src2, $src1|$src1, $src2}",
648 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
649 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
650 "comiss {$src2, $src1|$src1, $src2}",
651 [(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
652 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
653 "comisd {$src2, $src1|$src1, $src2}",
654 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
655 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
656 "comisd {$src2, $src1|$src1, $src2}",
657 [(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
659 // Aliases of packed instructions for scalar use. These all have names that
662 // Alias instructions that map fld0 to pxor for sse.
663 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
664 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
665 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
666 Requires<[HasSSE1]>, TB, OpSize;
667 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
668 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
669 Requires<[HasSSE2]>, TB, OpSize;
671 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
672 // Upper bits are disregarded.
673 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
674 "movaps {$src, $dst|$dst, $src}", []>;
675 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
676 "movapd {$src, $dst|$dst, $src}", []>;
678 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
679 // Upper bits are disregarded.
680 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
681 "movaps {$src, $dst|$dst, $src}",
682 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
683 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
684 "movapd {$src, $dst|$dst, $src}",
685 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
687 // Alias bitwise logical operations using SSE logical ops on packed FP values.
688 let isTwoAddress = 1 in {
689 let isCommutable = 1 in {
690 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
691 "andps {$src2, $dst|$dst, $src2}",
692 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
693 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
694 "andpd {$src2, $dst|$dst, $src2}",
695 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
696 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
697 "orps {$src2, $dst|$dst, $src2}", []>;
698 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
699 "orpd {$src2, $dst|$dst, $src2}", []>;
700 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
701 "xorps {$src2, $dst|$dst, $src2}",
702 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
703 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
704 "xorpd {$src2, $dst|$dst, $src2}",
705 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
707 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
708 "andps {$src2, $dst|$dst, $src2}",
709 [(set FR32:$dst, (X86fand FR32:$src1,
710 (X86loadpf32 addr:$src2)))]>;
711 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
712 "andpd {$src2, $dst|$dst, $src2}",
713 [(set FR64:$dst, (X86fand FR64:$src1,
714 (X86loadpf64 addr:$src2)))]>;
715 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
716 "orps {$src2, $dst|$dst, $src2}", []>;
717 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
718 "orpd {$src2, $dst|$dst, $src2}", []>;
719 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
720 "xorps {$src2, $dst|$dst, $src2}",
721 [(set FR32:$dst, (X86fxor FR32:$src1,
722 (X86loadpf32 addr:$src2)))]>;
723 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
724 "xorpd {$src2, $dst|$dst, $src2}",
725 [(set FR64:$dst, (X86fxor FR64:$src1,
726 (X86loadpf64 addr:$src2)))]>;
728 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
729 "andnps {$src2, $dst|$dst, $src2}", []>;
730 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
731 "andnps {$src2, $dst|$dst, $src2}", []>;
732 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
733 "andnpd {$src2, $dst|$dst, $src2}", []>;
734 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
735 "andnpd {$src2, $dst|$dst, $src2}", []>;
738 //===----------------------------------------------------------------------===//
739 // SSE packed FP Instructions
740 //===----------------------------------------------------------------------===//
742 // Some 'special' instructions
743 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
744 "#IMPLICIT_DEF $dst",
745 [(set VR128:$dst, (v4f32 (undef)))]>,
749 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
750 "movaps {$src, $dst|$dst, $src}", []>;
751 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
752 "movaps {$src, $dst|$dst, $src}",
753 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
754 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
755 "movapd {$src, $dst|$dst, $src}", []>;
756 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
757 "movapd {$src, $dst|$dst, $src}",
758 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
760 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
761 "movaps {$src, $dst|$dst, $src}",
762 [(store (v4f32 VR128:$src), addr:$dst)]>;
763 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
764 "movapd {$src, $dst|$dst, $src}",
765 [(store (v2f64 VR128:$src), addr:$dst)]>;
767 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
768 "movups {$src, $dst|$dst, $src}", []>;
769 def MOVUPSrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
770 "movups {$src, $dst|$dst, $src}",
771 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
772 def MOVUPSmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
773 "movups {$src, $dst|$dst, $src}",
774 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
775 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
776 "movupd {$src, $dst|$dst, $src}", []>;
777 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
778 "movupd {$src, $dst|$dst, $src}",
779 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
780 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
781 "movupd {$src, $dst|$dst, $src}",
782 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
784 let isTwoAddress = 1 in {
785 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
786 "movlps {$src2, $dst|$dst, $src2}",
788 (v4f32 (vector_shuffle VR128:$src1,
789 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
790 MOVLP_shuffle_mask)))]>;
791 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
792 "movlpd {$src2, $dst|$dst, $src2}",
794 (v2f64 (vector_shuffle VR128:$src1,
795 (scalar_to_vector (loadf64 addr:$src2)),
796 MOVLP_shuffle_mask)))]>;
797 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
798 "movhps {$src2, $dst|$dst, $src2}",
800 (v4f32 (vector_shuffle VR128:$src1,
801 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
802 MOVHP_shuffle_mask)))]>;
803 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
804 "movhpd {$src2, $dst|$dst, $src2}",
806 (v2f64 (vector_shuffle VR128:$src1,
807 (scalar_to_vector (loadf64 addr:$src2)),
808 MOVHP_shuffle_mask)))]>;
811 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
812 "movlps {$src, $dst|$dst, $src}",
813 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
814 (i32 0))), addr:$dst)]>;
815 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
816 "movlpd {$src, $dst|$dst, $src}",
817 [(store (f64 (vector_extract (v2f64 VR128:$src),
818 (i32 0))), addr:$dst)]>;
820 // v2f64 extract element 1 is always custom lowered to unpack high to low
821 // and extract element 0 so the non-store version isn't too horrible.
822 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
823 "movhps {$src, $dst|$dst, $src}",
824 [(store (f64 (vector_extract
825 (v2f64 (vector_shuffle
826 (bc_v2f64 (v4f32 VR128:$src)), (undef),
827 UNPCKH_shuffle_mask)), (i32 0))),
829 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
830 "movhpd {$src, $dst|$dst, $src}",
831 [(store (f64 (vector_extract
832 (v2f64 (vector_shuffle VR128:$src, (undef),
833 UNPCKH_shuffle_mask)), (i32 0))),
836 let isTwoAddress = 1 in {
837 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
838 "movlhps {$src2, $dst|$dst, $src2}",
840 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
841 MOVLHPS_shuffle_mask)))]>;
843 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
844 "movhlps {$src2, $dst|$dst, $src2}",
846 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
847 MOVHLPS_shuffle_mask)))]>;
850 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
851 "movshdup {$src, $dst|$dst, $src}",
852 [(set VR128:$dst, (v4f32 (vector_shuffle
854 MOVSHDUP_shuffle_mask)))]>;
855 def MOVSHDUPrm : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
856 "movshdup {$src, $dst|$dst, $src}",
857 [(set VR128:$dst, (v4f32 (vector_shuffle
858 (loadv4f32 addr:$src), (undef),
859 MOVSHDUP_shuffle_mask)))]>;
861 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
862 "movsldup {$src, $dst|$dst, $src}",
863 [(set VR128:$dst, (v4f32 (vector_shuffle
865 MOVSLDUP_shuffle_mask)))]>;
866 def MOVSLDUPrm : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
867 "movsldup {$src, $dst|$dst, $src}",
868 [(set VR128:$dst, (v4f32 (vector_shuffle
869 (loadv4f32 addr:$src), (undef),
870 MOVSLDUP_shuffle_mask)))]>;
872 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
873 "movddup {$src, $dst|$dst, $src}",
874 [(set VR128:$dst, (v2f64 (vector_shuffle
876 SSE_splat_v2_mask)))]>;
877 def MOVDDUPrm : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
878 "movddup {$src, $dst|$dst, $src}",
879 [(set VR128:$dst, (v2f64 (vector_shuffle
880 (loadv2f64 addr:$src), (undef),
881 SSE_splat_v2_mask)))]>;
883 // SSE2 instructions without OpSize prefix
884 def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
885 "cvtdq2ps {$src, $dst|$dst, $src}",
886 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
887 TB, Requires<[HasSSE2]>;
888 def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
889 "cvtdq2ps {$src, $dst|$dst, $src}",
890 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
891 (bc_v4i32 (loadv2i64 addr:$src))))]>,
892 TB, Requires<[HasSSE2]>;
894 // SSE2 instructions with XS prefix
895 def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
896 "cvtdq2pd {$src, $dst|$dst, $src}",
897 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
898 XS, Requires<[HasSSE2]>;
899 def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
900 "cvtdq2pd {$src, $dst|$dst, $src}",
901 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
902 (bc_v4i32 (loadv2i64 addr:$src))))]>,
903 XS, Requires<[HasSSE2]>;
905 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
906 "cvtps2dq {$src, $dst|$dst, $src}",
907 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
908 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
909 "cvtps2dq {$src, $dst|$dst, $src}",
910 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
911 (loadv4f32 addr:$src)))]>;
912 // SSE2 packed instructions with XS prefix
913 def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
914 "cvttps2dq {$src, $dst|$dst, $src}",
915 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
916 XS, Requires<[HasSSE2]>;
917 def CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
918 "cvttps2dq {$src, $dst|$dst, $src}",
919 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
920 (loadv4f32 addr:$src)))]>,
921 XS, Requires<[HasSSE2]>;
923 // SSE2 packed instructions with XD prefix
924 def CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
925 "cvtpd2dq {$src, $dst|$dst, $src}",
926 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
927 XD, Requires<[HasSSE2]>;
928 def CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
929 "cvtpd2dq {$src, $dst|$dst, $src}",
930 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
931 (loadv2f64 addr:$src)))]>,
932 XD, Requires<[HasSSE2]>;
933 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
934 "cvttpd2dq {$src, $dst|$dst, $src}",
935 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
936 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
937 "cvttpd2dq {$src, $dst|$dst, $src}",
938 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
939 (loadv2f64 addr:$src)))]>;
941 // SSE2 instructions without OpSize prefix
942 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
943 "cvtps2pd {$src, $dst|$dst, $src}",
944 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
945 TB, Requires<[HasSSE2]>;
946 def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
947 "cvtps2pd {$src, $dst|$dst, $src}",
948 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
949 (loadv4f32 addr:$src)))]>,
950 TB, Requires<[HasSSE2]>;
952 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
953 "cvtpd2ps {$src, $dst|$dst, $src}",
954 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
955 def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
956 "cvtpd2ps {$src, $dst|$dst, $src}",
957 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
958 (loadv2f64 addr:$src)))]>;
960 // Match intrinsics which expect XMM operand(s).
961 // Aliases for intrinsics
962 let isTwoAddress = 1 in {
963 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
964 (ops VR128:$dst, VR128:$src1, R32:$src2),
965 "cvtsi2sd {$src2, $dst|$dst, $src2}",
966 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
968 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
969 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
970 "cvtsi2sd {$src2, $dst|$dst, $src2}",
971 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
972 (loadi32 addr:$src2)))]>;
973 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
974 (ops VR128:$dst, VR128:$src1, VR128:$src2),
975 "cvtsd2ss {$src2, $dst|$dst, $src2}",
976 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
978 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
979 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
980 "cvtsd2ss {$src2, $dst|$dst, $src2}",
981 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
982 (loadv2f64 addr:$src2)))]>;
983 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
984 (ops VR128:$dst, VR128:$src1, VR128:$src2),
985 "cvtss2sd {$src2, $dst|$dst, $src2}",
986 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
989 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
990 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
991 "cvtss2sd {$src2, $dst|$dst, $src2}",
992 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
993 (loadv4f32 addr:$src2)))]>, XS,
998 let isTwoAddress = 1 in {
999 let isCommutable = 1 in {
1000 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1001 "addps {$src2, $dst|$dst, $src2}",
1002 [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
1003 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1004 "addpd {$src2, $dst|$dst, $src2}",
1005 [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
1006 def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1007 "mulps {$src2, $dst|$dst, $src2}",
1008 [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
1009 def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1010 "mulpd {$src2, $dst|$dst, $src2}",
1011 [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
1014 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1015 "addps {$src2, $dst|$dst, $src2}",
1016 [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
1017 (load addr:$src2))))]>;
1018 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1019 "addpd {$src2, $dst|$dst, $src2}",
1020 [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
1021 (load addr:$src2))))]>;
1022 def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1023 "mulps {$src2, $dst|$dst, $src2}",
1024 [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
1025 (load addr:$src2))))]>;
1026 def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1027 "mulpd {$src2, $dst|$dst, $src2}",
1028 [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
1029 (load addr:$src2))))]>;
1031 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1032 "divps {$src2, $dst|$dst, $src2}",
1033 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
1034 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1035 "divps {$src2, $dst|$dst, $src2}",
1036 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
1037 (load addr:$src2))))]>;
1038 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1039 "divpd {$src2, $dst|$dst, $src2}",
1040 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
1041 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1042 "divpd {$src2, $dst|$dst, $src2}",
1043 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
1044 (load addr:$src2))))]>;
1046 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1047 "subps {$src2, $dst|$dst, $src2}",
1048 [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
1049 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1050 "subps {$src2, $dst|$dst, $src2}",
1051 [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
1052 (load addr:$src2))))]>;
1053 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1054 "subpd {$src2, $dst|$dst, $src2}",
1055 [(set VR128:$dst, (v2f64 (fsub VR128:$src1, VR128:$src2)))]>;
1056 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1057 "subpd {$src2, $dst|$dst, $src2}",
1058 [(set VR128:$dst, (v2f64 (fsub VR128:$src1,
1059 (load addr:$src2))))]>;
1061 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
1062 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1063 "addsubps {$src2, $dst|$dst, $src2}",
1064 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1066 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
1067 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1068 "addsubps {$src2, $dst|$dst, $src2}",
1069 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1070 (loadv4f32 addr:$src2)))]>;
1071 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
1072 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1073 "addsubpd {$src2, $dst|$dst, $src2}",
1074 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1076 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
1077 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1078 "addsubpd {$src2, $dst|$dst, $src2}",
1079 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1080 (loadv2f64 addr:$src2)))]>;
1083 def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
1084 int_x86_sse_sqrt_ps>;
1085 def SQRTPSm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}",
1086 int_x86_sse_sqrt_ps>;
1087 def SQRTPDr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1088 int_x86_sse2_sqrt_pd>;
1089 def SQRTPDm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1090 int_x86_sse2_sqrt_pd>;
1092 def RSQRTPSr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1093 int_x86_sse_rsqrt_ps>;
1094 def RSQRTPSm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1095 int_x86_sse_rsqrt_ps>;
1096 def RCPPSr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}",
1097 int_x86_sse_rcp_ps>;
1098 def RCPPSm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}",
1099 int_x86_sse_rcp_ps>;
1101 let isTwoAddress = 1 in {
1102 def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1103 int_x86_sse_max_ps>;
1104 def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1105 int_x86_sse_max_ps>;
1106 def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1107 int_x86_sse2_max_pd>;
1108 def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1109 int_x86_sse2_max_pd>;
1110 def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}",
1111 int_x86_sse_min_ps>;
1112 def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}",
1113 int_x86_sse_min_ps>;
1114 def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1115 int_x86_sse2_min_pd>;
1116 def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1117 int_x86_sse2_min_pd>;
1121 let isTwoAddress = 1 in {
1122 let isCommutable = 1 in {
1123 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1124 "andps {$src2, $dst|$dst, $src2}",
1125 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1126 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1127 "andpd {$src2, $dst|$dst, $src2}",
1129 (and (bc_v2i64 (v2f64 VR128:$src1)),
1130 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1131 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1132 "orps {$src2, $dst|$dst, $src2}",
1133 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1134 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1135 "orpd {$src2, $dst|$dst, $src2}",
1137 (or (bc_v2i64 (v2f64 VR128:$src1)),
1138 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1139 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1140 "xorps {$src2, $dst|$dst, $src2}",
1141 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1142 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1143 "xorpd {$src2, $dst|$dst, $src2}",
1145 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1146 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1148 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1149 "andps {$src2, $dst|$dst, $src2}",
1150 [(set VR128:$dst, (and VR128:$src1,
1151 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1152 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1153 "andpd {$src2, $dst|$dst, $src2}",
1155 (and (bc_v2i64 (v2f64 VR128:$src1)),
1156 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1157 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1158 "orps {$src2, $dst|$dst, $src2}",
1159 [(set VR128:$dst, (or VR128:$src1,
1160 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1161 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1162 "orpd {$src2, $dst|$dst, $src2}",
1164 (or (bc_v2i64 (v2f64 VR128:$src1)),
1165 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1166 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1167 "xorps {$src2, $dst|$dst, $src2}",
1168 [(set VR128:$dst, (xor VR128:$src1,
1169 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1170 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1171 "xorpd {$src2, $dst|$dst, $src2}",
1173 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1174 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1175 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1176 "andnps {$src2, $dst|$dst, $src2}",
1177 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1178 (bc_v2i64 (v4i32 immAllOnesV))),
1180 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1181 "andnps {$src2, $dst|$dst, $src2}",
1182 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1183 (bc_v2i64 (v4i32 immAllOnesV))),
1184 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1185 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1186 "andnpd {$src2, $dst|$dst, $src2}",
1188 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1189 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1190 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1191 "andnpd {$src2, $dst|$dst, $src2}",
1193 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1194 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1197 let isTwoAddress = 1 in {
1198 def CMPPSrr : PSIi8<0xC2, MRMSrcReg,
1199 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1200 "cmp${cc}ps {$src, $dst|$dst, $src}",
1201 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1202 VR128:$src, imm:$cc))]>;
1203 def CMPPSrm : PSIi8<0xC2, MRMSrcMem,
1204 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1205 "cmp${cc}ps {$src, $dst|$dst, $src}",
1206 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1207 (load addr:$src), imm:$cc))]>;
1208 def CMPPDrr : PDIi8<0xC2, MRMSrcReg,
1209 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1210 "cmp${cc}pd {$src, $dst|$dst, $src}",
1211 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1212 VR128:$src, imm:$cc))]>;
1213 def CMPPDrm : PDIi8<0xC2, MRMSrcMem,
1214 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1215 "cmp${cc}pd {$src, $dst|$dst, $src}",
1216 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1217 (load addr:$src), imm:$cc))]>;
1220 // Shuffle and unpack instructions
1221 let isTwoAddress = 1 in {
1222 def SHUFPSrr : PSIi8<0xC6, MRMSrcReg,
1223 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1224 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1225 [(set VR128:$dst, (v4f32 (vector_shuffle
1226 VR128:$src1, VR128:$src2,
1227 SHUFP_shuffle_mask:$src3)))]>;
1228 def SHUFPSrm : PSIi8<0xC6, MRMSrcMem,
1229 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1230 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1231 [(set VR128:$dst, (v4f32 (vector_shuffle
1232 VR128:$src1, (load addr:$src2),
1233 SHUFP_shuffle_mask:$src3)))]>;
1234 def SHUFPDrr : PDIi8<0xC6, MRMSrcReg,
1235 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1236 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1237 [(set VR128:$dst, (v2f64 (vector_shuffle
1238 VR128:$src1, VR128:$src2,
1239 SHUFP_shuffle_mask:$src3)))]>;
1240 def SHUFPDrm : PDIi8<0xC6, MRMSrcMem,
1241 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1242 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1243 [(set VR128:$dst, (v2f64 (vector_shuffle
1244 VR128:$src1, (load addr:$src2),
1245 SHUFP_shuffle_mask:$src3)))]>;
1247 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1248 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1249 "unpckhps {$src2, $dst|$dst, $src2}",
1250 [(set VR128:$dst, (v4f32 (vector_shuffle
1251 VR128:$src1, VR128:$src2,
1252 UNPCKH_shuffle_mask)))]>;
1253 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1254 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1255 "unpckhps {$src2, $dst|$dst, $src2}",
1256 [(set VR128:$dst, (v4f32 (vector_shuffle
1257 VR128:$src1, (load addr:$src2),
1258 UNPCKH_shuffle_mask)))]>;
1259 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1260 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1261 "unpckhpd {$src2, $dst|$dst, $src2}",
1262 [(set VR128:$dst, (v2f64 (vector_shuffle
1263 VR128:$src1, VR128:$src2,
1264 UNPCKH_shuffle_mask)))]>;
1265 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1266 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1267 "unpckhpd {$src2, $dst|$dst, $src2}",
1268 [(set VR128:$dst, (v2f64 (vector_shuffle
1269 VR128:$src1, (load addr:$src2),
1270 UNPCKH_shuffle_mask)))]>;
1272 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1273 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1274 "unpcklps {$src2, $dst|$dst, $src2}",
1275 [(set VR128:$dst, (v4f32 (vector_shuffle
1276 VR128:$src1, VR128:$src2,
1277 UNPCKL_shuffle_mask)))]>;
1278 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1279 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1280 "unpcklps {$src2, $dst|$dst, $src2}",
1281 [(set VR128:$dst, (v4f32 (vector_shuffle
1282 VR128:$src1, (load addr:$src2),
1283 UNPCKL_shuffle_mask)))]>;
1284 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1285 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1286 "unpcklpd {$src2, $dst|$dst, $src2}",
1287 [(set VR128:$dst, (v2f64 (vector_shuffle
1288 VR128:$src1, VR128:$src2,
1289 UNPCKL_shuffle_mask)))]>;
1290 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1291 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1292 "unpcklpd {$src2, $dst|$dst, $src2}",
1293 [(set VR128:$dst, (v2f64 (vector_shuffle
1294 VR128:$src1, (load addr:$src2),
1295 UNPCKL_shuffle_mask)))]>;
1299 let isTwoAddress = 1 in {
1300 def HADDPSrr : S3D_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1301 int_x86_sse3_hadd_ps>;
1302 def HADDPSrm : S3D_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1303 int_x86_sse3_hadd_ps>;
1304 def HADDPDrr : S3_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1305 int_x86_sse3_hadd_pd>;
1306 def HADDPDrm : S3_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1307 int_x86_sse3_hadd_pd>;
1308 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1309 int_x86_sse3_hsub_ps>;
1310 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1311 int_x86_sse3_hsub_ps>;
1312 def HSUBPDrr : S3_Intrr<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1313 int_x86_sse3_hsub_pd>;
1314 def HSUBPDrm : S3_Intrm<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1315 int_x86_sse3_hsub_pd>;
1318 //===----------------------------------------------------------------------===//
1319 // SSE integer instructions
1320 //===----------------------------------------------------------------------===//
1322 // Move Instructions
1323 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1324 "movdqa {$src, $dst|$dst, $src}", []>;
1325 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1326 "movdqa {$src, $dst|$dst, $src}",
1327 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1328 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1329 "movdqa {$src, $dst|$dst, $src}",
1330 [(store (v2i64 VR128:$src), addr:$dst)]>;
1331 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1332 "movdqu {$src, $dst|$dst, $src}",
1333 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1334 XS, Requires<[HasSSE2]>;
1335 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1336 "movdqu {$src, $dst|$dst, $src}",
1337 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1338 XS, Requires<[HasSSE2]>;
1339 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1340 "lddqu {$src, $dst|$dst, $src}",
1341 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
1343 // 128-bit Integer Arithmetic
1344 let isTwoAddress = 1 in {
1345 let isCommutable = 1 in {
1346 def PADDBrr : PDI<0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1347 "paddb {$src2, $dst|$dst, $src2}",
1348 [(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))]>;
1349 def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1350 "paddw {$src2, $dst|$dst, $src2}",
1351 [(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))]>;
1352 def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1353 "paddd {$src2, $dst|$dst, $src2}",
1354 [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
1356 def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1357 "paddq {$src2, $dst|$dst, $src2}",
1358 [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
1360 def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1361 "paddb {$src2, $dst|$dst, $src2}",
1362 [(set VR128:$dst, (v16i8 (add VR128:$src1,
1363 (load addr:$src2))))]>;
1364 def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1365 "paddw {$src2, $dst|$dst, $src2}",
1366 [(set VR128:$dst, (v8i16 (add VR128:$src1,
1367 (load addr:$src2))))]>;
1368 def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1369 "paddd {$src2, $dst|$dst, $src2}",
1370 [(set VR128:$dst, (v4i32 (add VR128:$src1,
1371 (load addr:$src2))))]>;
1372 def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1373 "paddd {$src2, $dst|$dst, $src2}",
1374 [(set VR128:$dst, (v2i64 (add VR128:$src1,
1375 (load addr:$src2))))]>;
1377 let isCommutable = 1 in {
1378 def PADDSBrr : PDI<0xEC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1379 "paddsb {$src2, $dst|$dst, $src2}",
1380 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1382 def PADDSWrr : PDI<0xED, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1383 "paddsw {$src2, $dst|$dst, $src2}",
1384 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1386 def PADDUSBrr : PDI<0xDC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1387 "paddusb {$src2, $dst|$dst, $src2}",
1388 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1390 def PADDUSWrr : PDI<0xDD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1391 "paddusw {$src2, $dst|$dst, $src2}",
1392 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1395 def PADDSBrm : PDI<0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1396 "paddsb {$src2, $dst|$dst, $src2}",
1397 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1398 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1399 def PADDSWrm : PDI<0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1400 "paddsw {$src2, $dst|$dst, $src2}",
1401 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1402 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1403 def PADDUSBrm : PDI<0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1404 "paddusb {$src2, $dst|$dst, $src2}",
1405 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1406 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1407 def PADDUSWrm : PDI<0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1408 "paddusw {$src2, $dst|$dst, $src2}",
1409 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1410 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1413 def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1414 "psubb {$src2, $dst|$dst, $src2}",
1415 [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
1416 def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1417 "psubw {$src2, $dst|$dst, $src2}",
1418 [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))]>;
1419 def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1420 "psubd {$src2, $dst|$dst, $src2}",
1421 [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
1422 def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1423 "psubq {$src2, $dst|$dst, $src2}",
1424 [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
1426 def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1427 "psubb {$src2, $dst|$dst, $src2}",
1428 [(set VR128:$dst, (v16i8 (sub VR128:$src1,
1429 (load addr:$src2))))]>;
1430 def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1431 "psubw {$src2, $dst|$dst, $src2}",
1432 [(set VR128:$dst, (v8i16 (sub VR128:$src1,
1433 (load addr:$src2))))]>;
1434 def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1435 "psubd {$src2, $dst|$dst, $src2}",
1436 [(set VR128:$dst, (v4i32 (sub VR128:$src1,
1437 (load addr:$src2))))]>;
1438 def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1439 "psubd {$src2, $dst|$dst, $src2}",
1440 [(set VR128:$dst, (v2i64 (sub VR128:$src1,
1441 (load addr:$src2))))]>;
1443 def PSUBSBrr : PDI<0xE8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1444 "psubsb {$src2, $dst|$dst, $src2}",
1445 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1447 def PSUBSWrr : PDI<0xE9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1448 "psubsw {$src2, $dst|$dst, $src2}",
1449 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1451 def PSUBUSBrr : PDI<0xD8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1452 "psubusb {$src2, $dst|$dst, $src2}",
1453 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1455 def PSUBUSWrr : PDI<0xD9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1456 "psubusw {$src2, $dst|$dst, $src2}",
1457 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1460 def PSUBSBrm : PDI<0xE8, MRMSrcMem,
1461 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1462 "psubsb {$src2, $dst|$dst, $src2}",
1463 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1464 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1465 def PSUBSWrm : PDI<0xE9, MRMSrcMem,
1466 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1467 "psubsw {$src2, $dst|$dst, $src2}",
1468 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1469 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1470 def PSUBUSBrm : PDI<0xD8, MRMSrcMem,
1471 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1472 "psubusb {$src2, $dst|$dst, $src2}",
1473 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1474 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1475 def PSUBUSWrm : PDI<0xD9, MRMSrcMem,
1476 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1477 "psubusw {$src2, $dst|$dst, $src2}",
1478 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1479 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1481 let isCommutable = 1 in {
1482 def PMULHUWrr : PDI<0xE4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1483 "pmulhuw {$src2, $dst|$dst, $src2}",
1484 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1486 def PMULHWrr : PDI<0xE5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1487 "pmulhw {$src2, $dst|$dst, $src2}",
1488 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1490 def PMULLWrr : PDI<0xD5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1491 "pmullw {$src2, $dst|$dst, $src2}",
1492 [(set VR128:$dst, (v8i16 (mul VR128:$src1, VR128:$src2)))]>;
1493 def PMULUDQrr : PDI<0xF4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1494 "pmuludq {$src2, $dst|$dst, $src2}",
1495 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1498 def PMULHUWrm : PDI<0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1499 "pmulhuw {$src2, $dst|$dst, $src2}",
1500 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1501 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1502 def PMULHWrm : PDI<0xE5, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1503 "pmulhw {$src2, $dst|$dst, $src2}",
1504 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1505 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1506 def PMULLWrm : PDI<0xD5, MRMSrcMem,
1507 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1508 "pmullw {$src2, $dst|$dst, $src2}",
1509 [(set VR128:$dst, (v8i16 (mul VR128:$src1,
1510 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1511 def PMULUDQrm : PDI<0xF4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1512 "pmuludq {$src2, $dst|$dst, $src2}",
1513 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1514 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1516 let isCommutable = 1 in {
1517 def PMADDWDrr : PDI<0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1518 "pmaddwd {$src2, $dst|$dst, $src2}",
1519 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1522 def PMADDWDrm : PDI<0xF5, MRMSrcMem,
1523 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1524 "pmaddwd {$src2, $dst|$dst, $src2}",
1525 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1526 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1528 let isCommutable = 1 in {
1529 def PAVGBrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1530 "pavgb {$src2, $dst|$dst, $src2}",
1531 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1533 def PAVGWrr : PDI<0xE3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1534 "pavgw {$src2, $dst|$dst, $src2}",
1535 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1538 def PAVGBrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1539 "pavgb {$src2, $dst|$dst, $src2}",
1540 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1541 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1542 def PAVGWrm : PDI<0xE3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1543 "pavgw {$src2, $dst|$dst, $src2}",
1544 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1545 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1547 let isCommutable = 1 in {
1548 def PMAXUBrr : PDI<0xDE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1549 "pmaxub {$src2, $dst|$dst, $src2}",
1550 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1552 def PMAXSWrr : PDI<0xEE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1553 "pmaxsw {$src2, $dst|$dst, $src2}",
1554 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1557 def PMAXUBrm : PDI<0xDE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1558 "pmaxub {$src2, $dst|$dst, $src2}",
1559 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1560 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1561 def PMAXSWrm : PDI<0xEE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1562 "pmaxsw {$src2, $dst|$dst, $src2}",
1563 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1564 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1566 let isCommutable = 1 in {
1567 def PMINUBrr : PDI<0xDA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1568 "pminub {$src2, $dst|$dst, $src2}",
1569 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1571 def PMINSWrr : PDI<0xEA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1572 "pminsw {$src2, $dst|$dst, $src2}",
1573 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1576 def PMINUBrm : PDI<0xDA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1577 "pminub {$src2, $dst|$dst, $src2}",
1578 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1579 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1580 def PMINSWrm : PDI<0xEA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1581 "pminsw {$src2, $dst|$dst, $src2}",
1582 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1583 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1586 let isCommutable = 1 in {
1587 def PSADBWrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1588 "psadbw {$src2, $dst|$dst, $src2}",
1589 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1592 def PSADBWrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1593 "psadbw {$src2, $dst|$dst, $src2}",
1594 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1595 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1598 let isTwoAddress = 1 in {
1599 def PSLLWrr : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1600 "psllw {$src2, $dst|$dst, $src2}",
1601 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1603 def PSLLWrm : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1604 "psllw {$src2, $dst|$dst, $src2}",
1605 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1606 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1607 def PSLLWri : PDIi8<0x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1608 "psllw {$src2, $dst|$dst, $src2}",
1609 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1610 (scalar_to_vector (i32 imm:$src2))))]>;
1611 def PSLLDrr : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1612 "pslld {$src2, $dst|$dst, $src2}",
1613 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1615 def PSLLDrm : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1616 "pslld {$src2, $dst|$dst, $src2}",
1617 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1618 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1619 def PSLLDri : PDIi8<0x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1620 "pslld {$src2, $dst|$dst, $src2}",
1621 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1622 (scalar_to_vector (i32 imm:$src2))))]>;
1623 def PSLLQrr : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1624 "psllq {$src2, $dst|$dst, $src2}",
1625 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1627 def PSLLQrm : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1628 "psllq {$src2, $dst|$dst, $src2}",
1629 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1630 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1631 def PSLLQri : PDIi8<0x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1632 "psllq {$src2, $dst|$dst, $src2}",
1633 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1634 (scalar_to_vector (i32 imm:$src2))))]>;
1635 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1636 "pslldq {$src2, $dst|$dst, $src2}", []>;
1638 def PSRLWrr : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1639 "psrlw {$src2, $dst|$dst, $src2}",
1640 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1642 def PSRLWrm : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1643 "psrlw {$src2, $dst|$dst, $src2}",
1644 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1645 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1646 def PSRLWri : PDIi8<0x71, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1647 "psrlw {$src2, $dst|$dst, $src2}",
1648 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1649 (scalar_to_vector (i32 imm:$src2))))]>;
1650 def PSRLDrr : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1651 "psrld {$src2, $dst|$dst, $src2}",
1652 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1654 def PSRLDrm : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1655 "psrld {$src2, $dst|$dst, $src2}",
1656 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1657 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1658 def PSRLDri : PDIi8<0x72, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1659 "psrld {$src2, $dst|$dst, $src2}",
1660 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1661 (scalar_to_vector (i32 imm:$src2))))]>;
1662 def PSRLQrr : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1663 "psrlq {$src2, $dst|$dst, $src2}",
1664 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1666 def PSRLQrm : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1667 "psrlq {$src2, $dst|$dst, $src2}",
1668 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1669 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1670 def PSRLQri : PDIi8<0x73, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1671 "psrlq {$src2, $dst|$dst, $src2}",
1672 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1673 (scalar_to_vector (i32 imm:$src2))))]>;
1674 def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1675 "psrldq {$src2, $dst|$dst, $src2}", []>;
1677 def PSRAWrr : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1678 "psraw {$src2, $dst|$dst, $src2}",
1679 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1681 def PSRAWrm : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1682 "psraw {$src2, $dst|$dst, $src2}",
1683 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1684 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1685 def PSRAWri : PDIi8<0x71, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1686 "psraw {$src2, $dst|$dst, $src2}",
1687 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1688 (scalar_to_vector (i32 imm:$src2))))]>;
1689 def PSRADrr : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1690 "psrad {$src2, $dst|$dst, $src2}",
1691 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1693 def PSRADrm : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1694 "psrad {$src2, $dst|$dst, $src2}",
1695 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1696 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1697 def PSRADri : PDIi8<0x72, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1698 "psrad {$src2, $dst|$dst, $src2}",
1699 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1700 (scalar_to_vector (i32 imm:$src2))))]>;
1704 let isTwoAddress = 1 in {
1705 let isCommutable = 1 in {
1706 def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1707 "pand {$src2, $dst|$dst, $src2}",
1708 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1709 def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1710 "por {$src2, $dst|$dst, $src2}",
1711 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1712 def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1713 "pxor {$src2, $dst|$dst, $src2}",
1714 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1717 def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1718 "pand {$src2, $dst|$dst, $src2}",
1719 [(set VR128:$dst, (v2i64 (and VR128:$src1,
1720 (load addr:$src2))))]>;
1721 def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1722 "por {$src2, $dst|$dst, $src2}",
1723 [(set VR128:$dst, (v2i64 (or VR128:$src1,
1724 (load addr:$src2))))]>;
1725 def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1726 "pxor {$src2, $dst|$dst, $src2}",
1727 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
1728 (load addr:$src2))))]>;
1730 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1731 "pandn {$src2, $dst|$dst, $src2}",
1732 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1735 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1736 "pandn {$src2, $dst|$dst, $src2}",
1737 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1738 (load addr:$src2))))]>;
1741 // SSE2 Integer comparison
1742 let isTwoAddress = 1 in {
1743 def PCMPEQBrr : PDI<0x74, MRMSrcReg,
1744 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1745 "pcmpeqb {$src2, $dst|$dst, $src2}",
1746 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1748 def PCMPEQBrm : PDI<0x74, MRMSrcReg,
1749 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1750 "pcmpeqb {$src2, $dst|$dst, $src2}",
1751 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1752 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1753 def PCMPEQWrr : PDI<0x75, MRMSrcReg,
1754 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1755 "pcmpeqw {$src2, $dst|$dst, $src2}",
1756 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1758 def PCMPEQWrm : PDI<0x75, MRMSrcReg,
1759 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1760 "pcmpeqw {$src2, $dst|$dst, $src2}",
1761 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1762 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1763 def PCMPEQDrr : PDI<0x76, MRMSrcReg,
1764 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1765 "pcmpeqd {$src2, $dst|$dst, $src2}",
1766 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1768 def PCMPEQDrm : PDI<0x76, MRMSrcReg,
1769 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1770 "pcmpeqd {$src2, $dst|$dst, $src2}",
1771 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1772 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1774 def PCMPGTBrr : PDI<0x64, MRMSrcReg,
1775 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1776 "pcmpgtb {$src2, $dst|$dst, $src2}",
1777 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1779 def PCMPGTBrm : PDI<0x64, MRMSrcReg,
1780 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1781 "pcmpgtb {$src2, $dst|$dst, $src2}",
1782 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1783 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1784 def PCMPGTWrr : PDI<0x65, MRMSrcReg,
1785 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1786 "pcmpgtw {$src2, $dst|$dst, $src2}",
1787 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1789 def PCMPGTWrm : PDI<0x65, MRMSrcReg,
1790 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1791 "pcmpgtw {$src2, $dst|$dst, $src2}",
1792 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1793 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1794 def PCMPGTDrr : PDI<0x66, MRMSrcReg,
1795 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1796 "pcmpgtd {$src2, $dst|$dst, $src2}",
1797 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1799 def PCMPGTDrm : PDI<0x66, MRMSrcReg,
1800 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1801 "pcmpgtd {$src2, $dst|$dst, $src2}",
1802 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1803 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1806 // Pack instructions
1807 let isTwoAddress = 1 in {
1808 def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1810 "packsswb {$src2, $dst|$dst, $src2}",
1811 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1814 def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1816 "packsswb {$src2, $dst|$dst, $src2}",
1817 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1819 (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
1820 def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1822 "packssdw {$src2, $dst|$dst, $src2}",
1823 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1826 def PACKSSDWrm : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1828 "packssdw {$src2, $dst|$dst, $src2}",
1829 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1831 (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
1832 def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1834 "packuswb {$src2, $dst|$dst, $src2}",
1835 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1838 def PACKUSWBrm : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1840 "packuswb {$src2, $dst|$dst, $src2}",
1841 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1843 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1846 // Shuffle and unpack instructions
1847 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1848 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1849 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1850 [(set VR128:$dst, (v4i32 (vector_shuffle
1851 VR128:$src1, (undef),
1852 PSHUFD_shuffle_mask:$src2)))]>;
1853 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1854 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1855 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1856 [(set VR128:$dst, (v4i32 (vector_shuffle
1857 (bc_v4i32 (loadv2i64 addr:$src1)),
1859 PSHUFD_shuffle_mask:$src2)))]>;
1861 // SSE2 with ImmT == Imm8 and XS prefix.
1862 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1863 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1864 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1865 [(set VR128:$dst, (v8i16 (vector_shuffle
1866 VR128:$src1, (undef),
1867 PSHUFHW_shuffle_mask:$src2)))]>,
1868 XS, Requires<[HasSSE2]>;
1869 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1870 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1871 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1872 [(set VR128:$dst, (v8i16 (vector_shuffle
1873 (bc_v8i16 (loadv2i64 addr:$src1)),
1875 PSHUFHW_shuffle_mask:$src2)))]>,
1876 XS, Requires<[HasSSE2]>;
1878 // SSE2 with ImmT == Imm8 and XD prefix.
1879 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1880 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1881 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1882 [(set VR128:$dst, (v8i16 (vector_shuffle
1883 VR128:$src1, (undef),
1884 PSHUFLW_shuffle_mask:$src2)))]>,
1885 XD, Requires<[HasSSE2]>;
1886 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1887 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1888 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1889 [(set VR128:$dst, (v8i16 (vector_shuffle
1890 (bc_v8i16 (loadv2i64 addr:$src1)),
1892 PSHUFLW_shuffle_mask:$src2)))]>,
1893 XD, Requires<[HasSSE2]>;
1895 let isTwoAddress = 1 in {
1896 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1897 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1898 "punpcklbw {$src2, $dst|$dst, $src2}",
1900 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1901 UNPCKL_shuffle_mask)))]>;
1902 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1903 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1904 "punpcklbw {$src2, $dst|$dst, $src2}",
1906 (v16i8 (vector_shuffle VR128:$src1,
1907 (bc_v16i8 (loadv2i64 addr:$src2)),
1908 UNPCKL_shuffle_mask)))]>;
1909 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1910 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1911 "punpcklwd {$src2, $dst|$dst, $src2}",
1913 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1914 UNPCKL_shuffle_mask)))]>;
1915 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1916 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1917 "punpcklwd {$src2, $dst|$dst, $src2}",
1919 (v8i16 (vector_shuffle VR128:$src1,
1920 (bc_v8i16 (loadv2i64 addr:$src2)),
1921 UNPCKL_shuffle_mask)))]>;
1922 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1923 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1924 "punpckldq {$src2, $dst|$dst, $src2}",
1926 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1927 UNPCKL_shuffle_mask)))]>;
1928 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1929 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1930 "punpckldq {$src2, $dst|$dst, $src2}",
1932 (v4i32 (vector_shuffle VR128:$src1,
1933 (bc_v4i32 (loadv2i64 addr:$src2)),
1934 UNPCKL_shuffle_mask)))]>;
1935 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1936 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1937 "punpcklqdq {$src2, $dst|$dst, $src2}",
1939 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1940 UNPCKL_shuffle_mask)))]>;
1941 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1942 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1943 "punpcklqdq {$src2, $dst|$dst, $src2}",
1945 (v2i64 (vector_shuffle VR128:$src1,
1946 (loadv2i64 addr:$src2),
1947 UNPCKL_shuffle_mask)))]>;
1949 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1950 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1951 "punpckhbw {$src2, $dst|$dst, $src2}",
1953 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1954 UNPCKH_shuffle_mask)))]>;
1955 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1956 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1957 "punpckhbw {$src2, $dst|$dst, $src2}",
1959 (v16i8 (vector_shuffle VR128:$src1,
1960 (bc_v16i8 (loadv2i64 addr:$src2)),
1961 UNPCKH_shuffle_mask)))]>;
1962 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1963 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1964 "punpckhwd {$src2, $dst|$dst, $src2}",
1966 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1967 UNPCKH_shuffle_mask)))]>;
1968 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1969 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1970 "punpckhwd {$src2, $dst|$dst, $src2}",
1972 (v8i16 (vector_shuffle VR128:$src1,
1973 (bc_v8i16 (loadv2i64 addr:$src2)),
1974 UNPCKH_shuffle_mask)))]>;
1975 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1976 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1977 "punpckhdq {$src2, $dst|$dst, $src2}",
1979 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1980 UNPCKH_shuffle_mask)))]>;
1981 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1982 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1983 "punpckhdq {$src2, $dst|$dst, $src2}",
1985 (v4i32 (vector_shuffle VR128:$src1,
1986 (bc_v4i32 (loadv2i64 addr:$src2)),
1987 UNPCKH_shuffle_mask)))]>;
1988 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1989 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1990 "punpckhdq {$src2, $dst|$dst, $src2}",
1992 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1993 UNPCKH_shuffle_mask)))]>;
1994 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1995 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1996 "punpckhqdq {$src2, $dst|$dst, $src2}",
1998 (v2i64 (vector_shuffle VR128:$src1,
1999 (loadv2i64 addr:$src2),
2000 UNPCKH_shuffle_mask)))]>;
2004 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2005 (ops R32:$dst, VR128:$src1, i32i8imm:$src2),
2006 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
2007 [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1),
2008 (i32 imm:$src2)))]>;
2009 def PEXTRWmi : PDIi8<0xC5, MRMSrcMem,
2010 (ops R32:$dst, i128mem:$src1, i32i8imm:$src2),
2011 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
2012 [(set R32:$dst, (X86pextrw
2013 (bc_v8i16 (loadv2i64 addr:$src1)),
2014 (i32 imm:$src2)))]>;
2016 let isTwoAddress = 1 in {
2017 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2018 (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
2019 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2020 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2021 R32:$src2, (i32 imm:$src3))))]>;
2022 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2023 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
2024 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2026 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2027 (i32 (anyext (loadi16 addr:$src2))),
2028 (i32 imm:$src3))))]>;
2031 //===----------------------------------------------------------------------===//
2032 // Miscellaneous Instructions
2033 //===----------------------------------------------------------------------===//
2036 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
2037 "movmskps {$src, $dst|$dst, $src}",
2038 [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
2039 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
2040 "movmskpd {$src, $dst|$dst, $src}",
2041 [(set R32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
2043 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
2044 "pmovmskb {$src, $dst|$dst, $src}",
2045 [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2047 // Conditional store
2048 def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
2049 "maskmovdqu {$mask, $src|$src, $mask}",
2050 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
2053 // Prefetching loads
2054 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
2055 "prefetcht0 $src", []>;
2056 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
2057 "prefetcht1 $src", []>;
2058 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
2059 "prefetcht2 $src", []>;
2060 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
2061 "prefetchtnta $src", []>;
2063 // Non-temporal stores
2064 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2065 "movntps {$src, $dst|$dst, $src}",
2066 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2067 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2068 "movntpd {$src, $dst|$dst, $src}",
2069 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2070 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
2071 "movntdq {$src, $dst|$dst, $src}",
2072 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2073 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
2074 "movnti {$src, $dst|$dst, $src}",
2075 [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>,
2076 TB, Requires<[HasSSE2]>;
2079 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
2080 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
2081 TB, Requires<[HasSSE2]>;
2083 // Load, store, and memory fence
2084 def SFENCE : I<0xAE, MRM7m, (ops),
2085 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
2086 def LFENCE : I<0xAE, MRM5m, (ops),
2087 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2088 def MFENCE : I<0xAE, MRM6m, (ops),
2089 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2092 def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src),
2094 [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
2095 def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
2097 [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
2099 // Thread synchronization
2100 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
2101 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,
2102 TB, Requires<[HasSSE3]>;
2103 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
2104 [(int_x86_sse3_mwait ECX, EAX)]>,
2105 TB, Requires<[HasSSE3]>;
2107 //===----------------------------------------------------------------------===//
2108 // Alias Instructions
2109 //===----------------------------------------------------------------------===//
2111 // Alias instructions that map zero vector to pxor / xorp* for sse.
2112 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2113 def V_SET0_PI : PDI<0xEF, MRMInitReg, (ops VR128:$dst),
2115 [(set VR128:$dst, (v2i64 immAllZerosV))]>;
2116 def V_SET0_PS : PSI<0x57, MRMInitReg, (ops VR128:$dst),
2118 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2119 def V_SET0_PD : PDI<0x57, MRMInitReg, (ops VR128:$dst),
2121 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2123 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
2124 "pcmpeqd $dst, $dst",
2125 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
2127 // FR32 / FR64 to 128-bit vector conversion.
2128 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
2129 "movss {$src, $dst|$dst, $src}",
2131 (v4f32 (scalar_to_vector FR32:$src)))]>;
2132 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2133 "movss {$src, $dst|$dst, $src}",
2135 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
2136 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
2137 "movsd {$src, $dst|$dst, $src}",
2139 (v2f64 (scalar_to_vector FR64:$src)))]>;
2140 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2141 "movsd {$src, $dst|$dst, $src}",
2143 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2145 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
2146 "movd {$src, $dst|$dst, $src}",
2148 (v4i32 (scalar_to_vector R32:$src)))]>;
2149 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2150 "movd {$src, $dst|$dst, $src}",
2152 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2153 // SSE2 instructions with XS prefix
2154 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
2155 "movq {$src, $dst|$dst, $src}",
2157 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
2158 Requires<[HasSSE2]>;
2159 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2160 "movq {$src, $dst|$dst, $src}",
2162 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2163 Requires<[HasSSE2]>;
2164 // FIXME: may not be able to eliminate this movss with coalescing the src and
2165 // dest register classes are different. We really want to write this pattern
2167 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (i32 0))),
2168 // (f32 FR32:$src)>;
2169 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
2170 "movss {$src, $dst|$dst, $src}",
2171 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
2173 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
2174 "movss {$src, $dst|$dst, $src}",
2175 [(store (f32 (vector_extract (v4f32 VR128:$src),
2176 (i32 0))), addr:$dst)]>;
2177 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
2178 "movsd {$src, $dst|$dst, $src}",
2179 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2181 def MOVPDI2DIrr : PDI<0x6E, MRMSrcReg, (ops R32:$dst, VR128:$src),
2182 "movd {$src, $dst|$dst, $src}",
2183 [(set R32:$dst, (vector_extract (v4i32 VR128:$src),
2185 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
2186 "movd {$src, $dst|$dst, $src}",
2187 [(store (i32 (vector_extract (v4i32 VR128:$src),
2188 (i32 0))), addr:$dst)]>;
2190 // Move to lower bits of a VR128, leaving upper bits alone.
2191 // Three operand (but two address) aliases.
2192 let isTwoAddress = 1 in {
2193 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
2194 "movss {$src2, $dst|$dst, $src2}", []>;
2195 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
2196 "movsd {$src2, $dst|$dst, $src2}", []>;
2197 def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2),
2198 "movd {$src2, $dst|$dst, $src2}", []>;
2200 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2201 "movss {$src2, $dst|$dst, $src2}",
2203 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2204 MOVS_shuffle_mask)))]>;
2205 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2206 "movsd {$src2, $dst|$dst, $src2}",
2208 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2209 MOVS_shuffle_mask)))]>;
2212 // Store / copy lower 64-bits of a XMM register.
2213 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
2214 "movq {$src, $dst|$dst, $src}",
2215 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2217 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2218 def MOVLQ128rr : PDI<0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2219 "movq {$src, $dst|$dst, $src}",
2220 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>;
2222 // Move to lower bits of a VR128 and zeroing upper bits.
2223 // Loading from memory automatically zeroing upper bits.
2224 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2225 "movss {$src, $dst|$dst, $src}",
2227 (v4f32 (X86zexts2vec (loadf32 addr:$src))))]>;
2228 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2229 "movsd {$src, $dst|$dst, $src}",
2231 (v2f64 (X86zexts2vec (loadf64 addr:$src))))]>;
2232 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2233 "movd {$src, $dst|$dst, $src}",
2235 (v4i32 (X86zexts2vec (loadi32 addr:$src))))]>;
2236 def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2237 "movq {$src, $dst|$dst, $src}",
2239 (bc_v2i64 (v2f64 (X86zexts2vec
2240 (loadf64 addr:$src)))))]>;
2242 //===----------------------------------------------------------------------===//
2243 // Non-Instruction Patterns
2244 //===----------------------------------------------------------------------===//
2246 // 128-bit vector undef's.
2247 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2248 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2249 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2250 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2251 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2253 // 128-bit vector all zero's.
2254 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0_PI))>, Requires<[HasSSE2]>;
2255 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0_PI))>, Requires<[HasSSE2]>;
2256 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0_PI))>, Requires<[HasSSE2]>;
2258 // 128-bit vector all one's.
2259 def : Pat<(v16i8 immAllOnesV), (v16i8 (V_SETALLONES))>, Requires<[HasSSE2]>;
2260 def : Pat<(v8i16 immAllOnesV), (v8i16 (V_SETALLONES))>, Requires<[HasSSE2]>;
2261 def : Pat<(v4i32 immAllOnesV), (v4i32 (V_SETALLONES))>, Requires<[HasSSE2]>;
2262 def : Pat<(v2i64 immAllOnesV), (v2i64 (V_SETALLONES))>, Requires<[HasSSE2]>;
2263 def : Pat<(v4f32 immAllOnesV), (v4f32 (V_SETALLONES))>, Requires<[HasSSE1]>;
2265 // Store 128-bit integer vector values.
2266 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2267 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2268 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2269 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2270 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2271 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2273 // Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
2275 def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
2276 Requires<[HasSSE2]>;
2277 def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
2278 Requires<[HasSSE2]>;
2281 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
2282 Requires<[HasSSE2]>;
2283 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>,
2284 Requires<[HasSSE2]>;
2285 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>,
2286 Requires<[HasSSE2]>;
2287 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>,
2288 Requires<[HasSSE2]>;
2289 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>,
2290 Requires<[HasSSE2]>;
2291 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2292 Requires<[HasSSE2]>;
2293 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2294 Requires<[HasSSE2]>;
2295 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2296 Requires<[HasSSE2]>;
2297 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>,
2298 Requires<[HasSSE2]>;
2299 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
2300 Requires<[HasSSE2]>;
2301 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2302 Requires<[HasSSE2]>;
2303 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
2304 Requires<[HasSSE2]>;
2305 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2306 Requires<[HasSSE2]>;
2307 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>,
2308 Requires<[HasSSE2]>;
2309 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>,
2310 Requires<[HasSSE2]>;
2311 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2312 Requires<[HasSSE2]>;
2313 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
2314 Requires<[HasSSE2]>;
2315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2316 Requires<[HasSSE2]>;
2317 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>,
2318 Requires<[HasSSE2]>;
2319 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>,
2320 Requires<[HasSSE2]>;
2321 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>,
2322 Requires<[HasSSE2]>;
2323 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
2324 Requires<[HasSSE2]>;
2325 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>,
2326 Requires<[HasSSE2]>;
2327 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>,
2328 Requires<[HasSSE2]>;
2329 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>,
2330 Requires<[HasSSE2]>;
2331 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>,
2332 Requires<[HasSSE2]>;
2333 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>,
2334 Requires<[HasSSE2]>;
2335 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>,
2336 Requires<[HasSSE2]>;
2337 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>,
2338 Requires<[HasSSE2]>;
2339 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>,
2340 Requires<[HasSSE2]>;
2342 // Zeroing a VR128 then do a MOVS* to the lower bits.
2343 def : Pat<(v2f64 (X86zexts2vec FR64:$src)),
2344 (MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>;
2345 def : Pat<(v4f32 (X86zexts2vec FR32:$src)),
2346 (MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>;
2347 def : Pat<(v4i32 (X86zexts2vec R32:$src)),
2348 (MOVLDI2PDIrr (V_SET0_PI), R32:$src)>, Requires<[HasSSE2]>;
2349 def : Pat<(v8i16 (X86zexts2vec R16:$src)),
2350 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr16 R16:$src))>, Requires<[HasSSE2]>;
2351 def : Pat<(v16i8 (X86zexts2vec R8:$src)),
2352 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
2354 // Splat v2f64 / v2i64
2355 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2356 (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
2357 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2358 (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
2361 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2362 (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
2363 Requires<[HasSSE1]>;
2365 // Special unary SHUFPSrr case.
2366 // FIXME: when we want non two-address code, then we should use PSHUFD?
2367 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2368 SHUFP_unary_shuffle_mask:$sm),
2369 (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm))>,
2370 Requires<[HasSSE1]>;
2371 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2372 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
2373 SHUFP_unary_shuffle_mask:$sm),
2374 (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm))>,
2375 Requires<[HasSSE2]>;
2376 // Special binary v4i32 shuffle cases with SHUFPS.
2377 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2378 PSHUFD_binary_shuffle_mask:$sm),
2379 (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
2380 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
2381 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2382 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2383 (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
2384 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
2386 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2387 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2388 UNPCKL_v_undef_shuffle_mask)),
2389 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2390 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2391 UNPCKL_v_undef_shuffle_mask)),
2392 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2393 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2394 UNPCKL_v_undef_shuffle_mask)),
2395 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2396 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2397 UNPCKL_v_undef_shuffle_mask)),
2398 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2400 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2401 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2402 MOVSHDUP_shuffle_mask)),
2403 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2404 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2405 MOVSHDUP_shuffle_mask)),
2406 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2408 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2409 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2410 MOVSLDUP_shuffle_mask)),
2411 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2412 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2413 MOVSLDUP_shuffle_mask)),
2414 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2416 // 128-bit logical shifts
2417 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2418 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2419 Requires<[HasSSE2]>;
2420 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2421 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2422 Requires<[HasSSE2]>;
2424 // Some special case pandn patterns.
2425 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2427 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2428 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2430 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2431 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2433 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2435 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2436 (load addr:$src2))),
2437 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2438 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2439 (load addr:$src2))),
2440 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2441 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2442 (load addr:$src2))),
2443 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;