1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
272 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
273 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
274 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
275 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
276 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
277 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
278 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
279 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
280 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
281 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
282 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
283 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
286 // Implicitly promote a 32-bit scalar to a vector.
287 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
288 (COPY_TO_REGCLASS FR32:$src, VR128)>;
289 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
290 (COPY_TO_REGCLASS FR32:$src, VR128)>;
291 // Implicitly promote a 64-bit scalar to a vector.
292 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
293 (COPY_TO_REGCLASS FR64:$src, VR128)>;
294 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
295 (COPY_TO_REGCLASS FR64:$src, VR128)>;
297 // Bitcasts between 128-bit vector types. Return the original type since
298 // no instruction is needed for the conversion
299 let Predicates = [HasSSE2] in {
300 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
304 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
309 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
314 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
319 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
324 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
328 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
329 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
332 // Bitcasts between 256-bit vector types. Return the original type since
333 // no instruction is needed for the conversion
334 let Predicates = [HasAVX] in {
335 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
339 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
344 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
349 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
354 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
359 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
363 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
364 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
367 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
368 // This is expanded by ExpandPostRAPseudos.
369 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
371 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
372 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
373 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
374 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
377 //===----------------------------------------------------------------------===//
378 // AVX & SSE - Zero/One Vectors
379 //===----------------------------------------------------------------------===//
381 // Alias instruction that maps zero vector to pxor / xorp* for sse.
382 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
383 // swizzled by ExecutionDepsFix to pxor.
384 // We set canFoldAsLoad because this can be converted to a constant-pool
385 // load of an all-zeros value if folding it would be beneficial.
386 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
388 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
389 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
392 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
394 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
395 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
396 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
399 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
400 // and doesn't need it because on sandy bridge the register is set to zero
401 // at the rename stage without using any execution unit, so SET0PSY
402 // and SET0PDY can be used for vector int instructions without penalty
403 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
404 isPseudo = 1, Predicates = [HasAVX] in {
405 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
406 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
409 let Predicates = [HasAVX] in
410 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
412 let Predicates = [HasAVX2] in {
413 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
414 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
415 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
416 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
419 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
420 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
421 let Predicates = [HasAVX1Only] in {
422 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
423 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
424 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
426 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 // We set canFoldAsLoad because this can be converted to a constant-pool
440 // load of an all-ones value if folding it would be beneficial.
441 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
443 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
444 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
445 let Predicates = [HasAVX2] in
446 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
447 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
451 //===----------------------------------------------------------------------===//
452 // SSE 1 & 2 - Move FP Scalar Instructions
454 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
455 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
456 // is used instead. Register-to-register movss/movsd is not modeled as an
457 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
458 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
459 //===----------------------------------------------------------------------===//
461 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
462 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
463 [(set VR128:$dst, (vt (OpNode VR128:$src1,
464 (scalar_to_vector RC:$src2))))],
467 // Loading from memory automatically zeroing upper bits.
468 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
469 PatFrag mem_pat, string OpcodeStr> :
470 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
471 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
472 [(set RC:$dst, (mem_pat addr:$src))],
476 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
477 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
479 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
480 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
483 // For the disassembler
484 let isCodeGenOnly = 1 in {
485 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
486 (ins VR128:$src1, FR32:$src2),
487 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
490 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
491 (ins VR128:$src1, FR64:$src2),
492 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
497 let canFoldAsLoad = 1, isReMaterializable = 1 in {
498 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
500 let AddedComplexity = 20 in
501 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
505 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
506 "movss\t{$src, $dst|$dst, $src}",
507 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
509 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
510 "movsd\t{$src, $dst|$dst, $src}",
511 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
515 let Constraints = "$src1 = $dst" in {
516 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
517 "movss\t{$src2, $dst|$dst, $src2}">, XS;
518 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
519 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
521 // For the disassembler
522 let isCodeGenOnly = 1 in {
523 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
524 (ins VR128:$src1, FR32:$src2),
525 "movss\t{$src2, $dst|$dst, $src2}", [],
526 IIC_SSE_MOV_S_RR>, XS;
527 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
528 (ins VR128:$src1, FR64:$src2),
529 "movsd\t{$src2, $dst|$dst, $src2}", [],
530 IIC_SSE_MOV_S_RR>, XD;
534 let canFoldAsLoad = 1, isReMaterializable = 1 in {
535 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
537 let AddedComplexity = 20 in
538 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
541 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
542 "movss\t{$src, $dst|$dst, $src}",
543 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
544 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
545 "movsd\t{$src, $dst|$dst, $src}",
546 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
549 let Predicates = [HasAVX] in {
550 let AddedComplexity = 15 in {
551 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
552 // MOVS{S,D} to the lower bits.
553 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
554 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
555 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
556 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
557 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
558 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
559 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
560 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
562 // Move low f32 and clear high bits.
563 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
564 (SUBREG_TO_REG (i32 0),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
567 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
568 (SUBREG_TO_REG (i32 0),
569 (VMOVSSrr (v4i32 (V_SET0)),
570 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
573 let AddedComplexity = 20 in {
574 // MOVSSrm zeros the high parts of the register; represent this
575 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
576 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
577 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
578 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
579 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
580 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
581 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
583 // MOVSDrm zeros the high parts of the register; represent this
584 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
585 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
586 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
587 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
588 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
589 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
590 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
591 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
592 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
593 def : Pat<(v2f64 (X86vzload addr:$src)),
594 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
596 // Represent the same patterns above but in the form they appear for
598 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
599 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
600 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
601 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
602 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
603 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
604 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
605 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
606 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
608 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
609 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
610 (SUBREG_TO_REG (i32 0),
611 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
613 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
614 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
615 (SUBREG_TO_REG (i64 0),
616 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
618 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
619 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
620 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
622 // Move low f64 and clear high bits.
623 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
624 (SUBREG_TO_REG (i32 0),
625 (VMOVSDrr (v2f64 (V_SET0)),
626 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
628 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
629 (SUBREG_TO_REG (i32 0),
630 (VMOVSDrr (v2i64 (V_SET0)),
631 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
633 // Extract and store.
634 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
636 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
637 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
639 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
641 // Shuffle with VMOVSS
642 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
643 (VMOVSSrr (v4i32 VR128:$src1),
644 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
645 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
646 (VMOVSSrr (v4f32 VR128:$src1),
647 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
650 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
651 (SUBREG_TO_REG (i32 0),
652 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
653 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
655 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
656 (SUBREG_TO_REG (i32 0),
657 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
658 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
661 // Shuffle with VMOVSD
662 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
663 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
664 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
665 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
666 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
667 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
668 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
669 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
673 (SUBREG_TO_REG (i32 0),
674 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
675 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
677 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
678 (SUBREG_TO_REG (i32 0),
679 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
680 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
684 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
685 // is during lowering, where it's not possible to recognize the fold cause
686 // it has two uses through a bitcast. One use disappears at isel time and the
687 // fold opportunity reappears.
688 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
689 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
690 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
691 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
692 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
693 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
694 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
695 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
698 let Predicates = [UseSSE1] in {
699 let AddedComplexity = 15 in {
700 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
701 // MOVSS to the lower bits.
702 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
703 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
704 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
705 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
706 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
707 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
710 let AddedComplexity = 20 in {
711 // MOVSSrm already zeros the high parts of the register.
712 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
713 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
714 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
715 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
716 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
717 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
720 // Extract and store.
721 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
723 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
725 // Shuffle with MOVSS
726 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
727 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
728 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
729 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
732 let Predicates = [UseSSE2] in {
733 let AddedComplexity = 15 in {
734 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
735 // MOVSD to the lower bits.
736 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
737 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
740 let AddedComplexity = 20 in {
741 // MOVSDrm already zeros the high parts of the register.
742 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
743 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
744 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
745 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
746 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
747 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
748 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
749 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
750 def : Pat<(v2f64 (X86vzload addr:$src)),
751 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
754 // Extract and store.
755 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
757 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
759 // Shuffle with MOVSD
760 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
761 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
762 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
763 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
764 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
765 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
766 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
767 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
769 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
770 // is during lowering, where it's not possible to recognize the fold cause
771 // it has two uses through a bitcast. One use disappears at isel time and the
772 // fold opportunity reappears.
773 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
774 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
775 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
776 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
777 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
778 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
779 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
780 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
783 //===----------------------------------------------------------------------===//
784 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
785 //===----------------------------------------------------------------------===//
787 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
788 X86MemOperand x86memop, PatFrag ld_frag,
789 string asm, Domain d,
791 bit IsReMaterializable = 1> {
792 let neverHasSideEffects = 1 in
793 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
794 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
795 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
796 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
797 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
798 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
801 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
802 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
804 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
805 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
807 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
808 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
810 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
811 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
814 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
815 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
817 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
818 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
819 TB, OpSize, VEX, VEX_L;
820 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
821 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
823 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
824 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
825 TB, OpSize, VEX, VEX_L;
826 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
827 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
829 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
830 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
832 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
833 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
835 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
836 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
839 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
840 "movaps\t{$src, $dst|$dst, $src}",
841 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
842 IIC_SSE_MOVA_P_MR>, VEX;
843 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
844 "movapd\t{$src, $dst|$dst, $src}",
845 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
846 IIC_SSE_MOVA_P_MR>, VEX;
847 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
848 "movups\t{$src, $dst|$dst, $src}",
849 [(store (v4f32 VR128:$src), addr:$dst)],
850 IIC_SSE_MOVU_P_MR>, VEX;
851 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
852 "movupd\t{$src, $dst|$dst, $src}",
853 [(store (v2f64 VR128:$src), addr:$dst)],
854 IIC_SSE_MOVU_P_MR>, VEX;
855 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
856 "movaps\t{$src, $dst|$dst, $src}",
857 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
858 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
859 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
860 "movapd\t{$src, $dst|$dst, $src}",
861 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
862 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
863 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
864 "movups\t{$src, $dst|$dst, $src}",
865 [(store (v8f32 VR256:$src), addr:$dst)],
866 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
867 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
868 "movupd\t{$src, $dst|$dst, $src}",
869 [(store (v4f64 VR256:$src), addr:$dst)],
870 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
873 let isCodeGenOnly = 1 in {
874 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
876 "movaps\t{$src, $dst|$dst, $src}", [],
877 IIC_SSE_MOVA_P_RR>, VEX;
878 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
880 "movapd\t{$src, $dst|$dst, $src}", [],
881 IIC_SSE_MOVA_P_RR>, VEX;
882 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
884 "movups\t{$src, $dst|$dst, $src}", [],
885 IIC_SSE_MOVU_P_RR>, VEX;
886 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
888 "movupd\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVU_P_RR>, VEX;
890 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
892 "movaps\t{$src, $dst|$dst, $src}", [],
893 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
894 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
896 "movapd\t{$src, $dst|$dst, $src}", [],
897 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
898 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
900 "movups\t{$src, $dst|$dst, $src}", [],
901 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
902 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
904 "movupd\t{$src, $dst|$dst, $src}", [],
905 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
908 let Predicates = [HasAVX] in {
909 def : Pat<(v8i32 (X86vzmovl
910 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
911 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
912 def : Pat<(v4i64 (X86vzmovl
913 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
914 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
915 def : Pat<(v8f32 (X86vzmovl
916 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
917 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
918 def : Pat<(v4f64 (X86vzmovl
919 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
920 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
924 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
925 (VMOVUPSYmr addr:$dst, VR256:$src)>;
926 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
927 (VMOVUPDYmr addr:$dst, VR256:$src)>;
929 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
930 "movaps\t{$src, $dst|$dst, $src}",
931 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
933 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
934 "movapd\t{$src, $dst|$dst, $src}",
935 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
937 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
938 "movups\t{$src, $dst|$dst, $src}",
939 [(store (v4f32 VR128:$src), addr:$dst)],
941 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
942 "movupd\t{$src, $dst|$dst, $src}",
943 [(store (v2f64 VR128:$src), addr:$dst)],
947 let isCodeGenOnly = 1 in {
948 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
949 "movaps\t{$src, $dst|$dst, $src}", [],
951 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
952 "movapd\t{$src, $dst|$dst, $src}", [],
954 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
955 "movups\t{$src, $dst|$dst, $src}", [],
957 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
958 "movupd\t{$src, $dst|$dst, $src}", [],
962 let Predicates = [HasAVX] in {
963 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
964 (VMOVUPSmr addr:$dst, VR128:$src)>;
965 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
966 (VMOVUPDmr addr:$dst, VR128:$src)>;
969 let Predicates = [UseSSE1] in
970 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
971 (MOVUPSmr addr:$dst, VR128:$src)>;
972 let Predicates = [UseSSE2] in
973 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
974 (MOVUPDmr addr:$dst, VR128:$src)>;
976 // Use vmovaps/vmovups for AVX integer load/store.
977 let Predicates = [HasAVX] in {
978 // 128-bit load/store
979 def : Pat<(alignedloadv2i64 addr:$src),
980 (VMOVAPSrm addr:$src)>;
981 def : Pat<(loadv2i64 addr:$src),
982 (VMOVUPSrm addr:$src)>;
984 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
985 (VMOVAPSmr addr:$dst, VR128:$src)>;
986 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
987 (VMOVAPSmr addr:$dst, VR128:$src)>;
988 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
989 (VMOVAPSmr addr:$dst, VR128:$src)>;
990 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
991 (VMOVAPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
993 (VMOVUPSmr addr:$dst, VR128:$src)>;
994 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
995 (VMOVUPSmr addr:$dst, VR128:$src)>;
996 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
999 (VMOVUPSmr addr:$dst, VR128:$src)>;
1001 // 256-bit load/store
1002 def : Pat<(alignedloadv4i64 addr:$src),
1003 (VMOVAPSYrm addr:$src)>;
1004 def : Pat<(loadv4i64 addr:$src),
1005 (VMOVUPSYrm addr:$src)>;
1006 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1007 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1008 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1009 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1010 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1011 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1012 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1013 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1014 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1015 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1016 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1017 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1018 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1019 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1020 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1021 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1023 // Special patterns for storing subvector extracts of lower 128-bits
1024 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1025 def : Pat<(alignedstore (v2f64 (extract_subvector
1026 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1027 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1028 def : Pat<(alignedstore (v4f32 (extract_subvector
1029 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1030 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1031 def : Pat<(alignedstore (v2i64 (extract_subvector
1032 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1033 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1034 def : Pat<(alignedstore (v4i32 (extract_subvector
1035 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1036 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1037 def : Pat<(alignedstore (v8i16 (extract_subvector
1038 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1039 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1040 def : Pat<(alignedstore (v16i8 (extract_subvector
1041 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1042 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1044 def : Pat<(store (v2f64 (extract_subvector
1045 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1046 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1047 def : Pat<(store (v4f32 (extract_subvector
1048 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1049 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1050 def : Pat<(store (v2i64 (extract_subvector
1051 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1052 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1053 def : Pat<(store (v4i32 (extract_subvector
1054 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1055 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1056 def : Pat<(store (v8i16 (extract_subvector
1057 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1058 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1059 def : Pat<(store (v16i8 (extract_subvector
1060 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1061 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 // Use movaps / movups for SSE integer load / store (one byte shorter).
1065 // The instructions selected below are then converted to MOVDQA/MOVDQU
1066 // during the SSE domain pass.
1067 let Predicates = [UseSSE1] in {
1068 def : Pat<(alignedloadv2i64 addr:$src),
1069 (MOVAPSrm addr:$src)>;
1070 def : Pat<(loadv2i64 addr:$src),
1071 (MOVUPSrm addr:$src)>;
1073 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1074 (MOVAPSmr addr:$dst, VR128:$src)>;
1075 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1076 (MOVAPSmr addr:$dst, VR128:$src)>;
1077 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1078 (MOVAPSmr addr:$dst, VR128:$src)>;
1079 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1080 (MOVAPSmr addr:$dst, VR128:$src)>;
1081 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1082 (MOVUPSmr addr:$dst, VR128:$src)>;
1083 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1084 (MOVUPSmr addr:$dst, VR128:$src)>;
1085 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1086 (MOVUPSmr addr:$dst, VR128:$src)>;
1087 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1088 (MOVUPSmr addr:$dst, VR128:$src)>;
1091 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1092 // bits are disregarded. FIXME: Set encoding to pseudo!
1093 let neverHasSideEffects = 1 in {
1094 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1095 "movaps\t{$src, $dst|$dst, $src}", [],
1096 IIC_SSE_MOVA_P_RR>, VEX;
1097 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1098 "movapd\t{$src, $dst|$dst, $src}", [],
1099 IIC_SSE_MOVA_P_RR>, VEX;
1100 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1101 "movaps\t{$src, $dst|$dst, $src}", [],
1103 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1104 "movapd\t{$src, $dst|$dst, $src}", [],
1108 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1109 // bits are disregarded. FIXME: Set encoding to pseudo!
1110 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1111 let isCodeGenOnly = 1 in {
1112 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1113 "movaps\t{$src, $dst|$dst, $src}",
1114 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1115 IIC_SSE_MOVA_P_RM>, VEX;
1116 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1117 "movapd\t{$src, $dst|$dst, $src}",
1118 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1119 IIC_SSE_MOVA_P_RM>, VEX;
1121 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1122 "movaps\t{$src, $dst|$dst, $src}",
1123 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1125 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1126 "movapd\t{$src, $dst|$dst, $src}",
1127 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1131 //===----------------------------------------------------------------------===//
1132 // SSE 1 & 2 - Move Low packed FP Instructions
1133 //===----------------------------------------------------------------------===//
1135 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1136 SDNode psnode, SDNode pdnode, string base_opc,
1137 string asm_opr, InstrItinClass itin> {
1138 def PSrm : PI<opc, MRMSrcMem,
1139 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1140 !strconcat(base_opc, "s", asm_opr),
1143 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1144 itin, SSEPackedSingle>, TB;
1146 def PDrm : PI<opc, MRMSrcMem,
1147 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1148 !strconcat(base_opc, "d", asm_opr),
1149 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1150 (scalar_to_vector (loadf64 addr:$src2)))))],
1151 itin, SSEPackedDouble>, TB, OpSize;
1154 let AddedComplexity = 20 in {
1155 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1156 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1157 IIC_SSE_MOV_LH>, VEX_4V;
1159 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1160 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1161 "\t{$src2, $dst|$dst, $src2}",
1165 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1166 "movlps\t{$src, $dst|$dst, $src}",
1167 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1168 (iPTR 0))), addr:$dst)],
1169 IIC_SSE_MOV_LH>, VEX;
1170 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1171 "movlpd\t{$src, $dst|$dst, $src}",
1172 [(store (f64 (vector_extract (v2f64 VR128:$src),
1173 (iPTR 0))), addr:$dst)],
1174 IIC_SSE_MOV_LH>, VEX;
1175 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1176 "movlps\t{$src, $dst|$dst, $src}",
1177 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1178 (iPTR 0))), addr:$dst)],
1180 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1181 "movlpd\t{$src, $dst|$dst, $src}",
1182 [(store (f64 (vector_extract (v2f64 VR128:$src),
1183 (iPTR 0))), addr:$dst)],
1186 let Predicates = [HasAVX] in {
1187 // Shuffle with VMOVLPS
1188 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1189 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1190 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1191 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1193 // Shuffle with VMOVLPD
1194 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1195 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1196 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1197 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1200 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1202 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1203 def : Pat<(store (v4i32 (X86Movlps
1204 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1205 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1206 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1208 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1209 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1211 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1214 let Predicates = [UseSSE1] in {
1215 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1216 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1217 (iPTR 0))), addr:$src1),
1218 (MOVLPSmr addr:$src1, VR128:$src2)>;
1220 // Shuffle with MOVLPS
1221 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1222 (MOVLPSrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1224 (MOVLPSrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(X86Movlps VR128:$src1,
1226 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1227 (MOVLPSrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (MOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1236 (MOVLPSmr addr:$src1, VR128:$src2)>;
1239 let Predicates = [UseSSE2] in {
1240 // Shuffle with MOVLPD
1241 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1242 (MOVLPDrm VR128:$src1, addr:$src2)>;
1243 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1244 (MOVLPDrm VR128:$src1, addr:$src2)>;
1247 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1249 (MOVLPDmr addr:$src1, VR128:$src2)>;
1250 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1252 (MOVLPDmr addr:$src1, VR128:$src2)>;
1255 //===----------------------------------------------------------------------===//
1256 // SSE 1 & 2 - Move Hi packed FP Instructions
1257 //===----------------------------------------------------------------------===//
1259 let AddedComplexity = 20 in {
1260 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1261 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1262 IIC_SSE_MOV_LH>, VEX_4V;
1264 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1265 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1266 "\t{$src2, $dst|$dst, $src2}",
1270 // v2f64 extract element 1 is always custom lowered to unpack high to low
1271 // and extract element 0 so the non-store version isn't too horrible.
1272 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1273 "movhps\t{$src, $dst|$dst, $src}",
1274 [(store (f64 (vector_extract
1275 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1276 (bc_v2f64 (v4f32 VR128:$src))),
1277 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1278 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1279 "movhpd\t{$src, $dst|$dst, $src}",
1280 [(store (f64 (vector_extract
1281 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1282 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1283 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1284 "movhps\t{$src, $dst|$dst, $src}",
1285 [(store (f64 (vector_extract
1286 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1287 (bc_v2f64 (v4f32 VR128:$src))),
1288 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1289 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1290 "movhpd\t{$src, $dst|$dst, $src}",
1291 [(store (f64 (vector_extract
1292 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1293 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1295 let Predicates = [HasAVX] in {
1297 def : Pat<(X86Movlhps VR128:$src1,
1298 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1299 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1300 def : Pat<(X86Movlhps VR128:$src1,
1301 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1302 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1304 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1305 // is during lowering, where it's not possible to recognize the load fold
1306 // cause it has two uses through a bitcast. One use disappears at isel time
1307 // and the fold opportunity reappears.
1308 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1309 (scalar_to_vector (loadf64 addr:$src2)))),
1310 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1313 let Predicates = [UseSSE1] in {
1315 def : Pat<(X86Movlhps VR128:$src1,
1316 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1317 (MOVHPSrm VR128:$src1, addr:$src2)>;
1318 def : Pat<(X86Movlhps VR128:$src1,
1319 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1320 (MOVHPSrm VR128:$src1, addr:$src2)>;
1323 let Predicates = [UseSSE2] in {
1324 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1325 // is during lowering, where it's not possible to recognize the load fold
1326 // cause it has two uses through a bitcast. One use disappears at isel time
1327 // and the fold opportunity reappears.
1328 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1329 (scalar_to_vector (loadf64 addr:$src2)))),
1330 (MOVHPDrm VR128:$src1, addr:$src2)>;
1333 //===----------------------------------------------------------------------===//
1334 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1335 //===----------------------------------------------------------------------===//
1337 let AddedComplexity = 20 in {
1338 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1339 (ins VR128:$src1, VR128:$src2),
1340 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1342 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1345 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1346 (ins VR128:$src1, VR128:$src2),
1347 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1349 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1353 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1354 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1355 (ins VR128:$src1, VR128:$src2),
1356 "movlhps\t{$src2, $dst|$dst, $src2}",
1358 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1360 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1361 (ins VR128:$src1, VR128:$src2),
1362 "movhlps\t{$src2, $dst|$dst, $src2}",
1364 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1368 let Predicates = [HasAVX] in {
1370 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1371 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1372 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1373 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1376 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1377 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1380 let Predicates = [UseSSE1] in {
1382 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1383 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1384 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1385 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1388 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1389 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1392 //===----------------------------------------------------------------------===//
1393 // SSE 1 & 2 - Conversion Instructions
1394 //===----------------------------------------------------------------------===//
1396 def SSE_CVT_PD : OpndItins<
1397 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1400 def SSE_CVT_PS : OpndItins<
1401 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1404 def SSE_CVT_Scalar : OpndItins<
1405 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1408 def SSE_CVT_SS2SI_32 : OpndItins<
1409 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1412 def SSE_CVT_SS2SI_64 : OpndItins<
1413 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1416 def SSE_CVT_SD2SI : OpndItins<
1417 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1420 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1421 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1422 string asm, OpndItins itins> {
1423 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1424 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1426 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1427 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1431 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1432 X86MemOperand x86memop, string asm, Domain d,
1434 let neverHasSideEffects = 1 in {
1435 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1438 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1443 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1444 X86MemOperand x86memop, string asm> {
1445 let neverHasSideEffects = 1 in {
1446 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1447 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1449 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1450 (ins DstRC:$src1, x86memop:$src),
1451 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1452 } // neverHasSideEffects = 1
1455 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1456 "cvttss2si\t{$src, $dst|$dst, $src}",
1459 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1460 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1462 XS, VEX, VEX_W, VEX_LIG;
1463 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1464 "cvttsd2si\t{$src, $dst|$dst, $src}",
1467 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1468 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1470 XD, VEX, VEX_W, VEX_LIG;
1472 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1473 // register, but the same isn't true when only using memory operands,
1474 // provide other assembly "l" and "q" forms to address this explicitly
1475 // where appropriate to do so.
1476 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1477 XS, VEX_4V, VEX_LIG;
1478 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1479 XS, VEX_4V, VEX_W, VEX_LIG;
1480 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1481 XD, VEX_4V, VEX_LIG;
1482 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1483 XD, VEX_4V, VEX_W, VEX_LIG;
1485 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1486 (VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
1487 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1488 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1490 let Predicates = [HasAVX] in {
1491 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1492 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1493 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1494 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1495 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1496 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1497 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1498 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1500 def : Pat<(f32 (sint_to_fp GR32:$src)),
1501 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1502 def : Pat<(f32 (sint_to_fp GR64:$src)),
1503 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1504 def : Pat<(f64 (sint_to_fp GR32:$src)),
1505 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1506 def : Pat<(f64 (sint_to_fp GR64:$src)),
1507 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1510 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1511 "cvttss2si\t{$src, $dst|$dst, $src}",
1512 SSE_CVT_SS2SI_32>, XS;
1513 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1514 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1515 SSE_CVT_SS2SI_64>, XS, REX_W;
1516 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1517 "cvttsd2si\t{$src, $dst|$dst, $src}",
1519 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1520 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1521 SSE_CVT_SD2SI>, XD, REX_W;
1522 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1523 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1524 SSE_CVT_Scalar>, XS;
1525 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1526 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1527 SSE_CVT_Scalar>, XS, REX_W;
1528 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1529 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1530 SSE_CVT_Scalar>, XD;
1531 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1532 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1533 SSE_CVT_Scalar>, XD, REX_W;
1535 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1536 // and/or XMM operand(s).
1538 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1539 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1540 string asm, OpndItins itins> {
1541 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1542 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1543 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1544 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1545 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1546 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>;
1549 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1550 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1551 PatFrag ld_frag, string asm, OpndItins itins,
1553 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1555 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1556 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1557 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1559 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1560 (ins DstRC:$src1, x86memop:$src2),
1562 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1563 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1564 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1568 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1569 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si{l}",
1570 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1571 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1572 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si{q}",
1573 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1575 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1576 sdmem, sse_load_f64, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1577 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1578 sdmem, sse_load_f64, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1581 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1582 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1583 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1584 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1585 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1586 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1588 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1589 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1590 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1591 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1592 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1593 SSE_CVT_Scalar, 0>, XD,
1596 let Constraints = "$src1 = $dst" in {
1597 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1598 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1599 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1600 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1601 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1602 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1603 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1604 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1605 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1606 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1607 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1608 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1613 // Aliases for intrinsics
1614 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1615 ssmem, sse_load_f32, "cvttss2si",
1616 SSE_CVT_SS2SI_32>, XS, VEX;
1617 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1618 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1619 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1621 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1622 sdmem, sse_load_f64, "cvttsd2si",
1623 SSE_CVT_SD2SI>, XD, VEX;
1624 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1625 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1626 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1628 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1629 ssmem, sse_load_f32, "cvttss2si",
1630 SSE_CVT_SS2SI_32>, XS;
1631 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1632 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1633 "cvttss2si{q}", SSE_CVT_SS2SI_64>, XS, REX_W;
1634 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1635 sdmem, sse_load_f64, "cvttsd2si",
1637 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1638 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1639 "cvttsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1641 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1642 ssmem, sse_load_f32, "cvtss2si{l}",
1643 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1644 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1645 ssmem, sse_load_f32, "cvtss2si{q}",
1646 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1648 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1649 ssmem, sse_load_f32, "cvtss2si{l}",
1650 SSE_CVT_SS2SI_32>, XS;
1651 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1652 ssmem, sse_load_f32, "cvtss2si{q}",
1653 SSE_CVT_SS2SI_64>, XS, REX_W;
1655 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1656 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1657 SSEPackedSingle, SSE_CVT_PS>,
1658 TB, VEX, Requires<[HasAVX]>;
1659 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1660 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1661 SSEPackedSingle, SSE_CVT_PS>,
1662 TB, VEX, VEX_L, Requires<[HasAVX]>;
1664 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1665 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1666 SSEPackedSingle, SSE_CVT_PS>,
1667 TB, Requires<[UseSSE2]>;
1671 // Convert scalar double to scalar single
1672 let neverHasSideEffects = 1 in {
1673 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1674 (ins FR64:$src1, FR64:$src2),
1675 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1676 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1678 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1679 (ins FR64:$src1, f64mem:$src2),
1680 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1681 [], IIC_SSE_CVT_Scalar_RM>,
1682 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1685 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1688 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1689 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1690 [(set FR32:$dst, (fround FR64:$src))],
1691 IIC_SSE_CVT_Scalar_RR>;
1692 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1693 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1694 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1695 IIC_SSE_CVT_Scalar_RM>,
1697 Requires<[UseSSE2, OptForSize]>;
1699 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1700 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1701 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1703 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1704 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
1705 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1706 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1707 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1708 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1709 VR128:$src1, sse_load_f64:$src2))],
1710 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
1712 let Constraints = "$src1 = $dst" in {
1713 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1714 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1715 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1717 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1718 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>;
1719 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1720 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1721 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1722 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1723 VR128:$src1, sse_load_f64:$src2))],
1724 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>;
1727 // Convert scalar single to scalar double
1728 // SSE2 instructions with XS prefix
1729 let neverHasSideEffects = 1 in {
1730 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1731 (ins FR32:$src1, FR32:$src2),
1732 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1733 [], IIC_SSE_CVT_Scalar_RR>,
1734 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1736 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1737 (ins FR32:$src1, f32mem:$src2),
1738 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1739 [], IIC_SSE_CVT_Scalar_RM>,
1740 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1743 def : Pat<(f64 (fextend FR32:$src)),
1744 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1745 def : Pat<(fextend (loadf32 addr:$src)),
1746 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1748 def : Pat<(extloadf32 addr:$src),
1749 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1750 Requires<[HasAVX, OptForSize]>;
1751 def : Pat<(extloadf32 addr:$src),
1752 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1753 Requires<[HasAVX, OptForSpeed]>;
1755 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1756 "cvtss2sd\t{$src, $dst|$dst, $src}",
1757 [(set FR64:$dst, (fextend FR32:$src))],
1758 IIC_SSE_CVT_Scalar_RR>, XS,
1759 Requires<[UseSSE2]>;
1760 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1761 "cvtss2sd\t{$src, $dst|$dst, $src}",
1762 [(set FR64:$dst, (extloadf32 addr:$src))],
1763 IIC_SSE_CVT_Scalar_RM>, XS,
1764 Requires<[UseSSE2, OptForSize]>;
1766 // extload f32 -> f64. This matches load+fextend because we have a hack in
1767 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1769 // Since these loads aren't folded into the fextend, we have to match it
1771 def : Pat<(fextend (loadf32 addr:$src)),
1772 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1773 def : Pat<(extloadf32 addr:$src),
1774 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1776 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1777 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1778 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1780 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1781 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
1782 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1783 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1784 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1786 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1787 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
1788 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1789 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1790 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1791 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1793 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1794 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>;
1795 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1796 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1797 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1799 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1800 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>;
1803 // Convert packed single/double fp to doubleword
1804 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvtps2dq\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1807 IIC_SSE_CVT_PS_RR>, VEX;
1808 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1809 "cvtps2dq\t{$src, $dst|$dst, $src}",
1811 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1812 IIC_SSE_CVT_PS_RM>, VEX;
1813 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1814 "cvtps2dq\t{$src, $dst|$dst, $src}",
1816 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1817 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1818 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1819 "cvtps2dq\t{$src, $dst|$dst, $src}",
1821 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1822 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1823 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1824 "cvtps2dq\t{$src, $dst|$dst, $src}",
1825 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1827 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1828 "cvtps2dq\t{$src, $dst|$dst, $src}",
1830 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1834 // Convert Packed Double FP to Packed DW Integers
1835 let Predicates = [HasAVX] in {
1836 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1837 // register, but the same isn't true when using memory operands instead.
1838 // Provide other assembly rr and rm forms to address this explicitly.
1839 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1840 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1841 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1845 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1846 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1847 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1848 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1850 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
1853 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1854 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1856 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L;
1857 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1858 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1860 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1862 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1863 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1866 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1867 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1869 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1871 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1872 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1873 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1876 // Convert with truncation packed single/double fp to doubleword
1877 // SSE2 packed instructions with XS prefix
1878 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1879 "cvttps2dq\t{$src, $dst|$dst, $src}",
1881 (int_x86_sse2_cvttps2dq VR128:$src))],
1882 IIC_SSE_CVT_PS_RR>, VEX;
1883 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1884 "cvttps2dq\t{$src, $dst|$dst, $src}",
1885 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1886 (memopv4f32 addr:$src)))],
1887 IIC_SSE_CVT_PS_RM>, VEX;
1888 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1889 "cvttps2dq\t{$src, $dst|$dst, $src}",
1891 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1892 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1893 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1894 "cvttps2dq\t{$src, $dst|$dst, $src}",
1895 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1896 (memopv8f32 addr:$src)))],
1897 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1899 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 "cvttps2dq\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1903 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1904 "cvttps2dq\t{$src, $dst|$dst, $src}",
1906 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1909 let Predicates = [HasAVX] in {
1910 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1911 (VCVTDQ2PSrr VR128:$src)>;
1912 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1913 (VCVTDQ2PSrm addr:$src)>;
1915 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1916 (VCVTDQ2PSrr VR128:$src)>;
1917 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1918 (VCVTDQ2PSrm addr:$src)>;
1920 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1921 (VCVTTPS2DQrr VR128:$src)>;
1922 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1923 (VCVTTPS2DQrm addr:$src)>;
1925 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1926 (VCVTDQ2PSYrr VR256:$src)>;
1927 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1928 (VCVTDQ2PSYrm addr:$src)>;
1930 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1931 (VCVTTPS2DQYrr VR256:$src)>;
1932 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1933 (VCVTTPS2DQYrm addr:$src)>;
1936 let Predicates = [UseSSE2] in {
1937 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1938 (CVTDQ2PSrr VR128:$src)>;
1939 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1940 (CVTDQ2PSrm addr:$src)>;
1942 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1943 (CVTDQ2PSrr VR128:$src)>;
1944 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1945 (CVTDQ2PSrm addr:$src)>;
1947 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1948 (CVTTPS2DQrr VR128:$src)>;
1949 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1950 (CVTTPS2DQrm addr:$src)>;
1953 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1954 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1956 (int_x86_sse2_cvttpd2dq VR128:$src))],
1957 IIC_SSE_CVT_PD_RR>, VEX;
1959 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1960 // register, but the same isn't true when using memory operands instead.
1961 // Provide other assembly rr and rm forms to address this explicitly.
1964 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
1965 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
1966 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1967 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
1968 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1969 (memopv2f64 addr:$src)))],
1970 IIC_SSE_CVT_PD_RM>, VEX;
1973 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1974 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1976 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
1977 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
1978 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1979 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1981 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
1982 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1983 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
1984 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
1986 let Predicates = [HasAVX] in {
1987 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
1988 (VCVTTPD2DQYrr VR256:$src)>;
1989 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
1990 (VCVTTPD2DQYrm addr:$src)>;
1991 } // Predicates = [HasAVX]
1993 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1994 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1995 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1997 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1998 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1999 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2000 (memopv2f64 addr:$src)))],
2003 // Convert packed single to packed double
2004 let Predicates = [HasAVX] in {
2005 // SSE2 instructions without OpSize prefix
2006 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2007 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2008 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2009 IIC_SSE_CVT_PD_RR>, TB, VEX;
2010 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2011 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2012 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2013 IIC_SSE_CVT_PD_RM>, TB, VEX;
2014 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2015 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2017 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2018 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L;
2019 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2020 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2022 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2023 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L;
2026 let Predicates = [UseSSE2] in {
2027 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2028 "cvtps2pd\t{$src, $dst|$dst, $src}",
2029 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2030 IIC_SSE_CVT_PD_RR>, TB;
2031 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2032 "cvtps2pd\t{$src, $dst|$dst, $src}",
2033 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2034 IIC_SSE_CVT_PD_RM>, TB;
2037 // Convert Packed DW Integers to Packed Double FP
2038 let Predicates = [HasAVX] in {
2039 let neverHasSideEffects = 1, mayLoad = 1 in
2040 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2041 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2043 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
2047 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2048 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2050 (int_x86_avx_cvtdq2_pd_256
2051 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L;
2052 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2053 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2055 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L;
2058 let neverHasSideEffects = 1, mayLoad = 1 in
2059 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2060 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2062 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2063 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2064 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2067 // AVX 256-bit register conversion intrinsics
2068 let Predicates = [HasAVX] in {
2069 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2070 (VCVTDQ2PDYrr VR128:$src)>;
2071 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2072 (VCVTDQ2PDYrm addr:$src)>;
2073 } // Predicates = [HasAVX]
2075 // Convert packed double to packed single
2076 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2077 // register, but the same isn't true when using memory operands instead.
2078 // Provide other assembly rr and rm forms to address this explicitly.
2079 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2080 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2081 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2082 IIC_SSE_CVT_PD_RR>, VEX;
2085 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2086 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2087 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2088 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2090 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2091 IIC_SSE_CVT_PD_RM>, VEX;
2094 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2095 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2097 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2098 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
2099 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2100 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2102 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2103 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2104 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2105 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2107 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2108 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2109 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2111 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2112 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2114 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2118 // AVX 256-bit register conversion intrinsics
2119 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2120 // whenever possible to avoid declaring two versions of each one.
2121 let Predicates = [HasAVX] in {
2122 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2123 (VCVTDQ2PSYrr VR256:$src)>;
2124 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2125 (VCVTDQ2PSYrm addr:$src)>;
2127 // Match fround and fextend for 128/256-bit conversions
2128 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2129 (VCVTPD2PSrr VR128:$src)>;
2130 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2131 (VCVTPD2PSXrm addr:$src)>;
2132 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2133 (VCVTPD2PSYrr VR256:$src)>;
2134 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2135 (VCVTPD2PSYrm addr:$src)>;
2137 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2138 (VCVTPS2PDrr VR128:$src)>;
2139 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2140 (VCVTPS2PDYrr VR128:$src)>;
2141 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2142 (VCVTPS2PDYrm addr:$src)>;
2145 let Predicates = [UseSSE2] in {
2146 // Match fround and fextend for 128 conversions
2147 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2148 (CVTPD2PSrr VR128:$src)>;
2149 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2150 (CVTPD2PSrm addr:$src)>;
2152 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2153 (CVTPS2PDrr VR128:$src)>;
2156 //===----------------------------------------------------------------------===//
2157 // SSE 1 & 2 - Compare Instructions
2158 //===----------------------------------------------------------------------===//
2160 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2161 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2162 Operand CC, SDNode OpNode, ValueType VT,
2163 PatFrag ld_frag, string asm, string asm_alt,
2165 def rr : SIi8<0xC2, MRMSrcReg,
2166 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2167 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2169 def rm : SIi8<0xC2, MRMSrcMem,
2170 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2171 [(set RC:$dst, (OpNode (VT RC:$src1),
2172 (ld_frag addr:$src2), imm:$cc))],
2175 // Accept explicit immediate argument form instead of comparison code.
2176 let neverHasSideEffects = 1 in {
2177 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2178 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2179 IIC_SSE_ALU_F32S_RR>;
2181 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2182 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2183 IIC_SSE_ALU_F32S_RM>;
2187 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2188 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2189 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2191 XS, VEX_4V, VEX_LIG;
2192 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2193 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2194 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2195 SSE_ALU_F32S>, // same latency as 32 bit compare
2196 XD, VEX_4V, VEX_LIG;
2198 let Constraints = "$src1 = $dst" in {
2199 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2200 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2201 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2203 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2204 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2205 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2206 SSE_ALU_F32S>, // same latency as 32 bit compare
2210 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2211 Intrinsic Int, string asm, OpndItins itins> {
2212 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2213 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2214 [(set VR128:$dst, (Int VR128:$src1,
2215 VR128:$src, imm:$cc))],
2217 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2218 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2219 [(set VR128:$dst, (Int VR128:$src1,
2220 (load addr:$src), imm:$cc))],
2224 // Aliases to match intrinsics which expect XMM operand(s).
2225 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2226 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2229 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2230 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2231 SSE_ALU_F32S>, // same latency as f32
2233 let Constraints = "$src1 = $dst" in {
2234 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2235 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2237 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2238 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2239 SSE_ALU_F32S>, // same latency as f32
2244 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2245 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2246 ValueType vt, X86MemOperand x86memop,
2247 PatFrag ld_frag, string OpcodeStr, Domain d> {
2248 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2249 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2250 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2251 IIC_SSE_COMIS_RR, d>;
2252 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2253 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2254 [(set EFLAGS, (OpNode (vt RC:$src1),
2255 (ld_frag addr:$src2)))],
2256 IIC_SSE_COMIS_RM, d>;
2259 let Defs = [EFLAGS] in {
2260 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2261 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2262 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2263 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2265 let Pattern = []<dag> in {
2266 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2267 "comiss", SSEPackedSingle>, TB, VEX,
2269 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2270 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2274 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2275 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2276 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2277 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2279 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2280 load, "comiss", SSEPackedSingle>, TB, VEX;
2281 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2282 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2283 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2284 "ucomiss", SSEPackedSingle>, TB;
2285 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2286 "ucomisd", SSEPackedDouble>, TB, OpSize;
2288 let Pattern = []<dag> in {
2289 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2290 "comiss", SSEPackedSingle>, TB;
2291 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2292 "comisd", SSEPackedDouble>, TB, OpSize;
2295 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2296 load, "ucomiss", SSEPackedSingle>, TB;
2297 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2298 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2300 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2301 "comiss", SSEPackedSingle>, TB;
2302 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2303 "comisd", SSEPackedDouble>, TB, OpSize;
2304 } // Defs = [EFLAGS]
2306 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2307 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2308 Operand CC, Intrinsic Int, string asm,
2309 string asm_alt, Domain d> {
2310 def rri : PIi8<0xC2, MRMSrcReg,
2311 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2312 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2313 IIC_SSE_CMPP_RR, d>;
2314 def rmi : PIi8<0xC2, MRMSrcMem,
2315 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2316 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2317 IIC_SSE_CMPP_RM, d>;
2319 // Accept explicit immediate argument form instead of comparison code.
2320 let neverHasSideEffects = 1 in {
2321 def rri_alt : PIi8<0xC2, MRMSrcReg,
2322 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2323 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2324 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2325 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2326 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2330 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2331 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2332 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2333 SSEPackedSingle>, TB, VEX_4V;
2334 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2335 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2336 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2337 SSEPackedDouble>, TB, OpSize, VEX_4V;
2338 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2339 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2340 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2341 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2342 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2343 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2344 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2345 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2346 let Constraints = "$src1 = $dst" in {
2347 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2348 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2349 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2350 SSEPackedSingle>, TB;
2351 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2352 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2353 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2354 SSEPackedDouble>, TB, OpSize;
2357 let Predicates = [HasAVX] in {
2358 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2359 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2360 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2361 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2362 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2363 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2364 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2365 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2367 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2368 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2369 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2370 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2371 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2372 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2373 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2374 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2377 let Predicates = [UseSSE1] in {
2378 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2379 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2380 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2381 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2384 let Predicates = [UseSSE2] in {
2385 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2386 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2387 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2388 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2391 //===----------------------------------------------------------------------===//
2392 // SSE 1 & 2 - Shuffle Instructions
2393 //===----------------------------------------------------------------------===//
2395 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2396 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2397 ValueType vt, string asm, PatFrag mem_frag,
2398 Domain d, bit IsConvertibleToThreeAddress = 0> {
2399 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2400 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2401 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2402 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2403 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2404 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2405 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2406 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2407 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2410 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2411 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2412 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2413 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2414 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2415 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2416 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2417 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2418 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2419 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2420 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2421 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2423 let Constraints = "$src1 = $dst" in {
2424 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2425 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2426 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2428 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2429 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2430 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2434 let Predicates = [HasAVX] in {
2435 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2436 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2437 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2438 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2439 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2441 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2442 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2443 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2444 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2445 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2448 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2449 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2450 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2451 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2452 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2454 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2455 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2456 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2457 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2458 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2461 let Predicates = [UseSSE1] in {
2462 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2463 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2464 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2465 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2466 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2469 let Predicates = [UseSSE2] in {
2470 // Generic SHUFPD patterns
2471 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2472 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2473 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2474 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2475 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2478 //===----------------------------------------------------------------------===//
2479 // SSE 1 & 2 - Unpack Instructions
2480 //===----------------------------------------------------------------------===//
2482 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2483 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2484 PatFrag mem_frag, RegisterClass RC,
2485 X86MemOperand x86memop, string asm,
2487 def rr : PI<opc, MRMSrcReg,
2488 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2490 (vt (OpNode RC:$src1, RC:$src2)))],
2492 def rm : PI<opc, MRMSrcMem,
2493 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2495 (vt (OpNode RC:$src1,
2496 (mem_frag addr:$src2))))],
2500 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2501 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2502 SSEPackedSingle>, TB, VEX_4V;
2503 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2504 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2505 SSEPackedDouble>, TB, OpSize, VEX_4V;
2506 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2507 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2508 SSEPackedSingle>, TB, VEX_4V;
2509 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2510 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2511 SSEPackedDouble>, TB, OpSize, VEX_4V;
2513 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2514 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2515 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2516 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2517 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2518 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2519 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2520 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2521 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2522 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2523 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2524 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2526 let Constraints = "$src1 = $dst" in {
2527 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2528 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2529 SSEPackedSingle>, TB;
2530 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2531 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2532 SSEPackedDouble>, TB, OpSize;
2533 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2534 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2535 SSEPackedSingle>, TB;
2536 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2537 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2538 SSEPackedDouble>, TB, OpSize;
2539 } // Constraints = "$src1 = $dst"
2541 let Predicates = [HasAVX1Only] in {
2542 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2543 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2544 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2545 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2546 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2547 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2548 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2549 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2551 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2552 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2553 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2554 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2555 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2556 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2557 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2558 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2561 let Predicates = [HasAVX] in {
2562 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2563 // problem is during lowering, where it's not possible to recognize the load
2564 // fold cause it has two uses through a bitcast. One use disappears at isel
2565 // time and the fold opportunity reappears.
2566 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2567 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2570 let Predicates = [UseSSE2] in {
2571 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2572 // problem is during lowering, where it's not possible to recognize the load
2573 // fold cause it has two uses through a bitcast. One use disappears at isel
2574 // time and the fold opportunity reappears.
2575 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2576 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2579 //===----------------------------------------------------------------------===//
2580 // SSE 1 & 2 - Extract Floating-Point Sign mask
2581 //===----------------------------------------------------------------------===//
2583 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2584 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2586 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2587 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2588 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2589 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2590 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2591 IIC_SSE_MOVMSK, d>, REX_W;
2594 let Predicates = [HasAVX] in {
2595 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2596 "movmskps", SSEPackedSingle>, TB, VEX;
2597 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2598 "movmskpd", SSEPackedDouble>, TB,
2600 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2601 "movmskps", SSEPackedSingle>, TB,
2603 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2604 "movmskpd", SSEPackedDouble>, TB,
2607 def : Pat<(i32 (X86fgetsign FR32:$src)),
2608 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2609 def : Pat<(i64 (X86fgetsign FR32:$src)),
2610 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2611 def : Pat<(i32 (X86fgetsign FR64:$src)),
2612 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2613 def : Pat<(i64 (X86fgetsign FR64:$src)),
2614 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2617 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2618 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2619 SSEPackedSingle>, TB, VEX;
2620 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2621 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2622 SSEPackedDouble>, TB,
2624 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2625 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2626 SSEPackedSingle>, TB, VEX, VEX_L;
2627 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2628 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2629 SSEPackedDouble>, TB,
2633 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2634 SSEPackedSingle>, TB;
2635 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2636 SSEPackedDouble>, TB, OpSize;
2638 def : Pat<(i32 (X86fgetsign FR32:$src)),
2639 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2640 Requires<[UseSSE1]>;
2641 def : Pat<(i64 (X86fgetsign FR32:$src)),
2642 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2643 Requires<[UseSSE1]>;
2644 def : Pat<(i32 (X86fgetsign FR64:$src)),
2645 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2646 Requires<[UseSSE2]>;
2647 def : Pat<(i64 (X86fgetsign FR64:$src)),
2648 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2649 Requires<[UseSSE2]>;
2651 //===---------------------------------------------------------------------===//
2652 // SSE2 - Packed Integer Logical Instructions
2653 //===---------------------------------------------------------------------===//
2655 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2657 /// PDI_binop_rm - Simple SSE2 binary operator.
2658 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2659 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2660 X86MemOperand x86memop,
2662 bit IsCommutable = 0,
2664 let isCommutable = IsCommutable in
2665 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2666 (ins RC:$src1, RC:$src2),
2668 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2669 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2670 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2671 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2672 (ins RC:$src1, x86memop:$src2),
2674 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2675 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2676 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2677 (bitconvert (memop_frag addr:$src2)))))],
2680 } // ExeDomain = SSEPackedInt
2682 // These are ordered here for pattern ordering requirements with the fp versions
2684 let Predicates = [HasAVX] in {
2685 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2686 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2687 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2688 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2689 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2690 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2691 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2692 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2695 let Constraints = "$src1 = $dst" in {
2696 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2697 i128mem, SSE_BIT_ITINS_P, 1>;
2698 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2699 i128mem, SSE_BIT_ITINS_P, 1>;
2700 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2701 i128mem, SSE_BIT_ITINS_P, 1>;
2702 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2703 i128mem, SSE_BIT_ITINS_P, 0>;
2704 } // Constraints = "$src1 = $dst"
2706 let Predicates = [HasAVX2] in {
2707 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2708 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
2709 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2710 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
2711 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2712 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
2713 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2714 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V, VEX_L;
2717 //===----------------------------------------------------------------------===//
2718 // SSE 1 & 2 - Logical Instructions
2719 //===----------------------------------------------------------------------===//
2721 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2723 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2724 SDNode OpNode, OpndItins itins> {
2725 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2726 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2729 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2730 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2733 let Constraints = "$src1 = $dst" in {
2734 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2735 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2738 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2739 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2744 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2745 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2747 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2749 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2752 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2753 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2756 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2758 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2760 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2761 // are all promoted to v2i64, and the patterns are covered by the int
2762 // version. This is needed in SSE only, because v2i64 isn't supported on
2763 // SSE1, but only on SSE2.
2764 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2765 !strconcat(OpcodeStr, "ps"), f128mem, [],
2766 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2767 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2769 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2770 !strconcat(OpcodeStr, "pd"), f128mem,
2771 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2772 (bc_v2i64 (v2f64 VR128:$src2))))],
2773 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2774 (memopv2i64 addr:$src2)))], 0>,
2776 let Constraints = "$src1 = $dst" in {
2777 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2778 !strconcat(OpcodeStr, "ps"), f128mem,
2779 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2780 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2781 (memopv2i64 addr:$src2)))]>, TB;
2783 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2784 !strconcat(OpcodeStr, "pd"), f128mem,
2785 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2786 (bc_v2i64 (v2f64 VR128:$src2))))],
2787 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2788 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2792 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2794 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2796 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2797 !strconcat(OpcodeStr, "ps"), f256mem,
2798 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2799 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2800 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2802 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2803 !strconcat(OpcodeStr, "pd"), f256mem,
2804 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2805 (bc_v4i64 (v4f64 VR256:$src2))))],
2806 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2807 (memopv4i64 addr:$src2)))], 0>,
2808 TB, OpSize, VEX_4V, VEX_L;
2811 // AVX 256-bit packed logical ops forms
2812 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2813 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2814 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2815 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2817 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2818 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2819 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2820 let isCommutable = 0 in
2821 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2823 //===----------------------------------------------------------------------===//
2824 // SSE 1 & 2 - Arithmetic Instructions
2825 //===----------------------------------------------------------------------===//
2827 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2830 /// In addition, we also have a special variant of the scalar form here to
2831 /// represent the associated intrinsic operation. This form is unlike the
2832 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2833 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2835 /// These three forms can each be reg+reg or reg+mem.
2838 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2840 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2843 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2844 OpNode, FR32, f32mem,
2845 itins.s, Is2Addr>, XS;
2846 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2847 OpNode, FR64, f64mem,
2848 itins.d, Is2Addr>, XD;
2851 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2854 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2855 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2857 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2858 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2862 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2865 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2866 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2868 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2869 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2873 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2876 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2877 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2878 itins.s, Is2Addr>, XS;
2879 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2880 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2881 itins.d, Is2Addr>, XD;
2884 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2887 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2888 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2889 SSEPackedSingle, itins.s, Is2Addr>,
2892 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2893 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2894 SSEPackedDouble, itins.d, Is2Addr>,
2898 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2900 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2901 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2902 SSEPackedSingle, itins.s, 0>, TB, VEX_L;
2904 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2905 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2906 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_L;
2909 // Binary Arithmetic instructions
2910 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2911 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2913 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2914 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2916 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2917 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2919 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2920 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2923 let isCommutable = 0 in {
2924 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2925 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2927 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2928 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2930 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2931 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2933 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2934 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2936 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2937 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2939 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2940 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2941 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2942 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2944 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2945 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2947 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2948 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2949 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2950 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2954 let Constraints = "$src1 = $dst" in {
2955 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2956 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2957 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2958 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2959 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2960 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2962 let isCommutable = 0 in {
2963 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2964 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2965 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2966 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2967 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2968 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2969 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2970 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2971 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2972 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2973 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2974 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2975 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2976 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2980 let isCodeGenOnly = 1 in {
2981 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
2983 defm VMAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P, 0>,
2984 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>, VEX_4V;
2985 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
2987 defm VMINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P, 0>,
2988 basic_sse12_fp_binop_p_y<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>, VEX_4V;
2989 let Constraints = "$src1 = $dst" in {
2990 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>,
2991 basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2992 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>,
2993 basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2998 /// In addition, we also have a special variant of the scalar form here to
2999 /// represent the associated intrinsic operation. This form is unlike the
3000 /// plain scalar form, in that it takes an entire vector (instead of a
3001 /// scalar) and leaves the top elements undefined.
3003 /// And, we have a special variant form for a full-vector intrinsic form.
3005 def SSE_SQRTP : OpndItins<
3006 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
3009 def SSE_SQRTS : OpndItins<
3010 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
3013 def SSE_RCPP : OpndItins<
3014 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3017 def SSE_RCPS : OpndItins<
3018 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3021 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3022 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3023 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3024 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3025 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3026 [(set FR32:$dst, (OpNode FR32:$src))]>;
3027 // For scalar unary operations, fold a load into the operation
3028 // only in OptForSize mode. It eliminates an instruction, but it also
3029 // eliminates a whole-register clobber (the load), so it introduces a
3030 // partial register update condition.
3031 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3032 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3033 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3034 Requires<[UseSSE1, OptForSize]>;
3035 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3036 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3037 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3038 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3039 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3040 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3043 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3044 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3045 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3046 !strconcat(OpcodeStr,
3047 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3048 let mayLoad = 1 in {
3049 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3050 !strconcat(OpcodeStr,
3051 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3052 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3053 (ins VR128:$src1, ssmem:$src2),
3054 !strconcat(OpcodeStr,
3055 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3059 /// sse1_fp_unop_p - SSE1 unops in packed form.
3060 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3062 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3063 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3064 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3065 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3066 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3067 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3070 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3071 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3073 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3074 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3075 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3077 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3078 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3079 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3083 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3084 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3085 Intrinsic V4F32Int, OpndItins itins> {
3086 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3087 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3088 [(set VR128:$dst, (V4F32Int VR128:$src))],
3090 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3091 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3092 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3096 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3097 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3098 Intrinsic V4F32Int, OpndItins itins> {
3099 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3100 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3101 [(set VR256:$dst, (V4F32Int VR256:$src))],
3103 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3104 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3105 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3109 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3110 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3111 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3112 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3113 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3114 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3115 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3116 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3117 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3118 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3119 Requires<[UseSSE2, OptForSize]>;
3120 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3121 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3122 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3123 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3124 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3125 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3128 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3129 let hasSideEffects = 0 in
3130 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3131 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3132 !strconcat(OpcodeStr,
3133 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3134 let mayLoad = 1 in {
3135 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3136 !strconcat(OpcodeStr,
3137 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3138 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3139 (ins VR128:$src1, sdmem:$src2),
3140 !strconcat(OpcodeStr,
3141 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3145 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3146 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3147 SDNode OpNode, OpndItins itins> {
3148 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3149 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3150 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3151 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3152 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3153 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3156 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3157 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3159 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3160 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3161 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3163 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3164 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3165 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3169 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3170 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3171 Intrinsic V2F64Int, OpndItins itins> {
3172 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3173 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3174 [(set VR128:$dst, (V2F64Int VR128:$src))],
3176 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3177 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3178 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3182 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3183 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3184 Intrinsic V2F64Int, OpndItins itins> {
3185 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3186 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3187 [(set VR256:$dst, (V2F64Int VR256:$src))],
3189 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3190 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3191 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3195 let Predicates = [HasAVX] in {
3197 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3198 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3200 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3201 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3202 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3203 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3204 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3206 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3208 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3210 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3214 // Reciprocal approximations. Note that these typically require refinement
3215 // in order to obtain suitable precision.
3216 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3217 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3218 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3219 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3221 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3224 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3225 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3226 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3227 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3229 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3233 def : Pat<(f32 (fsqrt FR32:$src)),
3234 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3235 def : Pat<(f32 (fsqrt (load addr:$src))),
3236 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3237 Requires<[HasAVX, OptForSize]>;
3238 def : Pat<(f64 (fsqrt FR64:$src)),
3239 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3240 def : Pat<(f64 (fsqrt (load addr:$src))),
3241 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3242 Requires<[HasAVX, OptForSize]>;
3244 def : Pat<(f32 (X86frsqrt FR32:$src)),
3245 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3246 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3247 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3248 Requires<[HasAVX, OptForSize]>;
3250 def : Pat<(f32 (X86frcp FR32:$src)),
3251 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3252 def : Pat<(f32 (X86frcp (load addr:$src))),
3253 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3254 Requires<[HasAVX, OptForSize]>;
3256 let Predicates = [HasAVX] in {
3257 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3258 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3259 (COPY_TO_REGCLASS VR128:$src, FR32)),
3261 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3262 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3264 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3265 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3266 (COPY_TO_REGCLASS VR128:$src, FR64)),
3268 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3269 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3271 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3272 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3273 (COPY_TO_REGCLASS VR128:$src, FR32)),
3275 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3276 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3278 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3279 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3280 (COPY_TO_REGCLASS VR128:$src, FR32)),
3282 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3283 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3287 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3289 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3290 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3291 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3293 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3294 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3296 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3297 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3298 Intrinsic F32Int, OpndItins itins> {
3299 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3300 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3301 [(set FR32:$dst, (OpNode FR32:$src))]>;
3302 // For scalar unary operations, fold a load into the operation
3303 // only in OptForSize mode. It eliminates an instruction, but it also
3304 // eliminates a whole-register clobber (the load), so it introduces a
3305 // partial register update condition.
3306 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3307 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3308 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3309 Requires<[UseSSE1, OptForSize]>;
3310 let Constraints = "$src1 = $dst" in {
3311 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3312 (ins VR128:$src1, VR128:$src2),
3313 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3315 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3316 (ins VR128:$src1, ssmem:$src2),
3317 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3322 // Reciprocal approximations. Note that these typically require refinement
3323 // in order to obtain suitable precision.
3324 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3326 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3327 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3329 let Predicates = [UseSSE1] in {
3330 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3331 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3334 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3336 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3337 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3338 let Predicates = [UseSSE1] in {
3339 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3340 (RCPSSr_Int VR128:$src, VR128:$src)>;
3343 // There is no f64 version of the reciprocal approximation instructions.
3345 //===----------------------------------------------------------------------===//
3346 // SSE 1 & 2 - Non-temporal stores
3347 //===----------------------------------------------------------------------===//
3349 let AddedComplexity = 400 in { // Prefer non-temporal versions
3350 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3351 (ins f128mem:$dst, VR128:$src),
3352 "movntps\t{$src, $dst|$dst, $src}",
3353 [(alignednontemporalstore (v4f32 VR128:$src),
3355 IIC_SSE_MOVNT>, VEX;
3356 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3357 (ins f128mem:$dst, VR128:$src),
3358 "movntpd\t{$src, $dst|$dst, $src}",
3359 [(alignednontemporalstore (v2f64 VR128:$src),
3361 IIC_SSE_MOVNT>, VEX;
3363 let ExeDomain = SSEPackedInt in
3364 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3365 (ins f128mem:$dst, VR128:$src),
3366 "movntdq\t{$src, $dst|$dst, $src}",
3367 [(alignednontemporalstore (v2i64 VR128:$src),
3369 IIC_SSE_MOVNT>, VEX;
3371 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3372 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3374 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3375 (ins f256mem:$dst, VR256:$src),
3376 "movntps\t{$src, $dst|$dst, $src}",
3377 [(alignednontemporalstore (v8f32 VR256:$src),
3379 IIC_SSE_MOVNT>, VEX, VEX_L;
3380 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3381 (ins f256mem:$dst, VR256:$src),
3382 "movntpd\t{$src, $dst|$dst, $src}",
3383 [(alignednontemporalstore (v4f64 VR256:$src),
3385 IIC_SSE_MOVNT>, VEX, VEX_L;
3386 let ExeDomain = SSEPackedInt in
3387 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3388 (ins f256mem:$dst, VR256:$src),
3389 "movntdq\t{$src, $dst|$dst, $src}",
3390 [(alignednontemporalstore (v4i64 VR256:$src),
3392 IIC_SSE_MOVNT>, VEX, VEX_L;
3395 let AddedComplexity = 400 in { // Prefer non-temporal versions
3396 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3397 "movntps\t{$src, $dst|$dst, $src}",
3398 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3400 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3401 "movntpd\t{$src, $dst|$dst, $src}",
3402 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3405 let ExeDomain = SSEPackedInt in
3406 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3407 "movntdq\t{$src, $dst|$dst, $src}",
3408 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3411 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3412 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3414 // There is no AVX form for instructions below this point
3415 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3416 "movnti{l}\t{$src, $dst|$dst, $src}",
3417 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3419 TB, Requires<[HasSSE2]>;
3420 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3421 "movnti{q}\t{$src, $dst|$dst, $src}",
3422 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3424 TB, Requires<[HasSSE2]>;
3427 //===----------------------------------------------------------------------===//
3428 // SSE 1 & 2 - Prefetch and memory fence
3429 //===----------------------------------------------------------------------===//
3431 // Prefetch intrinsic.
3432 let Predicates = [HasSSE1] in {
3433 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3434 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3435 IIC_SSE_PREFETCH>, TB;
3436 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3437 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3438 IIC_SSE_PREFETCH>, TB;
3439 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3440 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3441 IIC_SSE_PREFETCH>, TB;
3442 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3443 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3444 IIC_SSE_PREFETCH>, TB;
3448 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3449 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3450 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3452 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3453 // was introduced with SSE2, it's backward compatible.
3454 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3456 // Load, store, and memory fence
3457 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3458 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3459 TB, Requires<[HasSSE1]>;
3460 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3461 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3462 TB, Requires<[HasSSE2]>;
3463 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3464 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3465 TB, Requires<[HasSSE2]>;
3467 def : Pat<(X86SFence), (SFENCE)>;
3468 def : Pat<(X86LFence), (LFENCE)>;
3469 def : Pat<(X86MFence), (MFENCE)>;
3471 //===----------------------------------------------------------------------===//
3472 // SSE 1 & 2 - Load/Store XCSR register
3473 //===----------------------------------------------------------------------===//
3475 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3476 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3477 IIC_SSE_LDMXCSR>, VEX;
3478 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3479 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3480 IIC_SSE_STMXCSR>, VEX;
3482 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3483 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3485 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3486 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3489 //===---------------------------------------------------------------------===//
3490 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3491 //===---------------------------------------------------------------------===//
3493 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3495 let neverHasSideEffects = 1 in {
3496 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3497 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3499 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3500 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3502 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3503 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3505 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3506 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3511 let isCodeGenOnly = 1 in {
3512 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3513 "movdqa\t{$src, $dst|$dst, $src}", [],
3516 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3517 "movdqa\t{$src, $dst|$dst, $src}", [],
3518 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3519 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3520 "movdqu\t{$src, $dst|$dst, $src}", [],
3523 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3524 "movdqu\t{$src, $dst|$dst, $src}", [],
3525 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3528 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3529 neverHasSideEffects = 1 in {
3530 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3531 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3533 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3534 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3536 let Predicates = [HasAVX] in {
3537 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3538 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3540 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3541 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3546 let mayStore = 1, neverHasSideEffects = 1 in {
3547 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3548 (ins i128mem:$dst, VR128:$src),
3549 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3551 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3552 (ins i256mem:$dst, VR256:$src),
3553 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3555 let Predicates = [HasAVX] in {
3556 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3557 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3559 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3560 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3565 let neverHasSideEffects = 1 in
3566 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3567 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3569 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3570 "movdqu\t{$src, $dst|$dst, $src}",
3571 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3574 let isCodeGenOnly = 1 in {
3575 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3576 "movdqa\t{$src, $dst|$dst, $src}", [],
3579 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3580 "movdqu\t{$src, $dst|$dst, $src}",
3581 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3584 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3585 neverHasSideEffects = 1 in {
3586 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3587 "movdqa\t{$src, $dst|$dst, $src}",
3588 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3590 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3591 "movdqu\t{$src, $dst|$dst, $src}",
3592 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3594 XS, Requires<[UseSSE2]>;
3597 let mayStore = 1 in {
3598 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3599 "movdqa\t{$src, $dst|$dst, $src}",
3600 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3602 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3603 "movdqu\t{$src, $dst|$dst, $src}",
3604 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3606 XS, Requires<[UseSSE2]>;
3609 } // ExeDomain = SSEPackedInt
3611 let Predicates = [HasAVX] in {
3612 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3613 (VMOVDQUmr addr:$dst, VR128:$src)>;
3614 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3615 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3617 let Predicates = [UseSSE2] in
3618 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3619 (MOVDQUmr addr:$dst, VR128:$src)>;
3621 //===---------------------------------------------------------------------===//
3622 // SSE2 - Packed Integer Arithmetic Instructions
3623 //===---------------------------------------------------------------------===//
3625 def SSE_PMADD : OpndItins<
3626 IIC_SSE_PMADD, IIC_SSE_PMADD
3629 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3631 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3632 RegisterClass RC, PatFrag memop_frag,
3633 X86MemOperand x86memop,
3635 bit IsCommutable = 0,
3637 let isCommutable = IsCommutable in
3638 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3639 (ins RC:$src1, RC:$src2),
3641 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3642 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3643 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3644 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3645 (ins RC:$src1, x86memop:$src2),
3647 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3648 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3649 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3653 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3654 string OpcodeStr, SDNode OpNode,
3655 SDNode OpNode2, RegisterClass RC,
3656 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3657 ShiftOpndItins itins,
3659 // src2 is always 128-bit
3660 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3661 (ins RC:$src1, VR128:$src2),
3663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3664 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3665 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3667 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3668 (ins RC:$src1, i128mem:$src2),
3670 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3671 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3672 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3673 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3674 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3675 (ins RC:$src1, i32i8imm:$src2),
3677 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3678 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3679 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3682 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3683 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3684 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3685 PatFrag memop_frag, X86MemOperand x86memop,
3687 bit IsCommutable = 0, bit Is2Addr = 1> {
3688 let isCommutable = IsCommutable in
3689 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3690 (ins RC:$src1, RC:$src2),
3692 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3693 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3694 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3695 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3696 (ins RC:$src1, x86memop:$src2),
3698 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3699 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3700 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3701 (bitconvert (memop_frag addr:$src2)))))]>;
3703 } // ExeDomain = SSEPackedInt
3705 // 128-bit Integer Arithmetic
3707 let Predicates = [HasAVX] in {
3708 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3709 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3711 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3712 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3713 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3714 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3715 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3716 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3717 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3718 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3719 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3720 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3721 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3722 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3723 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3724 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3725 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3726 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3727 defm VPSUBUSB : PDI_binop_rm<0xD8, "vpsubusb", X86subus, v16i8, VR128,
3728 memopv2i64, i128mem, SSE_INTALU_ITINS_P, 0, 0>,
3730 defm VPSUBUSW : PDI_binop_rm<0xD9, "vpsubusw", X86subus, v8i16, VR128,
3731 memopv2i64, i128mem, SSE_INTALU_ITINS_P, 0, 0>,
3733 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3734 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3736 defm VPMINUB : PDI_binop_rm<0xDA, "vpminub", X86umin, v16i8, VR128, memopv2i64,
3737 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3738 defm VPMINSW : PDI_binop_rm<0xEA, "vpminsw", X86smin, v8i16, VR128, memopv2i64,
3739 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3740 defm VPMAXUB : PDI_binop_rm<0xDE, "vpmaxub", X86umax, v16i8, VR128, memopv2i64,
3741 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3742 defm VPMAXSW : PDI_binop_rm<0xEE, "vpmaxsw", X86smax, v8i16, VR128, memopv2i64,
3743 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3746 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3747 VR128, memopv2i64, i128mem,
3748 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3749 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3750 VR128, memopv2i64, i128mem,
3751 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3752 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3753 VR128, memopv2i64, i128mem,
3754 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3755 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3756 VR128, memopv2i64, i128mem,
3757 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3758 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3759 VR128, memopv2i64, i128mem,
3760 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3761 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3762 VR128, memopv2i64, i128mem,
3763 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3764 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3765 VR128, memopv2i64, i128mem,
3766 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3767 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3768 VR128, memopv2i64, i128mem,
3769 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3770 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3771 VR128, memopv2i64, i128mem,
3772 SSE_PMADD, 1, 0>, VEX_4V;
3773 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3774 VR128, memopv2i64, i128mem,
3775 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3776 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3777 VR128, memopv2i64, i128mem,
3778 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3779 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3780 VR128, memopv2i64, i128mem,
3781 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3784 let Predicates = [HasAVX2] in {
3785 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3786 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3787 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3788 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3789 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3790 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3791 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3792 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3793 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3794 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3795 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3796 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3797 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3798 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3799 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3800 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3801 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3802 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3803 defm VPSUBUSBY : PDI_binop_rm<0xD8, "vpsubusb", X86subus, v32i8, VR256,
3804 memopv4i64, i256mem, SSE_INTALU_ITINS_P, 0, 0>,
3806 defm VPSUBUSWY : PDI_binop_rm<0xD9, "vpsubusw", X86subus, v16i16, VR256,
3807 memopv4i64, i256mem, SSE_INTALU_ITINS_P, 0, 0>,
3809 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3810 VR256, memopv4i64, i256mem,
3811 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3812 defm VPMINUBY : PDI_binop_rm<0xDA, "vpminub", X86umin, v32i8,
3813 VR256, memopv4i64, i256mem,
3814 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3815 defm VPMINSWY : PDI_binop_rm<0xEA, "vpminsw", X86smin, v16i16,
3816 VR256, memopv4i64, i256mem,
3817 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3818 defm VPMAXUBY : PDI_binop_rm<0xDE, "vpmaxub", X86umax, v32i8,
3819 VR256, memopv4i64, i256mem,
3820 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3821 defm VPMAXSWY : PDI_binop_rm<0xEE, "vpmaxsw", X86smax, v16i16,
3822 VR256, memopv4i64, i256mem,
3823 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3826 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3827 VR256, memopv4i64, i256mem,
3828 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3829 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3830 VR256, memopv4i64, i256mem,
3831 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3832 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3833 VR256, memopv4i64, i256mem,
3834 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3835 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3836 VR256, memopv4i64, i256mem,
3837 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3838 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3839 VR256, memopv4i64, i256mem,
3840 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3841 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3842 VR256, memopv4i64, i256mem,
3843 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3844 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3845 VR256, memopv4i64, i256mem,
3846 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3847 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3848 VR256, memopv4i64, i256mem,
3849 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3850 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3851 VR256, memopv4i64, i256mem,
3852 SSE_PMADD, 1, 0>, VEX_4V, VEX_L;
3853 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3854 VR256, memopv4i64, i256mem,
3855 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3856 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3857 VR256, memopv4i64, i256mem,
3858 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3859 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3860 VR256, memopv4i64, i256mem,
3861 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3864 let Constraints = "$src1 = $dst" in {
3865 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3866 i128mem, SSE_INTALU_ITINS_P, 1>;
3867 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3868 i128mem, SSE_INTALU_ITINS_P, 1>;
3869 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3870 i128mem, SSE_INTALU_ITINS_P, 1>;
3871 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3872 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3873 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3874 i128mem, SSE_INTMUL_ITINS_P, 1>;
3875 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3876 i128mem, SSE_INTALU_ITINS_P>;
3877 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3878 i128mem, SSE_INTALU_ITINS_P>;
3879 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3880 i128mem, SSE_INTALU_ITINS_P>;
3881 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3882 i128mem, SSE_INTALUQ_ITINS_P>;
3883 defm PSUBUSB : PDI_binop_rm<0xD8, "psubusb", X86subus, v16i8, VR128, memopv2i64,
3884 i128mem, SSE_INTALU_ITINS_P>;
3885 defm PSUBUSW : PDI_binop_rm<0xD9, "psubusw", X86subus, v8i16, VR128, memopv2i64,
3886 i128mem, SSE_INTALU_ITINS_P>;
3887 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3888 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3889 defm PMINUB : PDI_binop_rm<0xDA, "pminub", X86umin, v16i8, VR128, memopv2i64,
3890 i128mem, SSE_INTALU_ITINS_P, 1>;
3891 defm PMINSW : PDI_binop_rm<0xEA, "pminsw", X86smin, v8i16, VR128, memopv2i64,
3892 i128mem, SSE_INTALU_ITINS_P, 1>;
3893 defm PMAXUB : PDI_binop_rm<0xDE, "pmaxub", X86umax, v16i8, VR128, memopv2i64,
3894 i128mem, SSE_INTALU_ITINS_P, 1>;
3895 defm PMAXSW : PDI_binop_rm<0xEE, "pmaxsw", X86smax, v8i16, VR128, memopv2i64,
3896 i128mem, SSE_INTALU_ITINS_P, 1>;
3899 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3900 VR128, memopv2i64, i128mem,
3901 SSE_INTALU_ITINS_P>;
3902 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3903 VR128, memopv2i64, i128mem,
3904 SSE_INTALU_ITINS_P>;
3905 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3906 VR128, memopv2i64, i128mem,
3907 SSE_INTALU_ITINS_P, 1>;
3908 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3909 VR128, memopv2i64, i128mem,
3910 SSE_INTALU_ITINS_P, 1>;
3911 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3912 VR128, memopv2i64, i128mem,
3913 SSE_INTALU_ITINS_P, 1>;
3914 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3915 VR128, memopv2i64, i128mem,
3916 SSE_INTALU_ITINS_P, 1>;
3917 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3918 VR128, memopv2i64, i128mem,
3919 SSE_INTMUL_ITINS_P, 1>;
3920 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3921 VR128, memopv2i64, i128mem,
3922 SSE_INTMUL_ITINS_P, 1>;
3923 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3924 VR128, memopv2i64, i128mem,
3926 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3927 VR128, memopv2i64, i128mem,
3928 SSE_INTALU_ITINS_P, 1>;
3929 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3930 VR128, memopv2i64, i128mem,
3931 SSE_INTALU_ITINS_P, 1>;
3932 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3933 VR128, memopv2i64, i128mem,
3934 SSE_INTALU_ITINS_P, 1>;
3936 } // Constraints = "$src1 = $dst"
3938 //===---------------------------------------------------------------------===//
3939 // SSE2 - Packed Integer Logical Instructions
3940 //===---------------------------------------------------------------------===//
3942 let Predicates = [HasAVX] in {
3943 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3944 VR128, v8i16, v8i16, bc_v8i16,
3945 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3946 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3947 VR128, v4i32, v4i32, bc_v4i32,
3948 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3949 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3950 VR128, v2i64, v2i64, bc_v2i64,
3951 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3953 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3954 VR128, v8i16, v8i16, bc_v8i16,
3955 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3956 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3957 VR128, v4i32, v4i32, bc_v4i32,
3958 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3959 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3960 VR128, v2i64, v2i64, bc_v2i64,
3961 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3963 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3964 VR128, v8i16, v8i16, bc_v8i16,
3965 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3966 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3967 VR128, v4i32, v4i32, bc_v4i32,
3968 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3970 let ExeDomain = SSEPackedInt in {
3971 // 128-bit logical shifts.
3972 def VPSLLDQri : PDIi8<0x73, MRM7r,
3973 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3974 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3976 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3978 def VPSRLDQri : PDIi8<0x73, MRM3r,
3979 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3980 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3982 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3984 // PSRADQri doesn't exist in SSE[1-3].
3986 } // Predicates = [HasAVX]
3988 let Predicates = [HasAVX2] in {
3989 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3990 VR256, v16i16, v8i16, bc_v8i16,
3991 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3992 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3993 VR256, v8i32, v4i32, bc_v4i32,
3994 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3995 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3996 VR256, v4i64, v2i64, bc_v2i64,
3997 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3999 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4000 VR256, v16i16, v8i16, bc_v8i16,
4001 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4002 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4003 VR256, v8i32, v4i32, bc_v4i32,
4004 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4005 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4006 VR256, v4i64, v2i64, bc_v2i64,
4007 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4009 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4010 VR256, v16i16, v8i16, bc_v8i16,
4011 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4012 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4013 VR256, v8i32, v4i32, bc_v4i32,
4014 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4016 let ExeDomain = SSEPackedInt in {
4017 // 256-bit logical shifts.
4018 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4019 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4020 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4022 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4024 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4025 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4026 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4028 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4030 // PSRADQYri doesn't exist in SSE[1-3].
4032 } // Predicates = [HasAVX2]
4034 let Constraints = "$src1 = $dst" in {
4035 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4036 VR128, v8i16, v8i16, bc_v8i16,
4037 SSE_INTSHIFT_ITINS_P>;
4038 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4039 VR128, v4i32, v4i32, bc_v4i32,
4040 SSE_INTSHIFT_ITINS_P>;
4041 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4042 VR128, v2i64, v2i64, bc_v2i64,
4043 SSE_INTSHIFT_ITINS_P>;
4045 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4046 VR128, v8i16, v8i16, bc_v8i16,
4047 SSE_INTSHIFT_ITINS_P>;
4048 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4049 VR128, v4i32, v4i32, bc_v4i32,
4050 SSE_INTSHIFT_ITINS_P>;
4051 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4052 VR128, v2i64, v2i64, bc_v2i64,
4053 SSE_INTSHIFT_ITINS_P>;
4055 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4056 VR128, v8i16, v8i16, bc_v8i16,
4057 SSE_INTSHIFT_ITINS_P>;
4058 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4059 VR128, v4i32, v4i32, bc_v4i32,
4060 SSE_INTSHIFT_ITINS_P>;
4062 let ExeDomain = SSEPackedInt in {
4063 // 128-bit logical shifts.
4064 def PSLLDQri : PDIi8<0x73, MRM7r,
4065 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4066 "pslldq\t{$src2, $dst|$dst, $src2}",
4068 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4069 def PSRLDQri : PDIi8<0x73, MRM3r,
4070 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4071 "psrldq\t{$src2, $dst|$dst, $src2}",
4073 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4074 // PSRADQri doesn't exist in SSE[1-3].
4076 } // Constraints = "$src1 = $dst"
4078 let Predicates = [HasAVX] in {
4079 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4080 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4081 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4082 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4083 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4084 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4086 // Shift up / down and insert zero's.
4087 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4088 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4089 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4090 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4093 let Predicates = [HasAVX2] in {
4094 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4095 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4096 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4097 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4100 let Predicates = [UseSSE2] in {
4101 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4102 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4103 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4104 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4105 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4106 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4108 // Shift up / down and insert zero's.
4109 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4110 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4111 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4112 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4115 //===---------------------------------------------------------------------===//
4116 // SSE2 - Packed Integer Comparison Instructions
4117 //===---------------------------------------------------------------------===//
4119 let Predicates = [HasAVX] in {
4120 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4121 VR128, memopv2i64, i128mem,
4122 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4123 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4124 VR128, memopv2i64, i128mem,
4125 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4126 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4127 VR128, memopv2i64, i128mem,
4128 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4129 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4130 VR128, memopv2i64, i128mem,
4131 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4132 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4133 VR128, memopv2i64, i128mem,
4134 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4135 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4136 VR128, memopv2i64, i128mem,
4137 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4140 let Predicates = [HasAVX2] in {
4141 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4142 VR256, memopv4i64, i256mem,
4143 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4144 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4145 VR256, memopv4i64, i256mem,
4146 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4147 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4148 VR256, memopv4i64, i256mem,
4149 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4150 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4151 VR256, memopv4i64, i256mem,
4152 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4153 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4154 VR256, memopv4i64, i256mem,
4155 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4156 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4157 VR256, memopv4i64, i256mem,
4158 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4161 let Constraints = "$src1 = $dst" in {
4162 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4163 VR128, memopv2i64, i128mem,
4164 SSE_INTALU_ITINS_P, 1>;
4165 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4166 VR128, memopv2i64, i128mem,
4167 SSE_INTALU_ITINS_P, 1>;
4168 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4169 VR128, memopv2i64, i128mem,
4170 SSE_INTALU_ITINS_P, 1>;
4171 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4172 VR128, memopv2i64, i128mem,
4173 SSE_INTALU_ITINS_P>;
4174 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4175 VR128, memopv2i64, i128mem,
4176 SSE_INTALU_ITINS_P>;
4177 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4178 VR128, memopv2i64, i128mem,
4179 SSE_INTALU_ITINS_P>;
4180 } // Constraints = "$src1 = $dst"
4182 //===---------------------------------------------------------------------===//
4183 // SSE2 - Packed Integer Pack Instructions
4184 //===---------------------------------------------------------------------===//
4186 let Predicates = [HasAVX] in {
4187 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4188 VR128, memopv2i64, i128mem,
4189 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4190 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4191 VR128, memopv2i64, i128mem,
4192 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4193 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4194 VR128, memopv2i64, i128mem,
4195 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4198 let Predicates = [HasAVX2] in {
4199 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4200 VR256, memopv4i64, i256mem,
4201 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4202 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4203 VR256, memopv4i64, i256mem,
4204 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4205 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4206 VR256, memopv4i64, i256mem,
4207 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4210 let Constraints = "$src1 = $dst" in {
4211 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4212 VR128, memopv2i64, i128mem,
4213 SSE_INTALU_ITINS_P>;
4214 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4215 VR128, memopv2i64, i128mem,
4216 SSE_INTALU_ITINS_P>;
4217 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4218 VR128, memopv2i64, i128mem,
4219 SSE_INTALU_ITINS_P>;
4220 } // Constraints = "$src1 = $dst"
4222 //===---------------------------------------------------------------------===//
4223 // SSE2 - Packed Integer Shuffle Instructions
4224 //===---------------------------------------------------------------------===//
4226 let ExeDomain = SSEPackedInt in {
4227 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4228 def ri : Ii8<0x70, MRMSrcReg,
4229 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4230 !strconcat(OpcodeStr,
4231 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4232 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4234 def mi : Ii8<0x70, MRMSrcMem,
4235 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4236 !strconcat(OpcodeStr,
4237 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4239 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4244 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4245 def Yri : Ii8<0x70, MRMSrcReg,
4246 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4247 !strconcat(OpcodeStr,
4248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4249 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4250 def Ymi : Ii8<0x70, MRMSrcMem,
4251 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4252 !strconcat(OpcodeStr,
4253 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4255 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4256 (i8 imm:$src2))))]>;
4258 } // ExeDomain = SSEPackedInt
4260 let Predicates = [HasAVX] in {
4261 let AddedComplexity = 5 in
4262 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4264 // SSE2 with ImmT == Imm8 and XS prefix.
4265 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4267 // SSE2 with ImmT == Imm8 and XD prefix.
4268 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4270 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4271 (VPSHUFDmi addr:$src1, imm:$imm)>;
4272 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4273 (VPSHUFDri VR128:$src1, imm:$imm)>;
4276 let Predicates = [HasAVX2] in {
4277 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>,
4278 TB, OpSize, VEX,VEX_L;
4279 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>,
4281 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>,
4285 let Predicates = [UseSSE2] in {
4286 let AddedComplexity = 5 in
4287 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4289 // SSE2 with ImmT == Imm8 and XS prefix.
4290 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4292 // SSE2 with ImmT == Imm8 and XD prefix.
4293 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4295 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4296 (PSHUFDmi addr:$src1, imm:$imm)>;
4297 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4298 (PSHUFDri VR128:$src1, imm:$imm)>;
4301 //===---------------------------------------------------------------------===//
4302 // SSE2 - Packed Integer Unpack Instructions
4303 //===---------------------------------------------------------------------===//
4305 let ExeDomain = SSEPackedInt in {
4306 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4307 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4308 def rr : PDI<opc, MRMSrcReg,
4309 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4311 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4312 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4313 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4315 def rm : PDI<opc, MRMSrcMem,
4316 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4318 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4319 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4320 [(set VR128:$dst, (OpNode VR128:$src1,
4321 (bc_frag (memopv2i64
4326 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4327 SDNode OpNode, PatFrag bc_frag> {
4328 def Yrr : PDI<opc, MRMSrcReg,
4329 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4330 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4331 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4332 def Yrm : PDI<opc, MRMSrcMem,
4333 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4334 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4335 [(set VR256:$dst, (OpNode VR256:$src1,
4336 (bc_frag (memopv4i64 addr:$src2))))]>;
4339 let Predicates = [HasAVX] in {
4340 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4341 bc_v16i8, 0>, VEX_4V;
4342 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4343 bc_v8i16, 0>, VEX_4V;
4344 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4345 bc_v4i32, 0>, VEX_4V;
4346 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4347 bc_v2i64, 0>, VEX_4V;
4349 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4350 bc_v16i8, 0>, VEX_4V;
4351 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4352 bc_v8i16, 0>, VEX_4V;
4353 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4354 bc_v4i32, 0>, VEX_4V;
4355 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4356 bc_v2i64, 0>, VEX_4V;
4359 let Predicates = [HasAVX2] in {
4360 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4361 bc_v32i8>, VEX_4V, VEX_L;
4362 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4363 bc_v16i16>, VEX_4V, VEX_L;
4364 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4365 bc_v8i32>, VEX_4V, VEX_L;
4366 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4367 bc_v4i64>, VEX_4V, VEX_L;
4369 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4370 bc_v32i8>, VEX_4V, VEX_L;
4371 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4372 bc_v16i16>, VEX_4V, VEX_L;
4373 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4374 bc_v8i32>, VEX_4V, VEX_L;
4375 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4376 bc_v4i64>, VEX_4V, VEX_L;
4379 let Constraints = "$src1 = $dst" in {
4380 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4382 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4384 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4386 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4389 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4391 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4393 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4395 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4398 } // ExeDomain = SSEPackedInt
4400 //===---------------------------------------------------------------------===//
4401 // SSE2 - Packed Integer Extract and Insert
4402 //===---------------------------------------------------------------------===//
4404 let ExeDomain = SSEPackedInt in {
4405 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4406 def rri : Ii8<0xC4, MRMSrcReg,
4407 (outs VR128:$dst), (ins VR128:$src1,
4408 GR32:$src2, i32i8imm:$src3),
4410 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4411 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4413 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4414 def rmi : Ii8<0xC4, MRMSrcMem,
4415 (outs VR128:$dst), (ins VR128:$src1,
4416 i16mem:$src2, i32i8imm:$src3),
4418 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4419 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4421 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4422 imm:$src3))], IIC_SSE_PINSRW>;
4426 let Predicates = [HasAVX] in
4427 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4428 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4429 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4430 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4431 imm:$src2))]>, TB, OpSize, VEX;
4432 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4433 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4434 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4435 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4436 imm:$src2))], IIC_SSE_PEXTRW>;
4439 let Predicates = [HasAVX] in {
4440 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4441 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4442 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4443 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4444 []>, TB, OpSize, VEX_4V;
4447 let Constraints = "$src1 = $dst" in
4448 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4450 } // ExeDomain = SSEPackedInt
4452 //===---------------------------------------------------------------------===//
4453 // SSE2 - Packed Mask Creation
4454 //===---------------------------------------------------------------------===//
4456 let ExeDomain = SSEPackedInt in {
4458 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4459 "pmovmskb\t{$src, $dst|$dst, $src}",
4460 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4461 IIC_SSE_MOVMSK>, VEX;
4462 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4463 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4465 let Predicates = [HasAVX2] in {
4466 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4467 "pmovmskb\t{$src, $dst|$dst, $src}",
4468 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4469 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4470 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4473 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4474 "pmovmskb\t{$src, $dst|$dst, $src}",
4475 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4478 } // ExeDomain = SSEPackedInt
4480 //===---------------------------------------------------------------------===//
4481 // SSE2 - Conditional Store
4482 //===---------------------------------------------------------------------===//
4484 let ExeDomain = SSEPackedInt in {
4487 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4488 (ins VR128:$src, VR128:$mask),
4489 "maskmovdqu\t{$mask, $src|$src, $mask}",
4490 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4491 IIC_SSE_MASKMOV>, VEX;
4493 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4494 (ins VR128:$src, VR128:$mask),
4495 "maskmovdqu\t{$mask, $src|$src, $mask}",
4496 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4497 IIC_SSE_MASKMOV>, VEX;
4500 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4501 "maskmovdqu\t{$mask, $src|$src, $mask}",
4502 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4505 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4506 "maskmovdqu\t{$mask, $src|$src, $mask}",
4507 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4510 } // ExeDomain = SSEPackedInt
4512 //===---------------------------------------------------------------------===//
4513 // SSE2 - Move Doubleword
4514 //===---------------------------------------------------------------------===//
4516 //===---------------------------------------------------------------------===//
4517 // Move Int Doubleword to Packed Double Int
4519 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4520 "movd\t{$src, $dst|$dst, $src}",
4522 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4524 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4525 "movd\t{$src, $dst|$dst, $src}",
4527 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4530 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4531 "mov{d|q}\t{$src, $dst|$dst, $src}",
4533 (v2i64 (scalar_to_vector GR64:$src)))],
4534 IIC_SSE_MOVDQ>, VEX;
4535 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4536 "mov{d|q}\t{$src, $dst|$dst, $src}",
4537 [(set FR64:$dst, (bitconvert GR64:$src))],
4538 IIC_SSE_MOVDQ>, VEX;
4540 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4541 "movd\t{$src, $dst|$dst, $src}",
4543 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4544 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4545 "movd\t{$src, $dst|$dst, $src}",
4547 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4549 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4550 "mov{d|q}\t{$src, $dst|$dst, $src}",
4552 (v2i64 (scalar_to_vector GR64:$src)))],
4554 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4555 "mov{d|q}\t{$src, $dst|$dst, $src}",
4556 [(set FR64:$dst, (bitconvert GR64:$src))],
4559 //===---------------------------------------------------------------------===//
4560 // Move Int Doubleword to Single Scalar
4562 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4563 "movd\t{$src, $dst|$dst, $src}",
4564 [(set FR32:$dst, (bitconvert GR32:$src))],
4565 IIC_SSE_MOVDQ>, VEX;
4567 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4568 "movd\t{$src, $dst|$dst, $src}",
4569 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4572 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4573 "movd\t{$src, $dst|$dst, $src}",
4574 [(set FR32:$dst, (bitconvert GR32:$src))],
4577 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4578 "movd\t{$src, $dst|$dst, $src}",
4579 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4582 //===---------------------------------------------------------------------===//
4583 // Move Packed Doubleword Int to Packed Double Int
4585 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4586 "movd\t{$src, $dst|$dst, $src}",
4587 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4588 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4589 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4590 (ins i32mem:$dst, VR128:$src),
4591 "movd\t{$src, $dst|$dst, $src}",
4592 [(store (i32 (vector_extract (v4i32 VR128:$src),
4593 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4595 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4596 "movd\t{$src, $dst|$dst, $src}",
4597 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4598 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4599 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4600 "movd\t{$src, $dst|$dst, $src}",
4601 [(store (i32 (vector_extract (v4i32 VR128:$src),
4602 (iPTR 0))), addr:$dst)],
4605 //===---------------------------------------------------------------------===//
4606 // Move Packed Doubleword Int first element to Doubleword Int
4608 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4609 "vmov{d|q}\t{$src, $dst|$dst, $src}",
4610 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4613 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4615 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4616 "mov{d|q}\t{$src, $dst|$dst, $src}",
4617 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4621 //===---------------------------------------------------------------------===//
4622 // Bitcast FR64 <-> GR64
4624 let Predicates = [HasAVX] in
4625 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4626 "vmovq\t{$src, $dst|$dst, $src}",
4627 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4629 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4630 "mov{d|q}\t{$src, $dst|$dst, $src}",
4631 [(set GR64:$dst, (bitconvert FR64:$src))],
4632 IIC_SSE_MOVDQ>, VEX;
4633 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4634 "movq\t{$src, $dst|$dst, $src}",
4635 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4636 IIC_SSE_MOVDQ>, VEX;
4638 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4639 "movq\t{$src, $dst|$dst, $src}",
4640 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4642 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4643 "mov{d|q}\t{$src, $dst|$dst, $src}",
4644 [(set GR64:$dst, (bitconvert FR64:$src))],
4646 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4647 "movq\t{$src, $dst|$dst, $src}",
4648 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4651 //===---------------------------------------------------------------------===//
4652 // Move Scalar Single to Double Int
4654 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4655 "movd\t{$src, $dst|$dst, $src}",
4656 [(set GR32:$dst, (bitconvert FR32:$src))],
4657 IIC_SSE_MOVD_ToGP>, VEX;
4658 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4659 "movd\t{$src, $dst|$dst, $src}",
4660 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4661 IIC_SSE_MOVDQ>, VEX;
4662 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4663 "movd\t{$src, $dst|$dst, $src}",
4664 [(set GR32:$dst, (bitconvert FR32:$src))],
4666 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4667 "movd\t{$src, $dst|$dst, $src}",
4668 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4671 //===---------------------------------------------------------------------===//
4672 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4674 let AddedComplexity = 15 in {
4675 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4676 "movd\t{$src, $dst|$dst, $src}",
4677 [(set VR128:$dst, (v4i32 (X86vzmovl
4678 (v4i32 (scalar_to_vector GR32:$src)))))],
4679 IIC_SSE_MOVDQ>, VEX;
4680 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4681 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4682 [(set VR128:$dst, (v2i64 (X86vzmovl
4683 (v2i64 (scalar_to_vector GR64:$src)))))],
4687 let AddedComplexity = 15 in {
4688 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4689 "movd\t{$src, $dst|$dst, $src}",
4690 [(set VR128:$dst, (v4i32 (X86vzmovl
4691 (v4i32 (scalar_to_vector GR32:$src)))))],
4693 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4694 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4695 [(set VR128:$dst, (v2i64 (X86vzmovl
4696 (v2i64 (scalar_to_vector GR64:$src)))))],
4700 let AddedComplexity = 20 in {
4701 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4702 "movd\t{$src, $dst|$dst, $src}",
4704 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4705 (loadi32 addr:$src))))))],
4706 IIC_SSE_MOVDQ>, VEX;
4707 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4708 "movd\t{$src, $dst|$dst, $src}",
4710 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4711 (loadi32 addr:$src))))))],
4715 let Predicates = [HasAVX] in {
4716 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4717 let AddedComplexity = 20 in {
4718 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4719 (VMOVZDI2PDIrm addr:$src)>;
4720 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4721 (VMOVZDI2PDIrm addr:$src)>;
4723 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4724 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4725 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4726 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4727 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4728 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4729 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4732 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4733 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4734 (MOVZDI2PDIrm addr:$src)>;
4735 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4736 (MOVZDI2PDIrm addr:$src)>;
4739 // These are the correct encodings of the instructions so that we know how to
4740 // read correct assembly, even though we continue to emit the wrong ones for
4741 // compatibility with Darwin's buggy assembler.
4742 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4743 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4744 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4745 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4746 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4747 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4748 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4749 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4750 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4751 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4752 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4753 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4755 //===---------------------------------------------------------------------===//
4756 // SSE2 - Move Quadword
4757 //===---------------------------------------------------------------------===//
4759 //===---------------------------------------------------------------------===//
4760 // Move Quadword Int to Packed Quadword Int
4762 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4763 "vmovq\t{$src, $dst|$dst, $src}",
4765 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4766 VEX, Requires<[HasAVX]>;
4767 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4768 "movq\t{$src, $dst|$dst, $src}",
4770 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4772 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4774 //===---------------------------------------------------------------------===//
4775 // Move Packed Quadword Int to Quadword Int
4777 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4778 "movq\t{$src, $dst|$dst, $src}",
4779 [(store (i64 (vector_extract (v2i64 VR128:$src),
4780 (iPTR 0))), addr:$dst)],
4781 IIC_SSE_MOVDQ>, VEX;
4782 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4783 "movq\t{$src, $dst|$dst, $src}",
4784 [(store (i64 (vector_extract (v2i64 VR128:$src),
4785 (iPTR 0))), addr:$dst)],
4788 //===---------------------------------------------------------------------===//
4789 // Store / copy lower 64-bits of a XMM register.
4791 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4792 "movq\t{$src, $dst|$dst, $src}",
4793 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4794 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4795 "movq\t{$src, $dst|$dst, $src}",
4796 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4799 let AddedComplexity = 20 in
4800 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4801 "vmovq\t{$src, $dst|$dst, $src}",
4803 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4804 (loadi64 addr:$src))))))],
4806 XS, VEX, Requires<[HasAVX]>;
4808 let AddedComplexity = 20 in
4809 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4810 "movq\t{$src, $dst|$dst, $src}",
4812 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4813 (loadi64 addr:$src))))))],
4815 XS, Requires<[UseSSE2]>;
4817 let Predicates = [HasAVX], AddedComplexity = 20 in {
4818 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4819 (VMOVZQI2PQIrm addr:$src)>;
4820 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4821 (VMOVZQI2PQIrm addr:$src)>;
4822 def : Pat<(v2i64 (X86vzload addr:$src)),
4823 (VMOVZQI2PQIrm addr:$src)>;
4826 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4827 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4828 (MOVZQI2PQIrm addr:$src)>;
4829 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4830 (MOVZQI2PQIrm addr:$src)>;
4831 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4834 let Predicates = [HasAVX] in {
4835 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4836 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4837 def : Pat<(v4i64 (X86vzload addr:$src)),
4838 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4841 //===---------------------------------------------------------------------===//
4842 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4843 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4845 let AddedComplexity = 15 in
4846 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4847 "vmovq\t{$src, $dst|$dst, $src}",
4848 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4850 XS, VEX, Requires<[HasAVX]>;
4851 let AddedComplexity = 15 in
4852 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4853 "movq\t{$src, $dst|$dst, $src}",
4854 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4856 XS, Requires<[UseSSE2]>;
4858 let AddedComplexity = 20 in
4859 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4860 "vmovq\t{$src, $dst|$dst, $src}",
4861 [(set VR128:$dst, (v2i64 (X86vzmovl
4862 (loadv2i64 addr:$src))))],
4864 XS, VEX, Requires<[HasAVX]>;
4865 let AddedComplexity = 20 in {
4866 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4867 "movq\t{$src, $dst|$dst, $src}",
4868 [(set VR128:$dst, (v2i64 (X86vzmovl
4869 (loadv2i64 addr:$src))))],
4871 XS, Requires<[UseSSE2]>;
4874 let AddedComplexity = 20 in {
4875 let Predicates = [HasAVX] in {
4876 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4877 (VMOVZPQILo2PQIrm addr:$src)>;
4878 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4879 (VMOVZPQILo2PQIrr VR128:$src)>;
4881 let Predicates = [UseSSE2] in {
4882 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4883 (MOVZPQILo2PQIrm addr:$src)>;
4884 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4885 (MOVZPQILo2PQIrr VR128:$src)>;
4889 // Instructions to match in the assembler
4890 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4891 "movq\t{$src, $dst|$dst, $src}", [],
4892 IIC_SSE_MOVDQ>, VEX, VEX_W;
4893 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4894 "movq\t{$src, $dst|$dst, $src}", [],
4895 IIC_SSE_MOVDQ>, VEX, VEX_W;
4896 // Recognize "movd" with GR64 destination, but encode as a "movq"
4897 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4898 "movd\t{$src, $dst|$dst, $src}", [],
4899 IIC_SSE_MOVDQ>, VEX, VEX_W;
4901 // Instructions for the disassembler
4902 // xr = XMM register
4905 let Predicates = [HasAVX] in
4906 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4907 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4908 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4909 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4911 //===---------------------------------------------------------------------===//
4912 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4913 //===---------------------------------------------------------------------===//
4914 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4915 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4916 X86MemOperand x86memop> {
4917 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4918 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4919 [(set RC:$dst, (vt (OpNode RC:$src)))],
4921 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4922 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4923 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4927 let Predicates = [HasAVX] in {
4928 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4929 v4f32, VR128, memopv4f32, f128mem>, VEX;
4930 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4931 v4f32, VR128, memopv4f32, f128mem>, VEX;
4932 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4933 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4934 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4935 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4937 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4938 memopv4f32, f128mem>;
4939 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4940 memopv4f32, f128mem>;
4942 let Predicates = [HasAVX] in {
4943 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4944 (VMOVSHDUPrr VR128:$src)>;
4945 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4946 (VMOVSHDUPrm addr:$src)>;
4947 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4948 (VMOVSLDUPrr VR128:$src)>;
4949 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4950 (VMOVSLDUPrm addr:$src)>;
4951 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4952 (VMOVSHDUPYrr VR256:$src)>;
4953 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4954 (VMOVSHDUPYrm addr:$src)>;
4955 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4956 (VMOVSLDUPYrr VR256:$src)>;
4957 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4958 (VMOVSLDUPYrm addr:$src)>;
4961 let Predicates = [UseSSE3] in {
4962 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4963 (MOVSHDUPrr VR128:$src)>;
4964 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4965 (MOVSHDUPrm addr:$src)>;
4966 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4967 (MOVSLDUPrr VR128:$src)>;
4968 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4969 (MOVSLDUPrm addr:$src)>;
4972 //===---------------------------------------------------------------------===//
4973 // SSE3 - Replicate Double FP - MOVDDUP
4974 //===---------------------------------------------------------------------===//
4976 multiclass sse3_replicate_dfp<string OpcodeStr> {
4977 let neverHasSideEffects = 1 in
4978 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4979 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4980 [], IIC_SSE_MOV_LH>;
4981 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4982 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4985 (scalar_to_vector (loadf64 addr:$src)))))],
4989 // FIXME: Merge with above classe when there're patterns for the ymm version
4990 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4991 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4992 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4993 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4994 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4995 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4998 (scalar_to_vector (loadf64 addr:$src)))))]>;
5001 let Predicates = [HasAVX] in {
5002 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5003 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5006 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5008 let Predicates = [HasAVX] in {
5009 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5010 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5011 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5012 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5013 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5014 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5015 def : Pat<(X86Movddup (bc_v2f64
5016 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5017 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5020 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
5021 (VMOVDDUPYrm addr:$src)>;
5022 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
5023 (VMOVDDUPYrm addr:$src)>;
5024 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5025 (VMOVDDUPYrm addr:$src)>;
5026 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5027 (VMOVDDUPYrr VR256:$src)>;
5030 let Predicates = [UseSSE3] in {
5031 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5032 (MOVDDUPrm addr:$src)>;
5033 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5034 (MOVDDUPrm addr:$src)>;
5035 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5036 (MOVDDUPrm addr:$src)>;
5037 def : Pat<(X86Movddup (bc_v2f64
5038 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5039 (MOVDDUPrm addr:$src)>;
5042 //===---------------------------------------------------------------------===//
5043 // SSE3 - Move Unaligned Integer
5044 //===---------------------------------------------------------------------===//
5046 let Predicates = [HasAVX] in {
5047 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5048 "vlddqu\t{$src, $dst|$dst, $src}",
5049 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5050 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5051 "vlddqu\t{$src, $dst|$dst, $src}",
5052 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5055 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5056 "lddqu\t{$src, $dst|$dst, $src}",
5057 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5060 //===---------------------------------------------------------------------===//
5061 // SSE3 - Arithmetic
5062 //===---------------------------------------------------------------------===//
5064 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5065 X86MemOperand x86memop, OpndItins itins,
5067 def rr : I<0xD0, MRMSrcReg,
5068 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5070 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5071 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5072 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5073 def rm : I<0xD0, MRMSrcMem,
5074 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5076 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5077 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5078 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5081 let Predicates = [HasAVX] in {
5082 let ExeDomain = SSEPackedSingle in {
5083 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5084 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5085 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5086 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
5088 let ExeDomain = SSEPackedDouble in {
5089 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5090 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5091 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5092 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
5095 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5096 let ExeDomain = SSEPackedSingle in
5097 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5098 f128mem, SSE_ALU_F32P>, TB, XD;
5099 let ExeDomain = SSEPackedDouble in
5100 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5101 f128mem, SSE_ALU_F64P>, TB, OpSize;
5104 //===---------------------------------------------------------------------===//
5105 // SSE3 Instructions
5106 //===---------------------------------------------------------------------===//
5109 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5110 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5111 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5114 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5115 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5117 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5119 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5120 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5121 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5122 IIC_SSE_HADDSUB_RM>;
5124 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5125 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5126 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5128 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5129 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5130 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5132 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5134 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5135 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5136 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5137 IIC_SSE_HADDSUB_RM>;
5140 let Predicates = [HasAVX] in {
5141 let ExeDomain = SSEPackedSingle in {
5142 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5143 X86fhadd, 0>, VEX_4V;
5144 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5145 X86fhsub, 0>, VEX_4V;
5146 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5147 X86fhadd, 0>, VEX_4V, VEX_L;
5148 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5149 X86fhsub, 0>, VEX_4V, VEX_L;
5151 let ExeDomain = SSEPackedDouble in {
5152 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5153 X86fhadd, 0>, VEX_4V;
5154 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5155 X86fhsub, 0>, VEX_4V;
5156 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5157 X86fhadd, 0>, VEX_4V, VEX_L;
5158 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5159 X86fhsub, 0>, VEX_4V, VEX_L;
5163 let Constraints = "$src1 = $dst" in {
5164 let ExeDomain = SSEPackedSingle in {
5165 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5166 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5168 let ExeDomain = SSEPackedDouble in {
5169 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5170 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5174 //===---------------------------------------------------------------------===//
5175 // SSSE3 - Packed Absolute Instructions
5176 //===---------------------------------------------------------------------===//
5179 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5180 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5181 Intrinsic IntId128> {
5182 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5184 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5185 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5188 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5190 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5193 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5197 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5198 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5199 Intrinsic IntId256> {
5200 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5202 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5203 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5206 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5208 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5211 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5214 let Predicates = [HasAVX] in {
5215 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5216 int_x86_ssse3_pabs_b_128>, VEX;
5217 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5218 int_x86_ssse3_pabs_w_128>, VEX;
5219 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5220 int_x86_ssse3_pabs_d_128>, VEX;
5223 let Predicates = [HasAVX2] in {
5224 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5225 int_x86_avx2_pabs_b>, VEX, VEX_L;
5226 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5227 int_x86_avx2_pabs_w>, VEX, VEX_L;
5228 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5229 int_x86_avx2_pabs_d>, VEX, VEX_L;
5232 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5233 int_x86_ssse3_pabs_b_128>;
5234 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5235 int_x86_ssse3_pabs_w_128>;
5236 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5237 int_x86_ssse3_pabs_d_128>;
5239 //===---------------------------------------------------------------------===//
5240 // SSSE3 - Packed Binary Operator Instructions
5241 //===---------------------------------------------------------------------===//
5243 def SSE_PHADDSUBD : OpndItins<
5244 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5246 def SSE_PHADDSUBSW : OpndItins<
5247 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5249 def SSE_PHADDSUBW : OpndItins<
5250 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5252 def SSE_PSHUFB : OpndItins<
5253 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5255 def SSE_PSIGN : OpndItins<
5256 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5258 def SSE_PMULHRSW : OpndItins<
5259 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5262 /// SS3I_binop_rm - Simple SSSE3 bin op
5263 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5264 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5265 X86MemOperand x86memop, OpndItins itins,
5267 let isCommutable = 1 in
5268 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5269 (ins RC:$src1, RC:$src2),
5271 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5272 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5273 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5275 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5276 (ins RC:$src1, x86memop:$src2),
5278 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5279 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5281 (OpVT (OpNode RC:$src1,
5282 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5285 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5286 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5287 Intrinsic IntId128, OpndItins itins,
5289 let isCommutable = 1 in
5290 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5291 (ins VR128:$src1, VR128:$src2),
5293 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5294 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5295 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5297 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5298 (ins VR128:$src1, i128mem:$src2),
5300 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5301 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5303 (IntId128 VR128:$src1,
5304 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5307 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5308 Intrinsic IntId256> {
5309 let isCommutable = 1 in
5310 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5311 (ins VR256:$src1, VR256:$src2),
5312 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5313 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5315 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5316 (ins VR256:$src1, i256mem:$src2),
5317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5319 (IntId256 VR256:$src1,
5320 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5323 let ImmT = NoImm, Predicates = [HasAVX] in {
5324 let isCommutable = 0 in {
5325 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5326 memopv2i64, i128mem,
5327 SSE_PHADDSUBW, 0>, VEX_4V;
5328 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5329 memopv2i64, i128mem,
5330 SSE_PHADDSUBD, 0>, VEX_4V;
5331 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5332 memopv2i64, i128mem,
5333 SSE_PHADDSUBW, 0>, VEX_4V;
5334 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5335 memopv2i64, i128mem,
5336 SSE_PHADDSUBD, 0>, VEX_4V;
5337 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5338 memopv2i64, i128mem,
5339 SSE_PSIGN, 0>, VEX_4V;
5340 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5341 memopv2i64, i128mem,
5342 SSE_PSIGN, 0>, VEX_4V;
5343 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5344 memopv2i64, i128mem,
5345 SSE_PSIGN, 0>, VEX_4V;
5346 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5347 memopv2i64, i128mem,
5348 SSE_PSHUFB, 0>, VEX_4V;
5349 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5350 int_x86_ssse3_phadd_sw_128,
5351 SSE_PHADDSUBSW, 0>, VEX_4V;
5352 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5353 int_x86_ssse3_phsub_sw_128,
5354 SSE_PHADDSUBSW, 0>, VEX_4V;
5355 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5356 int_x86_ssse3_pmadd_ub_sw_128,
5357 SSE_PMADD, 0>, VEX_4V;
5359 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5360 int_x86_ssse3_pmul_hr_sw_128,
5361 SSE_PMULHRSW, 0>, VEX_4V;
5364 let ImmT = NoImm, Predicates = [HasAVX2] in {
5365 let isCommutable = 0 in {
5366 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5367 memopv4i64, i256mem,
5368 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5369 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5370 memopv4i64, i256mem,
5371 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5372 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5373 memopv4i64, i256mem,
5374 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5375 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5376 memopv4i64, i256mem,
5377 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5378 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5379 memopv4i64, i256mem,
5380 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5381 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5382 memopv4i64, i256mem,
5383 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5384 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5385 memopv4i64, i256mem,
5386 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5387 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5388 memopv4i64, i256mem,
5389 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5390 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5391 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5392 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5393 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5394 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5395 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5397 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5398 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5401 // None of these have i8 immediate fields.
5402 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5403 let isCommutable = 0 in {
5404 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5405 memopv2i64, i128mem, SSE_PHADDSUBW>;
5406 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5407 memopv2i64, i128mem, SSE_PHADDSUBD>;
5408 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5409 memopv2i64, i128mem, SSE_PHADDSUBW>;
5410 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5411 memopv2i64, i128mem, SSE_PHADDSUBD>;
5412 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5413 memopv2i64, i128mem, SSE_PSIGN>;
5414 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5415 memopv2i64, i128mem, SSE_PSIGN>;
5416 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5417 memopv2i64, i128mem, SSE_PSIGN>;
5418 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5419 memopv2i64, i128mem, SSE_PSHUFB>;
5420 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5421 int_x86_ssse3_phadd_sw_128,
5423 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5424 int_x86_ssse3_phsub_sw_128,
5426 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5427 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5429 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5430 int_x86_ssse3_pmul_hr_sw_128,
5434 //===---------------------------------------------------------------------===//
5435 // SSSE3 - Packed Align Instruction Patterns
5436 //===---------------------------------------------------------------------===//
5438 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5439 let neverHasSideEffects = 1 in {
5440 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5441 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5443 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5445 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5446 [], IIC_SSE_PALIGNR>, OpSize;
5448 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5449 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5451 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5453 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5454 [], IIC_SSE_PALIGNR>, OpSize;
5458 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5459 let neverHasSideEffects = 1 in {
5460 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5461 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5463 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5466 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5467 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5469 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5474 let Predicates = [HasAVX] in
5475 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5476 let Predicates = [HasAVX2] in
5477 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V, VEX_L;
5478 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5479 defm PALIGN : ssse3_palign<"palignr">;
5481 let Predicates = [HasAVX2] in {
5482 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5483 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5484 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5485 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5486 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5487 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5488 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5489 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5492 let Predicates = [HasAVX] in {
5493 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5494 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5495 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5496 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5497 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5498 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5499 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5500 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5503 let Predicates = [UseSSSE3] in {
5504 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5505 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5506 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5507 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5508 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5509 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5510 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5511 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5514 //===---------------------------------------------------------------------===//
5515 // SSSE3 - Thread synchronization
5516 //===---------------------------------------------------------------------===//
5518 let usesCustomInserter = 1 in {
5519 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5520 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5521 Requires<[HasSSE3]>;
5524 let Uses = [EAX, ECX, EDX] in
5525 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5526 TB, Requires<[HasSSE3]>;
5527 let Uses = [ECX, EAX] in
5528 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5529 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5530 TB, Requires<[HasSSE3]>;
5532 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5533 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5535 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5536 Requires<[In32BitMode]>;
5537 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5538 Requires<[In64BitMode]>;
5540 //===----------------------------------------------------------------------===//
5541 // SSE4.1 - Packed Move with Sign/Zero Extend
5542 //===----------------------------------------------------------------------===//
5544 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5545 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5546 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5547 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5549 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5550 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5552 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5556 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5558 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5559 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5560 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5562 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5563 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5564 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5567 let Predicates = [HasAVX] in {
5568 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5570 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5572 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5574 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5576 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5578 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5582 let Predicates = [HasAVX2] in {
5583 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5584 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5585 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5586 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5587 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5588 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5589 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5590 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5591 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5592 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5593 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5594 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5597 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5598 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5599 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5600 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5601 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5602 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5604 let Predicates = [HasAVX] in {
5605 // Common patterns involving scalar load.
5606 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5607 (VPMOVSXBWrm addr:$src)>;
5608 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5609 (VPMOVSXBWrm addr:$src)>;
5610 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5611 (VPMOVSXBWrm addr:$src)>;
5613 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5614 (VPMOVSXWDrm addr:$src)>;
5615 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5616 (VPMOVSXWDrm addr:$src)>;
5617 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5618 (VPMOVSXWDrm addr:$src)>;
5620 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5621 (VPMOVSXDQrm addr:$src)>;
5622 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5623 (VPMOVSXDQrm addr:$src)>;
5624 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5625 (VPMOVSXDQrm addr:$src)>;
5627 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5628 (VPMOVZXBWrm addr:$src)>;
5629 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5630 (VPMOVZXBWrm addr:$src)>;
5631 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5632 (VPMOVZXBWrm addr:$src)>;
5634 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5635 (VPMOVZXWDrm addr:$src)>;
5636 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5637 (VPMOVZXWDrm addr:$src)>;
5638 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5639 (VPMOVZXWDrm addr:$src)>;
5641 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5642 (VPMOVZXDQrm addr:$src)>;
5643 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5644 (VPMOVZXDQrm addr:$src)>;
5645 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5646 (VPMOVZXDQrm addr:$src)>;
5649 let Predicates = [UseSSE41] in {
5650 // Common patterns involving scalar load.
5651 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5652 (PMOVSXBWrm addr:$src)>;
5653 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5654 (PMOVSXBWrm addr:$src)>;
5655 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5656 (PMOVSXBWrm addr:$src)>;
5658 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5659 (PMOVSXWDrm addr:$src)>;
5660 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5661 (PMOVSXWDrm addr:$src)>;
5662 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5663 (PMOVSXWDrm addr:$src)>;
5665 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5666 (PMOVSXDQrm addr:$src)>;
5667 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5668 (PMOVSXDQrm addr:$src)>;
5669 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5670 (PMOVSXDQrm addr:$src)>;
5672 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5673 (PMOVZXBWrm addr:$src)>;
5674 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5675 (PMOVZXBWrm addr:$src)>;
5676 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5677 (PMOVZXBWrm addr:$src)>;
5679 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5680 (PMOVZXWDrm addr:$src)>;
5681 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5682 (PMOVZXWDrm addr:$src)>;
5683 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5684 (PMOVZXWDrm addr:$src)>;
5686 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5687 (PMOVZXDQrm addr:$src)>;
5688 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5689 (PMOVZXDQrm addr:$src)>;
5690 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5691 (PMOVZXDQrm addr:$src)>;
5694 let Predicates = [HasAVX2] in {
5695 let AddedComplexity = 15 in {
5696 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5697 (VPMOVZXDQYrr VR128:$src)>;
5698 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5699 (VPMOVZXWDYrr VR128:$src)>;
5702 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5703 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5706 let Predicates = [HasAVX] in {
5707 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5708 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5711 let Predicates = [UseSSE41] in {
5712 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5713 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5717 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5718 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5719 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5720 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5722 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5723 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5725 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5729 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5731 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5732 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5733 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5735 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5736 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5738 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5742 let Predicates = [HasAVX] in {
5743 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5745 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5747 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5749 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5753 let Predicates = [HasAVX2] in {
5754 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5755 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5756 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5757 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5758 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5759 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5760 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5761 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5764 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5765 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5766 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5767 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5769 let Predicates = [HasAVX] in {
5770 // Common patterns involving scalar load
5771 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5772 (VPMOVSXBDrm addr:$src)>;
5773 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5774 (VPMOVSXWQrm addr:$src)>;
5776 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5777 (VPMOVZXBDrm addr:$src)>;
5778 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5779 (VPMOVZXWQrm addr:$src)>;
5782 let Predicates = [UseSSE41] in {
5783 // Common patterns involving scalar load
5784 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5785 (PMOVSXBDrm addr:$src)>;
5786 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5787 (PMOVSXWQrm addr:$src)>;
5789 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5790 (PMOVZXBDrm addr:$src)>;
5791 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5792 (PMOVZXWQrm addr:$src)>;
5795 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5796 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5797 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5798 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5800 // Expecting a i16 load any extended to i32 value.
5801 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5802 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5803 [(set VR128:$dst, (IntId (bitconvert
5804 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5808 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5810 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5811 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5812 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5814 // Expecting a i16 load any extended to i32 value.
5815 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5816 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5817 [(set VR256:$dst, (IntId (bitconvert
5818 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5822 let Predicates = [HasAVX] in {
5823 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5825 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5828 let Predicates = [HasAVX2] in {
5829 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5830 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5831 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5832 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5834 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5835 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5837 let Predicates = [HasAVX2] in {
5838 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5839 (VPMOVSXWDYrm addr:$src)>;
5840 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5841 (VPMOVSXDQYrm addr:$src)>;
5843 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5844 (scalar_to_vector (loadi64 addr:$src))))))),
5845 (VPMOVSXBDYrm addr:$src)>;
5846 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5847 (scalar_to_vector (loadf64 addr:$src))))))),
5848 (VPMOVSXBDYrm addr:$src)>;
5850 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5851 (scalar_to_vector (loadi64 addr:$src))))))),
5852 (VPMOVSXWQYrm addr:$src)>;
5853 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5854 (scalar_to_vector (loadf64 addr:$src))))))),
5855 (VPMOVSXWQYrm addr:$src)>;
5857 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5858 (scalar_to_vector (loadi32 addr:$src))))))),
5859 (VPMOVSXBQYrm addr:$src)>;
5862 let Predicates = [HasAVX] in {
5863 // Common patterns involving scalar load
5864 def : Pat<(int_x86_sse41_pmovsxbq
5865 (bitconvert (v4i32 (X86vzmovl
5866 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5867 (VPMOVSXBQrm addr:$src)>;
5869 def : Pat<(int_x86_sse41_pmovzxbq
5870 (bitconvert (v4i32 (X86vzmovl
5871 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5872 (VPMOVZXBQrm addr:$src)>;
5875 let Predicates = [UseSSE41] in {
5876 // Common patterns involving scalar load
5877 def : Pat<(int_x86_sse41_pmovsxbq
5878 (bitconvert (v4i32 (X86vzmovl
5879 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5880 (PMOVSXBQrm addr:$src)>;
5882 def : Pat<(int_x86_sse41_pmovzxbq
5883 (bitconvert (v4i32 (X86vzmovl
5884 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5885 (PMOVZXBQrm addr:$src)>;
5887 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5888 (scalar_to_vector (loadi64 addr:$src))))))),
5889 (PMOVSXWDrm addr:$src)>;
5890 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5891 (scalar_to_vector (loadf64 addr:$src))))))),
5892 (PMOVSXWDrm addr:$src)>;
5893 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5894 (scalar_to_vector (loadi32 addr:$src))))))),
5895 (PMOVSXBDrm addr:$src)>;
5896 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5897 (scalar_to_vector (loadi32 addr:$src))))))),
5898 (PMOVSXWQrm addr:$src)>;
5899 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5900 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5901 (PMOVSXBQrm addr:$src)>;
5902 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5903 (scalar_to_vector (loadi64 addr:$src))))))),
5904 (PMOVSXDQrm addr:$src)>;
5905 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5906 (scalar_to_vector (loadf64 addr:$src))))))),
5907 (PMOVSXDQrm addr:$src)>;
5908 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5909 (scalar_to_vector (loadi64 addr:$src))))))),
5910 (PMOVSXBWrm addr:$src)>;
5911 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5912 (scalar_to_vector (loadf64 addr:$src))))))),
5913 (PMOVSXBWrm addr:$src)>;
5916 let Predicates = [HasAVX2] in {
5917 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5918 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5919 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5921 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5922 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5924 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5926 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5927 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5928 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5929 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5930 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5931 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5933 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5934 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5935 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5936 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5938 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5939 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5942 let Predicates = [HasAVX] in {
5943 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5944 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5945 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5947 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5948 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5950 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5952 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5953 (VPMOVZXBWrm addr:$src)>;
5954 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5955 (VPMOVZXBWrm addr:$src)>;
5956 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5957 (VPMOVZXBDrm addr:$src)>;
5958 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5959 (VPMOVZXBQrm addr:$src)>;
5961 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5962 (VPMOVZXWDrm addr:$src)>;
5963 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5964 (VPMOVZXWDrm addr:$src)>;
5965 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5966 (VPMOVZXWQrm addr:$src)>;
5968 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5969 (VPMOVZXDQrm addr:$src)>;
5970 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5971 (VPMOVZXDQrm addr:$src)>;
5972 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5973 (VPMOVZXDQrm addr:$src)>;
5975 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5976 (scalar_to_vector (loadi64 addr:$src))))))),
5977 (VPMOVSXWDrm addr:$src)>;
5978 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5979 (scalar_to_vector (loadi64 addr:$src))))))),
5980 (VPMOVSXDQrm addr:$src)>;
5981 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5982 (scalar_to_vector (loadf64 addr:$src))))))),
5983 (VPMOVSXWDrm addr:$src)>;
5984 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5985 (scalar_to_vector (loadf64 addr:$src))))))),
5986 (VPMOVSXDQrm addr:$src)>;
5987 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5988 (scalar_to_vector (loadi64 addr:$src))))))),
5989 (VPMOVSXBWrm addr:$src)>;
5990 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5991 (scalar_to_vector (loadf64 addr:$src))))))),
5992 (VPMOVSXBWrm addr:$src)>;
5994 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5995 (scalar_to_vector (loadi32 addr:$src))))))),
5996 (VPMOVSXBDrm addr:$src)>;
5997 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5998 (scalar_to_vector (loadi32 addr:$src))))))),
5999 (VPMOVSXWQrm addr:$src)>;
6000 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6001 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6002 (VPMOVSXBQrm addr:$src)>;
6005 let Predicates = [UseSSE41] in {
6006 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6007 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6008 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6010 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6011 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6013 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6015 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6016 (PMOVZXBWrm addr:$src)>;
6017 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6018 (PMOVZXBWrm addr:$src)>;
6019 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6020 (PMOVZXBDrm addr:$src)>;
6021 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6022 (PMOVZXBQrm addr:$src)>;
6024 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6025 (PMOVZXWDrm addr:$src)>;
6026 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6027 (PMOVZXWDrm addr:$src)>;
6028 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6029 (PMOVZXWQrm addr:$src)>;
6031 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6032 (PMOVZXDQrm addr:$src)>;
6033 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6034 (PMOVZXDQrm addr:$src)>;
6035 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6036 (PMOVZXDQrm addr:$src)>;
6039 //===----------------------------------------------------------------------===//
6040 // SSE4.1 - Extract Instructions
6041 //===----------------------------------------------------------------------===//
6043 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6044 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6045 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6046 (ins VR128:$src1, i32i8imm:$src2),
6047 !strconcat(OpcodeStr,
6048 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6049 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
6051 let neverHasSideEffects = 1, mayStore = 1 in
6052 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6053 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6054 !strconcat(OpcodeStr,
6055 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6058 // There's an AssertZext in the way of writing the store pattern
6059 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6062 let Predicates = [HasAVX] in {
6063 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6064 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
6065 (ins VR128:$src1, i32i8imm:$src2),
6066 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
6069 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6072 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6073 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6074 let neverHasSideEffects = 1, mayStore = 1 in
6075 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6076 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6077 !strconcat(OpcodeStr,
6078 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6081 // There's an AssertZext in the way of writing the store pattern
6082 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6085 let Predicates = [HasAVX] in
6086 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6088 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6091 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6092 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6093 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6094 (ins VR128:$src1, i32i8imm:$src2),
6095 !strconcat(OpcodeStr,
6096 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6098 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6099 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6100 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6101 !strconcat(OpcodeStr,
6102 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6103 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6104 addr:$dst)]>, OpSize;
6107 let Predicates = [HasAVX] in
6108 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6110 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6112 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6113 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6114 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6115 (ins VR128:$src1, i32i8imm:$src2),
6116 !strconcat(OpcodeStr,
6117 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6119 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6120 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6121 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6122 !strconcat(OpcodeStr,
6123 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6124 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6125 addr:$dst)]>, OpSize, REX_W;
6128 let Predicates = [HasAVX] in
6129 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6131 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6133 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6135 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
6136 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6137 (ins VR128:$src1, i32i8imm:$src2),
6138 !strconcat(OpcodeStr,
6139 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6141 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
6143 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6144 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6145 !strconcat(OpcodeStr,
6146 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6147 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6148 addr:$dst)]>, OpSize;
6151 let ExeDomain = SSEPackedSingle in {
6152 let Predicates = [HasAVX] in {
6153 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6154 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6155 (ins VR128:$src1, i32i8imm:$src2),
6156 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
6159 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
6162 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6163 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6166 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6168 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6171 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6172 Requires<[UseSSE41]>;
6174 //===----------------------------------------------------------------------===//
6175 // SSE4.1 - Insert Instructions
6176 //===----------------------------------------------------------------------===//
6178 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6179 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6180 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6182 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6184 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6186 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6187 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6188 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6190 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6192 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6194 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6195 imm:$src3))]>, OpSize;
6198 let Predicates = [HasAVX] in
6199 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6200 let Constraints = "$src1 = $dst" in
6201 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6203 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6204 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6205 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6207 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6209 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6211 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6213 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6214 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6216 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6218 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6220 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6221 imm:$src3)))]>, OpSize;
6224 let Predicates = [HasAVX] in
6225 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6226 let Constraints = "$src1 = $dst" in
6227 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6229 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6230 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6231 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6233 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6235 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6237 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6239 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6240 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6242 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6244 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6246 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6247 imm:$src3)))]>, OpSize;
6250 let Predicates = [HasAVX] in
6251 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6252 let Constraints = "$src1 = $dst" in
6253 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6255 // insertps has a few different modes, there's the first two here below which
6256 // are optimized inserts that won't zero arbitrary elements in the destination
6257 // vector. The next one matches the intrinsic and could zero arbitrary elements
6258 // in the target vector.
6259 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6260 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6261 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6263 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6265 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6267 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6269 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6270 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6272 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6274 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6276 (X86insrtps VR128:$src1,
6277 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6278 imm:$src3))]>, OpSize;
6281 let ExeDomain = SSEPackedSingle in {
6282 let Predicates = [HasAVX] in
6283 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6284 let Constraints = "$src1 = $dst" in
6285 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6288 //===----------------------------------------------------------------------===//
6289 // SSE4.1 - Round Instructions
6290 //===----------------------------------------------------------------------===//
6292 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6293 X86MemOperand x86memop, RegisterClass RC,
6294 PatFrag mem_frag32, PatFrag mem_frag64,
6295 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6296 let ExeDomain = SSEPackedSingle in {
6297 // Intrinsic operation, reg.
6298 // Vector intrinsic operation, reg
6299 def PSr : SS4AIi8<opcps, MRMSrcReg,
6300 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6301 !strconcat(OpcodeStr,
6302 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6303 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6306 // Vector intrinsic operation, mem
6307 def PSm : SS4AIi8<opcps, MRMSrcMem,
6308 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6309 !strconcat(OpcodeStr,
6310 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6312 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6314 } // ExeDomain = SSEPackedSingle
6316 let ExeDomain = SSEPackedDouble in {
6317 // Vector intrinsic operation, reg
6318 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6319 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6320 !strconcat(OpcodeStr,
6321 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6322 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6325 // Vector intrinsic operation, mem
6326 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6327 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6328 !strconcat(OpcodeStr,
6329 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6331 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6333 } // ExeDomain = SSEPackedDouble
6336 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6339 Intrinsic F64Int, bit Is2Addr = 1> {
6340 let ExeDomain = GenericDomain in {
6342 def SSr : SS4AIi8<opcss, MRMSrcReg,
6343 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6345 !strconcat(OpcodeStr,
6346 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6347 !strconcat(OpcodeStr,
6348 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6351 // Intrinsic operation, reg.
6352 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6353 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6355 !strconcat(OpcodeStr,
6356 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6357 !strconcat(OpcodeStr,
6358 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6359 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6362 // Intrinsic operation, mem.
6363 def SSm : SS4AIi8<opcss, MRMSrcMem,
6364 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6366 !strconcat(OpcodeStr,
6367 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6368 !strconcat(OpcodeStr,
6369 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6371 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6375 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6376 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6378 !strconcat(OpcodeStr,
6379 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6380 !strconcat(OpcodeStr,
6381 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6384 // Intrinsic operation, reg.
6385 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6386 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6388 !strconcat(OpcodeStr,
6389 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6390 !strconcat(OpcodeStr,
6391 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6392 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6395 // Intrinsic operation, mem.
6396 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6397 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6399 !strconcat(OpcodeStr,
6400 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6401 !strconcat(OpcodeStr,
6402 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6404 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6406 } // ExeDomain = GenericDomain
6409 // FP round - roundss, roundps, roundsd, roundpd
6410 let Predicates = [HasAVX] in {
6412 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6413 memopv4f32, memopv2f64,
6414 int_x86_sse41_round_ps,
6415 int_x86_sse41_round_pd>, VEX;
6416 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6417 memopv8f32, memopv4f64,
6418 int_x86_avx_round_ps_256,
6419 int_x86_avx_round_pd_256>, VEX, VEX_L;
6420 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6421 int_x86_sse41_round_ss,
6422 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6424 def : Pat<(ffloor FR32:$src),
6425 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6426 def : Pat<(f64 (ffloor FR64:$src)),
6427 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6428 def : Pat<(f32 (fnearbyint FR32:$src)),
6429 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6430 def : Pat<(f64 (fnearbyint FR64:$src)),
6431 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6432 def : Pat<(f32 (fceil FR32:$src)),
6433 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6434 def : Pat<(f64 (fceil FR64:$src)),
6435 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6436 def : Pat<(f32 (frint FR32:$src)),
6437 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6438 def : Pat<(f64 (frint FR64:$src)),
6439 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6440 def : Pat<(f32 (ftrunc FR32:$src)),
6441 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6442 def : Pat<(f64 (ftrunc FR64:$src)),
6443 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6445 def : Pat<(v4f32 (ffloor VR128:$src)),
6446 (VROUNDPSr VR128:$src, (i32 0x1))>;
6447 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6448 (VROUNDPSr VR128:$src, (i32 0xC))>;
6449 def : Pat<(v4f32 (fceil VR128:$src)),
6450 (VROUNDPSr VR128:$src, (i32 0x2))>;
6451 def : Pat<(v4f32 (frint VR128:$src)),
6452 (VROUNDPSr VR128:$src, (i32 0x4))>;
6453 def : Pat<(v4f32 (ftrunc VR128:$src)),
6454 (VROUNDPSr VR128:$src, (i32 0x3))>;
6456 def : Pat<(v2f64 (ffloor VR128:$src)),
6457 (VROUNDPDr VR128:$src, (i32 0x1))>;
6458 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6459 (VROUNDPDr VR128:$src, (i32 0xC))>;
6460 def : Pat<(v2f64 (fceil VR128:$src)),
6461 (VROUNDPDr VR128:$src, (i32 0x2))>;
6462 def : Pat<(v2f64 (frint VR128:$src)),
6463 (VROUNDPDr VR128:$src, (i32 0x4))>;
6464 def : Pat<(v2f64 (ftrunc VR128:$src)),
6465 (VROUNDPDr VR128:$src, (i32 0x3))>;
6467 def : Pat<(v8f32 (ffloor VR256:$src)),
6468 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6469 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6470 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6471 def : Pat<(v8f32 (fceil VR256:$src)),
6472 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6473 def : Pat<(v8f32 (frint VR256:$src)),
6474 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6475 def : Pat<(v8f32 (ftrunc VR256:$src)),
6476 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6478 def : Pat<(v4f64 (ffloor VR256:$src)),
6479 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6480 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6481 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6482 def : Pat<(v4f64 (fceil VR256:$src)),
6483 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6484 def : Pat<(v4f64 (frint VR256:$src)),
6485 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6486 def : Pat<(v4f64 (ftrunc VR256:$src)),
6487 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6490 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6491 memopv4f32, memopv2f64,
6492 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6493 let Constraints = "$src1 = $dst" in
6494 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6495 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6497 let Predicates = [UseSSE41] in {
6498 def : Pat<(ffloor FR32:$src),
6499 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6500 def : Pat<(f64 (ffloor FR64:$src)),
6501 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6502 def : Pat<(f32 (fnearbyint FR32:$src)),
6503 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6504 def : Pat<(f64 (fnearbyint FR64:$src)),
6505 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6506 def : Pat<(f32 (fceil FR32:$src)),
6507 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6508 def : Pat<(f64 (fceil FR64:$src)),
6509 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6510 def : Pat<(f32 (frint FR32:$src)),
6511 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6512 def : Pat<(f64 (frint FR64:$src)),
6513 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6514 def : Pat<(f32 (ftrunc FR32:$src)),
6515 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6516 def : Pat<(f64 (ftrunc FR64:$src)),
6517 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6519 def : Pat<(v4f32 (ffloor VR128:$src)),
6520 (ROUNDPSr VR128:$src, (i32 0x1))>;
6521 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6522 (ROUNDPSr VR128:$src, (i32 0xC))>;
6523 def : Pat<(v4f32 (fceil VR128:$src)),
6524 (ROUNDPSr VR128:$src, (i32 0x2))>;
6525 def : Pat<(v4f32 (frint VR128:$src)),
6526 (ROUNDPSr VR128:$src, (i32 0x4))>;
6527 def : Pat<(v4f32 (ftrunc VR128:$src)),
6528 (ROUNDPSr VR128:$src, (i32 0x3))>;
6530 def : Pat<(v2f64 (ffloor VR128:$src)),
6531 (ROUNDPDr VR128:$src, (i32 0x1))>;
6532 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6533 (ROUNDPDr VR128:$src, (i32 0xC))>;
6534 def : Pat<(v2f64 (fceil VR128:$src)),
6535 (ROUNDPDr VR128:$src, (i32 0x2))>;
6536 def : Pat<(v2f64 (frint VR128:$src)),
6537 (ROUNDPDr VR128:$src, (i32 0x4))>;
6538 def : Pat<(v2f64 (ftrunc VR128:$src)),
6539 (ROUNDPDr VR128:$src, (i32 0x3))>;
6542 //===----------------------------------------------------------------------===//
6543 // SSE4.1 - Packed Bit Test
6544 //===----------------------------------------------------------------------===//
6546 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6547 // the intel intrinsic that corresponds to this.
6548 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6549 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6550 "vptest\t{$src2, $src1|$src1, $src2}",
6551 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6553 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6554 "vptest\t{$src2, $src1|$src1, $src2}",
6555 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6558 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6559 "vptest\t{$src2, $src1|$src1, $src2}",
6560 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6562 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6563 "vptest\t{$src2, $src1|$src1, $src2}",
6564 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6568 let Defs = [EFLAGS] in {
6569 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6570 "ptest\t{$src2, $src1|$src1, $src2}",
6571 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6573 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6574 "ptest\t{$src2, $src1|$src1, $src2}",
6575 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6579 // The bit test instructions below are AVX only
6580 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6581 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6582 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6583 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6584 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6585 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6586 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6587 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6591 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6592 let ExeDomain = SSEPackedSingle in {
6593 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6594 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6597 let ExeDomain = SSEPackedDouble in {
6598 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6599 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6604 //===----------------------------------------------------------------------===//
6605 // SSE4.1 - Misc Instructions
6606 //===----------------------------------------------------------------------===//
6608 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6609 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6610 "popcnt{w}\t{$src, $dst|$dst, $src}",
6611 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6613 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6614 "popcnt{w}\t{$src, $dst|$dst, $src}",
6615 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6616 (implicit EFLAGS)]>, OpSize, XS;
6618 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6619 "popcnt{l}\t{$src, $dst|$dst, $src}",
6620 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6622 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6623 "popcnt{l}\t{$src, $dst|$dst, $src}",
6624 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6625 (implicit EFLAGS)]>, XS;
6627 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6628 "popcnt{q}\t{$src, $dst|$dst, $src}",
6629 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6631 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6632 "popcnt{q}\t{$src, $dst|$dst, $src}",
6633 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6634 (implicit EFLAGS)]>, XS;
6639 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6640 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6641 Intrinsic IntId128> {
6642 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6644 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6645 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6646 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6648 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6651 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6654 let Predicates = [HasAVX] in
6655 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6656 int_x86_sse41_phminposuw>, VEX;
6657 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6658 int_x86_sse41_phminposuw>;
6660 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6661 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6662 Intrinsic IntId128, bit Is2Addr = 1> {
6663 let isCommutable = 1 in
6664 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6665 (ins VR128:$src1, VR128:$src2),
6667 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6668 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6669 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6670 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6671 (ins VR128:$src1, i128mem:$src2),
6673 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6674 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6676 (IntId128 VR128:$src1,
6677 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6680 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6681 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6682 Intrinsic IntId256> {
6683 let isCommutable = 1 in
6684 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6685 (ins VR256:$src1, VR256:$src2),
6686 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6687 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6688 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6689 (ins VR256:$src1, i256mem:$src2),
6690 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6692 (IntId256 VR256:$src1,
6693 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6697 /// SS48I_binop_rm - Simple SSE41 binary operator.
6698 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6699 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6700 X86MemOperand x86memop, bit Is2Addr = 1> {
6701 let isCommutable = 1 in
6702 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6703 (ins RC:$src1, RC:$src2),
6705 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6706 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6707 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6708 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6709 (ins RC:$src1, x86memop:$src2),
6711 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6712 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6714 (OpVT (OpNode RC:$src1,
6715 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6718 let Predicates = [HasAVX] in {
6719 let isCommutable = 0 in
6720 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6722 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6723 memopv2i64, i128mem, 0>, VEX_4V;
6724 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6725 memopv2i64, i128mem, 0>, VEX_4V;
6726 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6727 memopv2i64, i128mem, 0>, VEX_4V;
6728 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6729 memopv2i64, i128mem, 0>, VEX_4V;
6730 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6731 memopv2i64, i128mem, 0>, VEX_4V;
6732 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6733 memopv2i64, i128mem, 0>, VEX_4V;
6734 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6735 memopv2i64, i128mem, 0>, VEX_4V;
6736 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6737 memopv2i64, i128mem, 0>, VEX_4V;
6738 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6742 let Predicates = [HasAVX2] in {
6743 let isCommutable = 0 in
6744 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6745 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6746 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6747 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6748 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6749 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6750 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6751 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6752 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6753 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6754 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6755 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6756 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6757 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6758 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6759 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6760 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6761 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6762 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6763 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6766 let Constraints = "$src1 = $dst" in {
6767 let isCommutable = 0 in
6768 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6769 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6770 memopv2i64, i128mem>;
6771 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6772 memopv2i64, i128mem>;
6773 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6774 memopv2i64, i128mem>;
6775 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6776 memopv2i64, i128mem>;
6777 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6778 memopv2i64, i128mem>;
6779 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6780 memopv2i64, i128mem>;
6781 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6782 memopv2i64, i128mem>;
6783 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6784 memopv2i64, i128mem>;
6785 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6788 let Predicates = [HasAVX] in {
6789 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6790 memopv2i64, i128mem, 0>, VEX_4V;
6791 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6792 memopv2i64, i128mem, 0>, VEX_4V;
6794 let Predicates = [HasAVX2] in {
6795 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6796 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6797 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6798 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6801 let Constraints = "$src1 = $dst" in {
6802 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6803 memopv2i64, i128mem>;
6804 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6805 memopv2i64, i128mem>;
6808 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6809 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6810 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6811 X86MemOperand x86memop, bit Is2Addr = 1> {
6812 let isCommutable = 1 in
6813 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6814 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6816 !strconcat(OpcodeStr,
6817 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6818 !strconcat(OpcodeStr,
6819 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6820 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6822 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6823 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6825 !strconcat(OpcodeStr,
6826 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6827 !strconcat(OpcodeStr,
6828 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6831 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6835 let Predicates = [HasAVX] in {
6836 let isCommutable = 0 in {
6837 let ExeDomain = SSEPackedSingle in {
6838 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6839 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6840 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6841 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6842 f256mem, 0>, VEX_4V, VEX_L;
6844 let ExeDomain = SSEPackedDouble in {
6845 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6846 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6847 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6848 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6849 f256mem, 0>, VEX_4V, VEX_L;
6851 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6852 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6853 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6854 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6856 let ExeDomain = SSEPackedSingle in
6857 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6858 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6859 let ExeDomain = SSEPackedDouble in
6860 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6861 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6862 let ExeDomain = SSEPackedSingle in
6863 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6864 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6867 let Predicates = [HasAVX2] in {
6868 let isCommutable = 0 in {
6869 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6870 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6871 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6872 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6876 let Constraints = "$src1 = $dst" in {
6877 let isCommutable = 0 in {
6878 let ExeDomain = SSEPackedSingle in
6879 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6880 VR128, memopv4f32, f128mem>;
6881 let ExeDomain = SSEPackedDouble in
6882 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6883 VR128, memopv2f64, f128mem>;
6884 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6885 VR128, memopv2i64, i128mem>;
6886 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6887 VR128, memopv2i64, i128mem>;
6889 let ExeDomain = SSEPackedSingle in
6890 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6891 VR128, memopv4f32, f128mem>;
6892 let ExeDomain = SSEPackedDouble in
6893 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6894 VR128, memopv2f64, f128mem>;
6897 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6898 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6899 RegisterClass RC, X86MemOperand x86memop,
6900 PatFrag mem_frag, Intrinsic IntId> {
6901 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6902 (ins RC:$src1, RC:$src2, RC:$src3),
6903 !strconcat(OpcodeStr,
6904 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6905 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6906 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6908 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6909 (ins RC:$src1, x86memop:$src2, RC:$src3),
6910 !strconcat(OpcodeStr,
6911 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6913 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6915 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6918 let Predicates = [HasAVX] in {
6919 let ExeDomain = SSEPackedDouble in {
6920 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6921 memopv2f64, int_x86_sse41_blendvpd>;
6922 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6923 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6924 } // ExeDomain = SSEPackedDouble
6925 let ExeDomain = SSEPackedSingle in {
6926 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6927 memopv4f32, int_x86_sse41_blendvps>;
6928 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6929 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6930 } // ExeDomain = SSEPackedSingle
6931 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6932 memopv2i64, int_x86_sse41_pblendvb>;
6935 let Predicates = [HasAVX2] in {
6936 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6937 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6940 let Predicates = [HasAVX] in {
6941 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6942 (v16i8 VR128:$src2))),
6943 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6944 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6945 (v4i32 VR128:$src2))),
6946 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6947 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6948 (v4f32 VR128:$src2))),
6949 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6950 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6951 (v2i64 VR128:$src2))),
6952 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6953 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6954 (v2f64 VR128:$src2))),
6955 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6956 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6957 (v8i32 VR256:$src2))),
6958 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6959 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6960 (v8f32 VR256:$src2))),
6961 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6962 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6963 (v4i64 VR256:$src2))),
6964 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6965 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6966 (v4f64 VR256:$src2))),
6967 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6969 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6971 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6972 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6974 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6976 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6978 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6979 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6981 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6982 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6984 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6987 let Predicates = [HasAVX2] in {
6988 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6989 (v32i8 VR256:$src2))),
6990 (VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
6991 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6993 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6996 /// SS41I_ternary_int - SSE 4.1 ternary operator
6997 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6998 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6999 X86MemOperand x86memop, Intrinsic IntId> {
7000 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7001 (ins VR128:$src1, VR128:$src2),
7002 !strconcat(OpcodeStr,
7003 "\t{$src2, $dst|$dst, $src2}"),
7004 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
7007 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7008 (ins VR128:$src1, x86memop:$src2),
7009 !strconcat(OpcodeStr,
7010 "\t{$src2, $dst|$dst, $src2}"),
7013 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
7017 let ExeDomain = SSEPackedDouble in
7018 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7019 int_x86_sse41_blendvpd>;
7020 let ExeDomain = SSEPackedSingle in
7021 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7022 int_x86_sse41_blendvps>;
7023 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7024 int_x86_sse41_pblendvb>;
7026 // Aliases with the implicit xmm0 argument
7027 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7028 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7029 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7030 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7031 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7032 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7033 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7034 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7035 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7036 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7037 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7038 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7040 let Predicates = [UseSSE41] in {
7041 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7042 (v16i8 VR128:$src2))),
7043 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7044 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7045 (v4i32 VR128:$src2))),
7046 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7047 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7048 (v4f32 VR128:$src2))),
7049 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7050 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7051 (v2i64 VR128:$src2))),
7052 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7053 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7054 (v2f64 VR128:$src2))),
7055 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7057 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7059 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7060 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7062 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7063 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7065 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7069 let Predicates = [HasAVX] in
7070 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7071 "vmovntdqa\t{$src, $dst|$dst, $src}",
7072 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7074 let Predicates = [HasAVX2] in
7075 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7076 "vmovntdqa\t{$src, $dst|$dst, $src}",
7077 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7079 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7080 "movntdqa\t{$src, $dst|$dst, $src}",
7081 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7084 //===----------------------------------------------------------------------===//
7085 // SSE4.2 - Compare Instructions
7086 //===----------------------------------------------------------------------===//
7088 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7089 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7090 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7091 X86MemOperand x86memop, bit Is2Addr = 1> {
7092 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7093 (ins RC:$src1, RC:$src2),
7095 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7096 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7097 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7099 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7100 (ins RC:$src1, x86memop:$src2),
7102 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7103 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7105 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7108 let Predicates = [HasAVX] in
7109 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7110 memopv2i64, i128mem, 0>, VEX_4V;
7112 let Predicates = [HasAVX2] in
7113 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7114 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
7116 let Constraints = "$src1 = $dst" in
7117 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7118 memopv2i64, i128mem>;
7120 //===----------------------------------------------------------------------===//
7121 // SSE4.2 - String/text Processing Instructions
7122 //===----------------------------------------------------------------------===//
7124 // Packed Compare Implicit Length Strings, Return Mask
7125 multiclass pseudo_pcmpistrm<string asm> {
7126 def REG : PseudoI<(outs VR128:$dst),
7127 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7128 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7130 def MEM : PseudoI<(outs VR128:$dst),
7131 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7132 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7133 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7136 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7137 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7138 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7141 multiclass pcmpistrm_SS42AI<string asm> {
7142 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7143 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7144 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7147 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7148 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7149 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7153 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7154 let Predicates = [HasAVX] in
7155 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7156 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7159 // Packed Compare Explicit Length Strings, Return Mask
7160 multiclass pseudo_pcmpestrm<string asm> {
7161 def REG : PseudoI<(outs VR128:$dst),
7162 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7163 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7164 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7165 def MEM : PseudoI<(outs VR128:$dst),
7166 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7167 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7168 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7171 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7172 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7173 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7176 multiclass SS42AI_pcmpestrm<string asm> {
7177 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7178 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7179 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7182 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7183 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7184 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7188 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7189 let Predicates = [HasAVX] in
7190 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7191 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7194 // Packed Compare Implicit Length Strings, Return Index
7195 multiclass pseudo_pcmpistri<string asm> {
7196 def REG : PseudoI<(outs GR32:$dst),
7197 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7198 [(set GR32:$dst, EFLAGS,
7199 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7200 def MEM : PseudoI<(outs GR32:$dst),
7201 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7202 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7203 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7206 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7207 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7208 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7211 multiclass SS42AI_pcmpistri<string asm> {
7212 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7213 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7214 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7217 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7218 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7219 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7223 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7224 let Predicates = [HasAVX] in
7225 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7226 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7229 // Packed Compare Explicit Length Strings, Return Index
7230 multiclass pseudo_pcmpestri<string asm> {
7231 def REG : PseudoI<(outs GR32:$dst),
7232 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7233 [(set GR32:$dst, EFLAGS,
7234 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7235 def MEM : PseudoI<(outs GR32:$dst),
7236 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7237 [(set GR32:$dst, EFLAGS,
7238 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7242 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7243 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7244 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7247 multiclass SS42AI_pcmpestri<string asm> {
7248 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7249 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7250 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7253 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7254 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7255 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7259 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7260 let Predicates = [HasAVX] in
7261 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7262 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7265 //===----------------------------------------------------------------------===//
7266 // SSE4.2 - CRC Instructions
7267 //===----------------------------------------------------------------------===//
7269 // No CRC instructions have AVX equivalents
7271 // crc intrinsic instruction
7272 // This set of instructions are only rm, the only difference is the size
7274 let Constraints = "$src1 = $dst" in {
7275 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7276 (ins GR32:$src1, i8mem:$src2),
7277 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7279 (int_x86_sse42_crc32_32_8 GR32:$src1,
7280 (load addr:$src2)))]>;
7281 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7282 (ins GR32:$src1, GR8:$src2),
7283 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7285 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7286 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7287 (ins GR32:$src1, i16mem:$src2),
7288 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7290 (int_x86_sse42_crc32_32_16 GR32:$src1,
7291 (load addr:$src2)))]>,
7293 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7294 (ins GR32:$src1, GR16:$src2),
7295 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7297 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7299 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7300 (ins GR32:$src1, i32mem:$src2),
7301 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7303 (int_x86_sse42_crc32_32_32 GR32:$src1,
7304 (load addr:$src2)))]>;
7305 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7306 (ins GR32:$src1, GR32:$src2),
7307 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7309 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7310 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7311 (ins GR64:$src1, i8mem:$src2),
7312 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7314 (int_x86_sse42_crc32_64_8 GR64:$src1,
7315 (load addr:$src2)))]>,
7317 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7318 (ins GR64:$src1, GR8:$src2),
7319 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7321 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7323 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7324 (ins GR64:$src1, i64mem:$src2),
7325 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7327 (int_x86_sse42_crc32_64_64 GR64:$src1,
7328 (load addr:$src2)))]>,
7330 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7331 (ins GR64:$src1, GR64:$src2),
7332 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7334 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7338 //===----------------------------------------------------------------------===//
7339 // AES-NI Instructions
7340 //===----------------------------------------------------------------------===//
7342 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7343 Intrinsic IntId128, bit Is2Addr = 1> {
7344 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7345 (ins VR128:$src1, VR128:$src2),
7347 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7348 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7349 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7351 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7352 (ins VR128:$src1, i128mem:$src2),
7354 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7357 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7360 // Perform One Round of an AES Encryption/Decryption Flow
7361 let Predicates = [HasAVX, HasAES] in {
7362 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7363 int_x86_aesni_aesenc, 0>, VEX_4V;
7364 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7365 int_x86_aesni_aesenclast, 0>, VEX_4V;
7366 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7367 int_x86_aesni_aesdec, 0>, VEX_4V;
7368 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7369 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7372 let Constraints = "$src1 = $dst" in {
7373 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7374 int_x86_aesni_aesenc>;
7375 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7376 int_x86_aesni_aesenclast>;
7377 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7378 int_x86_aesni_aesdec>;
7379 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7380 int_x86_aesni_aesdeclast>;
7383 // Perform the AES InvMixColumn Transformation
7384 let Predicates = [HasAVX, HasAES] in {
7385 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7387 "vaesimc\t{$src1, $dst|$dst, $src1}",
7389 (int_x86_aesni_aesimc VR128:$src1))]>,
7391 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7392 (ins i128mem:$src1),
7393 "vaesimc\t{$src1, $dst|$dst, $src1}",
7394 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7397 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7399 "aesimc\t{$src1, $dst|$dst, $src1}",
7401 (int_x86_aesni_aesimc VR128:$src1))]>,
7403 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7404 (ins i128mem:$src1),
7405 "aesimc\t{$src1, $dst|$dst, $src1}",
7406 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7409 // AES Round Key Generation Assist
7410 let Predicates = [HasAVX, HasAES] in {
7411 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7412 (ins VR128:$src1, i8imm:$src2),
7413 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7415 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7417 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7418 (ins i128mem:$src1, i8imm:$src2),
7419 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7421 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7424 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7425 (ins VR128:$src1, i8imm:$src2),
7426 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7428 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7430 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7431 (ins i128mem:$src1, i8imm:$src2),
7432 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7434 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7437 //===----------------------------------------------------------------------===//
7438 // PCLMUL Instructions
7439 //===----------------------------------------------------------------------===//
7441 // AVX carry-less Multiplication instructions
7442 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7443 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7444 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7446 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7448 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7449 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7450 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7451 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7452 (memopv2i64 addr:$src2), imm:$src3))]>;
7454 // Carry-less Multiplication instructions
7455 let Constraints = "$src1 = $dst" in {
7456 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7457 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7458 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7460 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7462 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7463 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7464 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7465 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7466 (memopv2i64 addr:$src2), imm:$src3))]>;
7467 } // Constraints = "$src1 = $dst"
7470 multiclass pclmul_alias<string asm, int immop> {
7471 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7472 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7474 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7475 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7477 def : InstAlias<!strconcat("vpclmul", asm,
7478 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7479 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7481 def : InstAlias<!strconcat("vpclmul", asm,
7482 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7483 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7485 defm : pclmul_alias<"hqhq", 0x11>;
7486 defm : pclmul_alias<"hqlq", 0x01>;
7487 defm : pclmul_alias<"lqhq", 0x10>;
7488 defm : pclmul_alias<"lqlq", 0x00>;
7490 //===----------------------------------------------------------------------===//
7491 // SSE4A Instructions
7492 //===----------------------------------------------------------------------===//
7494 let Predicates = [HasSSE4A] in {
7496 let Constraints = "$src = $dst" in {
7497 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7498 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7499 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7500 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7501 imm:$idx))]>, TB, OpSize;
7502 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7503 (ins VR128:$src, VR128:$mask),
7504 "extrq\t{$mask, $src|$src, $mask}",
7505 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7506 VR128:$mask))]>, TB, OpSize;
7508 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7509 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7510 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7511 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7512 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7513 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7514 (ins VR128:$src, VR128:$mask),
7515 "insertq\t{$mask, $src|$src, $mask}",
7516 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7517 VR128:$mask))]>, XD;
7520 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7521 "movntss\t{$src, $dst|$dst, $src}",
7522 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7524 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7525 "movntsd\t{$src, $dst|$dst, $src}",
7526 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7529 //===----------------------------------------------------------------------===//
7531 //===----------------------------------------------------------------------===//
7533 //===----------------------------------------------------------------------===//
7534 // VBROADCAST - Load from memory and broadcast to all elements of the
7535 // destination operand
7537 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7538 X86MemOperand x86memop, Intrinsic Int> :
7539 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7540 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7541 [(set RC:$dst, (Int addr:$src))]>, VEX;
7543 // AVX2 adds register forms
7544 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7546 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7547 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7548 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7550 let ExeDomain = SSEPackedSingle in {
7551 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7552 int_x86_avx_vbroadcast_ss>;
7553 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7554 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7556 let ExeDomain = SSEPackedDouble in
7557 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7558 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7559 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7560 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7562 let ExeDomain = SSEPackedSingle in {
7563 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7564 int_x86_avx2_vbroadcast_ss_ps>;
7565 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7566 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7568 let ExeDomain = SSEPackedDouble in
7569 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7570 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7572 let Predicates = [HasAVX2] in
7573 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7574 int_x86_avx2_vbroadcasti128>, VEX_L;
7576 let Predicates = [HasAVX] in
7577 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7578 (VBROADCASTF128 addr:$src)>;
7581 //===----------------------------------------------------------------------===//
7582 // VINSERTF128 - Insert packed floating-point values
7584 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7585 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7586 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7587 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7590 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7591 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7592 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7596 let Predicates = [HasAVX] in {
7597 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7599 (VINSERTF128rr VR256:$src1, VR128:$src2,
7600 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7601 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7603 (VINSERTF128rr VR256:$src1, VR128:$src2,
7604 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7606 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7608 (VINSERTF128rm VR256:$src1, addr:$src2,
7609 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7610 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7612 (VINSERTF128rm VR256:$src1, addr:$src2,
7613 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7616 let Predicates = [HasAVX1Only] in {
7617 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7619 (VINSERTF128rr VR256:$src1, VR128:$src2,
7620 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7621 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7623 (VINSERTF128rr VR256:$src1, VR128:$src2,
7624 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7625 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7627 (VINSERTF128rr VR256:$src1, VR128:$src2,
7628 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7629 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7631 (VINSERTF128rr VR256:$src1, VR128:$src2,
7632 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7634 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7636 (VINSERTF128rm VR256:$src1, addr:$src2,
7637 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7638 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7639 (bc_v4i32 (memopv2i64 addr:$src2)),
7641 (VINSERTF128rm VR256:$src1, addr:$src2,
7642 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7643 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7644 (bc_v16i8 (memopv2i64 addr:$src2)),
7646 (VINSERTF128rm VR256:$src1, addr:$src2,
7647 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7648 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7649 (bc_v8i16 (memopv2i64 addr:$src2)),
7651 (VINSERTF128rm VR256:$src1, addr:$src2,
7652 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7655 //===----------------------------------------------------------------------===//
7656 // VEXTRACTF128 - Extract packed floating-point values
7658 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7659 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7660 (ins VR256:$src1, i8imm:$src2),
7661 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7664 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7665 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7666 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7671 let Predicates = [HasAVX] in {
7672 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7673 (v4f32 (VEXTRACTF128rr
7674 (v8f32 VR256:$src1),
7675 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7676 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7677 (v2f64 (VEXTRACTF128rr
7678 (v4f64 VR256:$src1),
7679 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7681 def : Pat<(alignedstore (v4f32 (vextractf128_extract:$ext (v8f32 VR256:$src1),
7682 (iPTR imm))), addr:$dst),
7683 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7684 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7685 def : Pat<(alignedstore (v2f64 (vextractf128_extract:$ext (v4f64 VR256:$src1),
7686 (iPTR imm))), addr:$dst),
7687 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7688 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7691 let Predicates = [HasAVX1Only] in {
7692 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7693 (v2i64 (VEXTRACTF128rr
7694 (v4i64 VR256:$src1),
7695 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7696 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7697 (v4i32 (VEXTRACTF128rr
7698 (v8i32 VR256:$src1),
7699 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7700 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7701 (v8i16 (VEXTRACTF128rr
7702 (v16i16 VR256:$src1),
7703 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7704 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7705 (v16i8 (VEXTRACTF128rr
7706 (v32i8 VR256:$src1),
7707 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7709 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7710 (iPTR imm))), addr:$dst),
7711 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7712 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7713 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7714 (iPTR imm))), addr:$dst),
7715 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7716 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7717 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7718 (iPTR imm))), addr:$dst),
7719 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7720 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7721 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7722 (iPTR imm))), addr:$dst),
7723 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7724 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7727 //===----------------------------------------------------------------------===//
7728 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7730 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7731 Intrinsic IntLd, Intrinsic IntLd256,
7732 Intrinsic IntSt, Intrinsic IntSt256> {
7733 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7734 (ins VR128:$src1, f128mem:$src2),
7735 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7736 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7738 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7739 (ins VR256:$src1, f256mem:$src2),
7740 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7741 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7743 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7744 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7745 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7746 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7747 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7748 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7749 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7750 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7753 let ExeDomain = SSEPackedSingle in
7754 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7755 int_x86_avx_maskload_ps,
7756 int_x86_avx_maskload_ps_256,
7757 int_x86_avx_maskstore_ps,
7758 int_x86_avx_maskstore_ps_256>;
7759 let ExeDomain = SSEPackedDouble in
7760 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7761 int_x86_avx_maskload_pd,
7762 int_x86_avx_maskload_pd_256,
7763 int_x86_avx_maskstore_pd,
7764 int_x86_avx_maskstore_pd_256>;
7766 //===----------------------------------------------------------------------===//
7767 // VPERMIL - Permute Single and Double Floating-Point Values
7769 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7770 RegisterClass RC, X86MemOperand x86memop_f,
7771 X86MemOperand x86memop_i, PatFrag i_frag,
7772 Intrinsic IntVar, ValueType vt> {
7773 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7774 (ins RC:$src1, RC:$src2),
7775 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7776 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7777 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7778 (ins RC:$src1, x86memop_i:$src2),
7779 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7780 [(set RC:$dst, (IntVar RC:$src1,
7781 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7783 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7784 (ins RC:$src1, i8imm:$src2),
7785 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7786 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7787 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7788 (ins x86memop_f:$src1, i8imm:$src2),
7789 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7791 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7794 let ExeDomain = SSEPackedSingle in {
7795 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7796 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7797 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7798 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7800 let ExeDomain = SSEPackedDouble in {
7801 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7802 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7803 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7804 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7807 let Predicates = [HasAVX] in {
7808 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7809 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7810 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7811 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7812 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7814 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7815 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7816 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7818 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7819 (VPERMILPDri VR128:$src1, imm:$imm)>;
7820 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7821 (VPERMILPDmi addr:$src1, imm:$imm)>;
7824 //===----------------------------------------------------------------------===//
7825 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7827 let ExeDomain = SSEPackedSingle in {
7828 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7829 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7830 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7831 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7832 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7833 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7834 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7835 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7836 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7837 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7840 let Predicates = [HasAVX] in {
7841 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7842 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7843 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7844 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7845 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7848 let Predicates = [HasAVX1Only] in {
7849 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7850 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7851 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7852 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7853 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7854 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7855 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7856 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7858 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7859 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7860 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7861 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7862 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7863 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7864 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7865 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7866 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7867 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7868 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7869 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7872 //===----------------------------------------------------------------------===//
7873 // VZERO - Zero YMM registers
7875 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7876 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7877 // Zero All YMM registers
7878 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7879 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7881 // Zero Upper bits of YMM registers
7882 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7883 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7886 //===----------------------------------------------------------------------===//
7887 // Half precision conversion instructions
7888 //===----------------------------------------------------------------------===//
7889 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7890 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7891 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7892 [(set RC:$dst, (Int VR128:$src))]>,
7894 let neverHasSideEffects = 1, mayLoad = 1 in
7895 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7896 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7899 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7900 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7901 (ins RC:$src1, i32i8imm:$src2),
7902 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7903 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7905 let neverHasSideEffects = 1, mayStore = 1 in
7906 def mr : Ii8<0x1D, MRMDestMem, (outs),
7907 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7908 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7912 let Predicates = [HasAVX, HasF16C] in {
7913 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7914 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7915 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7916 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7919 //===----------------------------------------------------------------------===//
7920 // AVX2 Instructions
7921 //===----------------------------------------------------------------------===//
7923 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7924 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7925 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7926 X86MemOperand x86memop> {
7927 let isCommutable = 1 in
7928 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7929 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7930 !strconcat(OpcodeStr,
7931 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7932 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7934 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7935 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7936 !strconcat(OpcodeStr,
7937 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7940 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7944 let isCommutable = 0 in {
7945 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7946 VR128, memopv2i64, i128mem>;
7947 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7948 VR256, memopv4i64, i256mem>, VEX_L;
7951 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
7953 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7954 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
7956 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7958 //===----------------------------------------------------------------------===//
7959 // VPBROADCAST - Load from memory and broadcast to all elements of the
7960 // destination operand
7962 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7963 X86MemOperand x86memop, PatFrag ld_frag,
7964 Intrinsic Int128, Intrinsic Int256> {
7965 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7966 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7967 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7968 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7969 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7971 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7972 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7973 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7974 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
7975 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7976 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7978 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
7982 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7983 int_x86_avx2_pbroadcastb_128,
7984 int_x86_avx2_pbroadcastb_256>;
7985 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7986 int_x86_avx2_pbroadcastw_128,
7987 int_x86_avx2_pbroadcastw_256>;
7988 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7989 int_x86_avx2_pbroadcastd_128,
7990 int_x86_avx2_pbroadcastd_256>;
7991 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7992 int_x86_avx2_pbroadcastq_128,
7993 int_x86_avx2_pbroadcastq_256>;
7995 let Predicates = [HasAVX2] in {
7996 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7997 (VPBROADCASTBrm addr:$src)>;
7998 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7999 (VPBROADCASTBYrm addr:$src)>;
8000 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8001 (VPBROADCASTWrm addr:$src)>;
8002 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8003 (VPBROADCASTWYrm addr:$src)>;
8004 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8005 (VPBROADCASTDrm addr:$src)>;
8006 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8007 (VPBROADCASTDYrm addr:$src)>;
8008 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8009 (VPBROADCASTQrm addr:$src)>;
8010 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8011 (VPBROADCASTQYrm addr:$src)>;
8013 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8014 (VPBROADCASTBrr VR128:$src)>;
8015 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8016 (VPBROADCASTBYrr VR128:$src)>;
8017 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8018 (VPBROADCASTWrr VR128:$src)>;
8019 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8020 (VPBROADCASTWYrr VR128:$src)>;
8021 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8022 (VPBROADCASTDrr VR128:$src)>;
8023 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8024 (VPBROADCASTDYrr VR128:$src)>;
8025 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8026 (VPBROADCASTQrr VR128:$src)>;
8027 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8028 (VPBROADCASTQYrr VR128:$src)>;
8029 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8030 (VBROADCASTSSrr VR128:$src)>;
8031 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8032 (VBROADCASTSSYrr VR128:$src)>;
8033 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8034 (VPBROADCASTQrr VR128:$src)>;
8035 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8036 (VBROADCASTSDYrr VR128:$src)>;
8038 // Provide fallback in case the load node that is used in the patterns above
8039 // is used by additional users, which prevents the pattern selection.
8040 let AddedComplexity = 20 in {
8041 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8042 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8043 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8044 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8045 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8046 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8048 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8049 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8050 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8051 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8052 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8053 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8057 // AVX1 broadcast patterns
8058 let Predicates = [HasAVX1Only] in {
8059 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8060 (VBROADCASTSSYrm addr:$src)>;
8061 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8062 (VBROADCASTSDYrm addr:$src)>;
8063 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8064 (VBROADCASTSSrm addr:$src)>;
8067 let Predicates = [HasAVX] in {
8068 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8069 (VBROADCASTSSYrm addr:$src)>;
8070 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8071 (VBROADCASTSDYrm addr:$src)>;
8072 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8073 (VBROADCASTSSrm addr:$src)>;
8075 // Provide fallback in case the load node that is used in the patterns above
8076 // is used by additional users, which prevents the pattern selection.
8077 let AddedComplexity = 20 in {
8078 // 128bit broadcasts:
8079 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8080 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8081 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8082 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8083 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8084 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8085 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8086 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8087 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8088 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8090 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8091 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8092 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8093 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8094 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8095 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8096 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8097 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8098 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8099 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8103 //===----------------------------------------------------------------------===//
8104 // VPERM - Permute instructions
8107 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8109 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8110 (ins VR256:$src1, VR256:$src2),
8111 !strconcat(OpcodeStr,
8112 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8114 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8116 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8117 (ins VR256:$src1, i256mem:$src2),
8118 !strconcat(OpcodeStr,
8119 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8121 (OpVT (X86VPermv VR256:$src1,
8122 (bitconvert (mem_frag addr:$src2)))))]>,
8126 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
8127 let ExeDomain = SSEPackedSingle in
8128 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
8130 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8132 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8133 (ins VR256:$src1, i8imm:$src2),
8134 !strconcat(OpcodeStr,
8135 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8137 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8139 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8140 (ins i256mem:$src1, i8imm:$src2),
8141 !strconcat(OpcodeStr,
8142 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8144 (OpVT (X86VPermi (mem_frag addr:$src1),
8145 (i8 imm:$src2))))]>, VEX, VEX_L;
8148 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
8149 let ExeDomain = SSEPackedDouble in
8150 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
8152 //===----------------------------------------------------------------------===//
8153 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8155 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8156 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8157 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8158 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8159 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8160 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8161 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8162 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8163 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
8164 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8166 let Predicates = [HasAVX2] in {
8167 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8168 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8169 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8170 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8171 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8172 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8174 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
8176 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8177 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8178 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
8179 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8180 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
8182 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8186 //===----------------------------------------------------------------------===//
8187 // VINSERTI128 - Insert packed integer values
8189 let neverHasSideEffects = 1 in {
8190 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8191 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8192 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8195 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8196 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8197 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8201 let Predicates = [HasAVX2] in {
8202 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8204 (VINSERTI128rr VR256:$src1, VR128:$src2,
8205 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8206 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8208 (VINSERTI128rr VR256:$src1, VR128:$src2,
8209 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8210 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8212 (VINSERTI128rr VR256:$src1, VR128:$src2,
8213 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8214 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8216 (VINSERTI128rr VR256:$src1, VR128:$src2,
8217 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8219 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
8221 (VINSERTI128rm VR256:$src1, addr:$src2,
8222 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8223 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
8224 (bc_v4i32 (memopv2i64 addr:$src2)),
8226 (VINSERTI128rm VR256:$src1, addr:$src2,
8227 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8228 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
8229 (bc_v16i8 (memopv2i64 addr:$src2)),
8231 (VINSERTI128rm VR256:$src1, addr:$src2,
8232 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8233 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
8234 (bc_v8i16 (memopv2i64 addr:$src2)),
8236 (VINSERTI128rm VR256:$src1, addr:$src2,
8237 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8240 //===----------------------------------------------------------------------===//
8241 // VEXTRACTI128 - Extract packed integer values
8243 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8244 (ins VR256:$src1, i8imm:$src2),
8245 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8247 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8249 let neverHasSideEffects = 1, mayStore = 1 in
8250 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8251 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8252 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8255 let Predicates = [HasAVX2] in {
8256 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8257 (v2i64 (VEXTRACTI128rr
8258 (v4i64 VR256:$src1),
8259 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8260 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8261 (v4i32 (VEXTRACTI128rr
8262 (v8i32 VR256:$src1),
8263 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8264 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8265 (v8i16 (VEXTRACTI128rr
8266 (v16i16 VR256:$src1),
8267 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8268 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8269 (v16i8 (VEXTRACTI128rr
8270 (v32i8 VR256:$src1),
8271 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8273 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
8274 (iPTR imm))), addr:$dst),
8275 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8276 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8277 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
8278 (iPTR imm))), addr:$dst),
8279 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8280 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8281 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
8282 (iPTR imm))), addr:$dst),
8283 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8284 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8285 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
8286 (iPTR imm))), addr:$dst),
8287 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8288 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8291 //===----------------------------------------------------------------------===//
8292 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8294 multiclass avx2_pmovmask<string OpcodeStr,
8295 Intrinsic IntLd128, Intrinsic IntLd256,
8296 Intrinsic IntSt128, Intrinsic IntSt256> {
8297 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8298 (ins VR128:$src1, i128mem:$src2),
8299 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8300 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8301 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8302 (ins VR256:$src1, i256mem:$src2),
8303 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8304 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8306 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8307 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8308 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8309 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8310 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8311 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8312 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8313 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8316 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8317 int_x86_avx2_maskload_d,
8318 int_x86_avx2_maskload_d_256,
8319 int_x86_avx2_maskstore_d,
8320 int_x86_avx2_maskstore_d_256>;
8321 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8322 int_x86_avx2_maskload_q,
8323 int_x86_avx2_maskload_q_256,
8324 int_x86_avx2_maskstore_q,
8325 int_x86_avx2_maskstore_q_256>, VEX_W;
8328 //===----------------------------------------------------------------------===//
8329 // Variable Bit Shifts
8331 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8332 ValueType vt128, ValueType vt256> {
8333 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8334 (ins VR128:$src1, VR128:$src2),
8335 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8337 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8339 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8340 (ins VR128:$src1, i128mem:$src2),
8341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8343 (vt128 (OpNode VR128:$src1,
8344 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8346 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8347 (ins VR256:$src1, VR256:$src2),
8348 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8350 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8352 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8353 (ins VR256:$src1, i256mem:$src2),
8354 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8356 (vt256 (OpNode VR256:$src1,
8357 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8361 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8362 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8363 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8364 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8365 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8367 //===----------------------------------------------------------------------===//
8368 // VGATHER - GATHER Operations
8369 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8370 X86MemOperand memop128, X86MemOperand memop256> {
8371 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8372 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8373 !strconcat(OpcodeStr,
8374 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8376 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8377 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8378 !strconcat(OpcodeStr,
8379 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8380 []>, VEX_4VOp3, VEX_L;
8383 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
8384 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8385 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8386 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8387 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8388 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8389 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8390 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8391 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;