1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE scalar FP Instructions
18 //===----------------------------------------------------------------------===//
20 // Instruction templates
21 // SSI - SSE1 instructions with XS prefix.
22 // SDI - SSE2 instructions with XD prefix.
23 // PSI - SSE1 instructions with TB prefix.
24 // PDI - SSE2 instructions with TB and OpSize prefixes.
25 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
26 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
27 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
28 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
29 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
30 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
31 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
32 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
34 // Some 'special' instructions
35 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
37 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
38 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
40 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
42 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
43 // scheduler into a branch sequence.
44 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
45 def CMOV_FR32 : I<0, Pseudo,
46 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
48 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
49 def CMOV_FR64 : I<0, Pseudo,
50 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
52 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
56 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
57 "movss {$src, $dst|$dst, $src}", []>;
58 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
59 "movss {$src, $dst|$dst, $src}",
60 [(set FR32:$dst, (loadf32 addr:$src))]>;
61 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
62 "movsd {$src, $dst|$dst, $src}", []>;
63 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
64 "movsd {$src, $dst|$dst, $src}",
65 [(set FR64:$dst, (loadf64 addr:$src))]>;
67 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
68 "movss {$src, $dst|$dst, $src}",
69 [(store FR32:$src, addr:$dst)]>;
70 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
71 "movsd {$src, $dst|$dst, $src}",
72 [(store FR64:$src, addr:$dst)]>;
74 // Conversion instructions
75 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
76 "cvttss2si {$src, $dst|$dst, $src}",
77 [(set R32:$dst, (fp_to_sint FR32:$src))]>;
78 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
79 "cvttss2si {$src, $dst|$dst, $src}",
80 [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
81 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
82 "cvttsd2si {$src, $dst|$dst, $src}",
83 [(set R32:$dst, (fp_to_sint FR64:$src))]>;
84 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
85 "cvttsd2si {$src, $dst|$dst, $src}",
86 [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
87 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
88 "cvtsd2ss {$src, $dst|$dst, $src}",
89 [(set FR32:$dst, (fround FR64:$src))]>;
90 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
91 "cvtsd2ss {$src, $dst|$dst, $src}",
92 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
93 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
94 "cvtsi2ss {$src, $dst|$dst, $src}",
95 [(set FR32:$dst, (sint_to_fp R32:$src))]>;
96 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
97 "cvtsi2ss {$src, $dst|$dst, $src}",
98 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
99 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
100 "cvtsi2sd {$src, $dst|$dst, $src}",
101 [(set FR64:$dst, (sint_to_fp R32:$src))]>;
102 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
103 "cvtsi2sd {$src, $dst|$dst, $src}",
104 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
105 // SSE2 instructions with XS prefix
106 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
107 "cvtss2sd {$src, $dst|$dst, $src}",
108 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
110 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
111 "cvtss2sd {$src, $dst|$dst, $src}",
112 [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
115 // Arithmetic instructions
116 let isTwoAddress = 1 in {
117 let isCommutable = 1 in {
118 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
119 "addss {$src2, $dst|$dst, $src2}",
120 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
121 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
122 "addsd {$src2, $dst|$dst, $src2}",
123 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
124 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
125 "mulss {$src2, $dst|$dst, $src2}",
126 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
127 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
128 "mulsd {$src2, $dst|$dst, $src2}",
129 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
132 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
133 "addss {$src2, $dst|$dst, $src2}",
134 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
135 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
136 "addsd {$src2, $dst|$dst, $src2}",
137 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
138 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
139 "mulss {$src2, $dst|$dst, $src2}",
140 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
141 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
142 "mulsd {$src2, $dst|$dst, $src2}",
143 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
145 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
146 "divss {$src2, $dst|$dst, $src2}",
147 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
148 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
149 "divss {$src2, $dst|$dst, $src2}",
150 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
151 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
152 "divsd {$src2, $dst|$dst, $src2}",
153 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
154 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
155 "divsd {$src2, $dst|$dst, $src2}",
156 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
158 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
159 "subss {$src2, $dst|$dst, $src2}",
160 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
161 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
162 "subss {$src2, $dst|$dst, $src2}",
163 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
164 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
165 "subsd {$src2, $dst|$dst, $src2}",
166 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
167 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
168 "subsd {$src2, $dst|$dst, $src2}",
169 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
172 def SQRTSSrr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
173 "sqrtss {$src, $dst|$dst, $src}",
174 [(set FR32:$dst, (fsqrt FR32:$src))]>;
175 def SQRTSSrm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
176 "sqrtss {$src, $dst|$dst, $src}",
177 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
178 def SQRTSDrr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
179 "sqrtsd {$src, $dst|$dst, $src}",
180 [(set FR64:$dst, (fsqrt FR64:$src))]>;
181 def SQRTSDrm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
182 "sqrtsd {$src, $dst|$dst, $src}",
183 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
185 def RSQRTSSrr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
186 "rsqrtss {$src, $dst|$dst, $src}", []>;
187 def RSQRTSSrm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
188 "rsqrtss {$src, $dst|$dst, $src}", []>;
189 def RCPSSrr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
190 "rcpss {$src, $dst|$dst, $src}", []>;
191 def RCPSSrm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
192 "rcpss {$src, $dst|$dst, $src}", []>;
194 def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src),
195 "maxss {$src, $dst|$dst, $src}", []>;
196 def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
197 "maxss {$src, $dst|$dst, $src}", []>;
198 def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR64:$src),
199 "maxsd {$src, $dst|$dst, $src}", []>;
200 def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
201 "maxsd {$src, $dst|$dst, $src}", []>;
202 def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src),
203 "minss {$src, $dst|$dst, $src}", []>;
204 def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
205 "minss {$src, $dst|$dst, $src}", []>;
206 def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR64:$src),
207 "minsd {$src, $dst|$dst, $src}", []>;
208 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
209 "minsd {$src, $dst|$dst, $src}", []>;
211 // Comparison instructions
212 let isTwoAddress = 1 in {
213 def CMPSSrr : SSI<0xC2, MRMSrcReg,
214 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
215 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
216 def CMPSSrm : SSI<0xC2, MRMSrcMem,
217 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
218 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
219 def CMPSDrr : SDI<0xC2, MRMSrcReg,
220 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
221 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
222 def CMPSDrm : SDI<0xC2, MRMSrcMem,
223 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
224 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
227 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
228 "ucomiss {$src2, $src1|$src1, $src2}",
229 [(X86cmp FR32:$src1, FR32:$src2)]>;
230 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
231 "ucomiss {$src2, $src1|$src1, $src2}",
232 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
233 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
234 "ucomisd {$src2, $src1|$src1, $src2}",
235 [(X86cmp FR64:$src1, FR64:$src2)]>;
236 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
237 "ucomisd {$src2, $src1|$src1, $src2}",
238 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
240 // Aliases of packed instructions for scalar use. These all have names that
243 // Alias instructions that map fld0 to pxor for sse.
244 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
245 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
246 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
247 Requires<[HasSSE1]>, TB, OpSize;
248 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
249 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
250 Requires<[HasSSE2]>, TB, OpSize;
252 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
253 // Upper bits are disregarded.
254 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
255 "movaps {$src, $dst|$dst, $src}", []>;
256 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
257 "movapd {$src, $dst|$dst, $src}", []>;
259 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
260 // Upper bits are disregarded.
261 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
262 "movaps {$src, $dst|$dst, $src}",
263 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
264 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
265 "movapd {$src, $dst|$dst, $src}",
266 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
268 // Alias bitwise logical operations using SSE logical ops on packed FP values.
269 let isTwoAddress = 1 in {
270 let isCommutable = 1 in {
271 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
272 "andps {$src2, $dst|$dst, $src2}",
273 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
274 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
275 "andpd {$src2, $dst|$dst, $src2}",
276 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
277 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
278 "orps {$src2, $dst|$dst, $src2}", []>;
279 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
280 "orpd {$src2, $dst|$dst, $src2}", []>;
281 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
282 "xorps {$src2, $dst|$dst, $src2}",
283 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
284 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
285 "xorpd {$src2, $dst|$dst, $src2}",
286 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
288 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
289 "andps {$src2, $dst|$dst, $src2}",
290 [(set FR32:$dst, (X86fand FR32:$src1,
291 (X86loadpf32 addr:$src2)))]>;
292 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
293 "andpd {$src2, $dst|$dst, $src2}",
294 [(set FR64:$dst, (X86fand FR64:$src1,
295 (X86loadpf64 addr:$src2)))]>;
296 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
297 "orps {$src2, $dst|$dst, $src2}", []>;
298 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
299 "orpd {$src2, $dst|$dst, $src2}", []>;
300 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
301 "xorps {$src2, $dst|$dst, $src2}",
302 [(set FR32:$dst, (X86fxor FR32:$src1,
303 (X86loadpf32 addr:$src2)))]>;
304 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
305 "xorpd {$src2, $dst|$dst, $src2}",
306 [(set FR64:$dst, (X86fxor FR64:$src1,
307 (X86loadpf64 addr:$src2)))]>;
309 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
310 "andnps {$src2, $dst|$dst, $src2}", []>;
311 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
312 "andnps {$src2, $dst|$dst, $src2}", []>;
313 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
314 "andnpd {$src2, $dst|$dst, $src2}", []>;
315 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
316 "andnpd {$src2, $dst|$dst, $src2}", []>;
319 //===----------------------------------------------------------------------===//
320 // SSE packed FP Instructions
321 //===----------------------------------------------------------------------===//
324 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
325 "movaps {$src, $dst|$dst, $src}", []>;
326 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
327 "movaps {$src, $dst|$dst, $src}",
328 [(set V4F32:$dst, (X86loadv4f32 addr:$src))]>;
329 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
330 "movapd {$src, $dst|$dst, $src}", []>;
331 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
332 "movapd {$src, $dst|$dst, $src}",
333 [(set V2F64:$dst, (X86loadv2f64 addr:$src))]>;
335 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
336 "movaps {$src, $dst|$dst, $src}",
337 [(store V4F32:$src, addr:$dst)]>;
338 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
339 "movapd {$src, $dst|$dst, $src}",
340 [(store V2F64:$src, addr:$dst)]>;
342 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
343 "movups {$src, $dst|$dst, $src}", []>;
344 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
345 "movups {$src, $dst|$dst, $src}", []>;
346 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
347 "movups {$src, $dst|$dst, $src}", []>;
348 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
349 "movupd {$src, $dst|$dst, $src}", []>;
350 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
351 "movupd {$src, $dst|$dst, $src}", []>;
352 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
353 "movupd {$src, $dst|$dst, $src}", []>;
355 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops V4F32:$dst, f64mem:$src),
356 "movlps {$src, $dst|$dst, $src}", []>;
357 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, V4F32:$src),
358 "movlps {$src, $dst|$dst, $src}", []>;
359 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops V2F64:$dst, f64mem:$src),
360 "movlpd {$src, $dst|$dst, $src}", []>;
361 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, V2F64:$src),
362 "movlpd {$src, $dst|$dst, $src}", []>;
364 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops V4F32:$dst, f64mem:$src),
365 "movhps {$src, $dst|$dst, $src}", []>;
366 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, V4F32:$src),
367 "movhps {$src, $dst|$dst, $src}", []>;
368 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops V2F64:$dst, f64mem:$src),
369 "movhpd {$src, $dst|$dst, $src}", []>;
370 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, V2F64:$src),
371 "movhpd {$src, $dst|$dst, $src}", []>;
373 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
374 "movlhps {$src, $dst|$dst, $src}", []>;
375 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
376 "movlhps {$src, $dst|$dst, $src}", []>;
378 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, V4F32:$src),
379 "movmskps {$src, $dst|$dst, $src}", []>;
380 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, V2F64:$src),
381 "movmskpd {$src, $dst|$dst, $src}", []>;
383 // Conversion instructions
384 def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops V4F32:$dst, V2I32:$src),
385 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
386 def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops V4F32:$dst, i64mem:$src),
387 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
388 def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops V2F64:$dst, V2I32:$src),
389 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
390 def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops V2F64:$dst, i64mem:$src),
391 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
393 // SSE2 instructions without OpSize prefix
394 def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops V4F32:$dst, V4I32:$src),
395 "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB,
397 def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops V4F32:$dst, i128mem:$src),
398 "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB,
401 // SSE2 instructions with XS prefix
402 def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops V2F64:$dst, V2I32:$src),
403 "cvtdq2pd {$src, $dst|$dst, $src}", []>,
404 XS, Requires<[HasSSE2]>;
405 def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops V4F32:$dst, i64mem:$src),
406 "cvtdq2pd {$src, $dst|$dst, $src}", []>,
407 XS, Requires<[HasSSE2]>;
409 def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops V2I32:$dst, V4F32:$src),
410 "cvtps2pi {$src, $dst|$dst, $src}", []>;
411 def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops V2I32:$dst, f64mem:$src),
412 "cvtps2pi {$src, $dst|$dst, $src}", []>;
413 def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops V2I32:$dst, V2F64:$src),
414 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
415 def CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (ops V2I32:$dst, f128mem:$src),
416 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
418 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops V4I32:$dst, V4F32:$src),
419 "cvtps2dq {$src, $dst|$dst, $src}", []>;
420 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops V4I32:$dst, f128mem:$src),
421 "cvtps2dq {$src, $dst|$dst, $src}", []>;
422 // SSE2 packed instructions with XD prefix
423 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (ops V4I32:$dst, V2F64:$src),
424 "cvtpd2dq {$src, $dst|$dst, $src}", []>;
425 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (ops V4I32:$dst, f128mem:$src),
426 "cvtpd2dq {$src, $dst|$dst, $src}", []>;
428 // SSE2 instructions without OpSize prefix
429 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops V4I32:$dst, V2F64:$src),
430 "cvtps2pd {$src, $dst|$dst, $src}", []>, TB,
432 def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops V4I32:$dst, f64mem:$src),
433 "cvtps2pd {$src, $dst|$dst, $src}", []>, TB,
436 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops V4F32:$dst, V2F64:$src),
437 "cvtpd2ps {$src, $dst|$dst, $src}", []>;
438 def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops V4F32:$dst, f128mem:$src),
439 "cvtpd2ps {$src, $dst|$dst, $src}", []>;
442 let isTwoAddress = 1 in {
443 let isCommutable = 1 in {
444 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
445 "addps {$src2, $dst|$dst, $src2}",
446 [(set V4F32:$dst, (fadd V4F32:$src1, V4F32:$src2))]>;
447 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
448 "addpd {$src2, $dst|$dst, $src2}",
449 [(set V2F64:$dst, (fadd V2F64:$src1, V2F64:$src2))]>;
450 def MULPSrr : PSI<0x59, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
451 "mulps {$src2, $dst|$dst, $src2}",
452 [(set V4F32:$dst, (fmul V4F32:$src1, V4F32:$src2))]>;
453 def MULPDrr : PDI<0x59, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
454 "mulpd {$src2, $dst|$dst, $src2}",
455 [(set V2F64:$dst, (fmul V2F64:$src1, V2F64:$src2))]>;
458 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
459 "addps {$src2, $dst|$dst, $src2}",
460 [(set V4F32:$dst, (fadd V4F32:$src1,
461 (X86loadv4f32 addr:$src2)))]>;
462 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
463 "addpd {$src2, $dst|$dst, $src2}",
464 [(set V2F64:$dst, (fadd V2F64:$src1,
465 (X86loadv2f64 addr:$src2)))]>;
466 def MULPSrm : PSI<0x59, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
467 "mulps {$src2, $dst|$dst, $src2}",
468 [(set V4F32:$dst, (fmul V4F32:$src1,
469 (X86loadv4f32 addr:$src2)))]>;
470 def MULPDrm : PDI<0x59, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
471 "mulpd {$src2, $dst|$dst, $src2}",
472 [(set V2F64:$dst, (fmul V2F64:$src1,
473 (X86loadv2f64 addr:$src2)))]>;
475 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
476 "divps {$src2, $dst|$dst, $src2}",
477 [(set V4F32:$dst, (fdiv V4F32:$src1, V4F32:$src2))]>;
478 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
479 "divps {$src2, $dst|$dst, $src2}",
480 [(set V4F32:$dst, (fdiv V4F32:$src1,
481 (X86loadv4f32 addr:$src2)))]>;
482 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
483 "divpd {$src2, $dst|$dst, $src2}",
484 [(set V2F64:$dst, (fdiv V2F64:$src1, V2F64:$src2))]>;
485 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
486 "divpd {$src2, $dst|$dst, $src2}",
487 [(set V2F64:$dst, (fdiv V2F64:$src1,
488 (X86loadv2f64 addr:$src2)))]>;
490 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
491 "subps {$src2, $dst|$dst, $src2}",
492 [(set V4F32:$dst, (fsub V4F32:$src1, V4F32:$src2))]>;
493 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
494 "subps {$src2, $dst|$dst, $src2}",
495 [(set V4F32:$dst, (fsub V4F32:$src1,
496 (X86loadv4f32 addr:$src2)))]>;
497 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
498 "subpd {$src2, $dst|$dst, $src2}",
499 [(set V2F64:$dst, (fsub V2F64:$src1, V2F64:$src2))]>;
500 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
501 "subpd {$src2, $dst|$dst, $src2}",
502 [(set V2F64:$dst, (fsub V2F64:$src1,
503 (X86loadv2f64 addr:$src2)))]>;
506 def SQRTPSrr : PSI<0x51, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
507 "sqrtps {$src, $dst|$dst, $src}",
508 [(set V4F32:$dst, (fsqrt V4F32:$src))]>;
509 def SQRTPSrm : PSI<0x51, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
510 "sqrtps {$src, $dst|$dst, $src}",
511 [(set V4F32:$dst, (fsqrt (X86loadv4f32 addr:$src)))]>;
512 def SQRTPDrr : PDI<0x51, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
513 "sqrtpd {$src, $dst|$dst, $src}",
514 [(set V2F64:$dst, (fsqrt V2F64:$src))]>;
515 def SQRTPDrm : PDI<0x51, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
516 "sqrtpd {$src, $dst|$dst, $src}",
517 [(set V2F64:$dst, (fsqrt (X86loadv2f64 addr:$src)))]>;
519 def RSQRTPSrr : PSI<0x52, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
520 "rsqrtps {$src, $dst|$dst, $src}", []>;
521 def RSQRTPSrm : PSI<0x52, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
522 "rsqrtps {$src, $dst|$dst, $src}", []>;
523 def RCPPSrr : PSI<0x53, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
524 "rcpps {$src, $dst|$dst, $src}", []>;
525 def RCPPSrm : PSI<0x53, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
526 "rcpps {$src, $dst|$dst, $src}", []>;
528 def MAXPSrr : PSI<0x5F, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
529 "maxps {$src, $dst|$dst, $src}", []>;
530 def MAXPSrm : PSI<0x5F, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
531 "maxps {$src, $dst|$dst, $src}", []>;
532 def MAXPDrr : PDI<0x5F, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
533 "maxpd {$src, $dst|$dst, $src}", []>;
534 def MAXPDrm : PDI<0x5F, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
535 "maxpd {$src, $dst|$dst, $src}", []>;
536 def MINPSrr : PSI<0x5D, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
537 "minps {$src, $dst|$dst, $src}", []>;
538 def MINPSrm : PSI<0x5D, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
539 "minps {$src, $dst|$dst, $src}", []>;
540 def MINPDrr : PDI<0x5D, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
541 "minpd {$src, $dst|$dst, $src}", []>;
542 def MINPDrm : PDI<0x5D, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
543 "minpd {$src, $dst|$dst, $src}", []>;
546 let isTwoAddress = 1 in {
547 let isCommutable = 1 in {
548 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
549 "andps {$src2, $dst|$dst, $src2}",
550 [(set V4F32:$dst, (X86fand V4F32:$src1, V4F32:$src2))]>;
551 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
552 "andpd {$src2, $dst|$dst, $src2}",
553 [(set V2F64:$dst, (X86fand V2F64:$src1, V2F64:$src2))]>;
554 def ORPSrr : PSI<0x56, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
555 "orps {$src2, $dst|$dst, $src2}", []>;
556 def ORPDrr : PDI<0x56, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
557 "orpd {$src2, $dst|$dst, $src2}", []>;
558 def XORPSrr : PSI<0x57, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
559 "xorps {$src2, $dst|$dst, $src2}",
560 [(set V4F32:$dst, (X86fxor V4F32:$src1, V4F32:$src2))]>;
561 def XORPDrr : PDI<0x57, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
562 "xorpd {$src2, $dst|$dst, $src2}",
563 [(set V2F64:$dst, (X86fxor V2F64:$src1, V2F64:$src2))]>;
565 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
566 "andps {$src2, $dst|$dst, $src2}",
567 [(set V4F32:$dst, (X86fand V4F32:$src1,
568 (X86loadv4f32 addr:$src2)))]>;
569 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
570 "andpd {$src2, $dst|$dst, $src2}",
571 [(set V2F64:$dst, (X86fand V2F64:$src1,
572 (X86loadv2f64 addr:$src2)))]>;
573 def ORPSrm : PSI<0x56, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
574 "orps {$src2, $dst|$dst, $src2}", []>;
575 def ORPDrm : PDI<0x56, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
576 "orpd {$src2, $dst|$dst, $src2}", []>;
577 def XORPSrm : PSI<0x57, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
578 "xorps {$src2, $dst|$dst, $src2}",
579 [(set V4F32:$dst, (X86fxor V4F32:$src1,
580 (X86loadv4f32 addr:$src2)))]>;
581 def XORPDrm : PDI<0x57, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
582 "xorpd {$src2, $dst|$dst, $src2}",
583 [(set V2F64:$dst, (X86fxor V2F64:$src1,
584 (X86loadv2f64 addr:$src2)))]>;
585 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
586 "andnps {$src2, $dst|$dst, $src2}", []>;
587 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
588 "andnps {$src2, $dst|$dst, $src2}", []>;
589 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
590 "andnpd {$src2, $dst|$dst, $src2}", []>;
591 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
592 "andnpd {$src2, $dst|$dst, $src2}", []>;
595 let isTwoAddress = 1 in {
596 def CMPPSrr : PSI<0xC2, MRMSrcReg,
597 (ops V4F32:$dst, V4F32:$src1, V4F32:$src, SSECC:$cc),
598 "cmp${cc}ps {$src, $dst|$dst, $src}", []>;
599 def CMPPSrm : PSI<0xC2, MRMSrcMem,
600 (ops V4F32:$dst, V4F32:$src1, f128mem:$src, SSECC:$cc),
601 "cmp${cc}ps {$src, $dst|$dst, $src}", []>;
602 def CMPPDrr : PDI<0xC2, MRMSrcReg,
603 (ops V2F64:$dst, V2F64:$src1, V2F64:$src, SSECC:$cc),
604 "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
605 def CMPPDrm : PDI<0xC2, MRMSrcMem,
606 (ops V2F64:$dst, V2F64:$src1, f128mem:$src, SSECC:$cc),
607 "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
610 // Shuffle and unpack instructions
611 def SHUFPSrr : PSI<0xC6, MRMSrcReg,
612 (ops V4F32:$dst, V4F32:$src1, V4F32:$src2, i8imm:$src3),
613 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
614 def SHUFPSrm : PSI<0xC6, MRMSrcMem,
615 (ops V4F32:$dst, V4F32:$src1, f128mem:$src2, i8imm:$src3),
616 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
617 def SHUFPDrr : PDI<0xC6, MRMSrcReg,
618 (ops V2F64:$dst, V2F64:$src1, V2F64:$src2, i8imm:$src3),
619 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
620 def SHUFPDrm : PDI<0xC6, MRMSrcMem,
621 (ops V2F64:$dst, V2F64:$src1, f128mem:$src2, i8imm:$src3),
622 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
624 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
625 (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
626 "unpckhps {$src2, $dst|$dst, $src2}", []>;
627 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
628 (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
629 "unpckhps {$src2, $dst|$dst, $src2}", []>;
630 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
631 (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
632 "unpckhpd {$src2, $dst|$dst, $src2}", []>;
633 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
634 (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
635 "unpckhpd {$src2, $dst|$dst, $src2}", []>;
636 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
637 (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
638 "unpcklps {$src2, $dst|$dst, $src2}", []>;
639 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
640 (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
641 "unpcklps {$src2, $dst|$dst, $src2}", []>;
642 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
643 (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
644 "unpcklpd {$src2, $dst|$dst, $src2}", []>;
645 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
646 (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
647 "unpcklpd {$src2, $dst|$dst, $src2}", []>;
649 //===----------------------------------------------------------------------===//
650 // SSE integer instructions
651 //===----------------------------------------------------------------------===//
654 def MOVD128rr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
655 "movd {$src, $dst|$dst, $src}", []>;
656 def MOVD128rm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
657 "movd {$src, $dst|$dst, $src}", []>;
658 def MOVD128mr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
659 "movd {$src, $dst|$dst, $src}", []>;
661 // SSE2 instructions with XS prefix
662 def MOVQ128rr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
663 "movq {$src, $dst|$dst, $src}", []>, XS,
665 def MOVQ128rm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
666 "movq {$src, $dst|$dst, $src}", []>, XS,
669 def MOVQ128mr : PDI<0xD6, MRMSrcMem, (ops i64mem:$dst, VR128:$src),
670 "movq {$src, $dst|$dst, $src}", []>;