1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 bit rr_hasSideEffects = 0> {
85 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
86 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
88 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
89 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
91 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
93 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
94 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
98 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
99 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
100 string asm, string SSEVer, string FPSizeStr,
101 X86MemOperand x86memop, PatFrag mem_frag,
102 Domain d, bit Is2Addr = 1> {
103 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
105 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
106 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
107 [(set RC:$dst, (!cast<Intrinsic>(
108 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
109 RC:$src1, RC:$src2))], d>;
110 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
112 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
113 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
114 [(set RC:$dst, (!cast<Intrinsic>(
115 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
116 RC:$src1, (mem_frag addr:$src2)))], d>;
119 //===----------------------------------------------------------------------===//
120 // Non-instruction patterns
121 //===----------------------------------------------------------------------===//
123 // A vector extract of the first f32/f64 position is a subregister copy
124 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
125 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
126 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
127 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
129 // A 128-bit subvector extract from the first 256-bit vector position
130 // is a subregister copy that needs no instruction.
131 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
132 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
133 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
134 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
136 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
137 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
138 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
139 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
141 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
142 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
143 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
144 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
146 // A 128-bit subvector insert to the first 256-bit vector position
147 // is a subregister copy that needs no instruction.
148 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
149 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
150 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
151 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
152 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
153 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
154 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
155 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
156 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
157 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
158 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
159 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
161 // Implicitly promote a 32-bit scalar to a vector.
162 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
163 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
164 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
165 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
166 // Implicitly promote a 64-bit scalar to a vector.
167 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
168 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
169 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
170 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
172 // Bitcasts between 128-bit vector types. Return the original type since
173 // no instruction is needed for the conversion
174 let Predicates = [HasXMMInt] in {
175 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
204 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
207 // Bitcasts between 256-bit vector types. Return the original type since
208 // no instruction is needed for the conversion
209 let Predicates = [HasAVX] in {
210 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
239 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
242 // Alias instructions that map fld0 to pxor for sse.
243 // FIXME: Set encoding to pseudo!
244 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
245 canFoldAsLoad = 1 in {
246 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
247 [(set FR32:$dst, fp32imm0)]>,
248 Requires<[HasSSE1]>, TB, OpSize;
249 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
250 [(set FR64:$dst, fpimm0)]>,
251 Requires<[HasSSE2]>, TB, OpSize;
252 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
253 [(set FR32:$dst, fp32imm0)]>,
254 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
255 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
256 [(set FR64:$dst, fpimm0)]>,
257 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
260 //===----------------------------------------------------------------------===//
261 // AVX & SSE - Zero/One Vectors
262 //===----------------------------------------------------------------------===//
264 // Alias instruction that maps zero vector to pxor / xorp* for sse.
265 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
266 // swizzled by ExecutionDepsFix to pxor.
267 // We set canFoldAsLoad because this can be converted to a constant-pool
268 // load of an all-zeros value if folding it would be beneficial.
269 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
270 isPseudo = 1, neverHasSideEffects = 1 in {
271 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
274 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
275 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
276 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
277 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
278 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
279 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
282 // The same as done above but for AVX. The 256-bit ISA does not support PI,
283 // and doesn't need it because on sandy bridge the register is set to zero
284 // at the rename stage without using any execution unit, so SET0PSY
285 // and SET0PDY can be used for vector int instructions without penalty
286 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
287 // JIT implementatioan, it does not expand the instructions below like
288 // X86MCInstLower does.
289 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
290 isCodeGenOnly = 1, Predicates = [HasAVX] in {
291 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
292 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
293 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
294 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
298 // AVX has no support for 256-bit integer instructions, but since the 128-bit
299 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
300 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
301 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
302 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
304 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
305 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
306 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
308 // We set canFoldAsLoad because this can be converted to a constant-pool
309 // load of an all-ones value if folding it would be beneficial.
310 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
311 // JIT implementation, it does not expand the instructions below like
312 // X86MCInstLower does.
313 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
314 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
315 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
316 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
317 let Predicates = [HasAVX] in
318 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
319 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
320 let Predicates = [HasAVX2] in
321 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
322 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
326 //===----------------------------------------------------------------------===//
327 // SSE 1 & 2 - Move FP Scalar Instructions
329 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
330 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
331 // is used instead. Register-to-register movss/movsd is not modeled as an
332 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
333 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
334 //===----------------------------------------------------------------------===//
336 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
337 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
338 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
340 // Loading from memory automatically zeroing upper bits.
341 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
342 PatFrag mem_pat, string OpcodeStr> :
343 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
344 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
345 [(set RC:$dst, (mem_pat addr:$src))]>;
348 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
349 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
351 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
352 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
355 // For the disassembler
356 let isCodeGenOnly = 1 in {
357 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
358 (ins VR128:$src1, FR32:$src2),
359 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
361 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
362 (ins VR128:$src1, FR64:$src2),
363 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
367 let canFoldAsLoad = 1, isReMaterializable = 1 in {
368 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
370 let AddedComplexity = 20 in
371 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
375 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
376 "movss\t{$src, $dst|$dst, $src}",
377 [(store FR32:$src, addr:$dst)]>, XS, VEX, VEX_LIG;
378 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
379 "movsd\t{$src, $dst|$dst, $src}",
380 [(store FR64:$src, addr:$dst)]>, XD, VEX, VEX_LIG;
383 let Constraints = "$src1 = $dst" in {
384 def MOVSSrr : sse12_move_rr<FR32, v4f32,
385 "movss\t{$src2, $dst|$dst, $src2}">, XS;
386 def MOVSDrr : sse12_move_rr<FR64, v2f64,
387 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
389 // For the disassembler
390 let isCodeGenOnly = 1 in {
391 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
392 (ins VR128:$src1, FR32:$src2),
393 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
394 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
395 (ins VR128:$src1, FR64:$src2),
396 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
400 let canFoldAsLoad = 1, isReMaterializable = 1 in {
401 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
403 let AddedComplexity = 20 in
404 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
407 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
408 "movss\t{$src, $dst|$dst, $src}",
409 [(store FR32:$src, addr:$dst)]>;
410 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
411 "movsd\t{$src, $dst|$dst, $src}",
412 [(store FR64:$src, addr:$dst)]>;
415 let Predicates = [HasSSE1] in {
416 let AddedComplexity = 15 in {
417 // Extract the low 32-bit value from one vector and insert it into another.
418 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
419 (MOVSSrr (v4f32 VR128:$src1),
420 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
421 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
422 (MOVSSrr (v4i32 VR128:$src1),
423 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
425 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
426 // MOVSS to the lower bits.
427 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
428 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
429 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
430 (MOVSSrr (v4f32 (V_SET0)),
431 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
432 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
433 (MOVSSrr (v4i32 (V_SET0)),
434 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
437 let AddedComplexity = 20 in {
438 // MOVSSrm zeros the high parts of the register; represent this
439 // with SUBREG_TO_REG.
440 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
441 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
442 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
443 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
444 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
445 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
448 // Extract and store.
449 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
452 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
454 // Shuffle with MOVSS
455 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
456 (MOVSSrr VR128:$src1, FR32:$src2)>;
457 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
458 (MOVSSrr (v4i32 VR128:$src1),
459 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
460 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
461 (MOVSSrr (v4f32 VR128:$src1),
462 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
465 let Predicates = [HasSSE2] in {
466 let AddedComplexity = 15 in {
467 // Extract the low 64-bit value from one vector and insert it into another.
468 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
469 (MOVSDrr (v2f64 VR128:$src1),
470 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
471 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
472 (MOVSDrr (v2i64 VR128:$src1),
473 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
475 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
476 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
477 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
478 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
479 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
481 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
482 // MOVSD to the lower bits.
483 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
484 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
487 let AddedComplexity = 20 in {
488 // MOVSDrm zeros the high parts of the register; represent this
489 // with SUBREG_TO_REG.
490 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
491 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
492 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
493 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
494 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
495 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
496 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
497 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
498 def : Pat<(v2f64 (X86vzload addr:$src)),
499 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
502 // Extract and store.
503 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
506 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
508 // Shuffle with MOVSD
509 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
510 (MOVSDrr VR128:$src1, FR64:$src2)>;
511 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
512 (MOVSDrr (v2i64 VR128:$src1),
513 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
514 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
515 (MOVSDrr (v2f64 VR128:$src1),
516 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
517 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
518 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
519 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
520 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
522 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
523 // is during lowering, where it's not possible to recognize the fold cause
524 // it has two uses through a bitcast. One use disappears at isel time and the
525 // fold opportunity reappears.
526 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
527 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
528 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
529 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
530 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
531 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
532 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
533 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
536 let Predicates = [HasAVX] in {
537 let AddedComplexity = 15 in {
538 // Extract the low 32-bit value from one vector and insert it into another.
539 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
540 (VMOVSSrr (v4f32 VR128:$src1),
541 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
542 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
543 (VMOVSSrr (v4i32 VR128:$src1),
544 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
546 // Extract the low 64-bit value from one vector and insert it into another.
547 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
548 (VMOVSDrr (v2f64 VR128:$src1),
549 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
550 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
551 (VMOVSDrr (v2i64 VR128:$src1),
552 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
554 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
555 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
556 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
557 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
558 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
560 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
561 // MOVS{S,D} to the lower bits.
562 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
563 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
564 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
567 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
568 (VMOVSSrr (v4i32 (V_SET0)),
569 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
570 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
571 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
574 let AddedComplexity = 20 in {
575 // MOVSSrm zeros the high parts of the register; represent this
576 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
577 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
578 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
579 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
580 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
581 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
582 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
584 // MOVSDrm zeros the high parts of the register; represent this
585 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
586 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
587 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
588 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
589 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
590 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
591 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
592 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
593 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
594 def : Pat<(v2f64 (X86vzload addr:$src)),
595 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
597 // Represent the same patterns above but in the form they appear for
599 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
600 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
601 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
602 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
603 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
604 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
606 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
607 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
608 (SUBREG_TO_REG (i32 0),
609 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
611 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
612 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
613 (SUBREG_TO_REG (i64 0),
614 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
617 // Extract and store.
618 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
621 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
622 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
625 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
627 // Shuffle with VMOVSS
628 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
629 (VMOVSSrr VR128:$src1, FR32:$src2)>;
630 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
631 (VMOVSSrr (v4i32 VR128:$src1),
632 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
633 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
634 (VMOVSSrr (v4f32 VR128:$src1),
635 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
637 // Shuffle with VMOVSD
638 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
639 (VMOVSDrr VR128:$src1, FR64:$src2)>;
640 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
641 (VMOVSDrr (v2i64 VR128:$src1),
642 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
643 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
644 (VMOVSDrr (v2f64 VR128:$src1),
645 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
646 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
647 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
649 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
650 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
653 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
654 // is during lowering, where it's not possible to recognize the fold cause
655 // it has two uses through a bitcast. One use disappears at isel time and the
656 // fold opportunity reappears.
657 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
658 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
660 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
661 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
663 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
664 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
668 //===----------------------------------------------------------------------===//
669 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
670 //===----------------------------------------------------------------------===//
672 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
673 X86MemOperand x86memop, PatFrag ld_frag,
674 string asm, Domain d,
675 bit IsReMaterializable = 1> {
676 let neverHasSideEffects = 1 in
677 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
678 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
679 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
680 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
681 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
682 [(set RC:$dst, (ld_frag addr:$src))], d>;
685 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
686 "movaps", SSEPackedSingle>, TB, VEX;
687 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
688 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
689 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
690 "movups", SSEPackedSingle>, TB, VEX;
691 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
692 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
694 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
695 "movaps", SSEPackedSingle>, TB, VEX;
696 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
697 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
698 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
699 "movups", SSEPackedSingle>, TB, VEX;
700 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
701 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
702 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
703 "movaps", SSEPackedSingle>, TB;
704 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
705 "movapd", SSEPackedDouble>, TB, OpSize;
706 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
707 "movups", SSEPackedSingle>, TB;
708 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
709 "movupd", SSEPackedDouble, 0>, TB, OpSize;
711 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
712 "movaps\t{$src, $dst|$dst, $src}",
713 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
714 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
715 "movapd\t{$src, $dst|$dst, $src}",
716 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
717 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
718 "movups\t{$src, $dst|$dst, $src}",
719 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
720 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
721 "movupd\t{$src, $dst|$dst, $src}",
722 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
723 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
724 "movaps\t{$src, $dst|$dst, $src}",
725 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
726 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
727 "movapd\t{$src, $dst|$dst, $src}",
728 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
729 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
730 "movups\t{$src, $dst|$dst, $src}",
731 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
732 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
733 "movupd\t{$src, $dst|$dst, $src}",
734 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
737 let isCodeGenOnly = 1 in {
738 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
740 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
741 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
743 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
744 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
746 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
747 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
749 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
750 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
752 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
753 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
755 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
756 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
758 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
759 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
761 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
764 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
765 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
766 (VMOVUPSYmr addr:$dst, VR256:$src)>;
768 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
769 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
770 (VMOVUPDYmr addr:$dst, VR256:$src)>;
772 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
773 "movaps\t{$src, $dst|$dst, $src}",
774 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
775 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
776 "movapd\t{$src, $dst|$dst, $src}",
777 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
778 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
779 "movups\t{$src, $dst|$dst, $src}",
780 [(store (v4f32 VR128:$src), addr:$dst)]>;
781 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
782 "movupd\t{$src, $dst|$dst, $src}",
783 [(store (v2f64 VR128:$src), addr:$dst)]>;
786 let isCodeGenOnly = 1 in {
787 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
788 "movaps\t{$src, $dst|$dst, $src}", []>;
789 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
790 "movapd\t{$src, $dst|$dst, $src}", []>;
791 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
792 "movups\t{$src, $dst|$dst, $src}", []>;
793 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
794 "movupd\t{$src, $dst|$dst, $src}", []>;
797 let Predicates = [HasAVX] in {
798 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
799 (VMOVUPSmr addr:$dst, VR128:$src)>;
800 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
801 (VMOVUPDmr addr:$dst, VR128:$src)>;
804 let Predicates = [HasSSE1] in
805 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
806 (MOVUPSmr addr:$dst, VR128:$src)>;
807 let Predicates = [HasSSE2] in
808 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
809 (MOVUPDmr addr:$dst, VR128:$src)>;
811 // Use movaps / movups for SSE integer load / store (one byte shorter).
812 // The instructions selected below are then converted to MOVDQA/MOVDQU
813 // during the SSE domain pass.
814 let Predicates = [HasSSE1] in {
815 def : Pat<(alignedloadv4i32 addr:$src),
816 (MOVAPSrm addr:$src)>;
817 def : Pat<(loadv4i32 addr:$src),
818 (MOVUPSrm addr:$src)>;
819 def : Pat<(alignedloadv2i64 addr:$src),
820 (MOVAPSrm addr:$src)>;
821 def : Pat<(loadv2i64 addr:$src),
822 (MOVUPSrm addr:$src)>;
824 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
825 (MOVAPSmr addr:$dst, VR128:$src)>;
826 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
827 (MOVAPSmr addr:$dst, VR128:$src)>;
828 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
829 (MOVAPSmr addr:$dst, VR128:$src)>;
830 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
831 (MOVAPSmr addr:$dst, VR128:$src)>;
832 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
833 (MOVUPSmr addr:$dst, VR128:$src)>;
834 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
835 (MOVUPSmr addr:$dst, VR128:$src)>;
836 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
837 (MOVUPSmr addr:$dst, VR128:$src)>;
838 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
839 (MOVUPSmr addr:$dst, VR128:$src)>;
842 // Use vmovaps/vmovups for AVX integer load/store.
843 let Predicates = [HasAVX] in {
844 // 128-bit load/store
845 def : Pat<(alignedloadv4i32 addr:$src),
846 (VMOVAPSrm addr:$src)>;
847 def : Pat<(loadv4i32 addr:$src),
848 (VMOVUPSrm addr:$src)>;
849 def : Pat<(alignedloadv2i64 addr:$src),
850 (VMOVAPSrm addr:$src)>;
851 def : Pat<(loadv2i64 addr:$src),
852 (VMOVUPSrm addr:$src)>;
854 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
855 (VMOVAPSmr addr:$dst, VR128:$src)>;
856 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
857 (VMOVAPSmr addr:$dst, VR128:$src)>;
858 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
859 (VMOVAPSmr addr:$dst, VR128:$src)>;
860 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
861 (VMOVAPSmr addr:$dst, VR128:$src)>;
862 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
863 (VMOVUPSmr addr:$dst, VR128:$src)>;
864 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
865 (VMOVUPSmr addr:$dst, VR128:$src)>;
866 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
867 (VMOVUPSmr addr:$dst, VR128:$src)>;
868 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
869 (VMOVUPSmr addr:$dst, VR128:$src)>;
871 // 256-bit load/store
872 def : Pat<(alignedloadv4i64 addr:$src),
873 (VMOVAPSYrm addr:$src)>;
874 def : Pat<(loadv4i64 addr:$src),
875 (VMOVUPSYrm addr:$src)>;
876 def : Pat<(alignedloadv8i32 addr:$src),
877 (VMOVAPSYrm addr:$src)>;
878 def : Pat<(loadv8i32 addr:$src),
879 (VMOVUPSYrm addr:$src)>;
880 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
881 (VMOVAPSYmr addr:$dst, VR256:$src)>;
882 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
883 (VMOVAPSYmr addr:$dst, VR256:$src)>;
884 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
885 (VMOVAPSYmr addr:$dst, VR256:$src)>;
886 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
887 (VMOVAPSYmr addr:$dst, VR256:$src)>;
888 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
889 (VMOVUPSYmr addr:$dst, VR256:$src)>;
890 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
891 (VMOVUPSYmr addr:$dst, VR256:$src)>;
892 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
893 (VMOVUPSYmr addr:$dst, VR256:$src)>;
894 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
895 (VMOVUPSYmr addr:$dst, VR256:$src)>;
898 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
899 // bits are disregarded. FIXME: Set encoding to pseudo!
900 let neverHasSideEffects = 1 in {
901 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
902 "movaps\t{$src, $dst|$dst, $src}", []>;
903 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
904 "movapd\t{$src, $dst|$dst, $src}", []>;
905 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
906 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
907 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
908 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
911 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
912 // bits are disregarded. FIXME: Set encoding to pseudo!
913 let canFoldAsLoad = 1, isReMaterializable = 1 in {
914 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
915 "movaps\t{$src, $dst|$dst, $src}",
916 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
917 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
918 "movapd\t{$src, $dst|$dst, $src}",
919 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
920 let isCodeGenOnly = 1 in {
921 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
922 "movaps\t{$src, $dst|$dst, $src}",
923 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
924 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
925 "movapd\t{$src, $dst|$dst, $src}",
926 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
930 //===----------------------------------------------------------------------===//
931 // SSE 1 & 2 - Move Low packed FP Instructions
932 //===----------------------------------------------------------------------===//
934 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
935 PatFrag mov_frag, string base_opc,
937 def PSrm : PI<opc, MRMSrcMem,
938 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
939 !strconcat(base_opc, "s", asm_opr),
942 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
943 SSEPackedSingle>, TB;
945 def PDrm : PI<opc, MRMSrcMem,
946 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
947 !strconcat(base_opc, "d", asm_opr),
948 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
949 (scalar_to_vector (loadf64 addr:$src2)))))],
950 SSEPackedDouble>, TB, OpSize;
953 let AddedComplexity = 20 in {
954 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
955 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
957 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
958 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
959 "\t{$src2, $dst|$dst, $src2}">;
962 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
963 "movlps\t{$src, $dst|$dst, $src}",
964 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
965 (iPTR 0))), addr:$dst)]>, VEX;
966 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
967 "movlpd\t{$src, $dst|$dst, $src}",
968 [(store (f64 (vector_extract (v2f64 VR128:$src),
969 (iPTR 0))), addr:$dst)]>, VEX;
970 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
971 "movlps\t{$src, $dst|$dst, $src}",
972 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
973 (iPTR 0))), addr:$dst)]>;
974 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
975 "movlpd\t{$src, $dst|$dst, $src}",
976 [(store (f64 (vector_extract (v2f64 VR128:$src),
977 (iPTR 0))), addr:$dst)]>;
979 let Predicates = [HasAVX] in {
980 let AddedComplexity = 20 in {
981 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
982 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
983 (VMOVLPSrm VR128:$src1, addr:$src2)>;
984 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
985 (VMOVLPSrm VR128:$src1, addr:$src2)>;
986 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
987 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
988 (VMOVLPDrm VR128:$src1, addr:$src2)>;
989 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
990 (VMOVLPDrm VR128:$src1, addr:$src2)>;
993 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
994 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
995 (VMOVLPSmr addr:$src1, VR128:$src2)>;
996 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
997 VR128:$src2)), addr:$src1),
998 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1000 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1001 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1002 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1003 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1004 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1006 // Shuffle with VMOVLPS
1007 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1008 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1009 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1010 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1011 def : Pat<(X86Movlps VR128:$src1,
1012 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1013 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1015 // Shuffle with VMOVLPD
1016 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1017 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1018 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1019 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1020 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1021 (scalar_to_vector (loadf64 addr:$src2)))),
1022 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1025 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1027 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1028 def : Pat<(store (v4i32 (X86Movlps
1029 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1030 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1031 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1033 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1034 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1036 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1039 let Predicates = [HasSSE1] in {
1040 let AddedComplexity = 20 in {
1041 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1042 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1043 (MOVLPSrm VR128:$src1, addr:$src2)>;
1044 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1045 (MOVLPSrm VR128:$src1, addr:$src2)>;
1048 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1049 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1050 (iPTR 0))), addr:$src1),
1051 (MOVLPSmr addr:$src1, VR128:$src2)>;
1052 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1053 (MOVLPSmr addr:$src1, VR128:$src2)>;
1054 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1055 VR128:$src2)), addr:$src1),
1056 (MOVLPSmr addr:$src1, VR128:$src2)>;
1058 // Shuffle with MOVLPS
1059 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1060 (MOVLPSrm VR128:$src1, addr:$src2)>;
1061 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1062 (MOVLPSrm VR128:$src1, addr:$src2)>;
1063 def : Pat<(X86Movlps VR128:$src1,
1064 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1065 (MOVLPSrm VR128:$src1, addr:$src2)>;
1066 def : Pat<(X86Movlps VR128:$src1,
1067 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1068 (MOVLPSrm VR128:$src1, addr:$src2)>;
1071 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1073 (MOVLPSmr addr:$src1, VR128:$src2)>;
1074 def : Pat<(store (v4i32 (X86Movlps
1075 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1077 (MOVLPSmr addr:$src1, VR128:$src2)>;
1080 let Predicates = [HasSSE2] in {
1081 let AddedComplexity = 20 in {
1082 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1083 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1084 (MOVLPDrm VR128:$src1, addr:$src2)>;
1085 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1086 (MOVLPDrm VR128:$src1, addr:$src2)>;
1089 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1090 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1091 (MOVLPDmr addr:$src1, VR128:$src2)>;
1092 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1093 (MOVLPDmr addr:$src1, VR128:$src2)>;
1095 // Shuffle with MOVLPD
1096 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1097 (MOVLPDrm VR128:$src1, addr:$src2)>;
1098 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1099 (MOVLPDrm VR128:$src1, addr:$src2)>;
1100 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1101 (scalar_to_vector (loadf64 addr:$src2)))),
1102 (MOVLPDrm VR128:$src1, addr:$src2)>;
1105 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1107 (MOVLPDmr addr:$src1, VR128:$src2)>;
1108 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1110 (MOVLPDmr addr:$src1, VR128:$src2)>;
1113 //===----------------------------------------------------------------------===//
1114 // SSE 1 & 2 - Move Hi packed FP Instructions
1115 //===----------------------------------------------------------------------===//
1117 let AddedComplexity = 20 in {
1118 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1119 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1121 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1122 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1123 "\t{$src2, $dst|$dst, $src2}">;
1126 // v2f64 extract element 1 is always custom lowered to unpack high to low
1127 // and extract element 0 so the non-store version isn't too horrible.
1128 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1129 "movhps\t{$src, $dst|$dst, $src}",
1130 [(store (f64 (vector_extract
1131 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1132 (undef)), (iPTR 0))), addr:$dst)]>,
1134 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1135 "movhpd\t{$src, $dst|$dst, $src}",
1136 [(store (f64 (vector_extract
1137 (v2f64 (unpckh VR128:$src, (undef))),
1138 (iPTR 0))), addr:$dst)]>,
1140 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1141 "movhps\t{$src, $dst|$dst, $src}",
1142 [(store (f64 (vector_extract
1143 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1144 (undef)), (iPTR 0))), addr:$dst)]>;
1145 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1146 "movhpd\t{$src, $dst|$dst, $src}",
1147 [(store (f64 (vector_extract
1148 (v2f64 (unpckh VR128:$src, (undef))),
1149 (iPTR 0))), addr:$dst)]>;
1151 let Predicates = [HasAVX] in {
1153 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1154 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1155 def : Pat<(X86Movlhps VR128:$src1,
1156 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1157 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1158 def : Pat<(X86Movlhps VR128:$src1,
1159 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1160 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1162 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1163 // is during lowering, where it's not possible to recognize the load fold cause
1164 // it has two uses through a bitcast. One use disappears at isel time and the
1165 // fold opportunity reappears.
1166 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1167 (scalar_to_vector (loadf64 addr:$src2)))),
1168 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1170 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1171 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1172 (scalar_to_vector (loadf64 addr:$src2)))),
1173 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1176 def : Pat<(store (f64 (vector_extract
1177 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1178 (VMOVHPSmr addr:$dst, VR128:$src)>;
1179 def : Pat<(store (f64 (vector_extract
1180 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1181 (VMOVHPDmr addr:$dst, VR128:$src)>;
1184 let Predicates = [HasSSE1] in {
1186 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1187 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1188 def : Pat<(X86Movlhps VR128:$src1,
1189 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1190 (MOVHPSrm VR128:$src1, addr:$src2)>;
1191 def : Pat<(X86Movlhps VR128:$src1,
1192 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1193 (MOVHPSrm VR128:$src1, addr:$src2)>;
1196 def : Pat<(store (f64 (vector_extract
1197 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1198 (MOVHPSmr addr:$dst, VR128:$src)>;
1201 let Predicates = [HasSSE2] in {
1202 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1203 // is during lowering, where it's not possible to recognize the load fold cause
1204 // it has two uses through a bitcast. One use disappears at isel time and the
1205 // fold opportunity reappears.
1206 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1207 (scalar_to_vector (loadf64 addr:$src2)))),
1208 (MOVHPDrm VR128:$src1, addr:$src2)>;
1210 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1211 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1212 (scalar_to_vector (loadf64 addr:$src2)))),
1213 (MOVHPDrm VR128:$src1, addr:$src2)>;
1216 def : Pat<(store (f64 (vector_extract
1217 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
1218 (MOVHPDmr addr:$dst, VR128:$src)>;
1221 //===----------------------------------------------------------------------===//
1222 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1223 //===----------------------------------------------------------------------===//
1225 let AddedComplexity = 20 in {
1226 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1227 (ins VR128:$src1, VR128:$src2),
1228 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1230 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
1232 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1233 (ins VR128:$src1, VR128:$src2),
1234 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1236 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
1239 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1240 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1241 (ins VR128:$src1, VR128:$src2),
1242 "movlhps\t{$src2, $dst|$dst, $src2}",
1244 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1245 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1246 (ins VR128:$src1, VR128:$src2),
1247 "movhlps\t{$src2, $dst|$dst, $src2}",
1249 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1252 let Predicates = [HasAVX] in {
1254 let AddedComplexity = 20 in {
1255 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1256 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1257 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1258 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1260 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1261 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1262 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1264 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1265 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1266 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1267 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1268 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1269 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1272 let AddedComplexity = 20 in {
1273 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1274 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1275 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1277 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1278 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1279 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1280 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1281 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1284 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1285 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1286 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1287 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1290 let Predicates = [HasSSE1] in {
1292 let AddedComplexity = 20 in {
1293 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1294 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1295 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1296 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1298 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1299 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1300 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1302 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1303 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1304 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1305 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1306 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1307 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1310 let AddedComplexity = 20 in {
1311 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1312 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1313 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1315 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1316 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1317 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1318 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1319 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1322 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1323 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1324 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1325 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1328 //===----------------------------------------------------------------------===//
1329 // SSE 1 & 2 - Conversion Instructions
1330 //===----------------------------------------------------------------------===//
1332 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1333 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1335 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1336 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1337 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1338 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1341 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1342 X86MemOperand x86memop, string asm> {
1343 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, []>;
1345 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, []>;
1348 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1349 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1350 string asm, Domain d> {
1351 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1352 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1353 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1354 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1357 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1358 X86MemOperand x86memop, string asm> {
1359 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1360 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1362 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1363 (ins DstRC:$src1, x86memop:$src),
1364 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1367 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1368 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1370 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1371 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1373 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1374 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX,
1376 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1377 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1378 VEX, VEX_W, VEX_LIG;
1380 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1381 // register, but the same isn't true when only using memory operands,
1382 // provide other assembly "l" and "q" forms to address this explicitly
1383 // where appropriate to do so.
1384 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1386 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1387 VEX_4V, VEX_W, VEX_LIG;
1388 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1390 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1392 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1393 VEX_4V, VEX_W, VEX_LIG;
1395 let Predicates = [HasAVX] in {
1396 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1397 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1398 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1399 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1400 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1401 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1402 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1403 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1405 def : Pat<(f32 (sint_to_fp GR32:$src)),
1406 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1407 def : Pat<(f32 (sint_to_fp GR64:$src)),
1408 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1409 def : Pat<(f64 (sint_to_fp GR32:$src)),
1410 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1411 def : Pat<(f64 (sint_to_fp GR64:$src)),
1412 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1415 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1416 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1417 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1418 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1419 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1420 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1421 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1422 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1423 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1424 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1425 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1426 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1427 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1428 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1429 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1430 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1432 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1433 // and/or XMM operand(s).
1435 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1436 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1438 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1439 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1440 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1441 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1442 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1443 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1446 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1447 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1448 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1449 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1451 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1452 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1453 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1454 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1455 (ins DstRC:$src1, x86memop:$src2),
1457 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1458 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1459 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1462 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1463 f128mem, load, "cvtsd2si">, XD, VEX;
1464 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1465 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1468 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1469 // Get rid of this hack or rename the intrinsics, there are several
1470 // intructions that only match with the intrinsic form, why create duplicates
1471 // to let them be recognized by the assembler?
1472 defm VCVTSD2SI : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
1473 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_LIG;
1474 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
1475 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W,
1478 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1479 f128mem, load, "cvtsd2si{l}">, XD;
1480 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1481 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1484 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1485 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1486 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1487 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1489 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1490 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1491 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1492 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1495 let Constraints = "$src1 = $dst" in {
1496 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1497 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1499 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1500 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1501 "cvtsi2ss{q}">, XS, REX_W;
1502 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1503 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1505 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1506 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1507 "cvtsi2sd">, XD, REX_W;
1512 // Aliases for intrinsics
1513 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1514 f32mem, load, "cvttss2si">, XS, VEX;
1515 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1516 int_x86_sse_cvttss2si64, f32mem, load,
1517 "cvttss2si">, XS, VEX, VEX_W;
1518 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1519 f128mem, load, "cvttsd2si">, XD, VEX;
1520 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1521 int_x86_sse2_cvttsd2si64, f128mem, load,
1522 "cvttsd2si">, XD, VEX, VEX_W;
1523 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1524 f32mem, load, "cvttss2si">, XS;
1525 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1526 int_x86_sse_cvttss2si64, f32mem, load,
1527 "cvttss2si{q}">, XS, REX_W;
1528 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1529 f128mem, load, "cvttsd2si">, XD;
1530 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1531 int_x86_sse2_cvttsd2si64, f128mem, load,
1532 "cvttsd2si{q}">, XD, REX_W;
1534 let Pattern = []<dag> in {
1535 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1536 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS,
1538 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1539 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1541 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1542 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1543 SSEPackedSingle>, TB, VEX;
1544 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1545 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1546 SSEPackedSingle>, TB, VEX;
1549 let Pattern = []<dag> in {
1550 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1551 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1552 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1553 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1554 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1555 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1556 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1559 let Predicates = [HasSSE1] in {
1560 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1561 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1562 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1563 (CVTSS2SIrm addr:$src)>;
1564 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1565 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1566 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1567 (CVTSS2SI64rm addr:$src)>;
1570 let Predicates = [HasAVX] in {
1571 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1572 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1573 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1574 (VCVTSS2SIrm addr:$src)>;
1575 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1576 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1577 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1578 (VCVTSS2SI64rm addr:$src)>;
1583 // Convert scalar double to scalar single
1584 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1585 (ins FR64:$src1, FR64:$src2),
1586 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1589 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1590 (ins FR64:$src1, f64mem:$src2),
1591 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1592 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1594 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1597 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1598 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1599 [(set FR32:$dst, (fround FR64:$src))]>;
1600 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1601 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1602 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1603 Requires<[HasSSE2, OptForSize]>;
1605 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1606 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1608 let Constraints = "$src1 = $dst" in
1609 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1610 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1612 // Convert scalar single to scalar double
1613 // SSE2 instructions with XS prefix
1614 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1615 (ins FR32:$src1, FR32:$src2),
1616 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1617 []>, XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1619 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1620 (ins FR32:$src1, f32mem:$src2),
1621 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1622 []>, XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1624 let Predicates = [HasAVX] in {
1625 def : Pat<(f64 (fextend FR32:$src)),
1626 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1627 def : Pat<(fextend (loadf32 addr:$src)),
1628 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1629 def : Pat<(extloadf32 addr:$src),
1630 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1633 def : Pat<(extloadf32 addr:$src),
1634 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1635 Requires<[HasAVX, OptForSpeed]>;
1637 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1638 "cvtss2sd\t{$src, $dst|$dst, $src}",
1639 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1640 Requires<[HasSSE2]>;
1641 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1642 "cvtss2sd\t{$src, $dst|$dst, $src}",
1643 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1644 Requires<[HasSSE2, OptForSize]>;
1646 // extload f32 -> f64. This matches load+fextend because we have a hack in
1647 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1649 // Since these loads aren't folded into the fextend, we have to match it
1651 def : Pat<(fextend (loadf32 addr:$src)),
1652 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1653 def : Pat<(extloadf32 addr:$src),
1654 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1656 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1657 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1658 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1659 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1660 VR128:$src2))]>, XS, VEX_4V,
1662 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1663 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1664 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1665 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1666 (load addr:$src2)))]>, XS, VEX_4V,
1668 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1669 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1670 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1671 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1672 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1673 VR128:$src2))]>, XS,
1674 Requires<[HasSSE2]>;
1675 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1676 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1677 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1678 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1679 (load addr:$src2)))]>, XS,
1680 Requires<[HasSSE2]>;
1683 // Convert doubleword to packed single/double fp
1684 // SSE2 instructions without OpSize prefix
1685 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1686 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1687 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1688 TB, VEX, Requires<[HasAVX]>;
1689 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1690 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1691 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1692 (bitconvert (memopv2i64 addr:$src))))]>,
1693 TB, VEX, Requires<[HasAVX]>;
1694 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1695 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1696 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1697 TB, Requires<[HasSSE2]>;
1698 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1699 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1700 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1701 (bitconvert (memopv2i64 addr:$src))))]>,
1702 TB, Requires<[HasSSE2]>;
1704 // FIXME: why the non-intrinsic version is described as SSE3?
1705 // SSE2 instructions with XS prefix
1706 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1707 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1708 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1709 XS, VEX, Requires<[HasAVX]>;
1710 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1711 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1712 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1713 (bitconvert (memopv2i64 addr:$src))))]>,
1714 XS, VEX, Requires<[HasAVX]>;
1715 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1716 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1717 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1718 XS, Requires<[HasSSE2]>;
1719 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1720 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1721 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1722 (bitconvert (memopv2i64 addr:$src))))]>,
1723 XS, Requires<[HasSSE2]>;
1726 // Convert packed single/double fp to doubleword
1727 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1728 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1729 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1730 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1731 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1732 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1733 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1734 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1735 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1736 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1737 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1738 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1740 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1741 "cvtps2dq\t{$src, $dst|$dst, $src}",
1742 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1744 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1746 "cvtps2dq\t{$src, $dst|$dst, $src}",
1747 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1748 (memop addr:$src)))]>, VEX;
1749 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1750 "cvtps2dq\t{$src, $dst|$dst, $src}",
1751 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1752 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1753 "cvtps2dq\t{$src, $dst|$dst, $src}",
1754 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1755 (memop addr:$src)))]>;
1757 // SSE2 packed instructions with XD prefix
1758 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1759 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1760 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1761 XD, VEX, Requires<[HasAVX]>;
1762 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1763 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1764 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1765 (memop addr:$src)))]>,
1766 XD, VEX, Requires<[HasAVX]>;
1767 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1768 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1769 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1770 XD, Requires<[HasSSE2]>;
1771 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1772 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1773 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1774 (memop addr:$src)))]>,
1775 XD, Requires<[HasSSE2]>;
1778 // Convert with truncation packed single/double fp to doubleword
1779 // SSE2 packed instructions with XS prefix
1780 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1781 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1783 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1784 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1785 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1786 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1788 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1789 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1790 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1791 "cvttps2dq\t{$src, $dst|$dst, $src}",
1793 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1794 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1795 "cvttps2dq\t{$src, $dst|$dst, $src}",
1797 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1799 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1800 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1802 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1803 XS, VEX, Requires<[HasAVX]>;
1804 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1805 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1807 (memop addr:$src)))]>,
1808 XS, VEX, Requires<[HasAVX]>;
1810 let Predicates = [HasSSE2] in {
1811 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1812 (Int_CVTDQ2PSrr VR128:$src)>;
1813 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1814 (CVTTPS2DQrr VR128:$src)>;
1817 let Predicates = [HasAVX] in {
1818 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1819 (Int_VCVTDQ2PSrr VR128:$src)>;
1820 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1821 (VCVTTPS2DQrr VR128:$src)>;
1822 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1823 (VCVTDQ2PSYrr VR256:$src)>;
1824 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1825 (VCVTTPS2DQYrr VR256:$src)>;
1828 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1829 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1831 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1832 let isCodeGenOnly = 1 in
1833 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1834 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1835 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1836 (memop addr:$src)))]>, VEX;
1837 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1838 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1839 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1840 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1841 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1842 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1843 (memop addr:$src)))]>;
1845 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1846 // register, but the same isn't true when using memory operands instead.
1847 // Provide other assembly rr and rm forms to address this explicitly.
1848 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1849 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1852 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1853 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1854 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1855 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1858 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1859 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1860 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1861 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1863 // Convert packed single to packed double
1864 let Predicates = [HasAVX] in {
1865 // SSE2 instructions without OpSize prefix
1866 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1867 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1868 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1869 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1870 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1871 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1872 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1873 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1875 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1876 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1877 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1878 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1880 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1881 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1882 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1883 TB, VEX, Requires<[HasAVX]>;
1884 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1885 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1886 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1887 (load addr:$src)))]>,
1888 TB, VEX, Requires<[HasAVX]>;
1889 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1890 "cvtps2pd\t{$src, $dst|$dst, $src}",
1891 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1892 TB, Requires<[HasSSE2]>;
1893 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1894 "cvtps2pd\t{$src, $dst|$dst, $src}",
1895 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1896 (load addr:$src)))]>,
1897 TB, Requires<[HasSSE2]>;
1899 // Convert packed double to packed single
1900 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1901 // register, but the same isn't true when using memory operands instead.
1902 // Provide other assembly rr and rm forms to address this explicitly.
1903 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1904 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1905 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1906 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1909 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1910 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1911 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1912 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1915 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1916 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1917 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1918 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1919 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1920 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1921 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1922 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1925 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1926 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1927 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1928 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1930 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1931 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1932 (memop addr:$src)))]>;
1933 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1934 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1935 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1936 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1937 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1938 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1939 (memop addr:$src)))]>;
1941 // AVX 256-bit register conversion intrinsics
1942 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1943 // whenever possible to avoid declaring two versions of each one.
1944 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1945 (VCVTDQ2PSYrr VR256:$src)>;
1946 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1947 (VCVTDQ2PSYrm addr:$src)>;
1949 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1950 (VCVTPD2PSYrr VR256:$src)>;
1951 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1952 (VCVTPD2PSYrm addr:$src)>;
1954 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1955 (VCVTPS2DQYrr VR256:$src)>;
1956 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1957 (VCVTPS2DQYrm addr:$src)>;
1959 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1960 (VCVTPS2PDYrr VR128:$src)>;
1961 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1962 (VCVTPS2PDYrm addr:$src)>;
1964 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1965 (VCVTTPD2DQYrr VR256:$src)>;
1966 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1967 (VCVTTPD2DQYrm addr:$src)>;
1969 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1970 (VCVTTPS2DQYrr VR256:$src)>;
1971 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1972 (VCVTTPS2DQYrm addr:$src)>;
1974 // Match fround and fextend for 128/256-bit conversions
1975 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1976 (VCVTPD2PSYrr VR256:$src)>;
1977 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1978 (VCVTPD2PSYrm addr:$src)>;
1980 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1981 (VCVTPS2PDYrr VR128:$src)>;
1982 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1983 (VCVTPS2PDYrm addr:$src)>;
1985 //===----------------------------------------------------------------------===//
1986 // SSE 1 & 2 - Compare Instructions
1987 //===----------------------------------------------------------------------===//
1989 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1990 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1991 SDNode OpNode, ValueType VT, PatFrag ld_frag,
1992 string asm, string asm_alt> {
1993 def rr : SIi8<0xC2, MRMSrcReg,
1994 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
1995 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
1996 def rm : SIi8<0xC2, MRMSrcMem,
1997 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
1998 [(set RC:$dst, (OpNode (VT RC:$src1),
1999 (ld_frag addr:$src2), imm:$cc))]>;
2001 // Accept explicit immediate argument form instead of comparison code.
2002 let neverHasSideEffects = 1 in {
2003 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2004 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
2006 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2007 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
2011 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2012 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2013 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2014 XS, VEX_4V, VEX_LIG;
2015 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2016 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2017 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2018 XD, VEX_4V, VEX_LIG;
2020 let Constraints = "$src1 = $dst" in {
2021 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2022 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2023 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2025 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2026 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2027 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2031 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2032 Intrinsic Int, string asm> {
2033 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2034 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2035 [(set VR128:$dst, (Int VR128:$src1,
2036 VR128:$src, imm:$cc))]>;
2037 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2038 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
2039 [(set VR128:$dst, (Int VR128:$src1,
2040 (load addr:$src), imm:$cc))]>;
2043 // Aliases to match intrinsics which expect XMM operand(s).
2044 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2045 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2047 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2048 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2050 let Constraints = "$src1 = $dst" in {
2051 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2052 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2053 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2054 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2058 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2059 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2060 ValueType vt, X86MemOperand x86memop,
2061 PatFrag ld_frag, string OpcodeStr, Domain d> {
2062 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2063 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2064 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2065 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2066 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2067 [(set EFLAGS, (OpNode (vt RC:$src1),
2068 (ld_frag addr:$src2)))], d>;
2071 let Defs = [EFLAGS] in {
2072 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2073 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2074 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2075 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2077 let Pattern = []<dag> in {
2078 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2079 "comiss", SSEPackedSingle>, TB, VEX,
2081 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2082 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2086 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2087 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2088 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2089 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2091 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2092 load, "comiss", SSEPackedSingle>, TB, VEX;
2093 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2094 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2095 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2096 "ucomiss", SSEPackedSingle>, TB;
2097 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2098 "ucomisd", SSEPackedDouble>, TB, OpSize;
2100 let Pattern = []<dag> in {
2101 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2102 "comiss", SSEPackedSingle>, TB;
2103 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2104 "comisd", SSEPackedDouble>, TB, OpSize;
2107 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2108 load, "ucomiss", SSEPackedSingle>, TB;
2109 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2110 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2112 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2113 "comiss", SSEPackedSingle>, TB;
2114 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2115 "comisd", SSEPackedDouble>, TB, OpSize;
2116 } // Defs = [EFLAGS]
2118 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2119 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2120 Intrinsic Int, string asm, string asm_alt,
2122 let isAsmParserOnly = 1 in {
2123 def rri : PIi8<0xC2, MRMSrcReg,
2124 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2125 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], d>;
2126 def rmi : PIi8<0xC2, MRMSrcMem,
2127 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, SSECC:$cc), asm,
2128 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], d>;
2131 // Accept explicit immediate argument form instead of comparison code.
2132 def rri_alt : PIi8<0xC2, MRMSrcReg,
2133 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2135 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2136 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, i8imm:$cc),
2140 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2141 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2142 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2143 SSEPackedSingle>, TB, VEX_4V;
2144 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2145 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2146 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2147 SSEPackedDouble>, TB, OpSize, VEX_4V;
2148 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2149 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2150 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2151 SSEPackedSingle>, TB, VEX_4V;
2152 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2153 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2154 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2155 SSEPackedDouble>, TB, OpSize, VEX_4V;
2156 let Constraints = "$src1 = $dst" in {
2157 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2158 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2159 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2160 SSEPackedSingle>, TB;
2161 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2162 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2163 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2164 SSEPackedDouble>, TB, OpSize;
2167 let Predicates = [HasSSE1] in {
2168 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2169 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2170 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2171 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2174 let Predicates = [HasSSE2] in {
2175 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2176 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2177 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2178 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2181 let Predicates = [HasAVX] in {
2182 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2183 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2184 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2185 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2186 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2187 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2188 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2189 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2191 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2192 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2193 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2194 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2195 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2196 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2197 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2198 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2201 //===----------------------------------------------------------------------===//
2202 // SSE 1 & 2 - Shuffle Instructions
2203 //===----------------------------------------------------------------------===//
2205 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2206 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2207 ValueType vt, string asm, PatFrag mem_frag,
2208 Domain d, bit IsConvertibleToThreeAddress = 0> {
2209 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2210 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
2211 [(set RC:$dst, (vt (shufp:$src3
2212 RC:$src1, (mem_frag addr:$src2))))], d>;
2213 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2214 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2215 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2217 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2220 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2221 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2222 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2223 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2224 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2225 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2226 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2227 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2228 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2229 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2230 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2231 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2233 let Constraints = "$src1 = $dst" in {
2234 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2235 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2236 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2238 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2239 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2240 memopv2f64, SSEPackedDouble>, TB, OpSize;
2243 let Predicates = [HasSSE1] in {
2244 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2245 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2246 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2247 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2248 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2249 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2250 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2251 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2252 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2253 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2254 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2255 // fall back to this for SSE1)
2256 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2257 (SHUFPSrri VR128:$src2, VR128:$src1,
2258 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2259 // Special unary SHUFPSrri case.
2260 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2261 (SHUFPSrri VR128:$src1, VR128:$src1,
2262 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2265 let Predicates = [HasSSE2] in {
2266 // Special binary v4i32 shuffle cases with SHUFPS.
2267 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2268 (SHUFPSrri VR128:$src1, VR128:$src2,
2269 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2270 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2271 (bc_v4i32 (memopv2i64 addr:$src2)))),
2272 (SHUFPSrmi VR128:$src1, addr:$src2,
2273 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2274 // Special unary SHUFPDrri cases.
2275 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2276 (SHUFPDrri VR128:$src1, VR128:$src1,
2277 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2278 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2279 (SHUFPDrri VR128:$src1, VR128:$src1,
2280 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2281 // Special binary v2i64 shuffle cases using SHUFPDrri.
2282 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2283 (SHUFPDrri VR128:$src1, VR128:$src2,
2284 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2285 // Generic SHUFPD patterns
2286 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2287 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2288 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2289 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2290 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2291 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2292 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2295 let Predicates = [HasAVX] in {
2296 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2297 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2298 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2299 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2300 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2301 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2302 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2303 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2304 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2305 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2306 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2307 // fall back to this for SSE1)
2308 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2309 (VSHUFPSrri VR128:$src2, VR128:$src1,
2310 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2311 // Special unary SHUFPSrri case.
2312 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2313 (VSHUFPSrri VR128:$src1, VR128:$src1,
2314 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2315 // Special binary v4i32 shuffle cases with SHUFPS.
2316 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2317 (VSHUFPSrri VR128:$src1, VR128:$src2,
2318 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2319 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2320 (bc_v4i32 (memopv2i64 addr:$src2)))),
2321 (VSHUFPSrmi VR128:$src1, addr:$src2,
2322 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2323 // Special unary SHUFPDrri cases.
2324 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2325 (VSHUFPDrri VR128:$src1, VR128:$src1,
2326 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2327 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2328 (VSHUFPDrri VR128:$src1, VR128:$src1,
2329 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2330 // Special binary v2i64 shuffle cases using SHUFPDrri.
2331 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2332 (VSHUFPDrri VR128:$src1, VR128:$src2,
2333 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2335 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2336 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2337 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2338 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2339 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2340 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2341 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2344 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2345 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2346 def : Pat<(v8i32 (X86Shufps VR256:$src1,
2347 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2348 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2350 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2351 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2352 def : Pat<(v8f32 (X86Shufps VR256:$src1,
2353 (memopv8f32 addr:$src2), (i8 imm:$imm))),
2354 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2356 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2357 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2358 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
2359 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2360 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2362 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2363 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2364 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
2365 (memopv4f64 addr:$src2), (i8 imm:$imm))),
2366 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2369 //===----------------------------------------------------------------------===//
2370 // SSE 1 & 2 - Unpack Instructions
2371 //===----------------------------------------------------------------------===//
2373 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2374 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2375 PatFrag mem_frag, RegisterClass RC,
2376 X86MemOperand x86memop, string asm,
2378 def rr : PI<opc, MRMSrcReg,
2379 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2381 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2382 def rm : PI<opc, MRMSrcMem,
2383 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2385 (vt (OpNode RC:$src1,
2386 (mem_frag addr:$src2))))], d>;
2389 let AddedComplexity = 10 in {
2390 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2391 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2392 SSEPackedSingle>, TB, VEX_4V;
2393 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2394 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2395 SSEPackedDouble>, TB, OpSize, VEX_4V;
2396 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2397 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2398 SSEPackedSingle>, TB, VEX_4V;
2399 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2400 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2401 SSEPackedDouble>, TB, OpSize, VEX_4V;
2403 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2404 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2405 SSEPackedSingle>, TB, VEX_4V;
2406 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2407 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2408 SSEPackedDouble>, TB, OpSize, VEX_4V;
2409 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2410 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2411 SSEPackedSingle>, TB, VEX_4V;
2412 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2413 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2414 SSEPackedDouble>, TB, OpSize, VEX_4V;
2416 let Constraints = "$src1 = $dst" in {
2417 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2418 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2419 SSEPackedSingle>, TB;
2420 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2421 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2422 SSEPackedDouble>, TB, OpSize;
2423 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2424 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2425 SSEPackedSingle>, TB;
2426 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2427 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2428 SSEPackedDouble>, TB, OpSize;
2429 } // Constraints = "$src1 = $dst"
2430 } // AddedComplexity
2432 let Predicates = [HasSSE1] in {
2433 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2434 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2435 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2436 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2437 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2438 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2439 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2440 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2443 let Predicates = [HasSSE2] in {
2444 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2445 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2446 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2447 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2448 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2449 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2450 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2451 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2453 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2454 // problem is during lowering, where it's not possible to recognize the load
2455 // fold cause it has two uses through a bitcast. One use disappears at isel
2456 // time and the fold opportunity reappears.
2457 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2458 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2460 let AddedComplexity = 10 in
2461 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2462 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2465 let Predicates = [HasAVX] in {
2466 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2467 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2468 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2469 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2470 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2471 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2472 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2473 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2475 def : Pat<(v8f32 (X86Unpcklps VR256:$src1, (memopv8f32 addr:$src2))),
2476 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2477 def : Pat<(v8f32 (X86Unpcklps VR256:$src1, VR256:$src2)),
2478 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2479 def : Pat<(v8i32 (X86Unpcklps VR256:$src1, VR256:$src2)),
2480 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2481 def : Pat<(v8i32 (X86Unpcklps VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2482 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2483 def : Pat<(v8f32 (X86Unpckhps VR256:$src1, (memopv8f32 addr:$src2))),
2484 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2485 def : Pat<(v8f32 (X86Unpckhps VR256:$src1, VR256:$src2)),
2486 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2487 def : Pat<(v8i32 (X86Unpckhps VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2488 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2489 def : Pat<(v8i32 (X86Unpckhps VR256:$src1, VR256:$src2)),
2490 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2492 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2493 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2494 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2495 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2496 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2497 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2498 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2499 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2501 def : Pat<(v4f64 (X86Unpcklpd VR256:$src1, (memopv4f64 addr:$src2))),
2502 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2503 def : Pat<(v4f64 (X86Unpcklpd VR256:$src1, VR256:$src2)),
2504 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2505 def : Pat<(v4i64 (X86Unpcklpd VR256:$src1, (memopv4i64 addr:$src2))),
2506 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2507 def : Pat<(v4i64 (X86Unpcklpd VR256:$src1, VR256:$src2)),
2508 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2509 def : Pat<(v4f64 (X86Unpckhpd VR256:$src1, (memopv4f64 addr:$src2))),
2510 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2511 def : Pat<(v4f64 (X86Unpckhpd VR256:$src1, VR256:$src2)),
2512 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2513 def : Pat<(v4i64 (X86Unpckhpd VR256:$src1, (memopv4i64 addr:$src2))),
2514 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2515 def : Pat<(v4i64 (X86Unpckhpd VR256:$src1, VR256:$src2)),
2516 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2518 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2519 // problem is during lowering, where it's not possible to recognize the load
2520 // fold cause it has two uses through a bitcast. One use disappears at isel
2521 // time and the fold opportunity reappears.
2522 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2523 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2524 let AddedComplexity = 10 in
2525 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2526 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2529 //===----------------------------------------------------------------------===//
2530 // SSE 1 & 2 - Extract Floating-Point Sign mask
2531 //===----------------------------------------------------------------------===//
2533 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2534 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2536 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2537 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2538 [(set GR32:$dst, (Int RC:$src))], d>;
2539 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2540 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2543 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2544 SSEPackedSingle>, TB;
2545 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2546 SSEPackedDouble>, TB, OpSize;
2548 def : Pat<(i32 (X86fgetsign FR32:$src)),
2549 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2550 sub_ss))>, Requires<[HasSSE1]>;
2551 def : Pat<(i64 (X86fgetsign FR32:$src)),
2552 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2553 sub_ss))>, Requires<[HasSSE1]>;
2554 def : Pat<(i32 (X86fgetsign FR64:$src)),
2555 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2556 sub_sd))>, Requires<[HasSSE2]>;
2557 def : Pat<(i64 (X86fgetsign FR64:$src)),
2558 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2559 sub_sd))>, Requires<[HasSSE2]>;
2561 let Predicates = [HasAVX] in {
2562 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2563 "movmskps", SSEPackedSingle>, TB, VEX;
2564 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2565 "movmskpd", SSEPackedDouble>, TB,
2567 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2568 "movmskps", SSEPackedSingle>, TB, VEX;
2569 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2570 "movmskpd", SSEPackedDouble>, TB,
2573 def : Pat<(i32 (X86fgetsign FR32:$src)),
2574 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2576 def : Pat<(i64 (X86fgetsign FR32:$src)),
2577 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2579 def : Pat<(i32 (X86fgetsign FR64:$src)),
2580 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2582 def : Pat<(i64 (X86fgetsign FR64:$src)),
2583 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2587 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2588 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2589 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2590 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2592 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2593 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2594 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2595 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2599 //===----------------------------------------------------------------------===//
2600 // SSE 1 & 2 - Logical Instructions
2601 //===----------------------------------------------------------------------===//
2603 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2605 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2607 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2608 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2610 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2611 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2613 let Constraints = "$src1 = $dst" in {
2614 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2615 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2617 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2618 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2622 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2623 let mayLoad = 0 in {
2624 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2625 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2626 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2629 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2630 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2632 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2634 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2636 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2637 // are all promoted to v2i64, and the patterns are covered by the int
2638 // version. This is needed in SSE only, because v2i64 isn't supported on
2639 // SSE1, but only on SSE2.
2640 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2641 !strconcat(OpcodeStr, "ps"), f128mem, [],
2642 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2643 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2645 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2646 !strconcat(OpcodeStr, "pd"), f128mem,
2647 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2648 (bc_v2i64 (v2f64 VR128:$src2))))],
2649 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2650 (memopv2i64 addr:$src2)))], 0>,
2652 let Constraints = "$src1 = $dst" in {
2653 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2654 !strconcat(OpcodeStr, "ps"), f128mem,
2655 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2656 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2657 (memopv2i64 addr:$src2)))]>, TB;
2659 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2660 !strconcat(OpcodeStr, "pd"), f128mem,
2661 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2662 (bc_v2i64 (v2f64 VR128:$src2))))],
2663 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2664 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2668 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2670 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2672 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2673 !strconcat(OpcodeStr, "ps"), f256mem,
2674 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2675 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2676 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2678 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2679 !strconcat(OpcodeStr, "pd"), f256mem,
2680 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2681 (bc_v4i64 (v4f64 VR256:$src2))))],
2682 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2683 (memopv4i64 addr:$src2)))], 0>,
2687 // AVX 256-bit packed logical ops forms
2688 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2689 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2690 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2691 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2693 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2694 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2695 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2696 let isCommutable = 0 in
2697 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2699 //===----------------------------------------------------------------------===//
2700 // SSE 1 & 2 - Arithmetic Instructions
2701 //===----------------------------------------------------------------------===//
2703 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2706 /// In addition, we also have a special variant of the scalar form here to
2707 /// represent the associated intrinsic operation. This form is unlike the
2708 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2709 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2711 /// These three forms can each be reg+reg or reg+mem.
2714 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2716 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2718 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2719 OpNode, FR32, f32mem, Is2Addr>, XS;
2720 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2721 OpNode, FR64, f64mem, Is2Addr>, XD;
2724 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2726 let mayLoad = 0 in {
2727 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2728 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2729 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2730 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2734 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2736 let mayLoad = 0 in {
2737 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2738 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2739 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2740 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2744 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2746 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2747 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2748 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2749 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2752 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2754 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2755 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2756 SSEPackedSingle, Is2Addr>, TB;
2758 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2759 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2760 SSEPackedDouble, Is2Addr>, TB, OpSize;
2763 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2764 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2765 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2766 SSEPackedSingle, 0>, TB;
2768 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2769 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2770 SSEPackedDouble, 0>, TB, OpSize;
2773 // Binary Arithmetic instructions
2774 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2775 basic_sse12_fp_binop_s_int<0x58, "add", 0>, VEX_4V, VEX_LIG;
2776 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2777 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2778 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2779 basic_sse12_fp_binop_s_int<0x59, "mul", 0>, VEX_4V, VEX_LIG;
2780 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2781 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2783 let isCommutable = 0 in {
2784 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2785 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>, VEX_4V, VEX_LIG;
2786 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2787 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2788 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2789 basic_sse12_fp_binop_s_int<0x5E, "div", 0>, VEX_4V, VEX_LIG;
2790 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2791 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2792 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2793 basic_sse12_fp_binop_s_int<0x5F, "max", 0>, VEX_4V, VEX_LIG;
2794 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2795 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2796 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2797 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2798 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2799 basic_sse12_fp_binop_s_int<0x5D, "min", 0>, VEX_4V, VEX_LIG;
2800 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2801 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2802 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2803 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2806 let Constraints = "$src1 = $dst" in {
2807 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2808 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2809 basic_sse12_fp_binop_s_int<0x58, "add">;
2810 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2811 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2812 basic_sse12_fp_binop_s_int<0x59, "mul">;
2814 let isCommutable = 0 in {
2815 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2816 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2817 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2818 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2819 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2820 basic_sse12_fp_binop_s_int<0x5E, "div">;
2821 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2822 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2823 basic_sse12_fp_binop_s_int<0x5F, "max">,
2824 basic_sse12_fp_binop_p_int<0x5F, "max">;
2825 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2826 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2827 basic_sse12_fp_binop_s_int<0x5D, "min">,
2828 basic_sse12_fp_binop_p_int<0x5D, "min">;
2833 /// In addition, we also have a special variant of the scalar form here to
2834 /// represent the associated intrinsic operation. This form is unlike the
2835 /// plain scalar form, in that it takes an entire vector (instead of a
2836 /// scalar) and leaves the top elements undefined.
2838 /// And, we have a special variant form for a full-vector intrinsic form.
2840 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2841 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2842 SDNode OpNode, Intrinsic F32Int> {
2843 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2844 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2845 [(set FR32:$dst, (OpNode FR32:$src))]>;
2846 // For scalar unary operations, fold a load into the operation
2847 // only in OptForSize mode. It eliminates an instruction, but it also
2848 // eliminates a whole-register clobber (the load), so it introduces a
2849 // partial register update condition.
2850 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2851 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2852 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2853 Requires<[HasSSE1, OptForSize]>;
2854 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2855 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2856 [(set VR128:$dst, (F32Int VR128:$src))]>;
2857 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2858 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2859 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2862 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2863 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2864 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2865 !strconcat(OpcodeStr,
2866 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2868 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2869 !strconcat(OpcodeStr,
2870 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2871 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2872 (ins ssmem:$src1, VR128:$src2),
2873 !strconcat(OpcodeStr,
2874 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2877 /// sse1_fp_unop_p - SSE1 unops in packed form.
2878 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2879 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2880 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2881 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2882 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2883 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2884 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2887 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2888 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2889 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2890 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2891 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2892 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2893 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2894 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2897 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2898 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2899 Intrinsic V4F32Int> {
2900 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2901 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2902 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2903 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2904 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2905 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2908 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2909 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2910 Intrinsic V4F32Int> {
2911 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2912 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2913 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2914 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2915 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2916 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2919 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2920 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2921 SDNode OpNode, Intrinsic F64Int> {
2922 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2923 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2924 [(set FR64:$dst, (OpNode FR64:$src))]>;
2925 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2926 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2927 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2928 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2929 Requires<[HasSSE2, OptForSize]>;
2930 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2931 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2932 [(set VR128:$dst, (F64Int VR128:$src))]>;
2933 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2934 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2935 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2938 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2939 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2940 let neverHasSideEffects = 1 in {
2941 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2942 !strconcat(OpcodeStr,
2943 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2945 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2946 !strconcat(OpcodeStr,
2947 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2949 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2950 (ins VR128:$src1, sdmem:$src2),
2951 !strconcat(OpcodeStr,
2952 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2955 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2956 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2958 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2959 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2960 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2961 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2962 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2963 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2966 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2967 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2968 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2969 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2970 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2971 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2972 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2973 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2976 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2977 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2978 Intrinsic V2F64Int> {
2979 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2980 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2981 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2982 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2983 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2984 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2987 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2988 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2989 Intrinsic V2F64Int> {
2990 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2991 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2992 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2993 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2994 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2995 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2998 let Predicates = [HasAVX] in {
3000 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3001 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3003 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
3004 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
3005 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3006 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3007 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
3008 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
3009 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
3010 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
3013 // Reciprocal approximations. Note that these typically require refinement
3014 // in order to obtain suitable precision.
3015 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3016 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
3017 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
3018 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
3019 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
3021 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3022 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
3023 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
3024 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
3025 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
3028 def : Pat<(f32 (fsqrt FR32:$src)),
3029 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3030 def : Pat<(f32 (fsqrt (load addr:$src))),
3031 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3032 Requires<[HasAVX, OptForSize]>;
3033 def : Pat<(f64 (fsqrt FR64:$src)),
3034 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3035 def : Pat<(f64 (fsqrt (load addr:$src))),
3036 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3037 Requires<[HasAVX, OptForSize]>;
3039 def : Pat<(f32 (X86frsqrt FR32:$src)),
3040 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3041 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3042 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3043 Requires<[HasAVX, OptForSize]>;
3045 def : Pat<(f32 (X86frcp FR32:$src)),
3046 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3047 def : Pat<(f32 (X86frcp (load addr:$src))),
3048 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3049 Requires<[HasAVX, OptForSize]>;
3051 let Predicates = [HasAVX] in {
3052 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3053 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3054 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3055 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3057 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3058 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3060 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3061 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3062 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3063 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3065 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3066 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3068 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3069 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3070 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3071 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3073 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3074 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3076 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3077 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3078 (VRCPSSr (f32 (IMPLICIT_DEF)),
3079 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3081 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3082 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3086 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3087 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3088 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3089 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3090 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3091 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3093 // Reciprocal approximations. Note that these typically require refinement
3094 // in order to obtain suitable precision.
3095 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3096 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3097 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3098 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3099 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3100 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3102 // There is no f64 version of the reciprocal approximation instructions.
3104 //===----------------------------------------------------------------------===//
3105 // SSE 1 & 2 - Non-temporal stores
3106 //===----------------------------------------------------------------------===//
3108 let AddedComplexity = 400 in { // Prefer non-temporal versions
3109 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3110 (ins f128mem:$dst, VR128:$src),
3111 "movntps\t{$src, $dst|$dst, $src}",
3112 [(alignednontemporalstore (v4f32 VR128:$src),
3114 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3115 (ins f128mem:$dst, VR128:$src),
3116 "movntpd\t{$src, $dst|$dst, $src}",
3117 [(alignednontemporalstore (v2f64 VR128:$src),
3119 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
3120 (ins f128mem:$dst, VR128:$src),
3121 "movntdq\t{$src, $dst|$dst, $src}",
3122 [(alignednontemporalstore (v2f64 VR128:$src),
3125 let ExeDomain = SSEPackedInt in
3126 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3127 (ins f128mem:$dst, VR128:$src),
3128 "movntdq\t{$src, $dst|$dst, $src}",
3129 [(alignednontemporalstore (v4f32 VR128:$src),
3132 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3133 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3135 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3136 (ins f256mem:$dst, VR256:$src),
3137 "movntps\t{$src, $dst|$dst, $src}",
3138 [(alignednontemporalstore (v8f32 VR256:$src),
3140 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3141 (ins f256mem:$dst, VR256:$src),
3142 "movntpd\t{$src, $dst|$dst, $src}",
3143 [(alignednontemporalstore (v4f64 VR256:$src),
3145 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
3146 (ins f256mem:$dst, VR256:$src),
3147 "movntdq\t{$src, $dst|$dst, $src}",
3148 [(alignednontemporalstore (v4f64 VR256:$src),
3150 let ExeDomain = SSEPackedInt in
3151 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3152 (ins f256mem:$dst, VR256:$src),
3153 "movntdq\t{$src, $dst|$dst, $src}",
3154 [(alignednontemporalstore (v8f32 VR256:$src),
3158 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3159 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3160 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3161 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3162 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3163 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3165 let AddedComplexity = 400 in { // Prefer non-temporal versions
3166 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3167 "movntps\t{$src, $dst|$dst, $src}",
3168 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3169 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3170 "movntpd\t{$src, $dst|$dst, $src}",
3171 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3173 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3174 "movntdq\t{$src, $dst|$dst, $src}",
3175 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
3177 let ExeDomain = SSEPackedInt in
3178 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3179 "movntdq\t{$src, $dst|$dst, $src}",
3180 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3182 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3183 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3185 // There is no AVX form for instructions below this point
3186 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3187 "movnti{l}\t{$src, $dst|$dst, $src}",
3188 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3189 TB, Requires<[HasSSE2]>;
3190 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3191 "movnti{q}\t{$src, $dst|$dst, $src}",
3192 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3193 TB, Requires<[HasSSE2]>;
3196 //===----------------------------------------------------------------------===//
3197 // SSE 1 & 2 - Prefetch and memory fence
3198 //===----------------------------------------------------------------------===//
3200 // Prefetch intrinsic.
3201 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
3202 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
3203 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
3204 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
3205 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
3206 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
3207 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
3208 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
3211 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3212 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3213 TB, Requires<[HasSSE2]>;
3215 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3216 // was introduced with SSE2, it's backward compatible.
3217 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3219 // Load, store, and memory fence
3220 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3221 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3222 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3223 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3224 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3225 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3227 def : Pat<(X86SFence), (SFENCE)>;
3228 def : Pat<(X86LFence), (LFENCE)>;
3229 def : Pat<(X86MFence), (MFENCE)>;
3231 //===----------------------------------------------------------------------===//
3232 // SSE 1 & 2 - Load/Store XCSR register
3233 //===----------------------------------------------------------------------===//
3235 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3236 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3237 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3238 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3240 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3241 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3242 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3243 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3245 //===---------------------------------------------------------------------===//
3246 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3247 //===---------------------------------------------------------------------===//
3249 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3251 let neverHasSideEffects = 1 in {
3252 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3253 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3254 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3255 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3257 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3258 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3259 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3260 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3263 let isCodeGenOnly = 1 in {
3264 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3265 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3266 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3267 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3268 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3269 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3270 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3271 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3274 let canFoldAsLoad = 1, mayLoad = 1 in {
3275 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3276 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3277 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3278 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3279 let Predicates = [HasAVX] in {
3280 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3281 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3282 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3283 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3287 let mayStore = 1 in {
3288 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3289 (ins i128mem:$dst, VR128:$src),
3290 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3291 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3292 (ins i256mem:$dst, VR256:$src),
3293 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3294 let Predicates = [HasAVX] in {
3295 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3296 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3297 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3298 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3302 let neverHasSideEffects = 1 in
3303 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3304 "movdqa\t{$src, $dst|$dst, $src}", []>;
3306 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3307 "movdqu\t{$src, $dst|$dst, $src}",
3308 []>, XS, Requires<[HasSSE2]>;
3311 let isCodeGenOnly = 1 in {
3312 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3313 "movdqa\t{$src, $dst|$dst, $src}", []>;
3315 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3316 "movdqu\t{$src, $dst|$dst, $src}",
3317 []>, XS, Requires<[HasSSE2]>;
3320 let canFoldAsLoad = 1, mayLoad = 1 in {
3321 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3322 "movdqa\t{$src, $dst|$dst, $src}",
3323 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3324 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3325 "movdqu\t{$src, $dst|$dst, $src}",
3326 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3327 XS, Requires<[HasSSE2]>;
3330 let mayStore = 1 in {
3331 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3332 "movdqa\t{$src, $dst|$dst, $src}",
3333 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3334 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3335 "movdqu\t{$src, $dst|$dst, $src}",
3336 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3337 XS, Requires<[HasSSE2]>;
3340 // Intrinsic forms of MOVDQU load and store
3341 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3342 "vmovdqu\t{$src, $dst|$dst, $src}",
3343 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3344 XS, VEX, Requires<[HasAVX]>;
3346 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3347 "movdqu\t{$src, $dst|$dst, $src}",
3348 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3349 XS, Requires<[HasSSE2]>;
3351 } // ExeDomain = SSEPackedInt
3353 let Predicates = [HasAVX] in {
3354 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
3355 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3356 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3359 //===---------------------------------------------------------------------===//
3360 // SSE2 - Packed Integer Arithmetic Instructions
3361 //===---------------------------------------------------------------------===//
3363 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3365 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3366 RegisterClass RC, PatFrag memop_frag,
3367 X86MemOperand x86memop, bit IsCommutable = 0,
3369 let isCommutable = IsCommutable in
3370 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3371 (ins RC:$src1, RC:$src2),
3373 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3374 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3375 [(set RC:$dst, (IntId RC:$src1, RC:$src2))]>;
3376 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3377 (ins RC:$src1, x86memop:$src2),
3379 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3380 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3381 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))]>;
3384 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
3385 string OpcodeStr, Intrinsic IntId,
3386 Intrinsic IntId2, RegisterClass RC,
3388 // src2 is always 128-bit
3389 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3390 (ins RC:$src1, VR128:$src2),
3392 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3393 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3394 [(set RC:$dst, (IntId RC:$src1, VR128:$src2))]>;
3395 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3396 (ins RC:$src1, i128mem:$src2),
3398 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3399 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3400 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memopv2i64 addr:$src2))))]>;
3401 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3402 (ins RC:$src1, i32i8imm:$src2),
3404 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3405 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3406 [(set RC:$dst, (IntId2 RC:$src1, (i32 imm:$src2)))]>;
3409 /// PDI_binop_rm - Simple SSE2 binary operator.
3410 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3411 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3412 X86MemOperand x86memop, bit IsCommutable = 0,
3414 let isCommutable = IsCommutable in
3415 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3416 (ins RC:$src1, RC:$src2),
3418 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3419 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3420 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
3421 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3422 (ins RC:$src1, x86memop:$src2),
3424 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3425 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3426 [(set RC:$dst, (OpVT (OpNode RC:$src1,
3427 (bitconvert (memop_frag addr:$src2)))))]>;
3429 } // ExeDomain = SSEPackedInt
3431 // 128-bit Integer Arithmetic
3433 let Predicates = [HasAVX] in {
3434 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3435 i128mem, 1, 0 /*3addr*/>, VEX_4V;
3436 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3437 i128mem, 1, 0>, VEX_4V;
3438 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3439 i128mem, 1, 0>, VEX_4V;
3440 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3441 i128mem, 1, 0>, VEX_4V;
3442 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3443 i128mem, 1, 0>, VEX_4V;
3444 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3445 i128mem, 0, 0>, VEX_4V;
3446 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3447 i128mem, 0, 0>, VEX_4V;
3448 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3449 i128mem, 0, 0>, VEX_4V;
3450 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3451 i128mem, 0, 0>, VEX_4V;
3454 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3455 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3456 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3457 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3458 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3459 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3460 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3461 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3462 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3463 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3464 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3465 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3466 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3467 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3468 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3469 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3470 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3471 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3472 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3473 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3474 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq,
3475 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3476 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3477 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3478 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3479 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3480 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3481 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3482 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3483 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3484 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3485 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3486 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3487 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3488 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3489 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3490 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3491 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3494 let Predicates = [HasAVX2] in {
3495 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3496 i256mem, 1, 0>, VEX_4V;
3497 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3498 i256mem, 1, 0>, VEX_4V;
3499 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3500 i256mem, 1, 0>, VEX_4V;
3501 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3502 i256mem, 1, 0>, VEX_4V;
3503 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3504 i256mem, 1, 0>, VEX_4V;
3505 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3506 i256mem, 0, 0>, VEX_4V;
3507 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3508 i256mem, 0, 0>, VEX_4V;
3509 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3510 i256mem, 0, 0>, VEX_4V;
3511 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3512 i256mem, 0, 0>, VEX_4V;
3515 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3516 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3517 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3518 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3519 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3520 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3521 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3522 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3523 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3524 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3525 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3526 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3527 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3528 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3529 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3530 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3531 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3532 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3533 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3534 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3535 defm VPMULUDQY : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_avx2_pmulu_dq,
3536 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3537 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3538 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3539 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3540 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3541 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3542 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3543 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3544 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3545 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3546 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3547 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3548 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3549 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3550 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3551 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3552 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3555 let Constraints = "$src1 = $dst" in {
3556 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3558 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3560 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3562 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3564 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3566 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3568 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3570 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3572 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3576 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3577 VR128, memopv2i64, i128mem>;
3578 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3579 VR128, memopv2i64, i128mem>;
3580 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3581 VR128, memopv2i64, i128mem>;
3582 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3583 VR128, memopv2i64, i128mem>;
3584 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3585 VR128, memopv2i64, i128mem, 1>;
3586 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3587 VR128, memopv2i64, i128mem, 1>;
3588 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3589 VR128, memopv2i64, i128mem, 1>;
3590 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3591 VR128, memopv2i64, i128mem, 1>;
3592 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3593 VR128, memopv2i64, i128mem, 1>;
3594 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3595 VR128, memopv2i64, i128mem, 1>;
3596 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq,
3597 VR128, memopv2i64, i128mem, 1>;
3598 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3599 VR128, memopv2i64, i128mem, 1>;
3600 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3601 VR128, memopv2i64, i128mem, 1>;
3602 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3603 VR128, memopv2i64, i128mem, 1>;
3604 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3605 VR128, memopv2i64, i128mem, 1>;
3606 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3607 VR128, memopv2i64, i128mem, 1>;
3608 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3609 VR128, memopv2i64, i128mem, 1>;
3610 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3611 VR128, memopv2i64, i128mem, 1>;
3612 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3613 VR128, memopv2i64, i128mem, 1>;
3615 } // Constraints = "$src1 = $dst"
3617 //===---------------------------------------------------------------------===//
3618 // SSE2 - Packed Integer Logical Instructions
3619 //===---------------------------------------------------------------------===//
3621 let Predicates = [HasAVX] in {
3622 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3623 int_x86_sse2_psll_w, int_x86_sse2_pslli_w,
3625 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3626 int_x86_sse2_psll_d, int_x86_sse2_pslli_d,
3628 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3629 int_x86_sse2_psll_q, int_x86_sse2_pslli_q,
3632 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3633 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w,
3635 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3636 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d,
3638 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3639 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q,
3642 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3643 int_x86_sse2_psra_w, int_x86_sse2_psrai_w,
3645 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3646 int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
3649 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
3650 i128mem, 1, 0>, VEX_4V;
3651 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
3652 i128mem, 1, 0>, VEX_4V;
3653 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
3654 i128mem, 1, 0>, VEX_4V;
3656 let ExeDomain = SSEPackedInt in {
3657 let neverHasSideEffects = 1 in {
3658 // 128-bit logical shifts.
3659 def VPSLLDQri : PDIi8<0x73, MRM7r,
3660 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3661 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3663 def VPSRLDQri : PDIi8<0x73, MRM3r,
3664 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3665 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3667 // PSRADQri doesn't exist in SSE[1-3].
3669 def VPANDNrr : PDI<0xDF, MRMSrcReg,
3670 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3671 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3673 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
3675 def VPANDNrm : PDI<0xDF, MRMSrcMem,
3676 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3677 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3678 [(set VR128:$dst, (X86andnp VR128:$src1,
3679 (memopv2i64 addr:$src2)))]>, VEX_4V;
3683 let Predicates = [HasAVX2] in {
3684 defm VPSLLWY : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3685 int_x86_avx2_psll_w, int_x86_avx2_pslli_w,
3687 defm VPSLLDY : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3688 int_x86_avx2_psll_d, int_x86_avx2_pslli_d,
3690 defm VPSLLQY : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3691 int_x86_avx2_psll_q, int_x86_avx2_pslli_q,
3694 defm VPSRLWY : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3695 int_x86_avx2_psrl_w, int_x86_avx2_psrli_w,
3697 defm VPSRLDY : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3698 int_x86_avx2_psrl_d, int_x86_avx2_psrli_d,
3700 defm VPSRLQY : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3701 int_x86_avx2_psrl_q, int_x86_avx2_psrli_q,
3704 defm VPSRAWY : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3705 int_x86_avx2_psra_w, int_x86_avx2_psrai_w,
3707 defm VPSRADY : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3708 int_x86_avx2_psra_d, int_x86_avx2_psrai_d,
3711 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
3712 i256mem, 1, 0>, VEX_4V;
3713 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
3714 i256mem, 1, 0>, VEX_4V;
3715 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
3716 i256mem, 1, 0>, VEX_4V;
3718 let ExeDomain = SSEPackedInt in {
3719 let neverHasSideEffects = 1 in {
3720 // 128-bit logical shifts.
3721 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3722 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3723 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3725 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3726 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3727 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3729 // PSRADQYri doesn't exist in SSE[1-3].
3731 def VPANDNYrr : PDI<0xDF, MRMSrcReg,
3732 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
3733 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3735 (v4i64 (X86andnp VR256:$src1, VR256:$src2)))]>,VEX_4V;
3737 def VPANDNYrm : PDI<0xDF, MRMSrcMem,
3738 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
3739 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3740 [(set VR256:$dst, (X86andnp VR256:$src1,
3741 (memopv4i64 addr:$src2)))]>, VEX_4V;
3745 let Constraints = "$src1 = $dst" in {
3746 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3747 int_x86_sse2_psll_w, int_x86_sse2_pslli_w,
3749 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3750 int_x86_sse2_psll_d, int_x86_sse2_pslli_d,
3752 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3753 int_x86_sse2_psll_q, int_x86_sse2_pslli_q,
3756 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3757 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w,
3759 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3760 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d,
3762 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3763 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q,
3766 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3767 int_x86_sse2_psra_w, int_x86_sse2_psrai_w,
3769 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3770 int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
3773 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
3775 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
3777 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
3780 let ExeDomain = SSEPackedInt in {
3781 let neverHasSideEffects = 1 in {
3782 // 128-bit logical shifts.
3783 def PSLLDQri : PDIi8<0x73, MRM7r,
3784 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3785 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3786 def PSRLDQri : PDIi8<0x73, MRM3r,
3787 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3788 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3789 // PSRADQri doesn't exist in SSE[1-3].
3790 def PANDNrr : PDI<0xDF, MRMSrcReg,
3791 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3792 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3795 def PANDNrm : PDI<0xDF, MRMSrcMem,
3796 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3797 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3800 } // Constraints = "$src1 = $dst"
3802 let Predicates = [HasAVX] in {
3803 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3804 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3805 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3806 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3807 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3808 (VPSLLDQri VR128:$src1, imm:$src2)>;
3809 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3810 (VPSRLDQri VR128:$src1, imm:$src2)>;
3811 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3812 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3814 // Shift up / down and insert zero's.
3815 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3816 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3817 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3818 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3821 let Predicates = [HasAVX2] in {
3822 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
3823 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3824 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
3825 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3826 def : Pat<(int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2),
3827 (VPSLLDQYri VR256:$src1, imm:$src2)>;
3828 def : Pat<(int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2),
3829 (VPSRLDQYri VR256:$src1, imm:$src2)>;
3832 let Predicates = [HasSSE2] in {
3833 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3834 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3835 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3836 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3837 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3838 (PSLLDQri VR128:$src1, imm:$src2)>;
3839 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3840 (PSRLDQri VR128:$src1, imm:$src2)>;
3841 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3842 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3844 // Shift up / down and insert zero's.
3845 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3846 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3847 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3848 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3851 //===---------------------------------------------------------------------===//
3852 // SSE2 - Packed Integer Comparison Instructions
3853 //===---------------------------------------------------------------------===//
3855 let Predicates = [HasAVX] in {
3856 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b,
3857 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3858 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w,
3859 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3860 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d,
3861 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3862 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b,
3863 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3864 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w,
3865 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3866 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d,
3867 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3869 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3870 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3871 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
3872 (bc_v16i8 (memopv2i64 addr:$src2)))),
3873 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3874 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3875 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3876 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
3877 (bc_v8i16 (memopv2i64 addr:$src2)))),
3878 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3879 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3880 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3881 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
3882 (bc_v4i32 (memopv2i64 addr:$src2)))),
3883 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3885 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3886 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3887 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
3888 (bc_v16i8 (memopv2i64 addr:$src2)))),
3889 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3890 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3891 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3892 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
3893 (bc_v8i16 (memopv2i64 addr:$src2)))),
3894 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3895 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3896 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3897 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
3898 (bc_v4i32 (memopv2i64 addr:$src2)))),
3899 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3902 let Predicates = [HasAVX2] in {
3903 defm VPCMPEQBY : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_avx2_pcmpeq_b,
3904 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3905 defm VPCMPEQWY : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_avx2_pcmpeq_w,
3906 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3907 defm VPCMPEQDY : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_avx2_pcmpeq_d,
3908 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3909 defm VPCMPGTBY : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_avx2_pcmpgt_b,
3910 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3911 defm VPCMPGTWY : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_avx2_pcmpgt_w,
3912 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3913 defm VPCMPGTDY : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_avx2_pcmpgt_d,
3914 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3916 def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, VR256:$src2)),
3917 (VPCMPEQBYrr VR256:$src1, VR256:$src2)>;
3918 def : Pat<(v32i8 (X86pcmpeqb VR256:$src1,
3919 (bc_v32i8 (memopv4i64 addr:$src2)))),
3920 (VPCMPEQBYrm VR256:$src1, addr:$src2)>;
3921 def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, VR256:$src2)),
3922 (VPCMPEQWYrr VR256:$src1, VR256:$src2)>;
3923 def : Pat<(v16i16 (X86pcmpeqw VR256:$src1,
3924 (bc_v16i16 (memopv4i64 addr:$src2)))),
3925 (VPCMPEQWYrm VR256:$src1, addr:$src2)>;
3926 def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, VR256:$src2)),
3927 (VPCMPEQDYrr VR256:$src1, VR256:$src2)>;
3928 def : Pat<(v8i32 (X86pcmpeqd VR256:$src1,
3929 (bc_v8i32 (memopv4i64 addr:$src2)))),
3930 (VPCMPEQDYrm VR256:$src1, addr:$src2)>;
3932 def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, VR256:$src2)),
3933 (VPCMPGTBYrr VR256:$src1, VR256:$src2)>;
3934 def : Pat<(v32i8 (X86pcmpgtb VR256:$src1,
3935 (bc_v32i8 (memopv4i64 addr:$src2)))),
3936 (VPCMPGTBYrm VR256:$src1, addr:$src2)>;
3937 def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, VR256:$src2)),
3938 (VPCMPGTWYrr VR256:$src1, VR256:$src2)>;
3939 def : Pat<(v16i16 (X86pcmpgtw VR256:$src1,
3940 (bc_v16i16 (memopv4i64 addr:$src2)))),
3941 (VPCMPGTWYrm VR256:$src1, addr:$src2)>;
3942 def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, VR256:$src2)),
3943 (VPCMPGTDYrr VR256:$src1, VR256:$src2)>;
3944 def : Pat<(v8i32 (X86pcmpgtd VR256:$src1,
3945 (bc_v8i32 (memopv4i64 addr:$src2)))),
3946 (VPCMPGTDYrm VR256:$src1, addr:$src2)>;
3949 let Constraints = "$src1 = $dst" in {
3950 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b,
3951 VR128, memopv2i64, i128mem, 1>;
3952 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w,
3953 VR128, memopv2i64, i128mem, 1>;
3954 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d,
3955 VR128, memopv2i64, i128mem, 1>;
3956 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b,
3957 VR128, memopv2i64, i128mem>;
3958 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w,
3959 VR128, memopv2i64, i128mem>;
3960 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d,
3961 VR128, memopv2i64, i128mem>;
3962 } // Constraints = "$src1 = $dst"
3964 let Predicates = [HasSSE2] in {
3965 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3966 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3967 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
3968 (bc_v16i8 (memopv2i64 addr:$src2)))),
3969 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3970 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3971 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3972 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
3973 (bc_v8i16 (memopv2i64 addr:$src2)))),
3974 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3975 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3976 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3977 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
3978 (bc_v4i32 (memopv2i64 addr:$src2)))),
3979 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3981 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3982 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3983 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
3984 (bc_v16i8 (memopv2i64 addr:$src2)))),
3985 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3986 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3987 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3988 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
3989 (bc_v8i16 (memopv2i64 addr:$src2)))),
3990 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3991 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3992 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3993 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
3994 (bc_v4i32 (memopv2i64 addr:$src2)))),
3995 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3998 //===---------------------------------------------------------------------===//
3999 // SSE2 - Packed Integer Pack Instructions
4000 //===---------------------------------------------------------------------===//
4002 let Predicates = [HasAVX] in {
4003 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4004 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
4005 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4006 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
4007 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4008 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
4011 let Predicates = [HasAVX2] in {
4012 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4013 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
4014 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4015 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
4016 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4017 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
4020 let Constraints = "$src1 = $dst" in {
4021 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4022 VR128, memopv2i64, i128mem>;
4023 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4024 VR128, memopv2i64, i128mem>;
4025 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4026 VR128, memopv2i64, i128mem>;
4027 } // Constraints = "$src1 = $dst"
4029 //===---------------------------------------------------------------------===//
4030 // SSE2 - Packed Integer Shuffle Instructions
4031 //===---------------------------------------------------------------------===//
4033 let ExeDomain = SSEPackedInt in {
4034 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
4036 def ri : Ii8<0x70, MRMSrcReg,
4037 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4038 !strconcat(OpcodeStr,
4039 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4040 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
4042 def mi : Ii8<0x70, MRMSrcMem,
4043 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4044 !strconcat(OpcodeStr,
4045 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4046 [(set VR128:$dst, (vt (pshuf_frag:$src2
4047 (bc_frag (memopv2i64 addr:$src1)),
4051 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
4053 def Yri : Ii8<0x70, MRMSrcReg,
4054 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4055 !strconcat(OpcodeStr,
4056 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4057 [(set VR256:$dst, (vt (pshuf_frag:$src2 VR256:$src1,
4059 def Ymi : Ii8<0x70, MRMSrcMem,
4060 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4061 !strconcat(OpcodeStr,
4062 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4063 [(set VR256:$dst, (vt (pshuf_frag:$src2
4064 (bc_frag (memopv4i64 addr:$src1)),
4067 } // ExeDomain = SSEPackedInt
4069 let Predicates = [HasAVX] in {
4070 let AddedComplexity = 5 in
4071 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
4074 // SSE2 with ImmT == Imm8 and XS prefix.
4075 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
4078 // SSE2 with ImmT == Imm8 and XD prefix.
4079 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
4082 let AddedComplexity = 5 in
4083 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
4084 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4085 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
4086 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
4087 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4089 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
4091 (VPSHUFDmi addr:$src1, imm:$imm)>;
4092 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
4094 (VPSHUFDmi addr:$src1, imm:$imm)>;
4095 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4096 (VPSHUFDri VR128:$src1, imm:$imm)>;
4097 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4098 (VPSHUFDri VR128:$src1, imm:$imm)>;
4099 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
4100 (VPSHUFHWri VR128:$src, imm:$imm)>;
4101 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
4103 (VPSHUFHWmi addr:$src, imm:$imm)>;
4104 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
4105 (VPSHUFLWri VR128:$src, imm:$imm)>;
4106 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
4108 (VPSHUFLWmi addr:$src, imm:$imm)>;
4111 let Predicates = [HasAVX2] in {
4112 let AddedComplexity = 5 in
4113 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, pshufd, bc_v8i32>, TB,
4116 // SSE2 with ImmT == Imm8 and XS prefix.
4117 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, pshufhw, bc_v16i16>, XS,
4120 // SSE2 with ImmT == Imm8 and XD prefix.
4121 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, pshuflw, bc_v16i16>, XD,
4125 let Predicates = [HasSSE2] in {
4126 let AddedComplexity = 5 in
4127 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
4129 // SSE2 with ImmT == Imm8 and XS prefix.
4130 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
4132 // SSE2 with ImmT == Imm8 and XD prefix.
4133 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
4135 let AddedComplexity = 5 in
4136 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
4137 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4138 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
4139 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
4140 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4142 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
4144 (PSHUFDmi addr:$src1, imm:$imm)>;
4145 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
4147 (PSHUFDmi addr:$src1, imm:$imm)>;
4148 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4149 (PSHUFDri VR128:$src1, imm:$imm)>;
4150 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4151 (PSHUFDri VR128:$src1, imm:$imm)>;
4152 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
4153 (PSHUFHWri VR128:$src, imm:$imm)>;
4154 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
4156 (PSHUFHWmi addr:$src, imm:$imm)>;
4157 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
4158 (PSHUFLWri VR128:$src, imm:$imm)>;
4159 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
4161 (PSHUFLWmi addr:$src, imm:$imm)>;
4164 //===---------------------------------------------------------------------===//
4165 // SSE2 - Packed Integer Unpack Instructions
4166 //===---------------------------------------------------------------------===//
4168 let ExeDomain = SSEPackedInt in {
4169 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4170 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4171 def rr : PDI<opc, MRMSrcReg,
4172 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4174 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4175 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4176 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
4177 def rm : PDI<opc, MRMSrcMem,
4178 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4180 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4181 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4182 [(set VR128:$dst, (OpNode VR128:$src1,
4183 (bc_frag (memopv2i64
4187 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4188 SDNode OpNode, PatFrag bc_frag> {
4189 def Yrr : PDI<opc, MRMSrcReg,
4190 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4191 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4192 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4193 def Yrm : PDI<opc, MRMSrcMem,
4194 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4195 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4196 [(set VR256:$dst, (OpNode VR256:$src1,
4197 (bc_frag (memopv4i64 addr:$src2))))]>;
4200 let Predicates = [HasAVX] in {
4201 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
4202 bc_v16i8, 0>, VEX_4V;
4203 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
4204 bc_v8i16, 0>, VEX_4V;
4205 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
4206 bc_v4i32, 0>, VEX_4V;
4207 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Punpcklqdq,
4208 bc_v2i64, 0>, VEX_4V;
4210 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
4211 bc_v16i8, 0>, VEX_4V;
4212 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
4213 bc_v8i16, 0>, VEX_4V;
4214 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
4215 bc_v4i32, 0>, VEX_4V;
4216 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Punpckhqdq,
4217 bc_v2i64, 0>, VEX_4V;
4220 let Predicates = [HasAVX2] in {
4221 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Punpcklbw,
4223 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Punpcklwd,
4225 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Punpckldq,
4227 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Punpcklqdq,
4230 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Punpckhbw,
4232 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Punpckhwd,
4234 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Punpckhdq,
4236 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Punpckhqdq,
4240 let Constraints = "$src1 = $dst" in {
4241 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw,
4243 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd,
4245 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq,
4247 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Punpcklqdq,
4250 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw,
4252 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd,
4254 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq,
4256 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Punpckhqdq,
4259 } // ExeDomain = SSEPackedInt
4261 // Splat v2f64 / v2i64
4262 let AddedComplexity = 10 in {
4263 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4264 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
4265 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4266 (VPUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasAVX]>;
4269 //===---------------------------------------------------------------------===//
4270 // SSE2 - Packed Integer Extract and Insert
4271 //===---------------------------------------------------------------------===//
4273 let ExeDomain = SSEPackedInt in {
4274 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4275 def rri : Ii8<0xC4, MRMSrcReg,
4276 (outs VR128:$dst), (ins VR128:$src1,
4277 GR32:$src2, i32i8imm:$src3),
4279 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4280 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4282 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
4283 def rmi : Ii8<0xC4, MRMSrcMem,
4284 (outs VR128:$dst), (ins VR128:$src1,
4285 i16mem:$src2, i32i8imm:$src3),
4287 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4288 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4290 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4295 let Predicates = [HasAVX] in
4296 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4297 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4298 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4299 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4300 imm:$src2))]>, TB, OpSize, VEX;
4301 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4302 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4303 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4304 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4308 let Predicates = [HasAVX] in {
4309 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4310 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4311 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4312 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4313 []>, TB, OpSize, VEX_4V;
4316 let Constraints = "$src1 = $dst" in
4317 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4319 } // ExeDomain = SSEPackedInt
4321 //===---------------------------------------------------------------------===//
4322 // SSE2 - Packed Mask Creation
4323 //===---------------------------------------------------------------------===//
4325 let ExeDomain = SSEPackedInt in {
4327 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4328 "pmovmskb\t{$src, $dst|$dst, $src}",
4329 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4330 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4331 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4333 let Predicates = [HasAVX2] in {
4334 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4335 "pmovmskb\t{$src, $dst|$dst, $src}",
4336 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4337 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4338 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4341 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4342 "pmovmskb\t{$src, $dst|$dst, $src}",
4343 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4345 } // ExeDomain = SSEPackedInt
4347 //===---------------------------------------------------------------------===//
4348 // SSE2 - Conditional Store
4349 //===---------------------------------------------------------------------===//
4351 let ExeDomain = SSEPackedInt in {
4354 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4355 (ins VR128:$src, VR128:$mask),
4356 "maskmovdqu\t{$mask, $src|$src, $mask}",
4357 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4359 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4360 (ins VR128:$src, VR128:$mask),
4361 "maskmovdqu\t{$mask, $src|$src, $mask}",
4362 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4365 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4366 "maskmovdqu\t{$mask, $src|$src, $mask}",
4367 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4369 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4370 "maskmovdqu\t{$mask, $src|$src, $mask}",
4371 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4373 } // ExeDomain = SSEPackedInt
4375 //===---------------------------------------------------------------------===//
4376 // SSE2 - Move Doubleword
4377 //===---------------------------------------------------------------------===//
4379 //===---------------------------------------------------------------------===//
4380 // Move Int Doubleword to Packed Double Int
4382 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4383 "movd\t{$src, $dst|$dst, $src}",
4385 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4386 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4387 "movd\t{$src, $dst|$dst, $src}",
4389 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4391 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4392 "mov{d|q}\t{$src, $dst|$dst, $src}",
4394 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4395 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4396 "mov{d|q}\t{$src, $dst|$dst, $src}",
4397 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4399 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4400 "movd\t{$src, $dst|$dst, $src}",
4402 (v4i32 (scalar_to_vector GR32:$src)))]>;
4403 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4404 "movd\t{$src, $dst|$dst, $src}",
4406 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4407 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4408 "mov{d|q}\t{$src, $dst|$dst, $src}",
4410 (v2i64 (scalar_to_vector GR64:$src)))]>;
4411 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4412 "mov{d|q}\t{$src, $dst|$dst, $src}",
4413 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4415 //===---------------------------------------------------------------------===//
4416 // Move Int Doubleword to Single Scalar
4418 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4419 "movd\t{$src, $dst|$dst, $src}",
4420 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4422 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4423 "movd\t{$src, $dst|$dst, $src}",
4424 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4426 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4427 "movd\t{$src, $dst|$dst, $src}",
4428 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4430 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4431 "movd\t{$src, $dst|$dst, $src}",
4432 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4434 //===---------------------------------------------------------------------===//
4435 // Move Packed Doubleword Int to Packed Double Int
4437 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4438 "movd\t{$src, $dst|$dst, $src}",
4439 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4441 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4442 (ins i32mem:$dst, VR128:$src),
4443 "movd\t{$src, $dst|$dst, $src}",
4444 [(store (i32 (vector_extract (v4i32 VR128:$src),
4445 (iPTR 0))), addr:$dst)]>, VEX;
4446 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4447 "movd\t{$src, $dst|$dst, $src}",
4448 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4450 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4451 "movd\t{$src, $dst|$dst, $src}",
4452 [(store (i32 (vector_extract (v4i32 VR128:$src),
4453 (iPTR 0))), addr:$dst)]>;
4455 //===---------------------------------------------------------------------===//
4456 // Move Packed Doubleword Int first element to Doubleword Int
4458 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4459 "mov{d|q}\t{$src, $dst|$dst, $src}",
4460 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4462 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4464 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4465 "mov{d|q}\t{$src, $dst|$dst, $src}",
4466 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4469 //===---------------------------------------------------------------------===//
4470 // Bitcast FR64 <-> GR64
4472 let Predicates = [HasAVX] in
4473 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4474 "vmovq\t{$src, $dst|$dst, $src}",
4475 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4477 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4478 "mov{d|q}\t{$src, $dst|$dst, $src}",
4479 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4480 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4481 "movq\t{$src, $dst|$dst, $src}",
4482 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4484 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4485 "movq\t{$src, $dst|$dst, $src}",
4486 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4487 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4488 "mov{d|q}\t{$src, $dst|$dst, $src}",
4489 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4490 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4491 "movq\t{$src, $dst|$dst, $src}",
4492 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4494 //===---------------------------------------------------------------------===//
4495 // Move Scalar Single to Double Int
4497 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4498 "movd\t{$src, $dst|$dst, $src}",
4499 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4500 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4501 "movd\t{$src, $dst|$dst, $src}",
4502 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4503 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4504 "movd\t{$src, $dst|$dst, $src}",
4505 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4506 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4507 "movd\t{$src, $dst|$dst, $src}",
4508 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4510 //===---------------------------------------------------------------------===//
4511 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4513 let AddedComplexity = 15 in {
4514 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4515 "movd\t{$src, $dst|$dst, $src}",
4516 [(set VR128:$dst, (v4i32 (X86vzmovl
4517 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4519 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4520 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4521 [(set VR128:$dst, (v2i64 (X86vzmovl
4522 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4525 let AddedComplexity = 15 in {
4526 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4527 "movd\t{$src, $dst|$dst, $src}",
4528 [(set VR128:$dst, (v4i32 (X86vzmovl
4529 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4530 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4531 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4532 [(set VR128:$dst, (v2i64 (X86vzmovl
4533 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4536 let AddedComplexity = 20 in {
4537 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4538 "movd\t{$src, $dst|$dst, $src}",
4540 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4541 (loadi32 addr:$src))))))]>,
4543 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4544 "movd\t{$src, $dst|$dst, $src}",
4546 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4547 (loadi32 addr:$src))))))]>;
4550 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4551 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4552 (MOVZDI2PDIrm addr:$src)>;
4553 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4554 (MOVZDI2PDIrm addr:$src)>;
4555 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4556 (MOVZDI2PDIrm addr:$src)>;
4559 let Predicates = [HasAVX] in {
4560 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4561 let AddedComplexity = 20 in {
4562 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4563 (VMOVZDI2PDIrm addr:$src)>;
4564 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4565 (VMOVZDI2PDIrm addr:$src)>;
4566 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4567 (VMOVZDI2PDIrm addr:$src)>;
4569 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4570 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4571 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4572 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4573 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4574 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4575 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4578 // These are the correct encodings of the instructions so that we know how to
4579 // read correct assembly, even though we continue to emit the wrong ones for
4580 // compatibility with Darwin's buggy assembler.
4581 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4582 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4583 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4584 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4585 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4586 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4587 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4588 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4589 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4590 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4591 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4592 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4594 //===---------------------------------------------------------------------===//
4595 // SSE2 - Move Quadword
4596 //===---------------------------------------------------------------------===//
4598 //===---------------------------------------------------------------------===//
4599 // Move Quadword Int to Packed Quadword Int
4601 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4602 "vmovq\t{$src, $dst|$dst, $src}",
4604 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4605 VEX, Requires<[HasAVX]>;
4606 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4607 "movq\t{$src, $dst|$dst, $src}",
4609 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4610 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4612 //===---------------------------------------------------------------------===//
4613 // Move Packed Quadword Int to Quadword Int
4615 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4616 "movq\t{$src, $dst|$dst, $src}",
4617 [(store (i64 (vector_extract (v2i64 VR128:$src),
4618 (iPTR 0))), addr:$dst)]>, VEX;
4619 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4620 "movq\t{$src, $dst|$dst, $src}",
4621 [(store (i64 (vector_extract (v2i64 VR128:$src),
4622 (iPTR 0))), addr:$dst)]>;
4624 //===---------------------------------------------------------------------===//
4625 // Store / copy lower 64-bits of a XMM register.
4627 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4628 "movq\t{$src, $dst|$dst, $src}",
4629 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4630 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4631 "movq\t{$src, $dst|$dst, $src}",
4632 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4634 let AddedComplexity = 20 in
4635 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4636 "vmovq\t{$src, $dst|$dst, $src}",
4638 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4639 (loadi64 addr:$src))))))]>,
4640 XS, VEX, Requires<[HasAVX]>;
4642 let AddedComplexity = 20 in
4643 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4644 "movq\t{$src, $dst|$dst, $src}",
4646 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4647 (loadi64 addr:$src))))))]>,
4648 XS, Requires<[HasSSE2]>;
4650 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4651 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4652 (MOVZQI2PQIrm addr:$src)>;
4653 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4654 (MOVZQI2PQIrm addr:$src)>;
4655 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4658 let Predicates = [HasAVX], AddedComplexity = 20 in {
4659 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4660 (VMOVZQI2PQIrm addr:$src)>;
4661 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4662 (VMOVZQI2PQIrm addr:$src)>;
4663 def : Pat<(v2i64 (X86vzload addr:$src)),
4664 (VMOVZQI2PQIrm addr:$src)>;
4667 //===---------------------------------------------------------------------===//
4668 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4669 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4671 let AddedComplexity = 15 in
4672 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4673 "vmovq\t{$src, $dst|$dst, $src}",
4674 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4675 XS, VEX, Requires<[HasAVX]>;
4676 let AddedComplexity = 15 in
4677 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4678 "movq\t{$src, $dst|$dst, $src}",
4679 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4680 XS, Requires<[HasSSE2]>;
4682 let AddedComplexity = 20 in
4683 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4684 "vmovq\t{$src, $dst|$dst, $src}",
4685 [(set VR128:$dst, (v2i64 (X86vzmovl
4686 (loadv2i64 addr:$src))))]>,
4687 XS, VEX, Requires<[HasAVX]>;
4688 let AddedComplexity = 20 in {
4689 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4690 "movq\t{$src, $dst|$dst, $src}",
4691 [(set VR128:$dst, (v2i64 (X86vzmovl
4692 (loadv2i64 addr:$src))))]>,
4693 XS, Requires<[HasSSE2]>;
4696 let AddedComplexity = 20 in {
4697 let Predicates = [HasSSE2] in {
4698 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4699 (MOVZPQILo2PQIrm addr:$src)>;
4700 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4701 (MOVZPQILo2PQIrr VR128:$src)>;
4703 let Predicates = [HasAVX] in {
4704 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4705 (VMOVZPQILo2PQIrm addr:$src)>;
4706 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4707 (VMOVZPQILo2PQIrr VR128:$src)>;
4711 // Instructions to match in the assembler
4712 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4713 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4714 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4715 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4716 // Recognize "movd" with GR64 destination, but encode as a "movq"
4717 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4718 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4720 // Instructions for the disassembler
4721 // xr = XMM register
4724 let Predicates = [HasAVX] in
4725 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4726 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4727 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4728 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4730 //===---------------------------------------------------------------------===//
4731 // SSE3 - Conversion Instructions
4732 //===---------------------------------------------------------------------===//
4734 // Convert Packed Double FP to Packed DW Integers
4735 let Predicates = [HasAVX] in {
4736 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4737 // register, but the same isn't true when using memory operands instead.
4738 // Provide other assembly rr and rm forms to address this explicitly.
4739 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4740 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4741 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4742 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4745 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4746 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4747 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4748 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4751 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4752 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4753 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4754 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4757 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4758 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4759 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4760 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4762 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4763 (VCVTPD2DQYrr VR256:$src)>;
4764 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4765 (VCVTPD2DQYrm addr:$src)>;
4767 // Convert Packed DW Integers to Packed Double FP
4768 let Predicates = [HasAVX] in {
4769 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4770 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4771 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4772 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4773 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4774 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4775 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4776 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4779 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4780 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4781 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4782 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4784 // AVX 256-bit register conversion intrinsics
4785 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4786 (VCVTDQ2PDYrr VR128:$src)>;
4787 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
4788 (VCVTDQ2PDYrm addr:$src)>;
4790 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4791 (VCVTPD2DQYrr VR256:$src)>;
4792 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4793 (VCVTPD2DQYrm addr:$src)>;
4795 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4796 (VCVTDQ2PDYrr VR128:$src)>;
4797 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
4798 (VCVTDQ2PDYrm addr:$src)>;
4800 //===---------------------------------------------------------------------===//
4801 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4802 //===---------------------------------------------------------------------===//
4803 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4804 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4805 X86MemOperand x86memop> {
4806 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4807 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4808 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4809 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4810 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4811 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4814 let Predicates = [HasAVX] in {
4815 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4816 v4f32, VR128, memopv4f32, f128mem>, VEX;
4817 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4818 v4f32, VR128, memopv4f32, f128mem>, VEX;
4819 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4820 v8f32, VR256, memopv8f32, f256mem>, VEX;
4821 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4822 v8f32, VR256, memopv8f32, f256mem>, VEX;
4824 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4825 memopv4f32, f128mem>;
4826 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4827 memopv4f32, f128mem>;
4829 let Predicates = [HasSSE3] in {
4830 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4831 (MOVSHDUPrr VR128:$src)>;
4832 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4833 (MOVSHDUPrm addr:$src)>;
4834 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4835 (MOVSLDUPrr VR128:$src)>;
4836 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4837 (MOVSLDUPrm addr:$src)>;
4840 let Predicates = [HasAVX] in {
4841 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4842 (VMOVSHDUPrr VR128:$src)>;
4843 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4844 (VMOVSHDUPrm addr:$src)>;
4845 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4846 (VMOVSLDUPrr VR128:$src)>;
4847 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4848 (VMOVSLDUPrm addr:$src)>;
4849 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4850 (VMOVSHDUPYrr VR256:$src)>;
4851 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4852 (VMOVSHDUPYrm addr:$src)>;
4853 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4854 (VMOVSLDUPYrr VR256:$src)>;
4855 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4856 (VMOVSLDUPYrm addr:$src)>;
4859 //===---------------------------------------------------------------------===//
4860 // SSE3 - Replicate Double FP - MOVDDUP
4861 //===---------------------------------------------------------------------===//
4863 multiclass sse3_replicate_dfp<string OpcodeStr> {
4864 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4865 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4866 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4867 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4868 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4870 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4874 // FIXME: Merge with above classe when there're patterns for the ymm version
4875 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4876 let Predicates = [HasAVX] in {
4877 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4878 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4880 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4881 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4886 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4887 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4888 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4890 let Predicates = [HasSSE3] in {
4891 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4893 (MOVDDUPrm addr:$src)>;
4894 let AddedComplexity = 5 in {
4895 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4896 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4897 (MOVDDUPrm addr:$src)>;
4898 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4899 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4900 (MOVDDUPrm addr:$src)>;
4902 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4903 (MOVDDUPrm addr:$src)>;
4904 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4905 (MOVDDUPrm addr:$src)>;
4906 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4907 (MOVDDUPrm addr:$src)>;
4908 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4909 (MOVDDUPrm addr:$src)>;
4910 def : Pat<(X86Movddup (bc_v2f64
4911 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4912 (MOVDDUPrm addr:$src)>;
4915 let Predicates = [HasAVX] in {
4916 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4918 (VMOVDDUPrm addr:$src)>;
4919 let AddedComplexity = 5 in {
4920 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4921 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4922 (VMOVDDUPrm addr:$src)>;
4923 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4924 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4925 (VMOVDDUPrm addr:$src)>;
4927 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4928 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4929 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4930 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4931 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4932 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4933 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4934 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4935 def : Pat<(X86Movddup (bc_v2f64
4936 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4937 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4940 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4941 (VMOVDDUPYrm addr:$src)>;
4942 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4943 (VMOVDDUPYrm addr:$src)>;
4944 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4945 (VMOVDDUPYrm addr:$src)>;
4946 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4947 (VMOVDDUPYrm addr:$src)>;
4948 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4949 (VMOVDDUPYrr VR256:$src)>;
4950 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4951 (VMOVDDUPYrr VR256:$src)>;
4954 //===---------------------------------------------------------------------===//
4955 // SSE3 - Move Unaligned Integer
4956 //===---------------------------------------------------------------------===//
4958 let Predicates = [HasAVX] in {
4959 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4960 "vlddqu\t{$src, $dst|$dst, $src}",
4961 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4962 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4963 "vlddqu\t{$src, $dst|$dst, $src}",
4964 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4966 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4967 "lddqu\t{$src, $dst|$dst, $src}",
4968 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4970 //===---------------------------------------------------------------------===//
4971 // SSE3 - Arithmetic
4972 //===---------------------------------------------------------------------===//
4974 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4975 X86MemOperand x86memop, bit Is2Addr = 1> {
4976 def rr : I<0xD0, MRMSrcReg,
4977 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4979 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4980 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4981 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4982 def rm : I<0xD0, MRMSrcMem,
4983 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4985 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4986 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4987 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4990 let Predicates = [HasAVX] in {
4991 let ExeDomain = SSEPackedSingle in {
4992 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4993 f128mem, 0>, TB, XD, VEX_4V;
4994 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4995 f256mem, 0>, TB, XD, VEX_4V;
4997 let ExeDomain = SSEPackedDouble in {
4998 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4999 f128mem, 0>, TB, OpSize, VEX_4V;
5000 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5001 f256mem, 0>, TB, OpSize, VEX_4V;
5004 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5005 let ExeDomain = SSEPackedSingle in
5006 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5008 let ExeDomain = SSEPackedDouble in
5009 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5010 f128mem>, TB, OpSize;
5013 //===---------------------------------------------------------------------===//
5014 // SSE3 Instructions
5015 //===---------------------------------------------------------------------===//
5018 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5019 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5020 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5022 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5023 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5024 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
5026 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5028 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5029 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5030 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
5032 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5033 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5034 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5036 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5037 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5038 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
5040 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5042 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5043 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5044 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
5047 let Predicates = [HasAVX] in {
5048 let ExeDomain = SSEPackedSingle in {
5049 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5050 X86fhadd, 0>, VEX_4V;
5051 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5052 X86fhsub, 0>, VEX_4V;
5053 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5054 X86fhadd, 0>, VEX_4V;
5055 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5056 X86fhsub, 0>, VEX_4V;
5058 let ExeDomain = SSEPackedDouble in {
5059 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5060 X86fhadd, 0>, VEX_4V;
5061 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5062 X86fhsub, 0>, VEX_4V;
5063 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5064 X86fhadd, 0>, VEX_4V;
5065 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5066 X86fhsub, 0>, VEX_4V;
5070 let Constraints = "$src1 = $dst" in {
5071 let ExeDomain = SSEPackedSingle in {
5072 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5073 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5075 let ExeDomain = SSEPackedDouble in {
5076 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5077 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5081 //===---------------------------------------------------------------------===//
5082 // SSSE3 - Packed Absolute Instructions
5083 //===---------------------------------------------------------------------===//
5086 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5087 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5088 PatFrag mem_frag128, Intrinsic IntId128> {
5089 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5091 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5092 [(set VR128:$dst, (IntId128 VR128:$src))]>,
5095 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5097 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5100 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
5103 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5104 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5105 PatFrag mem_frag256, Intrinsic IntId256> {
5106 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5108 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5109 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5112 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5117 (bitconvert (mem_frag256 addr:$src))))]>, OpSize;
5120 let Predicates = [HasAVX] in {
5121 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
5122 int_x86_ssse3_pabs_b_128>, VEX;
5123 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
5124 int_x86_ssse3_pabs_w_128>, VEX;
5125 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
5126 int_x86_ssse3_pabs_d_128>, VEX;
5129 let Predicates = [HasAVX2] in {
5130 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb", memopv32i8,
5131 int_x86_avx2_pabs_b>, VEX;
5132 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw", memopv16i16,
5133 int_x86_avx2_pabs_w>, VEX;
5134 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd", memopv8i32,
5135 int_x86_avx2_pabs_d>, VEX;
5138 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
5139 int_x86_ssse3_pabs_b_128>;
5140 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
5141 int_x86_ssse3_pabs_w_128>;
5142 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
5143 int_x86_ssse3_pabs_d_128>;
5145 //===---------------------------------------------------------------------===//
5146 // SSSE3 - Packed Binary Operator Instructions
5147 //===---------------------------------------------------------------------===//
5149 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5150 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5151 PatFrag mem_frag128, Intrinsic IntId128,
5153 let isCommutable = 1 in
5154 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5155 (ins VR128:$src1, VR128:$src2),
5157 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5158 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5159 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5161 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5162 (ins VR128:$src1, i128mem:$src2),
5164 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5165 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5167 (IntId128 VR128:$src1,
5168 (bitconvert (mem_frag128 addr:$src2))))]>, OpSize;
5171 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5172 PatFrag mem_frag256, Intrinsic IntId256> {
5173 let isCommutable = 1 in
5174 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5175 (ins VR256:$src1, VR256:$src2),
5176 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5177 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5179 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5180 (ins VR256:$src1, i256mem:$src2),
5181 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5183 (IntId256 VR256:$src1,
5184 (bitconvert (mem_frag256 addr:$src2))))]>, OpSize;
5187 let ImmT = NoImm, Predicates = [HasAVX] in {
5188 let isCommutable = 0 in {
5189 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
5190 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
5191 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
5192 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
5193 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
5194 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
5195 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
5196 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
5197 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
5198 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
5199 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
5200 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
5201 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
5202 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
5203 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
5204 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
5205 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
5206 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
5207 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
5208 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
5209 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
5210 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
5212 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
5213 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
5216 let ImmT = NoImm, Predicates = [HasAVX2] in {
5217 let isCommutable = 0 in {
5218 defm VPHADDW : SS3I_binop_rm_int_y<0x01, "vphaddw", memopv16i16,
5219 int_x86_avx2_phadd_w>, VEX_4V;
5220 defm VPHADDD : SS3I_binop_rm_int_y<0x02, "vphaddd", memopv8i32,
5221 int_x86_avx2_phadd_d>, VEX_4V;
5222 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw", memopv16i16,
5223 int_x86_avx2_phadd_sw>, VEX_4V;
5224 defm VPHSUBW : SS3I_binop_rm_int_y<0x05, "vphsubw", memopv16i16,
5225 int_x86_avx2_phsub_w>, VEX_4V;
5226 defm VPHSUBD : SS3I_binop_rm_int_y<0x06, "vphsubd", memopv8i32,
5227 int_x86_avx2_phsub_d>, VEX_4V;
5228 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw", memopv16i16,
5229 int_x86_avx2_phsub_sw>, VEX_4V;
5230 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw", memopv32i8,
5231 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5232 defm VPSHUFB : SS3I_binop_rm_int_y<0x00, "vpshufb", memopv32i8,
5233 int_x86_avx2_pshuf_b>, VEX_4V;
5234 defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb", memopv32i8,
5235 int_x86_avx2_psign_b>, VEX_4V;
5236 defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw", memopv16i16,
5237 int_x86_avx2_psign_w>, VEX_4V;
5238 defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd", memopv8i32,
5239 int_x86_avx2_psign_d>, VEX_4V;
5241 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw", memopv16i16,
5242 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5245 // None of these have i8 immediate fields.
5246 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5247 let isCommutable = 0 in {
5248 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
5249 int_x86_ssse3_phadd_w_128>;
5250 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
5251 int_x86_ssse3_phadd_d_128>;
5252 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
5253 int_x86_ssse3_phadd_sw_128>;
5254 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
5255 int_x86_ssse3_phsub_w_128>;
5256 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
5257 int_x86_ssse3_phsub_d_128>;
5258 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
5259 int_x86_ssse3_phsub_sw_128>;
5260 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
5261 int_x86_ssse3_pmadd_ub_sw_128>;
5262 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
5263 int_x86_ssse3_pshuf_b_128>;
5264 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
5265 int_x86_ssse3_psign_b_128>;
5266 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
5267 int_x86_ssse3_psign_w_128>;
5268 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
5269 int_x86_ssse3_psign_d_128>;
5271 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
5272 int_x86_ssse3_pmul_hr_sw_128>;
5275 let Predicates = [HasSSSE3] in {
5276 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
5277 (PSHUFBrr128 VR128:$src, VR128:$mask)>;
5278 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
5279 (PSHUFBrm128 VR128:$src, addr:$mask)>;
5281 def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
5282 (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
5283 def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
5284 (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
5285 def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
5286 (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
5288 def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
5289 (PHADDWrr128 VR128:$src1, VR128:$src2)>;
5290 def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
5291 (PHADDDrr128 VR128:$src1, VR128:$src2)>;
5292 def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
5293 (PHSUBWrr128 VR128:$src1, VR128:$src2)>;
5294 def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
5295 (PHSUBDrr128 VR128:$src1, VR128:$src2)>;
5298 let Predicates = [HasAVX] in {
5299 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
5300 (VPSHUFBrr128 VR128:$src, VR128:$mask)>;
5301 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
5302 (VPSHUFBrm128 VR128:$src, addr:$mask)>;
5304 def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
5305 (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
5306 def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
5307 (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
5308 def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
5309 (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
5311 def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
5312 (VPHADDWrr128 VR128:$src1, VR128:$src2)>;
5313 def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
5314 (VPHADDDrr128 VR128:$src1, VR128:$src2)>;
5315 def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
5316 (VPHSUBWrr128 VR128:$src1, VR128:$src2)>;
5317 def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
5318 (VPHSUBDrr128 VR128:$src1, VR128:$src2)>;
5321 let Predicates = [HasAVX2] in {
5322 def : Pat<(v32i8 (X86psign VR256:$src1, VR256:$src2)),
5323 (VPSIGNBrr256 VR256:$src1, VR256:$src2)>;
5324 def : Pat<(v16i16 (X86psign VR256:$src1, VR256:$src2)),
5325 (VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
5326 def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
5327 (VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
5329 def : Pat<(v16i16 (X86hadd VR256:$src1, VR256:$src2)),
5330 (VPHADDWrr256 VR256:$src1, VR256:$src2)>;
5331 def : Pat<(v8i32 (X86hadd VR256:$src1, VR256:$src2)),
5332 (VPHADDDrr256 VR256:$src1, VR256:$src2)>;
5333 def : Pat<(v16i16 (X86hsub VR256:$src1, VR256:$src2)),
5334 (VPHSUBWrr256 VR256:$src1, VR256:$src2)>;
5335 def : Pat<(v8i32 (X86hsub VR256:$src1, VR256:$src2)),
5336 (VPHSUBDrr256 VR256:$src1, VR256:$src2)>;
5339 //===---------------------------------------------------------------------===//
5340 // SSSE3 - Packed Align Instruction Patterns
5341 //===---------------------------------------------------------------------===//
5343 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5344 let neverHasSideEffects = 1 in {
5345 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5346 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5348 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5350 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5353 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5354 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5356 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5358 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5363 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5364 let neverHasSideEffects = 1 in {
5365 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5366 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5368 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5371 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5372 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5374 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5379 let Predicates = [HasAVX] in
5380 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5381 let Predicates = [HasAVX2] in
5382 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5383 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5384 defm PALIGN : ssse3_palign<"palignr">;
5386 let Predicates = [HasSSSE3] in {
5387 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5388 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5389 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5390 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5391 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5392 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5393 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5394 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5397 let Predicates = [HasAVX] in {
5398 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5399 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5400 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5401 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5402 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5403 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5404 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5405 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5408 //===---------------------------------------------------------------------===//
5409 // SSSE3 - Thread synchronization
5410 //===---------------------------------------------------------------------===//
5412 let usesCustomInserter = 1 in {
5413 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5414 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
5415 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5416 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
5419 let Uses = [EAX, ECX, EDX] in
5420 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
5421 Requires<[HasSSE3]>;
5422 let Uses = [ECX, EAX] in
5423 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
5424 Requires<[HasSSE3]>;
5426 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5427 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5429 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5430 Requires<[In32BitMode]>;
5431 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5432 Requires<[In64BitMode]>;
5434 //===----------------------------------------------------------------------===//
5435 // SSE4.1 - Packed Move with Sign/Zero Extend
5436 //===----------------------------------------------------------------------===//
5438 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5439 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5441 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5443 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5444 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5446 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5450 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5452 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5453 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5454 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5456 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5457 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5458 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5461 let Predicates = [HasAVX] in {
5462 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5464 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5466 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5468 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5470 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5472 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5476 let Predicates = [HasAVX2] in {
5477 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5478 int_x86_avx2_pmovsxbw>, VEX;
5479 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5480 int_x86_avx2_pmovsxwd>, VEX;
5481 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5482 int_x86_avx2_pmovsxdq>, VEX;
5483 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5484 int_x86_avx2_pmovzxbw>, VEX;
5485 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5486 int_x86_avx2_pmovzxwd>, VEX;
5487 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5488 int_x86_avx2_pmovzxdq>, VEX;
5491 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5492 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5493 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5494 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5495 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5496 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5498 let Predicates = [HasSSE41] in {
5499 // Common patterns involving scalar load.
5500 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5501 (PMOVSXBWrm addr:$src)>;
5502 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5503 (PMOVSXBWrm addr:$src)>;
5505 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5506 (PMOVSXWDrm addr:$src)>;
5507 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5508 (PMOVSXWDrm addr:$src)>;
5510 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5511 (PMOVSXDQrm addr:$src)>;
5512 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5513 (PMOVSXDQrm addr:$src)>;
5515 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5516 (PMOVZXBWrm addr:$src)>;
5517 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5518 (PMOVZXBWrm addr:$src)>;
5520 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5521 (PMOVZXWDrm addr:$src)>;
5522 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5523 (PMOVZXWDrm addr:$src)>;
5525 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5526 (PMOVZXDQrm addr:$src)>;
5527 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5528 (PMOVZXDQrm addr:$src)>;
5531 let Predicates = [HasAVX] in {
5532 // Common patterns involving scalar load.
5533 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5534 (VPMOVSXBWrm addr:$src)>;
5535 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5536 (VPMOVSXBWrm addr:$src)>;
5538 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5539 (VPMOVSXWDrm addr:$src)>;
5540 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5541 (VPMOVSXWDrm addr:$src)>;
5543 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5544 (VPMOVSXDQrm addr:$src)>;
5545 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5546 (VPMOVSXDQrm addr:$src)>;
5548 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5549 (VPMOVZXBWrm addr:$src)>;
5550 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5551 (VPMOVZXBWrm addr:$src)>;
5553 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5554 (VPMOVZXWDrm addr:$src)>;
5555 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5556 (VPMOVZXWDrm addr:$src)>;
5558 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5559 (VPMOVZXDQrm addr:$src)>;
5560 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5561 (VPMOVZXDQrm addr:$src)>;
5565 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5566 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5567 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5568 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5570 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5571 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5573 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5577 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5579 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5581 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5583 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5586 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5590 let Predicates = [HasAVX] in {
5591 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5593 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5595 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5597 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5601 let Predicates = [HasAVX2] in {
5602 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5603 int_x86_avx2_pmovsxbd>, VEX;
5604 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5605 int_x86_avx2_pmovsxwq>, VEX;
5606 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5607 int_x86_avx2_pmovzxbd>, VEX;
5608 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5609 int_x86_avx2_pmovzxwq>, VEX;
5612 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5613 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5614 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5615 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5617 let Predicates = [HasSSE41] in {
5618 // Common patterns involving scalar load
5619 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5620 (PMOVSXBDrm addr:$src)>;
5621 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5622 (PMOVSXWQrm addr:$src)>;
5624 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5625 (PMOVZXBDrm addr:$src)>;
5626 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5627 (PMOVZXWQrm addr:$src)>;
5630 let Predicates = [HasAVX] in {
5631 // Common patterns involving scalar load
5632 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5633 (VPMOVSXBDrm addr:$src)>;
5634 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5635 (VPMOVSXWQrm addr:$src)>;
5637 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5638 (VPMOVZXBDrm addr:$src)>;
5639 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5640 (VPMOVZXWQrm addr:$src)>;
5643 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5644 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5645 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5646 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5648 // Expecting a i16 load any extended to i32 value.
5649 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5650 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5651 [(set VR128:$dst, (IntId (bitconvert
5652 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5656 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5658 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5659 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5660 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5662 // Expecting a i16 load any extended to i32 value.
5663 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5664 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5665 [(set VR256:$dst, (IntId (bitconvert
5666 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5670 let Predicates = [HasAVX] in {
5671 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5673 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5676 let Predicates = [HasAVX2] in {
5677 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5678 int_x86_avx2_pmovsxbq>, VEX;
5679 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5680 int_x86_avx2_pmovzxbq>, VEX;
5682 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5683 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5685 let Predicates = [HasSSE41] in {
5686 // Common patterns involving scalar load
5687 def : Pat<(int_x86_sse41_pmovsxbq
5688 (bitconvert (v4i32 (X86vzmovl
5689 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5690 (PMOVSXBQrm addr:$src)>;
5692 def : Pat<(int_x86_sse41_pmovzxbq
5693 (bitconvert (v4i32 (X86vzmovl
5694 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5695 (PMOVZXBQrm addr:$src)>;
5698 let Predicates = [HasAVX] in {
5699 // Common patterns involving scalar load
5700 def : Pat<(int_x86_sse41_pmovsxbq
5701 (bitconvert (v4i32 (X86vzmovl
5702 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5703 (VPMOVSXBQrm addr:$src)>;
5705 def : Pat<(int_x86_sse41_pmovzxbq
5706 (bitconvert (v4i32 (X86vzmovl
5707 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5708 (VPMOVZXBQrm addr:$src)>;
5711 //===----------------------------------------------------------------------===//
5712 // SSE4.1 - Extract Instructions
5713 //===----------------------------------------------------------------------===//
5715 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5716 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5717 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5718 (ins VR128:$src1, i32i8imm:$src2),
5719 !strconcat(OpcodeStr,
5720 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5721 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5723 let neverHasSideEffects = 1, mayStore = 1 in
5724 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5725 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5726 !strconcat(OpcodeStr,
5727 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5730 // There's an AssertZext in the way of writing the store pattern
5731 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5734 let Predicates = [HasAVX] in {
5735 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5736 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5737 (ins VR128:$src1, i32i8imm:$src2),
5738 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5741 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5744 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5745 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5746 let neverHasSideEffects = 1, mayStore = 1 in
5747 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5748 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5749 !strconcat(OpcodeStr,
5750 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5753 // There's an AssertZext in the way of writing the store pattern
5754 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5757 let Predicates = [HasAVX] in
5758 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5760 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5763 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5764 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5765 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5766 (ins VR128:$src1, i32i8imm:$src2),
5767 !strconcat(OpcodeStr,
5768 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5770 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5771 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5772 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5773 !strconcat(OpcodeStr,
5774 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5775 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5776 addr:$dst)]>, OpSize;
5779 let Predicates = [HasAVX] in
5780 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5782 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5784 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5785 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5786 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5787 (ins VR128:$src1, i32i8imm:$src2),
5788 !strconcat(OpcodeStr,
5789 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5791 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5792 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5793 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5794 !strconcat(OpcodeStr,
5795 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5796 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5797 addr:$dst)]>, OpSize, REX_W;
5800 let Predicates = [HasAVX] in
5801 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5803 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5805 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5807 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5808 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5809 (ins VR128:$src1, i32i8imm:$src2),
5810 !strconcat(OpcodeStr,
5811 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5813 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5815 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5816 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5817 !strconcat(OpcodeStr,
5818 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5819 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5820 addr:$dst)]>, OpSize;
5823 let ExeDomain = SSEPackedSingle in {
5824 let Predicates = [HasAVX] in {
5825 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5826 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5827 (ins VR128:$src1, i32i8imm:$src2),
5828 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5831 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5834 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5835 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5838 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5839 Requires<[HasSSE41]>;
5840 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5843 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5846 //===----------------------------------------------------------------------===//
5847 // SSE4.1 - Insert Instructions
5848 //===----------------------------------------------------------------------===//
5850 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5851 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5852 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5854 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5856 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5858 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5859 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5860 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5862 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5864 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5866 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5867 imm:$src3))]>, OpSize;
5870 let Predicates = [HasAVX] in
5871 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5872 let Constraints = "$src1 = $dst" in
5873 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5875 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5876 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5877 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5879 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5881 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5883 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5885 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5886 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5888 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5890 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5892 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5893 imm:$src3)))]>, OpSize;
5896 let Predicates = [HasAVX] in
5897 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5898 let Constraints = "$src1 = $dst" in
5899 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5901 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5902 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5903 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5905 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5907 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5909 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5911 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5912 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5914 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5916 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5918 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5919 imm:$src3)))]>, OpSize;
5922 let Predicates = [HasAVX] in
5923 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5924 let Constraints = "$src1 = $dst" in
5925 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5927 // insertps has a few different modes, there's the first two here below which
5928 // are optimized inserts that won't zero arbitrary elements in the destination
5929 // vector. The next one matches the intrinsic and could zero arbitrary elements
5930 // in the target vector.
5931 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5932 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5933 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5935 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5937 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5939 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5941 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5942 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5944 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5946 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5948 (X86insrtps VR128:$src1,
5949 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5950 imm:$src3))]>, OpSize;
5953 let ExeDomain = SSEPackedSingle in {
5954 let Constraints = "$src1 = $dst" in
5955 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5956 let Predicates = [HasAVX] in
5957 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5960 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5961 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5963 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5964 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5965 Requires<[HasSSE41]>;
5967 //===----------------------------------------------------------------------===//
5968 // SSE4.1 - Round Instructions
5969 //===----------------------------------------------------------------------===//
5971 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5972 X86MemOperand x86memop, RegisterClass RC,
5973 PatFrag mem_frag32, PatFrag mem_frag64,
5974 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5975 let ExeDomain = SSEPackedSingle in {
5976 // Intrinsic operation, reg.
5977 // Vector intrinsic operation, reg
5978 def PSr : SS4AIi8<opcps, MRMSrcReg,
5979 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5980 !strconcat(OpcodeStr,
5981 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5982 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5985 // Vector intrinsic operation, mem
5986 def PSm : SS4AIi8<opcps, MRMSrcMem,
5987 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5988 !strconcat(OpcodeStr,
5989 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5991 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5993 } // ExeDomain = SSEPackedSingle
5995 let ExeDomain = SSEPackedDouble in {
5996 // Vector intrinsic operation, reg
5997 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5998 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5999 !strconcat(OpcodeStr,
6000 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6001 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6004 // Vector intrinsic operation, mem
6005 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6006 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6007 !strconcat(OpcodeStr,
6008 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6010 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6012 } // ExeDomain = SSEPackedDouble
6015 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6018 Intrinsic F64Int, bit Is2Addr = 1> {
6019 let ExeDomain = GenericDomain in {
6020 // Intrinsic operation, reg.
6021 def SSr : SS4AIi8<opcss, MRMSrcReg,
6022 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6024 !strconcat(OpcodeStr,
6025 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6026 !strconcat(OpcodeStr,
6027 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6028 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6031 // Intrinsic operation, mem.
6032 def SSm : SS4AIi8<opcss, MRMSrcMem,
6033 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6035 !strconcat(OpcodeStr,
6036 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6037 !strconcat(OpcodeStr,
6038 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6040 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6043 // Intrinsic operation, reg.
6044 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6045 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6047 !strconcat(OpcodeStr,
6048 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6049 !strconcat(OpcodeStr,
6050 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6051 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6054 // Intrinsic operation, mem.
6055 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6056 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6058 !strconcat(OpcodeStr,
6059 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6060 !strconcat(OpcodeStr,
6061 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6063 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6065 } // ExeDomain = GenericDomain
6068 // FP round - roundss, roundps, roundsd, roundpd
6069 let Predicates = [HasAVX] in {
6071 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6072 memopv4f32, memopv2f64,
6073 int_x86_sse41_round_ps,
6074 int_x86_sse41_round_pd>, VEX;
6075 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6076 memopv8f32, memopv4f64,
6077 int_x86_avx_round_ps_256,
6078 int_x86_avx_round_pd_256>, VEX;
6079 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6080 int_x86_sse41_round_ss,
6081 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6084 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6085 memopv4f32, memopv2f64,
6086 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6087 let Constraints = "$src1 = $dst" in
6088 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6089 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6091 //===----------------------------------------------------------------------===//
6092 // SSE4.1 - Packed Bit Test
6093 //===----------------------------------------------------------------------===//
6095 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6096 // the intel intrinsic that corresponds to this.
6097 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6098 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6099 "vptest\t{$src2, $src1|$src1, $src2}",
6100 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
6102 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6103 "vptest\t{$src2, $src1|$src1, $src2}",
6104 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
6107 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6108 "vptest\t{$src2, $src1|$src1, $src2}",
6109 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6111 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6112 "vptest\t{$src2, $src1|$src1, $src2}",
6113 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6117 let Defs = [EFLAGS] in {
6118 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6119 "ptest\t{$src2, $src1|$src1, $src2}",
6120 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
6122 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6123 "ptest\t{$src2, $src1|$src1, $src2}",
6124 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
6128 // The bit test instructions below are AVX only
6129 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6130 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6131 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6132 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6133 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6134 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6135 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6136 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6140 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6141 let ExeDomain = SSEPackedSingle in {
6142 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6143 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6145 let ExeDomain = SSEPackedDouble in {
6146 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6147 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6151 //===----------------------------------------------------------------------===//
6152 // SSE4.1 - Misc Instructions
6153 //===----------------------------------------------------------------------===//
6155 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6156 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6157 "popcnt{w}\t{$src, $dst|$dst, $src}",
6158 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6160 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6161 "popcnt{w}\t{$src, $dst|$dst, $src}",
6162 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6163 (implicit EFLAGS)]>, OpSize, XS;
6165 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6166 "popcnt{l}\t{$src, $dst|$dst, $src}",
6167 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6169 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6170 "popcnt{l}\t{$src, $dst|$dst, $src}",
6171 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6172 (implicit EFLAGS)]>, XS;
6174 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6175 "popcnt{q}\t{$src, $dst|$dst, $src}",
6176 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6178 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6179 "popcnt{q}\t{$src, $dst|$dst, $src}",
6180 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6181 (implicit EFLAGS)]>, XS;
6186 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6187 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6188 Intrinsic IntId128> {
6189 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6191 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6192 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6193 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6195 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6198 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
6201 let Predicates = [HasAVX] in
6202 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6203 int_x86_sse41_phminposuw>, VEX;
6204 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6205 int_x86_sse41_phminposuw>;
6207 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6208 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6209 Intrinsic IntId128, bit Is2Addr = 1> {
6210 let isCommutable = 1 in
6211 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6212 (ins VR128:$src1, VR128:$src2),
6214 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6215 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6216 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6217 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6218 (ins VR128:$src1, i128mem:$src2),
6220 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6221 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6223 (IntId128 VR128:$src1,
6224 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6227 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6228 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6229 Intrinsic IntId256> {
6230 let isCommutable = 1 in
6231 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6232 (ins VR256:$src1, VR256:$src2),
6233 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6234 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6235 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6236 (ins VR256:$src1, i256mem:$src2),
6237 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6239 (IntId256 VR256:$src1,
6240 (bitconvert (memopv32i8 addr:$src2))))]>, OpSize;
6243 let Predicates = [HasAVX] in {
6244 let isCommutable = 0 in
6245 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6247 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
6249 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6251 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6253 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6255 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6257 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6259 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6261 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6263 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6265 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6268 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
6269 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
6270 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
6271 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
6274 let Predicates = [HasAVX2] in {
6275 let isCommutable = 0 in
6276 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6277 int_x86_avx2_packusdw>, VEX_4V;
6278 defm VPCMPEQQ : SS41I_binop_rm_int_y<0x29, "vpcmpeqq",
6279 int_x86_avx2_pcmpeq_q>, VEX_4V;
6280 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6281 int_x86_avx2_pmins_b>, VEX_4V;
6282 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6283 int_x86_avx2_pmins_d>, VEX_4V;
6284 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6285 int_x86_avx2_pminu_d>, VEX_4V;
6286 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6287 int_x86_avx2_pminu_w>, VEX_4V;
6288 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6289 int_x86_avx2_pmaxs_b>, VEX_4V;
6290 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6291 int_x86_avx2_pmaxs_d>, VEX_4V;
6292 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6293 int_x86_avx2_pmaxu_d>, VEX_4V;
6294 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6295 int_x86_avx2_pmaxu_w>, VEX_4V;
6296 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6297 int_x86_avx2_pmul_dq>, VEX_4V;
6299 def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, VR256:$src2)),
6300 (VPCMPEQQYrr VR256:$src1, VR256:$src2)>;
6301 def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, (memop addr:$src2))),
6302 (VPCMPEQQYrm VR256:$src1, addr:$src2)>;
6305 let Constraints = "$src1 = $dst" in {
6306 let isCommutable = 0 in
6307 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6308 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
6309 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6310 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6311 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6312 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6313 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6314 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6315 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6316 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6317 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6320 let Predicates = [HasSSE41] in {
6321 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
6322 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
6323 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
6324 (PCMPEQQrm VR128:$src1, addr:$src2)>;
6327 /// SS48I_binop_rm - Simple SSE41 binary operator.
6328 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6329 ValueType OpVT, bit Is2Addr = 1> {
6330 let isCommutable = 1 in
6331 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6332 (ins VR128:$src1, VR128:$src2),
6334 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6335 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6336 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
6338 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6339 (ins VR128:$src1, i128mem:$src2),
6341 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6342 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6343 [(set VR128:$dst, (OpNode VR128:$src1,
6344 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
6348 /// SS48I_binop_rm - Simple SSE41 binary operator.
6349 multiclass SS48I_binop_rm_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
6351 let isCommutable = 1 in
6352 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6353 (ins VR256:$src1, VR256:$src2),
6354 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6355 [(set VR256:$dst, (OpVT (OpNode VR256:$src1, VR256:$src2)))]>,
6357 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6358 (ins VR256:$src1, i256mem:$src2),
6359 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6360 [(set VR256:$dst, (OpNode VR256:$src1,
6361 (bc_v8i32 (memopv4i64 addr:$src2))))]>,
6365 let Predicates = [HasAVX] in
6366 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
6367 let Predicates = [HasAVX2] in
6368 defm VPMULLD : SS48I_binop_rm_y<0x40, "vpmulld", mul, v8i32>, VEX_4V;
6369 let Constraints = "$src1 = $dst" in
6370 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
6372 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6373 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6374 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6375 X86MemOperand x86memop, bit Is2Addr = 1> {
6376 let isCommutable = 1 in
6377 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6378 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6380 !strconcat(OpcodeStr,
6381 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6382 !strconcat(OpcodeStr,
6383 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6384 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6386 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6387 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6389 !strconcat(OpcodeStr,
6390 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6391 !strconcat(OpcodeStr,
6392 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6395 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6399 let Predicates = [HasAVX] in {
6400 let isCommutable = 0 in {
6401 let ExeDomain = SSEPackedSingle in {
6402 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6403 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6404 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6405 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
6407 let ExeDomain = SSEPackedDouble in {
6408 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6409 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6410 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6411 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
6413 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6414 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6415 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6416 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6418 let ExeDomain = SSEPackedSingle in
6419 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6420 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6421 let ExeDomain = SSEPackedDouble in
6422 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6423 VR128, memopv16i8, i128mem, 0>, VEX_4V;
6424 let ExeDomain = SSEPackedSingle in
6425 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6426 VR256, memopv32i8, i256mem, 0>, VEX_4V;
6429 let Predicates = [HasAVX2] in {
6430 let isCommutable = 0 in {
6431 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6432 VR256, memopv32i8, i256mem, 0>, VEX_4V;
6433 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6434 VR256, memopv32i8, i256mem, 0>, VEX_4V;
6438 let Constraints = "$src1 = $dst" in {
6439 let isCommutable = 0 in {
6440 let ExeDomain = SSEPackedSingle in
6441 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6442 VR128, memopv16i8, i128mem>;
6443 let ExeDomain = SSEPackedDouble in
6444 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6445 VR128, memopv16i8, i128mem>;
6446 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6447 VR128, memopv16i8, i128mem>;
6448 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6449 VR128, memopv16i8, i128mem>;
6451 let ExeDomain = SSEPackedSingle in
6452 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6453 VR128, memopv16i8, i128mem>;
6454 let ExeDomain = SSEPackedDouble in
6455 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6456 VR128, memopv16i8, i128mem>;
6459 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6460 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6461 RegisterClass RC, X86MemOperand x86memop,
6462 PatFrag mem_frag, Intrinsic IntId> {
6463 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
6464 (ins RC:$src1, RC:$src2, RC:$src3),
6465 !strconcat(OpcodeStr,
6466 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6467 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6468 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6470 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
6471 (ins RC:$src1, x86memop:$src2, RC:$src3),
6472 !strconcat(OpcodeStr,
6473 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6475 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6477 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6480 let Predicates = [HasAVX] in {
6481 let ExeDomain = SSEPackedDouble in {
6482 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6483 memopv16i8, int_x86_sse41_blendvpd>;
6484 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6485 memopv32i8, int_x86_avx_blendv_pd_256>;
6486 } // ExeDomain = SSEPackedDouble
6487 let ExeDomain = SSEPackedSingle in {
6488 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6489 memopv16i8, int_x86_sse41_blendvps>;
6490 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6491 memopv32i8, int_x86_avx_blendv_ps_256>;
6492 } // ExeDomain = SSEPackedSingle
6493 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6494 memopv16i8, int_x86_sse41_pblendvb>;
6497 let Predicates = [HasAVX2] in {
6498 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6499 memopv32i8, int_x86_avx2_pblendvb>;
6502 let Predicates = [HasAVX] in {
6503 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6504 (v16i8 VR128:$src2))),
6505 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6506 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6507 (v4i32 VR128:$src2))),
6508 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6509 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6510 (v4f32 VR128:$src2))),
6511 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6512 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6513 (v2i64 VR128:$src2))),
6514 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6515 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6516 (v2f64 VR128:$src2))),
6517 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6518 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6519 (v8i32 VR256:$src2))),
6520 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6521 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6522 (v8f32 VR256:$src2))),
6523 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6524 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6525 (v4i64 VR256:$src2))),
6526 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6527 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6528 (v4f64 VR256:$src2))),
6529 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6532 let Predicates = [HasAVX2] in {
6533 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6534 (v32i8 VR256:$src2))),
6535 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6538 /// SS41I_ternary_int - SSE 4.1 ternary operator
6539 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6540 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
6541 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6542 (ins VR128:$src1, VR128:$src2),
6543 !strconcat(OpcodeStr,
6544 "\t{$src2, $dst|$dst, $src2}"),
6545 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6548 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6549 (ins VR128:$src1, i128mem:$src2),
6550 !strconcat(OpcodeStr,
6551 "\t{$src2, $dst|$dst, $src2}"),
6554 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
6558 let ExeDomain = SSEPackedDouble in
6559 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
6560 let ExeDomain = SSEPackedSingle in
6561 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
6562 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
6564 let Predicates = [HasSSE41] in {
6565 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6566 (v16i8 VR128:$src2))),
6567 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6568 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6569 (v4i32 VR128:$src2))),
6570 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6571 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6572 (v4f32 VR128:$src2))),
6573 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6574 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6575 (v2i64 VR128:$src2))),
6576 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6577 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6578 (v2f64 VR128:$src2))),
6579 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6582 let Predicates = [HasAVX] in
6583 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6584 "vmovntdqa\t{$src, $dst|$dst, $src}",
6585 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6587 let Predicates = [HasAVX2] in
6588 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6589 "vmovntdqa\t{$src, $dst|$dst, $src}",
6590 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6592 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6593 "movntdqa\t{$src, $dst|$dst, $src}",
6594 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6597 //===----------------------------------------------------------------------===//
6598 // SSE4.2 - Compare Instructions
6599 //===----------------------------------------------------------------------===//
6601 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6602 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
6603 Intrinsic IntId128, bit Is2Addr = 1> {
6604 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
6605 (ins VR128:$src1, VR128:$src2),
6607 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6608 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6609 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6611 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
6612 (ins VR128:$src1, i128mem:$src2),
6614 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6615 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6617 (IntId128 VR128:$src1,
6618 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6621 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6622 multiclass SS42I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6623 Intrinsic IntId256> {
6624 def Yrr : SS428I<opc, MRMSrcReg, (outs VR256:$dst),
6625 (ins VR256:$src1, VR256:$src2),
6626 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6627 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
6629 def Yrm : SS428I<opc, MRMSrcMem, (outs VR256:$dst),
6630 (ins VR256:$src1, i256mem:$src2),
6631 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6633 (IntId256 VR256:$src1,
6634 (bitconvert (memopv32i8 addr:$src2))))]>, OpSize;
6637 let Predicates = [HasAVX] in {
6638 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
6641 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6642 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
6643 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6644 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
6647 let Predicates = [HasAVX2] in {
6648 defm VPCMPGTQ : SS42I_binop_rm_int_y<0x37, "vpcmpgtq", int_x86_avx2_pcmpgt_q>,
6651 def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, VR256:$src2)),
6652 (VPCMPGTQYrr VR256:$src1, VR256:$src2)>;
6653 def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, (memop addr:$src2))),
6654 (VPCMPGTQYrm VR256:$src1, addr:$src2)>;
6657 let Constraints = "$src1 = $dst" in
6658 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
6660 let Predicates = [HasSSE42] in {
6661 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6662 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
6663 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6664 (PCMPGTQrm VR128:$src1, addr:$src2)>;
6667 //===----------------------------------------------------------------------===//
6668 // SSE4.2 - String/text Processing Instructions
6669 //===----------------------------------------------------------------------===//
6671 // Packed Compare Implicit Length Strings, Return Mask
6672 multiclass pseudo_pcmpistrm<string asm> {
6673 def REG : PseudoI<(outs VR128:$dst),
6674 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6675 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6677 def MEM : PseudoI<(outs VR128:$dst),
6678 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6679 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6680 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6683 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6684 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6685 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6688 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6689 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6690 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6691 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6693 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6694 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6695 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6698 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6699 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6700 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6701 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6703 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6704 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6705 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6708 // Packed Compare Explicit Length Strings, Return Mask
6709 multiclass pseudo_pcmpestrm<string asm> {
6710 def REG : PseudoI<(outs VR128:$dst),
6711 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6712 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6713 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6714 def MEM : PseudoI<(outs VR128:$dst),
6715 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6716 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6717 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6720 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6721 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6722 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6725 let Predicates = [HasAVX],
6726 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6727 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6728 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6729 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6731 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6732 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6733 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6736 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6737 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6738 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6739 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6741 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6742 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6743 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6746 // Packed Compare Implicit Length Strings, Return Index
6747 let Defs = [ECX, EFLAGS] in {
6748 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6749 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6750 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6751 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6752 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6753 (implicit EFLAGS)]>, OpSize;
6754 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6755 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6756 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6757 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6758 (implicit EFLAGS)]>, OpSize;
6762 let Predicates = [HasAVX] in {
6763 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6765 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6767 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6769 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6771 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6773 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6777 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6778 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6779 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6780 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6781 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6782 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6784 // Packed Compare Explicit Length Strings, Return Index
6785 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6786 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6787 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6788 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6789 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6790 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6791 (implicit EFLAGS)]>, OpSize;
6792 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6793 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6794 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6796 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6797 (implicit EFLAGS)]>, OpSize;
6801 let Predicates = [HasAVX] in {
6802 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6804 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6806 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6808 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6810 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6812 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6816 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6817 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6818 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6819 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6820 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6821 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6823 //===----------------------------------------------------------------------===//
6824 // SSE4.2 - CRC Instructions
6825 //===----------------------------------------------------------------------===//
6827 // No CRC instructions have AVX equivalents
6829 // crc intrinsic instruction
6830 // This set of instructions are only rm, the only difference is the size
6832 let Constraints = "$src1 = $dst" in {
6833 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6834 (ins GR32:$src1, i8mem:$src2),
6835 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6837 (int_x86_sse42_crc32_32_8 GR32:$src1,
6838 (load addr:$src2)))]>;
6839 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6840 (ins GR32:$src1, GR8:$src2),
6841 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6843 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6844 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6845 (ins GR32:$src1, i16mem:$src2),
6846 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6848 (int_x86_sse42_crc32_32_16 GR32:$src1,
6849 (load addr:$src2)))]>,
6851 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6852 (ins GR32:$src1, GR16:$src2),
6853 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6855 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6857 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6858 (ins GR32:$src1, i32mem:$src2),
6859 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6861 (int_x86_sse42_crc32_32_32 GR32:$src1,
6862 (load addr:$src2)))]>;
6863 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6864 (ins GR32:$src1, GR32:$src2),
6865 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6867 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6868 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6869 (ins GR64:$src1, i8mem:$src2),
6870 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6872 (int_x86_sse42_crc32_64_8 GR64:$src1,
6873 (load addr:$src2)))]>,
6875 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6876 (ins GR64:$src1, GR8:$src2),
6877 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6879 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6881 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6882 (ins GR64:$src1, i64mem:$src2),
6883 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6885 (int_x86_sse42_crc32_64_64 GR64:$src1,
6886 (load addr:$src2)))]>,
6888 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6889 (ins GR64:$src1, GR64:$src2),
6890 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6892 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6896 //===----------------------------------------------------------------------===//
6897 // AES-NI Instructions
6898 //===----------------------------------------------------------------------===//
6900 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6901 Intrinsic IntId128, bit Is2Addr = 1> {
6902 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6903 (ins VR128:$src1, VR128:$src2),
6905 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6906 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6907 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6909 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6910 (ins VR128:$src1, i128mem:$src2),
6912 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6913 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6915 (IntId128 VR128:$src1,
6916 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6919 // Perform One Round of an AES Encryption/Decryption Flow
6920 let Predicates = [HasAVX, HasAES] in {
6921 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6922 int_x86_aesni_aesenc, 0>, VEX_4V;
6923 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6924 int_x86_aesni_aesenclast, 0>, VEX_4V;
6925 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6926 int_x86_aesni_aesdec, 0>, VEX_4V;
6927 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6928 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6931 let Constraints = "$src1 = $dst" in {
6932 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6933 int_x86_aesni_aesenc>;
6934 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6935 int_x86_aesni_aesenclast>;
6936 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6937 int_x86_aesni_aesdec>;
6938 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6939 int_x86_aesni_aesdeclast>;
6942 let Predicates = [HasAES] in {
6943 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6944 (AESENCrr VR128:$src1, VR128:$src2)>;
6945 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6946 (AESENCrm VR128:$src1, addr:$src2)>;
6947 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6948 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
6949 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6950 (AESENCLASTrm VR128:$src1, addr:$src2)>;
6951 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6952 (AESDECrr VR128:$src1, VR128:$src2)>;
6953 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6954 (AESDECrm VR128:$src1, addr:$src2)>;
6955 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6956 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
6957 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6958 (AESDECLASTrm VR128:$src1, addr:$src2)>;
6961 let Predicates = [HasAVX, HasAES], AddedComplexity = 20 in {
6962 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6963 (VAESENCrr VR128:$src1, VR128:$src2)>;
6964 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6965 (VAESENCrm VR128:$src1, addr:$src2)>;
6966 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6967 (VAESENCLASTrr VR128:$src1, VR128:$src2)>;
6968 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6969 (VAESENCLASTrm VR128:$src1, addr:$src2)>;
6970 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6971 (VAESDECrr VR128:$src1, VR128:$src2)>;
6972 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6973 (VAESDECrm VR128:$src1, addr:$src2)>;
6974 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6975 (VAESDECLASTrr VR128:$src1, VR128:$src2)>;
6976 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6977 (VAESDECLASTrm VR128:$src1, addr:$src2)>;
6980 // Perform the AES InvMixColumn Transformation
6981 let Predicates = [HasAVX, HasAES] in {
6982 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6984 "vaesimc\t{$src1, $dst|$dst, $src1}",
6986 (int_x86_aesni_aesimc VR128:$src1))]>,
6988 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6989 (ins i128mem:$src1),
6990 "vaesimc\t{$src1, $dst|$dst, $src1}",
6992 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6995 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6997 "aesimc\t{$src1, $dst|$dst, $src1}",
6999 (int_x86_aesni_aesimc VR128:$src1))]>,
7001 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7002 (ins i128mem:$src1),
7003 "aesimc\t{$src1, $dst|$dst, $src1}",
7005 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
7008 // AES Round Key Generation Assist
7009 let Predicates = [HasAVX, HasAES] in {
7010 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7011 (ins VR128:$src1, i8imm:$src2),
7012 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7014 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7016 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7017 (ins i128mem:$src1, i8imm:$src2),
7018 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7020 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
7024 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7025 (ins VR128:$src1, i8imm:$src2),
7026 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7028 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7030 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7031 (ins i128mem:$src1, i8imm:$src2),
7032 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7034 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
7038 //===----------------------------------------------------------------------===//
7039 // CLMUL Instructions
7040 //===----------------------------------------------------------------------===//
7042 // Carry-less Multiplication instructions
7043 let neverHasSideEffects = 1 in {
7044 let Constraints = "$src1 = $dst" in {
7045 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7046 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7047 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7051 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7052 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7053 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7057 // AVX carry-less Multiplication instructions
7058 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7059 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7060 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7064 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7065 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7066 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7071 multiclass pclmul_alias<string asm, int immop> {
7072 def : InstAlias<!strconcat("pclmul", asm,
7073 "dq {$src, $dst|$dst, $src}"),
7074 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7076 def : InstAlias<!strconcat("pclmul", asm,
7077 "dq {$src, $dst|$dst, $src}"),
7078 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7080 def : InstAlias<!strconcat("vpclmul", asm,
7081 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7082 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7084 def : InstAlias<!strconcat("vpclmul", asm,
7085 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7086 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7088 defm : pclmul_alias<"hqhq", 0x11>;
7089 defm : pclmul_alias<"hqlq", 0x01>;
7090 defm : pclmul_alias<"lqhq", 0x10>;
7091 defm : pclmul_alias<"lqlq", 0x00>;
7093 //===----------------------------------------------------------------------===//
7095 //===----------------------------------------------------------------------===//
7097 //===----------------------------------------------------------------------===//
7098 // VBROADCAST - Load from memory and broadcast to all elements of the
7099 // destination operand
7101 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7102 X86MemOperand x86memop, Intrinsic Int> :
7103 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7104 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7105 [(set RC:$dst, (Int addr:$src))]>, VEX;
7107 // AVX2 adds register forms
7108 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7110 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7111 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7112 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7114 let ExeDomain = SSEPackedSingle in {
7115 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7116 int_x86_avx_vbroadcast_ss>;
7117 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7118 int_x86_avx_vbroadcast_ss_256>;
7120 let ExeDomain = SSEPackedDouble in
7121 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7122 int_x86_avx_vbroadcast_sd_256>;
7123 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7124 int_x86_avx_vbroadcastf128_pd_256>;
7126 let ExeDomain = SSEPackedSingle in {
7127 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7128 int_x86_avx2_vbroadcast_ss_ps>;
7129 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7130 int_x86_avx2_vbroadcast_ss_ps_256>;
7132 let ExeDomain = SSEPackedDouble in
7133 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7134 int_x86_avx2_vbroadcast_sd_pd_256>;
7136 let Predicates = [HasAVX2] in
7137 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7138 int_x86_avx2_vbroadcasti128>;
7140 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7141 (VBROADCASTF128 addr:$src)>;
7144 //===----------------------------------------------------------------------===//
7145 // VINSERTF128 - Insert packed floating-point values
7147 let neverHasSideEffects = 1 in {
7148 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7149 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7150 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7153 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7154 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7155 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7159 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
7160 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7161 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
7162 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7163 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
7164 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7166 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7168 (VINSERTF128rr VR256:$src1, VR128:$src2,
7169 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7170 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7172 (VINSERTF128rr VR256:$src1, VR128:$src2,
7173 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7174 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7176 (VINSERTF128rr VR256:$src1, VR128:$src2,
7177 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7178 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7180 (VINSERTF128rr VR256:$src1, VR128:$src2,
7181 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7182 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7184 (VINSERTF128rr VR256:$src1, VR128:$src2,
7185 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7186 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7188 (VINSERTF128rr VR256:$src1, VR128:$src2,
7189 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7191 //===----------------------------------------------------------------------===//
7192 // VEXTRACTF128 - Extract packed floating-point values
7194 let neverHasSideEffects = 1 in {
7195 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7196 (ins VR256:$src1, i8imm:$src2),
7197 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7200 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7201 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7202 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7206 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7207 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7208 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7209 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7210 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7211 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7213 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7214 (v4f32 (VEXTRACTF128rr
7215 (v8f32 VR256:$src1),
7216 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7217 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7218 (v2f64 (VEXTRACTF128rr
7219 (v4f64 VR256:$src1),
7220 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7221 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7222 (v4i32 (VEXTRACTF128rr
7223 (v8i32 VR256:$src1),
7224 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7225 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7226 (v2i64 (VEXTRACTF128rr
7227 (v4i64 VR256:$src1),
7228 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7229 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7230 (v8i16 (VEXTRACTF128rr
7231 (v16i16 VR256:$src1),
7232 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7233 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7234 (v16i8 (VEXTRACTF128rr
7235 (v32i8 VR256:$src1),
7236 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7238 //===----------------------------------------------------------------------===//
7239 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7241 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7242 Intrinsic IntLd, Intrinsic IntLd256,
7243 Intrinsic IntSt, Intrinsic IntSt256> {
7244 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7245 (ins VR128:$src1, f128mem:$src2),
7246 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7247 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7249 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7250 (ins VR256:$src1, f256mem:$src2),
7251 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7252 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7254 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7255 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7257 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7258 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7259 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7260 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7261 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7264 let ExeDomain = SSEPackedSingle in
7265 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7266 int_x86_avx_maskload_ps,
7267 int_x86_avx_maskload_ps_256,
7268 int_x86_avx_maskstore_ps,
7269 int_x86_avx_maskstore_ps_256>;
7270 let ExeDomain = SSEPackedDouble in
7271 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7272 int_x86_avx_maskload_pd,
7273 int_x86_avx_maskload_pd_256,
7274 int_x86_avx_maskstore_pd,
7275 int_x86_avx_maskstore_pd_256>;
7277 //===----------------------------------------------------------------------===//
7278 // VPERMIL - Permute Single and Double Floating-Point Values
7280 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7281 RegisterClass RC, X86MemOperand x86memop_f,
7282 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
7283 Intrinsic IntVar, Intrinsic IntImm> {
7284 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7285 (ins RC:$src1, RC:$src2),
7286 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7287 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7288 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7289 (ins RC:$src1, x86memop_i:$src2),
7290 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7291 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
7293 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7294 (ins RC:$src1, i8imm:$src2),
7295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7296 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
7297 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7298 (ins x86memop_f:$src1, i8imm:$src2),
7299 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7300 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
7303 let ExeDomain = SSEPackedSingle in {
7304 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7305 memopv4f32, memopv4i32,
7306 int_x86_avx_vpermilvar_ps,
7307 int_x86_avx_vpermil_ps>;
7308 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7309 memopv8f32, memopv8i32,
7310 int_x86_avx_vpermilvar_ps_256,
7311 int_x86_avx_vpermil_ps_256>;
7313 let ExeDomain = SSEPackedDouble in {
7314 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7315 memopv2f64, memopv2i64,
7316 int_x86_avx_vpermilvar_pd,
7317 int_x86_avx_vpermil_pd>;
7318 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7319 memopv4f64, memopv4i64,
7320 int_x86_avx_vpermilvar_pd_256,
7321 int_x86_avx_vpermil_pd_256>;
7324 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
7325 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7326 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
7327 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7328 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
7329 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7330 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
7331 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7333 //===----------------------------------------------------------------------===//
7334 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7336 let neverHasSideEffects = 1 in {
7337 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7338 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7339 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7342 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7343 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7344 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7348 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
7349 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7350 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
7351 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7352 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
7353 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7355 def : Pat<(int_x86_avx_vperm2f128_ps_256
7356 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
7357 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7358 def : Pat<(int_x86_avx_vperm2f128_pd_256
7359 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
7360 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7361 def : Pat<(int_x86_avx_vperm2f128_si_256
7362 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
7363 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7365 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7366 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7367 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7368 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7369 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7370 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7371 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7372 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7373 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7374 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7375 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7376 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7378 //===----------------------------------------------------------------------===//
7379 // VZERO - Zero YMM registers
7381 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7382 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7383 // Zero All YMM registers
7384 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7385 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7387 // Zero Upper bits of YMM registers
7388 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7389 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7392 //===----------------------------------------------------------------------===//
7393 // Half precision conversion instructions
7394 //===----------------------------------------------------------------------===//
7395 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7396 let Predicates = [HasAVX, HasF16C] in {
7397 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7398 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7399 [(set RC:$dst, (Int VR128:$src))]>,
7401 let neverHasSideEffects = 1, mayLoad = 1 in
7402 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7403 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7407 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7408 let Predicates = [HasAVX, HasF16C] in {
7409 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7410 (ins RC:$src1, i32i8imm:$src2),
7411 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7412 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7414 let neverHasSideEffects = 1, mayLoad = 1 in
7415 def mr : Ii8<0x1D, MRMDestMem, (outs x86memop:$dst),
7416 (ins RC:$src1, i32i8imm:$src2),
7417 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7422 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7423 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7424 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7425 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7427 //===----------------------------------------------------------------------===//
7428 // AVX2 Instructions
7429 //===----------------------------------------------------------------------===//
7431 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7432 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7433 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7434 X86MemOperand x86memop> {
7435 let isCommutable = 1 in
7436 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7437 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7438 !strconcat(OpcodeStr,
7439 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7440 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7442 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7443 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7444 !strconcat(OpcodeStr,
7445 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7448 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7452 let isCommutable = 0 in {
7453 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7454 VR128, memopv16i8, i128mem>;
7455 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7456 VR256, memopv32i8, i256mem>;
7459 //===----------------------------------------------------------------------===//
7460 // VPBROADCAST - Load from memory and broadcast to all elements of the
7461 // destination operand
7463 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7464 X86MemOperand x86memop, PatFrag ld_frag,
7465 Intrinsic Int128, Intrinsic Int256> {
7466 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7467 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7468 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7469 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7470 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7472 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7473 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7474 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7475 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7476 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7477 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7479 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7482 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7483 int_x86_avx2_pbroadcastb_128,
7484 int_x86_avx2_pbroadcastb_256>;
7485 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7486 int_x86_avx2_pbroadcastw_128,
7487 int_x86_avx2_pbroadcastw_256>;
7488 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7489 int_x86_avx2_pbroadcastd_128,
7490 int_x86_avx2_pbroadcastd_256>;
7491 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7492 int_x86_avx2_pbroadcastq_128,
7493 int_x86_avx2_pbroadcastq_256>;
7495 let Predicates = [HasAVX2] in {
7496 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7497 (VPBROADCASTBrm addr:$src)>;
7498 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7499 (VPBROADCASTBYrm addr:$src)>;
7500 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7501 (VPBROADCASTWrm addr:$src)>;
7502 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7503 (VPBROADCASTWYrm addr:$src)>;
7504 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7505 (VPBROADCASTDrm addr:$src)>;
7506 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7507 (VPBROADCASTDYrm addr:$src)>;
7508 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7509 (VPBROADCASTQrm addr:$src)>;
7510 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7511 (VPBROADCASTQYrm addr:$src)>;
7514 // AVX1 broadcast patterns
7515 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7516 (VBROADCASTSSYrm addr:$src)>;
7517 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7518 (VBROADCASTSDrm addr:$src)>;
7519 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7520 (VBROADCASTSSYrm addr:$src)>;
7521 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7522 (VBROADCASTSDrm addr:$src)>;
7524 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7525 (VBROADCASTSSrm addr:$src)>;
7526 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7527 (VBROADCASTSSrm addr:$src)>;
7529 //===----------------------------------------------------------------------===//
7530 // VPERM - Permute instructions
7533 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7535 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7536 (ins VR256:$src1, VR256:$src2),
7537 !strconcat(OpcodeStr,
7538 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7539 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2))]>, VEX_4V;
7540 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7541 (ins VR256:$src1, i256mem:$src2),
7542 !strconcat(OpcodeStr,
7543 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7544 [(set VR256:$dst, (Int VR256:$src1, (mem_frag addr:$src2)))]>,
7548 defm VPERMD : avx2_perm<0x36, "vpermd", memopv8i32, int_x86_avx2_permd>;
7549 let ExeDomain = SSEPackedSingle in
7550 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>;
7552 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7554 def Yrr : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7555 (ins VR256:$src1, i8imm:$src2),
7556 !strconcat(OpcodeStr,
7557 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7558 [(set VR256:$dst, (Int VR256:$src1, imm:$src2))]>, VEX;
7559 def Yrm : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7560 (ins i256mem:$src1, i8imm:$src2),
7561 !strconcat(OpcodeStr,
7562 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7563 [(set VR256:$dst, (Int (mem_frag addr:$src1), imm:$src2))]>,
7567 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, int_x86_avx2_permq>,
7569 let ExeDomain = SSEPackedDouble in
7570 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, int_x86_avx2_permpd>,
7573 //===----------------------------------------------------------------------===//
7574 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7576 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7577 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7578 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7580 (int_x86_avx2_vperm2i128 VR256:$src1, VR256:$src2, imm:$src3))]>,
7582 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7583 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7584 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7586 (int_x86_avx2_vperm2i128 VR256:$src1, (memopv4i64 addr:$src2),
7590 //===----------------------------------------------------------------------===//
7591 // VINSERTI128 - Insert packed integer values
7593 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7594 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7595 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7597 (int_x86_avx2_vinserti128 VR256:$src1, VR128:$src2, imm:$src3))]>,
7599 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7600 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7601 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7603 (int_x86_avx2_vinserti128 VR256:$src1, (memopv2i64 addr:$src2),
7604 imm:$src3))]>, VEX_4V;
7606 //===----------------------------------------------------------------------===//
7607 // VEXTRACTI128 - Extract packed integer values
7609 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7610 (ins VR256:$src1, i8imm:$src2),
7611 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7613 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7615 let neverHasSideEffects = 1, mayStore = 1 in
7616 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7617 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7618 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7620 //===----------------------------------------------------------------------===//
7621 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7623 multiclass avx2_pmovmask<string OpcodeStr,
7624 Intrinsic IntLd128, Intrinsic IntLd256,
7625 Intrinsic IntSt128, Intrinsic IntSt256> {
7626 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7627 (ins VR128:$src1, i128mem:$src2),
7628 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7629 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7630 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7631 (ins VR256:$src1, i256mem:$src2),
7632 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7633 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7634 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7635 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7636 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7637 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7638 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7639 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7640 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7641 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7644 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7645 int_x86_avx2_maskload_d,
7646 int_x86_avx2_maskload_d_256,
7647 int_x86_avx2_maskstore_d,
7648 int_x86_avx2_maskstore_d_256>;
7649 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7650 int_x86_avx2_maskload_q,
7651 int_x86_avx2_maskload_q_256,
7652 int_x86_avx2_maskstore_q,
7653 int_x86_avx2_maskstore_q_256>, VEX_W;
7656 //===----------------------------------------------------------------------===//
7657 // Variable Bit Shifts
7659 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7660 ValueType vt128, ValueType vt256> {
7661 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7662 (ins VR128:$src1, VR128:$src2),
7663 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7665 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7667 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7668 (ins VR128:$src1, i128mem:$src2),
7669 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7671 (vt128 (OpNode VR128:$src1,
7672 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7674 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7675 (ins VR256:$src1, VR256:$src2),
7676 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7678 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
7680 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7681 (ins VR256:$src1, i256mem:$src2),
7682 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7684 (vt256 (OpNode VR256:$src1,
7685 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
7689 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
7690 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
7691 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
7692 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
7693 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;