1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the University
6 // of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
24 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
25 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
26 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
27 [SDNPCommutative, SDNPAssociative]>;
28 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
33 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
34 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
35 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
36 [SDNPHasChain, SDNPOutFlag]>;
37 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
38 [SDNPHasChain, SDNPOutFlag]>;
39 def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
40 def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
41 def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
43 //===----------------------------------------------------------------------===//
44 // SSE 'Special' Instructions
45 //===----------------------------------------------------------------------===//
47 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (outs VR128:$dst), (ins),
49 [(set VR128:$dst, (v4f32 (undef)))]>,
51 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins),
53 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
54 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (outs FR64:$dst), (ins),
56 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
58 //===----------------------------------------------------------------------===//
59 // SSE Complex Patterns
60 //===----------------------------------------------------------------------===//
62 // These are 'extloads' from a scalar to the low element of a vector, zeroing
63 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
65 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
67 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
70 def ssmem : Operand<v4f32> {
71 let PrintMethod = "printf32mem";
72 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
74 def sdmem : Operand<v2f64> {
75 let PrintMethod = "printf64mem";
76 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
79 //===----------------------------------------------------------------------===//
80 // SSE pattern fragments
81 //===----------------------------------------------------------------------===//
83 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
84 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
85 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
86 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
88 // Like 'store', but always requires vector alignment.
89 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
90 (st node:$val, node:$ptr), [{
91 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
92 return !ST->isTruncatingStore() &&
93 ST->getAddressingMode() == ISD::UNINDEXED &&
94 ST->getAlignment() >= 16;
98 // Like 'load', but always requires vector alignment.
99 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
100 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
101 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
102 LD->getAddressingMode() == ISD::UNINDEXED &&
103 LD->getAlignment() >= 16;
107 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
108 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
109 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
110 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
111 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
112 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
114 // Like 'load', but uses special alignment checks suitable for use in
115 // memory operands in most SSE instructions, which are required to
116 // be naturally aligned on some targets but not on others.
117 // FIXME: Actually implement support for targets that don't require the
118 // alignment. This probably wants a subtarget predicate.
119 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
120 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
121 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
122 LD->getAddressingMode() == ISD::UNINDEXED &&
123 LD->getAlignment() >= 16;
127 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
128 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
129 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
130 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
131 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
132 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
134 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
135 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
136 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
137 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
138 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
139 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
141 def fp32imm0 : PatLeaf<(f32 fpimm), [{
142 return N->isExactlyValue(+0.0);
145 def PSxLDQ_imm : SDNodeXForm<imm, [{
146 // Transformation function: imm >> 3
147 return getI32Imm(N->getValue() >> 3);
150 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
152 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
153 return getI8Imm(X86::getShuffleSHUFImmediate(N));
156 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
158 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
159 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
162 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
164 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
165 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
168 def SSE_splat_mask : PatLeaf<(build_vector), [{
169 return X86::isSplatMask(N);
170 }], SHUFFLE_get_shuf_imm>;
172 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
173 return X86::isSplatLoMask(N);
176 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
177 return X86::isMOVHLPSMask(N);
180 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
181 return X86::isMOVHLPS_v_undef_Mask(N);
184 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
185 return X86::isMOVHPMask(N);
188 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
189 return X86::isMOVLPMask(N);
192 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
193 return X86::isMOVLMask(N);
196 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
197 return X86::isMOVSHDUPMask(N);
200 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
201 return X86::isMOVSLDUPMask(N);
204 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
205 return X86::isUNPCKLMask(N);
208 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
209 return X86::isUNPCKHMask(N);
212 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
213 return X86::isUNPCKL_v_undef_Mask(N);
216 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
217 return X86::isUNPCKH_v_undef_Mask(N);
220 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
221 return X86::isPSHUFDMask(N);
222 }], SHUFFLE_get_shuf_imm>;
224 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
225 return X86::isPSHUFHWMask(N);
226 }], SHUFFLE_get_pshufhw_imm>;
228 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
229 return X86::isPSHUFLWMask(N);
230 }], SHUFFLE_get_pshuflw_imm>;
232 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
233 return X86::isPSHUFDMask(N);
234 }], SHUFFLE_get_shuf_imm>;
236 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
237 return X86::isSHUFPMask(N);
238 }], SHUFFLE_get_shuf_imm>;
240 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
241 return X86::isSHUFPMask(N);
242 }], SHUFFLE_get_shuf_imm>;
244 //===----------------------------------------------------------------------===//
245 // SSE scalar FP Instructions
246 //===----------------------------------------------------------------------===//
248 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
249 // scheduler into a branch sequence.
250 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
251 def CMOV_FR32 : I<0, Pseudo,
252 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
253 "#CMOV_FR32 PSEUDO!",
254 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
255 def CMOV_FR64 : I<0, Pseudo,
256 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
257 "#CMOV_FR64 PSEUDO!",
258 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
259 def CMOV_V4F32 : I<0, Pseudo,
260 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
261 "#CMOV_V4F32 PSEUDO!",
263 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
264 def CMOV_V2F64 : I<0, Pseudo,
265 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
266 "#CMOV_V2F64 PSEUDO!",
268 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
269 def CMOV_V2I64 : I<0, Pseudo,
270 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
271 "#CMOV_V2I64 PSEUDO!",
273 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
276 //===----------------------------------------------------------------------===//
278 //===----------------------------------------------------------------------===//
281 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
282 "movss\t{$src, $dst|$dst, $src}", []>;
283 let isReMaterializable = 1 in
284 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
285 "movss\t{$src, $dst|$dst, $src}",
286 [(set FR32:$dst, (loadf32 addr:$src))]>;
287 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
288 "movss\t{$src, $dst|$dst, $src}",
289 [(store FR32:$src, addr:$dst)]>;
291 // Conversion instructions
292 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
293 "cvttss2si\t{$src, $dst|$dst, $src}",
294 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
295 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
296 "cvttss2si\t{$src, $dst|$dst, $src}",
297 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
298 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
299 "cvtsi2ss\t{$src, $dst|$dst, $src}",
300 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
301 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
302 "cvtsi2ss\t{$src, $dst|$dst, $src}",
303 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
305 // Match intrinsics which expect XMM operand(s).
306 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
307 "cvtss2si\t{$src, $dst|$dst, $src}",
308 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
309 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
310 "cvtss2si\t{$src, $dst|$dst, $src}",
311 [(set GR32:$dst, (int_x86_sse_cvtss2si
312 (load addr:$src)))]>;
314 // Aliases for intrinsics
315 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
316 "cvttss2si\t{$src, $dst|$dst, $src}",
318 (int_x86_sse_cvttss2si VR128:$src))]>;
319 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
320 "cvttss2si\t{$src, $dst|$dst, $src}",
322 (int_x86_sse_cvttss2si(load addr:$src)))]>;
324 let isTwoAddress = 1 in {
325 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
326 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
327 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
328 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
330 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
331 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
332 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
333 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
334 (loadi32 addr:$src2)))]>;
337 // Comparison instructions
338 let isTwoAddress = 1 in {
339 def CMPSSrr : SSI<0xC2, MRMSrcReg,
340 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
341 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
342 def CMPSSrm : SSI<0xC2, MRMSrcMem,
343 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
344 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
347 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
348 "ucomiss\t{$src2, $src1|$src1, $src2}",
349 [(X86cmp FR32:$src1, FR32:$src2)]>;
350 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
351 "ucomiss\t{$src2, $src1|$src1, $src2}",
352 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
354 // Aliases to match intrinsics which expect XMM operand(s).
355 let isTwoAddress = 1 in {
356 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
357 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
358 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
359 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
360 VR128:$src, imm:$cc))]>;
361 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
362 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
363 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
364 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
365 (load addr:$src), imm:$cc))]>;
368 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
369 "ucomiss\t{$src2, $src1|$src1, $src2}",
370 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
371 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
372 "ucomiss\t{$src2, $src1|$src1, $src2}",
373 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>;
375 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
376 "comiss\t{$src2, $src1|$src1, $src2}",
377 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
378 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
379 "comiss\t{$src2, $src1|$src1, $src2}",
380 [(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>;
382 // Aliases of packed SSE1 instructions for scalar use. These all have names that
385 // Alias instructions that map fld0 to pxor for sse.
386 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
387 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
388 Requires<[HasSSE1]>, TB, OpSize;
390 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
392 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
393 "movaps\t{$src, $dst|$dst, $src}", []>;
395 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
397 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
398 "movaps\t{$src, $dst|$dst, $src}",
399 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
401 // Alias bitwise logical operations using SSE logical ops on packed FP values.
402 let isTwoAddress = 1 in {
403 let isCommutable = 1 in {
404 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
405 "andps\t{$src2, $dst|$dst, $src2}",
406 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
407 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
408 "orps\t{$src2, $dst|$dst, $src2}",
409 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
410 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
411 "xorps\t{$src2, $dst|$dst, $src2}",
412 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
415 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
416 "andps\t{$src2, $dst|$dst, $src2}",
417 [(set FR32:$dst, (X86fand FR32:$src1,
418 (memopfsf32 addr:$src2)))]>;
419 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
420 "orps\t{$src2, $dst|$dst, $src2}",
421 [(set FR32:$dst, (X86for FR32:$src1,
422 (memopfsf32 addr:$src2)))]>;
423 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
424 "xorps\t{$src2, $dst|$dst, $src2}",
425 [(set FR32:$dst, (X86fxor FR32:$src1,
426 (memopfsf32 addr:$src2)))]>;
428 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
429 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
430 "andnps\t{$src2, $dst|$dst, $src2}", []>;
431 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
432 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
433 "andnps\t{$src2, $dst|$dst, $src2}", []>;
436 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
438 /// In addition, we also have a special variant of the scalar form here to
439 /// represent the associated intrinsic operation. This form is unlike the
440 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
441 /// and leaves the top elements undefined.
443 /// These three forms can each be reg+reg or reg+mem, so there are a total of
444 /// six "instructions".
446 let isTwoAddress = 1 in {
447 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
448 SDNode OpNode, Intrinsic F32Int,
449 bit Commutable = 0> {
450 // Scalar operation, reg+reg.
451 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
452 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
453 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
454 let isCommutable = Commutable;
457 // Scalar operation, reg+mem.
458 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
459 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
460 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
462 // Vector operation, reg+reg.
463 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
464 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
465 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
466 let isCommutable = Commutable;
469 // Vector operation, reg+mem.
470 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
471 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
472 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
474 // Intrinsic operation, reg+reg.
475 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
476 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
477 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
478 let isCommutable = Commutable;
481 // Intrinsic operation, reg+mem.
482 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
483 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
484 [(set VR128:$dst, (F32Int VR128:$src1,
485 sse_load_f32:$src2))]>;
489 // Arithmetic instructions
490 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
491 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
492 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
493 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
495 /// sse1_fp_binop_rm - Other SSE1 binops
497 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
498 /// instructions for a full-vector intrinsic form. Operations that map
499 /// onto C operators don't use this form since they just use the plain
500 /// vector form instead of having a separate vector intrinsic form.
502 /// This provides a total of eight "instructions".
504 let isTwoAddress = 1 in {
505 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
509 bit Commutable = 0> {
511 // Scalar operation, reg+reg.
512 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
513 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
514 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
515 let isCommutable = Commutable;
518 // Scalar operation, reg+mem.
519 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
520 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
521 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
523 // Vector operation, reg+reg.
524 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
525 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
526 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
527 let isCommutable = Commutable;
530 // Vector operation, reg+mem.
531 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
532 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
533 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
535 // Intrinsic operation, reg+reg.
536 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
537 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
538 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
539 let isCommutable = Commutable;
542 // Intrinsic operation, reg+mem.
543 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
544 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
545 [(set VR128:$dst, (F32Int VR128:$src1,
546 sse_load_f32:$src2))]>;
548 // Vector intrinsic operation, reg+reg.
549 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
550 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
551 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
552 let isCommutable = Commutable;
555 // Vector intrinsic operation, reg+mem.
556 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
557 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
558 [(set VR128:$dst, (V4F32Int VR128:$src1, (load addr:$src2)))]>;
562 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
563 int_x86_sse_max_ss, int_x86_sse_max_ps>;
564 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
565 int_x86_sse_min_ss, int_x86_sse_min_ps>;
567 //===----------------------------------------------------------------------===//
568 // SSE packed FP Instructions
571 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
572 "movaps\t{$src, $dst|$dst, $src}", []>;
573 let isReMaterializable = 1 in
574 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
575 "movaps\t{$src, $dst|$dst, $src}",
576 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
578 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
579 "movaps\t{$src, $dst|$dst, $src}",
580 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
582 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
583 "movups\t{$src, $dst|$dst, $src}", []>;
584 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
585 "movups\t{$src, $dst|$dst, $src}",
586 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
587 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
588 "movups\t{$src, $dst|$dst, $src}",
589 [(store (v4f32 VR128:$src), addr:$dst)]>;
591 // Intrinsic forms of MOVUPS load and store
592 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
593 "movups\t{$src, $dst|$dst, $src}",
594 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
595 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
596 "movups\t{$src, $dst|$dst, $src}",
597 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
599 let isTwoAddress = 1 in {
600 let AddedComplexity = 20 in {
601 def MOVLPSrm : PSI<0x12, MRMSrcMem,
602 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
603 "movlps\t{$src2, $dst|$dst, $src2}",
605 (v4f32 (vector_shuffle VR128:$src1,
606 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
607 MOVLP_shuffle_mask)))]>;
608 def MOVHPSrm : PSI<0x16, MRMSrcMem,
609 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
610 "movhps\t{$src2, $dst|$dst, $src2}",
612 (v4f32 (vector_shuffle VR128:$src1,
613 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
614 MOVHP_shuffle_mask)))]>;
618 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
619 "movlps\t{$src, $dst|$dst, $src}",
620 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
621 (iPTR 0))), addr:$dst)]>;
623 // v2f64 extract element 1 is always custom lowered to unpack high to low
624 // and extract element 0 so the non-store version isn't too horrible.
625 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
626 "movhps\t{$src, $dst|$dst, $src}",
627 [(store (f64 (vector_extract
628 (v2f64 (vector_shuffle
629 (bc_v2f64 (v4f32 VR128:$src)), (undef),
630 UNPCKH_shuffle_mask)), (iPTR 0))),
633 let isTwoAddress = 1 in {
634 let AddedComplexity = 15 in {
635 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
636 "movlhps\t{$src2, $dst|$dst, $src2}",
638 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
639 MOVHP_shuffle_mask)))]>;
641 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
642 "movhlps\t{$src2, $dst|$dst, $src2}",
644 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
645 MOVHLPS_shuffle_mask)))]>;
653 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
655 /// In addition, we also have a special variant of the scalar form here to
656 /// represent the associated intrinsic operation. This form is unlike the
657 /// plain scalar form, in that it takes an entire vector (instead of a
658 /// scalar) and leaves the top elements undefined.
660 /// And, we have a special variant form for a full-vector intrinsic form.
662 /// These four forms can each have a reg or a mem operand, so there are a
663 /// total of eight "instructions".
665 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
669 bit Commutable = 0> {
670 // Scalar operation, reg.
671 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
672 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
673 [(set FR32:$dst, (OpNode FR32:$src))]> {
674 let isCommutable = Commutable;
677 // Scalar operation, mem.
678 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
679 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
680 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
682 // Vector operation, reg.
683 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
684 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
685 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
686 let isCommutable = Commutable;
689 // Vector operation, mem.
690 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
691 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
692 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
694 // Intrinsic operation, reg.
695 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
696 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
697 [(set VR128:$dst, (F32Int VR128:$src))]> {
698 let isCommutable = Commutable;
701 // Intrinsic operation, mem.
702 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
703 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
704 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
706 // Vector intrinsic operation, reg
707 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
708 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
709 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
710 let isCommutable = Commutable;
713 // Vector intrinsic operation, mem
714 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
715 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
716 [(set VR128:$dst, (V4F32Int (load addr:$src)))]>;
720 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
721 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
723 // Reciprocal approximations. Note that these typically require refinement
724 // in order to obtain suitable precision.
725 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
726 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
727 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
728 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
731 let isTwoAddress = 1 in {
732 let isCommutable = 1 in {
733 def ANDPSrr : PSI<0x54, MRMSrcReg,
734 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
735 "andps\t{$src2, $dst|$dst, $src2}",
736 [(set VR128:$dst, (v2i64
737 (and VR128:$src1, VR128:$src2)))]>;
738 def ORPSrr : PSI<0x56, MRMSrcReg,
739 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
740 "orps\t{$src2, $dst|$dst, $src2}",
741 [(set VR128:$dst, (v2i64
742 (or VR128:$src1, VR128:$src2)))]>;
743 def XORPSrr : PSI<0x57, MRMSrcReg,
744 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
745 "xorps\t{$src2, $dst|$dst, $src2}",
746 [(set VR128:$dst, (v2i64
747 (xor VR128:$src1, VR128:$src2)))]>;
750 def ANDPSrm : PSI<0x54, MRMSrcMem,
751 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
752 "andps\t{$src2, $dst|$dst, $src2}",
753 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
754 (memopv2i64 addr:$src2)))]>;
755 def ORPSrm : PSI<0x56, MRMSrcMem,
756 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
757 "orps\t{$src2, $dst|$dst, $src2}",
758 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
759 (memopv2i64 addr:$src2)))]>;
760 def XORPSrm : PSI<0x57, MRMSrcMem,
761 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
762 "xorps\t{$src2, $dst|$dst, $src2}",
763 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
764 (memopv2i64 addr:$src2)))]>;
765 def ANDNPSrr : PSI<0x55, MRMSrcReg,
766 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
767 "andnps\t{$src2, $dst|$dst, $src2}",
769 (v2i64 (and (xor VR128:$src1,
770 (bc_v2i64 (v4i32 immAllOnesV))),
772 def ANDNPSrm : PSI<0x55, MRMSrcMem,
773 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
774 "andnps\t{$src2, $dst|$dst, $src2}",
776 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
777 (bc_v2i64 (v4i32 immAllOnesV))),
778 (memopv2i64 addr:$src2))))]>;
781 let isTwoAddress = 1 in {
782 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
783 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
784 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
785 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
786 VR128:$src, imm:$cc))]>;
787 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
788 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
789 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
790 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
791 (load addr:$src), imm:$cc))]>;
794 // Shuffle and unpack instructions
795 let isTwoAddress = 1 in {
796 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
797 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
798 (outs VR128:$dst), (ins VR128:$src1,
799 VR128:$src2, i32i8imm:$src3),
800 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
802 (v4f32 (vector_shuffle
803 VR128:$src1, VR128:$src2,
804 SHUFP_shuffle_mask:$src3)))]>;
805 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
806 (outs VR128:$dst), (ins VR128:$src1,
807 f128mem:$src2, i32i8imm:$src3),
808 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
810 (v4f32 (vector_shuffle
811 VR128:$src1, (memopv4f32 addr:$src2),
812 SHUFP_shuffle_mask:$src3)))]>;
814 let AddedComplexity = 10 in {
815 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
816 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
817 "unpckhps\t{$src2, $dst|$dst, $src2}",
819 (v4f32 (vector_shuffle
820 VR128:$src1, VR128:$src2,
821 UNPCKH_shuffle_mask)))]>;
822 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
823 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
824 "unpckhps\t{$src2, $dst|$dst, $src2}",
826 (v4f32 (vector_shuffle
827 VR128:$src1, (memopv4f32 addr:$src2),
828 UNPCKH_shuffle_mask)))]>;
830 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
831 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
832 "unpcklps\t{$src2, $dst|$dst, $src2}",
834 (v4f32 (vector_shuffle
835 VR128:$src1, VR128:$src2,
836 UNPCKL_shuffle_mask)))]>;
837 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
838 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
839 "unpcklps\t{$src2, $dst|$dst, $src2}",
841 (v4f32 (vector_shuffle
842 VR128:$src1, (memopv4f32 addr:$src2),
843 UNPCKL_shuffle_mask)))]>;
848 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
849 "movmskps\t{$src, $dst|$dst, $src}",
850 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
851 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
852 "movmskpd\t{$src, $dst|$dst, $src}",
853 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
855 // Prefetching loads.
856 // TODO: no intrinsics for these?
857 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src), "prefetcht0\t$src", []>;
858 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src), "prefetcht1\t$src", []>;
859 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src), "prefetcht2\t$src", []>;
860 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src), "prefetchnta\t$src", []>;
862 // Non-temporal stores
863 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
864 "movntps\t{$src, $dst|$dst, $src}",
865 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
867 // Load, store, and memory fence
868 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
871 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
872 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
873 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
874 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
876 // Alias instructions that map zero vector to pxor / xorp* for sse.
877 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
878 let isReMaterializable = 1 in
879 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
881 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
883 // FR32 to 128-bit vector conversion.
884 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
885 "movss\t{$src, $dst|$dst, $src}",
887 (v4f32 (scalar_to_vector FR32:$src)))]>;
888 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
889 "movss\t{$src, $dst|$dst, $src}",
891 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
893 // FIXME: may not be able to eliminate this movss with coalescing the src and
894 // dest register classes are different. We really want to write this pattern
896 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
898 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
899 "movss\t{$src, $dst|$dst, $src}",
900 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
902 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
903 "movss\t{$src, $dst|$dst, $src}",
904 [(store (f32 (vector_extract (v4f32 VR128:$src),
905 (iPTR 0))), addr:$dst)]>;
908 // Move to lower bits of a VR128, leaving upper bits alone.
909 // Three operand (but two address) aliases.
910 let isTwoAddress = 1 in {
911 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
912 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
913 "movss\t{$src2, $dst|$dst, $src2}", []>;
915 let AddedComplexity = 15 in
916 def MOVLPSrr : SSI<0x10, MRMSrcReg,
917 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
918 "movss\t{$src2, $dst|$dst, $src2}",
920 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
921 MOVL_shuffle_mask)))]>;
924 // Move to lower bits of a VR128 and zeroing upper bits.
925 // Loading from memory automatically zeroing upper bits.
926 let AddedComplexity = 20 in
927 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
928 "movss\t{$src, $dst|$dst, $src}",
929 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
930 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
931 MOVL_shuffle_mask)))]>;
934 //===----------------------------------------------------------------------===//
936 //===----------------------------------------------------------------------===//
939 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
940 "movsd\t{$src, $dst|$dst, $src}", []>;
941 let isReMaterializable = 1 in
942 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
943 "movsd\t{$src, $dst|$dst, $src}",
944 [(set FR64:$dst, (loadf64 addr:$src))]>;
945 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
946 "movsd\t{$src, $dst|$dst, $src}",
947 [(store FR64:$src, addr:$dst)]>;
949 // Conversion instructions
950 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
951 "cvttsd2si\t{$src, $dst|$dst, $src}",
952 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
953 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
954 "cvttsd2si\t{$src, $dst|$dst, $src}",
955 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
956 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
957 "cvtsd2ss\t{$src, $dst|$dst, $src}",
958 [(set FR32:$dst, (fround FR64:$src))]>;
959 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
960 "cvtsd2ss\t{$src, $dst|$dst, $src}",
961 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
962 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
963 "cvtsi2sd\t{$src, $dst|$dst, $src}",
964 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
965 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
966 "cvtsi2sd\t{$src, $dst|$dst, $src}",
967 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
969 // SSE2 instructions with XS prefix
970 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
971 "cvtss2sd\t{$src, $dst|$dst, $src}",
972 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
974 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
975 "cvtss2sd\t{$src, $dst|$dst, $src}",
976 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
979 // Match intrinsics which expect XMM operand(s).
980 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
981 "cvtsd2si\t{$src, $dst|$dst, $src}",
982 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
983 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
984 "cvtsd2si\t{$src, $dst|$dst, $src}",
985 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
986 (load addr:$src)))]>;
988 // Aliases for intrinsics
989 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
990 "cvttsd2si\t{$src, $dst|$dst, $src}",
992 (int_x86_sse2_cvttsd2si VR128:$src))]>;
993 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
994 "cvttsd2si\t{$src, $dst|$dst, $src}",
995 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
996 (load addr:$src)))]>;
998 // Comparison instructions
999 let isTwoAddress = 1 in {
1000 def CMPSDrr : SDI<0xC2, MRMSrcReg,
1001 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1002 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1003 def CMPSDrm : SDI<0xC2, MRMSrcMem,
1004 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1005 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1008 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1009 "ucomisd\t{$src2, $src1|$src1, $src2}",
1010 [(X86cmp FR64:$src1, FR64:$src2)]>;
1011 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1012 "ucomisd\t{$src2, $src1|$src1, $src2}",
1013 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
1015 // Aliases to match intrinsics which expect XMM operand(s).
1016 let isTwoAddress = 1 in {
1017 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
1018 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1019 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1020 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1021 VR128:$src, imm:$cc))]>;
1022 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
1023 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1024 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1025 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1026 (load addr:$src), imm:$cc))]>;
1029 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1030 "ucomisd\t{$src2, $src1|$src1, $src2}",
1031 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
1032 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1033 "ucomisd\t{$src2, $src1|$src1, $src2}",
1034 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>;
1036 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1037 "comisd\t{$src2, $src1|$src1, $src2}",
1038 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
1039 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1040 "comisd\t{$src2, $src1|$src1, $src2}",
1041 [(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
1043 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1046 // Alias instructions that map fld0 to pxor for sse.
1047 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1048 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1049 Requires<[HasSSE2]>, TB, OpSize;
1051 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1053 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1054 "movapd\t{$src, $dst|$dst, $src}", []>;
1056 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1058 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1059 "movapd\t{$src, $dst|$dst, $src}",
1060 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1062 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1063 let isTwoAddress = 1 in {
1064 let isCommutable = 1 in {
1065 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1066 "andpd\t{$src2, $dst|$dst, $src2}",
1067 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1068 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1069 "orpd\t{$src2, $dst|$dst, $src2}",
1070 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1071 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1072 "xorpd\t{$src2, $dst|$dst, $src2}",
1073 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1076 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1077 "andpd\t{$src2, $dst|$dst, $src2}",
1078 [(set FR64:$dst, (X86fand FR64:$src1,
1079 (memopfsf64 addr:$src2)))]>;
1080 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1081 "orpd\t{$src2, $dst|$dst, $src2}",
1082 [(set FR64:$dst, (X86for FR64:$src1,
1083 (memopfsf64 addr:$src2)))]>;
1084 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1085 "xorpd\t{$src2, $dst|$dst, $src2}",
1086 [(set FR64:$dst, (X86fxor FR64:$src1,
1087 (memopfsf64 addr:$src2)))]>;
1089 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1090 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1091 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1092 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1093 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1094 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1097 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1099 /// In addition, we also have a special variant of the scalar form here to
1100 /// represent the associated intrinsic operation. This form is unlike the
1101 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1102 /// and leaves the top elements undefined.
1104 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1105 /// six "instructions".
1107 let isTwoAddress = 1 in {
1108 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1109 SDNode OpNode, Intrinsic F64Int,
1110 bit Commutable = 0> {
1111 // Scalar operation, reg+reg.
1112 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1113 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1114 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1115 let isCommutable = Commutable;
1118 // Scalar operation, reg+mem.
1119 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1120 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1121 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1123 // Vector operation, reg+reg.
1124 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1125 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1126 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1127 let isCommutable = Commutable;
1130 // Vector operation, reg+mem.
1131 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1132 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1133 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1135 // Intrinsic operation, reg+reg.
1136 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1137 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1138 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1139 let isCommutable = Commutable;
1142 // Intrinsic operation, reg+mem.
1143 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1144 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1145 [(set VR128:$dst, (F64Int VR128:$src1,
1146 sse_load_f64:$src2))]>;
1150 // Arithmetic instructions
1151 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1152 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1153 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1154 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1156 /// sse2_fp_binop_rm - Other SSE2 binops
1158 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1159 /// instructions for a full-vector intrinsic form. Operations that map
1160 /// onto C operators don't use this form since they just use the plain
1161 /// vector form instead of having a separate vector intrinsic form.
1163 /// This provides a total of eight "instructions".
1165 let isTwoAddress = 1 in {
1166 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1170 bit Commutable = 0> {
1172 // Scalar operation, reg+reg.
1173 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1174 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1175 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1176 let isCommutable = Commutable;
1179 // Scalar operation, reg+mem.
1180 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1181 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1182 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1184 // Vector operation, reg+reg.
1185 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1186 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1187 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1188 let isCommutable = Commutable;
1191 // Vector operation, reg+mem.
1192 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1193 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1194 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1196 // Intrinsic operation, reg+reg.
1197 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1198 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1199 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1200 let isCommutable = Commutable;
1203 // Intrinsic operation, reg+mem.
1204 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1205 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1206 [(set VR128:$dst, (F64Int VR128:$src1,
1207 sse_load_f64:$src2))]>;
1209 // Vector intrinsic operation, reg+reg.
1210 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1211 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1212 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1213 let isCommutable = Commutable;
1216 // Vector intrinsic operation, reg+mem.
1217 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1218 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1219 [(set VR128:$dst, (V2F64Int VR128:$src1, (load addr:$src2)))]>;
1223 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1224 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1225 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1226 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1228 //===----------------------------------------------------------------------===//
1229 // SSE packed FP Instructions
1231 // Move Instructions
1232 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1233 "movapd\t{$src, $dst|$dst, $src}", []>;
1234 let isReMaterializable = 1 in
1235 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1236 "movapd\t{$src, $dst|$dst, $src}",
1237 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1239 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1240 "movapd\t{$src, $dst|$dst, $src}",
1241 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1243 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1244 "movupd\t{$src, $dst|$dst, $src}", []>;
1245 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1246 "movupd\t{$src, $dst|$dst, $src}",
1247 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1248 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1249 "movupd\t{$src, $dst|$dst, $src}",
1250 [(store (v2f64 VR128:$src), addr:$dst)]>;
1252 // Intrinsic forms of MOVUPD load and store
1253 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1254 "movupd\t{$src, $dst|$dst, $src}",
1255 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1256 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1257 "movupd\t{$src, $dst|$dst, $src}",
1258 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1260 let isTwoAddress = 1 in {
1261 let AddedComplexity = 20 in {
1262 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1263 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1264 "movlpd\t{$src2, $dst|$dst, $src2}",
1266 (v2f64 (vector_shuffle VR128:$src1,
1267 (scalar_to_vector (loadf64 addr:$src2)),
1268 MOVLP_shuffle_mask)))]>;
1269 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1270 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1271 "movhpd\t{$src2, $dst|$dst, $src2}",
1273 (v2f64 (vector_shuffle VR128:$src1,
1274 (scalar_to_vector (loadf64 addr:$src2)),
1275 MOVHP_shuffle_mask)))]>;
1276 } // AddedComplexity
1279 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1280 "movlpd\t{$src, $dst|$dst, $src}",
1281 [(store (f64 (vector_extract (v2f64 VR128:$src),
1282 (iPTR 0))), addr:$dst)]>;
1284 // v2f64 extract element 1 is always custom lowered to unpack high to low
1285 // and extract element 0 so the non-store version isn't too horrible.
1286 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1287 "movhpd\t{$src, $dst|$dst, $src}",
1288 [(store (f64 (vector_extract
1289 (v2f64 (vector_shuffle VR128:$src, (undef),
1290 UNPCKH_shuffle_mask)), (iPTR 0))),
1293 // SSE2 instructions without OpSize prefix
1294 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1295 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1296 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1297 TB, Requires<[HasSSE2]>;
1298 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1299 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1300 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1301 (bitconvert (memopv2i64 addr:$src))))]>,
1302 TB, Requires<[HasSSE2]>;
1304 // SSE2 instructions with XS prefix
1305 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1306 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1307 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1308 XS, Requires<[HasSSE2]>;
1309 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1310 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1311 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1312 (bitconvert (memopv2i64 addr:$src))))]>,
1313 XS, Requires<[HasSSE2]>;
1315 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1316 "cvtps2dq\t{$src, $dst|$dst, $src}",
1317 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1318 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1319 "cvtps2dq\t{$src, $dst|$dst, $src}",
1320 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1321 (load addr:$src)))]>;
1322 // SSE2 packed instructions with XS prefix
1323 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1324 "cvttps2dq\t{$src, $dst|$dst, $src}",
1325 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1326 XS, Requires<[HasSSE2]>;
1327 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1328 "cvttps2dq\t{$src, $dst|$dst, $src}",
1329 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1330 (load addr:$src)))]>,
1331 XS, Requires<[HasSSE2]>;
1333 // SSE2 packed instructions with XD prefix
1334 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1335 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1336 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1337 XD, Requires<[HasSSE2]>;
1338 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1339 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1340 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1341 (load addr:$src)))]>,
1342 XD, Requires<[HasSSE2]>;
1344 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1345 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1346 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1347 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1348 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1349 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1350 (load addr:$src)))]>;
1352 // SSE2 instructions without OpSize prefix
1353 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1354 "cvtps2pd\t{$src, $dst|$dst, $src}",
1355 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1356 TB, Requires<[HasSSE2]>;
1357 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f64mem:$src),
1358 "cvtps2pd\t{$src, $dst|$dst, $src}",
1359 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1360 (load addr:$src)))]>,
1361 TB, Requires<[HasSSE2]>;
1363 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1364 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1365 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1366 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f128mem:$src),
1367 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1368 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1369 (load addr:$src)))]>;
1371 // Match intrinsics which expect XMM operand(s).
1372 // Aliases for intrinsics
1373 let isTwoAddress = 1 in {
1374 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1375 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1376 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1377 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1379 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1380 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1381 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1382 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1383 (loadi32 addr:$src2)))]>;
1384 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1385 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1386 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1387 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1389 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1390 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1391 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1392 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1393 (load addr:$src2)))]>;
1394 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1395 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1396 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1397 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1398 VR128:$src2))]>, XS,
1399 Requires<[HasSSE2]>;
1400 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1401 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1402 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1403 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1404 (load addr:$src2)))]>, XS,
1405 Requires<[HasSSE2]>;
1410 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1412 /// In addition, we also have a special variant of the scalar form here to
1413 /// represent the associated intrinsic operation. This form is unlike the
1414 /// plain scalar form, in that it takes an entire vector (instead of a
1415 /// scalar) and leaves the top elements undefined.
1417 /// And, we have a special variant form for a full-vector intrinsic form.
1419 /// These four forms can each have a reg or a mem operand, so there are a
1420 /// total of eight "instructions".
1422 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1426 bit Commutable = 0> {
1427 // Scalar operation, reg.
1428 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1429 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1430 [(set FR64:$dst, (OpNode FR64:$src))]> {
1431 let isCommutable = Commutable;
1434 // Scalar operation, mem.
1435 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1436 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1437 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1439 // Vector operation, reg.
1440 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1441 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1442 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1443 let isCommutable = Commutable;
1446 // Vector operation, mem.
1447 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1448 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1449 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1451 // Intrinsic operation, reg.
1452 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1453 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1454 [(set VR128:$dst, (F64Int VR128:$src))]> {
1455 let isCommutable = Commutable;
1458 // Intrinsic operation, mem.
1459 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1460 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1461 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1463 // Vector intrinsic operation, reg
1464 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1465 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1466 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1467 let isCommutable = Commutable;
1470 // Vector intrinsic operation, mem
1471 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1472 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1473 [(set VR128:$dst, (V2F64Int (load addr:$src)))]>;
1477 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1478 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1480 // There is no f64 version of the reciprocal approximation instructions.
1483 let isTwoAddress = 1 in {
1484 let isCommutable = 1 in {
1485 def ANDPDrr : PDI<0x54, MRMSrcReg,
1486 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1487 "andpd\t{$src2, $dst|$dst, $src2}",
1489 (and (bc_v2i64 (v2f64 VR128:$src1)),
1490 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1491 def ORPDrr : PDI<0x56, MRMSrcReg,
1492 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1493 "orpd\t{$src2, $dst|$dst, $src2}",
1495 (or (bc_v2i64 (v2f64 VR128:$src1)),
1496 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1497 def XORPDrr : PDI<0x57, MRMSrcReg,
1498 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1499 "xorpd\t{$src2, $dst|$dst, $src2}",
1501 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1502 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1505 def ANDPDrm : PDI<0x54, MRMSrcMem,
1506 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1507 "andpd\t{$src2, $dst|$dst, $src2}",
1509 (and (bc_v2i64 (v2f64 VR128:$src1)),
1510 (memopv2i64 addr:$src2)))]>;
1511 def ORPDrm : PDI<0x56, MRMSrcMem,
1512 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1513 "orpd\t{$src2, $dst|$dst, $src2}",
1515 (or (bc_v2i64 (v2f64 VR128:$src1)),
1516 (memopv2i64 addr:$src2)))]>;
1517 def XORPDrm : PDI<0x57, MRMSrcMem,
1518 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1519 "xorpd\t{$src2, $dst|$dst, $src2}",
1521 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1522 (memopv2i64 addr:$src2)))]>;
1523 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1524 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1525 "andnpd\t{$src2, $dst|$dst, $src2}",
1527 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1528 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1529 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1530 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1531 "andnpd\t{$src2, $dst|$dst, $src2}",
1533 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1534 (memopv2i64 addr:$src2)))]>;
1537 let isTwoAddress = 1 in {
1538 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1539 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1540 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1541 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1542 VR128:$src, imm:$cc))]>;
1543 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1544 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1545 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1546 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1547 (load addr:$src), imm:$cc))]>;
1550 // Shuffle and unpack instructions
1551 let isTwoAddress = 1 in {
1552 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1553 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1554 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1555 [(set VR128:$dst, (v2f64 (vector_shuffle
1556 VR128:$src1, VR128:$src2,
1557 SHUFP_shuffle_mask:$src3)))]>;
1558 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1559 (outs VR128:$dst), (ins VR128:$src1,
1560 f128mem:$src2, i8imm:$src3),
1561 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1563 (v2f64 (vector_shuffle
1564 VR128:$src1, (memopv2f64 addr:$src2),
1565 SHUFP_shuffle_mask:$src3)))]>;
1567 let AddedComplexity = 10 in {
1568 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1569 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1570 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1572 (v2f64 (vector_shuffle
1573 VR128:$src1, VR128:$src2,
1574 UNPCKH_shuffle_mask)))]>;
1575 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1576 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1577 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1579 (v2f64 (vector_shuffle
1580 VR128:$src1, (memopv2f64 addr:$src2),
1581 UNPCKH_shuffle_mask)))]>;
1583 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1584 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1585 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1587 (v2f64 (vector_shuffle
1588 VR128:$src1, VR128:$src2,
1589 UNPCKL_shuffle_mask)))]>;
1590 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1591 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1592 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1594 (v2f64 (vector_shuffle
1595 VR128:$src1, (memopv2f64 addr:$src2),
1596 UNPCKL_shuffle_mask)))]>;
1597 } // AddedComplexity
1601 //===----------------------------------------------------------------------===//
1602 // SSE integer instructions
1604 // Move Instructions
1605 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1606 "movdqa\t{$src, $dst|$dst, $src}", []>;
1607 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1608 "movdqa\t{$src, $dst|$dst, $src}",
1609 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1610 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1611 "movdqa\t{$src, $dst|$dst, $src}",
1612 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1613 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1614 "movdqu\t{$src, $dst|$dst, $src}",
1615 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1616 XS, Requires<[HasSSE2]>;
1617 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1618 "movdqu\t{$src, $dst|$dst, $src}",
1619 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1620 XS, Requires<[HasSSE2]>;
1622 // Intrinsic forms of MOVDQU load and store
1623 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1624 "movdqu\t{$src, $dst|$dst, $src}",
1625 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1626 XS, Requires<[HasSSE2]>;
1627 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1628 "movdqu\t{$src, $dst|$dst, $src}",
1629 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1630 XS, Requires<[HasSSE2]>;
1632 let isTwoAddress = 1 in {
1634 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1635 bit Commutable = 0> {
1636 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1637 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1638 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1639 let isCommutable = Commutable;
1641 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1642 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1643 [(set VR128:$dst, (IntId VR128:$src1,
1644 (bitconvert (memopv2i64 addr:$src2))))]>;
1647 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1648 string OpcodeStr, Intrinsic IntId> {
1649 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1650 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1651 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1652 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1653 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1654 [(set VR128:$dst, (IntId VR128:$src1,
1655 (bitconvert (memopv2i64 addr:$src2))))]>;
1656 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1657 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1658 [(set VR128:$dst, (IntId VR128:$src1,
1659 (scalar_to_vector (i32 imm:$src2))))]>;
1663 /// PDI_binop_rm - Simple SSE2 binary operator.
1664 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1665 ValueType OpVT, bit Commutable = 0> {
1666 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1667 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1668 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1669 let isCommutable = Commutable;
1671 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1672 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1673 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1674 (bitconvert (memopv2i64 addr:$src2)))))]>;
1677 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1679 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1680 /// to collapse (bitconvert VT to VT) into its operand.
1682 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1683 bit Commutable = 0> {
1684 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1685 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1686 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1687 let isCommutable = Commutable;
1689 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1690 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1691 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1696 // 128-bit Integer Arithmetic
1698 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1699 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1700 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1701 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1703 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1704 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1705 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1706 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1708 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1709 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1710 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1711 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1713 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1714 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1715 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1716 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1718 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1720 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1721 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1722 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1724 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1726 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1727 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1730 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1731 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1732 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1733 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1734 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1737 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1738 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1739 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1741 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1742 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1743 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1745 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1746 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1747 // PSRAQ doesn't exist in SSE[1-3].
1749 // 128-bit logical shifts.
1750 let isTwoAddress = 1 in {
1751 def PSLLDQri : PDIi8<0x73, MRM7r,
1752 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1753 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1754 def PSRLDQri : PDIi8<0x73, MRM3r,
1755 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1756 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1757 // PSRADQri doesn't exist in SSE[1-3].
1760 let Predicates = [HasSSE2] in {
1761 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1762 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1763 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1764 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1765 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1766 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1770 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1771 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1772 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1774 let isTwoAddress = 1 in {
1775 def PANDNrr : PDI<0xDF, MRMSrcReg,
1776 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1777 "pandn\t{$src2, $dst|$dst, $src2}",
1778 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1781 def PANDNrm : PDI<0xDF, MRMSrcMem,
1782 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1783 "pandn\t{$src2, $dst|$dst, $src2}",
1784 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1785 (memopv2i64 addr:$src2))))]>;
1788 // SSE2 Integer comparison
1789 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1790 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1791 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1792 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1793 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1794 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1796 // Pack instructions
1797 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1798 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1799 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1801 // Shuffle and unpack instructions
1802 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1803 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1804 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1805 [(set VR128:$dst, (v4i32 (vector_shuffle
1806 VR128:$src1, (undef),
1807 PSHUFD_shuffle_mask:$src2)))]>;
1808 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1809 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1810 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1811 [(set VR128:$dst, (v4i32 (vector_shuffle
1812 (bc_v4i32(memopv2i64 addr:$src1)),
1814 PSHUFD_shuffle_mask:$src2)))]>;
1816 // SSE2 with ImmT == Imm8 and XS prefix.
1817 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1818 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1819 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1820 [(set VR128:$dst, (v8i16 (vector_shuffle
1821 VR128:$src1, (undef),
1822 PSHUFHW_shuffle_mask:$src2)))]>,
1823 XS, Requires<[HasSSE2]>;
1824 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1825 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1826 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1827 [(set VR128:$dst, (v8i16 (vector_shuffle
1828 (bc_v8i16 (memopv2i64 addr:$src1)),
1830 PSHUFHW_shuffle_mask:$src2)))]>,
1831 XS, Requires<[HasSSE2]>;
1833 // SSE2 with ImmT == Imm8 and XD prefix.
1834 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1835 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1836 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1837 [(set VR128:$dst, (v8i16 (vector_shuffle
1838 VR128:$src1, (undef),
1839 PSHUFLW_shuffle_mask:$src2)))]>,
1840 XD, Requires<[HasSSE2]>;
1841 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1842 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
1843 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1844 [(set VR128:$dst, (v8i16 (vector_shuffle
1845 (bc_v8i16 (memopv2i64 addr:$src1)),
1847 PSHUFLW_shuffle_mask:$src2)))]>,
1848 XD, Requires<[HasSSE2]>;
1851 let isTwoAddress = 1 in {
1852 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1853 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1854 "punpcklbw\t{$src2, $dst|$dst, $src2}",
1856 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1857 UNPCKL_shuffle_mask)))]>;
1858 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1859 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1860 "punpcklbw\t{$src2, $dst|$dst, $src2}",
1862 (v16i8 (vector_shuffle VR128:$src1,
1863 (bc_v16i8 (memopv2i64 addr:$src2)),
1864 UNPCKL_shuffle_mask)))]>;
1865 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 "punpcklwd\t{$src2, $dst|$dst, $src2}",
1869 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1870 UNPCKL_shuffle_mask)))]>;
1871 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1872 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1873 "punpcklwd\t{$src2, $dst|$dst, $src2}",
1875 (v8i16 (vector_shuffle VR128:$src1,
1876 (bc_v8i16 (memopv2i64 addr:$src2)),
1877 UNPCKL_shuffle_mask)))]>;
1878 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1879 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1880 "punpckldq\t{$src2, $dst|$dst, $src2}",
1882 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1883 UNPCKL_shuffle_mask)))]>;
1884 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1885 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1886 "punpckldq\t{$src2, $dst|$dst, $src2}",
1888 (v4i32 (vector_shuffle VR128:$src1,
1889 (bc_v4i32 (memopv2i64 addr:$src2)),
1890 UNPCKL_shuffle_mask)))]>;
1891 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1892 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1893 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
1895 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1896 UNPCKL_shuffle_mask)))]>;
1897 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1898 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1899 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
1901 (v2i64 (vector_shuffle VR128:$src1,
1902 (memopv2i64 addr:$src2),
1903 UNPCKL_shuffle_mask)))]>;
1905 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1906 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1907 "punpckhbw\t{$src2, $dst|$dst, $src2}",
1909 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1910 UNPCKH_shuffle_mask)))]>;
1911 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1912 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1913 "punpckhbw\t{$src2, $dst|$dst, $src2}",
1915 (v16i8 (vector_shuffle VR128:$src1,
1916 (bc_v16i8 (memopv2i64 addr:$src2)),
1917 UNPCKH_shuffle_mask)))]>;
1918 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1919 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1920 "punpckhwd\t{$src2, $dst|$dst, $src2}",
1922 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1923 UNPCKH_shuffle_mask)))]>;
1924 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1925 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1926 "punpckhwd\t{$src2, $dst|$dst, $src2}",
1928 (v8i16 (vector_shuffle VR128:$src1,
1929 (bc_v8i16 (memopv2i64 addr:$src2)),
1930 UNPCKH_shuffle_mask)))]>;
1931 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1932 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1933 "punpckhdq\t{$src2, $dst|$dst, $src2}",
1935 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1936 UNPCKH_shuffle_mask)))]>;
1937 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1938 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1939 "punpckhdq\t{$src2, $dst|$dst, $src2}",
1941 (v4i32 (vector_shuffle VR128:$src1,
1942 (bc_v4i32 (memopv2i64 addr:$src2)),
1943 UNPCKH_shuffle_mask)))]>;
1944 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1945 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1946 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
1948 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1949 UNPCKH_shuffle_mask)))]>;
1950 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1951 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1952 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
1954 (v2i64 (vector_shuffle VR128:$src1,
1955 (memopv2i64 addr:$src2),
1956 UNPCKH_shuffle_mask)))]>;
1960 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
1961 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
1962 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1963 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
1964 (iPTR imm:$src2)))]>;
1965 let isTwoAddress = 1 in {
1966 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
1967 (outs VR128:$dst), (ins VR128:$src1,
1968 GR32:$src2, i32i8imm:$src3),
1969 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1971 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1972 GR32:$src2, (iPTR imm:$src3))))]>;
1973 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
1974 (outs VR128:$dst), (ins VR128:$src1,
1975 i16mem:$src2, i32i8imm:$src3),
1976 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1978 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1979 (i32 (anyext (loadi16 addr:$src2))),
1980 (iPTR imm:$src3))))]>;
1984 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1985 "pmovmskb\t{$src, $dst|$dst, $src}",
1986 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1988 // Conditional store
1989 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
1990 "maskmovdqu\t{$mask, $src|$src, $mask}",
1991 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1994 // Non-temporal stores
1995 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1996 "movntpd\t{$src, $dst|$dst, $src}",
1997 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1998 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1999 "movntdq\t{$src, $dst|$dst, $src}",
2000 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2001 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2002 "movnti\t{$src, $dst|$dst, $src}",
2003 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2004 TB, Requires<[HasSSE2]>;
2007 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2008 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2009 TB, Requires<[HasSSE2]>;
2011 // Load, store, and memory fence
2012 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2013 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2014 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2015 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2018 // Alias instructions that map zero vector to pxor / xorp* for sse.
2019 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2020 let isReMaterializable = 1 in
2021 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2022 "pcmpeqd\t$dst, $dst",
2023 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
2025 // FR64 to 128-bit vector conversion.
2026 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2027 "movsd\t{$src, $dst|$dst, $src}",
2029 (v2f64 (scalar_to_vector FR64:$src)))]>;
2030 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2031 "movsd\t{$src, $dst|$dst, $src}",
2033 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2035 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2036 "movd\t{$src, $dst|$dst, $src}",
2038 (v4i32 (scalar_to_vector GR32:$src)))]>;
2039 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2040 "movd\t{$src, $dst|$dst, $src}",
2042 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2044 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2045 "movd\t{$src, $dst|$dst, $src}",
2046 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2048 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2049 "movd\t{$src, $dst|$dst, $src}",
2050 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2052 // SSE2 instructions with XS prefix
2053 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2054 "movq\t{$src, $dst|$dst, $src}",
2056 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2057 Requires<[HasSSE2]>;
2058 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2059 "movq\t{$src, $dst|$dst, $src}",
2060 [(store (i64 (vector_extract (v2i64 VR128:$src),
2061 (iPTR 0))), addr:$dst)]>;
2063 // FIXME: may not be able to eliminate this movss with coalescing the src and
2064 // dest register classes are different. We really want to write this pattern
2066 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2067 // (f32 FR32:$src)>;
2068 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2069 "movsd\t{$src, $dst|$dst, $src}",
2070 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2072 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2073 "movsd\t{$src, $dst|$dst, $src}",
2074 [(store (f64 (vector_extract (v2f64 VR128:$src),
2075 (iPTR 0))), addr:$dst)]>;
2076 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2077 "movd\t{$src, $dst|$dst, $src}",
2078 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2080 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2081 "movd\t{$src, $dst|$dst, $src}",
2082 [(store (i32 (vector_extract (v4i32 VR128:$src),
2083 (iPTR 0))), addr:$dst)]>;
2085 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2086 "movd\t{$src, $dst|$dst, $src}",
2087 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2088 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2089 "movd\t{$src, $dst|$dst, $src}",
2090 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2093 // Move to lower bits of a VR128, leaving upper bits alone.
2094 // Three operand (but two address) aliases.
2095 let isTwoAddress = 1 in {
2096 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2097 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2098 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2100 let AddedComplexity = 15 in
2101 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2102 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2103 "movsd\t{$src2, $dst|$dst, $src2}",
2105 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2106 MOVL_shuffle_mask)))]>;
2109 // Store / copy lower 64-bits of a XMM register.
2110 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2111 "movq\t{$src, $dst|$dst, $src}",
2112 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2114 // Move to lower bits of a VR128 and zeroing upper bits.
2115 // Loading from memory automatically zeroing upper bits.
2116 let AddedComplexity = 20 in
2117 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2118 "movsd\t{$src, $dst|$dst, $src}",
2120 (v2f64 (vector_shuffle immAllZerosV,
2121 (v2f64 (scalar_to_vector
2122 (loadf64 addr:$src))),
2123 MOVL_shuffle_mask)))]>;
2125 let AddedComplexity = 15 in
2126 // movd / movq to XMM register zero-extends
2127 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2128 "movd\t{$src, $dst|$dst, $src}",
2130 (v4i32 (vector_shuffle immAllZerosV,
2131 (v4i32 (scalar_to_vector GR32:$src)),
2132 MOVL_shuffle_mask)))]>;
2133 let AddedComplexity = 20 in
2134 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2135 "movd\t{$src, $dst|$dst, $src}",
2137 (v4i32 (vector_shuffle immAllZerosV,
2138 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
2139 MOVL_shuffle_mask)))]>;
2141 // Moving from XMM to XMM but still clear upper 64 bits.
2142 let AddedComplexity = 15 in
2143 def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2144 "movq\t{$src, $dst|$dst, $src}",
2145 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
2146 XS, Requires<[HasSSE2]>;
2147 let AddedComplexity = 20 in
2148 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2149 "movq\t{$src, $dst|$dst, $src}",
2150 [(set VR128:$dst, (int_x86_sse2_movl_dq
2151 (bitconvert (memopv2i64 addr:$src))))]>,
2152 XS, Requires<[HasSSE2]>;
2155 //===----------------------------------------------------------------------===//
2156 // SSE3 Instructions
2157 //===----------------------------------------------------------------------===//
2159 // Move Instructions
2160 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2161 "movshdup\t{$src, $dst|$dst, $src}",
2162 [(set VR128:$dst, (v4f32 (vector_shuffle
2163 VR128:$src, (undef),
2164 MOVSHDUP_shuffle_mask)))]>;
2165 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2166 "movshdup\t{$src, $dst|$dst, $src}",
2167 [(set VR128:$dst, (v4f32 (vector_shuffle
2168 (memopv4f32 addr:$src), (undef),
2169 MOVSHDUP_shuffle_mask)))]>;
2171 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2172 "movsldup\t{$src, $dst|$dst, $src}",
2173 [(set VR128:$dst, (v4f32 (vector_shuffle
2174 VR128:$src, (undef),
2175 MOVSLDUP_shuffle_mask)))]>;
2176 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2177 "movsldup\t{$src, $dst|$dst, $src}",
2178 [(set VR128:$dst, (v4f32 (vector_shuffle
2179 (memopv4f32 addr:$src), (undef),
2180 MOVSLDUP_shuffle_mask)))]>;
2182 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2183 "movddup\t{$src, $dst|$dst, $src}",
2184 [(set VR128:$dst, (v2f64 (vector_shuffle
2185 VR128:$src, (undef),
2186 SSE_splat_lo_mask)))]>;
2187 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2188 "movddup\t{$src, $dst|$dst, $src}",
2190 (v2f64 (vector_shuffle
2191 (scalar_to_vector (loadf64 addr:$src)),
2193 SSE_splat_lo_mask)))]>;
2196 let isTwoAddress = 1 in {
2197 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2198 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2199 "addsubps\t{$src2, $dst|$dst, $src2}",
2200 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2202 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2203 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2204 "addsubps\t{$src2, $dst|$dst, $src2}",
2205 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2206 (load addr:$src2)))]>;
2207 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2208 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2209 "addsubpd\t{$src2, $dst|$dst, $src2}",
2210 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2212 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2213 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2214 "addsubpd\t{$src2, $dst|$dst, $src2}",
2215 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2216 (load addr:$src2)))]>;
2219 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2220 "lddqu\t{$src, $dst|$dst, $src}",
2221 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2224 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2225 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2226 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2227 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2228 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2229 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2230 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2231 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
2232 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2233 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2234 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2235 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2236 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2237 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2238 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2239 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
2241 let isTwoAddress = 1 in {
2242 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2243 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2244 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2245 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2246 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2247 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2248 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2249 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2252 // Thread synchronization
2253 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2254 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2255 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2256 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2258 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2259 let AddedComplexity = 15 in
2260 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2261 MOVSHDUP_shuffle_mask)),
2262 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2263 let AddedComplexity = 20 in
2264 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2265 MOVSHDUP_shuffle_mask)),
2266 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2268 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2269 let AddedComplexity = 15 in
2270 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2271 MOVSLDUP_shuffle_mask)),
2272 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2273 let AddedComplexity = 20 in
2274 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2275 MOVSLDUP_shuffle_mask)),
2276 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2278 //===----------------------------------------------------------------------===//
2279 // SSSE3 Instructions
2280 //===----------------------------------------------------------------------===//
2282 // SSE3 Instruction Templates:
2284 // SS38I - SSSE3 instructions with T8 and OpSize prefixes.
2285 // SS3AI - SSSE3 instructions with TA and OpSize prefixes.
2287 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
2289 : I<o, F, outs, ins, asm, pattern>, T8, OpSize, Requires<[HasSSSE3]>;
2290 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
2292 : I<o, F, outs, ins, asm, pattern>, TA, OpSize, Requires<[HasSSSE3]>;
2294 /// SS3I_binop_rm_int - Simple SSSE3 binary operatr whose type is v2i64.
2295 let isTwoAddress = 1 in {
2296 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2297 bit Commutable = 0> {
2298 def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2299 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2300 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
2301 let isCommutable = Commutable;
2303 def rm : SS38I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2304 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2307 (bitconvert (memopv2i64 addr:$src2))))]>;
2311 defm PMULHRSW128 : SS3I_binop_rm_int<0x0B, "pmulhrsw",
2312 int_x86_ssse3_pmulhrsw_128, 1>;
2314 //===----------------------------------------------------------------------===//
2315 // Non-Instruction Patterns
2316 //===----------------------------------------------------------------------===//
2318 // 128-bit vector undef's.
2319 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2320 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2321 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2322 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2323 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2325 // 128-bit vector all zero's.
2326 def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2327 def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2328 def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2329 def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2330 def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2332 // 128-bit vector all one's.
2333 def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2334 def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2335 def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2336 def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2337 def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
2340 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
2342 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2343 Requires<[HasSSE2]>;
2344 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2345 Requires<[HasSSE2]>;
2348 let Predicates = [HasSSE2] in {
2349 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2350 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2351 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2352 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2353 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2354 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2355 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2356 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2357 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2358 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2359 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2360 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2361 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2362 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2363 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2364 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2365 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2366 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2367 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2368 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2369 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2370 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2371 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2372 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2373 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2374 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2375 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2376 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2377 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2378 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2381 // Move scalar to XMM zero-extended
2382 // movd to XMM register zero-extends
2383 let AddedComplexity = 15 in {
2384 def : Pat<(v8i16 (vector_shuffle immAllZerosV,
2385 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2386 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2387 def : Pat<(v16i8 (vector_shuffle immAllZerosV,
2388 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2389 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2390 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2391 def : Pat<(v2f64 (vector_shuffle immAllZerosV,
2392 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2393 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2394 def : Pat<(v4f32 (vector_shuffle immAllZerosV,
2395 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2396 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2399 // Splat v2f64 / v2i64
2400 let AddedComplexity = 10 in {
2401 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2402 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2403 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2404 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2405 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2406 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2407 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2408 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2412 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2413 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
2414 Requires<[HasSSE1]>;
2416 // Special unary SHUFPSrri case.
2417 // FIXME: when we want non two-address code, then we should use PSHUFD?
2418 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2419 SHUFP_unary_shuffle_mask:$sm),
2420 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2421 Requires<[HasSSE1]>;
2422 // Special unary SHUFPDrri case.
2423 def : Pat<(vector_shuffle (v2f64 VR128:$src1), (undef),
2424 SHUFP_unary_shuffle_mask:$sm),
2425 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2426 Requires<[HasSSE2]>;
2427 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2428 def : Pat<(vector_shuffle (memopv4f32 addr:$src1), (undef),
2429 SHUFP_unary_shuffle_mask:$sm),
2430 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2431 Requires<[HasSSE2]>;
2432 // Special binary v4i32 shuffle cases with SHUFPS.
2433 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2434 PSHUFD_binary_shuffle_mask:$sm),
2435 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2436 Requires<[HasSSE2]>;
2437 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2438 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2439 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2440 Requires<[HasSSE2]>;
2442 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2443 let AddedComplexity = 10 in {
2444 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2445 UNPCKL_v_undef_shuffle_mask)),
2446 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2447 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2448 UNPCKL_v_undef_shuffle_mask)),
2449 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2450 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2451 UNPCKL_v_undef_shuffle_mask)),
2452 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2453 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2454 UNPCKL_v_undef_shuffle_mask)),
2455 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2458 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2459 let AddedComplexity = 10 in {
2460 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2461 UNPCKH_v_undef_shuffle_mask)),
2462 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2463 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2464 UNPCKH_v_undef_shuffle_mask)),
2465 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2466 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2467 UNPCKH_v_undef_shuffle_mask)),
2468 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2469 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2470 UNPCKH_v_undef_shuffle_mask)),
2471 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2474 let AddedComplexity = 15 in {
2475 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2476 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2477 MOVHP_shuffle_mask)),
2478 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2480 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2481 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2482 MOVHLPS_shuffle_mask)),
2483 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2485 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2486 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2487 MOVHLPS_v_undef_shuffle_mask)),
2488 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2489 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2490 MOVHLPS_v_undef_shuffle_mask)),
2491 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2494 let AddedComplexity = 20 in {
2495 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2496 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2497 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2498 MOVLP_shuffle_mask)),
2499 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2500 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2501 MOVLP_shuffle_mask)),
2502 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2503 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2504 MOVHP_shuffle_mask)),
2505 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2506 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2507 MOVHP_shuffle_mask)),
2508 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2510 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2511 MOVLP_shuffle_mask)),
2512 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2513 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2514 MOVLP_shuffle_mask)),
2515 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2516 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2517 MOVHP_shuffle_mask)),
2518 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2519 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2520 MOVLP_shuffle_mask)),
2521 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2524 let AddedComplexity = 15 in {
2525 // Setting the lowest element in the vector.
2526 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2527 MOVL_shuffle_mask)),
2528 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2529 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2530 MOVL_shuffle_mask)),
2531 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2533 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2534 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2535 MOVLP_shuffle_mask)),
2536 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2537 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2538 MOVLP_shuffle_mask)),
2539 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2542 // Set lowest element and zero upper elements.
2543 let AddedComplexity = 20 in
2544 def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2545 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2546 MOVL_shuffle_mask)),
2547 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2549 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2550 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2551 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2552 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2553 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2554 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2555 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2556 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2557 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2558 Requires<[HasSSE2]>;
2559 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2560 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2561 Requires<[HasSSE2]>;
2562 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2563 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2564 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2565 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2566 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2567 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2568 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2569 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2570 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2571 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2572 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2573 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2574 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2575 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2576 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2577 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2579 // Some special case pandn patterns.
2580 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2582 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2583 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2585 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2586 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2588 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2590 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2591 (memopv2i64 addr:$src2))),
2592 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2593 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2594 (memopv2i64 addr:$src2))),
2595 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2596 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2597 (memopv2i64 addr:$src2))),
2598 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2600 // Use movaps / movups for SSE integer load / store (one byte shorter).
2601 def : Pat<(alignedloadv4i32 addr:$src),
2602 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
2603 def : Pat<(loadv4i32 addr:$src),
2604 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
2605 def : Pat<(alignedloadv2i64 addr:$src),
2606 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
2607 def : Pat<(loadv2i64 addr:$src),
2608 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
2610 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
2611 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2612 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
2613 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2614 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
2615 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2616 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
2617 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2618 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
2619 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2620 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2621 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2622 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2623 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2624 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2625 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2627 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
2628 def : Pat<(vector_extract
2629 (bc_v4i32 (v4f32 (scalar_to_vector (loadf32 addr:$src)))), (iPTR 0)),
2630 (MOV32rm addr:$src)>, Requires<[HasSSE2]>;
2631 def : Pat<(vector_extract
2632 (bc_v2i64 (v2f64 (scalar_to_vector (loadf64 addr:$src)))), (iPTR 0)),
2633 (MOV64rm addr:$src)>, Requires<[HasSSE2, In64BitMode]>;