1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
24 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
25 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
26 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
27 [SDNPCommutative, SDNPAssociative]>;
28 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
33 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
34 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
35 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
36 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
37 def X86pextrb : SDNode<"X86ISD::PEXTRB",
38 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
39 def X86pextrw : SDNode<"X86ISD::PEXTRW",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pinsrb : SDNode<"X86ISD::PINSRB",
42 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
43 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
44 def X86pinsrw : SDNode<"X86ISD::PINSRW",
45 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
46 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
47 def X86insrtps : SDNode<"X86ISD::INSERTPS",
48 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
49 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
51 //===----------------------------------------------------------------------===//
52 // SSE Complex Patterns
53 //===----------------------------------------------------------------------===//
55 // These are 'extloads' from a scalar to the low element of a vector, zeroing
56 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
58 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
59 [SDNPHasChain, SDNPMayLoad]>;
60 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
61 [SDNPHasChain, SDNPMayLoad]>;
63 def ssmem : Operand<v4f32> {
64 let PrintMethod = "printf32mem";
65 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
67 def sdmem : Operand<v2f64> {
68 let PrintMethod = "printf64mem";
69 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
72 //===----------------------------------------------------------------------===//
73 // SSE pattern fragments
74 //===----------------------------------------------------------------------===//
76 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
77 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
78 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
79 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
81 // Like 'store', but always requires vector alignment.
82 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
83 (st node:$val, node:$ptr), [{
84 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
85 return !ST->isTruncatingStore() &&
86 ST->getAddressingMode() == ISD::UNINDEXED &&
87 ST->getAlignment() >= 16;
91 // Like 'load', but always requires vector alignment.
92 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
93 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
94 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
95 LD->getAddressingMode() == ISD::UNINDEXED &&
96 LD->getAlignment() >= 16;
100 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
101 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
102 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
103 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
104 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
105 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
107 // Like 'load', but uses special alignment checks suitable for use in
108 // memory operands in most SSE instructions, which are required to
109 // be naturally aligned on some targets but not on others.
110 // FIXME: Actually implement support for targets that don't require the
111 // alignment. This probably wants a subtarget predicate.
112 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
113 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
114 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
115 LD->getAddressingMode() == ISD::UNINDEXED &&
116 LD->getAlignment() >= 16;
120 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
121 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
122 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
123 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
124 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
125 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
126 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
128 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
130 // FIXME: 8 byte alignment for mmx reads is not required
131 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
132 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
133 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
134 LD->getAddressingMode() == ISD::UNINDEXED &&
135 LD->getAlignment() >= 8;
139 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
140 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
141 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
142 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
144 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
145 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
146 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
147 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
148 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
149 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
151 def fp32imm0 : PatLeaf<(f32 fpimm), [{
152 return N->isExactlyValue(+0.0);
155 def PSxLDQ_imm : SDNodeXForm<imm, [{
156 // Transformation function: imm >> 3
157 return getI32Imm(N->getValue() >> 3);
160 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
162 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
163 return getI8Imm(X86::getShuffleSHUFImmediate(N));
166 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
168 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
169 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
172 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
174 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
175 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
178 def SSE_splat_mask : PatLeaf<(build_vector), [{
179 return X86::isSplatMask(N);
180 }], SHUFFLE_get_shuf_imm>;
182 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
183 return X86::isSplatLoMask(N);
186 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
187 return X86::isMOVHLPSMask(N);
190 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
191 return X86::isMOVHLPS_v_undef_Mask(N);
194 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
195 return X86::isMOVHPMask(N);
198 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
199 return X86::isMOVLPMask(N);
202 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
203 return X86::isMOVLMask(N);
206 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
207 return X86::isMOVSHDUPMask(N);
210 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
211 return X86::isMOVSLDUPMask(N);
214 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
215 return X86::isUNPCKLMask(N);
218 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
219 return X86::isUNPCKHMask(N);
222 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
223 return X86::isUNPCKL_v_undef_Mask(N);
226 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
227 return X86::isUNPCKH_v_undef_Mask(N);
230 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
231 return X86::isPSHUFDMask(N);
232 }], SHUFFLE_get_shuf_imm>;
234 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
235 return X86::isPSHUFHWMask(N);
236 }], SHUFFLE_get_pshufhw_imm>;
238 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
239 return X86::isPSHUFLWMask(N);
240 }], SHUFFLE_get_pshuflw_imm>;
242 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
243 return X86::isPSHUFDMask(N);
244 }], SHUFFLE_get_shuf_imm>;
246 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
247 return X86::isSHUFPMask(N);
248 }], SHUFFLE_get_shuf_imm>;
250 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
251 return X86::isSHUFPMask(N);
252 }], SHUFFLE_get_shuf_imm>;
254 //===----------------------------------------------------------------------===//
255 // SSE scalar FP Instructions
256 //===----------------------------------------------------------------------===//
258 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
259 // scheduler into a branch sequence.
260 // These are expanded by the scheduler.
261 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
262 def CMOV_FR32 : I<0, Pseudo,
263 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
264 "#CMOV_FR32 PSEUDO!",
265 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
267 def CMOV_FR64 : I<0, Pseudo,
268 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
269 "#CMOV_FR64 PSEUDO!",
270 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
272 def CMOV_V4F32 : I<0, Pseudo,
273 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
274 "#CMOV_V4F32 PSEUDO!",
276 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
278 def CMOV_V2F64 : I<0, Pseudo,
279 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
280 "#CMOV_V2F64 PSEUDO!",
282 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
284 def CMOV_V2I64 : I<0, Pseudo,
285 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
286 "#CMOV_V2I64 PSEUDO!",
288 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
292 //===----------------------------------------------------------------------===//
294 //===----------------------------------------------------------------------===//
297 let neverHasSideEffects = 1 in
298 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
299 "movss\t{$src, $dst|$dst, $src}", []>;
300 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
301 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
302 "movss\t{$src, $dst|$dst, $src}",
303 [(set FR32:$dst, (loadf32 addr:$src))]>;
304 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
305 "movss\t{$src, $dst|$dst, $src}",
306 [(store FR32:$src, addr:$dst)]>;
308 // Conversion instructions
309 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
310 "cvttss2si\t{$src, $dst|$dst, $src}",
311 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
312 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
313 "cvttss2si\t{$src, $dst|$dst, $src}",
314 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
315 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
316 "cvtsi2ss\t{$src, $dst|$dst, $src}",
317 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
318 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
319 "cvtsi2ss\t{$src, $dst|$dst, $src}",
320 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
322 // Match intrinsics which expect XMM operand(s).
323 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
324 "cvtss2si\t{$src, $dst|$dst, $src}",
325 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
326 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
327 "cvtss2si\t{$src, $dst|$dst, $src}",
328 [(set GR32:$dst, (int_x86_sse_cvtss2si
329 (load addr:$src)))]>;
331 // Match intrinisics which expect MM and XMM operand(s).
332 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
333 "cvtps2pi\t{$src, $dst|$dst, $src}",
334 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
335 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
336 "cvtps2pi\t{$src, $dst|$dst, $src}",
337 [(set VR64:$dst, (int_x86_sse_cvtps2pi
338 (load addr:$src)))]>;
339 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
340 "cvttps2pi\t{$src, $dst|$dst, $src}",
341 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
342 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
343 "cvttps2pi\t{$src, $dst|$dst, $src}",
344 [(set VR64:$dst, (int_x86_sse_cvttps2pi
345 (load addr:$src)))]>;
346 let Constraints = "$src1 = $dst" in {
347 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
348 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
349 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
350 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
352 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
353 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
354 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
355 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
356 (load addr:$src2)))]>;
359 // Aliases for intrinsics
360 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
361 "cvttss2si\t{$src, $dst|$dst, $src}",
363 (int_x86_sse_cvttss2si VR128:$src))]>;
364 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
365 "cvttss2si\t{$src, $dst|$dst, $src}",
367 (int_x86_sse_cvttss2si(load addr:$src)))]>;
369 let Constraints = "$src1 = $dst" in {
370 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
371 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
372 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
373 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
375 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
376 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
377 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
378 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
379 (loadi32 addr:$src2)))]>;
382 // Comparison instructions
383 let Constraints = "$src1 = $dst" in {
384 let neverHasSideEffects = 1 in
385 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
386 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
387 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
388 let neverHasSideEffects = 1, mayLoad = 1 in
389 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
390 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
391 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
394 let Defs = [EFLAGS] in {
395 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
396 "ucomiss\t{$src2, $src1|$src1, $src2}",
397 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
398 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
399 "ucomiss\t{$src2, $src1|$src1, $src2}",
400 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
404 // Aliases to match intrinsics which expect XMM operand(s).
405 let Constraints = "$src1 = $dst" in {
406 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
407 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
408 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
409 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
410 VR128:$src, imm:$cc))]>;
411 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
412 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
413 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
414 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
415 (load addr:$src), imm:$cc))]>;
418 let Defs = [EFLAGS] in {
419 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
420 (ins VR128:$src1, VR128:$src2),
421 "ucomiss\t{$src2, $src1|$src1, $src2}",
422 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
424 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
425 (ins VR128:$src1, f128mem:$src2),
426 "ucomiss\t{$src2, $src1|$src1, $src2}",
427 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
430 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
431 (ins VR128:$src1, VR128:$src2),
432 "comiss\t{$src2, $src1|$src1, $src2}",
433 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
435 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
436 (ins VR128:$src1, f128mem:$src2),
437 "comiss\t{$src2, $src1|$src1, $src2}",
438 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
442 // Aliases of packed SSE1 instructions for scalar use. These all have names that
445 // Alias instructions that map fld0 to pxor for sse.
446 let isReMaterializable = 1 in
447 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
448 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
449 Requires<[HasSSE1]>, TB, OpSize;
451 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
453 let neverHasSideEffects = 1 in
454 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
455 "movaps\t{$src, $dst|$dst, $src}", []>;
457 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
459 let isSimpleLoad = 1 in
460 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
461 "movaps\t{$src, $dst|$dst, $src}",
462 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
464 // Alias bitwise logical operations using SSE logical ops on packed FP values.
465 let Constraints = "$src1 = $dst" in {
466 let isCommutable = 1 in {
467 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
468 "andps\t{$src2, $dst|$dst, $src2}",
469 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
470 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
471 "orps\t{$src2, $dst|$dst, $src2}",
472 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
473 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
474 "xorps\t{$src2, $dst|$dst, $src2}",
475 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
478 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
479 "andps\t{$src2, $dst|$dst, $src2}",
480 [(set FR32:$dst, (X86fand FR32:$src1,
481 (memopfsf32 addr:$src2)))]>;
482 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
483 "orps\t{$src2, $dst|$dst, $src2}",
484 [(set FR32:$dst, (X86for FR32:$src1,
485 (memopfsf32 addr:$src2)))]>;
486 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
487 "xorps\t{$src2, $dst|$dst, $src2}",
488 [(set FR32:$dst, (X86fxor FR32:$src1,
489 (memopfsf32 addr:$src2)))]>;
490 let neverHasSideEffects = 1 in {
491 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
492 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
493 "andnps\t{$src2, $dst|$dst, $src2}", []>;
496 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
497 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
498 "andnps\t{$src2, $dst|$dst, $src2}", []>;
502 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
504 /// In addition, we also have a special variant of the scalar form here to
505 /// represent the associated intrinsic operation. This form is unlike the
506 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
507 /// and leaves the top elements undefined.
509 /// These three forms can each be reg+reg or reg+mem, so there are a total of
510 /// six "instructions".
512 let Constraints = "$src1 = $dst" in {
513 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
514 SDNode OpNode, Intrinsic F32Int,
515 bit Commutable = 0> {
516 // Scalar operation, reg+reg.
517 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
518 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
519 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
520 let isCommutable = Commutable;
523 // Scalar operation, reg+mem.
524 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
525 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
526 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
528 // Vector operation, reg+reg.
529 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
530 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
531 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
532 let isCommutable = Commutable;
535 // Vector operation, reg+mem.
536 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
537 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
538 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
540 // Intrinsic operation, reg+reg.
541 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
542 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
543 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
544 let isCommutable = Commutable;
547 // Intrinsic operation, reg+mem.
548 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
549 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
550 [(set VR128:$dst, (F32Int VR128:$src1,
551 sse_load_f32:$src2))]>;
555 // Arithmetic instructions
556 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
557 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
558 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
559 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
561 /// sse1_fp_binop_rm - Other SSE1 binops
563 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
564 /// instructions for a full-vector intrinsic form. Operations that map
565 /// onto C operators don't use this form since they just use the plain
566 /// vector form instead of having a separate vector intrinsic form.
568 /// This provides a total of eight "instructions".
570 let Constraints = "$src1 = $dst" in {
571 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
575 bit Commutable = 0> {
577 // Scalar operation, reg+reg.
578 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
579 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
580 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
581 let isCommutable = Commutable;
584 // Scalar operation, reg+mem.
585 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
586 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
587 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
589 // Vector operation, reg+reg.
590 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
591 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
592 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
593 let isCommutable = Commutable;
596 // Vector operation, reg+mem.
597 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
598 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
599 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
601 // Intrinsic operation, reg+reg.
602 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
603 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
604 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
605 let isCommutable = Commutable;
608 // Intrinsic operation, reg+mem.
609 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
610 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
611 [(set VR128:$dst, (F32Int VR128:$src1,
612 sse_load_f32:$src2))]>;
614 // Vector intrinsic operation, reg+reg.
615 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
616 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
617 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
618 let isCommutable = Commutable;
621 // Vector intrinsic operation, reg+mem.
622 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
623 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
624 [(set VR128:$dst, (V4F32Int VR128:$src1, (load addr:$src2)))]>;
628 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
629 int_x86_sse_max_ss, int_x86_sse_max_ps>;
630 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
631 int_x86_sse_min_ss, int_x86_sse_min_ps>;
633 //===----------------------------------------------------------------------===//
634 // SSE packed FP Instructions
637 let neverHasSideEffects = 1 in
638 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
639 "movaps\t{$src, $dst|$dst, $src}", []>;
640 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
641 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
642 "movaps\t{$src, $dst|$dst, $src}",
643 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
645 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
646 "movaps\t{$src, $dst|$dst, $src}",
647 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
649 let neverHasSideEffects = 1 in
650 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
651 "movups\t{$src, $dst|$dst, $src}", []>;
652 let isSimpleLoad = 1 in
653 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
654 "movups\t{$src, $dst|$dst, $src}",
655 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
656 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
657 "movups\t{$src, $dst|$dst, $src}",
658 [(store (v4f32 VR128:$src), addr:$dst)]>;
660 // Intrinsic forms of MOVUPS load and store
661 let isSimpleLoad = 1 in
662 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
663 "movups\t{$src, $dst|$dst, $src}",
664 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
665 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
666 "movups\t{$src, $dst|$dst, $src}",
667 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
669 let Constraints = "$src1 = $dst" in {
670 let AddedComplexity = 20 in {
671 def MOVLPSrm : PSI<0x12, MRMSrcMem,
672 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
673 "movlps\t{$src2, $dst|$dst, $src2}",
675 (v4f32 (vector_shuffle VR128:$src1,
676 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
677 MOVLP_shuffle_mask)))]>;
678 def MOVHPSrm : PSI<0x16, MRMSrcMem,
679 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
680 "movhps\t{$src2, $dst|$dst, $src2}",
682 (v4f32 (vector_shuffle VR128:$src1,
683 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
684 MOVHP_shuffle_mask)))]>;
686 } // Constraints = "$src1 = $dst"
688 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
689 "movlps\t{$src, $dst|$dst, $src}",
690 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
691 (iPTR 0))), addr:$dst)]>;
693 // v2f64 extract element 1 is always custom lowered to unpack high to low
694 // and extract element 0 so the non-store version isn't too horrible.
695 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
696 "movhps\t{$src, $dst|$dst, $src}",
697 [(store (f64 (vector_extract
698 (v2f64 (vector_shuffle
699 (bc_v2f64 (v4f32 VR128:$src)), (undef),
700 UNPCKH_shuffle_mask)), (iPTR 0))),
703 let Constraints = "$src1 = $dst" in {
704 let AddedComplexity = 15 in {
705 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
706 "movlhps\t{$src2, $dst|$dst, $src2}",
708 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
709 MOVHP_shuffle_mask)))]>;
711 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
712 "movhlps\t{$src2, $dst|$dst, $src2}",
714 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
715 MOVHLPS_shuffle_mask)))]>;
717 } // Constraints = "$src1 = $dst"
723 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
725 /// In addition, we also have a special variant of the scalar form here to
726 /// represent the associated intrinsic operation. This form is unlike the
727 /// plain scalar form, in that it takes an entire vector (instead of a
728 /// scalar) and leaves the top elements undefined.
730 /// And, we have a special variant form for a full-vector intrinsic form.
732 /// These four forms can each have a reg or a mem operand, so there are a
733 /// total of eight "instructions".
735 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
739 bit Commutable = 0> {
740 // Scalar operation, reg.
741 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
742 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
743 [(set FR32:$dst, (OpNode FR32:$src))]> {
744 let isCommutable = Commutable;
747 // Scalar operation, mem.
748 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
749 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
750 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
752 // Vector operation, reg.
753 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
754 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
755 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
756 let isCommutable = Commutable;
759 // Vector operation, mem.
760 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
761 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
762 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
764 // Intrinsic operation, reg.
765 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
766 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
767 [(set VR128:$dst, (F32Int VR128:$src))]> {
768 let isCommutable = Commutable;
771 // Intrinsic operation, mem.
772 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
773 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
774 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
776 // Vector intrinsic operation, reg
777 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
778 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
779 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
780 let isCommutable = Commutable;
783 // Vector intrinsic operation, mem
784 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
785 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
786 [(set VR128:$dst, (V4F32Int (load addr:$src)))]>;
790 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
791 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
793 // Reciprocal approximations. Note that these typically require refinement
794 // in order to obtain suitable precision.
795 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
796 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
797 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
798 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
801 let Constraints = "$src1 = $dst" in {
802 let isCommutable = 1 in {
803 def ANDPSrr : PSI<0x54, MRMSrcReg,
804 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
805 "andps\t{$src2, $dst|$dst, $src2}",
806 [(set VR128:$dst, (v2i64
807 (and VR128:$src1, VR128:$src2)))]>;
808 def ORPSrr : PSI<0x56, MRMSrcReg,
809 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
810 "orps\t{$src2, $dst|$dst, $src2}",
811 [(set VR128:$dst, (v2i64
812 (or VR128:$src1, VR128:$src2)))]>;
813 def XORPSrr : PSI<0x57, MRMSrcReg,
814 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
815 "xorps\t{$src2, $dst|$dst, $src2}",
816 [(set VR128:$dst, (v2i64
817 (xor VR128:$src1, VR128:$src2)))]>;
820 def ANDPSrm : PSI<0x54, MRMSrcMem,
821 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
822 "andps\t{$src2, $dst|$dst, $src2}",
823 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
824 (memopv2i64 addr:$src2)))]>;
825 def ORPSrm : PSI<0x56, MRMSrcMem,
826 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
827 "orps\t{$src2, $dst|$dst, $src2}",
828 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
829 (memopv2i64 addr:$src2)))]>;
830 def XORPSrm : PSI<0x57, MRMSrcMem,
831 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
832 "xorps\t{$src2, $dst|$dst, $src2}",
833 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
834 (memopv2i64 addr:$src2)))]>;
835 def ANDNPSrr : PSI<0x55, MRMSrcReg,
836 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
837 "andnps\t{$src2, $dst|$dst, $src2}",
839 (v2i64 (and (xor VR128:$src1,
840 (bc_v2i64 (v4i32 immAllOnesV))),
842 def ANDNPSrm : PSI<0x55, MRMSrcMem,
843 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
844 "andnps\t{$src2, $dst|$dst, $src2}",
846 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
847 (bc_v2i64 (v4i32 immAllOnesV))),
848 (memopv2i64 addr:$src2))))]>;
851 let Constraints = "$src1 = $dst" in {
852 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
853 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
854 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
855 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
856 VR128:$src, imm:$cc))]>;
857 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
858 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
859 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
860 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
861 (load addr:$src), imm:$cc))]>;
864 // Shuffle and unpack instructions
865 let Constraints = "$src1 = $dst" in {
866 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
867 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
868 (outs VR128:$dst), (ins VR128:$src1,
869 VR128:$src2, i32i8imm:$src3),
870 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
872 (v4f32 (vector_shuffle
873 VR128:$src1, VR128:$src2,
874 SHUFP_shuffle_mask:$src3)))]>;
875 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
876 (outs VR128:$dst), (ins VR128:$src1,
877 f128mem:$src2, i32i8imm:$src3),
878 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
880 (v4f32 (vector_shuffle
881 VR128:$src1, (memopv4f32 addr:$src2),
882 SHUFP_shuffle_mask:$src3)))]>;
884 let AddedComplexity = 10 in {
885 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
886 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
887 "unpckhps\t{$src2, $dst|$dst, $src2}",
889 (v4f32 (vector_shuffle
890 VR128:$src1, VR128:$src2,
891 UNPCKH_shuffle_mask)))]>;
892 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
893 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
894 "unpckhps\t{$src2, $dst|$dst, $src2}",
896 (v4f32 (vector_shuffle
897 VR128:$src1, (memopv4f32 addr:$src2),
898 UNPCKH_shuffle_mask)))]>;
900 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
901 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
902 "unpcklps\t{$src2, $dst|$dst, $src2}",
904 (v4f32 (vector_shuffle
905 VR128:$src1, VR128:$src2,
906 UNPCKL_shuffle_mask)))]>;
907 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
908 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
909 "unpcklps\t{$src2, $dst|$dst, $src2}",
911 (v4f32 (vector_shuffle
912 VR128:$src1, (memopv4f32 addr:$src2),
913 UNPCKL_shuffle_mask)))]>;
915 } // Constraints = "$src1 = $dst"
918 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
919 "movmskps\t{$src, $dst|$dst, $src}",
920 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
921 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
922 "movmskpd\t{$src, $dst|$dst, $src}",
923 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
925 // Prefetch intrinsic.
926 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
927 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
928 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
929 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
930 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
931 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
932 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
933 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
935 // Non-temporal stores
936 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
937 "movntps\t{$src, $dst|$dst, $src}",
938 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
940 // Load, store, and memory fence
941 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
944 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
945 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
946 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
947 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
949 // Alias instructions that map zero vector to pxor / xorp* for sse.
950 let isReMaterializable = 1 in
951 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
953 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
955 let Predicates = [HasSSE1] in {
956 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
957 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
958 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
959 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
960 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
963 // FR32 to 128-bit vector conversion.
964 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
965 "movss\t{$src, $dst|$dst, $src}",
967 (v4f32 (scalar_to_vector FR32:$src)))]>;
968 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
969 "movss\t{$src, $dst|$dst, $src}",
971 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
973 // FIXME: may not be able to eliminate this movss with coalescing the src and
974 // dest register classes are different. We really want to write this pattern
976 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
978 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
979 "movss\t{$src, $dst|$dst, $src}",
980 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
982 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
983 "movss\t{$src, $dst|$dst, $src}",
984 [(store (f32 (vector_extract (v4f32 VR128:$src),
985 (iPTR 0))), addr:$dst)]>;
988 // Move to lower bits of a VR128, leaving upper bits alone.
989 // Three operand (but two address) aliases.
990 let Constraints = "$src1 = $dst" in {
991 let neverHasSideEffects = 1 in
992 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
993 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
994 "movss\t{$src2, $dst|$dst, $src2}", []>;
996 let AddedComplexity = 15 in
997 def MOVLPSrr : SSI<0x10, MRMSrcReg,
998 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
999 "movss\t{$src2, $dst|$dst, $src2}",
1001 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1002 MOVL_shuffle_mask)))]>;
1005 // Move to lower bits of a VR128 and zeroing upper bits.
1006 // Loading from memory automatically zeroing upper bits.
1007 let AddedComplexity = 20 in
1008 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1009 "movss\t{$src, $dst|$dst, $src}",
1010 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV_bc,
1011 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
1012 MOVL_shuffle_mask)))]>;
1015 //===----------------------------------------------------------------------===//
1016 // SSE2 Instructions
1017 //===----------------------------------------------------------------------===//
1019 // Move Instructions
1020 let neverHasSideEffects = 1 in
1021 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1022 "movsd\t{$src, $dst|$dst, $src}", []>;
1023 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1024 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1025 "movsd\t{$src, $dst|$dst, $src}",
1026 [(set FR64:$dst, (loadf64 addr:$src))]>;
1027 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1028 "movsd\t{$src, $dst|$dst, $src}",
1029 [(store FR64:$src, addr:$dst)]>;
1031 // Conversion instructions
1032 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1033 "cvttsd2si\t{$src, $dst|$dst, $src}",
1034 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1035 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1036 "cvttsd2si\t{$src, $dst|$dst, $src}",
1037 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1038 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1039 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1040 [(set FR32:$dst, (fround FR64:$src))]>;
1041 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1042 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1043 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1044 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1045 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1046 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1047 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1048 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1049 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1051 // SSE2 instructions with XS prefix
1052 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1053 "cvtss2sd\t{$src, $dst|$dst, $src}",
1054 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1055 Requires<[HasSSE2]>;
1056 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1057 "cvtss2sd\t{$src, $dst|$dst, $src}",
1058 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1059 Requires<[HasSSE2]>;
1061 // Match intrinsics which expect XMM operand(s).
1062 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1063 "cvtsd2si\t{$src, $dst|$dst, $src}",
1064 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1065 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1066 "cvtsd2si\t{$src, $dst|$dst, $src}",
1067 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1068 (load addr:$src)))]>;
1070 // Match intrinisics which expect MM and XMM operand(s).
1071 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1072 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1073 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1074 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1075 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1076 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1077 (load addr:$src)))]>;
1078 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1079 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1080 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1081 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1082 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1083 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1084 (load addr:$src)))]>;
1085 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1086 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1087 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1088 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1089 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1090 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1091 (load addr:$src)))]>;
1093 // Aliases for intrinsics
1094 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1095 "cvttsd2si\t{$src, $dst|$dst, $src}",
1097 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1098 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1099 "cvttsd2si\t{$src, $dst|$dst, $src}",
1100 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1101 (load addr:$src)))]>;
1103 // Comparison instructions
1104 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1105 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1106 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1107 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1109 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1110 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1111 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1114 let Defs = [EFLAGS] in {
1115 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1116 "ucomisd\t{$src2, $src1|$src1, $src2}",
1117 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1118 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1119 "ucomisd\t{$src2, $src1|$src1, $src2}",
1120 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1121 (implicit EFLAGS)]>;
1124 // Aliases to match intrinsics which expect XMM operand(s).
1125 let Constraints = "$src1 = $dst" in {
1126 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1127 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1128 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1129 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1130 VR128:$src, imm:$cc))]>;
1131 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1132 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1133 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1134 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1135 (load addr:$src), imm:$cc))]>;
1138 let Defs = [EFLAGS] in {
1139 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1140 "ucomisd\t{$src2, $src1|$src1, $src2}",
1141 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1142 (implicit EFLAGS)]>;
1143 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1144 "ucomisd\t{$src2, $src1|$src1, $src2}",
1145 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1146 (implicit EFLAGS)]>;
1148 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1149 "comisd\t{$src2, $src1|$src1, $src2}",
1150 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1151 (implicit EFLAGS)]>;
1152 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1153 "comisd\t{$src2, $src1|$src1, $src2}",
1154 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1155 (implicit EFLAGS)]>;
1158 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1161 // Alias instructions that map fld0 to pxor for sse.
1162 let isReMaterializable = 1 in
1163 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1164 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1165 Requires<[HasSSE2]>, TB, OpSize;
1167 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1169 let neverHasSideEffects = 1 in
1170 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1171 "movapd\t{$src, $dst|$dst, $src}", []>;
1173 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1175 let isSimpleLoad = 1 in
1176 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1177 "movapd\t{$src, $dst|$dst, $src}",
1178 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1180 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1181 let Constraints = "$src1 = $dst" in {
1182 let isCommutable = 1 in {
1183 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1184 "andpd\t{$src2, $dst|$dst, $src2}",
1185 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1186 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1187 "orpd\t{$src2, $dst|$dst, $src2}",
1188 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1189 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1190 "xorpd\t{$src2, $dst|$dst, $src2}",
1191 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1194 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1195 "andpd\t{$src2, $dst|$dst, $src2}",
1196 [(set FR64:$dst, (X86fand FR64:$src1,
1197 (memopfsf64 addr:$src2)))]>;
1198 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1199 "orpd\t{$src2, $dst|$dst, $src2}",
1200 [(set FR64:$dst, (X86for FR64:$src1,
1201 (memopfsf64 addr:$src2)))]>;
1202 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1203 "xorpd\t{$src2, $dst|$dst, $src2}",
1204 [(set FR64:$dst, (X86fxor FR64:$src1,
1205 (memopfsf64 addr:$src2)))]>;
1207 let neverHasSideEffects = 1 in {
1208 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1209 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1210 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1212 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1213 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1214 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1218 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1220 /// In addition, we also have a special variant of the scalar form here to
1221 /// represent the associated intrinsic operation. This form is unlike the
1222 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1223 /// and leaves the top elements undefined.
1225 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1226 /// six "instructions".
1228 let Constraints = "$src1 = $dst" in {
1229 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1230 SDNode OpNode, Intrinsic F64Int,
1231 bit Commutable = 0> {
1232 // Scalar operation, reg+reg.
1233 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1234 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1235 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1236 let isCommutable = Commutable;
1239 // Scalar operation, reg+mem.
1240 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1241 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1242 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1244 // Vector operation, reg+reg.
1245 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1246 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1247 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1248 let isCommutable = Commutable;
1251 // Vector operation, reg+mem.
1252 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1253 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1254 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1256 // Intrinsic operation, reg+reg.
1257 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1258 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1259 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1260 let isCommutable = Commutable;
1263 // Intrinsic operation, reg+mem.
1264 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1265 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1266 [(set VR128:$dst, (F64Int VR128:$src1,
1267 sse_load_f64:$src2))]>;
1271 // Arithmetic instructions
1272 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1273 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1274 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1275 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1277 /// sse2_fp_binop_rm - Other SSE2 binops
1279 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1280 /// instructions for a full-vector intrinsic form. Operations that map
1281 /// onto C operators don't use this form since they just use the plain
1282 /// vector form instead of having a separate vector intrinsic form.
1284 /// This provides a total of eight "instructions".
1286 let Constraints = "$src1 = $dst" in {
1287 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1291 bit Commutable = 0> {
1293 // Scalar operation, reg+reg.
1294 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1295 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1296 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1297 let isCommutable = Commutable;
1300 // Scalar operation, reg+mem.
1301 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1302 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1303 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1305 // Vector operation, reg+reg.
1306 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1307 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1308 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1309 let isCommutable = Commutable;
1312 // Vector operation, reg+mem.
1313 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1314 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1315 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1317 // Intrinsic operation, reg+reg.
1318 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1319 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1320 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1321 let isCommutable = Commutable;
1324 // Intrinsic operation, reg+mem.
1325 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1326 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1327 [(set VR128:$dst, (F64Int VR128:$src1,
1328 sse_load_f64:$src2))]>;
1330 // Vector intrinsic operation, reg+reg.
1331 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1332 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1333 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1334 let isCommutable = Commutable;
1337 // Vector intrinsic operation, reg+mem.
1338 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1339 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1340 [(set VR128:$dst, (V2F64Int VR128:$src1, (load addr:$src2)))]>;
1344 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1345 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1346 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1347 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1349 //===----------------------------------------------------------------------===//
1350 // SSE packed FP Instructions
1352 // Move Instructions
1353 let neverHasSideEffects = 1 in
1354 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1355 "movapd\t{$src, $dst|$dst, $src}", []>;
1356 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1357 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1358 "movapd\t{$src, $dst|$dst, $src}",
1359 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1361 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1362 "movapd\t{$src, $dst|$dst, $src}",
1363 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1365 let neverHasSideEffects = 1 in
1366 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1367 "movupd\t{$src, $dst|$dst, $src}", []>;
1368 let isSimpleLoad = 1 in
1369 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1370 "movupd\t{$src, $dst|$dst, $src}",
1371 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1372 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1373 "movupd\t{$src, $dst|$dst, $src}",
1374 [(store (v2f64 VR128:$src), addr:$dst)]>;
1376 // Intrinsic forms of MOVUPD load and store
1377 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1378 "movupd\t{$src, $dst|$dst, $src}",
1379 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1380 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1381 "movupd\t{$src, $dst|$dst, $src}",
1382 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1384 let Constraints = "$src1 = $dst" in {
1385 let AddedComplexity = 20 in {
1386 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1387 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1388 "movlpd\t{$src2, $dst|$dst, $src2}",
1390 (v2f64 (vector_shuffle VR128:$src1,
1391 (scalar_to_vector (loadf64 addr:$src2)),
1392 MOVLP_shuffle_mask)))]>;
1393 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1394 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1395 "movhpd\t{$src2, $dst|$dst, $src2}",
1397 (v2f64 (vector_shuffle VR128:$src1,
1398 (scalar_to_vector (loadf64 addr:$src2)),
1399 MOVHP_shuffle_mask)))]>;
1400 } // AddedComplexity
1401 } // Constraints = "$src1 = $dst"
1403 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1404 "movlpd\t{$src, $dst|$dst, $src}",
1405 [(store (f64 (vector_extract (v2f64 VR128:$src),
1406 (iPTR 0))), addr:$dst)]>;
1408 // v2f64 extract element 1 is always custom lowered to unpack high to low
1409 // and extract element 0 so the non-store version isn't too horrible.
1410 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1411 "movhpd\t{$src, $dst|$dst, $src}",
1412 [(store (f64 (vector_extract
1413 (v2f64 (vector_shuffle VR128:$src, (undef),
1414 UNPCKH_shuffle_mask)), (iPTR 0))),
1417 // SSE2 instructions without OpSize prefix
1418 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1419 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1420 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1421 TB, Requires<[HasSSE2]>;
1422 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1423 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1424 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1425 (bitconvert (memopv2i64 addr:$src))))]>,
1426 TB, Requires<[HasSSE2]>;
1428 // SSE2 instructions with XS prefix
1429 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1430 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1431 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1432 XS, Requires<[HasSSE2]>;
1433 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1434 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1435 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1436 (bitconvert (memopv2i64 addr:$src))))]>,
1437 XS, Requires<[HasSSE2]>;
1439 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1440 "cvtps2dq\t{$src, $dst|$dst, $src}",
1441 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1442 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1443 "cvtps2dq\t{$src, $dst|$dst, $src}",
1444 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1445 (load addr:$src)))]>;
1446 // SSE2 packed instructions with XS prefix
1447 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1448 "cvttps2dq\t{$src, $dst|$dst, $src}",
1449 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1450 XS, Requires<[HasSSE2]>;
1451 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1452 "cvttps2dq\t{$src, $dst|$dst, $src}",
1453 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1454 (load addr:$src)))]>,
1455 XS, Requires<[HasSSE2]>;
1457 // SSE2 packed instructions with XD prefix
1458 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1459 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1460 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1461 XD, Requires<[HasSSE2]>;
1462 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1463 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1464 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1465 (load addr:$src)))]>,
1466 XD, Requires<[HasSSE2]>;
1468 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1469 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1470 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1471 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1472 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1473 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1474 (load addr:$src)))]>;
1476 // SSE2 instructions without OpSize prefix
1477 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1478 "cvtps2pd\t{$src, $dst|$dst, $src}",
1479 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1480 TB, Requires<[HasSSE2]>;
1481 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f64mem:$src),
1482 "cvtps2pd\t{$src, $dst|$dst, $src}",
1483 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1484 (load addr:$src)))]>,
1485 TB, Requires<[HasSSE2]>;
1487 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1488 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1489 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1490 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f128mem:$src),
1491 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1492 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1493 (load addr:$src)))]>;
1495 // Match intrinsics which expect XMM operand(s).
1496 // Aliases for intrinsics
1497 let Constraints = "$src1 = $dst" in {
1498 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1499 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1500 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1501 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1503 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1504 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1505 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1506 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1507 (loadi32 addr:$src2)))]>;
1508 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1509 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1510 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1511 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1513 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1514 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1515 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1516 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1517 (load addr:$src2)))]>;
1518 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1519 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1520 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1521 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1522 VR128:$src2))]>, XS,
1523 Requires<[HasSSE2]>;
1524 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1525 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1526 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1527 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1528 (load addr:$src2)))]>, XS,
1529 Requires<[HasSSE2]>;
1534 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1536 /// In addition, we also have a special variant of the scalar form here to
1537 /// represent the associated intrinsic operation. This form is unlike the
1538 /// plain scalar form, in that it takes an entire vector (instead of a
1539 /// scalar) and leaves the top elements undefined.
1541 /// And, we have a special variant form for a full-vector intrinsic form.
1543 /// These four forms can each have a reg or a mem operand, so there are a
1544 /// total of eight "instructions".
1546 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1550 bit Commutable = 0> {
1551 // Scalar operation, reg.
1552 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1553 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1554 [(set FR64:$dst, (OpNode FR64:$src))]> {
1555 let isCommutable = Commutable;
1558 // Scalar operation, mem.
1559 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1560 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1561 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1563 // Vector operation, reg.
1564 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1565 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1566 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1567 let isCommutable = Commutable;
1570 // Vector operation, mem.
1571 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1572 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1573 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1575 // Intrinsic operation, reg.
1576 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1577 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1578 [(set VR128:$dst, (F64Int VR128:$src))]> {
1579 let isCommutable = Commutable;
1582 // Intrinsic operation, mem.
1583 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1584 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1585 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1587 // Vector intrinsic operation, reg
1588 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1589 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1590 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1591 let isCommutable = Commutable;
1594 // Vector intrinsic operation, mem
1595 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1596 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1597 [(set VR128:$dst, (V2F64Int (load addr:$src)))]>;
1601 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1602 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1604 // There is no f64 version of the reciprocal approximation instructions.
1607 let Constraints = "$src1 = $dst" in {
1608 let isCommutable = 1 in {
1609 def ANDPDrr : PDI<0x54, MRMSrcReg,
1610 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1611 "andpd\t{$src2, $dst|$dst, $src2}",
1613 (and (bc_v2i64 (v2f64 VR128:$src1)),
1614 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1615 def ORPDrr : PDI<0x56, MRMSrcReg,
1616 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1617 "orpd\t{$src2, $dst|$dst, $src2}",
1619 (or (bc_v2i64 (v2f64 VR128:$src1)),
1620 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1621 def XORPDrr : PDI<0x57, MRMSrcReg,
1622 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1623 "xorpd\t{$src2, $dst|$dst, $src2}",
1625 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1626 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1629 def ANDPDrm : PDI<0x54, MRMSrcMem,
1630 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1631 "andpd\t{$src2, $dst|$dst, $src2}",
1633 (and (bc_v2i64 (v2f64 VR128:$src1)),
1634 (memopv2i64 addr:$src2)))]>;
1635 def ORPDrm : PDI<0x56, MRMSrcMem,
1636 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1637 "orpd\t{$src2, $dst|$dst, $src2}",
1639 (or (bc_v2i64 (v2f64 VR128:$src1)),
1640 (memopv2i64 addr:$src2)))]>;
1641 def XORPDrm : PDI<0x57, MRMSrcMem,
1642 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1643 "xorpd\t{$src2, $dst|$dst, $src2}",
1645 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1646 (memopv2i64 addr:$src2)))]>;
1647 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1648 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1649 "andnpd\t{$src2, $dst|$dst, $src2}",
1651 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1652 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1653 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1654 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1655 "andnpd\t{$src2, $dst|$dst, $src2}",
1657 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1658 (memopv2i64 addr:$src2)))]>;
1661 let Constraints = "$src1 = $dst" in {
1662 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1663 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1664 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1665 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1666 VR128:$src, imm:$cc))]>;
1667 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1668 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1669 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1670 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1671 (load addr:$src), imm:$cc))]>;
1674 // Shuffle and unpack instructions
1675 let Constraints = "$src1 = $dst" in {
1676 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1677 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1678 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1679 [(set VR128:$dst, (v2f64 (vector_shuffle
1680 VR128:$src1, VR128:$src2,
1681 SHUFP_shuffle_mask:$src3)))]>;
1682 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1683 (outs VR128:$dst), (ins VR128:$src1,
1684 f128mem:$src2, i8imm:$src3),
1685 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1687 (v2f64 (vector_shuffle
1688 VR128:$src1, (memopv2f64 addr:$src2),
1689 SHUFP_shuffle_mask:$src3)))]>;
1691 let AddedComplexity = 10 in {
1692 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1693 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1694 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1696 (v2f64 (vector_shuffle
1697 VR128:$src1, VR128:$src2,
1698 UNPCKH_shuffle_mask)))]>;
1699 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1700 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1701 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1703 (v2f64 (vector_shuffle
1704 VR128:$src1, (memopv2f64 addr:$src2),
1705 UNPCKH_shuffle_mask)))]>;
1707 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1708 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1709 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1711 (v2f64 (vector_shuffle
1712 VR128:$src1, VR128:$src2,
1713 UNPCKL_shuffle_mask)))]>;
1714 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1715 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1716 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1718 (v2f64 (vector_shuffle
1719 VR128:$src1, (memopv2f64 addr:$src2),
1720 UNPCKL_shuffle_mask)))]>;
1721 } // AddedComplexity
1722 } // Constraints = "$src1 = $dst"
1725 //===----------------------------------------------------------------------===//
1726 // SSE integer instructions
1728 // Move Instructions
1729 let neverHasSideEffects = 1 in
1730 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1731 "movdqa\t{$src, $dst|$dst, $src}", []>;
1732 let isSimpleLoad = 1, mayLoad = 1 in
1733 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1734 "movdqa\t{$src, $dst|$dst, $src}",
1735 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1737 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1738 "movdqa\t{$src, $dst|$dst, $src}",
1739 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1740 let isSimpleLoad = 1, mayLoad = 1 in
1741 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1742 "movdqu\t{$src, $dst|$dst, $src}",
1743 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1744 XS, Requires<[HasSSE2]>;
1746 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1747 "movdqu\t{$src, $dst|$dst, $src}",
1748 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1749 XS, Requires<[HasSSE2]>;
1751 // Intrinsic forms of MOVDQU load and store
1752 let isSimpleLoad = 1 in
1753 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1754 "movdqu\t{$src, $dst|$dst, $src}",
1755 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1756 XS, Requires<[HasSSE2]>;
1757 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1758 "movdqu\t{$src, $dst|$dst, $src}",
1759 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1760 XS, Requires<[HasSSE2]>;
1762 let Constraints = "$src1 = $dst" in {
1764 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1765 bit Commutable = 0> {
1766 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1767 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1768 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1769 let isCommutable = Commutable;
1771 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1772 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1773 [(set VR128:$dst, (IntId VR128:$src1,
1774 (bitconvert (memopv2i64 addr:$src2))))]>;
1777 /// PDI_binop_rm - Simple SSE2 binary operator.
1778 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1779 ValueType OpVT, bit Commutable = 0> {
1780 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1781 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1782 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1783 let isCommutable = Commutable;
1785 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1786 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1787 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1788 (bitconvert (memopv2i64 addr:$src2)))))]>;
1791 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1793 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1794 /// to collapse (bitconvert VT to VT) into its operand.
1796 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1797 bit Commutable = 0> {
1798 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1799 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1800 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1801 let isCommutable = Commutable;
1803 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1804 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1805 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1808 } // Constraints = "$src1 = $dst"
1810 // 128-bit Integer Arithmetic
1812 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1813 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1814 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1815 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1817 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1818 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1819 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1820 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1822 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1823 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1824 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1825 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1827 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1828 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1829 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1830 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1832 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1834 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1835 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1836 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1838 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1840 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1841 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1844 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1845 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1846 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1847 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1848 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1851 defm PSLLW : PDI_binop_rm_int<0xF1, "psllw", int_x86_sse2_psll_w>;
1852 defm PSLLD : PDI_binop_rm_int<0xF2, "pslld", int_x86_sse2_psll_d>;
1853 defm PSLLQ : PDI_binop_rm_int<0xF3, "psllq", int_x86_sse2_psll_q>;
1855 defm PSRLW : PDI_binop_rm_int<0xD1, "psrlw", int_x86_sse2_psrl_w>;
1856 defm PSRLD : PDI_binop_rm_int<0xD2, "psrld", int_x86_sse2_psrl_d>;
1857 defm PSRLQ : PDI_binop_rm_int<0xD3, "psrlq", int_x86_sse2_psrl_q>;
1859 defm PSRAW : PDI_binop_rm_int<0xE1, "psraw", int_x86_sse2_psra_w>;
1860 defm PSRAD : PDI_binop_rm_int<0xE2, "psrad", int_x86_sse2_psra_d>;
1862 // Some immediate variants need to match a bit_convert.
1863 let Constraints = "$src1 = $dst" in {
1864 def PSLLWri : PDIi8<0x71, MRM6r, (outs VR128:$dst),
1865 (ins VR128:$src1, i32i8imm:$src2),
1866 "psllw\t{$src2, $dst|$dst, $src2}",
1867 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1868 (bc_v8i16 (v4i32 (scalar_to_vector (i32 imm:$src2))))))]>;
1869 def PSLLDri : PDIi8<0x72, MRM6r, (outs VR128:$dst),
1870 (ins VR128:$src1, i32i8imm:$src2),
1871 "pslld\t{$src2, $dst|$dst, $src2}",
1872 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1873 (scalar_to_vector (i32 imm:$src2))))]>;
1874 def PSLLQri : PDIi8<0x73, MRM6r, (outs VR128:$dst),
1875 (ins VR128:$src1, i32i8imm:$src2),
1876 "psllq\t{$src2, $dst|$dst, $src2}",
1877 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1878 (bc_v2i64 (v4i32 (scalar_to_vector (i32 imm:$src2))))))]>;
1880 def PSRLWri : PDIi8<0x71, MRM2r, (outs VR128:$dst),
1881 (ins VR128:$src1, i32i8imm:$src2),
1882 "psrlw\t{$src2, $dst|$dst, $src2}",
1883 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1884 (bc_v8i16 (v4i32 (scalar_to_vector (i32 imm:$src2))))))]>;
1885 def PSRLDri : PDIi8<0x72, MRM2r, (outs VR128:$dst),
1886 (ins VR128:$src1, i32i8imm:$src2),
1887 "psrld\t{$src2, $dst|$dst, $src2}",
1888 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1889 (scalar_to_vector (i32 imm:$src2))))]>;
1890 def PSRLQri : PDIi8<0x73, MRM2r, (outs VR128:$dst),
1891 (ins VR128:$src1, i32i8imm:$src2),
1892 "psrlq\t{$src2, $dst|$dst, $src2}",
1893 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1894 (bc_v2i64 (v4i32 (scalar_to_vector (i32 imm:$src2))))))]>;
1896 def PSRAWri : PDIi8<0x71, MRM4r, (outs VR128:$dst),
1897 (ins VR128:$src1, i32i8imm:$src2),
1898 "psraw\t{$src2, $dst|$dst, $src2}",
1899 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1900 (bc_v8i16 (v4i32 (scalar_to_vector (i32 imm:$src2))))))]>;
1901 def PSRADri : PDIi8<0x72, MRM4r, (outs VR128:$dst),
1902 (ins VR128:$src1, i32i8imm:$src2),
1903 "psrad\t{$src2, $dst|$dst, $src2}",
1904 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1905 (scalar_to_vector (i32 imm:$src2))))]>;
1908 // PSRAQ doesn't exist in SSE[1-3].
1910 // 128-bit logical shifts.
1911 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1912 def PSLLDQri : PDIi8<0x73, MRM7r,
1913 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1914 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1915 def PSRLDQri : PDIi8<0x73, MRM3r,
1916 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1917 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1918 // PSRADQri doesn't exist in SSE[1-3].
1921 let Predicates = [HasSSE2] in {
1922 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1923 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1924 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1925 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1926 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1927 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1931 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1932 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1933 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1935 let Constraints = "$src1 = $dst" in {
1936 def PANDNrr : PDI<0xDF, MRMSrcReg,
1937 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1938 "pandn\t{$src2, $dst|$dst, $src2}",
1939 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1942 def PANDNrm : PDI<0xDF, MRMSrcMem,
1943 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1944 "pandn\t{$src2, $dst|$dst, $src2}",
1945 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1946 (memopv2i64 addr:$src2))))]>;
1949 // SSE2 Integer comparison
1950 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1951 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1952 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1953 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1954 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1955 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1957 // Pack instructions
1958 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1959 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1960 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1962 // Shuffle and unpack instructions
1963 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1964 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1965 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1966 [(set VR128:$dst, (v4i32 (vector_shuffle
1967 VR128:$src1, (undef),
1968 PSHUFD_shuffle_mask:$src2)))]>;
1969 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1970 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1971 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1972 [(set VR128:$dst, (v4i32 (vector_shuffle
1973 (bc_v4i32(memopv2i64 addr:$src1)),
1975 PSHUFD_shuffle_mask:$src2)))]>;
1977 // SSE2 with ImmT == Imm8 and XS prefix.
1978 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1979 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1980 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1981 [(set VR128:$dst, (v8i16 (vector_shuffle
1982 VR128:$src1, (undef),
1983 PSHUFHW_shuffle_mask:$src2)))]>,
1984 XS, Requires<[HasSSE2]>;
1985 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1986 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1987 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1988 [(set VR128:$dst, (v8i16 (vector_shuffle
1989 (bc_v8i16 (memopv2i64 addr:$src1)),
1991 PSHUFHW_shuffle_mask:$src2)))]>,
1992 XS, Requires<[HasSSE2]>;
1994 // SSE2 with ImmT == Imm8 and XD prefix.
1995 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1996 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1997 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1998 [(set VR128:$dst, (v8i16 (vector_shuffle
1999 VR128:$src1, (undef),
2000 PSHUFLW_shuffle_mask:$src2)))]>,
2001 XD, Requires<[HasSSE2]>;
2002 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2003 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2004 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2005 [(set VR128:$dst, (v8i16 (vector_shuffle
2006 (bc_v8i16 (memopv2i64 addr:$src1)),
2008 PSHUFLW_shuffle_mask:$src2)))]>,
2009 XD, Requires<[HasSSE2]>;
2012 let Constraints = "$src1 = $dst" in {
2013 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2014 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2015 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2017 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2018 UNPCKL_shuffle_mask)))]>;
2019 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2020 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2021 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2023 (v16i8 (vector_shuffle VR128:$src1,
2024 (bc_v16i8 (memopv2i64 addr:$src2)),
2025 UNPCKL_shuffle_mask)))]>;
2026 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2027 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2028 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2030 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2031 UNPCKL_shuffle_mask)))]>;
2032 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2033 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2034 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2036 (v8i16 (vector_shuffle VR128:$src1,
2037 (bc_v8i16 (memopv2i64 addr:$src2)),
2038 UNPCKL_shuffle_mask)))]>;
2039 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2040 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2041 "punpckldq\t{$src2, $dst|$dst, $src2}",
2043 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2044 UNPCKL_shuffle_mask)))]>;
2045 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2046 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2047 "punpckldq\t{$src2, $dst|$dst, $src2}",
2049 (v4i32 (vector_shuffle VR128:$src1,
2050 (bc_v4i32 (memopv2i64 addr:$src2)),
2051 UNPCKL_shuffle_mask)))]>;
2052 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2053 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2054 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2056 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2057 UNPCKL_shuffle_mask)))]>;
2058 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2059 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2060 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2062 (v2i64 (vector_shuffle VR128:$src1,
2063 (memopv2i64 addr:$src2),
2064 UNPCKL_shuffle_mask)))]>;
2066 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2067 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2068 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2070 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2071 UNPCKH_shuffle_mask)))]>;
2072 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2073 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2074 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2076 (v16i8 (vector_shuffle VR128:$src1,
2077 (bc_v16i8 (memopv2i64 addr:$src2)),
2078 UNPCKH_shuffle_mask)))]>;
2079 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2080 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2081 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2083 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2084 UNPCKH_shuffle_mask)))]>;
2085 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2086 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2087 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2089 (v8i16 (vector_shuffle VR128:$src1,
2090 (bc_v8i16 (memopv2i64 addr:$src2)),
2091 UNPCKH_shuffle_mask)))]>;
2092 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2093 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2094 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2096 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2097 UNPCKH_shuffle_mask)))]>;
2098 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2099 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2100 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2102 (v4i32 (vector_shuffle VR128:$src1,
2103 (bc_v4i32 (memopv2i64 addr:$src2)),
2104 UNPCKH_shuffle_mask)))]>;
2105 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2106 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2107 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2109 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2110 UNPCKH_shuffle_mask)))]>;
2111 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2112 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2113 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2115 (v2i64 (vector_shuffle VR128:$src1,
2116 (memopv2i64 addr:$src2),
2117 UNPCKH_shuffle_mask)))]>;
2121 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2122 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2123 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2124 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2126 let Constraints = "$src1 = $dst" in {
2127 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2128 (outs VR128:$dst), (ins VR128:$src1,
2129 GR32:$src2, i32i8imm:$src3),
2130 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2132 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2133 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2134 (outs VR128:$dst), (ins VR128:$src1,
2135 i16mem:$src2, i32i8imm:$src3),
2136 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2138 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2143 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2144 "pmovmskb\t{$src, $dst|$dst, $src}",
2145 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2147 // Conditional store
2149 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2150 "maskmovdqu\t{$mask, $src|$src, $mask}",
2151 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2153 // Non-temporal stores
2154 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2155 "movntpd\t{$src, $dst|$dst, $src}",
2156 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2157 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2158 "movntdq\t{$src, $dst|$dst, $src}",
2159 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2160 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2161 "movnti\t{$src, $dst|$dst, $src}",
2162 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2163 TB, Requires<[HasSSE2]>;
2166 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2167 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2168 TB, Requires<[HasSSE2]>;
2170 // Load, store, and memory fence
2171 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2172 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2173 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2174 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2176 //TODO: custom lower this so as to never even generate the noop
2177 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2179 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2180 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2181 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2184 // Alias instructions that map zero vector to pxor / xorp* for sse.
2185 let isReMaterializable = 1 in
2186 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2187 "pcmpeqd\t$dst, $dst",
2188 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2190 // FR64 to 128-bit vector conversion.
2191 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2192 "movsd\t{$src, $dst|$dst, $src}",
2194 (v2f64 (scalar_to_vector FR64:$src)))]>;
2195 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2196 "movsd\t{$src, $dst|$dst, $src}",
2198 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2200 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2201 "movd\t{$src, $dst|$dst, $src}",
2203 (v4i32 (scalar_to_vector GR32:$src)))]>;
2204 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2205 "movd\t{$src, $dst|$dst, $src}",
2207 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2209 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2210 "movd\t{$src, $dst|$dst, $src}",
2211 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2213 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2214 "movd\t{$src, $dst|$dst, $src}",
2215 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2217 // SSE2 instructions with XS prefix
2218 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2219 "movq\t{$src, $dst|$dst, $src}",
2221 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2222 Requires<[HasSSE2]>;
2223 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2224 "movq\t{$src, $dst|$dst, $src}",
2225 [(store (i64 (vector_extract (v2i64 VR128:$src),
2226 (iPTR 0))), addr:$dst)]>;
2228 // FIXME: may not be able to eliminate this movss with coalescing the src and
2229 // dest register classes are different. We really want to write this pattern
2231 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2232 // (f32 FR32:$src)>;
2233 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2234 "movsd\t{$src, $dst|$dst, $src}",
2235 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2237 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2238 "movsd\t{$src, $dst|$dst, $src}",
2239 [(store (f64 (vector_extract (v2f64 VR128:$src),
2240 (iPTR 0))), addr:$dst)]>;
2241 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2242 "movd\t{$src, $dst|$dst, $src}",
2243 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2245 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2246 "movd\t{$src, $dst|$dst, $src}",
2247 [(store (i32 (vector_extract (v4i32 VR128:$src),
2248 (iPTR 0))), addr:$dst)]>;
2250 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2251 "movd\t{$src, $dst|$dst, $src}",
2252 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2253 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2254 "movd\t{$src, $dst|$dst, $src}",
2255 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2258 // Move to lower bits of a VR128, leaving upper bits alone.
2259 // Three operand (but two address) aliases.
2260 let Constraints = "$src1 = $dst" in {
2261 let neverHasSideEffects = 1 in
2262 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2263 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2264 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2266 let AddedComplexity = 15 in
2267 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2268 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2269 "movsd\t{$src2, $dst|$dst, $src2}",
2271 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2272 MOVL_shuffle_mask)))]>;
2275 // Store / copy lower 64-bits of a XMM register.
2276 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2277 "movq\t{$src, $dst|$dst, $src}",
2278 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2280 // Move to lower bits of a VR128 and zeroing upper bits.
2281 // Loading from memory automatically zeroing upper bits.
2282 let AddedComplexity = 20 in
2283 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2284 "movsd\t{$src, $dst|$dst, $src}",
2286 (v2f64 (vector_shuffle immAllZerosV_bc,
2287 (v2f64 (scalar_to_vector
2288 (loadf64 addr:$src))),
2289 MOVL_shuffle_mask)))]>;
2291 // movd / movq to XMM register zero-extends
2292 let AddedComplexity = 15 in {
2293 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2294 "movd\t{$src, $dst|$dst, $src}",
2296 (v4i32 (vector_shuffle immAllZerosV,
2297 (v4i32 (scalar_to_vector GR32:$src)),
2298 MOVL_shuffle_mask)))]>;
2299 // This is X86-64 only.
2300 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2301 "mov{d|q}\t{$src, $dst|$dst, $src}",
2303 (v2i64 (vector_shuffle immAllZerosV_bc,
2304 (v2i64 (scalar_to_vector GR64:$src)),
2305 MOVL_shuffle_mask)))]>;
2308 // Handle the v2f64 form of 'MOVZQI2PQIrr' for PR2108. FIXME: this would be
2309 // better written as a dag combine xform.
2310 let AddedComplexity = 15 in
2311 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc,
2312 (v2f64 (scalar_to_vector
2313 (f64 (bitconvert GR64:$src)))),
2314 MOVL_shuffle_mask)),
2315 (MOVZQI2PQIrr GR64:$src)>, Requires<[HasSSE2]>;
2318 let AddedComplexity = 20 in {
2319 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2320 "movd\t{$src, $dst|$dst, $src}",
2322 (v4i32 (vector_shuffle immAllZerosV,
2323 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
2324 MOVL_shuffle_mask)))]>;
2325 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2326 "movq\t{$src, $dst|$dst, $src}",
2328 (v2i64 (vector_shuffle immAllZerosV_bc,
2329 (v2i64 (scalar_to_vector (loadi64 addr:$src))),
2330 MOVL_shuffle_mask)))]>, XS,
2331 Requires<[HasSSE2]>;
2334 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2335 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2336 let AddedComplexity = 15 in
2337 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2338 "movq\t{$src, $dst|$dst, $src}",
2339 [(set VR128:$dst, (v2i64 (vector_shuffle immAllZerosV_bc,
2341 MOVL_shuffle_mask)))]>,
2342 XS, Requires<[HasSSE2]>;
2344 let AddedComplexity = 20 in
2345 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2346 "movq\t{$src, $dst|$dst, $src}",
2347 [(set VR128:$dst, (v2i64 (vector_shuffle immAllZerosV_bc,
2348 (memopv2i64 addr:$src),
2349 MOVL_shuffle_mask)))]>,
2350 XS, Requires<[HasSSE2]>;
2352 //===----------------------------------------------------------------------===//
2353 // SSE3 Instructions
2354 //===----------------------------------------------------------------------===//
2356 // Move Instructions
2357 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2358 "movshdup\t{$src, $dst|$dst, $src}",
2359 [(set VR128:$dst, (v4f32 (vector_shuffle
2360 VR128:$src, (undef),
2361 MOVSHDUP_shuffle_mask)))]>;
2362 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2363 "movshdup\t{$src, $dst|$dst, $src}",
2364 [(set VR128:$dst, (v4f32 (vector_shuffle
2365 (memopv4f32 addr:$src), (undef),
2366 MOVSHDUP_shuffle_mask)))]>;
2368 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2369 "movsldup\t{$src, $dst|$dst, $src}",
2370 [(set VR128:$dst, (v4f32 (vector_shuffle
2371 VR128:$src, (undef),
2372 MOVSLDUP_shuffle_mask)))]>;
2373 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2374 "movsldup\t{$src, $dst|$dst, $src}",
2375 [(set VR128:$dst, (v4f32 (vector_shuffle
2376 (memopv4f32 addr:$src), (undef),
2377 MOVSLDUP_shuffle_mask)))]>;
2379 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2380 "movddup\t{$src, $dst|$dst, $src}",
2381 [(set VR128:$dst, (v2f64 (vector_shuffle
2382 VR128:$src, (undef),
2383 SSE_splat_lo_mask)))]>;
2384 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2385 "movddup\t{$src, $dst|$dst, $src}",
2387 (v2f64 (vector_shuffle
2388 (scalar_to_vector (loadf64 addr:$src)),
2390 SSE_splat_lo_mask)))]>;
2393 let Constraints = "$src1 = $dst" in {
2394 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2395 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2396 "addsubps\t{$src2, $dst|$dst, $src2}",
2397 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2399 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2400 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2401 "addsubps\t{$src2, $dst|$dst, $src2}",
2402 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2403 (load addr:$src2)))]>;
2404 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2405 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2406 "addsubpd\t{$src2, $dst|$dst, $src2}",
2407 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2409 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2410 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2411 "addsubpd\t{$src2, $dst|$dst, $src2}",
2412 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2413 (load addr:$src2)))]>;
2416 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2417 "lddqu\t{$src, $dst|$dst, $src}",
2418 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2421 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2422 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2423 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2424 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2425 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2426 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2427 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2428 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
2429 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2430 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2431 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2432 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2433 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2434 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2435 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2436 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
2438 let Constraints = "$src1 = $dst" in {
2439 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2440 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2441 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2442 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2443 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2444 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2445 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2446 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2449 // Thread synchronization
2450 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2451 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2452 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2453 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2455 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2456 let AddedComplexity = 15 in
2457 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2458 MOVSHDUP_shuffle_mask)),
2459 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2460 let AddedComplexity = 20 in
2461 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2462 MOVSHDUP_shuffle_mask)),
2463 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2465 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2466 let AddedComplexity = 15 in
2467 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2468 MOVSLDUP_shuffle_mask)),
2469 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2470 let AddedComplexity = 20 in
2471 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2472 MOVSLDUP_shuffle_mask)),
2473 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2475 //===----------------------------------------------------------------------===//
2476 // SSSE3 Instructions
2477 //===----------------------------------------------------------------------===//
2479 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2480 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2481 Intrinsic IntId64, Intrinsic IntId128> {
2482 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2483 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2484 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2486 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2487 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2489 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2491 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2493 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2494 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2497 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2499 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2502 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2505 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2506 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2507 Intrinsic IntId64, Intrinsic IntId128> {
2508 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2510 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2511 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2513 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2515 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2518 (bitconvert (memopv4i16 addr:$src))))]>;
2520 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2522 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2523 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2526 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2528 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2531 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2534 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2535 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2536 Intrinsic IntId64, Intrinsic IntId128> {
2537 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2539 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2540 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2542 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2544 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2547 (bitconvert (memopv2i32 addr:$src))))]>;
2549 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2551 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2552 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2555 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2557 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2560 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2563 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2564 int_x86_ssse3_pabs_b,
2565 int_x86_ssse3_pabs_b_128>;
2566 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2567 int_x86_ssse3_pabs_w,
2568 int_x86_ssse3_pabs_w_128>;
2569 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2570 int_x86_ssse3_pabs_d,
2571 int_x86_ssse3_pabs_d_128>;
2573 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2574 let Constraints = "$src1 = $dst" in {
2575 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2576 Intrinsic IntId64, Intrinsic IntId128,
2577 bit Commutable = 0> {
2578 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2579 (ins VR64:$src1, VR64:$src2),
2580 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2581 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2582 let isCommutable = Commutable;
2584 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2585 (ins VR64:$src1, i64mem:$src2),
2586 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2588 (IntId64 VR64:$src1,
2589 (bitconvert (memopv8i8 addr:$src2))))]>;
2591 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2592 (ins VR128:$src1, VR128:$src2),
2593 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2594 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2596 let isCommutable = Commutable;
2598 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2599 (ins VR128:$src1, i128mem:$src2),
2600 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2602 (IntId128 VR128:$src1,
2603 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2607 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2608 let Constraints = "$src1 = $dst" in {
2609 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2610 Intrinsic IntId64, Intrinsic IntId128,
2611 bit Commutable = 0> {
2612 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2613 (ins VR64:$src1, VR64:$src2),
2614 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2615 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2616 let isCommutable = Commutable;
2618 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2619 (ins VR64:$src1, i64mem:$src2),
2620 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2622 (IntId64 VR64:$src1,
2623 (bitconvert (memopv4i16 addr:$src2))))]>;
2625 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2626 (ins VR128:$src1, VR128:$src2),
2627 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2628 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2630 let isCommutable = Commutable;
2632 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2633 (ins VR128:$src1, i128mem:$src2),
2634 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2636 (IntId128 VR128:$src1,
2637 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2641 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2642 let Constraints = "$src1 = $dst" in {
2643 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2644 Intrinsic IntId64, Intrinsic IntId128,
2645 bit Commutable = 0> {
2646 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2647 (ins VR64:$src1, VR64:$src2),
2648 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2649 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2650 let isCommutable = Commutable;
2652 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2653 (ins VR64:$src1, i64mem:$src2),
2654 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2656 (IntId64 VR64:$src1,
2657 (bitconvert (memopv2i32 addr:$src2))))]>;
2659 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2660 (ins VR128:$src1, VR128:$src2),
2661 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2662 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2664 let isCommutable = Commutable;
2666 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2667 (ins VR128:$src1, i128mem:$src2),
2668 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2670 (IntId128 VR128:$src1,
2671 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2675 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2676 int_x86_ssse3_phadd_w,
2677 int_x86_ssse3_phadd_w_128, 1>;
2678 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2679 int_x86_ssse3_phadd_d,
2680 int_x86_ssse3_phadd_d_128, 1>;
2681 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2682 int_x86_ssse3_phadd_sw,
2683 int_x86_ssse3_phadd_sw_128, 1>;
2684 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2685 int_x86_ssse3_phsub_w,
2686 int_x86_ssse3_phsub_w_128>;
2687 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2688 int_x86_ssse3_phsub_d,
2689 int_x86_ssse3_phsub_d_128>;
2690 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2691 int_x86_ssse3_phsub_sw,
2692 int_x86_ssse3_phsub_sw_128>;
2693 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2694 int_x86_ssse3_pmadd_ub_sw,
2695 int_x86_ssse3_pmadd_ub_sw_128, 1>;
2696 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2697 int_x86_ssse3_pmul_hr_sw,
2698 int_x86_ssse3_pmul_hr_sw_128, 1>;
2699 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2700 int_x86_ssse3_pshuf_b,
2701 int_x86_ssse3_pshuf_b_128>;
2702 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2703 int_x86_ssse3_psign_b,
2704 int_x86_ssse3_psign_b_128>;
2705 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2706 int_x86_ssse3_psign_w,
2707 int_x86_ssse3_psign_w_128>;
2708 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2709 int_x86_ssse3_psign_d,
2710 int_x86_ssse3_psign_d_128>;
2712 let Constraints = "$src1 = $dst" in {
2713 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2714 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2715 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2717 (int_x86_ssse3_palign_r
2718 VR64:$src1, VR64:$src2,
2720 def PALIGNR64rm : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2721 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2722 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2724 (int_x86_ssse3_palign_r
2726 (bitconvert (memopv2i32 addr:$src2)),
2729 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2730 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2731 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2733 (int_x86_ssse3_palign_r_128
2734 VR128:$src1, VR128:$src2,
2735 imm:$src3))]>, OpSize;
2736 def PALIGNR128rm : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2737 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2738 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2740 (int_x86_ssse3_palign_r_128
2742 (bitconvert (memopv4i32 addr:$src2)),
2743 imm:$src3))]>, OpSize;
2746 //===----------------------------------------------------------------------===//
2747 // Non-Instruction Patterns
2748 //===----------------------------------------------------------------------===//
2750 // extload f32 -> f64. This matches load+fextend because we have a hack in
2751 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2752 // Since these loads aren't folded into the fextend, we have to match it
2754 let Predicates = [HasSSE2] in
2755 def : Pat<(fextend (loadf32 addr:$src)),
2756 (CVTSS2SDrm addr:$src)>;
2759 let Predicates = [HasSSE2] in {
2760 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2761 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2762 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2763 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2764 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2765 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2766 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2767 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2768 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2769 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2770 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2771 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2772 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2773 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2774 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2775 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2776 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2777 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2778 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2779 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2780 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2781 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2782 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2783 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2784 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2785 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2786 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2787 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2788 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2789 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2792 // Move scalar to XMM zero-extended
2793 // movd to XMM register zero-extends
2794 let AddedComplexity = 15 in {
2795 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2796 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc,
2797 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2798 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2799 def : Pat<(v4f32 (vector_shuffle immAllZerosV_bc,
2800 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2801 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2804 // Splat v2f64 / v2i64
2805 let AddedComplexity = 10 in {
2806 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2807 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2808 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2809 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2810 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2811 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2812 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2813 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2816 // Special unary SHUFPSrri case.
2817 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2818 SHUFP_unary_shuffle_mask:$sm)),
2819 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2820 Requires<[HasSSE1]>;
2821 // Special unary SHUFPDrri case.
2822 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2823 SHUFP_unary_shuffle_mask:$sm)),
2824 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2825 Requires<[HasSSE2]>;
2826 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2827 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2828 SHUFP_unary_shuffle_mask:$sm),
2829 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2830 Requires<[HasSSE2]>;
2831 // Special binary v4i32 shuffle cases with SHUFPS.
2832 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2833 PSHUFD_binary_shuffle_mask:$sm)),
2834 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2835 Requires<[HasSSE2]>;
2836 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2837 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2838 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2839 Requires<[HasSSE2]>;
2840 // Special binary v2i64 shuffle cases using SHUFPDrri.
2841 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2842 SHUFP_shuffle_mask:$sm)),
2843 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2844 Requires<[HasSSE2]>;
2845 // Special unary SHUFPDrri case.
2846 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2847 SHUFP_unary_shuffle_mask:$sm)),
2848 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2849 Requires<[HasSSE2]>;
2851 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2852 let AddedComplexity = 10 in {
2853 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2854 UNPCKL_v_undef_shuffle_mask)),
2855 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2856 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2857 UNPCKL_v_undef_shuffle_mask)),
2858 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2859 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2860 UNPCKL_v_undef_shuffle_mask)),
2861 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2862 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2863 UNPCKL_v_undef_shuffle_mask)),
2864 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2867 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2868 let AddedComplexity = 10 in {
2869 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2870 UNPCKH_v_undef_shuffle_mask)),
2871 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2872 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2873 UNPCKH_v_undef_shuffle_mask)),
2874 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2875 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2876 UNPCKH_v_undef_shuffle_mask)),
2877 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2878 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2879 UNPCKH_v_undef_shuffle_mask)),
2880 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2883 let AddedComplexity = 15 in {
2884 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2885 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2886 MOVHP_shuffle_mask)),
2887 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2889 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2890 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2891 MOVHLPS_shuffle_mask)),
2892 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2894 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2895 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2896 MOVHLPS_v_undef_shuffle_mask)),
2897 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2898 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2899 MOVHLPS_v_undef_shuffle_mask)),
2900 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2903 let AddedComplexity = 20 in {
2904 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2905 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2906 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2907 MOVLP_shuffle_mask)),
2908 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2909 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2910 MOVLP_shuffle_mask)),
2911 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2912 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2913 MOVHP_shuffle_mask)),
2914 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2915 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2916 MOVHP_shuffle_mask)),
2917 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2919 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2920 MOVLP_shuffle_mask)),
2921 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2922 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2923 MOVLP_shuffle_mask)),
2924 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2925 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2926 MOVHP_shuffle_mask)),
2927 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2928 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2929 MOVLP_shuffle_mask)),
2930 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2933 let AddedComplexity = 15 in {
2934 // Setting the lowest element in the vector.
2935 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2936 MOVL_shuffle_mask)),
2937 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2938 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2939 MOVL_shuffle_mask)),
2940 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2942 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2943 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2944 MOVLP_shuffle_mask)),
2945 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2946 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2947 MOVLP_shuffle_mask)),
2948 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2951 // Set lowest element and zero upper elements.
2952 let AddedComplexity = 15 in
2953 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
2954 MOVL_shuffle_mask)),
2955 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
2958 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2959 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2960 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2961 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2962 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2963 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2964 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2965 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2966 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2967 Requires<[HasSSE2]>;
2968 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2969 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2970 Requires<[HasSSE2]>;
2971 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2972 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2973 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2974 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2975 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2976 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2977 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2978 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2979 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2980 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2981 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2982 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2983 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2984 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2985 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2986 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2988 // Some special case pandn patterns.
2989 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2991 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2992 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2994 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2995 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2997 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2999 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3000 (memopv2i64 addr:$src2))),
3001 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3002 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3003 (memopv2i64 addr:$src2))),
3004 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3005 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3006 (memopv2i64 addr:$src2))),
3007 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3009 // vector -> vector casts
3010 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3011 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3012 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3013 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3015 // Use movaps / movups for SSE integer load / store (one byte shorter).
3016 def : Pat<(alignedloadv4i32 addr:$src),
3017 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3018 def : Pat<(loadv4i32 addr:$src),
3019 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3020 def : Pat<(alignedloadv2i64 addr:$src),
3021 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3022 def : Pat<(loadv2i64 addr:$src),
3023 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3025 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3026 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3027 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3028 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3029 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3030 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3031 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3032 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3033 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3034 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3035 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3036 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3037 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3038 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3039 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3040 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3042 //===----------------------------------------------------------------------===//
3043 // SSE4.1 Instructions
3044 //===----------------------------------------------------------------------===//
3046 multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
3047 bits<8> opcsd, bits<8> opcpd,
3052 Intrinsic V2F64Int> {
3053 // Intrinsic operation, reg.
3054 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3055 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3056 !strconcat(OpcodeStr,
3057 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3058 [(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
3061 // Intrinsic operation, mem.
3062 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3063 (outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
3064 !strconcat(OpcodeStr,
3065 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3066 [(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
3069 // Vector intrinsic operation, reg
3070 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3071 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3072 !strconcat(OpcodeStr,
3073 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3074 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3077 // Vector intrinsic operation, mem
3078 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3079 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3080 !strconcat(OpcodeStr,
3081 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3082 [(set VR128:$dst, (V4F32Int (load addr:$src1),imm:$src2))]>,
3085 // Intrinsic operation, reg.
3086 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3087 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3088 !strconcat(OpcodeStr,
3089 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3090 [(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
3093 // Intrinsic operation, mem.
3094 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3095 (outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
3096 !strconcat(OpcodeStr,
3097 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3098 [(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
3101 // Vector intrinsic operation, reg
3102 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3103 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3104 !strconcat(OpcodeStr,
3105 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3106 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3109 // Vector intrinsic operation, mem
3110 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3111 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3112 !strconcat(OpcodeStr,
3113 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3114 [(set VR128:$dst, (V2F64Int (load addr:$src1),imm:$src2))]>,
3118 // FP round - roundss, roundps, roundsd, roundpd
3119 defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
3120 int_x86_sse41_round_ss, int_x86_sse41_round_ps,
3121 int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
3123 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3124 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3125 Intrinsic IntId128> {
3126 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3128 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3129 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3130 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3132 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3135 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3138 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3139 int_x86_sse41_phminposuw>;
3141 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3142 let Constraints = "$src1 = $dst" in {
3143 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3144 Intrinsic IntId128, bit Commutable = 0> {
3145 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3146 (ins VR128:$src1, VR128:$src2),
3147 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3148 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3150 let isCommutable = Commutable;
3152 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3153 (ins VR128:$src1, i128mem:$src2),
3154 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3156 (IntId128 VR128:$src1,
3157 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3161 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3162 int_x86_sse41_pcmpeqq, 1>;
3163 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3164 int_x86_sse41_packusdw, 0>;
3165 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3166 int_x86_sse41_pminsb, 1>;
3167 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3168 int_x86_sse41_pminsd, 1>;
3169 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3170 int_x86_sse41_pminud, 1>;
3171 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3172 int_x86_sse41_pminuw, 1>;
3173 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3174 int_x86_sse41_pmaxsb, 1>;
3175 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3176 int_x86_sse41_pmaxsd, 1>;
3177 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3178 int_x86_sse41_pmaxud, 1>;
3179 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3180 int_x86_sse41_pmaxuw, 1>;
3181 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq",
3182 int_x86_sse41_pmuldq, 1>;
3185 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3186 let Constraints = "$src1 = $dst" in {
3187 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, SDNode OpNode,
3188 Intrinsic IntId128, bit Commutable = 0> {
3189 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3190 (ins VR128:$src1, VR128:$src2),
3191 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3192 [(set VR128:$dst, (OpNode (v4i32 VR128:$src1),
3193 VR128:$src2))]>, OpSize {
3194 let isCommutable = Commutable;
3196 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3197 (ins VR128:$src1, VR128:$src2),
3198 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3199 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3201 let isCommutable = Commutable;
3203 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3204 (ins VR128:$src1, i128mem:$src2),
3205 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3207 (OpNode VR128:$src1, (memopv4i32 addr:$src2)))]>, OpSize;
3208 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3209 (ins VR128:$src1, i128mem:$src2),
3210 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3212 (IntId128 VR128:$src1, (memopv4i32 addr:$src2)))]>,
3216 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", mul,
3217 int_x86_sse41_pmulld, 1>;
3220 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3221 let Constraints = "$src1 = $dst" in {
3222 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3223 Intrinsic IntId128, bit Commutable = 0> {
3224 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3225 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3226 !strconcat(OpcodeStr,
3227 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3229 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3231 let isCommutable = Commutable;
3233 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3234 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3235 !strconcat(OpcodeStr,
3236 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3238 (IntId128 VR128:$src1,
3239 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3244 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3245 int_x86_sse41_blendps, 0>;
3246 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3247 int_x86_sse41_blendpd, 0>;
3248 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3249 int_x86_sse41_pblendw, 0>;
3250 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3251 int_x86_sse41_dpps, 1>;
3252 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3253 int_x86_sse41_dppd, 1>;
3254 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3255 int_x86_sse41_mpsadbw, 0>;
3258 /// SS41I_ternary_int - SSE 4.1 ternary operator
3259 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3260 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3261 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3262 (ins VR128:$src1, VR128:$src2),
3263 !strconcat(OpcodeStr,
3264 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3265 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3268 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3269 (ins VR128:$src1, i128mem:$src2),
3270 !strconcat(OpcodeStr,
3271 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3274 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3278 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3279 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3280 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3283 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3284 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3285 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3286 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3288 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3289 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3291 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3294 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3295 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3296 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3297 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3298 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3299 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3301 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3302 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3303 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3304 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3306 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3307 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3309 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3312 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3313 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3314 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3315 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3317 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3318 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3319 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3320 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3322 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3323 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3325 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3328 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3329 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3332 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3333 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3334 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3335 (ins VR128:$src1, i32i8imm:$src2),
3336 !strconcat(OpcodeStr,
3337 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3338 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3340 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3341 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3342 !strconcat(OpcodeStr,
3343 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3346 // There's an AssertZext in the way of writing the store pattern
3347 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3350 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3353 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3354 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3355 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3356 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3357 !strconcat(OpcodeStr,
3358 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3361 // There's an AssertZext in the way of writing the store pattern
3362 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3365 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3368 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3369 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3370 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3371 (ins VR128:$src1, i32i8imm:$src2),
3372 !strconcat(OpcodeStr,
3373 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3375 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3376 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3377 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3378 !strconcat(OpcodeStr,
3379 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3380 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3381 addr:$dst)]>, OpSize;
3384 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3387 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3389 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3390 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3391 (ins VR128:$src1, i32i8imm:$src2),
3392 !strconcat(OpcodeStr,
3393 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3395 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3397 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3398 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3399 !strconcat(OpcodeStr,
3400 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3401 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3402 addr:$dst)]>, OpSize;
3405 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3407 let Constraints = "$src1 = $dst" in {
3408 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3409 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3410 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3411 !strconcat(OpcodeStr,
3412 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3414 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3415 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3416 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3417 !strconcat(OpcodeStr,
3418 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3420 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3421 imm:$src3))]>, OpSize;
3425 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3427 let Constraints = "$src1 = $dst" in {
3428 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3429 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3430 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3431 !strconcat(OpcodeStr,
3432 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3434 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3436 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3437 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3438 !strconcat(OpcodeStr,
3439 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3441 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3442 imm:$src3)))]>, OpSize;
3446 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3448 let Constraints = "$src1 = $dst" in {
3449 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3450 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3451 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3452 !strconcat(OpcodeStr,
3453 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3455 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3456 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3457 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3458 !strconcat(OpcodeStr,
3459 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3461 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3462 imm:$src3))]>, OpSize;
3466 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3468 let Defs = [EFLAGS] in {
3469 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3470 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3471 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3472 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3475 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3476 "movntdqa\t{$src, $dst|$dst, $src}",
3477 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;