1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
24 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, [SDNPHasChain]>;
25 def X86loadu : SDNode<"X86ISD::LOAD_UA", SDTLoad, [SDNPHasChain]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
35 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
36 [SDNPHasChain, SDNPOutFlag]>;
37 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
38 [SDNPHasChain, SDNPOutFlag]>;
39 def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
40 def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
41 def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
43 //===----------------------------------------------------------------------===//
44 // SSE Complex Patterns
45 //===----------------------------------------------------------------------===//
47 // These are 'extloads' from a scalar to the low element of a vector, zeroing
48 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
50 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
52 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
55 def ssmem : Operand<v4f32> {
56 let PrintMethod = "printf32mem";
57 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
59 def sdmem : Operand<v2f64> {
60 let PrintMethod = "printf64mem";
61 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
64 //===----------------------------------------------------------------------===//
65 // SSE pattern fragments
66 //===----------------------------------------------------------------------===//
68 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
69 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
71 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
72 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
73 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
75 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
76 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
77 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
78 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
79 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
80 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
82 def fp32imm0 : PatLeaf<(f32 fpimm), [{
83 return N->isExactlyValue(+0.0);
86 def PSxLDQ_imm : SDNodeXForm<imm, [{
87 // Transformation function: imm >> 3
88 return getI32Imm(N->getValue() >> 3);
91 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
93 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
94 return getI8Imm(X86::getShuffleSHUFImmediate(N));
97 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
99 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
100 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
103 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
105 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
106 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
109 def SSE_splat_mask : PatLeaf<(build_vector), [{
110 return X86::isSplatMask(N);
111 }], SHUFFLE_get_shuf_imm>;
113 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
114 return X86::isSplatLoMask(N);
117 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
118 return X86::isMOVHLPSMask(N);
121 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
122 return X86::isMOVHLPS_v_undef_Mask(N);
125 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
126 return X86::isMOVHPMask(N);
129 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
130 return X86::isMOVLPMask(N);
133 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
134 return X86::isMOVLMask(N);
137 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
138 return X86::isMOVSHDUPMask(N);
141 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
142 return X86::isMOVSLDUPMask(N);
145 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
146 return X86::isUNPCKLMask(N);
149 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
150 return X86::isUNPCKHMask(N);
153 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
154 return X86::isUNPCKL_v_undef_Mask(N);
157 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
158 return X86::isPSHUFDMask(N);
159 }], SHUFFLE_get_shuf_imm>;
161 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
162 return X86::isPSHUFHWMask(N);
163 }], SHUFFLE_get_pshufhw_imm>;
165 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
166 return X86::isPSHUFLWMask(N);
167 }], SHUFFLE_get_pshuflw_imm>;
169 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
170 return X86::isPSHUFDMask(N);
171 }], SHUFFLE_get_shuf_imm>;
173 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
174 return X86::isSHUFPMask(N);
175 }], SHUFFLE_get_shuf_imm>;
177 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
178 return X86::isSHUFPMask(N);
179 }], SHUFFLE_get_shuf_imm>;
181 //===----------------------------------------------------------------------===//
182 // SSE scalar FP Instructions
183 //===----------------------------------------------------------------------===//
185 // Instruction templates
186 // SSI - SSE1 instructions with XS prefix.
187 // SDI - SSE2 instructions with XD prefix.
188 // PSI - SSE1 instructions with TB prefix.
189 // PDI - SSE2 instructions with TB and OpSize prefixes.
190 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
191 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
192 // S3I - SSE3 instructions with TB and OpSize prefixes.
193 // S3SI - SSE3 instructions with XS prefix.
194 // S3DI - SSE3 instructions with XD prefix.
195 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
196 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
197 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
198 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
199 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
200 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
201 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
202 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
203 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
204 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
205 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
206 : Ii8<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
208 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
209 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
210 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
211 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
212 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
213 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
215 //===----------------------------------------------------------------------===//
216 // Helpers for defining instructions that directly correspond to intrinsics.
218 multiclass SS_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
219 def r : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
220 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
221 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
222 def m : SSI<o, MRMSrcMem, (ops VR128:$dst, ssmem:$src),
223 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
224 [(set VR128:$dst, (v4f32 (IntId sse_load_f32:$src)))]>;
227 multiclass SD_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
228 def r : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
229 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
230 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
231 def m : SDI<o, MRMSrcMem, (ops VR128:$dst, sdmem:$src),
232 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
233 [(set VR128:$dst, (v2f64 (IntId sse_load_f64:$src)))]>;
236 class PS_Intr<bits<8> o, string OpcodeStr, Intrinsic IntId>
237 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
238 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
239 [(set VR128:$dst, (IntId VR128:$src))]>;
240 class PS_Intm<bits<8> o, string OpcodeStr, Intrinsic IntId>
241 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
242 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
243 [(set VR128:$dst, (IntId (load addr:$src)))]>;
244 class PD_Intr<bits<8> o, string OpcodeStr, Intrinsic IntId>
245 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
246 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
247 [(set VR128:$dst, (IntId VR128:$src))]>;
248 class PD_Intm<bits<8> o, string OpcodeStr, Intrinsic IntId>
249 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
250 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
251 [(set VR128:$dst, (IntId (load addr:$src)))]>;
253 class PS_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
254 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
255 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
256 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
257 class PS_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
258 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
259 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
260 [(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))]>;
261 class PD_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
262 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
263 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
264 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
265 class PD_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
266 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
267 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
268 [(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))]>;
270 // Some 'special' instructions
271 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
272 "#IMPLICIT_DEF $dst",
273 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
274 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
275 "#IMPLICIT_DEF $dst",
276 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
278 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
279 // scheduler into a branch sequence.
280 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
281 def CMOV_FR32 : I<0, Pseudo,
282 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
283 "#CMOV_FR32 PSEUDO!",
284 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
285 def CMOV_FR64 : I<0, Pseudo,
286 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
287 "#CMOV_FR64 PSEUDO!",
288 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
289 def CMOV_V4F32 : I<0, Pseudo,
290 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
291 "#CMOV_V4F32 PSEUDO!",
293 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
294 def CMOV_V2F64 : I<0, Pseudo,
295 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
296 "#CMOV_V2F64 PSEUDO!",
298 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
299 def CMOV_V2I64 : I<0, Pseudo,
300 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
301 "#CMOV_V2I64 PSEUDO!",
303 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
307 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
308 "movss {$src, $dst|$dst, $src}", []>;
309 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
310 "movss {$src, $dst|$dst, $src}",
311 [(set FR32:$dst, (loadf32 addr:$src))]>;
312 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
313 "movsd {$src, $dst|$dst, $src}", []>;
314 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
315 "movsd {$src, $dst|$dst, $src}",
316 [(set FR64:$dst, (loadf64 addr:$src))]>;
318 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
319 "movss {$src, $dst|$dst, $src}",
320 [(store FR32:$src, addr:$dst)]>;
321 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
322 "movsd {$src, $dst|$dst, $src}",
323 [(store FR64:$src, addr:$dst)]>;
325 /// scalar_sse12_fp_binop_rm - Scalar SSE binops come in four basic forms:
326 /// 1. f32 vs f64 - These come in SSE1/SSE2 forms for float/doubles.
327 /// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
329 /// In addition, scalar SSE ops have an intrinsic form. This form is unlike the
330 /// normal form, in that they take an entire vector (instead of a scalar) and
331 /// leave the top elements undefined. This adds another two variants of the
332 /// above permutations, giving us 8 forms for 'instruction'.
334 let isTwoAddress = 1 in {
335 multiclass scalar_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
336 SDNode OpNode, Intrinsic F32Int,
337 Intrinsic F64Int, bit Commutable = 0> {
338 // Scalar operation, reg+reg.
339 def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
340 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
341 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
342 let isCommutable = Commutable;
344 def SDrr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
345 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
346 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
347 let isCommutable = Commutable;
349 // Scalar operation, reg+mem.
350 def SSrm : SSI<opc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
351 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
352 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
353 def SDrm : SDI<opc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
354 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
355 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
357 // Vector intrinsic operation, reg+reg.
358 def SSrr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
359 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
360 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
361 let isCommutable = Commutable;
363 def SDrr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
364 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
365 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
366 let isCommutable = Commutable;
368 // Vector intrinsic operation, reg+mem.
369 def SSrm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2),
370 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
371 [(set VR128:$dst, (F32Int VR128:$src1,
372 sse_load_f32:$src2))]>;
373 def SDrm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2),
374 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
375 [(set VR128:$dst, (F64Int VR128:$src1,
376 sse_load_f64:$src2))]>;
380 // Arithmetic instructions
382 defm ADD : scalar_sse12_fp_binop_rm<0x58, "add", fadd,
383 int_x86_sse_add_ss, int_x86_sse2_add_sd, 1>;
384 defm MUL : scalar_sse12_fp_binop_rm<0x59, "mul", fmul,
385 int_x86_sse_mul_ss, int_x86_sse2_mul_sd, 1>;
386 defm SUB : scalar_sse12_fp_binop_rm<0x5C, "sub", fsub,
387 int_x86_sse_sub_ss, int_x86_sse2_sub_sd>;
388 defm DIV : scalar_sse12_fp_binop_rm<0x5E, "div", fdiv,
389 int_x86_sse_div_ss, int_x86_sse2_div_sd>;
391 defm MAX : scalar_sse12_fp_binop_rm<0x5F, "max", X86fmax,
392 int_x86_sse_max_ss, int_x86_sse2_max_sd>;
393 defm MIN : scalar_sse12_fp_binop_rm<0x5D, "min", X86fmin,
394 int_x86_sse_min_ss, int_x86_sse2_min_sd>;
397 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
398 "sqrtss {$src, $dst|$dst, $src}",
399 [(set FR32:$dst, (fsqrt FR32:$src))]>;
400 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
401 "sqrtss {$src, $dst|$dst, $src}",
402 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
403 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
404 "sqrtsd {$src, $dst|$dst, $src}",
405 [(set FR64:$dst, (fsqrt FR64:$src))]>;
406 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
407 "sqrtsd {$src, $dst|$dst, $src}",
408 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
410 // Aliases to match intrinsics which expect XMM operand(s).
412 defm SQRTSS_Int : SS_IntUnary<0x51, "sqrtss" , int_x86_sse_sqrt_ss>;
413 defm SQRTSD_Int : SD_IntUnary<0x51, "sqrtsd" , int_x86_sse2_sqrt_sd>;
414 defm RSQRTSS_Int : SS_IntUnary<0x52, "rsqrtss", int_x86_sse_rsqrt_ss>;
415 defm RCPSS_Int : SS_IntUnary<0x53, "rcpss" , int_x86_sse_rcp_ss>;
417 // Conversion instructions
418 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src),
419 "cvttss2si {$src, $dst|$dst, $src}",
420 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
421 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
422 "cvttss2si {$src, $dst|$dst, $src}",
423 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
424 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src),
425 "cvttsd2si {$src, $dst|$dst, $src}",
426 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
427 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src),
428 "cvttsd2si {$src, $dst|$dst, $src}",
429 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
430 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
431 "cvtsd2ss {$src, $dst|$dst, $src}",
432 [(set FR32:$dst, (fround FR64:$src))]>;
433 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
434 "cvtsd2ss {$src, $dst|$dst, $src}",
435 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
436 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src),
437 "cvtsi2ss {$src, $dst|$dst, $src}",
438 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
439 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
440 "cvtsi2ss {$src, $dst|$dst, $src}",
441 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
442 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src),
443 "cvtsi2sd {$src, $dst|$dst, $src}",
444 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
445 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
446 "cvtsi2sd {$src, $dst|$dst, $src}",
447 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
449 // SSE2 instructions with XS prefix
450 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
451 "cvtss2sd {$src, $dst|$dst, $src}",
452 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
454 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
455 "cvtss2sd {$src, $dst|$dst, $src}",
456 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
459 // Match intrinsics which expect XMM operand(s).
460 def Int_CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
461 "cvtss2si {$src, $dst|$dst, $src}",
462 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
463 def Int_CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
464 "cvtss2si {$src, $dst|$dst, $src}",
465 [(set GR32:$dst, (int_x86_sse_cvtss2si
466 (load addr:$src)))]>;
467 def Int_CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
468 "cvtsd2si {$src, $dst|$dst, $src}",
469 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
470 def Int_CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
471 "cvtsd2si {$src, $dst|$dst, $src}",
472 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
473 (load addr:$src)))]>;
475 // Aliases for intrinsics
476 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
477 "cvttss2si {$src, $dst|$dst, $src}",
478 [(set GR32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
479 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
480 "cvttss2si {$src, $dst|$dst, $src}",
481 [(set GR32:$dst, (int_x86_sse_cvttss2si(load addr:$src)))]>;
482 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
483 "cvttsd2si {$src, $dst|$dst, $src}",
484 [(set GR32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
485 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
486 "cvttsd2si {$src, $dst|$dst, $src}",
487 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
488 (load addr:$src)))]>;
490 let isTwoAddress = 1 in {
491 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
492 (ops VR128:$dst, VR128:$src1, GR32:$src2),
493 "cvtsi2ss {$src2, $dst|$dst, $src2}",
494 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
496 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
497 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
498 "cvtsi2ss {$src2, $dst|$dst, $src2}",
499 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
500 (loadi32 addr:$src2)))]>;
503 // Comparison instructions
504 let isTwoAddress = 1 in {
505 def CMPSSrr : SSI<0xC2, MRMSrcReg,
506 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
507 "cmp${cc}ss {$src, $dst|$dst, $src}",
509 def CMPSSrm : SSI<0xC2, MRMSrcMem,
510 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
511 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
512 def CMPSDrr : SDI<0xC2, MRMSrcReg,
513 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
514 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
515 def CMPSDrm : SDI<0xC2, MRMSrcMem,
516 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
517 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
520 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
521 "ucomiss {$src2, $src1|$src1, $src2}",
522 [(X86cmp FR32:$src1, FR32:$src2)]>;
523 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
524 "ucomiss {$src2, $src1|$src1, $src2}",
525 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
526 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
527 "ucomisd {$src2, $src1|$src1, $src2}",
528 [(X86cmp FR64:$src1, FR64:$src2)]>;
529 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
530 "ucomisd {$src2, $src1|$src1, $src2}",
531 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
533 // Aliases to match intrinsics which expect XMM operand(s).
534 let isTwoAddress = 1 in {
535 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
536 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
537 "cmp${cc}ss {$src, $dst|$dst, $src}",
538 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
539 VR128:$src, imm:$cc))]>;
540 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
541 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
542 "cmp${cc}ss {$src, $dst|$dst, $src}",
543 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
544 (load addr:$src), imm:$cc))]>;
545 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
546 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
547 "cmp${cc}sd {$src, $dst|$dst, $src}",
548 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
549 VR128:$src, imm:$cc))]>;
550 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
551 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
552 "cmp${cc}sd {$src, $dst|$dst, $src}",
553 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
554 (load addr:$src), imm:$cc))]>;
557 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
558 "ucomiss {$src2, $src1|$src1, $src2}",
559 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
560 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
561 "ucomiss {$src2, $src1|$src1, $src2}",
562 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>;
563 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
564 "ucomisd {$src2, $src1|$src1, $src2}",
565 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
566 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
567 "ucomisd {$src2, $src1|$src1, $src2}",
568 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>;
570 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
571 "comiss {$src2, $src1|$src1, $src2}",
572 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
573 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
574 "comiss {$src2, $src1|$src1, $src2}",
575 [(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>;
576 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
577 "comisd {$src2, $src1|$src1, $src2}",
578 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
579 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
580 "comisd {$src2, $src1|$src1, $src2}",
581 [(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
583 // Aliases of packed instructions for scalar use. These all have names that
586 // Alias instructions that map fld0 to pxor for sse.
587 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
588 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
589 Requires<[HasSSE1]>, TB, OpSize;
590 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
591 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
592 Requires<[HasSSE2]>, TB, OpSize;
594 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
595 // Upper bits are disregarded.
596 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
597 "movaps {$src, $dst|$dst, $src}", []>;
598 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
599 "movapd {$src, $dst|$dst, $src}", []>;
601 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
602 // Upper bits are disregarded.
603 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
604 "movaps {$src, $dst|$dst, $src}",
605 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
606 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
607 "movapd {$src, $dst|$dst, $src}",
608 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
610 // Alias bitwise logical operations using SSE logical ops on packed FP values.
611 let isTwoAddress = 1 in {
612 let isCommutable = 1 in {
613 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
614 "andps {$src2, $dst|$dst, $src2}",
615 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
616 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
617 "andpd {$src2, $dst|$dst, $src2}",
618 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
619 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
620 "orps {$src2, $dst|$dst, $src2}",
621 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
622 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
623 "orpd {$src2, $dst|$dst, $src2}",
624 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
625 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
626 "xorps {$src2, $dst|$dst, $src2}",
627 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
628 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
629 "xorpd {$src2, $dst|$dst, $src2}",
630 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
632 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
633 "andps {$src2, $dst|$dst, $src2}",
634 [(set FR32:$dst, (X86fand FR32:$src1,
635 (X86loadpf32 addr:$src2)))]>;
636 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
637 "andpd {$src2, $dst|$dst, $src2}",
638 [(set FR64:$dst, (X86fand FR64:$src1,
639 (X86loadpf64 addr:$src2)))]>;
640 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
641 "orps {$src2, $dst|$dst, $src2}",
642 [(set FR32:$dst, (X86for FR32:$src1,
643 (X86loadpf32 addr:$src2)))]>;
644 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
645 "orpd {$src2, $dst|$dst, $src2}",
646 [(set FR64:$dst, (X86for FR64:$src1,
647 (X86loadpf64 addr:$src2)))]>;
648 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
649 "xorps {$src2, $dst|$dst, $src2}",
650 [(set FR32:$dst, (X86fxor FR32:$src1,
651 (X86loadpf32 addr:$src2)))]>;
652 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
653 "xorpd {$src2, $dst|$dst, $src2}",
654 [(set FR64:$dst, (X86fxor FR64:$src1,
655 (X86loadpf64 addr:$src2)))]>;
657 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
658 "andnps {$src2, $dst|$dst, $src2}", []>;
659 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
660 "andnps {$src2, $dst|$dst, $src2}", []>;
661 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
662 "andnpd {$src2, $dst|$dst, $src2}", []>;
663 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
664 "andnpd {$src2, $dst|$dst, $src2}", []>;
667 //===----------------------------------------------------------------------===//
668 // SSE packed FP Instructions
669 //===----------------------------------------------------------------------===//
671 // Some 'special' instructions
672 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
673 "#IMPLICIT_DEF $dst",
674 [(set VR128:$dst, (v4f32 (undef)))]>,
678 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
679 "movaps {$src, $dst|$dst, $src}", []>;
680 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
681 "movaps {$src, $dst|$dst, $src}",
682 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
683 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
684 "movapd {$src, $dst|$dst, $src}", []>;
685 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
686 "movapd {$src, $dst|$dst, $src}",
687 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
689 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
690 "movaps {$src, $dst|$dst, $src}",
691 [(store (v4f32 VR128:$src), addr:$dst)]>;
692 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
693 "movapd {$src, $dst|$dst, $src}",
694 [(store (v2f64 VR128:$src), addr:$dst)]>;
696 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
697 "movups {$src, $dst|$dst, $src}", []>;
698 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
699 "movups {$src, $dst|$dst, $src}",
700 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
701 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
702 "movups {$src, $dst|$dst, $src}",
703 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
704 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
705 "movupd {$src, $dst|$dst, $src}", []>;
706 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
707 "movupd {$src, $dst|$dst, $src}",
708 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
709 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
710 "movupd {$src, $dst|$dst, $src}",
711 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
713 let isTwoAddress = 1 in {
714 let AddedComplexity = 20 in {
715 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
716 "movlps {$src2, $dst|$dst, $src2}",
718 (v4f32 (vector_shuffle VR128:$src1,
719 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
720 MOVLP_shuffle_mask)))]>;
721 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
722 "movlpd {$src2, $dst|$dst, $src2}",
724 (v2f64 (vector_shuffle VR128:$src1,
725 (scalar_to_vector (loadf64 addr:$src2)),
726 MOVLP_shuffle_mask)))]>;
727 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
728 "movhps {$src2, $dst|$dst, $src2}",
730 (v4f32 (vector_shuffle VR128:$src1,
731 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
732 MOVHP_shuffle_mask)))]>;
733 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
734 "movhpd {$src2, $dst|$dst, $src2}",
736 (v2f64 (vector_shuffle VR128:$src1,
737 (scalar_to_vector (loadf64 addr:$src2)),
738 MOVHP_shuffle_mask)))]>;
742 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
743 "movlps {$src, $dst|$dst, $src}",
744 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
745 (iPTR 0))), addr:$dst)]>;
746 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
747 "movlpd {$src, $dst|$dst, $src}",
748 [(store (f64 (vector_extract (v2f64 VR128:$src),
749 (iPTR 0))), addr:$dst)]>;
751 // v2f64 extract element 1 is always custom lowered to unpack high to low
752 // and extract element 0 so the non-store version isn't too horrible.
753 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
754 "movhps {$src, $dst|$dst, $src}",
755 [(store (f64 (vector_extract
756 (v2f64 (vector_shuffle
757 (bc_v2f64 (v4f32 VR128:$src)), (undef),
758 UNPCKH_shuffle_mask)), (iPTR 0))),
760 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
761 "movhpd {$src, $dst|$dst, $src}",
762 [(store (f64 (vector_extract
763 (v2f64 (vector_shuffle VR128:$src, (undef),
764 UNPCKH_shuffle_mask)), (iPTR 0))),
767 let isTwoAddress = 1 in {
768 let AddedComplexity = 15 in {
769 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
770 "movlhps {$src2, $dst|$dst, $src2}",
772 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
773 MOVHP_shuffle_mask)))]>;
775 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
776 "movhlps {$src2, $dst|$dst, $src2}",
778 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
779 MOVHLPS_shuffle_mask)))]>;
783 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
784 "movshdup {$src, $dst|$dst, $src}",
785 [(set VR128:$dst, (v4f32 (vector_shuffle
787 MOVSHDUP_shuffle_mask)))]>;
788 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
789 "movshdup {$src, $dst|$dst, $src}",
790 [(set VR128:$dst, (v4f32 (vector_shuffle
791 (loadv4f32 addr:$src), (undef),
792 MOVSHDUP_shuffle_mask)))]>;
794 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
795 "movsldup {$src, $dst|$dst, $src}",
796 [(set VR128:$dst, (v4f32 (vector_shuffle
798 MOVSLDUP_shuffle_mask)))]>;
799 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
800 "movsldup {$src, $dst|$dst, $src}",
801 [(set VR128:$dst, (v4f32 (vector_shuffle
802 (loadv4f32 addr:$src), (undef),
803 MOVSLDUP_shuffle_mask)))]>;
805 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
806 "movddup {$src, $dst|$dst, $src}",
807 [(set VR128:$dst, (v2f64 (vector_shuffle
809 SSE_splat_lo_mask)))]>;
810 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
811 "movddup {$src, $dst|$dst, $src}",
812 [(set VR128:$dst, (v2f64 (vector_shuffle
813 (scalar_to_vector (loadf64 addr:$src)),
815 SSE_splat_lo_mask)))]>;
817 // SSE2 instructions without OpSize prefix
818 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
819 "cvtdq2ps {$src, $dst|$dst, $src}",
820 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
821 TB, Requires<[HasSSE2]>;
822 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
823 "cvtdq2ps {$src, $dst|$dst, $src}",
824 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
825 (bitconvert (loadv2i64 addr:$src))))]>,
826 TB, Requires<[HasSSE2]>;
828 // SSE2 instructions with XS prefix
829 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
830 "cvtdq2pd {$src, $dst|$dst, $src}",
831 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
832 XS, Requires<[HasSSE2]>;
833 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
834 "cvtdq2pd {$src, $dst|$dst, $src}",
835 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
836 (bitconvert (loadv2i64 addr:$src))))]>,
837 XS, Requires<[HasSSE2]>;
839 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
840 "cvtps2dq {$src, $dst|$dst, $src}",
841 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
842 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
843 "cvtps2dq {$src, $dst|$dst, $src}",
844 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
845 (load addr:$src)))]>;
846 // SSE2 packed instructions with XS prefix
847 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
848 "cvttps2dq {$src, $dst|$dst, $src}",
849 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
850 XS, Requires<[HasSSE2]>;
851 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
852 "cvttps2dq {$src, $dst|$dst, $src}",
853 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
854 (load addr:$src)))]>,
855 XS, Requires<[HasSSE2]>;
857 // SSE2 packed instructions with XD prefix
858 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
859 "cvtpd2dq {$src, $dst|$dst, $src}",
860 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
861 XD, Requires<[HasSSE2]>;
862 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
863 "cvtpd2dq {$src, $dst|$dst, $src}",
864 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
865 (load addr:$src)))]>,
866 XD, Requires<[HasSSE2]>;
867 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
868 "cvttpd2dq {$src, $dst|$dst, $src}",
869 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
870 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
871 "cvttpd2dq {$src, $dst|$dst, $src}",
872 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
873 (load addr:$src)))]>;
875 // SSE2 instructions without OpSize prefix
876 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
877 "cvtps2pd {$src, $dst|$dst, $src}",
878 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
879 TB, Requires<[HasSSE2]>;
880 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
881 "cvtps2pd {$src, $dst|$dst, $src}",
882 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
883 (load addr:$src)))]>,
884 TB, Requires<[HasSSE2]>;
886 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
887 "cvtpd2ps {$src, $dst|$dst, $src}",
888 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
889 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
890 "cvtpd2ps {$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
892 (load addr:$src)))]>;
894 // Match intrinsics which expect XMM operand(s).
895 // Aliases for intrinsics
896 let isTwoAddress = 1 in {
897 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
898 (ops VR128:$dst, VR128:$src1, GR32:$src2),
899 "cvtsi2sd {$src2, $dst|$dst, $src2}",
900 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
902 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
903 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
904 "cvtsi2sd {$src2, $dst|$dst, $src2}",
905 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
906 (loadi32 addr:$src2)))]>;
907 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
908 (ops VR128:$dst, VR128:$src1, VR128:$src2),
909 "cvtsd2ss {$src2, $dst|$dst, $src2}",
910 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
912 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
913 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
914 "cvtsd2ss {$src2, $dst|$dst, $src2}",
915 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
916 (load addr:$src2)))]>;
917 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
918 (ops VR128:$dst, VR128:$src1, VR128:$src2),
919 "cvtss2sd {$src2, $dst|$dst, $src2}",
920 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
923 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
924 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
925 "cvtss2sd {$src2, $dst|$dst, $src2}",
926 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
927 (load addr:$src2)))]>, XS,
931 /// packed_sse12_fp_binop_rm - Packed SSE binops come in four basic forms:
932 /// 1. v4f32 vs v2f64 - These come in SSE1/SSE2 forms for float/doubles.
933 /// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
935 let isTwoAddress = 1 in {
936 multiclass packed_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
937 SDNode OpNode, bit Commutable = 0> {
938 // Packed operation, reg+reg.
939 def PSrr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
940 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
941 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
942 let isCommutable = Commutable;
944 def PDrr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
945 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
946 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
947 let isCommutable = Commutable;
949 // Packed operation, reg+mem.
950 def PSrm : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
951 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
952 [(set VR128:$dst, (OpNode VR128:$src1, (loadv4f32 addr:$src2)))]>;
953 def PDrm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
954 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
955 [(set VR128:$dst, (OpNode VR128:$src1, (loadv2f64 addr:$src2)))]>;
959 defm ADD : packed_sse12_fp_binop_rm<0x58, "add", fadd, 1>;
960 defm MUL : packed_sse12_fp_binop_rm<0x59, "mul", fmul, 1>;
961 defm DIV : packed_sse12_fp_binop_rm<0x5E, "div", fdiv>;
962 defm SUB : packed_sse12_fp_binop_rm<0x5C, "sub", fsub>;
965 let isTwoAddress = 1 in {
966 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
967 (ops VR128:$dst, VR128:$src1, VR128:$src2),
968 "addsubps {$src2, $dst|$dst, $src2}",
969 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
971 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
972 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
973 "addsubps {$src2, $dst|$dst, $src2}",
974 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
975 (load addr:$src2)))]>;
976 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
977 (ops VR128:$dst, VR128:$src1, VR128:$src2),
978 "addsubpd {$src2, $dst|$dst, $src2}",
979 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
981 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
982 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
983 "addsubpd {$src2, $dst|$dst, $src2}",
984 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
985 (load addr:$src2)))]>;
988 def SQRTPSr : PS_Intr<0x51, "sqrtps", int_x86_sse_sqrt_ps>;
989 def SQRTPSm : PS_Intm<0x51, "sqrtps", int_x86_sse_sqrt_ps>;
990 def SQRTPDr : PD_Intr<0x51, "sqrtpd", int_x86_sse2_sqrt_pd>;
991 def SQRTPDm : PD_Intm<0x51, "sqrtpd", int_x86_sse2_sqrt_pd>;
993 def RSQRTPSr : PS_Intr<0x52, "rsqrtps", int_x86_sse_rsqrt_ps>;
994 def RSQRTPSm : PS_Intm<0x52, "rsqrtps", int_x86_sse_rsqrt_ps>;
995 def RCPPSr : PS_Intr<0x53, "rcpps", int_x86_sse_rcp_ps>;
996 def RCPPSm : PS_Intm<0x53, "rcpps", int_x86_sse_rcp_ps>;
998 let isTwoAddress = 1 in {
999 let isCommutable = 1 in {
1000 def MAXPSrr : PS_Intrr<0x5F, "maxps", int_x86_sse_max_ps>;
1001 def MAXPDrr : PD_Intrr<0x5F, "maxpd", int_x86_sse2_max_pd>;
1002 def MINPSrr : PS_Intrr<0x5D, "minps", int_x86_sse_min_ps>;
1003 def MINPDrr : PD_Intrr<0x5D, "minpd", int_x86_sse2_min_pd>;
1005 def MAXPSrm : PS_Intrm<0x5F, "maxps", int_x86_sse_max_ps>;
1006 def MAXPDrm : PD_Intrm<0x5F, "maxpd", int_x86_sse2_max_pd>;
1007 def MINPSrm : PS_Intrm<0x5D, "minps", int_x86_sse_min_ps>;
1008 def MINPDrm : PD_Intrm<0x5D, "minpd", int_x86_sse2_min_pd>;
1012 let isTwoAddress = 1 in {
1013 let isCommutable = 1 in {
1014 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1015 "andps {$src2, $dst|$dst, $src2}",
1016 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1017 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1018 "andpd {$src2, $dst|$dst, $src2}",
1020 (and (bc_v2i64 (v2f64 VR128:$src1)),
1021 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1022 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1023 "orps {$src2, $dst|$dst, $src2}",
1024 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1025 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1026 "orpd {$src2, $dst|$dst, $src2}",
1028 (or (bc_v2i64 (v2f64 VR128:$src1)),
1029 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1030 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1031 "xorps {$src2, $dst|$dst, $src2}",
1032 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1033 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1034 "xorpd {$src2, $dst|$dst, $src2}",
1036 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1037 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1039 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1040 "andps {$src2, $dst|$dst, $src2}",
1041 [(set VR128:$dst, (and VR128:$src1,
1042 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1043 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1044 "andpd {$src2, $dst|$dst, $src2}",
1046 (and (bc_v2i64 (v2f64 VR128:$src1)),
1047 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1048 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1049 "orps {$src2, $dst|$dst, $src2}",
1050 [(set VR128:$dst, (or VR128:$src1,
1051 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1052 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1053 "orpd {$src2, $dst|$dst, $src2}",
1055 (or (bc_v2i64 (v2f64 VR128:$src1)),
1056 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1057 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1058 "xorps {$src2, $dst|$dst, $src2}",
1059 [(set VR128:$dst, (xor VR128:$src1,
1060 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1061 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1062 "xorpd {$src2, $dst|$dst, $src2}",
1064 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1065 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1066 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1067 "andnps {$src2, $dst|$dst, $src2}",
1068 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1069 (bc_v2i64 (v4i32 immAllOnesV))),
1071 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1072 "andnps {$src2, $dst|$dst, $src2}",
1073 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1074 (bc_v2i64 (v4i32 immAllOnesV))),
1075 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1076 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1077 "andnpd {$src2, $dst|$dst, $src2}",
1079 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1080 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1081 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1082 "andnpd {$src2, $dst|$dst, $src2}",
1084 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1085 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1088 let isTwoAddress = 1 in {
1089 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1090 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1091 "cmp${cc}ps {$src, $dst|$dst, $src}",
1092 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1093 VR128:$src, imm:$cc))]>;
1094 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1095 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1096 "cmp${cc}ps {$src, $dst|$dst, $src}",
1097 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1098 (load addr:$src), imm:$cc))]>;
1099 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1100 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1101 "cmp${cc}pd {$src, $dst|$dst, $src}",
1102 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1103 VR128:$src, imm:$cc))]>;
1104 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1105 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1106 "cmp${cc}pd {$src, $dst|$dst, $src}",
1107 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1108 (load addr:$src), imm:$cc))]>;
1111 // Shuffle and unpack instructions
1112 let isTwoAddress = 1 in {
1113 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1114 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1115 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1116 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1117 [(set VR128:$dst, (v4f32 (vector_shuffle
1118 VR128:$src1, VR128:$src2,
1119 SHUFP_shuffle_mask:$src3)))]>;
1120 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1121 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1122 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1123 [(set VR128:$dst, (v4f32 (vector_shuffle
1124 VR128:$src1, (load addr:$src2),
1125 SHUFP_shuffle_mask:$src3)))]>;
1126 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1127 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1128 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1129 [(set VR128:$dst, (v2f64 (vector_shuffle
1130 VR128:$src1, VR128:$src2,
1131 SHUFP_shuffle_mask:$src3)))]>;
1132 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1133 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1134 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1135 [(set VR128:$dst, (v2f64 (vector_shuffle
1136 VR128:$src1, (load addr:$src2),
1137 SHUFP_shuffle_mask:$src3)))]>;
1139 let AddedComplexity = 10 in {
1140 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1141 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1142 "unpckhps {$src2, $dst|$dst, $src2}",
1143 [(set VR128:$dst, (v4f32 (vector_shuffle
1144 VR128:$src1, VR128:$src2,
1145 UNPCKH_shuffle_mask)))]>;
1146 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1147 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1148 "unpckhps {$src2, $dst|$dst, $src2}",
1149 [(set VR128:$dst, (v4f32 (vector_shuffle
1150 VR128:$src1, (load addr:$src2),
1151 UNPCKH_shuffle_mask)))]>;
1152 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1153 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1154 "unpckhpd {$src2, $dst|$dst, $src2}",
1155 [(set VR128:$dst, (v2f64 (vector_shuffle
1156 VR128:$src1, VR128:$src2,
1157 UNPCKH_shuffle_mask)))]>;
1158 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1159 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1160 "unpckhpd {$src2, $dst|$dst, $src2}",
1161 [(set VR128:$dst, (v2f64 (vector_shuffle
1162 VR128:$src1, (load addr:$src2),
1163 UNPCKH_shuffle_mask)))]>;
1165 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1166 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1167 "unpcklps {$src2, $dst|$dst, $src2}",
1168 [(set VR128:$dst, (v4f32 (vector_shuffle
1169 VR128:$src1, VR128:$src2,
1170 UNPCKL_shuffle_mask)))]>;
1171 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1172 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1173 "unpcklps {$src2, $dst|$dst, $src2}",
1174 [(set VR128:$dst, (v4f32 (vector_shuffle
1175 VR128:$src1, (load addr:$src2),
1176 UNPCKL_shuffle_mask)))]>;
1177 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1178 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1179 "unpcklpd {$src2, $dst|$dst, $src2}",
1180 [(set VR128:$dst, (v2f64 (vector_shuffle
1181 VR128:$src1, VR128:$src2,
1182 UNPCKL_shuffle_mask)))]>;
1183 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1184 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1185 "unpcklpd {$src2, $dst|$dst, $src2}",
1186 [(set VR128:$dst, (v2f64 (vector_shuffle
1187 VR128:$src1, (load addr:$src2),
1188 UNPCKL_shuffle_mask)))]>;
1189 } // AddedComplexity
1194 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
1195 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1196 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1197 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
1198 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
1199 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1200 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1201 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
1202 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
1203 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1204 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1205 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
1206 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
1207 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1208 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1209 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
1211 let isTwoAddress = 1 in {
1212 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
1213 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
1214 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
1215 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
1216 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
1217 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
1218 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
1219 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
1222 //===----------------------------------------------------------------------===//
1223 // SSE integer instructions
1224 //===----------------------------------------------------------------------===//
1226 // Move Instructions
1227 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1228 "movdqa {$src, $dst|$dst, $src}", []>;
1229 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1230 "movdqa {$src, $dst|$dst, $src}",
1231 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1232 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1233 "movdqa {$src, $dst|$dst, $src}",
1234 [(store (v2i64 VR128:$src), addr:$dst)]>;
1235 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1236 "movdqu {$src, $dst|$dst, $src}",
1237 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1238 XS, Requires<[HasSSE2]>;
1239 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1240 "movdqu {$src, $dst|$dst, $src}",
1241 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1242 XS, Requires<[HasSSE2]>;
1243 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1244 "lddqu {$src, $dst|$dst, $src}",
1245 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
1248 let isTwoAddress = 1 in {
1249 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1250 bit Commutable = 0> {
1251 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1252 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1253 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1254 let isCommutable = Commutable;
1256 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1257 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1258 [(set VR128:$dst, (IntId VR128:$src1,
1259 (bitconvert (loadv2i64 addr:$src2))))]>;
1263 let isTwoAddress = 1 in {
1264 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1265 string OpcodeStr, Intrinsic IntId> {
1266 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1267 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1268 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1269 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1270 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1271 [(set VR128:$dst, (IntId VR128:$src1,
1272 (bitconvert (loadv2i64 addr:$src2))))]>;
1273 def ri : PDIi8<opc2, ImmForm, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1274 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1275 [(set VR128:$dst, (IntId VR128:$src1,
1276 (scalar_to_vector (i32 imm:$src2))))]>;
1281 let isTwoAddress = 1 in {
1282 /// PDI_binop_rm - Simple SSE2 binary operator.
1283 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1284 ValueType OpVT, bit Commutable = 0> {
1285 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1286 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1287 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1288 let isCommutable = Commutable;
1290 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1291 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1292 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1293 (bitconvert (loadv2i64 addr:$src2)))))]>;
1296 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1298 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1299 /// to collapse (bitconvert VT to VT) into its operand.
1301 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1302 bit Commutable = 0> {
1303 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1304 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1305 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1306 let isCommutable = Commutable;
1308 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1309 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1310 [(set VR128:$dst, (OpNode VR128:$src1,(loadv2i64 addr:$src2)))]>;
1315 // 128-bit Integer Arithmetic
1317 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1318 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1319 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1320 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1322 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1323 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1324 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1325 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1327 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1328 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1329 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1330 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1332 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1333 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1334 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1335 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1337 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1339 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1340 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1341 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1343 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1345 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1346 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1349 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1350 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1351 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1352 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1353 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1356 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1357 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1358 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1360 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1361 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1362 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1364 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1365 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1366 // PSRAQ doesn't exist in SSE[1-3].
1369 // 128-bit logical shifts.
1370 let isTwoAddress = 1 in {
1371 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1372 "pslldq {$src2, $dst|$dst, $src2}", []>;
1373 def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1374 "psrldq {$src2, $dst|$dst, $src2}", []>;
1375 // PSRADQri doesn't exist in SSE[1-3].
1378 let Predicates = [HasSSE2] in {
1379 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1380 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1381 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1382 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1383 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1384 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1388 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1389 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1390 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1392 let isTwoAddress = 1 in {
1393 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1394 "pandn {$src2, $dst|$dst, $src2}",
1395 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1398 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1399 "pandn {$src2, $dst|$dst, $src2}",
1400 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1401 (load addr:$src2))))]>;
1404 // SSE2 Integer comparison
1405 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1406 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1407 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1408 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1409 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1410 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1412 // Pack instructions
1413 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1414 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1415 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1417 // Shuffle and unpack instructions
1418 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1419 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1420 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1421 [(set VR128:$dst, (v4i32 (vector_shuffle
1422 VR128:$src1, (undef),
1423 PSHUFD_shuffle_mask:$src2)))]>;
1424 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1425 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1426 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1427 [(set VR128:$dst, (v4i32 (vector_shuffle
1428 (bc_v4i32(loadv2i64 addr:$src1)),
1430 PSHUFD_shuffle_mask:$src2)))]>;
1432 // SSE2 with ImmT == Imm8 and XS prefix.
1433 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1434 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1435 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1436 [(set VR128:$dst, (v8i16 (vector_shuffle
1437 VR128:$src1, (undef),
1438 PSHUFHW_shuffle_mask:$src2)))]>,
1439 XS, Requires<[HasSSE2]>;
1440 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1441 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1442 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1443 [(set VR128:$dst, (v8i16 (vector_shuffle
1444 (bc_v8i16 (loadv2i64 addr:$src1)),
1446 PSHUFHW_shuffle_mask:$src2)))]>,
1447 XS, Requires<[HasSSE2]>;
1449 // SSE2 with ImmT == Imm8 and XD prefix.
1450 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1451 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1452 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1453 [(set VR128:$dst, (v8i16 (vector_shuffle
1454 VR128:$src1, (undef),
1455 PSHUFLW_shuffle_mask:$src2)))]>,
1456 XD, Requires<[HasSSE2]>;
1457 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1458 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1459 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1460 [(set VR128:$dst, (v8i16 (vector_shuffle
1461 (bc_v8i16 (loadv2i64 addr:$src1)),
1463 PSHUFLW_shuffle_mask:$src2)))]>,
1464 XD, Requires<[HasSSE2]>;
1466 let isTwoAddress = 1 in {
1467 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1468 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1469 "punpcklbw {$src2, $dst|$dst, $src2}",
1471 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1472 UNPCKL_shuffle_mask)))]>;
1473 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1474 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1475 "punpcklbw {$src2, $dst|$dst, $src2}",
1477 (v16i8 (vector_shuffle VR128:$src1,
1478 (bc_v16i8 (loadv2i64 addr:$src2)),
1479 UNPCKL_shuffle_mask)))]>;
1480 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1481 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1482 "punpcklwd {$src2, $dst|$dst, $src2}",
1484 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1485 UNPCKL_shuffle_mask)))]>;
1486 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1487 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1488 "punpcklwd {$src2, $dst|$dst, $src2}",
1490 (v8i16 (vector_shuffle VR128:$src1,
1491 (bc_v8i16 (loadv2i64 addr:$src2)),
1492 UNPCKL_shuffle_mask)))]>;
1493 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1494 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1495 "punpckldq {$src2, $dst|$dst, $src2}",
1497 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1498 UNPCKL_shuffle_mask)))]>;
1499 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1500 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1501 "punpckldq {$src2, $dst|$dst, $src2}",
1503 (v4i32 (vector_shuffle VR128:$src1,
1504 (bc_v4i32 (loadv2i64 addr:$src2)),
1505 UNPCKL_shuffle_mask)))]>;
1506 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1507 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1508 "punpcklqdq {$src2, $dst|$dst, $src2}",
1510 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1511 UNPCKL_shuffle_mask)))]>;
1512 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1513 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1514 "punpcklqdq {$src2, $dst|$dst, $src2}",
1516 (v2i64 (vector_shuffle VR128:$src1,
1517 (loadv2i64 addr:$src2),
1518 UNPCKL_shuffle_mask)))]>;
1520 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1521 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1522 "punpckhbw {$src2, $dst|$dst, $src2}",
1524 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1525 UNPCKH_shuffle_mask)))]>;
1526 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1527 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1528 "punpckhbw {$src2, $dst|$dst, $src2}",
1530 (v16i8 (vector_shuffle VR128:$src1,
1531 (bc_v16i8 (loadv2i64 addr:$src2)),
1532 UNPCKH_shuffle_mask)))]>;
1533 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1534 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1535 "punpckhwd {$src2, $dst|$dst, $src2}",
1537 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1538 UNPCKH_shuffle_mask)))]>;
1539 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1540 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1541 "punpckhwd {$src2, $dst|$dst, $src2}",
1543 (v8i16 (vector_shuffle VR128:$src1,
1544 (bc_v8i16 (loadv2i64 addr:$src2)),
1545 UNPCKH_shuffle_mask)))]>;
1546 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1547 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1548 "punpckhdq {$src2, $dst|$dst, $src2}",
1550 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1551 UNPCKH_shuffle_mask)))]>;
1552 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1553 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1554 "punpckhdq {$src2, $dst|$dst, $src2}",
1556 (v4i32 (vector_shuffle VR128:$src1,
1557 (bc_v4i32 (loadv2i64 addr:$src2)),
1558 UNPCKH_shuffle_mask)))]>;
1559 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1560 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1561 "punpckhqdq {$src2, $dst|$dst, $src2}",
1563 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1564 UNPCKH_shuffle_mask)))]>;
1565 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1566 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1567 "punpckhqdq {$src2, $dst|$dst, $src2}",
1569 (v2i64 (vector_shuffle VR128:$src1,
1570 (loadv2i64 addr:$src2),
1571 UNPCKH_shuffle_mask)))]>;
1575 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
1576 (ops GR32:$dst, VR128:$src1, i32i8imm:$src2),
1577 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1578 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
1579 (iPTR imm:$src2)))]>;
1580 let isTwoAddress = 1 in {
1581 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
1582 (ops VR128:$dst, VR128:$src1, GR32:$src2, i32i8imm:$src3),
1583 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1584 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1585 GR32:$src2, (iPTR imm:$src3))))]>;
1586 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
1587 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
1588 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1590 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1591 (i32 (anyext (loadi16 addr:$src2))),
1592 (iPTR imm:$src3))))]>;
1595 //===----------------------------------------------------------------------===//
1596 // Miscellaneous Instructions
1597 //===----------------------------------------------------------------------===//
1600 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1601 "movmskps {$src, $dst|$dst, $src}",
1602 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1603 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1604 "movmskpd {$src, $dst|$dst, $src}",
1605 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1607 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1608 "pmovmskb {$src, $dst|$dst, $src}",
1609 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1611 // Conditional store
1612 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (ops VR128:$src, VR128:$mask),
1613 "maskmovdqu {$mask, $src|$src, $mask}",
1614 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1617 // Prefetching loads.
1618 // TODO: no intrinsics for these?
1619 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), "prefetcht0 $src", []>;
1620 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), "prefetcht1 $src", []>;
1621 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), "prefetcht2 $src", []>;
1622 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src), "prefetchtnta $src", []>;
1624 // Non-temporal stores
1625 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1626 "movntps {$src, $dst|$dst, $src}",
1627 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1628 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1629 "movntpd {$src, $dst|$dst, $src}",
1630 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1631 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1632 "movntdq {$src, $dst|$dst, $src}",
1633 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1634 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1635 "movnti {$src, $dst|$dst, $src}",
1636 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
1637 TB, Requires<[HasSSE2]>;
1640 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
1641 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
1642 TB, Requires<[HasSSE2]>;
1644 // Load, store, and memory fence
1645 def SFENCE : PSI<0xAE, MRM7m, (ops), "sfence", [(int_x86_sse_sfence)]>;
1646 def LFENCE : I<0xAE, MRM5m, (ops),
1647 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
1648 def MFENCE : I<0xAE, MRM6m, (ops),
1649 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
1652 def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src),
1653 "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1654 def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst),
1655 "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1657 // Thread synchronization
1658 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
1659 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
1660 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
1661 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
1663 //===----------------------------------------------------------------------===//
1664 // Alias Instructions
1665 //===----------------------------------------------------------------------===//
1667 // Alias instructions that map zero vector to pxor / xorp* for sse.
1668 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1669 let isReMaterializable = 1 in {
1670 def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
1672 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1674 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
1675 "pcmpeqd $dst, $dst",
1676 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
1679 // FR32 / FR64 to 128-bit vector conversion.
1680 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
1681 "movss {$src, $dst|$dst, $src}",
1683 (v4f32 (scalar_to_vector FR32:$src)))]>;
1684 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1685 "movss {$src, $dst|$dst, $src}",
1687 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1688 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
1689 "movsd {$src, $dst|$dst, $src}",
1691 (v2f64 (scalar_to_vector FR64:$src)))]>;
1692 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1693 "movsd {$src, $dst|$dst, $src}",
1695 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
1697 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1698 "movd {$src, $dst|$dst, $src}",
1700 (v4i32 (scalar_to_vector GR32:$src)))]>;
1701 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1702 "movd {$src, $dst|$dst, $src}",
1704 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
1706 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (ops FR32:$dst, GR32:$src),
1707 "movd {$src, $dst|$dst, $src}",
1708 [(set FR32:$dst, (bitconvert GR32:$src))]>;
1710 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
1711 "movd {$src, $dst|$dst, $src}",
1712 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
1714 // SSE2 instructions with XS prefix
1715 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1716 "movq {$src, $dst|$dst, $src}",
1718 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
1719 Requires<[HasSSE2]>;
1720 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1721 "movq {$src, $dst|$dst, $src}",
1722 [(store (i64 (vector_extract (v2i64 VR128:$src),
1723 (iPTR 0))), addr:$dst)]>;
1725 // FIXME: may not be able to eliminate this movss with coalescing the src and
1726 // dest register classes are different. We really want to write this pattern
1728 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1729 // (f32 FR32:$src)>;
1730 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
1731 "movss {$src, $dst|$dst, $src}",
1732 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1734 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
1735 "movss {$src, $dst|$dst, $src}",
1736 [(store (f32 (vector_extract (v4f32 VR128:$src),
1737 (iPTR 0))), addr:$dst)]>;
1738 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
1739 "movsd {$src, $dst|$dst, $src}",
1740 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
1742 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1743 "movsd {$src, $dst|$dst, $src}",
1744 [(store (f64 (vector_extract (v2f64 VR128:$src),
1745 (iPTR 0))), addr:$dst)]>;
1746 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src),
1747 "movd {$src, $dst|$dst, $src}",
1748 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
1750 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
1751 "movd {$src, $dst|$dst, $src}",
1752 [(store (i32 (vector_extract (v4i32 VR128:$src),
1753 (iPTR 0))), addr:$dst)]>;
1755 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, FR32:$src),
1756 "movd {$src, $dst|$dst, $src}",
1757 [(set GR32:$dst, (bitconvert FR32:$src))]>;
1758 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, FR32:$src),
1759 "movd {$src, $dst|$dst, $src}",
1760 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
1763 // Move to lower bits of a VR128, leaving upper bits alone.
1764 // Three operand (but two address) aliases.
1765 let isTwoAddress = 1 in {
1766 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
1767 "movss {$src2, $dst|$dst, $src2}", []>;
1768 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
1769 "movsd {$src2, $dst|$dst, $src2}", []>;
1771 let AddedComplexity = 15 in {
1772 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1773 "movss {$src2, $dst|$dst, $src2}",
1775 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1776 MOVL_shuffle_mask)))]>;
1777 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1778 "movsd {$src2, $dst|$dst, $src2}",
1780 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
1781 MOVL_shuffle_mask)))]>;
1785 // Store / copy lower 64-bits of a XMM register.
1786 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1787 "movq {$src, $dst|$dst, $src}",
1788 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
1790 // Move to lower bits of a VR128 and zeroing upper bits.
1791 // Loading from memory automatically zeroing upper bits.
1792 let AddedComplexity = 20 in {
1793 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1794 "movss {$src, $dst|$dst, $src}",
1795 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
1796 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
1797 MOVL_shuffle_mask)))]>;
1798 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1799 "movsd {$src, $dst|$dst, $src}",
1800 [(set VR128:$dst, (v2f64 (vector_shuffle immAllZerosV,
1801 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
1802 MOVL_shuffle_mask)))]>;
1804 let AddedComplexity = 15 in
1805 // movd / movq to XMM register zero-extends
1806 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1807 "movd {$src, $dst|$dst, $src}",
1808 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
1809 (v4i32 (scalar_to_vector GR32:$src)),
1810 MOVL_shuffle_mask)))]>;
1811 let AddedComplexity = 20 in
1812 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1813 "movd {$src, $dst|$dst, $src}",
1814 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
1815 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
1816 MOVL_shuffle_mask)))]>;
1817 // Moving from XMM to XMM but still clear upper 64 bits.
1818 let AddedComplexity = 15 in
1819 def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1820 "movq {$src, $dst|$dst, $src}",
1821 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
1822 XS, Requires<[HasSSE2]>;
1823 let AddedComplexity = 20 in
1824 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1825 "movq {$src, $dst|$dst, $src}",
1826 [(set VR128:$dst, (int_x86_sse2_movl_dq
1827 (bitconvert (loadv2i64 addr:$src))))]>,
1828 XS, Requires<[HasSSE2]>;
1830 //===----------------------------------------------------------------------===//
1831 // Non-Instruction Patterns
1832 //===----------------------------------------------------------------------===//
1834 // 128-bit vector undef's.
1835 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1836 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1837 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1838 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1839 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1841 // 128-bit vector all zero's.
1842 def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1843 def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1844 def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1845 def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1846 def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1848 // 128-bit vector all one's.
1849 def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1850 def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1851 def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1852 def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1853 def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
1855 // Store 128-bit integer vector values.
1856 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1857 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1858 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1859 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1860 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1861 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1863 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
1865 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
1866 Requires<[HasSSE2]>;
1867 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
1868 Requires<[HasSSE2]>;
1871 let Predicates = [HasSSE2] in {
1872 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
1873 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
1874 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
1875 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
1876 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
1877 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
1878 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
1879 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
1880 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
1881 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
1882 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
1883 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
1884 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
1885 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
1886 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
1887 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
1888 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
1889 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
1890 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
1891 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
1892 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
1893 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
1894 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
1895 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
1896 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
1897 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
1898 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
1899 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
1900 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
1901 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
1904 // Move scalar to XMM zero-extended
1905 // movd to XMM register zero-extends
1906 let AddedComplexity = 15 in {
1907 def : Pat<(v8i16 (vector_shuffle immAllZerosV,
1908 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
1909 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
1910 def : Pat<(v16i8 (vector_shuffle immAllZerosV,
1911 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
1912 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
1913 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
1914 def : Pat<(v2f64 (vector_shuffle immAllZerosV,
1915 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
1916 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
1917 def : Pat<(v4f32 (vector_shuffle immAllZerosV,
1918 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
1919 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
1922 // Splat v2f64 / v2i64
1923 let AddedComplexity = 10 in {
1924 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
1925 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1926 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
1927 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1928 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
1929 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1930 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
1931 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1935 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
1936 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
1937 Requires<[HasSSE1]>;
1939 // Special unary SHUFPSrri case.
1940 // FIXME: when we want non two-address code, then we should use PSHUFD?
1941 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
1942 SHUFP_unary_shuffle_mask:$sm),
1943 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
1944 Requires<[HasSSE1]>;
1945 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
1946 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
1947 SHUFP_unary_shuffle_mask:$sm),
1948 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
1949 Requires<[HasSSE2]>;
1950 // Special binary v4i32 shuffle cases with SHUFPS.
1951 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
1952 PSHUFD_binary_shuffle_mask:$sm),
1953 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
1954 Requires<[HasSSE2]>;
1955 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
1956 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
1957 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
1958 Requires<[HasSSE2]>;
1960 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
1961 let AddedComplexity = 10 in {
1962 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
1963 UNPCKL_v_undef_shuffle_mask)),
1964 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1965 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
1966 UNPCKL_v_undef_shuffle_mask)),
1967 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1968 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
1969 UNPCKL_v_undef_shuffle_mask)),
1970 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1971 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1972 UNPCKL_v_undef_shuffle_mask)),
1973 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
1976 let AddedComplexity = 15 in
1977 // vector_shuffle v1, <undef> <1, 1, 3, 3>
1978 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1979 MOVSHDUP_shuffle_mask)),
1980 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
1981 let AddedComplexity = 20 in
1982 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
1983 MOVSHDUP_shuffle_mask)),
1984 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
1986 // vector_shuffle v1, <undef> <0, 0, 2, 2>
1987 let AddedComplexity = 15 in
1988 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1989 MOVSLDUP_shuffle_mask)),
1990 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
1991 let AddedComplexity = 20 in
1992 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
1993 MOVSLDUP_shuffle_mask)),
1994 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
1996 let AddedComplexity = 15 in {
1997 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1998 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1999 MOVHP_shuffle_mask)),
2000 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2002 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2003 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2004 MOVHLPS_shuffle_mask)),
2005 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2007 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2008 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2009 MOVHLPS_v_undef_shuffle_mask)),
2010 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2011 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2012 MOVHLPS_v_undef_shuffle_mask)),
2013 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2016 let AddedComplexity = 20 in {
2017 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2018 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2019 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2020 MOVLP_shuffle_mask)),
2021 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2022 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2023 MOVLP_shuffle_mask)),
2024 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2025 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2026 MOVHP_shuffle_mask)),
2027 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2028 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2029 MOVHP_shuffle_mask)),
2030 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2032 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2033 MOVLP_shuffle_mask)),
2034 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2035 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2036 MOVLP_shuffle_mask)),
2037 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2038 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2039 MOVHP_shuffle_mask)),
2040 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2041 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2042 MOVLP_shuffle_mask)),
2043 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2046 let AddedComplexity = 15 in {
2047 // Setting the lowest element in the vector.
2048 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2049 MOVL_shuffle_mask)),
2050 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2051 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2052 MOVL_shuffle_mask)),
2053 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2055 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2056 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2057 MOVLP_shuffle_mask)),
2058 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2059 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2060 MOVLP_shuffle_mask)),
2061 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2064 // Set lowest element and zero upper elements.
2065 let AddedComplexity = 20 in
2066 def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2067 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2068 MOVL_shuffle_mask)),
2069 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2071 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2072 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2073 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2074 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2075 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2076 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2077 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2078 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2079 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2080 Requires<[HasSSE2]>;
2081 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2082 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2083 Requires<[HasSSE2]>;
2084 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2085 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2086 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2087 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2088 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2089 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2090 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2091 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2092 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2093 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2094 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2095 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2096 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2097 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2098 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2099 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2101 // Some special case pandn patterns.
2102 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2104 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2105 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2107 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2108 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2110 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2112 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2113 (load addr:$src2))),
2114 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2115 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2116 (load addr:$src2))),
2117 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2118 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2119 (load addr:$src2))),
2120 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2123 def : Pat<(v4f32 (X86loadu addr:$src)), (MOVUPSrm addr:$src)>,
2124 Requires<[HasSSE1]>;