1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
246 let isCommutable = 1 in {
247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
252 Sched<[itins.Sched]>;
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
262 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
263 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
264 string asm, string SSEVer, string FPSizeStr,
265 Operand memopr, ComplexPattern mem_cpat,
268 let isCodeGenOnly = 1 in {
269 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
271 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
272 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 [(set RC:$dst, (!cast<Intrinsic>(
274 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
275 RC:$src1, RC:$src2))], itins.rr>,
276 Sched<[itins.Sched]>;
277 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
279 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
280 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
281 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
282 SSEVer, "_", OpcodeStr, FPSizeStr))
283 RC:$src1, mem_cpat:$src2))], itins.rm>,
284 Sched<[itins.Sched.Folded, ReadAfterLd]>;
288 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
290 RegisterClass RC, ValueType vt,
291 X86MemOperand x86memop, PatFrag mem_frag,
292 Domain d, OpndItins itins, bit Is2Addr = 1> {
293 let isCommutable = 1 in
294 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
297 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
299 Sched<[itins.Sched]>;
301 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
307 Sched<[itins.Sched.Folded, ReadAfterLd]>;
310 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
311 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
312 string OpcodeStr, X86MemOperand x86memop,
313 list<dag> pat_rr, list<dag> pat_rm,
315 let isCommutable = 1, hasSideEffects = 0 in
316 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
320 pat_rr, NoItinerary, d>,
321 Sched<[WriteVecLogic]>;
322 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
326 pat_rm, NoItinerary, d>,
327 Sched<[WriteVecLogicLd, ReadAfterLd]>;
330 //===----------------------------------------------------------------------===//
331 // Non-instruction patterns
332 //===----------------------------------------------------------------------===//
334 // A vector extract of the first f32/f64 position is a subregister copy
335 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
337 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
338 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
340 // A 128-bit subvector extract from the first 256-bit vector position
341 // is a subregister copy that needs no instruction.
342 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
343 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
347 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
348 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
353 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
357 // A 128-bit subvector insert to the first 256-bit vector position
358 // is a subregister copy that needs no instruction.
359 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
360 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
374 // Implicitly promote a 32-bit scalar to a vector.
375 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
378 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 // Implicitly promote a 64-bit scalar to a vector.
380 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
382 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
383 (COPY_TO_REGCLASS FR64:$src, VR128)>;
385 // Bitcasts between 128-bit vector types. Return the original type since
386 // no instruction is needed for the conversion
387 let Predicates = [HasSSE2] in {
388 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
397 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
402 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
407 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
417 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr> {
570 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
571 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
574 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
576 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
577 VEX, VEX_LIG, Sched<[WriteStore]>;
579 let Constraints = "$src1 = $dst" in {
580 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
581 "\t{$src2, $dst|$dst, $src2}">;
584 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
586 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
590 // Loading from memory automatically zeroing upper bits.
591 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
592 PatFrag mem_pat, string OpcodeStr> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
604 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
606 let canFoldAsLoad = 1, isReMaterializable = 1 in {
607 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
609 let AddedComplexity = 20 in
610 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
614 let Predicates = [UseAVX] in {
615 let AddedComplexity = 20 in {
616 // MOVSSrm zeros the high parts of the register; represent this
617 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
618 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
619 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
620 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
621 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
622 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
625 // MOVSDrm zeros the high parts of the register; represent this
626 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
627 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
628 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
629 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
630 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
631 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzload addr:$src)),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
638 // Represent the same patterns above but in the form they appear for
640 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
641 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
642 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
643 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
644 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
645 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
646 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
647 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
648 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
650 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
651 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
652 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
654 // Extract and store.
655 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
657 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
658 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
660 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
662 // Shuffle with VMOVSS
663 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
664 (VMOVSSrr (v4i32 VR128:$src1),
665 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
666 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
667 (VMOVSSrr (v4f32 VR128:$src1),
668 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
671 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
672 (SUBREG_TO_REG (i32 0),
673 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
674 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
676 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
677 (SUBREG_TO_REG (i32 0),
678 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
679 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
682 // Shuffle with VMOVSD
683 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
689 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
690 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
693 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
694 (SUBREG_TO_REG (i32 0),
695 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
696 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
698 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
699 (SUBREG_TO_REG (i32 0),
700 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
701 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
704 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
705 // is during lowering, where it's not possible to recognize the fold cause
706 // it has two uses through a bitcast. One use disappears at isel time and the
707 // fold opportunity reappears.
708 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
714 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
715 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
718 let Predicates = [UseSSE1] in {
719 let Predicates = [NoSSE41], AddedComplexity = 15 in {
720 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
721 // MOVSS to the lower bits.
722 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
723 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
724 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
725 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
726 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
727 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
730 let AddedComplexity = 20 in {
731 // MOVSSrm already zeros the high parts of the register.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
743 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
745 // Shuffle with MOVSS
746 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
748 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
749 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
752 let Predicates = [UseSSE2] in {
753 let Predicates = [NoSSE41], AddedComplexity = 15 in {
754 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
755 // MOVSD to the lower bits.
756 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
757 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
760 let AddedComplexity = 20 in {
761 // MOVSDrm already zeros the high parts of the register.
762 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
770 def : Pat<(v2f64 (X86vzload addr:$src)),
771 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
774 // Extract and store.
775 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
777 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
779 // Shuffle with MOVSD
780 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
786 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
787 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
789 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
790 // is during lowering, where it's not possible to recognize the fold cause
791 // it has two uses through a bitcast. One use disappears at isel time and the
792 // fold opportunity reappears.
793 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
799 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
800 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
803 //===----------------------------------------------------------------------===//
804 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
805 //===----------------------------------------------------------------------===//
807 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
808 X86MemOperand x86memop, PatFrag ld_frag,
809 string asm, Domain d,
811 bit IsReMaterializable = 1> {
812 let hasSideEffects = 0 in
813 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
814 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
815 Sched<[WriteFShuffle]>;
816 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
817 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
818 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
819 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
823 let Predicates = [HasAVX, NoVLX] in {
824 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
830 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
837 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
838 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
840 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
841 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
843 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
844 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
846 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
847 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
851 let Predicates = [UseSSE1] in {
852 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
853 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
855 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
856 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
859 let Predicates = [UseSSE2] in {
860 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
861 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
863 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
864 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
868 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
869 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
870 "movaps\t{$src, $dst|$dst, $src}",
871 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
872 IIC_SSE_MOVA_P_MR>, VEX;
873 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
874 "movapd\t{$src, $dst|$dst, $src}",
875 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
876 IIC_SSE_MOVA_P_MR>, VEX;
877 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
878 "movups\t{$src, $dst|$dst, $src}",
879 [(store (v4f32 VR128:$src), addr:$dst)],
880 IIC_SSE_MOVU_P_MR>, VEX;
881 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
882 "movupd\t{$src, $dst|$dst, $src}",
883 [(store (v2f64 VR128:$src), addr:$dst)],
884 IIC_SSE_MOVU_P_MR>, VEX;
885 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
886 "movaps\t{$src, $dst|$dst, $src}",
887 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
888 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
889 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
890 "movapd\t{$src, $dst|$dst, $src}",
891 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
892 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
893 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
894 "movups\t{$src, $dst|$dst, $src}",
895 [(store (v8f32 VR256:$src), addr:$dst)],
896 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
897 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
898 "movupd\t{$src, $dst|$dst, $src}",
899 [(store (v4f64 VR256:$src), addr:$dst)],
900 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
904 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
905 SchedRW = [WriteFShuffle] in {
906 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
908 "movaps\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX;
910 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
912 "movapd\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVA_P_RR>, VEX;
914 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
916 "movups\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX;
918 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
920 "movupd\t{$src, $dst|$dst, $src}", [],
921 IIC_SSE_MOVU_P_RR>, VEX;
922 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
924 "movaps\t{$src, $dst|$dst, $src}", [],
925 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
926 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
928 "movapd\t{$src, $dst|$dst, $src}", [],
929 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
930 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
932 "movups\t{$src, $dst|$dst, $src}", [],
933 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
934 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
936 "movupd\t{$src, $dst|$dst, $src}", [],
937 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
940 let Predicates = [HasAVX] in {
941 def : Pat<(v8i32 (X86vzmovl
942 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
943 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
944 def : Pat<(v4i64 (X86vzmovl
945 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
946 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
947 def : Pat<(v8f32 (X86vzmovl
948 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
949 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
950 def : Pat<(v4f64 (X86vzmovl
951 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
952 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
956 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
957 (VMOVUPSYmr addr:$dst, VR256:$src)>;
958 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
959 (VMOVUPDYmr addr:$dst, VR256:$src)>;
961 let SchedRW = [WriteStore] in {
962 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
963 "movaps\t{$src, $dst|$dst, $src}",
964 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
966 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
967 "movapd\t{$src, $dst|$dst, $src}",
968 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
970 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
971 "movups\t{$src, $dst|$dst, $src}",
972 [(store (v4f32 VR128:$src), addr:$dst)],
974 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
975 "movupd\t{$src, $dst|$dst, $src}",
976 [(store (v2f64 VR128:$src), addr:$dst)],
981 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
982 SchedRW = [WriteFShuffle] in {
983 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
984 "movaps\t{$src, $dst|$dst, $src}", [],
986 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
987 "movapd\t{$src, $dst|$dst, $src}", [],
989 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
990 "movups\t{$src, $dst|$dst, $src}", [],
992 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
993 "movupd\t{$src, $dst|$dst, $src}", [],
997 let Predicates = [HasAVX] in {
998 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
999 (VMOVUPSmr addr:$dst, VR128:$src)>;
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (VMOVUPDmr addr:$dst, VR128:$src)>;
1004 let Predicates = [UseSSE1] in
1005 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1006 (MOVUPSmr addr:$dst, VR128:$src)>;
1007 let Predicates = [UseSSE2] in
1008 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1009 (MOVUPDmr addr:$dst, VR128:$src)>;
1011 // Use vmovaps/vmovups for AVX integer load/store.
1012 let Predicates = [HasAVX, NoVLX] in {
1013 // 128-bit load/store
1014 def : Pat<(alignedloadv2i64 addr:$src),
1015 (VMOVAPSrm addr:$src)>;
1016 def : Pat<(loadv2i64 addr:$src),
1017 (VMOVUPSrm addr:$src)>;
1019 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1026 (VMOVAPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1033 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1034 (VMOVUPSmr addr:$dst, VR128:$src)>;
1036 // 256-bit load/store
1037 def : Pat<(alignedloadv4i64 addr:$src),
1038 (VMOVAPSYrm addr:$src)>;
1039 def : Pat<(loadv4i64 addr:$src),
1040 (VMOVUPSYrm addr:$src)>;
1041 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1048 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1055 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1056 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1058 // Special patterns for storing subvector extracts of lower 128-bits
1059 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1060 def : Pat<(alignedstore (v2f64 (extract_subvector
1061 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1062 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1063 def : Pat<(alignedstore (v4f32 (extract_subvector
1064 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1065 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1066 def : Pat<(alignedstore (v2i64 (extract_subvector
1067 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1068 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1069 def : Pat<(alignedstore (v4i32 (extract_subvector
1070 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1071 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1072 def : Pat<(alignedstore (v8i16 (extract_subvector
1073 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1074 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1075 def : Pat<(alignedstore (v16i8 (extract_subvector
1076 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1077 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1079 def : Pat<(store (v2f64 (extract_subvector
1080 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1081 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1082 def : Pat<(store (v4f32 (extract_subvector
1083 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1084 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1085 def : Pat<(store (v2i64 (extract_subvector
1086 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1087 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1088 def : Pat<(store (v4i32 (extract_subvector
1089 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1090 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1091 def : Pat<(store (v8i16 (extract_subvector
1092 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1093 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1094 def : Pat<(store (v16i8 (extract_subvector
1095 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1096 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1099 // Use movaps / movups for SSE integer load / store (one byte shorter).
1100 // The instructions selected below are then converted to MOVDQA/MOVDQU
1101 // during the SSE domain pass.
1102 let Predicates = [UseSSE1] in {
1103 def : Pat<(alignedloadv2i64 addr:$src),
1104 (MOVAPSrm addr:$src)>;
1105 def : Pat<(loadv2i64 addr:$src),
1106 (MOVUPSrm addr:$src)>;
1108 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1115 (MOVAPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1122 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1123 (MOVUPSmr addr:$dst, VR128:$src)>;
1126 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1127 // bits are disregarded. FIXME: Set encoding to pseudo!
1128 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1129 let isCodeGenOnly = 1 in {
1130 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1131 "movaps\t{$src, $dst|$dst, $src}",
1132 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1133 IIC_SSE_MOVA_P_RM>, VEX;
1134 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1135 "movapd\t{$src, $dst|$dst, $src}",
1136 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1137 IIC_SSE_MOVA_P_RM>, VEX;
1138 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1139 "movaps\t{$src, $dst|$dst, $src}",
1140 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1142 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1143 "movapd\t{$src, $dst|$dst, $src}",
1144 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1149 //===----------------------------------------------------------------------===//
1150 // SSE 1 & 2 - Move Low packed FP Instructions
1151 //===----------------------------------------------------------------------===//
1153 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1154 string base_opc, string asm_opr,
1155 InstrItinClass itin> {
1156 def PSrm : PI<opc, MRMSrcMem,
1157 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1158 !strconcat(base_opc, "s", asm_opr),
1160 (psnode VR128:$src1,
1161 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1162 itin, SSEPackedSingle>, PS,
1163 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1165 def PDrm : PI<opc, MRMSrcMem,
1166 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1167 !strconcat(base_opc, "d", asm_opr),
1168 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1169 (scalar_to_vector (loadf64 addr:$src2)))))],
1170 itin, SSEPackedDouble>, PD,
1171 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1175 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1176 string base_opc, InstrItinClass itin> {
1177 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1178 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1181 let Constraints = "$src1 = $dst" in
1182 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1183 "\t{$src2, $dst|$dst, $src2}",
1187 let AddedComplexity = 20 in {
1188 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1192 let SchedRW = [WriteStore] in {
1193 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1194 "movlps\t{$src, $dst|$dst, $src}",
1195 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1196 (iPTR 0))), addr:$dst)],
1197 IIC_SSE_MOV_LH>, VEX;
1198 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1199 "movlpd\t{$src, $dst|$dst, $src}",
1200 [(store (f64 (vector_extract (v2f64 VR128:$src),
1201 (iPTR 0))), addr:$dst)],
1202 IIC_SSE_MOV_LH>, VEX;
1203 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1204 "movlps\t{$src, $dst|$dst, $src}",
1205 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1206 (iPTR 0))), addr:$dst)],
1208 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1209 "movlpd\t{$src, $dst|$dst, $src}",
1210 [(store (f64 (vector_extract (v2f64 VR128:$src),
1211 (iPTR 0))), addr:$dst)],
1215 let Predicates = [HasAVX] in {
1216 // Shuffle with VMOVLPS
1217 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1219 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1220 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1222 // Shuffle with VMOVLPD
1223 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1226 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1227 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1228 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1229 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1232 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1234 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1235 def : Pat<(store (v4i32 (X86Movlps
1236 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1237 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1238 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1240 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1243 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1246 let Predicates = [UseSSE1] in {
1247 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1248 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1249 (iPTR 0))), addr:$src1),
1250 (MOVLPSmr addr:$src1, VR128:$src2)>;
1252 // Shuffle with MOVLPS
1253 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1256 (MOVLPSrm VR128:$src1, addr:$src2)>;
1257 def : Pat<(X86Movlps VR128:$src1,
1258 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1259 (MOVLPSrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1264 (MOVLPSmr addr:$src1, VR128:$src2)>;
1265 def : Pat<(store (v4i32 (X86Movlps
1266 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1268 (MOVLPSmr addr:$src1, VR128:$src2)>;
1271 let Predicates = [UseSSE2] in {
1272 // Shuffle with MOVLPD
1273 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1276 (MOVLPDrm VR128:$src1, addr:$src2)>;
1277 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1278 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1279 (MOVLPDrm VR128:$src1, addr:$src2)>;
1282 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1284 (MOVLPDmr addr:$src1, VR128:$src2)>;
1285 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1287 (MOVLPDmr addr:$src1, VR128:$src2)>;
1290 //===----------------------------------------------------------------------===//
1291 // SSE 1 & 2 - Move Hi packed FP Instructions
1292 //===----------------------------------------------------------------------===//
1294 let AddedComplexity = 20 in {
1295 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1299 let SchedRW = [WriteStore] in {
1300 // v2f64 extract element 1 is always custom lowered to unpack high to low
1301 // and extract element 0 so the non-store version isn't too horrible.
1302 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1303 "movhps\t{$src, $dst|$dst, $src}",
1304 [(store (f64 (vector_extract
1305 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1306 (bc_v2f64 (v4f32 VR128:$src))),
1307 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1308 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1309 "movhpd\t{$src, $dst|$dst, $src}",
1310 [(store (f64 (vector_extract
1311 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1312 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1313 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1314 "movhps\t{$src, $dst|$dst, $src}",
1315 [(store (f64 (vector_extract
1316 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1317 (bc_v2f64 (v4f32 VR128:$src))),
1318 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1319 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1320 "movhpd\t{$src, $dst|$dst, $src}",
1321 [(store (f64 (vector_extract
1322 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1323 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1326 let Predicates = [HasAVX] in {
1328 def : Pat<(X86Movlhps VR128:$src1,
1329 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1330 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1331 def : Pat<(X86Movlhps VR128:$src1,
1332 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1333 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1337 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1338 // is during lowering, where it's not possible to recognize the load fold
1339 // cause it has two uses through a bitcast. One use disappears at isel time
1340 // and the fold opportunity reappears.
1341 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1342 (scalar_to_vector (loadf64 addr:$src2)))),
1343 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1344 // Also handle an i64 load because that may get selected as a faster way to
1346 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1347 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1348 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1350 def : Pat<(store (f64 (vector_extract
1351 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1352 (iPTR 0))), addr:$dst),
1353 (VMOVHPDmr addr:$dst, VR128:$src)>;
1356 let Predicates = [UseSSE1] in {
1358 def : Pat<(X86Movlhps VR128:$src1,
1359 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1360 (MOVHPSrm VR128:$src1, addr:$src2)>;
1361 def : Pat<(X86Movlhps VR128:$src1,
1362 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1363 (MOVHPSrm VR128:$src1, addr:$src2)>;
1366 let Predicates = [UseSSE2] in {
1369 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1370 // is during lowering, where it's not possible to recognize the load fold
1371 // cause it has two uses through a bitcast. One use disappears at isel time
1372 // and the fold opportunity reappears.
1373 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1374 (scalar_to_vector (loadf64 addr:$src2)))),
1375 (MOVHPDrm VR128:$src1, addr:$src2)>;
1376 // Also handle an i64 load because that may get selected as a faster way to
1378 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1379 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1380 (MOVHPDrm VR128:$src1, addr:$src2)>;
1382 def : Pat<(store (f64 (vector_extract
1383 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1384 (iPTR 0))), addr:$dst),
1385 (MOVHPDmr addr:$dst, VR128:$src)>;
1388 //===----------------------------------------------------------------------===//
1389 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1390 //===----------------------------------------------------------------------===//
1392 let AddedComplexity = 20, Predicates = [UseAVX] in {
1393 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1394 (ins VR128:$src1, VR128:$src2),
1395 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1397 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1399 VEX_4V, Sched<[WriteFShuffle]>;
1400 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1401 (ins VR128:$src1, VR128:$src2),
1402 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1404 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1406 VEX_4V, Sched<[WriteFShuffle]>;
1408 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1409 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1410 (ins VR128:$src1, VR128:$src2),
1411 "movlhps\t{$src2, $dst|$dst, $src2}",
1413 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1414 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1415 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1416 (ins VR128:$src1, VR128:$src2),
1417 "movhlps\t{$src2, $dst|$dst, $src2}",
1419 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1420 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1423 let Predicates = [UseAVX] in {
1425 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1427 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1428 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1431 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1432 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1435 let Predicates = [UseSSE1] in {
1437 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1439 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1440 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1443 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1444 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1447 //===----------------------------------------------------------------------===//
1448 // SSE 1 & 2 - Conversion Instructions
1449 //===----------------------------------------------------------------------===//
1451 def SSE_CVT_PD : OpndItins<
1452 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1455 let Sched = WriteCvtI2F in
1456 def SSE_CVT_PS : OpndItins<
1457 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1460 let Sched = WriteCvtI2F in
1461 def SSE_CVT_Scalar : OpndItins<
1462 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1465 let Sched = WriteCvtF2I in
1466 def SSE_CVT_SS2SI_32 : OpndItins<
1467 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1470 let Sched = WriteCvtF2I in
1471 def SSE_CVT_SS2SI_64 : OpndItins<
1472 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1475 let Sched = WriteCvtF2I in
1476 def SSE_CVT_SD2SI : OpndItins<
1477 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1480 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1481 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1482 string asm, OpndItins itins> {
1483 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1484 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1485 itins.rr>, Sched<[itins.Sched]>;
1486 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1487 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1488 itins.rm>, Sched<[itins.Sched.Folded]>;
1491 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1492 X86MemOperand x86memop, string asm, Domain d,
1494 let hasSideEffects = 0 in {
1495 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1496 [], itins.rr, d>, Sched<[itins.Sched]>;
1498 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1499 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1503 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1504 X86MemOperand x86memop, string asm> {
1505 let hasSideEffects = 0, Predicates = [UseAVX] in {
1506 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1507 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1508 Sched<[WriteCvtI2F]>;
1510 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1511 (ins DstRC:$src1, x86memop:$src),
1512 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1513 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1514 } // hasSideEffects = 0
1517 let Predicates = [UseAVX] in {
1518 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1519 "cvttss2si\t{$src, $dst|$dst, $src}",
1522 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1523 "cvttss2si\t{$src, $dst|$dst, $src}",
1525 XS, VEX, VEX_W, VEX_LIG;
1526 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1527 "cvttsd2si\t{$src, $dst|$dst, $src}",
1530 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1531 "cvttsd2si\t{$src, $dst|$dst, $src}",
1533 XD, VEX, VEX_W, VEX_LIG;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1537 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1541 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1545 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1549 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1550 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1552 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1553 // register, but the same isn't true when only using memory operands,
1554 // provide other assembly "l" and "q" forms to address this explicitly
1555 // where appropriate to do so.
1556 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1557 XS, VEX_4V, VEX_LIG;
1558 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1559 XS, VEX_4V, VEX_W, VEX_LIG;
1560 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1561 XD, VEX_4V, VEX_LIG;
1562 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1563 XD, VEX_4V, VEX_W, VEX_LIG;
1565 let Predicates = [UseAVX] in {
1566 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1568 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1569 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1571 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1572 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1574 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1576 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1577 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1578 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR32:$src)),
1581 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1582 def : Pat<(f32 (sint_to_fp GR64:$src)),
1583 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR32:$src)),
1585 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1586 def : Pat<(f64 (sint_to_fp GR64:$src)),
1587 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1590 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1591 "cvttss2si\t{$src, $dst|$dst, $src}",
1592 SSE_CVT_SS2SI_32>, XS;
1593 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1594 "cvttss2si\t{$src, $dst|$dst, $src}",
1595 SSE_CVT_SS2SI_64>, XS, REX_W;
1596 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1597 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1600 "cvttsd2si\t{$src, $dst|$dst, $src}",
1601 SSE_CVT_SD2SI>, XD, REX_W;
1602 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1603 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1604 SSE_CVT_Scalar>, XS;
1605 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1606 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1607 SSE_CVT_Scalar>, XS, REX_W;
1608 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1609 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1610 SSE_CVT_Scalar>, XD;
1611 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1612 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1613 SSE_CVT_Scalar>, XD, REX_W;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1617 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1621 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1622 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1625 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1629 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1630 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1632 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1634 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1635 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1637 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1638 // and/or XMM operand(s).
1640 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1641 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1642 string asm, OpndItins itins> {
1643 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1644 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1645 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1646 Sched<[itins.Sched]>;
1647 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1648 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1649 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1650 Sched<[itins.Sched.Folded]>;
1653 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1654 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1655 PatFrag ld_frag, string asm, OpndItins itins,
1657 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1659 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1660 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1661 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1662 itins.rr>, Sched<[itins.Sched]>;
1663 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1664 (ins DstRC:$src1, x86memop:$src2),
1666 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1667 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1668 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1669 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1672 let Predicates = [UseAVX] in {
1673 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1674 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1675 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1676 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1677 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1678 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1680 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1682 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1683 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1686 let isCodeGenOnly = 1 in {
1687 let Predicates = [UseAVX] in {
1688 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1689 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1690 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1691 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1692 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1693 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1695 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1696 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1697 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1698 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1699 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1700 SSE_CVT_Scalar, 0>, XD,
1703 let Constraints = "$src1 = $dst" in {
1704 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1705 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1706 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1707 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1708 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1709 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1710 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1711 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1712 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1713 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1714 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1715 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1717 } // isCodeGenOnly = 1
1721 // Aliases for intrinsics
1722 let isCodeGenOnly = 1 in {
1723 let Predicates = [UseAVX] in {
1724 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1725 ssmem, sse_load_f32, "cvttss2si",
1726 SSE_CVT_SS2SI_32>, XS, VEX;
1727 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1728 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1729 "cvttss2si", SSE_CVT_SS2SI_64>,
1731 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1732 sdmem, sse_load_f64, "cvttsd2si",
1733 SSE_CVT_SD2SI>, XD, VEX;
1734 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1735 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1736 "cvttsd2si", SSE_CVT_SD2SI>,
1739 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1740 ssmem, sse_load_f32, "cvttss2si",
1741 SSE_CVT_SS2SI_32>, XS;
1742 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1743 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1744 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1745 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1746 sdmem, sse_load_f64, "cvttsd2si",
1748 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1749 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1750 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1751 } // isCodeGenOnly = 1
1753 let Predicates = [UseAVX] in {
1754 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1755 ssmem, sse_load_f32, "cvtss2si",
1756 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1757 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1758 ssmem, sse_load_f32, "cvtss2si",
1759 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1761 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1762 ssmem, sse_load_f32, "cvtss2si",
1763 SSE_CVT_SS2SI_32>, XS;
1764 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1765 ssmem, sse_load_f32, "cvtss2si",
1766 SSE_CVT_SS2SI_64>, XS, REX_W;
1768 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1769 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1770 SSEPackedSingle, SSE_CVT_PS>,
1771 PS, VEX, Requires<[HasAVX]>;
1772 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1773 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1774 SSEPackedSingle, SSE_CVT_PS>,
1775 PS, VEX, VEX_L, Requires<[HasAVX]>;
1777 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1778 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1779 SSEPackedSingle, SSE_CVT_PS>,
1780 PS, Requires<[UseSSE2]>;
1782 let Predicates = [UseAVX] in {
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1785 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1789 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1790 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1793 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1797 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1798 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1803 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1807 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1808 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1811 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1815 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1816 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1820 // Convert scalar double to scalar single
1821 let hasSideEffects = 0, Predicates = [UseAVX] in {
1822 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1823 (ins FR64:$src1, FR64:$src2),
1824 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1825 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1826 Sched<[WriteCvtF2F]>;
1828 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1829 (ins FR64:$src1, f64mem:$src2),
1830 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1831 [], IIC_SSE_CVT_Scalar_RM>,
1832 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1833 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1836 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1839 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1840 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1841 [(set FR32:$dst, (fround FR64:$src))],
1842 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1843 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1844 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1845 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1846 IIC_SSE_CVT_Scalar_RM>,
1848 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1850 let isCodeGenOnly = 1 in {
1851 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1852 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1853 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1855 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1856 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1857 Sched<[WriteCvtF2F]>;
1858 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1859 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1860 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1861 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1862 VR128:$src1, sse_load_f64:$src2))],
1863 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1864 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1866 let Constraints = "$src1 = $dst" in {
1867 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1868 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1869 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1871 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1872 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1873 Sched<[WriteCvtF2F]>;
1874 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1875 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1876 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1877 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1878 VR128:$src1, sse_load_f64:$src2))],
1879 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1880 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1882 } // isCodeGenOnly = 1
1884 // Convert scalar single to scalar double
1885 // SSE2 instructions with XS prefix
1886 let hasSideEffects = 0, Predicates = [UseAVX] in {
1887 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1888 (ins FR32:$src1, FR32:$src2),
1889 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1890 [], IIC_SSE_CVT_Scalar_RR>,
1891 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1892 Sched<[WriteCvtF2F]>;
1894 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1895 (ins FR32:$src1, f32mem:$src2),
1896 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1897 [], IIC_SSE_CVT_Scalar_RM>,
1898 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1899 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1902 def : Pat<(f64 (fextend FR32:$src)),
1903 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1904 def : Pat<(fextend (loadf32 addr:$src)),
1905 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1907 def : Pat<(extloadf32 addr:$src),
1908 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1909 Requires<[UseAVX, OptForSize]>;
1910 def : Pat<(extloadf32 addr:$src),
1911 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1912 Requires<[UseAVX, OptForSpeed]>;
1914 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1915 "cvtss2sd\t{$src, $dst|$dst, $src}",
1916 [(set FR64:$dst, (fextend FR32:$src))],
1917 IIC_SSE_CVT_Scalar_RR>, XS,
1918 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1919 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1920 "cvtss2sd\t{$src, $dst|$dst, $src}",
1921 [(set FR64:$dst, (extloadf32 addr:$src))],
1922 IIC_SSE_CVT_Scalar_RM>, XS,
1923 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1925 // extload f32 -> f64. This matches load+fextend because we have a hack in
1926 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1928 // Since these loads aren't folded into the fextend, we have to match it
1930 def : Pat<(fextend (loadf32 addr:$src)),
1931 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1932 def : Pat<(extloadf32 addr:$src),
1933 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1935 let isCodeGenOnly = 1 in {
1936 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1937 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1938 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1940 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1941 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1942 Sched<[WriteCvtF2F]>;
1943 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1944 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1945 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1947 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1948 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1949 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1950 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1951 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1952 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1953 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1955 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1956 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1957 Sched<[WriteCvtF2F]>;
1958 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1959 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1960 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1962 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1963 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1964 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1966 } // isCodeGenOnly = 1
1968 // Convert packed single/double fp to doubleword
1969 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1970 "cvtps2dq\t{$src, $dst|$dst, $src}",
1971 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1972 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1973 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1974 "cvtps2dq\t{$src, $dst|$dst, $src}",
1976 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1977 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1978 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1979 "cvtps2dq\t{$src, $dst|$dst, $src}",
1981 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1982 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1983 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1984 "cvtps2dq\t{$src, $dst|$dst, $src}",
1986 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1987 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1988 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1989 "cvtps2dq\t{$src, $dst|$dst, $src}",
1990 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1991 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1992 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1993 "cvtps2dq\t{$src, $dst|$dst, $src}",
1995 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1996 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1999 // Convert Packed Double FP to Packed DW Integers
2000 let Predicates = [HasAVX] in {
2001 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2002 // register, but the same isn't true when using memory operands instead.
2003 // Provide other assembly rr and rm forms to address this explicitly.
2004 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2005 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2006 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2007 VEX, Sched<[WriteCvtF2I]>;
2010 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2011 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2012 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2013 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2015 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2016 Sched<[WriteCvtF2ILd]>;
2019 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2020 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2022 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2023 Sched<[WriteCvtF2I]>;
2024 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2025 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2027 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2028 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2029 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2030 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2033 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2034 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2036 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2037 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2038 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2039 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2040 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2041 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2043 // Convert with truncation packed single/double fp to doubleword
2044 // SSE2 packed instructions with XS prefix
2045 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2046 "cvttps2dq\t{$src, $dst|$dst, $src}",
2048 (int_x86_sse2_cvttps2dq VR128:$src))],
2049 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2050 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2051 "cvttps2dq\t{$src, $dst|$dst, $src}",
2052 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2053 (loadv4f32 addr:$src)))],
2054 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2055 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2056 "cvttps2dq\t{$src, $dst|$dst, $src}",
2058 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2059 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2060 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2061 "cvttps2dq\t{$src, $dst|$dst, $src}",
2062 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2063 (loadv8f32 addr:$src)))],
2064 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2065 Sched<[WriteCvtF2ILd]>;
2067 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2068 "cvttps2dq\t{$src, $dst|$dst, $src}",
2069 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2070 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2071 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2072 "cvttps2dq\t{$src, $dst|$dst, $src}",
2074 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2075 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2077 let Predicates = [HasAVX] in {
2078 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2079 (VCVTDQ2PSrr VR128:$src)>;
2080 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2081 (VCVTDQ2PSrm addr:$src)>;
2083 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2084 (VCVTDQ2PSrr VR128:$src)>;
2085 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2086 (VCVTDQ2PSrm addr:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2089 (VCVTTPS2DQrr VR128:$src)>;
2090 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2091 (VCVTTPS2DQrm addr:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2094 (VCVTDQ2PSYrr VR256:$src)>;
2095 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2096 (VCVTDQ2PSYrm addr:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2099 (VCVTTPS2DQYrr VR256:$src)>;
2100 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2101 (VCVTTPS2DQYrm addr:$src)>;
2104 let Predicates = [UseSSE2] in {
2105 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2106 (CVTDQ2PSrr VR128:$src)>;
2107 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2108 (CVTDQ2PSrm addr:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2111 (CVTDQ2PSrr VR128:$src)>;
2112 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2113 (CVTDQ2PSrm addr:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2116 (CVTTPS2DQrr VR128:$src)>;
2117 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2118 (CVTTPS2DQrm addr:$src)>;
2121 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2122 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2124 (int_x86_sse2_cvttpd2dq VR128:$src))],
2125 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2127 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2128 // register, but the same isn't true when using memory operands instead.
2129 // Provide other assembly rr and rm forms to address this explicitly.
2132 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2133 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2134 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2135 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2136 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2137 (loadv2f64 addr:$src)))],
2138 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2141 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2142 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2145 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2146 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2147 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2149 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2150 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2151 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2152 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2154 let Predicates = [HasAVX] in {
2155 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2156 (VCVTTPD2DQYrr VR256:$src)>;
2157 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2158 (VCVTTPD2DQYrm addr:$src)>;
2159 } // Predicates = [HasAVX]
2161 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2162 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2163 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2164 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2165 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2166 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2167 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2168 (memopv2f64 addr:$src)))],
2170 Sched<[WriteCvtF2ILd]>;
2172 // Convert packed single to packed double
2173 let Predicates = [HasAVX] in {
2174 // SSE2 instructions without OpSize prefix
2175 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2179 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2180 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2181 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2182 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2183 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2184 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2186 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2187 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2188 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2189 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2192 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2195 let Predicates = [UseSSE2] in {
2196 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2197 "cvtps2pd\t{$src, $dst|$dst, $src}",
2198 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2199 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2200 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2201 "cvtps2pd\t{$src, $dst|$dst, $src}",
2202 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2203 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2206 // Convert Packed DW Integers to Packed Double FP
2207 let Predicates = [HasAVX] in {
2208 let hasSideEffects = 0, mayLoad = 1 in
2209 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2210 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2211 []>, VEX, Sched<[WriteCvtI2FLd]>;
2212 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2213 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2215 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2216 Sched<[WriteCvtI2F]>;
2217 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2218 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2220 (int_x86_avx_cvtdq2_pd_256
2221 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2222 Sched<[WriteCvtI2FLd]>;
2223 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2224 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2227 Sched<[WriteCvtI2F]>;
2230 let hasSideEffects = 0, mayLoad = 1 in
2231 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2232 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2233 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2234 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2235 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2236 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2237 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2239 // AVX 256-bit register conversion intrinsics
2240 let Predicates = [HasAVX] in {
2241 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2242 (VCVTDQ2PDYrr VR128:$src)>;
2243 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2244 (VCVTDQ2PDYrm addr:$src)>;
2245 } // Predicates = [HasAVX]
2247 // Convert packed double to packed single
2248 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2249 // register, but the same isn't true when using memory operands instead.
2250 // Provide other assembly rr and rm forms to address this explicitly.
2251 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2252 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2253 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2254 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2257 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2258 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2259 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2260 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2262 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2263 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2266 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2267 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2269 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2270 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2271 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2272 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2274 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2275 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2276 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2277 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2279 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2280 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2281 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2282 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2283 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2284 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2286 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2287 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2290 // AVX 256-bit register conversion intrinsics
2291 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2292 // whenever possible to avoid declaring two versions of each one.
2293 let Predicates = [HasAVX] in {
2294 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2295 (VCVTDQ2PSYrr VR256:$src)>;
2296 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2297 (VCVTDQ2PSYrm addr:$src)>;
2299 // Match fround and fextend for 128/256-bit conversions
2300 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2301 (VCVTPD2PSrr VR128:$src)>;
2302 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2303 (VCVTPD2PSXrm addr:$src)>;
2304 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2305 (VCVTPD2PSYrr VR256:$src)>;
2306 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2307 (VCVTPD2PSYrm addr:$src)>;
2309 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2310 (VCVTPS2PDrr VR128:$src)>;
2311 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2312 (VCVTPS2PDYrr VR128:$src)>;
2313 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2314 (VCVTPS2PDYrm addr:$src)>;
2317 let Predicates = [UseSSE2] in {
2318 // Match fround and fextend for 128 conversions
2319 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2320 (CVTPD2PSrr VR128:$src)>;
2321 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2322 (CVTPD2PSrm addr:$src)>;
2324 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2325 (CVTPS2PDrr VR128:$src)>;
2328 //===----------------------------------------------------------------------===//
2329 // SSE 1 & 2 - Compare Instructions
2330 //===----------------------------------------------------------------------===//
2332 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2333 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2334 Operand CC, SDNode OpNode, ValueType VT,
2335 PatFrag ld_frag, string asm, string asm_alt,
2337 def rr : SIi8<0xC2, MRMSrcReg,
2338 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2339 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2340 itins.rr>, Sched<[itins.Sched]>;
2341 def rm : SIi8<0xC2, MRMSrcMem,
2342 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2343 [(set RC:$dst, (OpNode (VT RC:$src1),
2344 (ld_frag addr:$src2), imm:$cc))],
2346 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2348 // Accept explicit immediate argument form instead of comparison code.
2349 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2350 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2351 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2352 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2354 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2355 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2356 IIC_SSE_ALU_F32S_RM>,
2357 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2361 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2362 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2363 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2365 XS, VEX_4V, VEX_LIG;
2366 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2367 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2368 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2369 SSE_ALU_F32S>, // same latency as 32 bit compare
2370 XD, VEX_4V, VEX_LIG;
2372 let Constraints = "$src1 = $dst" in {
2373 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2374 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2375 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2377 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2378 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2379 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2384 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2385 Intrinsic Int, string asm, OpndItins itins> {
2386 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2387 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2388 [(set VR128:$dst, (Int VR128:$src1,
2389 VR128:$src, imm:$cc))],
2391 Sched<[itins.Sched]>;
2392 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2393 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2394 [(set VR128:$dst, (Int VR128:$src1,
2395 (load addr:$src), imm:$cc))],
2397 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2400 let isCodeGenOnly = 1 in {
2401 // Aliases to match intrinsics which expect XMM operand(s).
2402 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2403 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2406 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2407 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2408 SSE_ALU_F32S>, // same latency as f32
2410 let Constraints = "$src1 = $dst" in {
2411 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2412 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2414 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2415 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2422 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2423 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2424 ValueType vt, X86MemOperand x86memop,
2425 PatFrag ld_frag, string OpcodeStr> {
2426 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2427 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2428 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2431 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2432 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2433 [(set EFLAGS, (OpNode (vt RC:$src1),
2434 (ld_frag addr:$src2)))],
2436 Sched<[WriteFAddLd, ReadAfterLd]>;
2439 let Defs = [EFLAGS] in {
2440 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2441 "ucomiss">, PS, VEX, VEX_LIG;
2442 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2443 "ucomisd">, PD, VEX, VEX_LIG;
2444 let Pattern = []<dag> in {
2445 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2446 "comiss">, PS, VEX, VEX_LIG;
2447 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2448 "comisd">, PD, VEX, VEX_LIG;
2451 let isCodeGenOnly = 1 in {
2452 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2453 load, "ucomiss">, PS, VEX;
2454 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2455 load, "ucomisd">, PD, VEX;
2457 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2458 load, "comiss">, PS, VEX;
2459 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2460 load, "comisd">, PD, VEX;
2462 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2464 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2467 let Pattern = []<dag> in {
2468 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2470 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2474 let isCodeGenOnly = 1 in {
2475 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2476 load, "ucomiss">, PS;
2477 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2478 load, "ucomisd">, PD;
2480 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2482 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2485 } // Defs = [EFLAGS]
2487 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2488 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2489 Operand CC, Intrinsic Int, string asm,
2490 string asm_alt, Domain d,
2491 OpndItins itins = SSE_ALU_F32P> {
2492 def rri : PIi8<0xC2, MRMSrcReg,
2493 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2494 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2497 def rmi : PIi8<0xC2, MRMSrcMem,
2498 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2499 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2501 Sched<[WriteFAddLd, ReadAfterLd]>;
2503 // Accept explicit immediate argument form instead of comparison code.
2504 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2505 def rri_alt : PIi8<0xC2, MRMSrcReg,
2506 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2507 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2508 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2509 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2510 asm_alt, [], itins.rm, d>,
2511 Sched<[WriteFAddLd, ReadAfterLd]>;
2515 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2516 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2517 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2518 SSEPackedSingle>, PS, VEX_4V;
2519 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2520 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2521 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2522 SSEPackedDouble>, PD, VEX_4V;
2523 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2524 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2525 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2526 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2527 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2528 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2529 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2530 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2531 let Constraints = "$src1 = $dst" in {
2532 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2533 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2534 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2535 SSEPackedSingle, SSE_ALU_F32P>, PS;
2536 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2537 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2538 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2539 SSEPackedDouble, SSE_ALU_F64P>, PD;
2542 let Predicates = [HasAVX] in {
2543 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2544 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2545 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2546 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2547 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2548 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2549 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2550 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2552 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2553 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2554 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2555 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2556 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2557 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2558 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2559 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2562 let Predicates = [UseSSE1] in {
2563 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2564 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2565 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2566 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2569 let Predicates = [UseSSE2] in {
2570 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2571 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2572 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2573 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2576 //===----------------------------------------------------------------------===//
2577 // SSE 1 & 2 - Shuffle Instructions
2578 //===----------------------------------------------------------------------===//
2580 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2581 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2582 ValueType vt, string asm, PatFrag mem_frag,
2584 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2585 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2586 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2587 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2588 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2589 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2590 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2591 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2592 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2593 Sched<[WriteFShuffle]>;
2596 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2597 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2598 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2599 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2600 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2601 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2602 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2603 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2604 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2605 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2606 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2607 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2609 let Constraints = "$src1 = $dst" in {
2610 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2611 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2612 memopv4f32, SSEPackedSingle>, PS;
2613 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2614 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2615 memopv2f64, SSEPackedDouble>, PD;
2618 let Predicates = [HasAVX] in {
2619 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2620 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2621 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2622 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2623 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2625 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2626 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2627 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2628 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2629 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2632 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2633 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2634 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2635 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2636 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2638 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2639 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2640 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2641 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2642 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2645 let Predicates = [UseSSE1] in {
2646 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2647 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2648 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2649 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2650 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2653 let Predicates = [UseSSE2] in {
2654 // Generic SHUFPD patterns
2655 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2656 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2657 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2658 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2659 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2662 //===----------------------------------------------------------------------===//
2663 // SSE 1 & 2 - Unpack FP Instructions
2664 //===----------------------------------------------------------------------===//
2666 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2667 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2668 PatFrag mem_frag, RegisterClass RC,
2669 X86MemOperand x86memop, string asm,
2671 def rr : PI<opc, MRMSrcReg,
2672 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2674 (vt (OpNode RC:$src1, RC:$src2)))],
2675 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2676 def rm : PI<opc, MRMSrcMem,
2677 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2679 (vt (OpNode RC:$src1,
2680 (mem_frag addr:$src2))))],
2682 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2685 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2686 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2687 SSEPackedSingle>, PS, VEX_4V;
2688 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2689 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2690 SSEPackedDouble>, PD, VEX_4V;
2691 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2692 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2693 SSEPackedSingle>, PS, VEX_4V;
2694 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2695 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2696 SSEPackedDouble>, PD, VEX_4V;
2698 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2699 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2700 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2701 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2702 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2704 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2705 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2706 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2707 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2708 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2709 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2711 let Constraints = "$src1 = $dst" in {
2712 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2713 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2714 SSEPackedSingle>, PS;
2715 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2716 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2717 SSEPackedDouble>, PD;
2718 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2719 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2720 SSEPackedSingle>, PS;
2721 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2722 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2723 SSEPackedDouble>, PD;
2724 } // Constraints = "$src1 = $dst"
2726 let Predicates = [HasAVX1Only] in {
2727 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2728 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2729 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2730 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2731 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2732 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2733 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2734 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2736 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2737 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2738 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2739 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2740 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2741 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2742 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2743 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2746 let Predicates = [HasAVX] in {
2747 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2748 // problem is during lowering, where it's not possible to recognize the load
2749 // fold cause it has two uses through a bitcast. One use disappears at isel
2750 // time and the fold opportunity reappears.
2751 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2752 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2755 let Predicates = [UseSSE2] in {
2756 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2757 // problem is during lowering, where it's not possible to recognize the load
2758 // fold cause it has two uses through a bitcast. One use disappears at isel
2759 // time and the fold opportunity reappears.
2760 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2761 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2764 //===----------------------------------------------------------------------===//
2765 // SSE 1 & 2 - Extract Floating-Point Sign mask
2766 //===----------------------------------------------------------------------===//
2768 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2769 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2771 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2772 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2773 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2774 Sched<[WriteVecLogic]>;
2777 let Predicates = [HasAVX] in {
2778 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2779 "movmskps", SSEPackedSingle>, PS, VEX;
2780 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2781 "movmskpd", SSEPackedDouble>, PD, VEX;
2782 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2783 "movmskps", SSEPackedSingle>, PS,
2785 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2786 "movmskpd", SSEPackedDouble>, PD,
2789 def : Pat<(i32 (X86fgetsign FR32:$src)),
2790 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2791 def : Pat<(i64 (X86fgetsign FR32:$src)),
2792 (SUBREG_TO_REG (i64 0),
2793 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2794 def : Pat<(i32 (X86fgetsign FR64:$src)),
2795 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2796 def : Pat<(i64 (X86fgetsign FR64:$src)),
2797 (SUBREG_TO_REG (i64 0),
2798 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2801 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2802 SSEPackedSingle>, PS;
2803 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2804 SSEPackedDouble>, PD;
2806 def : Pat<(i32 (X86fgetsign FR32:$src)),
2807 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2808 Requires<[UseSSE1]>;
2809 def : Pat<(i64 (X86fgetsign FR32:$src)),
2810 (SUBREG_TO_REG (i64 0),
2811 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2812 Requires<[UseSSE1]>;
2813 def : Pat<(i32 (X86fgetsign FR64:$src)),
2814 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2815 Requires<[UseSSE2]>;
2816 def : Pat<(i64 (X86fgetsign FR64:$src)),
2817 (SUBREG_TO_REG (i64 0),
2818 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2819 Requires<[UseSSE2]>;
2821 //===---------------------------------------------------------------------===//
2822 // SSE2 - Packed Integer Logical Instructions
2823 //===---------------------------------------------------------------------===//
2825 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2827 /// PDI_binop_rm - Simple SSE2 binary operator.
2828 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2829 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2830 X86MemOperand x86memop, OpndItins itins,
2831 bit IsCommutable, bit Is2Addr> {
2832 let isCommutable = IsCommutable in
2833 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2834 (ins RC:$src1, RC:$src2),
2836 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2837 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2838 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2839 Sched<[itins.Sched]>;
2840 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2841 (ins RC:$src1, x86memop:$src2),
2843 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2844 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2845 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2846 (bitconvert (memop_frag addr:$src2)))))],
2848 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2850 } // ExeDomain = SSEPackedInt
2852 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2853 ValueType OpVT128, ValueType OpVT256,
2854 OpndItins itins, bit IsCommutable = 0> {
2855 let Predicates = [HasAVX, NoVLX] in
2856 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2857 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2859 let Constraints = "$src1 = $dst" in
2860 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2861 memopv2i64, i128mem, itins, IsCommutable, 1>;
2863 let Predicates = [HasAVX2, NoVLX] in
2864 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2865 OpVT256, VR256, loadv4i64, i256mem, itins,
2866 IsCommutable, 0>, VEX_4V, VEX_L;
2869 // These are ordered here for pattern ordering requirements with the fp versions
2871 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2872 SSE_VEC_BIT_ITINS_P, 1>;
2873 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2874 SSE_VEC_BIT_ITINS_P, 1>;
2875 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2876 SSE_VEC_BIT_ITINS_P, 1>;
2877 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2878 SSE_VEC_BIT_ITINS_P, 0>;
2880 //===----------------------------------------------------------------------===//
2881 // SSE 1 & 2 - Logical Instructions
2882 //===----------------------------------------------------------------------===//
2884 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2886 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2887 SDNode OpNode, OpndItins itins> {
2888 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2889 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2892 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2893 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2896 let Constraints = "$src1 = $dst" in {
2897 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2898 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2901 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2902 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2907 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2908 let isCodeGenOnly = 1 in {
2909 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2911 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2913 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2916 let isCommutable = 0 in
2917 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2921 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2923 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2925 let Predicates = [HasAVX, NoVLX] in {
2926 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2927 !strconcat(OpcodeStr, "ps"), f256mem,
2928 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2929 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2930 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2932 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2933 !strconcat(OpcodeStr, "pd"), f256mem,
2934 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2935 (bc_v4i64 (v4f64 VR256:$src2))))],
2936 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2937 (loadv4i64 addr:$src2)))], 0>,
2940 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2941 // are all promoted to v2i64, and the patterns are covered by the int
2942 // version. This is needed in SSE only, because v2i64 isn't supported on
2943 // SSE1, but only on SSE2.
2944 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2945 !strconcat(OpcodeStr, "ps"), f128mem, [],
2946 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2947 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2949 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2950 !strconcat(OpcodeStr, "pd"), f128mem,
2951 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2952 (bc_v2i64 (v2f64 VR128:$src2))))],
2953 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2954 (loadv2i64 addr:$src2)))], 0>,
2958 let Constraints = "$src1 = $dst" in {
2959 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2960 !strconcat(OpcodeStr, "ps"), f128mem,
2961 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2962 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2963 (memopv2i64 addr:$src2)))]>, PS;
2965 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2966 !strconcat(OpcodeStr, "pd"), f128mem,
2967 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2968 (bc_v2i64 (v2f64 VR128:$src2))))],
2969 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2970 (memopv2i64 addr:$src2)))]>, PD;
2974 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2975 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2976 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2977 let isCommutable = 0 in
2978 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2980 // AVX1 requires type coercions in order to fold loads directly into logical
2982 let Predicates = [HasAVX1Only] in {
2983 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
2984 (VANDPSYrm VR256:$src1, addr:$src2)>;
2985 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
2986 (VORPSYrm VR256:$src1, addr:$src2)>;
2987 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
2988 (VXORPSYrm VR256:$src1, addr:$src2)>;
2989 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
2990 (VANDNPSYrm VR256:$src1, addr:$src2)>;
2993 //===----------------------------------------------------------------------===//
2994 // SSE 1 & 2 - Arithmetic Instructions
2995 //===----------------------------------------------------------------------===//
2997 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3000 /// In addition, we also have a special variant of the scalar form here to
3001 /// represent the associated intrinsic operation. This form is unlike the
3002 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3003 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3005 /// These three forms can each be reg+reg or reg+mem.
3008 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3010 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3011 SDNode OpNode, SizeItins itins> {
3012 let Predicates = [HasAVX, NoVLX] in {
3013 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3014 VR128, v4f32, f128mem, loadv4f32,
3015 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3016 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3017 VR128, v2f64, f128mem, loadv2f64,
3018 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3020 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3021 OpNode, VR256, v8f32, f256mem, loadv8f32,
3022 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3023 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3024 OpNode, VR256, v4f64, f256mem, loadv4f64,
3025 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3028 let Constraints = "$src1 = $dst" in {
3029 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3030 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3032 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3033 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3038 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3040 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3041 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3042 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3043 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3045 let Constraints = "$src1 = $dst" in {
3046 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3047 OpNode, FR32, f32mem, itins.s>, XS;
3048 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3049 OpNode, FR64, f64mem, itins.d>, XD;
3053 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3055 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3056 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3057 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3058 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3059 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3060 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3062 let Constraints = "$src1 = $dst" in {
3063 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3064 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3066 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3067 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3072 // Binary Arithmetic instructions
3073 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3074 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3075 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3076 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3077 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3078 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3079 let isCommutable = 0 in {
3080 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3081 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3082 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3083 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3084 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3085 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3086 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3087 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3088 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3089 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3090 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3091 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3094 let isCodeGenOnly = 1 in {
3095 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3096 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3097 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3098 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3101 // Patterns used to select SSE scalar fp arithmetic instructions from
3102 // a scalar fp operation followed by a blend.
3104 // These patterns know, for example, how to select an ADDSS from a
3105 // float add plus vector insert.
3107 // The effect is that the backend no longer emits unnecessary vector
3108 // insert instructions immediately after SSE scalar fp instructions
3109 // like addss or mulss.
3111 // For example, given the following code:
3112 // __m128 foo(__m128 A, __m128 B) {
3117 // previously we generated:
3118 // addss %xmm0, %xmm1
3119 // movss %xmm1, %xmm0
3122 // addss %xmm1, %xmm0
3124 let Predicates = [UseSSE1] in {
3125 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3126 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3128 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3129 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3130 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3132 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3133 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3134 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3136 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3137 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3138 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3140 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3143 let Predicates = [UseSSE2] in {
3144 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3145 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3146 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3148 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3149 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3150 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3152 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3153 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3154 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3156 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3157 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3158 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3160 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3163 let Predicates = [UseSSE41] in {
3164 // If the subtarget has SSE4.1 but not AVX, the vector insert instruction is
3165 // lowered into a X86insertps or a X86Blendi rather than a X86Movss. When
3166 // selecting SSE scalar single-precision fp arithmetic instructions, make
3167 // sure that we correctly match them.
3169 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3170 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3171 FR32:$src))), (iPTR 0))),
3172 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3173 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3174 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3175 FR32:$src))), (iPTR 0))),
3176 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3177 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3178 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3179 FR32:$src))), (iPTR 0))),
3180 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3181 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3182 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3183 FR32:$src))), (iPTR 0))),
3184 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3186 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3187 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3188 FR32:$src))), (i8 1))),
3189 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3190 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3191 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3192 FR32:$src))), (i8 1))),
3193 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3194 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3195 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3196 FR32:$src))), (i8 1))),
3197 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3198 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3199 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3200 FR32:$src))), (i8 1))),
3201 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3203 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3204 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3205 FR64:$src))), (i8 1))),
3206 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3207 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3208 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3209 FR64:$src))), (i8 1))),
3210 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3211 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3212 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3213 FR64:$src))), (i8 1))),
3214 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3215 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3216 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3217 FR64:$src))), (i8 1))),
3218 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3220 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3221 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3222 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3223 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3224 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3225 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3226 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3227 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3228 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3229 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3230 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3231 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3232 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3233 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3234 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3235 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3238 let Predicates = [HasAVX] in {
3239 // The following patterns select AVX Scalar single/double precision fp
3240 // arithmetic instructions.
3242 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3243 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3245 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3246 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3247 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3249 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3250 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3251 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3253 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3254 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3255 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3257 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3258 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3259 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3260 FR32:$src))), (iPTR 0))),
3261 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3262 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3263 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3264 FR32:$src))), (iPTR 0))),
3265 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3266 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3267 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3268 FR32:$src))), (iPTR 0))),
3269 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3270 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3271 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3272 FR32:$src))), (iPTR 0))),
3273 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3275 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3276 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3277 FR32:$src))), (i8 1))),
3278 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3279 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3280 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3281 FR32:$src))), (i8 1))),
3282 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3283 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3284 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3285 FR32:$src))), (i8 1))),
3286 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3287 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3288 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3289 FR32:$src))), (i8 1))),
3290 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3292 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3293 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3294 FR64:$src))), (i8 1))),
3295 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3296 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3297 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3298 FR64:$src))), (i8 1))),
3299 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3300 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3301 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3302 FR64:$src))), (i8 1))),
3303 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3304 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3305 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3306 FR64:$src))), (i8 1))),
3307 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3309 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3310 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3311 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3312 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3313 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3314 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3315 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3316 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3317 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3318 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3319 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3320 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3321 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3322 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3323 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3324 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3327 // Patterns used to select SSE scalar fp arithmetic instructions from
3328 // a vector packed single/double fp operation followed by a vector insert.
3330 // The effect is that the backend converts the packed fp instruction
3331 // followed by a vector insert into a single SSE scalar fp instruction.
3333 // For example, given the following code:
3334 // __m128 foo(__m128 A, __m128 B) {
3335 // __m128 C = A + B;
3336 // return (__m128) {c[0], a[1], a[2], a[3]};
3339 // previously we generated:
3340 // addps %xmm0, %xmm1
3341 // movss %xmm1, %xmm0
3344 // addss %xmm1, %xmm0
3346 let Predicates = [UseSSE1] in {
3347 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3348 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3349 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3350 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3351 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3352 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3353 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3354 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3355 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3356 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3357 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3358 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3361 let Predicates = [UseSSE2] in {
3362 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3363 // from a packed double-precision fp instruction plus movsd.
3365 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3366 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3367 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3368 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3369 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3370 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3371 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3372 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3373 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3374 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3375 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3376 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3379 let Predicates = [UseSSE41] in {
3380 // With SSE4.1 we may see these operations using X86Blendi rather than
3382 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3383 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3384 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3385 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3386 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3387 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3388 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3389 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3390 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3391 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3392 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3393 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3395 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3396 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3397 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3398 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3399 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3400 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3401 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3402 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3403 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3404 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3405 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3406 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3408 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3409 (v2f64 VR128:$dst), (i8 2))),
3410 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3411 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3412 (v2f64 VR128:$dst), (i8 2))),
3413 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3414 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3415 (v2f64 VR128:$dst), (i8 2))),
3416 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3417 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3418 (v2f64 VR128:$dst), (i8 2))),
3419 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3422 let Predicates = [HasAVX] in {
3423 // The following patterns select AVX Scalar single/double precision fp
3424 // arithmetic instructions from a packed single precision fp instruction
3425 // plus movss/movsd.
3427 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3428 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3429 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3430 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3431 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3432 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3433 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3434 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3435 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3436 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3437 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3438 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3439 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3440 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3441 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3442 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3443 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3444 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3445 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3446 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3447 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3448 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3449 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3450 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3452 // Also handle X86Blendi-based patterns.
3453 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3454 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3455 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3456 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3457 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3458 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3459 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3460 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3461 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3462 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3463 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3464 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3466 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3467 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3468 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3469 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3470 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3471 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3472 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3473 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3474 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3475 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3476 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3477 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3479 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3480 (v2f64 VR128:$dst), (i8 2))),
3481 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3482 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3483 (v2f64 VR128:$dst), (i8 2))),
3484 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3485 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3486 (v2f64 VR128:$dst), (i8 2))),
3487 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3488 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3489 (v2f64 VR128:$dst), (i8 2))),
3490 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3494 /// In addition, we also have a special variant of the scalar form here to
3495 /// represent the associated intrinsic operation. This form is unlike the
3496 /// plain scalar form, in that it takes an entire vector (instead of a
3497 /// scalar) and leaves the top elements undefined.
3499 /// And, we have a special variant form for a full-vector intrinsic form.
3501 let Sched = WriteFSqrt in {
3502 def SSE_SQRTPS : OpndItins<
3503 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3506 def SSE_SQRTSS : OpndItins<
3507 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3510 def SSE_SQRTPD : OpndItins<
3511 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3514 def SSE_SQRTSD : OpndItins<
3515 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3519 let Sched = WriteFRsqrt in {
3520 def SSE_RSQRTPS : OpndItins<
3521 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3524 def SSE_RSQRTSS : OpndItins<
3525 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3529 let Sched = WriteFRcp in {
3530 def SSE_RCPP : OpndItins<
3531 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3534 def SSE_RCPS : OpndItins<
3535 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3539 /// sse1_fp_unop_s - SSE1 unops in scalar form
3540 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3541 /// the HW instructions are 2 operand / destructive.
3542 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3544 let Predicates = [HasAVX], hasSideEffects = 0 in {
3545 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3546 (ins FR32:$src1, FR32:$src2),
3547 !strconcat("v", OpcodeStr,
3548 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3549 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3550 let mayLoad = 1 in {
3551 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3552 (ins FR32:$src1,f32mem:$src2),
3553 !strconcat("v", OpcodeStr,
3554 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3555 []>, VEX_4V, VEX_LIG,
3556 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3557 let isCodeGenOnly = 1 in
3558 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3559 (ins VR128:$src1, ssmem:$src2),
3560 !strconcat("v", OpcodeStr,
3561 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3562 []>, VEX_4V, VEX_LIG,
3563 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3567 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3568 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3569 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3570 // For scalar unary operations, fold a load into the operation
3571 // only in OptForSize mode. It eliminates an instruction, but it also
3572 // eliminates a whole-register clobber (the load), so it introduces a
3573 // partial register update condition.
3574 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3575 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3576 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3577 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3578 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3579 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3580 (ins VR128:$src1, VR128:$src2),
3581 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3582 [], itins.rr>, Sched<[itins.Sched]>;
3583 let mayLoad = 1, hasSideEffects = 0 in
3584 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3585 (ins VR128:$src1, ssmem:$src2),
3586 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3587 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3591 /// sse1_fp_unop_p - SSE1 unops in packed form.
3592 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3594 let Predicates = [HasAVX] in {
3595 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3596 !strconcat("v", OpcodeStr,
3597 "ps\t{$src, $dst|$dst, $src}"),
3598 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3599 itins.rr>, VEX, Sched<[itins.Sched]>;
3600 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3601 !strconcat("v", OpcodeStr,
3602 "ps\t{$src, $dst|$dst, $src}"),
3603 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3604 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3605 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3606 !strconcat("v", OpcodeStr,
3607 "ps\t{$src, $dst|$dst, $src}"),
3608 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3609 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3610 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3611 !strconcat("v", OpcodeStr,
3612 "ps\t{$src, $dst|$dst, $src}"),
3613 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3614 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3617 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3618 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3619 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3620 Sched<[itins.Sched]>;
3621 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3622 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3623 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3624 Sched<[itins.Sched.Folded]>;
3627 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3628 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3629 Intrinsic V4F32Int, Intrinsic V8F32Int,
3631 let isCodeGenOnly = 1 in {
3632 let Predicates = [HasAVX] in {
3633 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3634 !strconcat("v", OpcodeStr,
3635 "ps\t{$src, $dst|$dst, $src}"),
3636 [(set VR128:$dst, (V4F32Int VR128:$src))],
3637 itins.rr>, VEX, Sched<[itins.Sched]>;
3638 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3639 !strconcat("v", OpcodeStr,
3640 "ps\t{$src, $dst|$dst, $src}"),
3641 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3642 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3643 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3644 !strconcat("v", OpcodeStr,
3645 "ps\t{$src, $dst|$dst, $src}"),
3646 [(set VR256:$dst, (V8F32Int VR256:$src))],
3647 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3648 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3650 !strconcat("v", OpcodeStr,
3651 "ps\t{$src, $dst|$dst, $src}"),
3652 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3653 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3656 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3657 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3658 [(set VR128:$dst, (V4F32Int VR128:$src))],
3659 itins.rr>, Sched<[itins.Sched]>;
3660 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3661 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3662 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3663 itins.rm>, Sched<[itins.Sched.Folded]>;
3664 } // isCodeGenOnly = 1
3667 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3668 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3669 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3670 let Predicates = [HasAVX], hasSideEffects = 0 in {
3671 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3672 (ins FR64:$src1, FR64:$src2),
3673 !strconcat("v", OpcodeStr,
3674 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3675 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3676 let mayLoad = 1 in {
3677 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3678 (ins FR64:$src1,f64mem:$src2),
3679 !strconcat("v", OpcodeStr,
3680 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3681 []>, VEX_4V, VEX_LIG,
3682 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3683 let isCodeGenOnly = 1 in
3684 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3685 (ins VR128:$src1, sdmem:$src2),
3686 !strconcat("v", OpcodeStr,
3687 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3688 []>, VEX_4V, VEX_LIG,
3689 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3693 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3694 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3695 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3696 Sched<[itins.Sched]>;
3697 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3698 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3699 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3700 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3701 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3702 let isCodeGenOnly = 1 in {
3703 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3704 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3705 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3706 Sched<[itins.Sched]>;
3707 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3708 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3709 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3710 Sched<[itins.Sched.Folded]>;
3714 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3715 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3716 SDNode OpNode, OpndItins itins> {
3717 let Predicates = [HasAVX] in {
3718 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3719 !strconcat("v", OpcodeStr,
3720 "pd\t{$src, $dst|$dst, $src}"),
3721 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3722 itins.rr>, VEX, Sched<[itins.Sched]>;
3723 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3724 !strconcat("v", OpcodeStr,
3725 "pd\t{$src, $dst|$dst, $src}"),
3726 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3727 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3728 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3729 !strconcat("v", OpcodeStr,
3730 "pd\t{$src, $dst|$dst, $src}"),
3731 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3732 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3733 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3734 !strconcat("v", OpcodeStr,
3735 "pd\t{$src, $dst|$dst, $src}"),
3736 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3737 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3740 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3741 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3742 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3743 Sched<[itins.Sched]>;
3744 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3745 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3746 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3747 Sched<[itins.Sched.Folded]>;
3751 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3752 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3753 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3755 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3757 // Reciprocal approximations. Note that these typically require refinement
3758 // in order to obtain suitable precision.
3759 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3760 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
3761 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3762 int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
3763 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3764 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3765 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3766 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3768 let Predicates = [UseAVX] in {
3769 def : Pat<(f32 (fsqrt FR32:$src)),
3770 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3771 def : Pat<(f32 (fsqrt (load addr:$src))),
3772 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3773 Requires<[HasAVX, OptForSize]>;
3774 def : Pat<(f64 (fsqrt FR64:$src)),
3775 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3776 def : Pat<(f64 (fsqrt (load addr:$src))),
3777 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3778 Requires<[HasAVX, OptForSize]>;
3780 def : Pat<(f32 (X86frsqrt FR32:$src)),
3781 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3782 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3783 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3784 Requires<[HasAVX, OptForSize]>;
3786 def : Pat<(f32 (X86frcp FR32:$src)),
3787 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3788 def : Pat<(f32 (X86frcp (load addr:$src))),
3789 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3790 Requires<[HasAVX, OptForSize]>;
3792 let Predicates = [UseAVX] in {
3793 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3794 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3795 (COPY_TO_REGCLASS VR128:$src, FR32)),
3797 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3798 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3800 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3801 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3802 (COPY_TO_REGCLASS VR128:$src, FR64)),
3804 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3805 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3808 let Predicates = [HasAVX] in {
3809 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3810 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3811 (COPY_TO_REGCLASS VR128:$src, FR32)),
3813 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3814 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3816 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3817 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3818 (COPY_TO_REGCLASS VR128:$src, FR32)),
3820 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3821 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3824 // These are unary operations, but they are modeled as having 2 source operands
3825 // because the high elements of the destination are unchanged in SSE.
3826 let Predicates = [UseSSE1] in {
3827 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3828 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3829 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3830 (RCPSSr_Int VR128:$src, VR128:$src)>;
3831 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3832 (SQRTSSr_Int VR128:$src, VR128:$src)>;
3835 // There is no f64 version of the reciprocal approximation instructions.
3837 //===----------------------------------------------------------------------===//
3838 // SSE 1 & 2 - Non-temporal stores
3839 //===----------------------------------------------------------------------===//
3841 let AddedComplexity = 400 in { // Prefer non-temporal versions
3842 let SchedRW = [WriteStore] in {
3843 let Predicates = [HasAVX, NoVLX] in {
3844 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3845 (ins f128mem:$dst, VR128:$src),
3846 "movntps\t{$src, $dst|$dst, $src}",
3847 [(alignednontemporalstore (v4f32 VR128:$src),
3849 IIC_SSE_MOVNT>, VEX;
3850 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3851 (ins f128mem:$dst, VR128:$src),
3852 "movntpd\t{$src, $dst|$dst, $src}",
3853 [(alignednontemporalstore (v2f64 VR128:$src),
3855 IIC_SSE_MOVNT>, VEX;
3857 let ExeDomain = SSEPackedInt in
3858 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3859 (ins f128mem:$dst, VR128:$src),
3860 "movntdq\t{$src, $dst|$dst, $src}",
3861 [(alignednontemporalstore (v2i64 VR128:$src),
3863 IIC_SSE_MOVNT>, VEX;
3865 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3866 (ins f256mem:$dst, VR256:$src),
3867 "movntps\t{$src, $dst|$dst, $src}",
3868 [(alignednontemporalstore (v8f32 VR256:$src),
3870 IIC_SSE_MOVNT>, VEX, VEX_L;
3871 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3872 (ins f256mem:$dst, VR256:$src),
3873 "movntpd\t{$src, $dst|$dst, $src}",
3874 [(alignednontemporalstore (v4f64 VR256:$src),
3876 IIC_SSE_MOVNT>, VEX, VEX_L;
3877 let ExeDomain = SSEPackedInt in
3878 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3879 (ins f256mem:$dst, VR256:$src),
3880 "movntdq\t{$src, $dst|$dst, $src}",
3881 [(alignednontemporalstore (v4i64 VR256:$src),
3883 IIC_SSE_MOVNT>, VEX, VEX_L;
3886 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3887 "movntps\t{$src, $dst|$dst, $src}",
3888 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3890 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3891 "movntpd\t{$src, $dst|$dst, $src}",
3892 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3895 let ExeDomain = SSEPackedInt in
3896 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3897 "movntdq\t{$src, $dst|$dst, $src}",
3898 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3901 // There is no AVX form for instructions below this point
3902 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3903 "movnti{l}\t{$src, $dst|$dst, $src}",
3904 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3906 PS, Requires<[HasSSE2]>;
3907 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3908 "movnti{q}\t{$src, $dst|$dst, $src}",
3909 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3911 PS, Requires<[HasSSE2]>;
3912 } // SchedRW = [WriteStore]
3914 let Predicates = [HasAVX, NoVLX] in {
3915 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3916 (VMOVNTPSmr addr:$dst, VR128:$src)>;
3919 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3920 (MOVNTPSmr addr:$dst, VR128:$src)>;
3922 } // AddedComplexity
3924 //===----------------------------------------------------------------------===//
3925 // SSE 1 & 2 - Prefetch and memory fence
3926 //===----------------------------------------------------------------------===//
3928 // Prefetch intrinsic.
3929 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3930 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3931 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3932 IIC_SSE_PREFETCH>, TB;
3933 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3934 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3935 IIC_SSE_PREFETCH>, TB;
3936 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3937 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3938 IIC_SSE_PREFETCH>, TB;
3939 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3940 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3941 IIC_SSE_PREFETCH>, TB;
3944 // FIXME: How should flush instruction be modeled?
3945 let SchedRW = [WriteLoad] in {
3947 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3948 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3949 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3952 let SchedRW = [WriteNop] in {
3953 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3954 // was introduced with SSE2, it's backward compatible.
3955 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3956 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3957 OBXS, Requires<[HasSSE2]>;
3960 let SchedRW = [WriteFence] in {
3961 // Load, store, and memory fence
3962 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3963 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3964 TB, Requires<[HasSSE1]>;
3965 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3966 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3967 TB, Requires<[HasSSE2]>;
3968 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3969 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3970 TB, Requires<[HasSSE2]>;
3973 def : Pat<(X86SFence), (SFENCE)>;
3974 def : Pat<(X86LFence), (LFENCE)>;
3975 def : Pat<(X86MFence), (MFENCE)>;
3977 //===----------------------------------------------------------------------===//
3978 // SSE 1 & 2 - Load/Store XCSR register
3979 //===----------------------------------------------------------------------===//
3981 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3982 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3983 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3984 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3985 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3986 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3988 let Predicates = [UseSSE1] in {
3989 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3990 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3991 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3992 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3993 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3994 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3997 //===---------------------------------------------------------------------===//
3998 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3999 //===---------------------------------------------------------------------===//
4001 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4003 let hasSideEffects = 0, SchedRW = [WriteMove] in {
4004 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4005 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
4007 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4008 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
4010 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4011 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4013 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4014 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4019 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4020 SchedRW = [WriteMove] in {
4021 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4022 "movdqa\t{$src, $dst|$dst, $src}", [],
4025 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4026 "movdqa\t{$src, $dst|$dst, $src}", [],
4027 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
4028 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4029 "movdqu\t{$src, $dst|$dst, $src}", [],
4032 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4033 "movdqu\t{$src, $dst|$dst, $src}", [],
4034 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
4037 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4038 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4039 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4040 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4042 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4043 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4045 let Predicates = [HasAVX] in {
4046 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4047 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4049 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4050 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4055 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4056 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
4057 (ins i128mem:$dst, VR128:$src),
4058 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4060 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
4061 (ins i256mem:$dst, VR256:$src),
4062 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4064 let Predicates = [HasAVX] in {
4065 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4066 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4068 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
4069 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4074 let SchedRW = [WriteMove] in {
4075 let hasSideEffects = 0 in
4076 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4077 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
4079 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4080 "movdqu\t{$src, $dst|$dst, $src}",
4081 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4084 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
4085 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4086 "movdqa\t{$src, $dst|$dst, $src}", [],
4089 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4090 "movdqu\t{$src, $dst|$dst, $src}",
4091 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4095 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4096 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4097 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4098 "movdqa\t{$src, $dst|$dst, $src}",
4099 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
4101 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4102 "movdqu\t{$src, $dst|$dst, $src}",
4103 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
4105 XS, Requires<[UseSSE2]>;
4108 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4109 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4110 "movdqa\t{$src, $dst|$dst, $src}",
4111 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
4113 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4114 "movdqu\t{$src, $dst|$dst, $src}",
4115 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
4117 XS, Requires<[UseSSE2]>;
4120 } // ExeDomain = SSEPackedInt
4122 let Predicates = [HasAVX] in {
4123 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4124 (VMOVDQUmr addr:$dst, VR128:$src)>;
4125 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
4126 (VMOVDQUYmr addr:$dst, VR256:$src)>;
4128 let Predicates = [UseSSE2] in
4129 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4130 (MOVDQUmr addr:$dst, VR128:$src)>;
4132 //===---------------------------------------------------------------------===//
4133 // SSE2 - Packed Integer Arithmetic Instructions
4134 //===---------------------------------------------------------------------===//
4136 let Sched = WriteVecIMul in
4137 def SSE_PMADD : OpndItins<
4138 IIC_SSE_PMADD, IIC_SSE_PMADD
4141 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4143 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
4144 RegisterClass RC, PatFrag memop_frag,
4145 X86MemOperand x86memop,
4147 bit IsCommutable = 0,
4149 let isCommutable = IsCommutable in
4150 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4151 (ins RC:$src1, RC:$src2),
4153 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4154 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4155 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
4156 Sched<[itins.Sched]>;
4157 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4158 (ins RC:$src1, x86memop:$src2),
4160 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4161 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4162 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
4163 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
4166 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
4167 Intrinsic IntId256, OpndItins itins,
4168 bit IsCommutable = 0> {
4169 let Predicates = [HasAVX] in
4170 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
4171 VR128, loadv2i64, i128mem, itins,
4172 IsCommutable, 0>, VEX_4V;
4174 let Constraints = "$src1 = $dst" in
4175 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
4176 i128mem, itins, IsCommutable, 1>;
4178 let Predicates = [HasAVX2] in
4179 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
4180 VR256, loadv4i64, i256mem, itins,
4181 IsCommutable, 0>, VEX_4V, VEX_L;
4184 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
4185 string OpcodeStr, SDNode OpNode,
4186 SDNode OpNode2, RegisterClass RC,
4187 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
4188 ShiftOpndItins itins,
4190 // src2 is always 128-bit
4191 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4192 (ins RC:$src1, VR128:$src2),
4194 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4196 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
4197 itins.rr>, Sched<[WriteVecShift]>;
4198 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4199 (ins RC:$src1, i128mem:$src2),
4201 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4203 [(set RC:$dst, (DstVT (OpNode RC:$src1,
4204 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
4205 Sched<[WriteVecShiftLd, ReadAfterLd]>;
4206 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
4207 (ins RC:$src1, i8imm:$src2),
4209 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4210 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4211 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
4212 Sched<[WriteVecShift]>;
4215 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4216 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4217 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4218 PatFrag memop_frag, X86MemOperand x86memop,
4220 bit IsCommutable = 0, bit Is2Addr = 1> {
4221 let isCommutable = IsCommutable in
4222 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4223 (ins RC:$src1, RC:$src2),
4225 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4226 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4227 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4228 Sched<[itins.Sched]>;
4229 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4230 (ins RC:$src1, x86memop:$src2),
4232 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4233 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4234 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4235 (bitconvert (memop_frag addr:$src2)))))]>,
4236 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4238 } // ExeDomain = SSEPackedInt
4240 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4241 SSE_INTALU_ITINS_P, 1>;
4242 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4243 SSE_INTALU_ITINS_P, 1>;
4244 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4245 SSE_INTALU_ITINS_P, 1>;
4246 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4247 SSE_INTALUQ_ITINS_P, 1>;
4248 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4249 SSE_INTMUL_ITINS_P, 1>;
4250 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4251 SSE_INTMUL_ITINS_P, 1>;
4252 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4253 SSE_INTMUL_ITINS_P, 1>;
4254 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4255 SSE_INTALU_ITINS_P, 0>;
4256 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4257 SSE_INTALU_ITINS_P, 0>;
4258 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4259 SSE_INTALU_ITINS_P, 0>;
4260 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4261 SSE_INTALUQ_ITINS_P, 0>;
4262 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4263 SSE_INTALU_ITINS_P, 0>;
4264 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4265 SSE_INTALU_ITINS_P, 0>;
4266 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4267 SSE_INTALU_ITINS_P, 1>;
4268 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4269 SSE_INTALU_ITINS_P, 1>;
4270 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4271 SSE_INTALU_ITINS_P, 1>;
4272 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4273 SSE_INTALU_ITINS_P, 1>;
4276 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4277 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4278 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4279 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4280 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4281 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4282 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4283 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4284 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4285 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4286 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4287 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4288 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4289 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4290 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4291 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4292 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4293 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4294 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4295 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4297 let Predicates = [HasAVX] in
4298 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4299 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4301 let Predicates = [HasAVX2] in
4302 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4303 VR256, loadv4i64, i256mem,
4304 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4305 let Constraints = "$src1 = $dst" in
4306 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4307 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4309 //===---------------------------------------------------------------------===//
4310 // SSE2 - Packed Integer Logical Instructions
4311 //===---------------------------------------------------------------------===//
4313 let Predicates = [HasAVX] in {
4314 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4315 VR128, v8i16, v8i16, bc_v8i16,
4316 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4317 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4318 VR128, v4i32, v4i32, bc_v4i32,
4319 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4320 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4321 VR128, v2i64, v2i64, bc_v2i64,
4322 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4324 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4325 VR128, v8i16, v8i16, bc_v8i16,
4326 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4327 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4328 VR128, v4i32, v4i32, bc_v4i32,
4329 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4330 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4331 VR128, v2i64, v2i64, bc_v2i64,
4332 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4334 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4335 VR128, v8i16, v8i16, bc_v8i16,
4336 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4337 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4338 VR128, v4i32, v4i32, bc_v4i32,
4339 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4341 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4342 // 128-bit logical shifts.
4343 def VPSLLDQri : PDIi8<0x73, MRM7r,
4344 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4345 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4347 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4349 def VPSRLDQri : PDIi8<0x73, MRM3r,
4350 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4351 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4353 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4355 // PSRADQri doesn't exist in SSE[1-3].
4357 } // Predicates = [HasAVX]
4359 let Predicates = [HasAVX2] in {
4360 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4361 VR256, v16i16, v8i16, bc_v8i16,
4362 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4363 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4364 VR256, v8i32, v4i32, bc_v4i32,
4365 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4366 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4367 VR256, v4i64, v2i64, bc_v2i64,
4368 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4370 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4371 VR256, v16i16, v8i16, bc_v8i16,
4372 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4373 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4374 VR256, v8i32, v4i32, bc_v4i32,
4375 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4376 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4377 VR256, v4i64, v2i64, bc_v2i64,
4378 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4380 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4381 VR256, v16i16, v8i16, bc_v8i16,
4382 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4383 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4384 VR256, v8i32, v4i32, bc_v4i32,
4385 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4387 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4388 // 256-bit logical shifts.
4389 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4390 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4391 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4393 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4395 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4396 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4397 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4399 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4401 // PSRADQYri doesn't exist in SSE[1-3].
4403 } // Predicates = [HasAVX2]
4405 let Constraints = "$src1 = $dst" in {
4406 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4407 VR128, v8i16, v8i16, bc_v8i16,
4408 SSE_INTSHIFT_ITINS_P>;
4409 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4410 VR128, v4i32, v4i32, bc_v4i32,
4411 SSE_INTSHIFT_ITINS_P>;
4412 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4413 VR128, v2i64, v2i64, bc_v2i64,
4414 SSE_INTSHIFT_ITINS_P>;
4416 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4417 VR128, v8i16, v8i16, bc_v8i16,
4418 SSE_INTSHIFT_ITINS_P>;
4419 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4420 VR128, v4i32, v4i32, bc_v4i32,
4421 SSE_INTSHIFT_ITINS_P>;
4422 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4423 VR128, v2i64, v2i64, bc_v2i64,
4424 SSE_INTSHIFT_ITINS_P>;
4426 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4427 VR128, v8i16, v8i16, bc_v8i16,
4428 SSE_INTSHIFT_ITINS_P>;
4429 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4430 VR128, v4i32, v4i32, bc_v4i32,
4431 SSE_INTSHIFT_ITINS_P>;
4433 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4434 // 128-bit logical shifts.
4435 def PSLLDQri : PDIi8<0x73, MRM7r,
4436 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4437 "pslldq\t{$src2, $dst|$dst, $src2}",
4439 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4440 IIC_SSE_INTSHDQ_P_RI>;
4441 def PSRLDQri : PDIi8<0x73, MRM3r,
4442 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4443 "psrldq\t{$src2, $dst|$dst, $src2}",
4445 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4446 IIC_SSE_INTSHDQ_P_RI>;
4447 // PSRADQri doesn't exist in SSE[1-3].
4449 } // Constraints = "$src1 = $dst"
4451 let Predicates = [HasAVX] in {
4452 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4453 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4454 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4455 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4456 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4457 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4459 // Shift up / down and insert zero's.
4460 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4461 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4462 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4463 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4466 let Predicates = [HasAVX2] in {
4467 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4468 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4469 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4470 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4473 let Predicates = [UseSSE2] in {
4474 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4475 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4476 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4477 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4478 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4479 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4481 // Shift up / down and insert zero's.
4482 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4483 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4484 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4485 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4488 //===---------------------------------------------------------------------===//
4489 // SSE2 - Packed Integer Comparison Instructions
4490 //===---------------------------------------------------------------------===//
4492 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4493 SSE_INTALU_ITINS_P, 1>;
4494 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4495 SSE_INTALU_ITINS_P, 1>;
4496 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4497 SSE_INTALU_ITINS_P, 1>;
4498 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4499 SSE_INTALU_ITINS_P, 0>;
4500 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4501 SSE_INTALU_ITINS_P, 0>;
4502 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4503 SSE_INTALU_ITINS_P, 0>;
4505 //===---------------------------------------------------------------------===//
4506 // SSE2 - Packed Integer Shuffle Instructions
4507 //===---------------------------------------------------------------------===//
4509 let ExeDomain = SSEPackedInt in {
4510 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4512 let Predicates = [HasAVX] in {
4513 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4514 (ins VR128:$src1, i8imm:$src2),
4515 !strconcat("v", OpcodeStr,
4516 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4518 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4519 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4520 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4521 (ins i128mem:$src1, i8imm:$src2),
4522 !strconcat("v", OpcodeStr,
4523 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4525 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4526 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4527 Sched<[WriteShuffleLd]>;
4530 let Predicates = [HasAVX2] in {
4531 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4532 (ins VR256:$src1, i8imm:$src2),
4533 !strconcat("v", OpcodeStr,
4534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4536 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4537 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4538 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4539 (ins i256mem:$src1, i8imm:$src2),
4540 !strconcat("v", OpcodeStr,
4541 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4543 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4544 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4545 Sched<[WriteShuffleLd]>;
4548 let Predicates = [UseSSE2] in {
4549 def ri : Ii8<0x70, MRMSrcReg,
4550 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4551 !strconcat(OpcodeStr,
4552 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4554 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4555 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4556 def mi : Ii8<0x70, MRMSrcMem,
4557 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4558 !strconcat(OpcodeStr,
4559 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4561 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4562 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4563 Sched<[WriteShuffleLd, ReadAfterLd]>;
4566 } // ExeDomain = SSEPackedInt
4568 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4569 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4570 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4572 let Predicates = [HasAVX] in {
4573 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4574 (VPSHUFDmi addr:$src1, imm:$imm)>;
4575 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4576 (VPSHUFDri VR128:$src1, imm:$imm)>;
4579 let Predicates = [UseSSE2] in {
4580 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4581 (PSHUFDmi addr:$src1, imm:$imm)>;
4582 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4583 (PSHUFDri VR128:$src1, imm:$imm)>;
4586 //===---------------------------------------------------------------------===//
4587 // Packed Integer Pack Instructions (SSE & AVX)
4588 //===---------------------------------------------------------------------===//
4590 let ExeDomain = SSEPackedInt in {
4591 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4592 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4594 def rr : PDI<opc, MRMSrcReg,
4595 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4597 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4598 !strconcat(OpcodeStr,
4599 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4601 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4602 Sched<[WriteShuffle]>;
4603 def rm : PDI<opc, MRMSrcMem,
4604 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4606 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4607 !strconcat(OpcodeStr,
4608 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4610 (OutVT (OpNode VR128:$src1,
4611 (bc_frag (memopv2i64 addr:$src2)))))]>,
4612 Sched<[WriteShuffleLd, ReadAfterLd]>;
4615 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4616 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4617 def Yrr : PDI<opc, MRMSrcReg,
4618 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4619 !strconcat(OpcodeStr,
4620 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4622 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4623 Sched<[WriteShuffle]>;
4624 def Yrm : PDI<opc, MRMSrcMem,
4625 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4626 !strconcat(OpcodeStr,
4627 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4629 (OutVT (OpNode VR256:$src1,
4630 (bc_frag (memopv4i64 addr:$src2)))))]>,
4631 Sched<[WriteShuffleLd, ReadAfterLd]>;
4634 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4635 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4637 def rr : SS48I<opc, MRMSrcReg,
4638 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4640 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4641 !strconcat(OpcodeStr,
4642 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4644 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4645 Sched<[WriteShuffle]>;
4646 def rm : SS48I<opc, MRMSrcMem,
4647 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4649 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4650 !strconcat(OpcodeStr,
4651 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4653 (OutVT (OpNode VR128:$src1,
4654 (bc_frag (memopv2i64 addr:$src2)))))]>,
4655 Sched<[WriteShuffleLd, ReadAfterLd]>;
4658 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4659 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4660 def Yrr : SS48I<opc, MRMSrcReg,
4661 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4662 !strconcat(OpcodeStr,
4663 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4665 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4666 Sched<[WriteShuffle]>;
4667 def Yrm : SS48I<opc, MRMSrcMem,
4668 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4669 !strconcat(OpcodeStr,
4670 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4672 (OutVT (OpNode VR256:$src1,
4673 (bc_frag (memopv4i64 addr:$src2)))))]>,
4674 Sched<[WriteShuffleLd, ReadAfterLd]>;
4677 let Predicates = [HasAVX] in {
4678 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4679 bc_v8i16, 0>, VEX_4V;
4680 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4681 bc_v4i32, 0>, VEX_4V;
4683 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4684 bc_v8i16, 0>, VEX_4V;
4685 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4686 bc_v4i32, 0>, VEX_4V;
4689 let Predicates = [HasAVX2] in {
4690 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4691 bc_v16i16>, VEX_4V, VEX_L;
4692 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4693 bc_v8i32>, VEX_4V, VEX_L;
4695 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4696 bc_v16i16>, VEX_4V, VEX_L;
4697 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4698 bc_v8i32>, VEX_4V, VEX_L;
4701 let Constraints = "$src1 = $dst" in {
4702 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4704 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4707 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4710 let Predicates = [HasSSE41] in
4711 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4714 } // ExeDomain = SSEPackedInt
4716 //===---------------------------------------------------------------------===//
4717 // SSE2 - Packed Integer Unpack Instructions
4718 //===---------------------------------------------------------------------===//
4720 let ExeDomain = SSEPackedInt in {
4721 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4722 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4723 def rr : PDI<opc, MRMSrcReg,
4724 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4726 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4727 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4728 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4729 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4730 def rm : PDI<opc, MRMSrcMem,
4731 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4733 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4734 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4735 [(set VR128:$dst, (OpNode VR128:$src1,
4736 (bc_frag (memopv2i64
4739 Sched<[WriteShuffleLd, ReadAfterLd]>;
4742 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4743 SDNode OpNode, PatFrag bc_frag> {
4744 def Yrr : PDI<opc, MRMSrcReg,
4745 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4746 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4747 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4748 Sched<[WriteShuffle]>;
4749 def Yrm : PDI<opc, MRMSrcMem,
4750 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4751 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4752 [(set VR256:$dst, (OpNode VR256:$src1,
4753 (bc_frag (memopv4i64 addr:$src2))))]>,
4754 Sched<[WriteShuffleLd, ReadAfterLd]>;
4757 let Predicates = [HasAVX] in {
4758 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4759 bc_v16i8, 0>, VEX_4V;
4760 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4761 bc_v8i16, 0>, VEX_4V;
4762 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4763 bc_v4i32, 0>, VEX_4V;
4764 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4765 bc_v2i64, 0>, VEX_4V;
4767 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4768 bc_v16i8, 0>, VEX_4V;
4769 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4770 bc_v8i16, 0>, VEX_4V;
4771 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4772 bc_v4i32, 0>, VEX_4V;
4773 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4774 bc_v2i64, 0>, VEX_4V;
4777 let Predicates = [HasAVX2] in {
4778 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4779 bc_v32i8>, VEX_4V, VEX_L;
4780 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4781 bc_v16i16>, VEX_4V, VEX_L;
4782 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4783 bc_v8i32>, VEX_4V, VEX_L;
4784 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4785 bc_v4i64>, VEX_4V, VEX_L;
4787 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4788 bc_v32i8>, VEX_4V, VEX_L;
4789 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4790 bc_v16i16>, VEX_4V, VEX_L;
4791 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4792 bc_v8i32>, VEX_4V, VEX_L;
4793 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4794 bc_v4i64>, VEX_4V, VEX_L;
4797 let Constraints = "$src1 = $dst" in {
4798 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4800 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4802 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4804 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4807 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4809 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4811 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4813 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4816 } // ExeDomain = SSEPackedInt
4818 //===---------------------------------------------------------------------===//
4819 // SSE2 - Packed Integer Extract and Insert
4820 //===---------------------------------------------------------------------===//
4822 let ExeDomain = SSEPackedInt in {
4823 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4824 def rri : Ii8<0xC4, MRMSrcReg,
4825 (outs VR128:$dst), (ins VR128:$src1,
4826 GR32orGR64:$src2, i32i8imm:$src3),
4828 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4829 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4831 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4832 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4833 def rmi : Ii8<0xC4, MRMSrcMem,
4834 (outs VR128:$dst), (ins VR128:$src1,
4835 i16mem:$src2, i32i8imm:$src3),
4837 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4838 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4840 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4841 imm:$src3))], IIC_SSE_PINSRW>,
4842 Sched<[WriteShuffleLd, ReadAfterLd]>;
4846 let Predicates = [HasAVX] in
4847 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4848 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4849 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4850 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4851 imm:$src2))]>, PD, VEX,
4852 Sched<[WriteShuffle]>;
4853 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4854 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4855 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4856 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4857 imm:$src2))], IIC_SSE_PEXTRW>,
4858 Sched<[WriteShuffleLd, ReadAfterLd]>;
4861 let Predicates = [HasAVX] in
4862 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4864 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4865 defm PINSRW : sse2_pinsrw, PD;
4867 } // ExeDomain = SSEPackedInt
4869 //===---------------------------------------------------------------------===//
4870 // SSE2 - Packed Mask Creation
4871 //===---------------------------------------------------------------------===//
4873 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4875 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4877 "pmovmskb\t{$src, $dst|$dst, $src}",
4878 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4879 IIC_SSE_MOVMSK>, VEX;
4881 let Predicates = [HasAVX2] in {
4882 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4884 "pmovmskb\t{$src, $dst|$dst, $src}",
4885 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4889 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4890 "pmovmskb\t{$src, $dst|$dst, $src}",
4891 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4894 } // ExeDomain = SSEPackedInt
4896 //===---------------------------------------------------------------------===//
4897 // SSE2 - Conditional Store
4898 //===---------------------------------------------------------------------===//
4900 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4902 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4903 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4904 (ins VR128:$src, VR128:$mask),
4905 "maskmovdqu\t{$mask, $src|$src, $mask}",
4906 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4907 IIC_SSE_MASKMOV>, VEX;
4908 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4909 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4910 (ins VR128:$src, VR128:$mask),
4911 "maskmovdqu\t{$mask, $src|$src, $mask}",
4912 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4913 IIC_SSE_MASKMOV>, VEX;
4915 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4916 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4917 "maskmovdqu\t{$mask, $src|$src, $mask}",
4918 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4920 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4921 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4922 "maskmovdqu\t{$mask, $src|$src, $mask}",
4923 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4926 } // ExeDomain = SSEPackedInt
4928 //===---------------------------------------------------------------------===//
4929 // SSE2 - Move Doubleword
4930 //===---------------------------------------------------------------------===//
4932 //===---------------------------------------------------------------------===//
4933 // Move Int Doubleword to Packed Double Int
4935 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4936 "movd\t{$src, $dst|$dst, $src}",
4938 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4939 VEX, Sched<[WriteMove]>;
4940 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4941 "movd\t{$src, $dst|$dst, $src}",
4943 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4945 VEX, Sched<[WriteLoad]>;
4946 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4947 "movq\t{$src, $dst|$dst, $src}",
4949 (v2i64 (scalar_to_vector GR64:$src)))],
4950 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4951 let isCodeGenOnly = 1 in
4952 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4953 "movq\t{$src, $dst|$dst, $src}",
4954 [(set FR64:$dst, (bitconvert GR64:$src))],
4955 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4957 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4958 "movd\t{$src, $dst|$dst, $src}",
4960 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4962 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4963 "movd\t{$src, $dst|$dst, $src}",
4965 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4966 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4967 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4968 "mov{d|q}\t{$src, $dst|$dst, $src}",
4970 (v2i64 (scalar_to_vector GR64:$src)))],
4971 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4972 let isCodeGenOnly = 1 in
4973 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4974 "mov{d|q}\t{$src, $dst|$dst, $src}",
4975 [(set FR64:$dst, (bitconvert GR64:$src))],
4976 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4978 //===---------------------------------------------------------------------===//
4979 // Move Int Doubleword to Single Scalar
4981 let isCodeGenOnly = 1 in {
4982 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4983 "movd\t{$src, $dst|$dst, $src}",
4984 [(set FR32:$dst, (bitconvert GR32:$src))],
4985 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4987 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4988 "movd\t{$src, $dst|$dst, $src}",
4989 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4991 VEX, Sched<[WriteLoad]>;
4992 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4993 "movd\t{$src, $dst|$dst, $src}",
4994 [(set FR32:$dst, (bitconvert GR32:$src))],
4995 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4997 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4998 "movd\t{$src, $dst|$dst, $src}",
4999 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
5000 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5003 //===---------------------------------------------------------------------===//
5004 // Move Packed Doubleword Int to Packed Double Int
5006 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5007 "movd\t{$src, $dst|$dst, $src}",
5008 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5009 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
5011 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
5012 (ins i32mem:$dst, VR128:$src),
5013 "movd\t{$src, $dst|$dst, $src}",
5014 [(store (i32 (vector_extract (v4i32 VR128:$src),
5015 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
5016 VEX, Sched<[WriteStore]>;
5017 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5018 "movd\t{$src, $dst|$dst, $src}",
5019 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5020 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
5022 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
5023 "movd\t{$src, $dst|$dst, $src}",
5024 [(store (i32 (vector_extract (v4i32 VR128:$src),
5025 (iPTR 0))), addr:$dst)],
5026 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5028 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
5029 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5031 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
5032 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5034 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
5035 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5037 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
5038 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5040 //===---------------------------------------------------------------------===//
5041 // Move Packed Doubleword Int first element to Doubleword Int
5043 let SchedRW = [WriteMove] in {
5044 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5045 "movq\t{$src, $dst|$dst, $src}",
5046 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5051 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5052 "mov{d|q}\t{$src, $dst|$dst, $src}",
5053 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5058 //===---------------------------------------------------------------------===//
5059 // Bitcast FR64 <-> GR64
5061 let isCodeGenOnly = 1 in {
5062 let Predicates = [UseAVX] in
5063 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5064 "movq\t{$src, $dst|$dst, $src}",
5065 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
5066 VEX, Sched<[WriteLoad]>;
5067 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5068 "movq\t{$src, $dst|$dst, $src}",
5069 [(set GR64:$dst, (bitconvert FR64:$src))],
5070 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
5071 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5072 "movq\t{$src, $dst|$dst, $src}",
5073 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5074 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5076 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5077 "movq\t{$src, $dst|$dst, $src}",
5078 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
5079 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5080 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5081 "mov{d|q}\t{$src, $dst|$dst, $src}",
5082 [(set GR64:$dst, (bitconvert FR64:$src))],
5083 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5084 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5085 "movq\t{$src, $dst|$dst, $src}",
5086 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5087 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5090 //===---------------------------------------------------------------------===//
5091 // Move Scalar Single to Double Int
5093 let isCodeGenOnly = 1 in {
5094 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5095 "movd\t{$src, $dst|$dst, $src}",
5096 [(set GR32:$dst, (bitconvert FR32:$src))],
5097 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
5098 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5099 "movd\t{$src, $dst|$dst, $src}",
5100 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5101 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5102 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5103 "movd\t{$src, $dst|$dst, $src}",
5104 [(set GR32:$dst, (bitconvert FR32:$src))],
5105 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5106 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5107 "movd\t{$src, $dst|$dst, $src}",
5108 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5109 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5112 //===---------------------------------------------------------------------===//
5113 // Patterns and instructions to describe movd/movq to XMM register zero-extends
5115 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
5116 let AddedComplexity = 15 in {
5117 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5118 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
5119 [(set VR128:$dst, (v2i64 (X86vzmovl
5120 (v2i64 (scalar_to_vector GR64:$src)))))],
5123 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5124 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
5125 [(set VR128:$dst, (v2i64 (X86vzmovl
5126 (v2i64 (scalar_to_vector GR64:$src)))))],
5129 } // isCodeGenOnly, SchedRW
5131 let Predicates = [UseAVX] in {
5132 let AddedComplexity = 15 in
5133 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5134 (VMOVDI2PDIrr GR32:$src)>;
5136 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
5137 let AddedComplexity = 20 in {
5138 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5139 (VMOVDI2PDIrm addr:$src)>;
5140 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5141 (VMOVDI2PDIrm addr:$src)>;
5142 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5143 (VMOVDI2PDIrm addr:$src)>;
5145 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
5146 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
5147 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
5148 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
5149 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5150 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
5151 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
5154 let Predicates = [UseSSE2] in {
5155 let AddedComplexity = 15 in
5156 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5157 (MOVDI2PDIrr GR32:$src)>;
5159 let AddedComplexity = 20 in {
5160 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5161 (MOVDI2PDIrm addr:$src)>;
5162 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5163 (MOVDI2PDIrm addr:$src)>;
5164 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5165 (MOVDI2PDIrm addr:$src)>;
5169 // These are the correct encodings of the instructions so that we know how to
5170 // read correct assembly, even though we continue to emit the wrong ones for
5171 // compatibility with Darwin's buggy assembler.
5172 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5173 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5174 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5175 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5176 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
5177 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5178 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5179 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5180 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5182 //===---------------------------------------------------------------------===//
5183 // SSE2 - Move Quadword
5184 //===---------------------------------------------------------------------===//
5186 //===---------------------------------------------------------------------===//
5187 // Move Quadword Int to Packed Quadword Int
5190 let SchedRW = [WriteLoad] in {
5191 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5192 "vmovq\t{$src, $dst|$dst, $src}",
5194 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
5195 VEX, Requires<[UseAVX]>;
5196 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5197 "movq\t{$src, $dst|$dst, $src}",
5199 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
5201 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
5204 //===---------------------------------------------------------------------===//
5205 // Move Packed Quadword Int to Quadword Int
5207 let SchedRW = [WriteStore] in {
5208 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5209 "movq\t{$src, $dst|$dst, $src}",
5210 [(store (i64 (vector_extract (v2i64 VR128:$src),
5211 (iPTR 0))), addr:$dst)],
5212 IIC_SSE_MOVDQ>, VEX;
5213 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5214 "movq\t{$src, $dst|$dst, $src}",
5215 [(store (i64 (vector_extract (v2i64 VR128:$src),
5216 (iPTR 0))), addr:$dst)],
5220 // For disassembler only
5221 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5222 SchedRW = [WriteVecLogic] in {
5223 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5224 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5225 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5226 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5229 //===---------------------------------------------------------------------===//
5230 // Store / copy lower 64-bits of a XMM register.
5232 let Predicates = [UseAVX] in
5233 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5234 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5235 let Predicates = [UseSSE2] in
5236 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5237 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5239 let isCodeGenOnly = 1, AddedComplexity = 20 in {
5240 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5241 "vmovq\t{$src, $dst|$dst, $src}",
5243 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5244 (loadi64 addr:$src))))))],
5246 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5248 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5249 "movq\t{$src, $dst|$dst, $src}",
5251 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5252 (loadi64 addr:$src))))))],
5254 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5257 let Predicates = [UseAVX], AddedComplexity = 20 in {
5258 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5259 (VMOVZQI2PQIrm addr:$src)>;
5260 def : Pat<(v2i64 (X86vzload addr:$src)),
5261 (VMOVZQI2PQIrm addr:$src)>;
5264 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5265 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5266 (MOVZQI2PQIrm addr:$src)>;
5267 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5270 let Predicates = [HasAVX] in {
5271 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5272 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5273 def : Pat<(v4i64 (X86vzload addr:$src)),
5274 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5277 //===---------------------------------------------------------------------===//
5278 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5279 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5281 let SchedRW = [WriteVecLogic] in {
5282 let AddedComplexity = 15 in
5283 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5284 "vmovq\t{$src, $dst|$dst, $src}",
5285 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5287 XS, VEX, Requires<[UseAVX]>;
5288 let AddedComplexity = 15 in
5289 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5290 "movq\t{$src, $dst|$dst, $src}",
5291 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5293 XS, Requires<[UseSSE2]>;
5296 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5297 let AddedComplexity = 20 in
5298 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5299 "vmovq\t{$src, $dst|$dst, $src}",
5300 [(set VR128:$dst, (v2i64 (X86vzmovl
5301 (loadv2i64 addr:$src))))],
5303 XS, VEX, Requires<[UseAVX]>;
5304 let AddedComplexity = 20 in {
5305 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5306 "movq\t{$src, $dst|$dst, $src}",
5307 [(set VR128:$dst, (v2i64 (X86vzmovl
5308 (loadv2i64 addr:$src))))],
5310 XS, Requires<[UseSSE2]>;
5312 } // isCodeGenOnly, SchedRW
5314 let AddedComplexity = 20 in {
5315 let Predicates = [UseAVX] in {
5316 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5317 (VMOVZPQILo2PQIrr VR128:$src)>;
5319 let Predicates = [UseSSE2] in {
5320 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5321 (MOVZPQILo2PQIrr VR128:$src)>;
5325 //===---------------------------------------------------------------------===//
5326 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5327 //===---------------------------------------------------------------------===//
5328 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5329 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5330 X86MemOperand x86memop> {
5331 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5332 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5333 [(set RC:$dst, (vt (OpNode RC:$src)))],
5334 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5335 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5336 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5337 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5338 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5341 let Predicates = [HasAVX] in {
5342 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5343 v4f32, VR128, loadv4f32, f128mem>, VEX;
5344 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5345 v4f32, VR128, loadv4f32, f128mem>, VEX;
5346 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5347 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5348 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5349 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5351 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5352 memopv4f32, f128mem>;
5353 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5354 memopv4f32, f128mem>;
5356 let Predicates = [HasAVX] in {
5357 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5358 (VMOVSHDUPrr VR128:$src)>;
5359 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5360 (VMOVSHDUPrm addr:$src)>;
5361 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5362 (VMOVSLDUPrr VR128:$src)>;
5363 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5364 (VMOVSLDUPrm addr:$src)>;
5365 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5366 (VMOVSHDUPYrr VR256:$src)>;
5367 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5368 (VMOVSHDUPYrm addr:$src)>;
5369 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5370 (VMOVSLDUPYrr VR256:$src)>;
5371 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5372 (VMOVSLDUPYrm addr:$src)>;
5375 let Predicates = [UseSSE3] in {
5376 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5377 (MOVSHDUPrr VR128:$src)>;
5378 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5379 (MOVSHDUPrm addr:$src)>;
5380 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5381 (MOVSLDUPrr VR128:$src)>;
5382 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5383 (MOVSLDUPrm addr:$src)>;
5386 //===---------------------------------------------------------------------===//
5387 // SSE3 - Replicate Double FP - MOVDDUP
5388 //===---------------------------------------------------------------------===//
5390 multiclass sse3_replicate_dfp<string OpcodeStr> {
5391 let hasSideEffects = 0 in
5392 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5393 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5394 [], IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5395 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5396 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5399 (scalar_to_vector (loadf64 addr:$src)))))],
5400 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5403 // FIXME: Merge with above classe when there're patterns for the ymm version
5404 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5405 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5406 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5407 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5408 Sched<[WriteFShuffle]>;
5409 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5410 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5413 (scalar_to_vector (loadf64 addr:$src)))))]>,
5417 let Predicates = [HasAVX] in {
5418 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5419 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5422 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5424 let Predicates = [HasAVX] in {
5425 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5426 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5427 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5428 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5429 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5430 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5431 def : Pat<(X86Movddup (bc_v2f64
5432 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5433 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5436 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5437 (VMOVDDUPYrm addr:$src)>;
5438 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5439 (VMOVDDUPYrm addr:$src)>;
5440 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5441 (VMOVDDUPYrm addr:$src)>;
5442 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5443 (VMOVDDUPYrr VR256:$src)>;
5446 let Predicates = [UseAVX, OptForSize] in {
5447 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5448 (VMOVDDUPrm addr:$src)>;
5449 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5450 (VMOVDDUPrm addr:$src)>;
5453 let Predicates = [UseSSE3] in {
5454 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5455 (MOVDDUPrm addr:$src)>;
5456 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5457 (MOVDDUPrm addr:$src)>;
5458 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5459 (MOVDDUPrm addr:$src)>;
5460 def : Pat<(X86Movddup (bc_v2f64
5461 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5462 (MOVDDUPrm addr:$src)>;
5465 //===---------------------------------------------------------------------===//
5466 // SSE3 - Move Unaligned Integer
5467 //===---------------------------------------------------------------------===//
5469 let SchedRW = [WriteLoad] in {
5470 let Predicates = [HasAVX] in {
5471 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5472 "vlddqu\t{$src, $dst|$dst, $src}",
5473 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5474 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5475 "vlddqu\t{$src, $dst|$dst, $src}",
5476 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5479 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5480 "lddqu\t{$src, $dst|$dst, $src}",
5481 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5485 //===---------------------------------------------------------------------===//
5486 // SSE3 - Arithmetic
5487 //===---------------------------------------------------------------------===//
5489 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5490 X86MemOperand x86memop, OpndItins itins,
5492 def rr : I<0xD0, MRMSrcReg,
5493 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5495 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5496 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5497 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5498 Sched<[itins.Sched]>;
5499 def rm : I<0xD0, MRMSrcMem,
5500 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5502 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5503 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5504 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5505 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5508 let Predicates = [HasAVX] in {
5509 let ExeDomain = SSEPackedSingle in {
5510 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5511 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5512 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5513 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5515 let ExeDomain = SSEPackedDouble in {
5516 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5517 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5518 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5519 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5522 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5523 let ExeDomain = SSEPackedSingle in
5524 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5525 f128mem, SSE_ALU_F32P>, XD;
5526 let ExeDomain = SSEPackedDouble in
5527 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5528 f128mem, SSE_ALU_F64P>, PD;
5531 // Patterns used to select 'addsub' instructions.
5532 let Predicates = [HasAVX] in {
5533 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5534 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5535 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5536 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5537 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5538 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5539 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5540 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5542 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5543 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5544 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 (memop addr:$rhs)))),
5545 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5546 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5547 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5548 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 (memop addr:$rhs)))),
5549 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5552 let Predicates = [UseSSE3] in {
5553 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5554 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5555 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5556 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5557 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5558 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5559 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5560 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5563 //===---------------------------------------------------------------------===//
5564 // SSE3 Instructions
5565 //===---------------------------------------------------------------------===//
5568 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5569 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5570 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5572 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5573 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5574 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5577 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5579 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5580 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5581 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5582 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5584 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5585 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5586 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5588 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5589 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5590 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5593 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5595 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5596 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5597 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5598 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5601 let Predicates = [HasAVX] in {
5602 let ExeDomain = SSEPackedSingle in {
5603 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5604 X86fhadd, 0>, VEX_4V;
5605 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5606 X86fhsub, 0>, VEX_4V;
5607 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5608 X86fhadd, 0>, VEX_4V, VEX_L;
5609 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5610 X86fhsub, 0>, VEX_4V, VEX_L;
5612 let ExeDomain = SSEPackedDouble in {
5613 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5614 X86fhadd, 0>, VEX_4V;
5615 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5616 X86fhsub, 0>, VEX_4V;
5617 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5618 X86fhadd, 0>, VEX_4V, VEX_L;
5619 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5620 X86fhsub, 0>, VEX_4V, VEX_L;
5624 let Constraints = "$src1 = $dst" in {
5625 let ExeDomain = SSEPackedSingle in {
5626 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5627 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5629 let ExeDomain = SSEPackedDouble in {
5630 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5631 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5635 //===---------------------------------------------------------------------===//
5636 // SSSE3 - Packed Absolute Instructions
5637 //===---------------------------------------------------------------------===//
5640 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5641 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5642 Intrinsic IntId128> {
5643 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5645 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5646 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5647 Sched<[WriteVecALU]>;
5649 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5651 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5654 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5655 Sched<[WriteVecALULd]>;
5658 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5659 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5660 Intrinsic IntId256> {
5661 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5663 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5664 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5665 Sched<[WriteVecALU]>;
5667 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5669 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5672 (bitconvert (memopv4i64 addr:$src))))]>,
5673 Sched<[WriteVecALULd]>;
5676 // Helper fragments to match sext vXi1 to vXiY.
5677 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5679 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5680 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5681 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5683 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5684 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5686 let Predicates = [HasAVX] in {
5687 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5688 int_x86_ssse3_pabs_b_128>, VEX;
5689 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5690 int_x86_ssse3_pabs_w_128>, VEX;
5691 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5692 int_x86_ssse3_pabs_d_128>, VEX;
5695 (bc_v2i64 (v16i1sextv16i8)),
5696 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5697 (VPABSBrr128 VR128:$src)>;
5699 (bc_v2i64 (v8i1sextv8i16)),
5700 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5701 (VPABSWrr128 VR128:$src)>;
5703 (bc_v2i64 (v4i1sextv4i32)),
5704 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5705 (VPABSDrr128 VR128:$src)>;
5708 let Predicates = [HasAVX2] in {
5709 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5710 int_x86_avx2_pabs_b>, VEX, VEX_L;
5711 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5712 int_x86_avx2_pabs_w>, VEX, VEX_L;
5713 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5714 int_x86_avx2_pabs_d>, VEX, VEX_L;
5717 (bc_v4i64 (v32i1sextv32i8)),
5718 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5719 (VPABSBrr256 VR256:$src)>;
5721 (bc_v4i64 (v16i1sextv16i16)),
5722 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5723 (VPABSWrr256 VR256:$src)>;
5725 (bc_v4i64 (v8i1sextv8i32)),
5726 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5727 (VPABSDrr256 VR256:$src)>;
5730 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5731 int_x86_ssse3_pabs_b_128>;
5732 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5733 int_x86_ssse3_pabs_w_128>;
5734 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5735 int_x86_ssse3_pabs_d_128>;
5737 let Predicates = [HasSSSE3] in {
5739 (bc_v2i64 (v16i1sextv16i8)),
5740 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5741 (PABSBrr128 VR128:$src)>;
5743 (bc_v2i64 (v8i1sextv8i16)),
5744 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5745 (PABSWrr128 VR128:$src)>;
5747 (bc_v2i64 (v4i1sextv4i32)),
5748 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5749 (PABSDrr128 VR128:$src)>;
5752 //===---------------------------------------------------------------------===//
5753 // SSSE3 - Packed Binary Operator Instructions
5754 //===---------------------------------------------------------------------===//
5756 let Sched = WriteVecALU in {
5757 def SSE_PHADDSUBD : OpndItins<
5758 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5760 def SSE_PHADDSUBSW : OpndItins<
5761 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5763 def SSE_PHADDSUBW : OpndItins<
5764 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5767 let Sched = WriteShuffle in
5768 def SSE_PSHUFB : OpndItins<
5769 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5771 let Sched = WriteVecALU in
5772 def SSE_PSIGN : OpndItins<
5773 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5775 let Sched = WriteVecIMul in
5776 def SSE_PMULHRSW : OpndItins<
5777 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5780 /// SS3I_binop_rm - Simple SSSE3 bin op
5781 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5782 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5783 X86MemOperand x86memop, OpndItins itins,
5785 let isCommutable = 1 in
5786 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5787 (ins RC:$src1, RC:$src2),
5789 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5790 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5791 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5792 Sched<[itins.Sched]>;
5793 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5794 (ins RC:$src1, x86memop:$src2),
5796 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5797 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5799 (OpVT (OpNode RC:$src1,
5800 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5801 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5804 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5805 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5806 Intrinsic IntId128, OpndItins itins,
5808 let isCommutable = 1 in
5809 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5810 (ins VR128:$src1, VR128:$src2),
5812 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5813 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5814 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5815 Sched<[itins.Sched]>;
5816 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5817 (ins VR128:$src1, i128mem:$src2),
5819 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5820 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5822 (IntId128 VR128:$src1,
5823 (bitconvert (memopv2i64 addr:$src2))))]>,
5824 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5827 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5829 X86FoldableSchedWrite Sched> {
5830 let isCommutable = 1 in
5831 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5832 (ins VR256:$src1, VR256:$src2),
5833 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5834 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5836 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5837 (ins VR256:$src1, i256mem:$src2),
5838 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5840 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5841 Sched<[Sched.Folded, ReadAfterLd]>;
5844 let ImmT = NoImm, Predicates = [HasAVX] in {
5845 let isCommutable = 0 in {
5846 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5848 SSE_PHADDSUBW, 0>, VEX_4V;
5849 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5851 SSE_PHADDSUBD, 0>, VEX_4V;
5852 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5854 SSE_PHADDSUBW, 0>, VEX_4V;
5855 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5857 SSE_PHADDSUBD, 0>, VEX_4V;
5858 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5860 SSE_PSIGN, 0>, VEX_4V;
5861 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5863 SSE_PSIGN, 0>, VEX_4V;
5864 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5866 SSE_PSIGN, 0>, VEX_4V;
5867 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5869 SSE_PSHUFB, 0>, VEX_4V;
5870 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5871 int_x86_ssse3_phadd_sw_128,
5872 SSE_PHADDSUBSW, 0>, VEX_4V;
5873 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5874 int_x86_ssse3_phsub_sw_128,
5875 SSE_PHADDSUBSW, 0>, VEX_4V;
5876 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5877 int_x86_ssse3_pmadd_ub_sw_128,
5878 SSE_PMADD, 0>, VEX_4V;
5880 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5881 int_x86_ssse3_pmul_hr_sw_128,
5882 SSE_PMULHRSW, 0>, VEX_4V;
5885 let ImmT = NoImm, Predicates = [HasAVX2] in {
5886 let isCommutable = 0 in {
5887 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5889 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5890 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5892 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5893 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5895 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5896 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5898 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5899 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5901 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5902 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5904 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5905 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5907 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5908 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5910 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5911 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5912 int_x86_avx2_phadd_sw,
5913 WriteVecALU>, VEX_4V, VEX_L;
5914 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5915 int_x86_avx2_phsub_sw,
5916 WriteVecALU>, VEX_4V, VEX_L;
5917 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5918 int_x86_avx2_pmadd_ub_sw,
5919 WriteVecIMul>, VEX_4V, VEX_L;
5921 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5922 int_x86_avx2_pmul_hr_sw,
5923 WriteVecIMul>, VEX_4V, VEX_L;
5926 // None of these have i8 immediate fields.
5927 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5928 let isCommutable = 0 in {
5929 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5930 memopv2i64, i128mem, SSE_PHADDSUBW>;
5931 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5932 memopv2i64, i128mem, SSE_PHADDSUBD>;
5933 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5934 memopv2i64, i128mem, SSE_PHADDSUBW>;
5935 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5936 memopv2i64, i128mem, SSE_PHADDSUBD>;
5937 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5938 memopv2i64, i128mem, SSE_PSIGN>;
5939 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5940 memopv2i64, i128mem, SSE_PSIGN>;
5941 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5942 memopv2i64, i128mem, SSE_PSIGN>;
5943 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5944 memopv2i64, i128mem, SSE_PSHUFB>;
5945 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5946 int_x86_ssse3_phadd_sw_128,
5948 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5949 int_x86_ssse3_phsub_sw_128,
5951 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5952 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5954 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5955 int_x86_ssse3_pmul_hr_sw_128,
5959 //===---------------------------------------------------------------------===//
5960 // SSSE3 - Packed Align Instruction Patterns
5961 //===---------------------------------------------------------------------===//
5963 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5964 let hasSideEffects = 0 in {
5965 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5966 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5968 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5970 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5971 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5973 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5974 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5976 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5978 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5979 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5983 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5984 let hasSideEffects = 0 in {
5985 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5986 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5988 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5989 []>, Sched<[WriteShuffle]>;
5991 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5992 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5994 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5995 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5999 let Predicates = [HasAVX] in
6000 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
6001 let Predicates = [HasAVX2] in
6002 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
6003 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
6004 defm PALIGN : ssse3_palignr<"palignr">;
6006 let Predicates = [HasAVX2] in {
6007 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6008 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6009 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6010 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6011 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6012 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6013 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6014 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6017 let Predicates = [HasAVX] in {
6018 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6019 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6020 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6021 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6022 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6023 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6024 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6025 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6028 let Predicates = [UseSSSE3] in {
6029 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6030 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6031 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6032 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6033 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6034 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6035 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6036 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6039 //===---------------------------------------------------------------------===//
6040 // SSSE3 - Thread synchronization
6041 //===---------------------------------------------------------------------===//
6043 let SchedRW = [WriteSystem] in {
6044 let usesCustomInserter = 1 in {
6045 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
6046 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
6047 Requires<[HasSSE3]>;
6050 let Uses = [EAX, ECX, EDX] in
6051 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
6052 TB, Requires<[HasSSE3]>;
6053 let Uses = [ECX, EAX] in
6054 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
6055 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
6056 TB, Requires<[HasSSE3]>;
6059 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
6060 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
6062 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
6063 Requires<[Not64BitMode]>;
6064 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
6065 Requires<[In64BitMode]>;
6067 //===----------------------------------------------------------------------===//
6068 // SSE4.1 - Packed Move with Sign/Zero Extend
6069 //===----------------------------------------------------------------------===//
6071 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
6072 RegisterClass OutRC, RegisterClass InRC,
6074 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
6075 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6077 Sched<[itins.Sched]>;
6079 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
6080 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6082 itins.rm>, Sched<[itins.Sched.Folded]>;
6085 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
6086 X86MemOperand MemOp, X86MemOperand MemYOp,
6087 OpndItins SSEItins, OpndItins AVXItins,
6088 OpndItins AVX2Itins> {
6089 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
6090 let Predicates = [HasAVX] in
6091 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
6092 VR128, VR128, AVXItins>, VEX;
6093 let Predicates = [HasAVX2] in
6094 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
6095 VR256, VR128, AVX2Itins>, VEX, VEX_L;
6098 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
6099 X86MemOperand MemOp, X86MemOperand MemYOp> {
6100 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
6102 SSE_INTALU_ITINS_SHUFF_P,
6103 DEFAULT_ITINS_SHUFFLESCHED,
6104 DEFAULT_ITINS_SHUFFLESCHED>;
6105 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
6106 !strconcat("pmovzx", OpcodeStr),
6108 SSE_INTALU_ITINS_SHUFF_P,
6109 DEFAULT_ITINS_SHUFFLESCHED,
6110 DEFAULT_ITINS_SHUFFLESCHED>;
6113 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
6114 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
6115 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
6117 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
6118 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
6120 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
6123 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, SDNode ExtOp> {
6124 // Register-Register patterns
6125 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
6126 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
6127 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
6128 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
6129 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
6130 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
6132 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
6133 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
6134 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
6135 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
6137 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
6138 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
6140 // On AVX2, we also support 256bit inputs.
6141 // FIXME: remove these patterns when the old shuffle lowering goes away.
6142 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
6143 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6144 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
6145 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6146 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
6147 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6149 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
6150 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6151 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
6152 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6154 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
6155 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6157 // AVX2 Register-Memory patterns
6158 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6159 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6160 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6161 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6162 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6163 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6164 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6165 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6167 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6168 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6169 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6170 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6171 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6172 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6173 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6174 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6176 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6177 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6178 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6179 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6180 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6181 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6182 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6183 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6185 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6186 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6187 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6188 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6189 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6190 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6191 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6192 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6194 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6195 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6196 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6197 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6198 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6199 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6200 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6201 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6203 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6204 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6205 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6206 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6207 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6208 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6209 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6210 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6213 let Predicates = [HasAVX2] in {
6214 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", X86vsext>;
6215 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", X86vzext>;
6218 // SSE4.1/AVX patterns.
6219 multiclass SS41I_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
6220 PatFrag ExtLoad16> {
6221 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6222 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6223 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6224 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6225 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6226 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6228 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6229 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6230 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6231 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6233 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6234 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6236 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6237 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6238 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6239 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6240 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6241 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6242 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6243 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6244 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6245 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6247 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6248 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6249 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6250 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6251 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6252 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6253 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6254 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6256 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6257 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6258 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6259 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6260 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6261 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6262 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6263 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6265 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6266 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6267 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6268 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6269 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6270 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6271 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6272 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6273 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6274 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6276 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6277 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6278 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6279 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6280 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6281 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6282 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6283 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6285 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6286 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6287 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6288 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6289 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6290 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6291 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6292 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6293 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6294 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6297 let Predicates = [HasAVX] in {
6298 defm : SS41I_pmovx_patterns<"VPMOVSX", X86vsext, extloadi32i16>;
6299 defm : SS41I_pmovx_patterns<"VPMOVZX", X86vzext, loadi16_anyext>;
6302 let Predicates = [UseSSE41] in {
6303 defm : SS41I_pmovx_patterns<"PMOVSX", X86vsext, extloadi32i16>;
6304 defm : SS41I_pmovx_patterns<"PMOVZX", X86vzext, loadi16_anyext>;
6307 //===----------------------------------------------------------------------===//
6308 // SSE4.1 - Extract Instructions
6309 //===----------------------------------------------------------------------===//
6311 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6312 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6313 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6314 (ins VR128:$src1, i32i8imm:$src2),
6315 !strconcat(OpcodeStr,
6316 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6317 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6319 Sched<[WriteShuffle]>;
6320 let hasSideEffects = 0, mayStore = 1,
6321 SchedRW = [WriteShuffleLd, WriteRMW] in
6322 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6323 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6324 !strconcat(OpcodeStr,
6325 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6326 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6327 imm:$src2)))), addr:$dst)]>;
6330 let Predicates = [HasAVX] in
6331 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6333 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6336 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6337 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6338 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6339 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6340 (ins VR128:$src1, i32i8imm:$src2),
6341 !strconcat(OpcodeStr,
6342 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6343 []>, Sched<[WriteShuffle]>;
6345 let hasSideEffects = 0, mayStore = 1,
6346 SchedRW = [WriteShuffleLd, WriteRMW] in
6347 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6348 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6349 !strconcat(OpcodeStr,
6350 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6351 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6352 imm:$src2)))), addr:$dst)]>;
6355 let Predicates = [HasAVX] in
6356 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6358 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6361 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6362 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6363 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6364 (ins VR128:$src1, i32i8imm:$src2),
6365 !strconcat(OpcodeStr,
6366 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6368 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6369 Sched<[WriteShuffle]>;
6370 let SchedRW = [WriteShuffleLd, WriteRMW] in
6371 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6372 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6373 !strconcat(OpcodeStr,
6374 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6375 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6379 let Predicates = [HasAVX] in
6380 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6382 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6384 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6385 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6386 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6387 (ins VR128:$src1, i32i8imm:$src2),
6388 !strconcat(OpcodeStr,
6389 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6391 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6392 Sched<[WriteShuffle]>, REX_W;
6393 let SchedRW = [WriteShuffleLd, WriteRMW] in
6394 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6395 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6396 !strconcat(OpcodeStr,
6397 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6398 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6399 addr:$dst)]>, REX_W;
6402 let Predicates = [HasAVX] in
6403 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6405 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6407 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6409 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6410 OpndItins itins = DEFAULT_ITINS> {
6411 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6412 (ins VR128:$src1, i32i8imm:$src2),
6413 !strconcat(OpcodeStr,
6414 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6415 [(set GR32orGR64:$dst,
6416 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6417 itins.rr>, Sched<[WriteFBlend]>;
6418 let SchedRW = [WriteFBlendLd, WriteRMW] in
6419 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6420 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6421 !strconcat(OpcodeStr,
6422 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6423 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6424 addr:$dst)], itins.rm>;
6427 let ExeDomain = SSEPackedSingle in {
6428 let Predicates = [UseAVX] in
6429 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6430 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6433 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6434 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6437 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6439 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6442 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6443 Requires<[UseSSE41]>;
6445 //===----------------------------------------------------------------------===//
6446 // SSE4.1 - Insert Instructions
6447 //===----------------------------------------------------------------------===//
6449 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6450 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6451 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6453 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6455 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6457 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6458 Sched<[WriteShuffle]>;
6459 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6460 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6462 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6464 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6466 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6467 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6470 let Predicates = [HasAVX] in
6471 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6472 let Constraints = "$src1 = $dst" in
6473 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6475 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6476 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6477 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6479 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6481 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6483 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6484 Sched<[WriteShuffle]>;
6485 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6486 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6488 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6490 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6492 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6493 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6496 let Predicates = [HasAVX] in
6497 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6498 let Constraints = "$src1 = $dst" in
6499 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6501 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6502 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6503 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6505 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6507 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6509 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6510 Sched<[WriteShuffle]>;
6511 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6512 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6514 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6516 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6518 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6519 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6522 let Predicates = [HasAVX] in
6523 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6524 let Constraints = "$src1 = $dst" in
6525 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6527 // insertps has a few different modes, there's the first two here below which
6528 // are optimized inserts that won't zero arbitrary elements in the destination
6529 // vector. The next one matches the intrinsic and could zero arbitrary elements
6530 // in the target vector.
6531 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6532 OpndItins itins = DEFAULT_ITINS> {
6533 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6534 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6536 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6538 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6540 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6541 Sched<[WriteFShuffle]>;
6542 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6543 (ins VR128:$src1, f32mem:$src2, i8imm:$src3),
6545 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6547 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6549 (X86insertps VR128:$src1,
6550 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6551 imm:$src3))], itins.rm>,
6552 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6555 let ExeDomain = SSEPackedSingle in {
6556 let Predicates = [UseAVX] in
6557 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6558 let Constraints = "$src1 = $dst" in
6559 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6562 let Predicates = [UseSSE41] in {
6563 // If we're inserting an element from a load or a null pshuf of a load,
6564 // fold the load into the insertps instruction.
6565 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6566 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6568 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6569 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6570 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6571 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6574 let Predicates = [UseAVX] in {
6575 // If we're inserting an element from a vbroadcast of a load, fold the
6576 // load into the X86insertps instruction.
6577 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6578 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6579 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6580 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6581 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6582 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6585 //===----------------------------------------------------------------------===//
6586 // SSE4.1 - Round Instructions
6587 //===----------------------------------------------------------------------===//
6589 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6590 X86MemOperand x86memop, RegisterClass RC,
6591 PatFrag mem_frag32, PatFrag mem_frag64,
6592 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6593 let ExeDomain = SSEPackedSingle in {
6594 // Intrinsic operation, reg.
6595 // Vector intrinsic operation, reg
6596 def PSr : SS4AIi8<opcps, MRMSrcReg,
6597 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6598 !strconcat(OpcodeStr,
6599 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6600 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6601 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6603 // Vector intrinsic operation, mem
6604 def PSm : SS4AIi8<opcps, MRMSrcMem,
6605 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6606 !strconcat(OpcodeStr,
6607 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6609 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6610 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6611 } // ExeDomain = SSEPackedSingle
6613 let ExeDomain = SSEPackedDouble in {
6614 // Vector intrinsic operation, reg
6615 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6616 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6617 !strconcat(OpcodeStr,
6618 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6619 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6620 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6622 // Vector intrinsic operation, mem
6623 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6624 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6625 !strconcat(OpcodeStr,
6626 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6628 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6629 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6630 } // ExeDomain = SSEPackedDouble
6633 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6636 Intrinsic F64Int, bit Is2Addr = 1> {
6637 let ExeDomain = GenericDomain in {
6639 let hasSideEffects = 0 in
6640 def SSr : SS4AIi8<opcss, MRMSrcReg,
6641 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6643 !strconcat(OpcodeStr,
6644 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6645 !strconcat(OpcodeStr,
6646 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6647 []>, Sched<[WriteFAdd]>;
6649 // Intrinsic operation, reg.
6650 let isCodeGenOnly = 1 in
6651 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6652 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6654 !strconcat(OpcodeStr,
6655 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6656 !strconcat(OpcodeStr,
6657 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6658 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6661 // Intrinsic operation, mem.
6662 def SSm : SS4AIi8<opcss, MRMSrcMem,
6663 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6665 !strconcat(OpcodeStr,
6666 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6667 !strconcat(OpcodeStr,
6668 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6670 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6671 Sched<[WriteFAddLd, ReadAfterLd]>;
6674 let hasSideEffects = 0 in
6675 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6676 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6678 !strconcat(OpcodeStr,
6679 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6680 !strconcat(OpcodeStr,
6681 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6682 []>, Sched<[WriteFAdd]>;
6684 // Intrinsic operation, reg.
6685 let isCodeGenOnly = 1 in
6686 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6687 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6689 !strconcat(OpcodeStr,
6690 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6691 !strconcat(OpcodeStr,
6692 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6693 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6696 // Intrinsic operation, mem.
6697 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6698 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6700 !strconcat(OpcodeStr,
6701 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6702 !strconcat(OpcodeStr,
6703 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6705 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6706 Sched<[WriteFAddLd, ReadAfterLd]>;
6707 } // ExeDomain = GenericDomain
6710 // FP round - roundss, roundps, roundsd, roundpd
6711 let Predicates = [HasAVX] in {
6713 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6714 loadv4f32, loadv2f64,
6715 int_x86_sse41_round_ps,
6716 int_x86_sse41_round_pd>, VEX;
6717 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6718 loadv8f32, loadv4f64,
6719 int_x86_avx_round_ps_256,
6720 int_x86_avx_round_pd_256>, VEX, VEX_L;
6721 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6722 int_x86_sse41_round_ss,
6723 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6725 def : Pat<(ffloor FR32:$src),
6726 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6727 def : Pat<(f64 (ffloor FR64:$src)),
6728 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6729 def : Pat<(f32 (fnearbyint FR32:$src)),
6730 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6731 def : Pat<(f64 (fnearbyint FR64:$src)),
6732 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6733 def : Pat<(f32 (fceil FR32:$src)),
6734 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6735 def : Pat<(f64 (fceil FR64:$src)),
6736 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6737 def : Pat<(f32 (frint FR32:$src)),
6738 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6739 def : Pat<(f64 (frint FR64:$src)),
6740 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6741 def : Pat<(f32 (ftrunc FR32:$src)),
6742 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6743 def : Pat<(f64 (ftrunc FR64:$src)),
6744 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6746 def : Pat<(v4f32 (ffloor VR128:$src)),
6747 (VROUNDPSr VR128:$src, (i32 0x1))>;
6748 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6749 (VROUNDPSr VR128:$src, (i32 0xC))>;
6750 def : Pat<(v4f32 (fceil VR128:$src)),
6751 (VROUNDPSr VR128:$src, (i32 0x2))>;
6752 def : Pat<(v4f32 (frint VR128:$src)),
6753 (VROUNDPSr VR128:$src, (i32 0x4))>;
6754 def : Pat<(v4f32 (ftrunc VR128:$src)),
6755 (VROUNDPSr VR128:$src, (i32 0x3))>;
6757 def : Pat<(v2f64 (ffloor VR128:$src)),
6758 (VROUNDPDr VR128:$src, (i32 0x1))>;
6759 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6760 (VROUNDPDr VR128:$src, (i32 0xC))>;
6761 def : Pat<(v2f64 (fceil VR128:$src)),
6762 (VROUNDPDr VR128:$src, (i32 0x2))>;
6763 def : Pat<(v2f64 (frint VR128:$src)),
6764 (VROUNDPDr VR128:$src, (i32 0x4))>;
6765 def : Pat<(v2f64 (ftrunc VR128:$src)),
6766 (VROUNDPDr VR128:$src, (i32 0x3))>;
6768 def : Pat<(v8f32 (ffloor VR256:$src)),
6769 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6770 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6771 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6772 def : Pat<(v8f32 (fceil VR256:$src)),
6773 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6774 def : Pat<(v8f32 (frint VR256:$src)),
6775 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6776 def : Pat<(v8f32 (ftrunc VR256:$src)),
6777 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6779 def : Pat<(v4f64 (ffloor VR256:$src)),
6780 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6781 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6782 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6783 def : Pat<(v4f64 (fceil VR256:$src)),
6784 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6785 def : Pat<(v4f64 (frint VR256:$src)),
6786 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6787 def : Pat<(v4f64 (ftrunc VR256:$src)),
6788 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6791 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6792 memopv4f32, memopv2f64,
6793 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6794 let Constraints = "$src1 = $dst" in
6795 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6796 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6798 let Predicates = [UseSSE41] in {
6799 def : Pat<(ffloor FR32:$src),
6800 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6801 def : Pat<(f64 (ffloor FR64:$src)),
6802 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6803 def : Pat<(f32 (fnearbyint FR32:$src)),
6804 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6805 def : Pat<(f64 (fnearbyint FR64:$src)),
6806 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6807 def : Pat<(f32 (fceil FR32:$src)),
6808 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6809 def : Pat<(f64 (fceil FR64:$src)),
6810 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6811 def : Pat<(f32 (frint FR32:$src)),
6812 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6813 def : Pat<(f64 (frint FR64:$src)),
6814 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6815 def : Pat<(f32 (ftrunc FR32:$src)),
6816 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6817 def : Pat<(f64 (ftrunc FR64:$src)),
6818 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6820 def : Pat<(v4f32 (ffloor VR128:$src)),
6821 (ROUNDPSr VR128:$src, (i32 0x1))>;
6822 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6823 (ROUNDPSr VR128:$src, (i32 0xC))>;
6824 def : Pat<(v4f32 (fceil VR128:$src)),
6825 (ROUNDPSr VR128:$src, (i32 0x2))>;
6826 def : Pat<(v4f32 (frint VR128:$src)),
6827 (ROUNDPSr VR128:$src, (i32 0x4))>;
6828 def : Pat<(v4f32 (ftrunc VR128:$src)),
6829 (ROUNDPSr VR128:$src, (i32 0x3))>;
6831 def : Pat<(v2f64 (ffloor VR128:$src)),
6832 (ROUNDPDr VR128:$src, (i32 0x1))>;
6833 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6834 (ROUNDPDr VR128:$src, (i32 0xC))>;
6835 def : Pat<(v2f64 (fceil VR128:$src)),
6836 (ROUNDPDr VR128:$src, (i32 0x2))>;
6837 def : Pat<(v2f64 (frint VR128:$src)),
6838 (ROUNDPDr VR128:$src, (i32 0x4))>;
6839 def : Pat<(v2f64 (ftrunc VR128:$src)),
6840 (ROUNDPDr VR128:$src, (i32 0x3))>;
6843 //===----------------------------------------------------------------------===//
6844 // SSE4.1 - Packed Bit Test
6845 //===----------------------------------------------------------------------===//
6847 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6848 // the intel intrinsic that corresponds to this.
6849 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6850 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6851 "vptest\t{$src2, $src1|$src1, $src2}",
6852 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6853 Sched<[WriteVecLogic]>, VEX;
6854 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6855 "vptest\t{$src2, $src1|$src1, $src2}",
6856 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6857 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6859 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6860 "vptest\t{$src2, $src1|$src1, $src2}",
6861 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6862 Sched<[WriteVecLogic]>, VEX, VEX_L;
6863 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6864 "vptest\t{$src2, $src1|$src1, $src2}",
6865 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6866 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6869 let Defs = [EFLAGS] in {
6870 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6871 "ptest\t{$src2, $src1|$src1, $src2}",
6872 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6873 Sched<[WriteVecLogic]>;
6874 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6875 "ptest\t{$src2, $src1|$src1, $src2}",
6876 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6877 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6880 // The bit test instructions below are AVX only
6881 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6882 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6883 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6884 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6885 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6886 Sched<[WriteVecLogic]>, VEX;
6887 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6888 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6889 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6890 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6893 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6894 let ExeDomain = SSEPackedSingle in {
6895 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6896 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6899 let ExeDomain = SSEPackedDouble in {
6900 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6901 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6906 //===----------------------------------------------------------------------===//
6907 // SSE4.1 - Misc Instructions
6908 //===----------------------------------------------------------------------===//
6910 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6911 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6912 "popcnt{w}\t{$src, $dst|$dst, $src}",
6913 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6914 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6916 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6917 "popcnt{w}\t{$src, $dst|$dst, $src}",
6918 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6919 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6920 Sched<[WriteFAddLd]>, OpSize16, XS;
6922 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6923 "popcnt{l}\t{$src, $dst|$dst, $src}",
6924 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6925 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6928 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6929 "popcnt{l}\t{$src, $dst|$dst, $src}",
6930 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6931 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6932 Sched<[WriteFAddLd]>, OpSize32, XS;
6934 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6935 "popcnt{q}\t{$src, $dst|$dst, $src}",
6936 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6937 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6938 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6939 "popcnt{q}\t{$src, $dst|$dst, $src}",
6940 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6941 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6942 Sched<[WriteFAddLd]>, XS;
6947 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6948 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6950 X86FoldableSchedWrite Sched> {
6951 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6953 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6954 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6956 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6958 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6960 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>,
6961 Sched<[Sched.Folded]>;
6964 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6965 // model, although the naming is misleading.
6966 let Predicates = [HasAVX] in
6967 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6968 int_x86_sse41_phminposuw,
6970 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6971 int_x86_sse41_phminposuw,
6974 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6975 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6976 Intrinsic IntId128, bit Is2Addr = 1,
6977 OpndItins itins = DEFAULT_ITINS> {
6978 let isCommutable = 1 in
6979 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6980 (ins VR128:$src1, VR128:$src2),
6982 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6983 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6984 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
6985 itins.rr>, Sched<[itins.Sched]>;
6986 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6987 (ins VR128:$src1, i128mem:$src2),
6989 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6990 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6992 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
6993 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
6996 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6997 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6999 X86FoldableSchedWrite Sched> {
7000 let isCommutable = 1 in
7001 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
7002 (ins VR256:$src1, VR256:$src2),
7003 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7004 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
7006 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
7007 (ins VR256:$src1, i256mem:$src2),
7008 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7010 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
7011 Sched<[Sched.Folded, ReadAfterLd]>;
7015 /// SS48I_binop_rm - Simple SSE41 binary operator.
7016 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7017 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7018 X86MemOperand x86memop, bit Is2Addr = 1,
7019 OpndItins itins = SSE_INTALU_ITINS_P> {
7020 let isCommutable = 1 in
7021 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7022 (ins RC:$src1, RC:$src2),
7024 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7025 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7026 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7027 Sched<[itins.Sched]>;
7028 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7029 (ins RC:$src1, x86memop:$src2),
7031 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7032 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7034 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
7035 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7038 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
7040 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
7041 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
7042 PatFrag memop_frag, X86MemOperand x86memop,
7044 bit IsCommutable = 0, bit Is2Addr = 1> {
7045 let isCommutable = IsCommutable in
7046 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7047 (ins RC:$src1, RC:$src2),
7049 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7050 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7051 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
7052 Sched<[itins.Sched]>;
7053 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7054 (ins RC:$src1, x86memop:$src2),
7056 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7057 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7058 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
7059 (bitconvert (memop_frag addr:$src2)))))]>,
7060 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7063 let Predicates = [HasAVX, NoVLX] in {
7064 let isCommutable = 0 in
7065 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
7066 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7068 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
7069 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7071 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
7072 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7074 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
7075 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7077 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
7078 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7080 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
7081 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7083 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
7084 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7086 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
7087 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7089 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
7090 VR128, loadv2i64, i128mem,
7091 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
7094 let Predicates = [HasAVX2, NoVLX] in {
7095 let isCommutable = 0 in
7096 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
7097 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7099 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
7100 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7102 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
7103 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7105 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
7106 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7108 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
7109 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7111 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
7112 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7114 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
7115 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7117 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
7118 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7120 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
7121 VR256, loadv4i64, i256mem,
7122 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
7125 let Constraints = "$src1 = $dst" in {
7126 let isCommutable = 0 in
7127 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
7128 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7129 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
7130 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7131 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
7132 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7133 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
7134 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7135 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
7136 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7137 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
7138 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7139 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
7140 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7141 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7142 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7143 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
7144 VR128, memopv2i64, i128mem,
7145 SSE_INTMUL_ITINS_P, 1>;
7148 let Predicates = [HasAVX, NoVLX] in {
7149 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7150 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
7152 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7153 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7156 let Predicates = [HasAVX2] in {
7157 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7158 memopv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
7160 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7161 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7165 let Constraints = "$src1 = $dst" in {
7166 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7167 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7168 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7169 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7172 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7173 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7174 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7175 X86MemOperand x86memop, bit Is2Addr = 1,
7176 OpndItins itins = DEFAULT_ITINS> {
7177 let isCommutable = 1 in
7178 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7179 (ins RC:$src1, RC:$src2, i8imm:$src3),
7181 !strconcat(OpcodeStr,
7182 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7183 !strconcat(OpcodeStr,
7184 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7185 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7186 Sched<[itins.Sched]>;
7187 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7188 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
7190 !strconcat(OpcodeStr,
7191 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7192 !strconcat(OpcodeStr,
7193 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7196 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7197 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7200 let Predicates = [HasAVX] in {
7201 let isCommutable = 0 in {
7202 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7203 VR128, loadv2i64, i128mem, 0,
7204 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7207 let ExeDomain = SSEPackedSingle in {
7208 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7209 VR128, loadv4f32, f128mem, 0,
7210 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7211 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7212 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7213 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7216 let ExeDomain = SSEPackedDouble in {
7217 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7218 VR128, loadv2f64, f128mem, 0,
7219 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7220 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7221 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7222 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7225 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7226 VR128, loadv2i64, i128mem, 0,
7227 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7229 let ExeDomain = SSEPackedSingle in
7230 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7231 VR128, loadv4f32, f128mem, 0,
7232 SSE_DPPS_ITINS>, VEX_4V;
7233 let ExeDomain = SSEPackedDouble in
7234 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7235 VR128, loadv2f64, f128mem, 0,
7236 SSE_DPPS_ITINS>, VEX_4V;
7237 let ExeDomain = SSEPackedSingle in
7238 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7239 VR256, loadv8f32, i256mem, 0,
7240 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7243 let Predicates = [HasAVX2] in {
7244 let isCommutable = 0 in {
7245 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7246 VR256, loadv4i64, i256mem, 0,
7247 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7248 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7249 VR256, loadv4i64, i256mem, 0,
7250 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7254 let Constraints = "$src1 = $dst" in {
7255 let isCommutable = 0 in {
7256 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7257 VR128, memopv2i64, i128mem,
7258 1, SSE_MPSADBW_ITINS>;
7260 let ExeDomain = SSEPackedSingle in
7261 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7262 VR128, memopv4f32, f128mem,
7263 1, SSE_INTALU_ITINS_FBLEND_P>;
7264 let ExeDomain = SSEPackedDouble in
7265 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7266 VR128, memopv2f64, f128mem,
7267 1, SSE_INTALU_ITINS_FBLEND_P>;
7268 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7269 VR128, memopv2i64, i128mem,
7270 1, SSE_INTALU_ITINS_BLEND_P>;
7271 let ExeDomain = SSEPackedSingle in
7272 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7273 VR128, memopv4f32, f128mem, 1,
7275 let ExeDomain = SSEPackedDouble in
7276 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7277 VR128, memopv2f64, f128mem, 1,
7281 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7282 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7283 RegisterClass RC, X86MemOperand x86memop,
7284 PatFrag mem_frag, Intrinsic IntId,
7285 X86FoldableSchedWrite Sched> {
7286 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7287 (ins RC:$src1, RC:$src2, RC:$src3),
7288 !strconcat(OpcodeStr,
7289 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7290 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7291 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7294 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7295 (ins RC:$src1, x86memop:$src2, RC:$src3),
7296 !strconcat(OpcodeStr,
7297 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7299 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7301 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7302 Sched<[Sched.Folded, ReadAfterLd]>;
7305 let Predicates = [HasAVX] in {
7306 let ExeDomain = SSEPackedDouble in {
7307 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7308 loadv2f64, int_x86_sse41_blendvpd,
7310 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7311 loadv4f64, int_x86_avx_blendv_pd_256,
7312 WriteFVarBlend>, VEX_L;
7313 } // ExeDomain = SSEPackedDouble
7314 let ExeDomain = SSEPackedSingle in {
7315 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7316 loadv4f32, int_x86_sse41_blendvps,
7318 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7319 loadv8f32, int_x86_avx_blendv_ps_256,
7320 WriteFVarBlend>, VEX_L;
7321 } // ExeDomain = SSEPackedSingle
7322 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7323 loadv2i64, int_x86_sse41_pblendvb,
7327 let Predicates = [HasAVX2] in {
7328 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7329 loadv4i64, int_x86_avx2_pblendvb,
7330 WriteVarBlend>, VEX_L;
7333 let Predicates = [HasAVX] in {
7334 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7335 (v16i8 VR128:$src2))),
7336 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7337 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7338 (v4i32 VR128:$src2))),
7339 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7340 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7341 (v4f32 VR128:$src2))),
7342 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7343 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7344 (v2i64 VR128:$src2))),
7345 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7346 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7347 (v2f64 VR128:$src2))),
7348 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7349 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7350 (v8i32 VR256:$src2))),
7351 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7352 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7353 (v8f32 VR256:$src2))),
7354 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7355 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7356 (v4i64 VR256:$src2))),
7357 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7358 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7359 (v4f64 VR256:$src2))),
7360 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7362 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7364 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7365 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7367 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7369 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7371 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7372 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7374 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7375 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7377 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7380 let Predicates = [HasAVX2] in {
7381 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7382 (v32i8 VR256:$src2))),
7383 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7384 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7386 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7390 let Predicates = [UseAVX] in {
7391 let AddedComplexity = 15 in {
7392 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7393 // MOVS{S,D} to the lower bits.
7394 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7395 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7396 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7397 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7398 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7399 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7400 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7401 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7403 // Move low f32 and clear high bits.
7404 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7405 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7406 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7407 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7410 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7411 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7412 (SUBREG_TO_REG (i32 0),
7413 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7415 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7416 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7417 (SUBREG_TO_REG (i64 0),
7418 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7421 // Move low f64 and clear high bits.
7422 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7423 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7425 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7426 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7429 let Predicates = [UseSSE41] in {
7430 // With SSE41 we can use blends for these patterns.
7431 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7432 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7433 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7434 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7435 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7436 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7440 /// SS41I_ternary_int - SSE 4.1 ternary operator
7441 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7442 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7443 X86MemOperand x86memop, Intrinsic IntId,
7444 OpndItins itins = DEFAULT_ITINS> {
7445 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7446 (ins VR128:$src1, VR128:$src2),
7447 !strconcat(OpcodeStr,
7448 "\t{$src2, $dst|$dst, $src2}"),
7449 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7450 itins.rr>, Sched<[itins.Sched]>;
7452 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7453 (ins VR128:$src1, x86memop:$src2),
7454 !strconcat(OpcodeStr,
7455 "\t{$src2, $dst|$dst, $src2}"),
7458 (bitconvert (mem_frag addr:$src2)), XMM0))],
7459 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7463 let ExeDomain = SSEPackedDouble in
7464 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7465 int_x86_sse41_blendvpd,
7466 DEFAULT_ITINS_FBLENDSCHED>;
7467 let ExeDomain = SSEPackedSingle in
7468 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7469 int_x86_sse41_blendvps,
7470 DEFAULT_ITINS_FBLENDSCHED>;
7471 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7472 int_x86_sse41_pblendvb,
7473 DEFAULT_ITINS_VARBLENDSCHED>;
7475 // Aliases with the implicit xmm0 argument
7476 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7477 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7478 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7479 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7480 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7481 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7482 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7483 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7484 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7485 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7486 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7487 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7489 let Predicates = [UseSSE41] in {
7490 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7491 (v16i8 VR128:$src2))),
7492 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7493 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7494 (v4i32 VR128:$src2))),
7495 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7496 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7497 (v4f32 VR128:$src2))),
7498 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7499 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7500 (v2i64 VR128:$src2))),
7501 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7502 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7503 (v2f64 VR128:$src2))),
7504 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7506 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7508 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7509 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7511 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7512 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7514 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7518 let SchedRW = [WriteLoad] in {
7519 let Predicates = [HasAVX] in
7520 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7521 "vmovntdqa\t{$src, $dst|$dst, $src}",
7522 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7524 let Predicates = [HasAVX2] in
7525 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7526 "vmovntdqa\t{$src, $dst|$dst, $src}",
7527 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7529 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7530 "movntdqa\t{$src, $dst|$dst, $src}",
7531 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7534 //===----------------------------------------------------------------------===//
7535 // SSE4.2 - Compare Instructions
7536 //===----------------------------------------------------------------------===//
7538 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7539 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7540 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7541 X86MemOperand x86memop, bit Is2Addr = 1> {
7542 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7543 (ins RC:$src1, RC:$src2),
7545 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7546 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7547 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7548 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7549 (ins RC:$src1, x86memop:$src2),
7551 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7552 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7554 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7557 let Predicates = [HasAVX] in
7558 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7559 loadv2i64, i128mem, 0>, VEX_4V;
7561 let Predicates = [HasAVX2] in
7562 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7563 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7565 let Constraints = "$src1 = $dst" in
7566 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7567 memopv2i64, i128mem>;
7569 //===----------------------------------------------------------------------===//
7570 // SSE4.2 - String/text Processing Instructions
7571 //===----------------------------------------------------------------------===//
7573 // Packed Compare Implicit Length Strings, Return Mask
7574 multiclass pseudo_pcmpistrm<string asm> {
7575 def REG : PseudoI<(outs VR128:$dst),
7576 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7577 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7579 def MEM : PseudoI<(outs VR128:$dst),
7580 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7581 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7582 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7585 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7586 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7587 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7590 multiclass pcmpistrm_SS42AI<string asm> {
7591 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7592 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7593 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7594 []>, Sched<[WritePCmpIStrM]>;
7596 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7597 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7598 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7599 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7602 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7603 let Predicates = [HasAVX] in
7604 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7605 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7608 // Packed Compare Explicit Length Strings, Return Mask
7609 multiclass pseudo_pcmpestrm<string asm> {
7610 def REG : PseudoI<(outs VR128:$dst),
7611 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7612 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7613 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7614 def MEM : PseudoI<(outs VR128:$dst),
7615 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7616 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7617 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7620 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7621 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7622 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7625 multiclass SS42AI_pcmpestrm<string asm> {
7626 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7627 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7628 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7629 []>, Sched<[WritePCmpEStrM]>;
7631 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7632 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7633 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7634 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7637 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7638 let Predicates = [HasAVX] in
7639 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7640 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7643 // Packed Compare Implicit Length Strings, Return Index
7644 multiclass pseudo_pcmpistri<string asm> {
7645 def REG : PseudoI<(outs GR32:$dst),
7646 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7647 [(set GR32:$dst, EFLAGS,
7648 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7649 def MEM : PseudoI<(outs GR32:$dst),
7650 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7651 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7652 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7655 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7656 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7657 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7660 multiclass SS42AI_pcmpistri<string asm> {
7661 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7662 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7663 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7664 []>, Sched<[WritePCmpIStrI]>;
7666 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7667 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7668 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7669 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7672 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7673 let Predicates = [HasAVX] in
7674 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7675 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7678 // Packed Compare Explicit Length Strings, Return Index
7679 multiclass pseudo_pcmpestri<string asm> {
7680 def REG : PseudoI<(outs GR32:$dst),
7681 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7682 [(set GR32:$dst, EFLAGS,
7683 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7684 def MEM : PseudoI<(outs GR32:$dst),
7685 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7686 [(set GR32:$dst, EFLAGS,
7687 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7691 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7692 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7693 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7696 multiclass SS42AI_pcmpestri<string asm> {
7697 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7698 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7699 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7700 []>, Sched<[WritePCmpEStrI]>;
7702 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7703 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7704 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7705 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7708 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7709 let Predicates = [HasAVX] in
7710 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7711 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7714 //===----------------------------------------------------------------------===//
7715 // SSE4.2 - CRC Instructions
7716 //===----------------------------------------------------------------------===//
7718 // No CRC instructions have AVX equivalents
7720 // crc intrinsic instruction
7721 // This set of instructions are only rm, the only difference is the size
7723 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7724 RegisterClass RCIn, SDPatternOperator Int> :
7725 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7726 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7727 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7730 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7731 X86MemOperand x86memop, SDPatternOperator Int> :
7732 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7733 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7734 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7735 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7737 let Constraints = "$src1 = $dst" in {
7738 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7739 int_x86_sse42_crc32_32_8>;
7740 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7741 int_x86_sse42_crc32_32_8>;
7742 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7743 int_x86_sse42_crc32_32_16>, OpSize16;
7744 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7745 int_x86_sse42_crc32_32_16>, OpSize16;
7746 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7747 int_x86_sse42_crc32_32_32>, OpSize32;
7748 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7749 int_x86_sse42_crc32_32_32>, OpSize32;
7750 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7751 int_x86_sse42_crc32_64_64>, REX_W;
7752 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7753 int_x86_sse42_crc32_64_64>, REX_W;
7754 let hasSideEffects = 0 in {
7756 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7758 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7763 //===----------------------------------------------------------------------===//
7764 // SHA-NI Instructions
7765 //===----------------------------------------------------------------------===//
7767 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7769 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7770 (ins VR128:$src1, VR128:$src2),
7771 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7773 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7774 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7776 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7777 (ins VR128:$src1, i128mem:$src2),
7778 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7780 (set VR128:$dst, (IntId VR128:$src1,
7781 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7782 (set VR128:$dst, (IntId VR128:$src1,
7783 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7786 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7787 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7788 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7789 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7791 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7792 (i8 imm:$src3)))]>, TA;
7793 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7794 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7795 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7797 (int_x86_sha1rnds4 VR128:$src1,
7798 (bc_v4i32 (memopv2i64 addr:$src2)),
7799 (i8 imm:$src3)))]>, TA;
7801 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7802 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7803 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7806 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7808 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7809 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7812 // Aliases with explicit %xmm0
7813 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7814 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7815 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7816 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7818 //===----------------------------------------------------------------------===//
7819 // AES-NI Instructions
7820 //===----------------------------------------------------------------------===//
7822 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7823 Intrinsic IntId128, bit Is2Addr = 1> {
7824 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7825 (ins VR128:$src1, VR128:$src2),
7827 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7828 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7829 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7830 Sched<[WriteAESDecEnc]>;
7831 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7832 (ins VR128:$src1, i128mem:$src2),
7834 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7835 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7837 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
7838 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7841 // Perform One Round of an AES Encryption/Decryption Flow
7842 let Predicates = [HasAVX, HasAES] in {
7843 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7844 int_x86_aesni_aesenc, 0>, VEX_4V;
7845 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7846 int_x86_aesni_aesenclast, 0>, VEX_4V;
7847 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7848 int_x86_aesni_aesdec, 0>, VEX_4V;
7849 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7850 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7853 let Constraints = "$src1 = $dst" in {
7854 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7855 int_x86_aesni_aesenc>;
7856 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7857 int_x86_aesni_aesenclast>;
7858 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7859 int_x86_aesni_aesdec>;
7860 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7861 int_x86_aesni_aesdeclast>;
7864 // Perform the AES InvMixColumn Transformation
7865 let Predicates = [HasAVX, HasAES] in {
7866 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7868 "vaesimc\t{$src1, $dst|$dst, $src1}",
7870 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7872 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7873 (ins i128mem:$src1),
7874 "vaesimc\t{$src1, $dst|$dst, $src1}",
7875 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7876 Sched<[WriteAESIMCLd]>, VEX;
7878 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7880 "aesimc\t{$src1, $dst|$dst, $src1}",
7882 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7883 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7884 (ins i128mem:$src1),
7885 "aesimc\t{$src1, $dst|$dst, $src1}",
7886 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7887 Sched<[WriteAESIMCLd]>;
7889 // AES Round Key Generation Assist
7890 let Predicates = [HasAVX, HasAES] in {
7891 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7892 (ins VR128:$src1, i8imm:$src2),
7893 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7895 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7896 Sched<[WriteAESKeyGen]>, VEX;
7897 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7898 (ins i128mem:$src1, i8imm:$src2),
7899 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7901 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7902 Sched<[WriteAESKeyGenLd]>, VEX;
7904 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7905 (ins VR128:$src1, i8imm:$src2),
7906 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7908 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7909 Sched<[WriteAESKeyGen]>;
7910 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7911 (ins i128mem:$src1, i8imm:$src2),
7912 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7914 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7915 Sched<[WriteAESKeyGenLd]>;
7917 //===----------------------------------------------------------------------===//
7918 // PCLMUL Instructions
7919 //===----------------------------------------------------------------------===//
7921 // AVX carry-less Multiplication instructions
7922 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7923 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7924 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7926 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7927 Sched<[WriteCLMul]>;
7929 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7930 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7931 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7932 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7933 (loadv2i64 addr:$src2), imm:$src3))]>,
7934 Sched<[WriteCLMulLd, ReadAfterLd]>;
7936 // Carry-less Multiplication instructions
7937 let Constraints = "$src1 = $dst" in {
7938 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7939 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7940 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7942 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7943 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7945 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7946 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7947 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7948 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7949 (memopv2i64 addr:$src2), imm:$src3))],
7950 IIC_SSE_PCLMULQDQ_RM>,
7951 Sched<[WriteCLMulLd, ReadAfterLd]>;
7952 } // Constraints = "$src1 = $dst"
7955 multiclass pclmul_alias<string asm, int immop> {
7956 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7957 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7959 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7960 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7962 def : InstAlias<!strconcat("vpclmul", asm,
7963 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7964 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7967 def : InstAlias<!strconcat("vpclmul", asm,
7968 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7969 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7972 defm : pclmul_alias<"hqhq", 0x11>;
7973 defm : pclmul_alias<"hqlq", 0x01>;
7974 defm : pclmul_alias<"lqhq", 0x10>;
7975 defm : pclmul_alias<"lqlq", 0x00>;
7977 //===----------------------------------------------------------------------===//
7978 // SSE4A Instructions
7979 //===----------------------------------------------------------------------===//
7981 let Predicates = [HasSSE4A] in {
7983 let Constraints = "$src = $dst" in {
7984 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7985 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7986 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7987 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7989 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7990 (ins VR128:$src, VR128:$mask),
7991 "extrq\t{$mask, $src|$src, $mask}",
7992 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7993 VR128:$mask))]>, PD;
7995 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7996 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7997 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7998 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7999 VR128:$src2, imm:$len, imm:$idx))]>, XD;
8000 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8001 (ins VR128:$src, VR128:$mask),
8002 "insertq\t{$mask, $src|$src, $mask}",
8003 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
8004 VR128:$mask))]>, XD;
8007 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
8008 "movntss\t{$src, $dst|$dst, $src}",
8009 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
8011 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
8012 "movntsd\t{$src, $dst|$dst, $src}",
8013 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
8016 //===----------------------------------------------------------------------===//
8018 //===----------------------------------------------------------------------===//
8020 //===----------------------------------------------------------------------===//
8021 // VBROADCAST - Load from memory and broadcast to all elements of the
8022 // destination operand
8024 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
8025 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
8026 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8027 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8028 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
8030 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
8031 X86MemOperand x86memop, ValueType VT,
8032 PatFrag ld_frag, SchedWrite Sched> :
8033 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8034 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8035 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
8036 Sched<[Sched]>, VEX {
8040 // AVX2 adds register forms
8041 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
8042 Intrinsic Int, SchedWrite Sched> :
8043 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8044 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8045 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
8047 let ExeDomain = SSEPackedSingle in {
8048 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
8049 f32mem, v4f32, loadf32, WriteLoad>;
8050 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
8051 f32mem, v8f32, loadf32,
8052 WriteFShuffleLd>, VEX_L;
8054 let ExeDomain = SSEPackedDouble in
8055 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
8056 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
8057 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
8058 int_x86_avx_vbroadcastf128_pd_256,
8059 WriteFShuffleLd>, VEX_L;
8061 let ExeDomain = SSEPackedSingle in {
8062 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
8063 int_x86_avx2_vbroadcast_ss_ps,
8065 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
8066 int_x86_avx2_vbroadcast_ss_ps_256,
8067 WriteFShuffle256>, VEX_L;
8069 let ExeDomain = SSEPackedDouble in
8070 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
8071 int_x86_avx2_vbroadcast_sd_pd_256,
8072 WriteFShuffle256>, VEX_L;
8074 let Predicates = [HasAVX2] in
8075 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
8076 int_x86_avx2_vbroadcasti128, WriteLoad>,
8079 let Predicates = [HasAVX] in
8080 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
8081 (VBROADCASTF128 addr:$src)>;
8084 //===----------------------------------------------------------------------===//
8085 // VINSERTF128 - Insert packed floating-point values
8087 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8088 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8089 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8090 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8091 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
8093 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
8094 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
8095 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8096 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
8099 let Predicates = [HasAVX] in {
8100 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
8102 (VINSERTF128rr VR256:$src1, VR128:$src2,
8103 (INSERT_get_vinsert128_imm VR256:$ins))>;
8104 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
8106 (VINSERTF128rr VR256:$src1, VR128:$src2,
8107 (INSERT_get_vinsert128_imm VR256:$ins))>;
8109 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
8111 (VINSERTF128rm VR256:$src1, addr:$src2,
8112 (INSERT_get_vinsert128_imm VR256:$ins))>;
8113 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
8115 (VINSERTF128rm VR256:$src1, addr:$src2,
8116 (INSERT_get_vinsert128_imm VR256:$ins))>;
8119 // Combine two consecutive 16-byte loads with a common destination register into
8120 // one 32-byte load to that register.
8121 let Predicates = [HasAVX, HasFastMem32] in {
8122 def : Pat<(insert_subvector
8123 (v8f32 (insert_subvector undef, (loadv4f32 addr:$src), (iPTR 0))),
8124 (loadv4f32 (add addr:$src, (iPTR 16))),
8126 (VMOVUPSYrm addr:$src)>;
8128 def : Pat<(insert_subvector
8129 (v4f64 (insert_subvector undef, (loadv2f64 addr:$src), (iPTR 0))),
8130 (loadv2f64 (add addr:$src, (iPTR 16))),
8132 (VMOVUPDYrm addr:$src)>;
8134 def : Pat<(insert_subvector
8135 (v32i8 (insert_subvector
8136 undef, (bc_v16i8 (loadv2i64 addr:$src)), (iPTR 0))),
8137 (bc_v16i8 (loadv2i64 (add addr:$src, (iPTR 16)))),
8139 (VMOVDQUYrm addr:$src)>;
8141 def : Pat<(insert_subvector
8142 (v16i16 (insert_subvector
8143 undef, (bc_v8i16 (loadv2i64 addr:$src)), (iPTR 0))),
8144 (bc_v8i16 (loadv2i64 (add addr:$src, (iPTR 16)))),
8146 (VMOVDQUYrm addr:$src)>;
8148 def : Pat<(insert_subvector
8149 (v8i32 (insert_subvector
8150 undef, (bc_v4i32 (loadv2i64 addr:$src)), (iPTR 0))),
8151 (bc_v4i32 (loadv2i64 (add addr:$src, (iPTR 16)))),
8153 (VMOVDQUYrm addr:$src)>;
8155 def : Pat<(insert_subvector
8156 (v4i64 (insert_subvector undef, (loadv2i64 addr:$src), (iPTR 0))),
8157 (loadv2i64 (add addr:$src, (iPTR 16))),
8159 (VMOVDQUYrm addr:$src)>;
8162 let Predicates = [HasAVX1Only] in {
8163 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8165 (VINSERTF128rr VR256:$src1, VR128:$src2,
8166 (INSERT_get_vinsert128_imm VR256:$ins))>;
8167 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8169 (VINSERTF128rr VR256:$src1, VR128:$src2,
8170 (INSERT_get_vinsert128_imm VR256:$ins))>;
8171 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8173 (VINSERTF128rr VR256:$src1, VR128:$src2,
8174 (INSERT_get_vinsert128_imm VR256:$ins))>;
8175 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8177 (VINSERTF128rr VR256:$src1, VR128:$src2,
8178 (INSERT_get_vinsert128_imm VR256:$ins))>;
8180 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8182 (VINSERTF128rm VR256:$src1, addr:$src2,
8183 (INSERT_get_vinsert128_imm VR256:$ins))>;
8184 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8185 (bc_v4i32 (loadv2i64 addr:$src2)),
8187 (VINSERTF128rm VR256:$src1, addr:$src2,
8188 (INSERT_get_vinsert128_imm VR256:$ins))>;
8189 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8190 (bc_v16i8 (loadv2i64 addr:$src2)),
8192 (VINSERTF128rm VR256:$src1, addr:$src2,
8193 (INSERT_get_vinsert128_imm VR256:$ins))>;
8194 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8195 (bc_v8i16 (loadv2i64 addr:$src2)),
8197 (VINSERTF128rm VR256:$src1, addr:$src2,
8198 (INSERT_get_vinsert128_imm VR256:$ins))>;
8201 //===----------------------------------------------------------------------===//
8202 // VEXTRACTF128 - Extract packed floating-point values
8204 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8205 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
8206 (ins VR256:$src1, i8imm:$src2),
8207 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8208 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
8210 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
8211 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
8212 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8213 []>, Sched<[WriteStore]>, VEX, VEX_L;
8217 let Predicates = [HasAVX] in {
8218 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8219 (v4f32 (VEXTRACTF128rr
8220 (v8f32 VR256:$src1),
8221 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8222 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8223 (v2f64 (VEXTRACTF128rr
8224 (v4f64 VR256:$src1),
8225 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8227 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
8228 (iPTR imm))), addr:$dst),
8229 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8230 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8231 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
8232 (iPTR imm))), addr:$dst),
8233 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8234 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8237 let Predicates = [HasAVX1Only] in {
8238 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8239 (v2i64 (VEXTRACTF128rr
8240 (v4i64 VR256:$src1),
8241 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8242 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8243 (v4i32 (VEXTRACTF128rr
8244 (v8i32 VR256:$src1),
8245 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8246 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8247 (v8i16 (VEXTRACTF128rr
8248 (v16i16 VR256:$src1),
8249 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8250 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8251 (v16i8 (VEXTRACTF128rr
8252 (v32i8 VR256:$src1),
8253 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8255 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8256 (iPTR imm))), addr:$dst),
8257 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8258 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8259 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8260 (iPTR imm))), addr:$dst),
8261 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8262 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8263 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8264 (iPTR imm))), addr:$dst),
8265 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8266 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8267 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8268 (iPTR imm))), addr:$dst),
8269 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8270 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8273 //===----------------------------------------------------------------------===//
8274 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8276 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8277 Intrinsic IntLd, Intrinsic IntLd256,
8278 Intrinsic IntSt, Intrinsic IntSt256> {
8279 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8280 (ins VR128:$src1, f128mem:$src2),
8281 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8282 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8284 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8285 (ins VR256:$src1, f256mem:$src2),
8286 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8287 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8289 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8290 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8291 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8292 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8293 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8294 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8296 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8299 let ExeDomain = SSEPackedSingle in
8300 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8301 int_x86_avx_maskload_ps,
8302 int_x86_avx_maskload_ps_256,
8303 int_x86_avx_maskstore_ps,
8304 int_x86_avx_maskstore_ps_256>;
8305 let ExeDomain = SSEPackedDouble in
8306 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8307 int_x86_avx_maskload_pd,
8308 int_x86_avx_maskload_pd_256,
8309 int_x86_avx_maskstore_pd,
8310 int_x86_avx_maskstore_pd_256>;
8312 //===----------------------------------------------------------------------===//
8313 // VPERMIL - Permute Single and Double Floating-Point Values
8315 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8316 RegisterClass RC, X86MemOperand x86memop_f,
8317 X86MemOperand x86memop_i, PatFrag i_frag,
8318 Intrinsic IntVar, ValueType vt> {
8319 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8320 (ins RC:$src1, RC:$src2),
8321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8322 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8323 Sched<[WriteFShuffle]>;
8324 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8325 (ins RC:$src1, x86memop_i:$src2),
8326 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8327 [(set RC:$dst, (IntVar RC:$src1,
8328 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8329 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8331 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8332 (ins RC:$src1, i8imm:$src2),
8333 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8334 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8335 Sched<[WriteFShuffle]>;
8336 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8337 (ins x86memop_f:$src1, i8imm:$src2),
8338 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8340 (vt (X86VPermilpi (memop addr:$src1), (i8 imm:$src2))))]>, VEX,
8341 Sched<[WriteFShuffleLd]>;
8344 let ExeDomain = SSEPackedSingle in {
8345 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8346 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8347 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8348 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8350 let ExeDomain = SSEPackedDouble in {
8351 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8352 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8353 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8354 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8357 let Predicates = [HasAVX] in {
8358 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8359 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8360 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8361 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8362 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8363 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8364 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8365 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8367 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8368 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8369 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8370 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8371 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8373 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8374 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8375 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8377 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8378 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8379 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8380 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8381 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8382 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8383 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8384 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8386 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8387 (VPERMILPDri VR128:$src1, imm:$imm)>;
8388 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8389 (VPERMILPDmi addr:$src1, imm:$imm)>;
8392 //===----------------------------------------------------------------------===//
8393 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8395 let ExeDomain = SSEPackedSingle in {
8396 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8397 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8398 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8399 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8400 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8401 Sched<[WriteFShuffle]>;
8402 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8403 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8404 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8405 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8406 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8407 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8410 let Predicates = [HasAVX] in {
8411 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8412 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8413 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8414 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8415 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8418 let Predicates = [HasAVX1Only] in {
8419 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8420 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8421 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8422 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8423 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8424 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8425 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8426 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8428 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8429 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8430 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8431 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8432 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8433 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8434 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8435 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8436 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8437 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8438 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8439 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8442 //===----------------------------------------------------------------------===//
8443 // VZERO - Zero YMM registers
8445 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8446 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8447 // Zero All YMM registers
8448 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8449 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8451 // Zero Upper bits of YMM registers
8452 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8453 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8456 //===----------------------------------------------------------------------===//
8457 // Half precision conversion instructions
8458 //===----------------------------------------------------------------------===//
8459 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8460 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8461 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8462 [(set RC:$dst, (Int VR128:$src))]>,
8463 T8PD, VEX, Sched<[WriteCvtF2F]>;
8464 let hasSideEffects = 0, mayLoad = 1 in
8465 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8466 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8467 Sched<[WriteCvtF2FLd]>;
8470 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8471 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8472 (ins RC:$src1, i32i8imm:$src2),
8473 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8474 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8475 TAPD, VEX, Sched<[WriteCvtF2F]>;
8476 let hasSideEffects = 0, mayStore = 1,
8477 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8478 def mr : Ii8<0x1D, MRMDestMem, (outs),
8479 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8480 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8484 let Predicates = [HasF16C] in {
8485 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8486 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8487 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8488 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8490 // Pattern match vcvtph2ps of a scalar i64 load.
8491 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8492 (VCVTPH2PSrm addr:$src)>;
8493 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8494 (VCVTPH2PSrm addr:$src)>;
8497 // Patterns for matching conversions from float to half-float and vice versa.
8498 let Predicates = [HasF16C] in {
8499 def : Pat<(fp_to_f16 FR32:$src),
8500 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8501 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8503 def : Pat<(f16_to_fp GR16:$src),
8504 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8505 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8507 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8508 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8509 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8512 //===----------------------------------------------------------------------===//
8513 // AVX2 Instructions
8514 //===----------------------------------------------------------------------===//
8516 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8517 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8518 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8519 X86MemOperand x86memop> {
8520 let isCommutable = 1 in
8521 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8522 (ins RC:$src1, RC:$src2, i8imm:$src3),
8523 !strconcat(OpcodeStr,
8524 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8525 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8526 Sched<[WriteBlend]>, VEX_4V;
8527 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8528 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
8529 !strconcat(OpcodeStr,
8530 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8533 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8534 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8537 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8538 VR128, loadv2i64, i128mem>;
8539 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8540 VR256, loadv4i64, i256mem>, VEX_L;
8542 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8544 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8545 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8547 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8549 //===----------------------------------------------------------------------===//
8550 // VPBROADCAST - Load from memory and broadcast to all elements of the
8551 // destination operand
8553 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8554 X86MemOperand x86memop, PatFrag ld_frag,
8555 Intrinsic Int128, Intrinsic Int256> {
8556 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8557 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8558 [(set VR128:$dst, (Int128 VR128:$src))]>,
8559 Sched<[WriteShuffle]>, VEX;
8560 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8561 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8563 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8564 Sched<[WriteLoad]>, VEX;
8565 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8566 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8567 [(set VR256:$dst, (Int256 VR128:$src))]>,
8568 Sched<[WriteShuffle256]>, VEX, VEX_L;
8569 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8570 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8572 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8573 Sched<[WriteLoad]>, VEX, VEX_L;
8576 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8577 int_x86_avx2_pbroadcastb_128,
8578 int_x86_avx2_pbroadcastb_256>;
8579 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8580 int_x86_avx2_pbroadcastw_128,
8581 int_x86_avx2_pbroadcastw_256>;
8582 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8583 int_x86_avx2_pbroadcastd_128,
8584 int_x86_avx2_pbroadcastd_256>;
8585 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8586 int_x86_avx2_pbroadcastq_128,
8587 int_x86_avx2_pbroadcastq_256>;
8589 let Predicates = [HasAVX2] in {
8590 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8591 (VPBROADCASTBrm addr:$src)>;
8592 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8593 (VPBROADCASTBYrm addr:$src)>;
8594 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8595 (VPBROADCASTWrm addr:$src)>;
8596 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8597 (VPBROADCASTWYrm addr:$src)>;
8598 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8599 (VPBROADCASTDrm addr:$src)>;
8600 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8601 (VPBROADCASTDYrm addr:$src)>;
8602 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8603 (VPBROADCASTQrm addr:$src)>;
8604 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8605 (VPBROADCASTQYrm addr:$src)>;
8607 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8608 (VPBROADCASTBrr VR128:$src)>;
8609 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8610 (VPBROADCASTBYrr VR128:$src)>;
8611 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8612 (VPBROADCASTWrr VR128:$src)>;
8613 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8614 (VPBROADCASTWYrr VR128:$src)>;
8615 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8616 (VPBROADCASTDrr VR128:$src)>;
8617 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8618 (VPBROADCASTDYrr VR128:$src)>;
8619 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8620 (VPBROADCASTQrr VR128:$src)>;
8621 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8622 (VPBROADCASTQYrr VR128:$src)>;
8623 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8624 (VBROADCASTSSrr VR128:$src)>;
8625 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8626 (VBROADCASTSSYrr VR128:$src)>;
8627 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8628 (VPBROADCASTQrr VR128:$src)>;
8629 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8630 (VBROADCASTSDYrr VR128:$src)>;
8632 // Provide aliases for broadcast from the same regitser class that
8633 // automatically does the extract.
8634 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8635 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8637 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8638 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8640 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8641 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8643 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8644 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8646 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8647 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8649 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8650 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8653 // Provide fallback in case the load node that is used in the patterns above
8654 // is used by additional users, which prevents the pattern selection.
8655 let AddedComplexity = 20 in {
8656 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8657 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8658 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8659 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8660 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8661 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8663 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8664 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8665 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8666 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8667 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8668 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8670 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8671 (VPBROADCASTBrr (COPY_TO_REGCLASS
8672 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8674 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8675 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8676 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8679 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8680 (VPBROADCASTWrr (COPY_TO_REGCLASS
8681 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8683 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8684 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8685 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8688 // The patterns for VPBROADCASTD are not needed because they would match
8689 // the exact same thing as VBROADCASTSS patterns.
8691 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8692 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8693 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8697 // AVX1 broadcast patterns
8698 let Predicates = [HasAVX1Only] in {
8699 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8700 (VBROADCASTSSYrm addr:$src)>;
8701 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8702 (VBROADCASTSDYrm addr:$src)>;
8703 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8704 (VBROADCASTSSrm addr:$src)>;
8707 let Predicates = [HasAVX] in {
8708 // Provide fallback in case the load node that is used in the patterns above
8709 // is used by additional users, which prevents the pattern selection.
8710 let AddedComplexity = 20 in {
8711 // 128bit broadcasts:
8712 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8713 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8714 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8715 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8716 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8717 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8718 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8719 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8720 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8721 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8723 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8724 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8725 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8726 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8727 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8728 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8729 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8730 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8731 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8732 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8735 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8736 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8739 //===----------------------------------------------------------------------===//
8740 // VPERM - Permute instructions
8743 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8744 ValueType OpVT, X86FoldableSchedWrite Sched> {
8745 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8746 (ins VR256:$src1, VR256:$src2),
8747 !strconcat(OpcodeStr,
8748 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8750 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8751 Sched<[Sched]>, VEX_4V, VEX_L;
8752 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8753 (ins VR256:$src1, i256mem:$src2),
8754 !strconcat(OpcodeStr,
8755 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8757 (OpVT (X86VPermv VR256:$src1,
8758 (bitconvert (mem_frag addr:$src2)))))]>,
8759 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8762 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8763 let ExeDomain = SSEPackedSingle in
8764 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8766 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8767 ValueType OpVT, X86FoldableSchedWrite Sched> {
8768 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8769 (ins VR256:$src1, i8imm:$src2),
8770 !strconcat(OpcodeStr,
8771 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8773 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8774 Sched<[Sched]>, VEX, VEX_L;
8775 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8776 (ins i256mem:$src1, i8imm:$src2),
8777 !strconcat(OpcodeStr,
8778 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8780 (OpVT (X86VPermi (mem_frag addr:$src1),
8781 (i8 imm:$src2))))]>,
8782 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8785 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8786 WriteShuffle256>, VEX_W;
8787 let ExeDomain = SSEPackedDouble in
8788 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8789 WriteFShuffle256>, VEX_W;
8791 //===----------------------------------------------------------------------===//
8792 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8794 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8795 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8796 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8797 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8798 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8800 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8801 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8802 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8803 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8805 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8807 let Predicates = [HasAVX2] in {
8808 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8809 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8810 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8811 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8812 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8813 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8815 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8817 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8818 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8819 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8820 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8821 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8823 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8827 //===----------------------------------------------------------------------===//
8828 // VINSERTI128 - Insert packed integer values
8830 let hasSideEffects = 0 in {
8831 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8832 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8833 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8834 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8836 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8837 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8838 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8839 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8842 let Predicates = [HasAVX2] in {
8843 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8845 (VINSERTI128rr VR256:$src1, VR128:$src2,
8846 (INSERT_get_vinsert128_imm VR256:$ins))>;
8847 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8849 (VINSERTI128rr VR256:$src1, VR128:$src2,
8850 (INSERT_get_vinsert128_imm VR256:$ins))>;
8851 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8853 (VINSERTI128rr VR256:$src1, VR128:$src2,
8854 (INSERT_get_vinsert128_imm VR256:$ins))>;
8855 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8857 (VINSERTI128rr VR256:$src1, VR128:$src2,
8858 (INSERT_get_vinsert128_imm VR256:$ins))>;
8860 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8862 (VINSERTI128rm VR256:$src1, addr:$src2,
8863 (INSERT_get_vinsert128_imm VR256:$ins))>;
8864 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8865 (bc_v4i32 (loadv2i64 addr:$src2)),
8867 (VINSERTI128rm VR256:$src1, addr:$src2,
8868 (INSERT_get_vinsert128_imm VR256:$ins))>;
8869 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8870 (bc_v16i8 (loadv2i64 addr:$src2)),
8872 (VINSERTI128rm VR256:$src1, addr:$src2,
8873 (INSERT_get_vinsert128_imm VR256:$ins))>;
8874 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8875 (bc_v8i16 (loadv2i64 addr:$src2)),
8877 (VINSERTI128rm VR256:$src1, addr:$src2,
8878 (INSERT_get_vinsert128_imm VR256:$ins))>;
8881 //===----------------------------------------------------------------------===//
8882 // VEXTRACTI128 - Extract packed integer values
8884 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8885 (ins VR256:$src1, i8imm:$src2),
8886 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8888 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8889 Sched<[WriteShuffle256]>, VEX, VEX_L;
8890 let hasSideEffects = 0, mayStore = 1 in
8891 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8892 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8893 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8894 Sched<[WriteStore]>, VEX, VEX_L;
8896 let Predicates = [HasAVX2] in {
8897 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8898 (v2i64 (VEXTRACTI128rr
8899 (v4i64 VR256:$src1),
8900 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8901 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8902 (v4i32 (VEXTRACTI128rr
8903 (v8i32 VR256:$src1),
8904 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8905 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8906 (v8i16 (VEXTRACTI128rr
8907 (v16i16 VR256:$src1),
8908 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8909 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8910 (v16i8 (VEXTRACTI128rr
8911 (v32i8 VR256:$src1),
8912 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8914 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8915 (iPTR imm))), addr:$dst),
8916 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8917 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8918 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8919 (iPTR imm))), addr:$dst),
8920 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8921 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8922 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8923 (iPTR imm))), addr:$dst),
8924 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8925 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8926 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8927 (iPTR imm))), addr:$dst),
8928 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8929 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8932 //===----------------------------------------------------------------------===//
8933 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8935 multiclass avx2_pmovmask<string OpcodeStr,
8936 Intrinsic IntLd128, Intrinsic IntLd256,
8937 Intrinsic IntSt128, Intrinsic IntSt256> {
8938 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8939 (ins VR128:$src1, i128mem:$src2),
8940 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8941 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8942 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8943 (ins VR256:$src1, i256mem:$src2),
8944 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8945 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8947 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8948 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8949 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8950 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8951 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8952 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8953 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8954 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8957 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8958 int_x86_avx2_maskload_d,
8959 int_x86_avx2_maskload_d_256,
8960 int_x86_avx2_maskstore_d,
8961 int_x86_avx2_maskstore_d_256>;
8962 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8963 int_x86_avx2_maskload_q,
8964 int_x86_avx2_maskload_q_256,
8965 int_x86_avx2_maskstore_q,
8966 int_x86_avx2_maskstore_q_256>, VEX_W;
8968 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8969 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8971 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8972 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8974 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8975 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8977 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8978 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8980 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8981 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8983 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8984 (bc_v8f32 (v8i32 immAllZerosV)))),
8985 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8987 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8988 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8991 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8992 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8994 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8995 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8997 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8998 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
9001 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
9002 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
9004 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
9005 (bc_v4f32 (v4i32 immAllZerosV)))),
9006 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
9008 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
9009 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
9012 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
9013 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
9015 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
9016 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
9018 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
9019 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
9022 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
9023 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
9025 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
9026 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
9028 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
9029 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
9031 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
9032 (v4f64 immAllZerosV))),
9033 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
9035 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
9036 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
9039 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
9040 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9042 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
9043 (bc_v4i64 (v8i32 immAllZerosV)))),
9044 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9046 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
9047 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
9050 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
9051 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
9053 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
9054 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
9056 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
9057 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
9059 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
9060 (v2f64 immAllZerosV))),
9061 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
9063 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
9064 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
9067 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
9068 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
9070 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
9071 (bc_v2i64 (v4i32 immAllZerosV)))),
9072 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
9074 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
9075 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
9078 //===----------------------------------------------------------------------===//
9079 // Variable Bit Shifts
9081 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
9082 ValueType vt128, ValueType vt256> {
9083 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
9084 (ins VR128:$src1, VR128:$src2),
9085 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9087 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
9088 VEX_4V, Sched<[WriteVarVecShift]>;
9089 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
9090 (ins VR128:$src1, i128mem:$src2),
9091 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9093 (vt128 (OpNode VR128:$src1,
9094 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
9095 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9096 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
9097 (ins VR256:$src1, VR256:$src2),
9098 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9100 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
9101 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
9102 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
9103 (ins VR256:$src1, i256mem:$src2),
9104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9106 (vt256 (OpNode VR256:$src1,
9107 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
9108 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9111 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
9112 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
9113 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
9114 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
9115 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
9117 //===----------------------------------------------------------------------===//
9118 // VGATHER - GATHER Operations
9119 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
9120 X86MemOperand memop128, X86MemOperand memop256> {
9121 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
9122 (ins VR128:$src1, memop128:$src2, VR128:$mask),
9123 !strconcat(OpcodeStr,
9124 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9126 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
9127 (ins RC256:$src1, memop256:$src2, RC256:$mask),
9128 !strconcat(OpcodeStr,
9129 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9130 []>, VEX_4VOp3, VEX_L;
9133 let mayLoad = 1, Constraints
9134 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
9136 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
9137 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
9138 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
9139 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
9141 let ExeDomain = SSEPackedDouble in {
9142 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
9143 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
9146 let ExeDomain = SSEPackedSingle in {
9147 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
9148 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;