1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
246 let isCommutable = 1 in {
247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
252 Sched<[itins.Sched]>;
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
262 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
263 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
264 string asm, string SSEVer, string FPSizeStr,
265 Operand memopr, ComplexPattern mem_cpat,
268 let isCodeGenOnly = 1 in {
269 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
271 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
272 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 [(set RC:$dst, (!cast<Intrinsic>(
274 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
275 RC:$src1, RC:$src2))], itins.rr>,
276 Sched<[itins.Sched]>;
277 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
279 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
280 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
281 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
282 SSEVer, "_", OpcodeStr, FPSizeStr))
283 RC:$src1, mem_cpat:$src2))], itins.rm>,
284 Sched<[itins.Sched.Folded, ReadAfterLd]>;
288 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
290 RegisterClass RC, ValueType vt,
291 X86MemOperand x86memop, PatFrag mem_frag,
292 Domain d, OpndItins itins, bit Is2Addr = 1> {
293 let isCommutable = 1 in
294 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
297 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
299 Sched<[itins.Sched]>;
301 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
307 Sched<[itins.Sched.Folded, ReadAfterLd]>;
310 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
311 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
312 string OpcodeStr, X86MemOperand x86memop,
313 list<dag> pat_rr, list<dag> pat_rm,
315 let isCommutable = 1, hasSideEffects = 0 in
316 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
320 pat_rr, NoItinerary, d>,
321 Sched<[WriteVecLogic]>;
322 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
326 pat_rm, NoItinerary, d>,
327 Sched<[WriteVecLogicLd, ReadAfterLd]>;
330 //===----------------------------------------------------------------------===//
331 // Non-instruction patterns
332 //===----------------------------------------------------------------------===//
334 // A vector extract of the first f32/f64 position is a subregister copy
335 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
337 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
338 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
340 // A 128-bit subvector extract from the first 256-bit vector position
341 // is a subregister copy that needs no instruction.
342 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
343 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
347 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
348 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
353 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
357 // A 128-bit subvector insert to the first 256-bit vector position
358 // is a subregister copy that needs no instruction.
359 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
360 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
374 // Implicitly promote a 32-bit scalar to a vector.
375 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
378 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 // Implicitly promote a 64-bit scalar to a vector.
380 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
382 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
383 (COPY_TO_REGCLASS FR64:$src, VR128)>;
385 // Bitcasts between 128-bit vector types. Return the original type since
386 // no instruction is needed for the conversion
387 let Predicates = [HasSSE2] in {
388 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
397 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
402 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
407 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
417 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr> {
570 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
571 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
574 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
576 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
577 VEX, VEX_LIG, Sched<[WriteStore]>;
579 let Constraints = "$src1 = $dst" in {
580 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
581 "\t{$src2, $dst|$dst, $src2}">;
584 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
586 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
590 // Loading from memory automatically zeroing upper bits.
591 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
592 PatFrag mem_pat, string OpcodeStr> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
604 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
606 let canFoldAsLoad = 1, isReMaterializable = 1 in {
607 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
609 let AddedComplexity = 20 in
610 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
614 let Predicates = [UseAVX] in {
615 let AddedComplexity = 20 in {
616 // MOVSSrm zeros the high parts of the register; represent this
617 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
618 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
619 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
620 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
621 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
622 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
625 // MOVSDrm zeros the high parts of the register; represent this
626 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
627 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
628 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
629 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
630 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
631 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzload addr:$src)),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
638 // Represent the same patterns above but in the form they appear for
640 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
641 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
642 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
643 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
644 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
645 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
646 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
647 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
648 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
650 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
651 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
652 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
654 // Extract and store.
655 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
657 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
658 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
660 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
662 // Shuffle with VMOVSS
663 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
664 (VMOVSSrr (v4i32 VR128:$src1),
665 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
666 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
667 (VMOVSSrr (v4f32 VR128:$src1),
668 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
671 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
672 (SUBREG_TO_REG (i32 0),
673 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
674 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
676 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
677 (SUBREG_TO_REG (i32 0),
678 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
679 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
682 // Shuffle with VMOVSD
683 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
689 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
690 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
693 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
694 (SUBREG_TO_REG (i32 0),
695 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
696 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
698 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
699 (SUBREG_TO_REG (i32 0),
700 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
701 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
704 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
705 // is during lowering, where it's not possible to recognize the fold cause
706 // it has two uses through a bitcast. One use disappears at isel time and the
707 // fold opportunity reappears.
708 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
714 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
715 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
718 let Predicates = [UseSSE1] in {
719 let Predicates = [NoSSE41], AddedComplexity = 15 in {
720 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
721 // MOVSS to the lower bits.
722 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
723 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
724 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
725 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
726 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
727 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
730 let AddedComplexity = 20 in {
731 // MOVSSrm already zeros the high parts of the register.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
743 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
745 // Shuffle with MOVSS
746 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
748 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
749 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
752 let Predicates = [UseSSE2] in {
753 let Predicates = [NoSSE41], AddedComplexity = 15 in {
754 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
755 // MOVSD to the lower bits.
756 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
757 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
760 let AddedComplexity = 20 in {
761 // MOVSDrm already zeros the high parts of the register.
762 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
770 def : Pat<(v2f64 (X86vzload addr:$src)),
771 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
774 // Extract and store.
775 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
777 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
779 // Shuffle with MOVSD
780 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
786 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
787 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
789 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
790 // is during lowering, where it's not possible to recognize the fold cause
791 // it has two uses through a bitcast. One use disappears at isel time and the
792 // fold opportunity reappears.
793 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
799 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
800 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
803 //===----------------------------------------------------------------------===//
804 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
805 //===----------------------------------------------------------------------===//
807 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
808 X86MemOperand x86memop, PatFrag ld_frag,
809 string asm, Domain d,
811 bit IsReMaterializable = 1> {
812 let hasSideEffects = 0 in
813 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
814 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
815 Sched<[WriteFShuffle]>;
816 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
817 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
818 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
819 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
823 let Predicates = [HasAVX, NoVLX] in {
824 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
830 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
837 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
838 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
840 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
841 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
843 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
844 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
846 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
847 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
851 let Predicates = [UseSSE1] in {
852 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
853 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
855 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
856 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
859 let Predicates = [UseSSE2] in {
860 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
861 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
863 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
864 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
868 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
869 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
870 "movaps\t{$src, $dst|$dst, $src}",
871 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
872 IIC_SSE_MOVA_P_MR>, VEX;
873 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
874 "movapd\t{$src, $dst|$dst, $src}",
875 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
876 IIC_SSE_MOVA_P_MR>, VEX;
877 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
878 "movups\t{$src, $dst|$dst, $src}",
879 [(store (v4f32 VR128:$src), addr:$dst)],
880 IIC_SSE_MOVU_P_MR>, VEX;
881 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
882 "movupd\t{$src, $dst|$dst, $src}",
883 [(store (v2f64 VR128:$src), addr:$dst)],
884 IIC_SSE_MOVU_P_MR>, VEX;
885 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
886 "movaps\t{$src, $dst|$dst, $src}",
887 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
888 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
889 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
890 "movapd\t{$src, $dst|$dst, $src}",
891 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
892 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
893 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
894 "movups\t{$src, $dst|$dst, $src}",
895 [(store (v8f32 VR256:$src), addr:$dst)],
896 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
897 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
898 "movupd\t{$src, $dst|$dst, $src}",
899 [(store (v4f64 VR256:$src), addr:$dst)],
900 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
904 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
905 SchedRW = [WriteFShuffle] in {
906 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
908 "movaps\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX;
910 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
912 "movapd\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVA_P_RR>, VEX;
914 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
916 "movups\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX;
918 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
920 "movupd\t{$src, $dst|$dst, $src}", [],
921 IIC_SSE_MOVU_P_RR>, VEX;
922 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
924 "movaps\t{$src, $dst|$dst, $src}", [],
925 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
926 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
928 "movapd\t{$src, $dst|$dst, $src}", [],
929 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
930 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
932 "movups\t{$src, $dst|$dst, $src}", [],
933 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
934 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
936 "movupd\t{$src, $dst|$dst, $src}", [],
937 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
940 let Predicates = [HasAVX] in {
941 def : Pat<(v8i32 (X86vzmovl
942 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
943 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
944 def : Pat<(v4i64 (X86vzmovl
945 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
946 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
947 def : Pat<(v8f32 (X86vzmovl
948 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
949 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
950 def : Pat<(v4f64 (X86vzmovl
951 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
952 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
956 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
957 (VMOVUPSYmr addr:$dst, VR256:$src)>;
958 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
959 (VMOVUPDYmr addr:$dst, VR256:$src)>;
961 let SchedRW = [WriteStore] in {
962 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
963 "movaps\t{$src, $dst|$dst, $src}",
964 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
966 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
967 "movapd\t{$src, $dst|$dst, $src}",
968 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
970 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
971 "movups\t{$src, $dst|$dst, $src}",
972 [(store (v4f32 VR128:$src), addr:$dst)],
974 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
975 "movupd\t{$src, $dst|$dst, $src}",
976 [(store (v2f64 VR128:$src), addr:$dst)],
981 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
982 SchedRW = [WriteFShuffle] in {
983 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
984 "movaps\t{$src, $dst|$dst, $src}", [],
986 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
987 "movapd\t{$src, $dst|$dst, $src}", [],
989 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
990 "movups\t{$src, $dst|$dst, $src}", [],
992 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
993 "movupd\t{$src, $dst|$dst, $src}", [],
997 let Predicates = [HasAVX] in {
998 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
999 (VMOVUPSmr addr:$dst, VR128:$src)>;
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (VMOVUPDmr addr:$dst, VR128:$src)>;
1004 let Predicates = [UseSSE1] in
1005 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1006 (MOVUPSmr addr:$dst, VR128:$src)>;
1007 let Predicates = [UseSSE2] in
1008 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1009 (MOVUPDmr addr:$dst, VR128:$src)>;
1011 // Use vmovaps/vmovups for AVX integer load/store.
1012 let Predicates = [HasAVX, NoVLX] in {
1013 // 128-bit load/store
1014 def : Pat<(alignedloadv2i64 addr:$src),
1015 (VMOVAPSrm addr:$src)>;
1016 def : Pat<(loadv2i64 addr:$src),
1017 (VMOVUPSrm addr:$src)>;
1019 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1026 (VMOVAPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1033 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1034 (VMOVUPSmr addr:$dst, VR128:$src)>;
1036 // 256-bit load/store
1037 def : Pat<(alignedloadv4i64 addr:$src),
1038 (VMOVAPSYrm addr:$src)>;
1039 def : Pat<(loadv4i64 addr:$src),
1040 (VMOVUPSYrm addr:$src)>;
1041 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1048 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1055 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1056 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1058 // Special patterns for storing subvector extracts of lower 128-bits
1059 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1060 def : Pat<(alignedstore (v2f64 (extract_subvector
1061 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1062 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1063 def : Pat<(alignedstore (v4f32 (extract_subvector
1064 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1065 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1066 def : Pat<(alignedstore (v2i64 (extract_subvector
1067 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1068 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1069 def : Pat<(alignedstore (v4i32 (extract_subvector
1070 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1071 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1072 def : Pat<(alignedstore (v8i16 (extract_subvector
1073 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1074 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1075 def : Pat<(alignedstore (v16i8 (extract_subvector
1076 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1077 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1079 def : Pat<(store (v2f64 (extract_subvector
1080 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1081 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1082 def : Pat<(store (v4f32 (extract_subvector
1083 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1084 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1085 def : Pat<(store (v2i64 (extract_subvector
1086 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1087 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1088 def : Pat<(store (v4i32 (extract_subvector
1089 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1090 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1091 def : Pat<(store (v8i16 (extract_subvector
1092 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1093 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1094 def : Pat<(store (v16i8 (extract_subvector
1095 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1096 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1099 // Use movaps / movups for SSE integer load / store (one byte shorter).
1100 // The instructions selected below are then converted to MOVDQA/MOVDQU
1101 // during the SSE domain pass.
1102 let Predicates = [UseSSE1] in {
1103 def : Pat<(alignedloadv2i64 addr:$src),
1104 (MOVAPSrm addr:$src)>;
1105 def : Pat<(loadv2i64 addr:$src),
1106 (MOVUPSrm addr:$src)>;
1108 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1115 (MOVAPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1122 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1123 (MOVUPSmr addr:$dst, VR128:$src)>;
1126 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1127 // bits are disregarded. FIXME: Set encoding to pseudo!
1128 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1129 let isCodeGenOnly = 1 in {
1130 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1131 "movaps\t{$src, $dst|$dst, $src}",
1132 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1133 IIC_SSE_MOVA_P_RM>, VEX;
1134 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1135 "movapd\t{$src, $dst|$dst, $src}",
1136 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1137 IIC_SSE_MOVA_P_RM>, VEX;
1138 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1139 "movaps\t{$src, $dst|$dst, $src}",
1140 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1142 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1143 "movapd\t{$src, $dst|$dst, $src}",
1144 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1149 //===----------------------------------------------------------------------===//
1150 // SSE 1 & 2 - Move Low packed FP Instructions
1151 //===----------------------------------------------------------------------===//
1153 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1154 string base_opc, string asm_opr,
1155 InstrItinClass itin> {
1156 def PSrm : PI<opc, MRMSrcMem,
1157 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1158 !strconcat(base_opc, "s", asm_opr),
1160 (psnode VR128:$src1,
1161 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1162 itin, SSEPackedSingle>, PS,
1163 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1165 def PDrm : PI<opc, MRMSrcMem,
1166 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1167 !strconcat(base_opc, "d", asm_opr),
1168 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1169 (scalar_to_vector (loadf64 addr:$src2)))))],
1170 itin, SSEPackedDouble>, PD,
1171 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1175 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1176 string base_opc, InstrItinClass itin> {
1177 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1178 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1181 let Constraints = "$src1 = $dst" in
1182 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1183 "\t{$src2, $dst|$dst, $src2}",
1187 let AddedComplexity = 20 in {
1188 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1192 let SchedRW = [WriteStore] in {
1193 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1194 "movlps\t{$src, $dst|$dst, $src}",
1195 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1196 (iPTR 0))), addr:$dst)],
1197 IIC_SSE_MOV_LH>, VEX;
1198 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1199 "movlpd\t{$src, $dst|$dst, $src}",
1200 [(store (f64 (vector_extract (v2f64 VR128:$src),
1201 (iPTR 0))), addr:$dst)],
1202 IIC_SSE_MOV_LH>, VEX;
1203 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1204 "movlps\t{$src, $dst|$dst, $src}",
1205 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1206 (iPTR 0))), addr:$dst)],
1208 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1209 "movlpd\t{$src, $dst|$dst, $src}",
1210 [(store (f64 (vector_extract (v2f64 VR128:$src),
1211 (iPTR 0))), addr:$dst)],
1215 let Predicates = [HasAVX] in {
1216 // Shuffle with VMOVLPS
1217 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1219 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1220 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1222 // Shuffle with VMOVLPD
1223 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1226 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1227 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1228 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1229 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1232 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1234 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1235 def : Pat<(store (v4i32 (X86Movlps
1236 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1237 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1238 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1240 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1243 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1246 let Predicates = [UseSSE1] in {
1247 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1248 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1249 (iPTR 0))), addr:$src1),
1250 (MOVLPSmr addr:$src1, VR128:$src2)>;
1252 // Shuffle with MOVLPS
1253 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1256 (MOVLPSrm VR128:$src1, addr:$src2)>;
1257 def : Pat<(X86Movlps VR128:$src1,
1258 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1259 (MOVLPSrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1264 (MOVLPSmr addr:$src1, VR128:$src2)>;
1265 def : Pat<(store (v4i32 (X86Movlps
1266 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1268 (MOVLPSmr addr:$src1, VR128:$src2)>;
1271 let Predicates = [UseSSE2] in {
1272 // Shuffle with MOVLPD
1273 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1276 (MOVLPDrm VR128:$src1, addr:$src2)>;
1277 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1278 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1279 (MOVLPDrm VR128:$src1, addr:$src2)>;
1282 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1284 (MOVLPDmr addr:$src1, VR128:$src2)>;
1285 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1287 (MOVLPDmr addr:$src1, VR128:$src2)>;
1290 //===----------------------------------------------------------------------===//
1291 // SSE 1 & 2 - Move Hi packed FP Instructions
1292 //===----------------------------------------------------------------------===//
1294 let AddedComplexity = 20 in {
1295 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1299 let SchedRW = [WriteStore] in {
1300 // v2f64 extract element 1 is always custom lowered to unpack high to low
1301 // and extract element 0 so the non-store version isn't too horrible.
1302 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1303 "movhps\t{$src, $dst|$dst, $src}",
1304 [(store (f64 (vector_extract
1305 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1306 (bc_v2f64 (v4f32 VR128:$src))),
1307 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1308 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1309 "movhpd\t{$src, $dst|$dst, $src}",
1310 [(store (f64 (vector_extract
1311 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1312 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1313 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1314 "movhps\t{$src, $dst|$dst, $src}",
1315 [(store (f64 (vector_extract
1316 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1317 (bc_v2f64 (v4f32 VR128:$src))),
1318 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1319 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1320 "movhpd\t{$src, $dst|$dst, $src}",
1321 [(store (f64 (vector_extract
1322 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1323 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1326 let Predicates = [HasAVX] in {
1328 def : Pat<(X86Movlhps VR128:$src1,
1329 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1330 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1331 def : Pat<(X86Movlhps VR128:$src1,
1332 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1333 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1337 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1338 // is during lowering, where it's not possible to recognize the load fold
1339 // cause it has two uses through a bitcast. One use disappears at isel time
1340 // and the fold opportunity reappears.
1341 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1342 (scalar_to_vector (loadf64 addr:$src2)))),
1343 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1344 // Also handle an i64 load because that may get selected as a faster way to
1346 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1347 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1348 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1350 def : Pat<(store (f64 (vector_extract
1351 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1352 (iPTR 0))), addr:$dst),
1353 (VMOVHPDmr addr:$dst, VR128:$src)>;
1356 let Predicates = [UseSSE1] in {
1358 def : Pat<(X86Movlhps VR128:$src1,
1359 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1360 (MOVHPSrm VR128:$src1, addr:$src2)>;
1361 def : Pat<(X86Movlhps VR128:$src1,
1362 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1363 (MOVHPSrm VR128:$src1, addr:$src2)>;
1366 let Predicates = [UseSSE2] in {
1369 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1370 // is during lowering, where it's not possible to recognize the load fold
1371 // cause it has two uses through a bitcast. One use disappears at isel time
1372 // and the fold opportunity reappears.
1373 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1374 (scalar_to_vector (loadf64 addr:$src2)))),
1375 (MOVHPDrm VR128:$src1, addr:$src2)>;
1376 // Also handle an i64 load because that may get selected as a faster way to
1378 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1379 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1380 (MOVHPDrm VR128:$src1, addr:$src2)>;
1382 def : Pat<(store (f64 (vector_extract
1383 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1384 (iPTR 0))), addr:$dst),
1385 (MOVHPDmr addr:$dst, VR128:$src)>;
1388 //===----------------------------------------------------------------------===//
1389 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1390 //===----------------------------------------------------------------------===//
1392 let AddedComplexity = 20, Predicates = [UseAVX] in {
1393 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1394 (ins VR128:$src1, VR128:$src2),
1395 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1397 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1399 VEX_4V, Sched<[WriteFShuffle]>;
1400 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1401 (ins VR128:$src1, VR128:$src2),
1402 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1404 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1406 VEX_4V, Sched<[WriteFShuffle]>;
1408 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1409 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1410 (ins VR128:$src1, VR128:$src2),
1411 "movlhps\t{$src2, $dst|$dst, $src2}",
1413 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1414 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1415 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1416 (ins VR128:$src1, VR128:$src2),
1417 "movhlps\t{$src2, $dst|$dst, $src2}",
1419 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1420 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1423 let Predicates = [UseAVX] in {
1425 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1427 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1428 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1431 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1432 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1435 let Predicates = [UseSSE1] in {
1437 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1439 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1440 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1443 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1444 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1447 //===----------------------------------------------------------------------===//
1448 // SSE 1 & 2 - Conversion Instructions
1449 //===----------------------------------------------------------------------===//
1451 def SSE_CVT_PD : OpndItins<
1452 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1455 let Sched = WriteCvtI2F in
1456 def SSE_CVT_PS : OpndItins<
1457 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1460 let Sched = WriteCvtI2F in
1461 def SSE_CVT_Scalar : OpndItins<
1462 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1465 let Sched = WriteCvtF2I in
1466 def SSE_CVT_SS2SI_32 : OpndItins<
1467 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1470 let Sched = WriteCvtF2I in
1471 def SSE_CVT_SS2SI_64 : OpndItins<
1472 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1475 let Sched = WriteCvtF2I in
1476 def SSE_CVT_SD2SI : OpndItins<
1477 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1480 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1481 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1482 string asm, OpndItins itins> {
1483 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1484 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1485 itins.rr>, Sched<[itins.Sched]>;
1486 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1487 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1488 itins.rm>, Sched<[itins.Sched.Folded]>;
1491 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1492 X86MemOperand x86memop, string asm, Domain d,
1494 let hasSideEffects = 0 in {
1495 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1496 [], itins.rr, d>, Sched<[itins.Sched]>;
1498 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1499 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1503 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1504 X86MemOperand x86memop, string asm> {
1505 let hasSideEffects = 0, Predicates = [UseAVX] in {
1506 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1507 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1508 Sched<[WriteCvtI2F]>;
1510 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1511 (ins DstRC:$src1, x86memop:$src),
1512 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1513 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1514 } // hasSideEffects = 0
1517 let Predicates = [UseAVX] in {
1518 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1519 "cvttss2si\t{$src, $dst|$dst, $src}",
1522 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1523 "cvttss2si\t{$src, $dst|$dst, $src}",
1525 XS, VEX, VEX_W, VEX_LIG;
1526 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1527 "cvttsd2si\t{$src, $dst|$dst, $src}",
1530 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1531 "cvttsd2si\t{$src, $dst|$dst, $src}",
1533 XD, VEX, VEX_W, VEX_LIG;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1537 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1541 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1545 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1549 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1550 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1552 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1553 // register, but the same isn't true when only using memory operands,
1554 // provide other assembly "l" and "q" forms to address this explicitly
1555 // where appropriate to do so.
1556 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1557 XS, VEX_4V, VEX_LIG;
1558 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1559 XS, VEX_4V, VEX_W, VEX_LIG;
1560 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1561 XD, VEX_4V, VEX_LIG;
1562 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1563 XD, VEX_4V, VEX_W, VEX_LIG;
1565 let Predicates = [UseAVX] in {
1566 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1568 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1569 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1571 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1572 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1574 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1576 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1577 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1578 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR32:$src)),
1581 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1582 def : Pat<(f32 (sint_to_fp GR64:$src)),
1583 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR32:$src)),
1585 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1586 def : Pat<(f64 (sint_to_fp GR64:$src)),
1587 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1590 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1591 "cvttss2si\t{$src, $dst|$dst, $src}",
1592 SSE_CVT_SS2SI_32>, XS;
1593 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1594 "cvttss2si\t{$src, $dst|$dst, $src}",
1595 SSE_CVT_SS2SI_64>, XS, REX_W;
1596 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1597 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1600 "cvttsd2si\t{$src, $dst|$dst, $src}",
1601 SSE_CVT_SD2SI>, XD, REX_W;
1602 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1603 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1604 SSE_CVT_Scalar>, XS;
1605 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1606 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1607 SSE_CVT_Scalar>, XS, REX_W;
1608 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1609 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1610 SSE_CVT_Scalar>, XD;
1611 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1612 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1613 SSE_CVT_Scalar>, XD, REX_W;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1617 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1621 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1622 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1625 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1629 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1630 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1632 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1634 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1635 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1637 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1638 // and/or XMM operand(s).
1640 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1641 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1642 string asm, OpndItins itins> {
1643 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1644 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1645 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1646 Sched<[itins.Sched]>;
1647 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1648 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1649 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1650 Sched<[itins.Sched.Folded]>;
1653 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1654 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1655 PatFrag ld_frag, string asm, OpndItins itins,
1657 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1659 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1660 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1661 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1662 itins.rr>, Sched<[itins.Sched]>;
1663 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1664 (ins DstRC:$src1, x86memop:$src2),
1666 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1667 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1668 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1669 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1672 let Predicates = [UseAVX] in {
1673 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1674 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1675 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1676 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1677 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1678 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1680 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1682 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1683 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1686 let isCodeGenOnly = 1 in {
1687 let Predicates = [UseAVX] in {
1688 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1689 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1690 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1691 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1692 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1693 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1695 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1696 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1697 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1698 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1699 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1700 SSE_CVT_Scalar, 0>, XD,
1703 let Constraints = "$src1 = $dst" in {
1704 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1705 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1706 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1707 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1708 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1709 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1710 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1711 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1712 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1713 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1714 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1715 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1717 } // isCodeGenOnly = 1
1721 // Aliases for intrinsics
1722 let isCodeGenOnly = 1 in {
1723 let Predicates = [UseAVX] in {
1724 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1725 ssmem, sse_load_f32, "cvttss2si",
1726 SSE_CVT_SS2SI_32>, XS, VEX;
1727 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1728 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1729 "cvttss2si", SSE_CVT_SS2SI_64>,
1731 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1732 sdmem, sse_load_f64, "cvttsd2si",
1733 SSE_CVT_SD2SI>, XD, VEX;
1734 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1735 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1736 "cvttsd2si", SSE_CVT_SD2SI>,
1739 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1740 ssmem, sse_load_f32, "cvttss2si",
1741 SSE_CVT_SS2SI_32>, XS;
1742 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1743 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1744 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1745 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1746 sdmem, sse_load_f64, "cvttsd2si",
1748 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1749 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1750 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1751 } // isCodeGenOnly = 1
1753 let Predicates = [UseAVX] in {
1754 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1755 ssmem, sse_load_f32, "cvtss2si",
1756 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1757 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1758 ssmem, sse_load_f32, "cvtss2si",
1759 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1761 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1762 ssmem, sse_load_f32, "cvtss2si",
1763 SSE_CVT_SS2SI_32>, XS;
1764 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1765 ssmem, sse_load_f32, "cvtss2si",
1766 SSE_CVT_SS2SI_64>, XS, REX_W;
1768 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1769 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1770 SSEPackedSingle, SSE_CVT_PS>,
1771 PS, VEX, Requires<[HasAVX]>;
1772 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1773 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1774 SSEPackedSingle, SSE_CVT_PS>,
1775 PS, VEX, VEX_L, Requires<[HasAVX]>;
1777 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1778 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1779 SSEPackedSingle, SSE_CVT_PS>,
1780 PS, Requires<[UseSSE2]>;
1782 let Predicates = [UseAVX] in {
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1785 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1789 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1790 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1793 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1797 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1798 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1803 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1807 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1808 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1811 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1815 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1816 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1820 // Convert scalar double to scalar single
1821 let hasSideEffects = 0, Predicates = [UseAVX] in {
1822 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1823 (ins FR64:$src1, FR64:$src2),
1824 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1825 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1826 Sched<[WriteCvtF2F]>;
1828 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1829 (ins FR64:$src1, f64mem:$src2),
1830 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1831 [], IIC_SSE_CVT_Scalar_RM>,
1832 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1833 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1836 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1839 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1840 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1841 [(set FR32:$dst, (fround FR64:$src))],
1842 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1843 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1844 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1845 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1846 IIC_SSE_CVT_Scalar_RM>,
1848 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1850 let isCodeGenOnly = 1 in {
1851 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1852 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1853 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1855 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1856 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1857 Sched<[WriteCvtF2F]>;
1858 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1859 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1860 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1861 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1862 VR128:$src1, sse_load_f64:$src2))],
1863 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1864 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1866 let Constraints = "$src1 = $dst" in {
1867 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1868 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1869 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1871 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1872 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1873 Sched<[WriteCvtF2F]>;
1874 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1875 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1876 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1877 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1878 VR128:$src1, sse_load_f64:$src2))],
1879 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1880 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1882 } // isCodeGenOnly = 1
1884 // Convert scalar single to scalar double
1885 // SSE2 instructions with XS prefix
1886 let hasSideEffects = 0, Predicates = [UseAVX] in {
1887 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1888 (ins FR32:$src1, FR32:$src2),
1889 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1890 [], IIC_SSE_CVT_Scalar_RR>,
1891 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1892 Sched<[WriteCvtF2F]>;
1894 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1895 (ins FR32:$src1, f32mem:$src2),
1896 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1897 [], IIC_SSE_CVT_Scalar_RM>,
1898 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1899 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1902 def : Pat<(f64 (fextend FR32:$src)),
1903 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1904 def : Pat<(fextend (loadf32 addr:$src)),
1905 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1907 def : Pat<(extloadf32 addr:$src),
1908 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1909 Requires<[UseAVX, OptForSize]>;
1910 def : Pat<(extloadf32 addr:$src),
1911 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1912 Requires<[UseAVX, OptForSpeed]>;
1914 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1915 "cvtss2sd\t{$src, $dst|$dst, $src}",
1916 [(set FR64:$dst, (fextend FR32:$src))],
1917 IIC_SSE_CVT_Scalar_RR>, XS,
1918 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1919 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1920 "cvtss2sd\t{$src, $dst|$dst, $src}",
1921 [(set FR64:$dst, (extloadf32 addr:$src))],
1922 IIC_SSE_CVT_Scalar_RM>, XS,
1923 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1925 // extload f32 -> f64. This matches load+fextend because we have a hack in
1926 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1928 // Since these loads aren't folded into the fextend, we have to match it
1930 def : Pat<(fextend (loadf32 addr:$src)),
1931 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1932 def : Pat<(extloadf32 addr:$src),
1933 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1935 let isCodeGenOnly = 1 in {
1936 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1937 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1938 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1940 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1941 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1942 Sched<[WriteCvtF2F]>;
1943 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1944 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1945 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1947 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1948 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1949 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1950 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1951 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1952 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1953 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1955 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1956 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1957 Sched<[WriteCvtF2F]>;
1958 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1959 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1960 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1962 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1963 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1964 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1966 } // isCodeGenOnly = 1
1968 // Convert packed single/double fp to doubleword
1969 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1970 "cvtps2dq\t{$src, $dst|$dst, $src}",
1971 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1972 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1973 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1974 "cvtps2dq\t{$src, $dst|$dst, $src}",
1976 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1977 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1978 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1979 "cvtps2dq\t{$src, $dst|$dst, $src}",
1981 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1982 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1983 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1984 "cvtps2dq\t{$src, $dst|$dst, $src}",
1986 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1987 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1988 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1989 "cvtps2dq\t{$src, $dst|$dst, $src}",
1990 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1991 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1992 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1993 "cvtps2dq\t{$src, $dst|$dst, $src}",
1995 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1996 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1999 // Convert Packed Double FP to Packed DW Integers
2000 let Predicates = [HasAVX] in {
2001 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2002 // register, but the same isn't true when using memory operands instead.
2003 // Provide other assembly rr and rm forms to address this explicitly.
2004 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2005 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2006 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2007 VEX, Sched<[WriteCvtF2I]>;
2010 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2011 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2012 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2013 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2015 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2016 Sched<[WriteCvtF2ILd]>;
2019 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2020 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2022 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2023 Sched<[WriteCvtF2I]>;
2024 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2025 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2027 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2028 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2029 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2030 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2033 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2034 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2036 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2037 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2038 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2039 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2040 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2041 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2043 // Convert with truncation packed single/double fp to doubleword
2044 // SSE2 packed instructions with XS prefix
2045 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2046 "cvttps2dq\t{$src, $dst|$dst, $src}",
2048 (int_x86_sse2_cvttps2dq VR128:$src))],
2049 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2050 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2051 "cvttps2dq\t{$src, $dst|$dst, $src}",
2052 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2053 (loadv4f32 addr:$src)))],
2054 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2055 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2056 "cvttps2dq\t{$src, $dst|$dst, $src}",
2058 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2059 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2060 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2061 "cvttps2dq\t{$src, $dst|$dst, $src}",
2062 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2063 (loadv8f32 addr:$src)))],
2064 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2065 Sched<[WriteCvtF2ILd]>;
2067 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2068 "cvttps2dq\t{$src, $dst|$dst, $src}",
2069 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2070 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2071 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2072 "cvttps2dq\t{$src, $dst|$dst, $src}",
2074 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2075 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2077 let Predicates = [HasAVX] in {
2078 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2079 (VCVTDQ2PSrr VR128:$src)>;
2080 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2081 (VCVTDQ2PSrm addr:$src)>;
2083 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2084 (VCVTDQ2PSrr VR128:$src)>;
2085 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2086 (VCVTDQ2PSrm addr:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2089 (VCVTTPS2DQrr VR128:$src)>;
2090 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2091 (VCVTTPS2DQrm addr:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2094 (VCVTDQ2PSYrr VR256:$src)>;
2095 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2096 (VCVTDQ2PSYrm addr:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2099 (VCVTTPS2DQYrr VR256:$src)>;
2100 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2101 (VCVTTPS2DQYrm addr:$src)>;
2104 let Predicates = [UseSSE2] in {
2105 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2106 (CVTDQ2PSrr VR128:$src)>;
2107 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2108 (CVTDQ2PSrm addr:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2111 (CVTDQ2PSrr VR128:$src)>;
2112 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2113 (CVTDQ2PSrm addr:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2116 (CVTTPS2DQrr VR128:$src)>;
2117 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2118 (CVTTPS2DQrm addr:$src)>;
2121 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2122 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2124 (int_x86_sse2_cvttpd2dq VR128:$src))],
2125 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2127 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2128 // register, but the same isn't true when using memory operands instead.
2129 // Provide other assembly rr and rm forms to address this explicitly.
2132 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2133 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2134 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2135 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2136 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2137 (loadv2f64 addr:$src)))],
2138 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2141 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2142 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2145 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2146 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2147 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2149 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2150 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2151 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2152 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2154 let Predicates = [HasAVX] in {
2155 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2156 (VCVTTPD2DQYrr VR256:$src)>;
2157 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2158 (VCVTTPD2DQYrm addr:$src)>;
2159 } // Predicates = [HasAVX]
2161 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2162 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2163 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2164 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2165 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2166 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2167 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2168 (memopv2f64 addr:$src)))],
2170 Sched<[WriteCvtF2ILd]>;
2172 // Convert packed single to packed double
2173 let Predicates = [HasAVX] in {
2174 // SSE2 instructions without OpSize prefix
2175 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2179 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2180 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2181 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2182 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2183 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2184 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2186 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2187 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2188 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2189 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2192 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2195 let Predicates = [UseSSE2] in {
2196 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2197 "cvtps2pd\t{$src, $dst|$dst, $src}",
2198 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2199 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2200 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2201 "cvtps2pd\t{$src, $dst|$dst, $src}",
2202 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2203 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2206 // Convert Packed DW Integers to Packed Double FP
2207 let Predicates = [HasAVX] in {
2208 let hasSideEffects = 0, mayLoad = 1 in
2209 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2210 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2211 []>, VEX, Sched<[WriteCvtI2FLd]>;
2212 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2213 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2215 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2216 Sched<[WriteCvtI2F]>;
2217 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2218 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2220 (int_x86_avx_cvtdq2_pd_256
2221 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2222 Sched<[WriteCvtI2FLd]>;
2223 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2224 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2227 Sched<[WriteCvtI2F]>;
2230 let hasSideEffects = 0, mayLoad = 1 in
2231 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2232 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2233 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2234 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2235 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2236 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2237 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2239 // AVX 256-bit register conversion intrinsics
2240 let Predicates = [HasAVX] in {
2241 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2242 (VCVTDQ2PDYrr VR128:$src)>;
2243 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2244 (VCVTDQ2PDYrm addr:$src)>;
2245 } // Predicates = [HasAVX]
2247 // Convert packed double to packed single
2248 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2249 // register, but the same isn't true when using memory operands instead.
2250 // Provide other assembly rr and rm forms to address this explicitly.
2251 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2252 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2253 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2254 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2257 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2258 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2259 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2260 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2262 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2263 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2266 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2267 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2269 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2270 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2271 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2272 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2274 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2275 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2276 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2277 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2279 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2280 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2281 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2282 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2283 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2284 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2286 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2287 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2290 // AVX 256-bit register conversion intrinsics
2291 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2292 // whenever possible to avoid declaring two versions of each one.
2293 let Predicates = [HasAVX] in {
2294 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2295 (VCVTDQ2PSYrr VR256:$src)>;
2296 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2297 (VCVTDQ2PSYrm addr:$src)>;
2299 // Match fround and fextend for 128/256-bit conversions
2300 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2301 (VCVTPD2PSrr VR128:$src)>;
2302 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2303 (VCVTPD2PSXrm addr:$src)>;
2304 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2305 (VCVTPD2PSYrr VR256:$src)>;
2306 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2307 (VCVTPD2PSYrm addr:$src)>;
2309 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2310 (VCVTPS2PDrr VR128:$src)>;
2311 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2312 (VCVTPS2PDYrr VR128:$src)>;
2313 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2314 (VCVTPS2PDYrm addr:$src)>;
2317 let Predicates = [UseSSE2] in {
2318 // Match fround and fextend for 128 conversions
2319 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2320 (CVTPD2PSrr VR128:$src)>;
2321 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2322 (CVTPD2PSrm addr:$src)>;
2324 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2325 (CVTPS2PDrr VR128:$src)>;
2328 //===----------------------------------------------------------------------===//
2329 // SSE 1 & 2 - Compare Instructions
2330 //===----------------------------------------------------------------------===//
2332 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2333 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2334 Operand CC, SDNode OpNode, ValueType VT,
2335 PatFrag ld_frag, string asm, string asm_alt,
2336 OpndItins itins, ImmLeaf immLeaf> {
2337 def rr : SIi8<0xC2, MRMSrcReg,
2338 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2339 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2340 itins.rr>, Sched<[itins.Sched]>;
2341 def rm : SIi8<0xC2, MRMSrcMem,
2342 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2343 [(set RC:$dst, (OpNode (VT RC:$src1),
2344 (ld_frag addr:$src2), immLeaf:$cc))],
2346 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2348 // Accept explicit immediate argument form instead of comparison code.
2349 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2350 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2351 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2352 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2354 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2355 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2356 IIC_SSE_ALU_F32S_RM>,
2357 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2361 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2362 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2363 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2364 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2365 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2366 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2367 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2368 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2369 XD, VEX_4V, VEX_LIG;
2371 let Constraints = "$src1 = $dst" in {
2372 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2373 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2374 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2376 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2377 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2378 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2379 SSE_ALU_F64S, i8immZExt3>, XD;
2382 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2383 Intrinsic Int, string asm, OpndItins itins,
2385 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2386 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2387 [(set VR128:$dst, (Int VR128:$src1,
2388 VR128:$src, immLeaf:$cc))],
2390 Sched<[itins.Sched]>;
2391 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2392 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2393 [(set VR128:$dst, (Int VR128:$src1,
2394 (load addr:$src), immLeaf:$cc))],
2396 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2399 let isCodeGenOnly = 1 in {
2400 // Aliases to match intrinsics which expect XMM operand(s).
2401 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2402 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2403 SSE_ALU_F32S, i8immZExt5>,
2405 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2406 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2407 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2409 let Constraints = "$src1 = $dst" in {
2410 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2411 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2412 SSE_ALU_F32S, i8immZExt3>, XS;
2413 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2414 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2415 SSE_ALU_F64S, i8immZExt3>,
2421 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2422 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2423 ValueType vt, X86MemOperand x86memop,
2424 PatFrag ld_frag, string OpcodeStr> {
2425 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2426 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2427 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2430 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2431 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2432 [(set EFLAGS, (OpNode (vt RC:$src1),
2433 (ld_frag addr:$src2)))],
2435 Sched<[WriteFAddLd, ReadAfterLd]>;
2438 let Defs = [EFLAGS] in {
2439 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2440 "ucomiss">, PS, VEX, VEX_LIG;
2441 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2442 "ucomisd">, PD, VEX, VEX_LIG;
2443 let Pattern = []<dag> in {
2444 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2445 "comiss">, PS, VEX, VEX_LIG;
2446 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2447 "comisd">, PD, VEX, VEX_LIG;
2450 let isCodeGenOnly = 1 in {
2451 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2452 load, "ucomiss">, PS, VEX;
2453 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2454 load, "ucomisd">, PD, VEX;
2456 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2457 load, "comiss">, PS, VEX;
2458 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2459 load, "comisd">, PD, VEX;
2461 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2463 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2466 let Pattern = []<dag> in {
2467 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2469 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2473 let isCodeGenOnly = 1 in {
2474 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2475 load, "ucomiss">, PS;
2476 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2477 load, "ucomisd">, PD;
2479 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2481 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2484 } // Defs = [EFLAGS]
2486 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2487 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2488 Operand CC, Intrinsic Int, string asm,
2489 string asm_alt, Domain d, ImmLeaf immLeaf,
2490 OpndItins itins = SSE_ALU_F32P> {
2491 let isCommutable = 1 in
2492 def rri : PIi8<0xC2, MRMSrcReg,
2493 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2494 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2497 def rmi : PIi8<0xC2, MRMSrcMem,
2498 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2499 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), immLeaf:$cc))],
2501 Sched<[WriteFAddLd, ReadAfterLd]>;
2503 // Accept explicit immediate argument form instead of comparison code.
2504 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2505 def rri_alt : PIi8<0xC2, MRMSrcReg,
2506 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2507 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2509 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2510 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2511 asm_alt, [], itins.rm, d>,
2512 Sched<[WriteFAddLd, ReadAfterLd]>;
2516 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2517 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2518 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2519 SSEPackedSingle, i8immZExt5>, PS, VEX_4V;
2520 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2521 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2522 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2523 SSEPackedDouble, i8immZExt5>, PD, VEX_4V;
2524 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2525 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2526 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2527 SSEPackedSingle, i8immZExt5>, PS, VEX_4V, VEX_L;
2528 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2529 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2530 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2531 SSEPackedDouble, i8immZExt5>, PD, VEX_4V, VEX_L;
2532 let Constraints = "$src1 = $dst" in {
2533 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2534 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2535 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2536 SSEPackedSingle, i8immZExt5, SSE_ALU_F32P>, PS;
2537 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2538 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2539 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2540 SSEPackedDouble, i8immZExt5, SSE_ALU_F64P>, PD;
2543 let Predicates = [HasAVX] in {
2544 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2545 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2546 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2547 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2548 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2549 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2550 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2551 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2553 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2554 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2555 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2556 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2557 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2558 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2559 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2560 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2563 let Predicates = [UseSSE1] in {
2564 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2565 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2566 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2567 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2570 let Predicates = [UseSSE2] in {
2571 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2572 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2573 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2574 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2577 //===----------------------------------------------------------------------===//
2578 // SSE 1 & 2 - Shuffle Instructions
2579 //===----------------------------------------------------------------------===//
2581 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2582 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2583 ValueType vt, string asm, PatFrag mem_frag,
2585 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2586 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2587 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2588 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2589 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2590 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2591 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2592 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2593 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2594 Sched<[WriteFShuffle]>;
2597 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2598 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2599 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2600 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2601 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2602 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2603 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2604 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2605 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2606 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2607 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2608 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2610 let Constraints = "$src1 = $dst" in {
2611 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2612 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2613 memopv4f32, SSEPackedSingle>, PS;
2614 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2615 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2616 memopv2f64, SSEPackedDouble>, PD;
2619 let Predicates = [HasAVX] in {
2620 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2621 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2622 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2623 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2624 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2626 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2627 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2628 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2629 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2630 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2633 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2634 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2635 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2636 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2637 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2639 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2640 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2641 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2642 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2643 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2646 let Predicates = [UseSSE1] in {
2647 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2648 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2649 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2650 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2651 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2654 let Predicates = [UseSSE2] in {
2655 // Generic SHUFPD patterns
2656 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2657 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2658 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2659 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2660 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2663 //===----------------------------------------------------------------------===//
2664 // SSE 1 & 2 - Unpack FP Instructions
2665 //===----------------------------------------------------------------------===//
2667 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2668 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2669 PatFrag mem_frag, RegisterClass RC,
2670 X86MemOperand x86memop, string asm,
2672 def rr : PI<opc, MRMSrcReg,
2673 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2675 (vt (OpNode RC:$src1, RC:$src2)))],
2676 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2677 def rm : PI<opc, MRMSrcMem,
2678 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2680 (vt (OpNode RC:$src1,
2681 (mem_frag addr:$src2))))],
2683 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2686 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2687 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2688 SSEPackedSingle>, PS, VEX_4V;
2689 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2690 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2691 SSEPackedDouble>, PD, VEX_4V;
2692 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2693 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2694 SSEPackedSingle>, PS, VEX_4V;
2695 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2696 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2697 SSEPackedDouble>, PD, VEX_4V;
2699 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2700 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2701 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2702 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2703 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2704 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2705 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2706 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2707 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2708 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2709 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2710 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2712 let Constraints = "$src1 = $dst" in {
2713 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2714 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2715 SSEPackedSingle>, PS;
2716 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2717 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2718 SSEPackedDouble>, PD;
2719 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2720 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2721 SSEPackedSingle>, PS;
2722 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2723 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2724 SSEPackedDouble>, PD;
2725 } // Constraints = "$src1 = $dst"
2727 let Predicates = [HasAVX1Only] in {
2728 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2729 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2730 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2731 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2732 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2733 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2734 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2735 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2737 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2738 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2739 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2740 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2741 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2742 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2743 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2744 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2747 //===----------------------------------------------------------------------===//
2748 // SSE 1 & 2 - Extract Floating-Point Sign mask
2749 //===----------------------------------------------------------------------===//
2751 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2752 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2754 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2755 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2756 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2757 Sched<[WriteVecLogic]>;
2760 let Predicates = [HasAVX] in {
2761 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2762 "movmskps", SSEPackedSingle>, PS, VEX;
2763 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2764 "movmskpd", SSEPackedDouble>, PD, VEX;
2765 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2766 "movmskps", SSEPackedSingle>, PS,
2768 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2769 "movmskpd", SSEPackedDouble>, PD,
2772 def : Pat<(i32 (X86fgetsign FR32:$src)),
2773 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2774 def : Pat<(i64 (X86fgetsign FR32:$src)),
2775 (SUBREG_TO_REG (i64 0),
2776 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2777 def : Pat<(i32 (X86fgetsign FR64:$src)),
2778 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2779 def : Pat<(i64 (X86fgetsign FR64:$src)),
2780 (SUBREG_TO_REG (i64 0),
2781 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2784 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2785 SSEPackedSingle>, PS;
2786 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2787 SSEPackedDouble>, PD;
2789 def : Pat<(i32 (X86fgetsign FR32:$src)),
2790 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2791 Requires<[UseSSE1]>;
2792 def : Pat<(i64 (X86fgetsign FR32:$src)),
2793 (SUBREG_TO_REG (i64 0),
2794 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2795 Requires<[UseSSE1]>;
2796 def : Pat<(i32 (X86fgetsign FR64:$src)),
2797 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2798 Requires<[UseSSE2]>;
2799 def : Pat<(i64 (X86fgetsign FR64:$src)),
2800 (SUBREG_TO_REG (i64 0),
2801 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2802 Requires<[UseSSE2]>;
2804 //===---------------------------------------------------------------------===//
2805 // SSE2 - Packed Integer Logical Instructions
2806 //===---------------------------------------------------------------------===//
2808 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2810 /// PDI_binop_rm - Simple SSE2 binary operator.
2811 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2812 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2813 X86MemOperand x86memop, OpndItins itins,
2814 bit IsCommutable, bit Is2Addr> {
2815 let isCommutable = IsCommutable in
2816 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2817 (ins RC:$src1, RC:$src2),
2819 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2820 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2821 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2822 Sched<[itins.Sched]>;
2823 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2824 (ins RC:$src1, x86memop:$src2),
2826 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2827 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2828 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2829 (bitconvert (memop_frag addr:$src2)))))],
2831 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2833 } // ExeDomain = SSEPackedInt
2835 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2836 ValueType OpVT128, ValueType OpVT256,
2837 OpndItins itins, bit IsCommutable = 0> {
2838 let Predicates = [HasAVX, NoVLX] in
2839 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2840 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2842 let Constraints = "$src1 = $dst" in
2843 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2844 memopv2i64, i128mem, itins, IsCommutable, 1>;
2846 let Predicates = [HasAVX2, NoVLX] in
2847 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2848 OpVT256, VR256, loadv4i64, i256mem, itins,
2849 IsCommutable, 0>, VEX_4V, VEX_L;
2852 // These are ordered here for pattern ordering requirements with the fp versions
2854 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2855 SSE_VEC_BIT_ITINS_P, 1>;
2856 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2857 SSE_VEC_BIT_ITINS_P, 1>;
2858 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2859 SSE_VEC_BIT_ITINS_P, 1>;
2860 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2861 SSE_VEC_BIT_ITINS_P, 0>;
2863 //===----------------------------------------------------------------------===//
2864 // SSE 1 & 2 - Logical Instructions
2865 //===----------------------------------------------------------------------===//
2867 // Multiclass for scalars using the X86 logical operation aliases for FP.
2868 multiclass sse12_fp_packed_scalar_logical_alias<
2869 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2870 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2871 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2874 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2875 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2878 let Constraints = "$src1 = $dst" in {
2879 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2880 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2883 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2884 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2889 let isCodeGenOnly = 1 in {
2890 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2892 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2894 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2897 let isCommutable = 0 in
2898 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2902 // Multiclass for vectors using the X86 logical operation aliases for FP.
2903 multiclass sse12_fp_packed_vector_logical_alias<
2904 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2905 let Predicates = [HasAVX, NoVLX] in {
2906 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2907 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle, itins, 0>,
2910 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2911 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble, itins, 0>,
2915 let Constraints = "$src1 = $dst" in {
2916 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2917 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2920 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2921 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2926 let isCodeGenOnly = 1 in {
2927 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2929 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2931 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2934 let isCommutable = 0 in
2935 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2939 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2941 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2943 let Predicates = [HasAVX, NoVLX] in {
2944 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2945 !strconcat(OpcodeStr, "ps"), f256mem,
2946 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2947 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2948 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2950 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2951 !strconcat(OpcodeStr, "pd"), f256mem,
2952 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2953 (bc_v4i64 (v4f64 VR256:$src2))))],
2954 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2955 (loadv4i64 addr:$src2)))], 0>,
2958 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2959 // are all promoted to v2i64, and the patterns are covered by the int
2960 // version. This is needed in SSE only, because v2i64 isn't supported on
2961 // SSE1, but only on SSE2.
2962 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2963 !strconcat(OpcodeStr, "ps"), f128mem, [],
2964 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2965 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2967 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2968 !strconcat(OpcodeStr, "pd"), f128mem,
2969 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2970 (bc_v2i64 (v2f64 VR128:$src2))))],
2971 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2972 (loadv2i64 addr:$src2)))], 0>,
2976 let Constraints = "$src1 = $dst" in {
2977 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2978 !strconcat(OpcodeStr, "ps"), f128mem,
2979 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2980 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2981 (memopv2i64 addr:$src2)))]>, PS;
2983 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2984 !strconcat(OpcodeStr, "pd"), f128mem,
2985 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2986 (bc_v2i64 (v2f64 VR128:$src2))))],
2987 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2988 (memopv2i64 addr:$src2)))]>, PD;
2992 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2993 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2994 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2995 let isCommutable = 0 in
2996 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2998 // AVX1 requires type coercions in order to fold loads directly into logical
3000 let Predicates = [HasAVX1Only] in {
3001 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3002 (VANDPSYrm VR256:$src1, addr:$src2)>;
3003 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3004 (VORPSYrm VR256:$src1, addr:$src2)>;
3005 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3006 (VXORPSYrm VR256:$src1, addr:$src2)>;
3007 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3008 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3011 //===----------------------------------------------------------------------===//
3012 // SSE 1 & 2 - Arithmetic Instructions
3013 //===----------------------------------------------------------------------===//
3015 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3018 /// In addition, we also have a special variant of the scalar form here to
3019 /// represent the associated intrinsic operation. This form is unlike the
3020 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3021 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3023 /// These three forms can each be reg+reg or reg+mem.
3026 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3028 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3029 SDNode OpNode, SizeItins itins> {
3030 let Predicates = [HasAVX, NoVLX] in {
3031 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3032 VR128, v4f32, f128mem, loadv4f32,
3033 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3034 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3035 VR128, v2f64, f128mem, loadv2f64,
3036 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3038 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3039 OpNode, VR256, v8f32, f256mem, loadv8f32,
3040 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3041 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3042 OpNode, VR256, v4f64, f256mem, loadv4f64,
3043 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3046 let Constraints = "$src1 = $dst" in {
3047 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3048 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3050 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3051 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3056 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3058 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3059 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3060 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3061 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3063 let Constraints = "$src1 = $dst" in {
3064 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3065 OpNode, FR32, f32mem, itins.s>, XS;
3066 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3067 OpNode, FR64, f64mem, itins.d>, XD;
3071 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3073 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3074 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3075 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3076 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3077 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3078 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3080 let Constraints = "$src1 = $dst" in {
3081 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3082 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3084 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3085 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3090 // Binary Arithmetic instructions
3091 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3092 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3093 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3094 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3095 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3096 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3097 let isCommutable = 0 in {
3098 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3099 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3100 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3101 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3102 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3103 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3104 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3105 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3106 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3107 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3108 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3109 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3112 let isCodeGenOnly = 1 in {
3113 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3114 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3115 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3116 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3119 // Patterns used to select SSE scalar fp arithmetic instructions from
3120 // a scalar fp operation followed by a blend.
3122 // These patterns know, for example, how to select an ADDSS from a
3123 // float add plus vector insert.
3125 // The effect is that the backend no longer emits unnecessary vector
3126 // insert instructions immediately after SSE scalar fp instructions
3127 // like addss or mulss.
3129 // For example, given the following code:
3130 // __m128 foo(__m128 A, __m128 B) {
3135 // previously we generated:
3136 // addss %xmm0, %xmm1
3137 // movss %xmm1, %xmm0
3140 // addss %xmm1, %xmm0
3142 let Predicates = [UseSSE1] in {
3143 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3144 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3146 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3147 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3148 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3150 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3151 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3152 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3154 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3155 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3156 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3158 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3161 let Predicates = [UseSSE2] in {
3162 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3163 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3164 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3166 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3167 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3168 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3170 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3171 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3172 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3174 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3175 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3176 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3178 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3181 let Predicates = [UseSSE41] in {
3182 // If the subtarget has SSE4.1 but not AVX, the vector insert instruction is
3183 // lowered into a X86insertps or a X86Blendi rather than a X86Movss. When
3184 // selecting SSE scalar single-precision fp arithmetic instructions, make
3185 // sure that we correctly match them.
3187 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3188 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3189 FR32:$src))), (iPTR 0))),
3190 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3191 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3192 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3193 FR32:$src))), (iPTR 0))),
3194 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3195 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3196 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3197 FR32:$src))), (iPTR 0))),
3198 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3199 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3200 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3201 FR32:$src))), (iPTR 0))),
3202 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3204 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3205 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3206 FR32:$src))), (i8 1))),
3207 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3208 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3209 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3210 FR32:$src))), (i8 1))),
3211 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3212 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3213 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3214 FR32:$src))), (i8 1))),
3215 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3216 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3217 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3218 FR32:$src))), (i8 1))),
3219 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3221 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3222 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3223 FR64:$src))), (i8 1))),
3224 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3225 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3226 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3227 FR64:$src))), (i8 1))),
3228 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3229 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3230 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3231 FR64:$src))), (i8 1))),
3232 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3233 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3234 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3235 FR64:$src))), (i8 1))),
3236 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3238 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3239 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3240 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3241 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3242 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3243 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3244 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3245 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3246 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3247 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3248 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3249 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3250 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3251 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3252 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3253 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3256 let Predicates = [HasAVX] in {
3257 // The following patterns select AVX Scalar single/double precision fp
3258 // arithmetic instructions.
3260 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3261 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3263 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3264 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3265 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3267 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3268 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3269 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3271 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3272 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3273 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3275 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3276 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3277 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3278 FR32:$src))), (iPTR 0))),
3279 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3280 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3281 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3282 FR32:$src))), (iPTR 0))),
3283 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3284 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3285 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3286 FR32:$src))), (iPTR 0))),
3287 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3288 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3289 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3290 FR32:$src))), (iPTR 0))),
3291 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3293 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3294 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3295 FR32:$src))), (i8 1))),
3296 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3297 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3298 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3299 FR32:$src))), (i8 1))),
3300 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3301 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3302 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3303 FR32:$src))), (i8 1))),
3304 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3305 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3306 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3307 FR32:$src))), (i8 1))),
3308 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3310 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3311 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3312 FR64:$src))), (i8 1))),
3313 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3314 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3315 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3316 FR64:$src))), (i8 1))),
3317 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3318 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3319 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3320 FR64:$src))), (i8 1))),
3321 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3322 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3323 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3324 FR64:$src))), (i8 1))),
3325 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3327 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3328 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3329 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3330 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3331 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3332 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3333 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3334 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3335 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3336 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3337 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3338 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3339 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3340 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3341 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3342 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3345 // Patterns used to select SSE scalar fp arithmetic instructions from
3346 // a vector packed single/double fp operation followed by a vector insert.
3348 // The effect is that the backend converts the packed fp instruction
3349 // followed by a vector insert into a single SSE scalar fp instruction.
3351 // For example, given the following code:
3352 // __m128 foo(__m128 A, __m128 B) {
3353 // __m128 C = A + B;
3354 // return (__m128) {c[0], a[1], a[2], a[3]};
3357 // previously we generated:
3358 // addps %xmm0, %xmm1
3359 // movss %xmm1, %xmm0
3362 // addss %xmm1, %xmm0
3364 let Predicates = [UseSSE1] in {
3365 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3366 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3367 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3368 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3369 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3370 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3371 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3372 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3373 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3374 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3375 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3376 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3379 let Predicates = [UseSSE2] in {
3380 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3381 // from a packed double-precision fp instruction plus movsd.
3383 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3384 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3385 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3386 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3387 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3388 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3389 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3390 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3391 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3392 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3393 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3394 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3397 let Predicates = [UseSSE41] in {
3398 // With SSE4.1 we may see these operations using X86Blendi rather than
3400 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3401 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3402 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3403 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3404 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3405 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3406 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3407 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3408 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3409 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3410 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3411 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3413 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3414 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3415 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3416 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3417 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3418 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3419 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3420 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3421 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3422 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3423 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3424 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3426 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3427 (v2f64 VR128:$dst), (i8 2))),
3428 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3429 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3430 (v2f64 VR128:$dst), (i8 2))),
3431 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3432 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3433 (v2f64 VR128:$dst), (i8 2))),
3434 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3435 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3436 (v2f64 VR128:$dst), (i8 2))),
3437 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3440 let Predicates = [HasAVX] in {
3441 // The following patterns select AVX Scalar single/double precision fp
3442 // arithmetic instructions from a packed single precision fp instruction
3443 // plus movss/movsd.
3445 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3446 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3447 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3448 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3449 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3450 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3451 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3452 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3453 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3454 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3455 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3456 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3457 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3458 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3459 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3460 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3461 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3462 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3463 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3464 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3465 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3466 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3467 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3468 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3470 // Also handle X86Blendi-based patterns.
3471 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3472 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3473 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3474 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3475 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3476 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3477 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3478 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3479 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3480 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3481 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3482 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3484 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3485 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3486 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3487 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3488 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3489 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3490 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3491 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3492 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3493 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3494 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3495 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3497 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3498 (v2f64 VR128:$dst), (i8 2))),
3499 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3500 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3501 (v2f64 VR128:$dst), (i8 2))),
3502 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3503 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3504 (v2f64 VR128:$dst), (i8 2))),
3505 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3506 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3507 (v2f64 VR128:$dst), (i8 2))),
3508 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3512 /// In addition, we also have a special variant of the scalar form here to
3513 /// represent the associated intrinsic operation. This form is unlike the
3514 /// plain scalar form, in that it takes an entire vector (instead of a
3515 /// scalar) and leaves the top elements undefined.
3517 /// And, we have a special variant form for a full-vector intrinsic form.
3519 let Sched = WriteFSqrt in {
3520 def SSE_SQRTPS : OpndItins<
3521 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3524 def SSE_SQRTSS : OpndItins<
3525 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3528 def SSE_SQRTPD : OpndItins<
3529 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3532 def SSE_SQRTSD : OpndItins<
3533 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3537 let Sched = WriteFRsqrt in {
3538 def SSE_RSQRTPS : OpndItins<
3539 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3542 def SSE_RSQRTSS : OpndItins<
3543 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3547 let Sched = WriteFRcp in {
3548 def SSE_RCPP : OpndItins<
3549 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3552 def SSE_RCPS : OpndItins<
3553 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3557 /// sse1_fp_unop_s - SSE1 unops in scalar form
3558 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3559 /// the HW instructions are 2 operand / destructive.
3560 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3562 let Predicates = [HasAVX], hasSideEffects = 0 in {
3563 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3564 (ins FR32:$src1, FR32:$src2),
3565 !strconcat("v", OpcodeStr,
3566 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3567 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3568 let mayLoad = 1 in {
3569 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3570 (ins FR32:$src1,f32mem:$src2),
3571 !strconcat("v", OpcodeStr,
3572 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3573 []>, VEX_4V, VEX_LIG,
3574 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3575 let isCodeGenOnly = 1 in
3576 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3577 (ins VR128:$src1, ssmem:$src2),
3578 !strconcat("v", OpcodeStr,
3579 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3580 []>, VEX_4V, VEX_LIG,
3581 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3585 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3586 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3587 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3588 // For scalar unary operations, fold a load into the operation
3589 // only in OptForSize mode. It eliminates an instruction, but it also
3590 // eliminates a whole-register clobber (the load), so it introduces a
3591 // partial register update condition.
3592 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3593 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3594 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3595 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3596 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3597 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3598 (ins VR128:$src1, VR128:$src2),
3599 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3600 [], itins.rr>, Sched<[itins.Sched]>;
3601 let mayLoad = 1, hasSideEffects = 0 in
3602 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3603 (ins VR128:$src1, ssmem:$src2),
3604 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3605 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3609 /// sse1_fp_unop_p - SSE1 unops in packed form.
3610 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3612 let Predicates = [HasAVX] in {
3613 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3614 !strconcat("v", OpcodeStr,
3615 "ps\t{$src, $dst|$dst, $src}"),
3616 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3617 itins.rr>, VEX, Sched<[itins.Sched]>;
3618 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3619 !strconcat("v", OpcodeStr,
3620 "ps\t{$src, $dst|$dst, $src}"),
3621 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3622 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3623 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3624 !strconcat("v", OpcodeStr,
3625 "ps\t{$src, $dst|$dst, $src}"),
3626 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3627 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3628 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3629 !strconcat("v", OpcodeStr,
3630 "ps\t{$src, $dst|$dst, $src}"),
3631 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3632 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3635 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3636 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3637 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3638 Sched<[itins.Sched]>;
3639 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3640 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3641 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3642 Sched<[itins.Sched.Folded]>;
3645 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3646 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3647 Intrinsic V4F32Int, Intrinsic V8F32Int,
3649 let isCodeGenOnly = 1 in {
3650 let Predicates = [HasAVX] in {
3651 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3652 !strconcat("v", OpcodeStr,
3653 "ps\t{$src, $dst|$dst, $src}"),
3654 [(set VR128:$dst, (V4F32Int VR128:$src))],
3655 itins.rr>, VEX, Sched<[itins.Sched]>;
3656 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3657 !strconcat("v", OpcodeStr,
3658 "ps\t{$src, $dst|$dst, $src}"),
3659 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3660 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3661 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3662 !strconcat("v", OpcodeStr,
3663 "ps\t{$src, $dst|$dst, $src}"),
3664 [(set VR256:$dst, (V8F32Int VR256:$src))],
3665 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3666 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3668 !strconcat("v", OpcodeStr,
3669 "ps\t{$src, $dst|$dst, $src}"),
3670 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3671 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3674 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3675 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3676 [(set VR128:$dst, (V4F32Int VR128:$src))],
3677 itins.rr>, Sched<[itins.Sched]>;
3678 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3679 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3680 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3681 itins.rm>, Sched<[itins.Sched.Folded]>;
3682 } // isCodeGenOnly = 1
3685 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3686 // FIXME: Combine the following sse2 classes with the sse1 classes above.
3687 // The only usage of these is for SQRT[S/P]D. See sse12_fp_binop* for example.
3688 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3689 SDNode OpNode, OpndItins itins> {
3690 let Predicates = [HasAVX], hasSideEffects = 0 in {
3691 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3692 (ins FR64:$src1, FR64:$src2),
3693 !strconcat("v", OpcodeStr,
3694 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3695 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3696 let mayLoad = 1 in {
3697 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3698 (ins FR64:$src1,f64mem:$src2),
3699 !strconcat("v", OpcodeStr,
3700 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3701 []>, VEX_4V, VEX_LIG,
3702 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3703 let isCodeGenOnly = 1 in
3704 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3705 (ins VR128:$src1, sdmem:$src2),
3706 !strconcat("v", OpcodeStr,
3707 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3708 []>, VEX_4V, VEX_LIG,
3709 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3713 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3714 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3715 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3716 Sched<[itins.Sched]>;
3717 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3718 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3719 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3720 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3721 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3722 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3724 SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3725 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
3726 [], itins.rr>, Sched<[itins.Sched]>;
3728 let mayLoad = 1, hasSideEffects = 0 in
3730 SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
3731 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
3732 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3733 } // isCodeGenOnly, Constraints
3736 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3737 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3738 SDNode OpNode, OpndItins itins> {
3739 let Predicates = [HasAVX] in {
3740 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3741 !strconcat("v", OpcodeStr,
3742 "pd\t{$src, $dst|$dst, $src}"),
3743 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3744 itins.rr>, VEX, Sched<[itins.Sched]>;
3745 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3746 !strconcat("v", OpcodeStr,
3747 "pd\t{$src, $dst|$dst, $src}"),
3748 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3749 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3750 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3751 !strconcat("v", OpcodeStr,
3752 "pd\t{$src, $dst|$dst, $src}"),
3753 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3754 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3755 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3756 !strconcat("v", OpcodeStr,
3757 "pd\t{$src, $dst|$dst, $src}"),
3758 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3759 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3762 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3763 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3764 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3765 Sched<[itins.Sched]>;
3766 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3767 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3768 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3769 Sched<[itins.Sched.Folded]>;
3773 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3774 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3775 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3776 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3778 // Reciprocal approximations. Note that these typically require refinement
3779 // in order to obtain suitable precision.
3780 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3781 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
3782 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3783 int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
3784 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3785 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3786 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3787 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3789 let Predicates = [UseAVX] in {
3790 def : Pat<(f32 (fsqrt FR32:$src)),
3791 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3792 def : Pat<(f32 (fsqrt (load addr:$src))),
3793 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3794 Requires<[HasAVX, OptForSize]>;
3795 def : Pat<(f64 (fsqrt FR64:$src)),
3796 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3797 def : Pat<(f64 (fsqrt (load addr:$src))),
3798 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3799 Requires<[HasAVX, OptForSize]>;
3801 def : Pat<(f32 (X86frsqrt FR32:$src)),
3802 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3803 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3804 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3805 Requires<[HasAVX, OptForSize]>;
3807 def : Pat<(f32 (X86frcp FR32:$src)),
3808 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3809 def : Pat<(f32 (X86frcp (load addr:$src))),
3810 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3811 Requires<[HasAVX, OptForSize]>;
3813 let Predicates = [UseAVX] in {
3814 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3815 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3816 (COPY_TO_REGCLASS VR128:$src, FR32)),
3818 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3819 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3821 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3822 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3823 (COPY_TO_REGCLASS VR128:$src, FR64)),
3825 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3826 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3829 let Predicates = [HasAVX] in {
3830 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3831 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3832 (COPY_TO_REGCLASS VR128:$src, FR32)),
3834 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3835 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3837 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3838 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3839 (COPY_TO_REGCLASS VR128:$src, FR32)),
3841 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3842 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3845 // These are unary operations, but they are modeled as having 2 source operands
3846 // because the high elements of the destination are unchanged in SSE.
3847 let Predicates = [UseSSE1] in {
3848 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3849 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3850 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3851 (RCPSSr_Int VR128:$src, VR128:$src)>;
3852 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3853 (SQRTSSr_Int VR128:$src, VR128:$src)>;
3854 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3855 (SQRTSDr_Int VR128:$src, VR128:$src)>;
3858 // There is no f64 version of the reciprocal approximation instructions.
3860 //===----------------------------------------------------------------------===//
3861 // SSE 1 & 2 - Non-temporal stores
3862 //===----------------------------------------------------------------------===//
3864 let AddedComplexity = 400 in { // Prefer non-temporal versions
3865 let SchedRW = [WriteStore] in {
3866 let Predicates = [HasAVX, NoVLX] in {
3867 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3868 (ins f128mem:$dst, VR128:$src),
3869 "movntps\t{$src, $dst|$dst, $src}",
3870 [(alignednontemporalstore (v4f32 VR128:$src),
3872 IIC_SSE_MOVNT>, VEX;
3873 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3874 (ins f128mem:$dst, VR128:$src),
3875 "movntpd\t{$src, $dst|$dst, $src}",
3876 [(alignednontemporalstore (v2f64 VR128:$src),
3878 IIC_SSE_MOVNT>, VEX;
3880 let ExeDomain = SSEPackedInt in
3881 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3882 (ins f128mem:$dst, VR128:$src),
3883 "movntdq\t{$src, $dst|$dst, $src}",
3884 [(alignednontemporalstore (v2i64 VR128:$src),
3886 IIC_SSE_MOVNT>, VEX;
3888 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3889 (ins f256mem:$dst, VR256:$src),
3890 "movntps\t{$src, $dst|$dst, $src}",
3891 [(alignednontemporalstore (v8f32 VR256:$src),
3893 IIC_SSE_MOVNT>, VEX, VEX_L;
3894 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3895 (ins f256mem:$dst, VR256:$src),
3896 "movntpd\t{$src, $dst|$dst, $src}",
3897 [(alignednontemporalstore (v4f64 VR256:$src),
3899 IIC_SSE_MOVNT>, VEX, VEX_L;
3900 let ExeDomain = SSEPackedInt in
3901 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3902 (ins f256mem:$dst, VR256:$src),
3903 "movntdq\t{$src, $dst|$dst, $src}",
3904 [(alignednontemporalstore (v4i64 VR256:$src),
3906 IIC_SSE_MOVNT>, VEX, VEX_L;
3909 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3910 "movntps\t{$src, $dst|$dst, $src}",
3911 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3913 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3914 "movntpd\t{$src, $dst|$dst, $src}",
3915 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3918 let ExeDomain = SSEPackedInt in
3919 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3920 "movntdq\t{$src, $dst|$dst, $src}",
3921 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3924 // There is no AVX form for instructions below this point
3925 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3926 "movnti{l}\t{$src, $dst|$dst, $src}",
3927 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3929 PS, Requires<[HasSSE2]>;
3930 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3931 "movnti{q}\t{$src, $dst|$dst, $src}",
3932 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3934 PS, Requires<[HasSSE2]>;
3935 } // SchedRW = [WriteStore]
3937 let Predicates = [HasAVX, NoVLX] in {
3938 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3939 (VMOVNTPSmr addr:$dst, VR128:$src)>;
3942 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3943 (MOVNTPSmr addr:$dst, VR128:$src)>;
3945 } // AddedComplexity
3947 //===----------------------------------------------------------------------===//
3948 // SSE 1 & 2 - Prefetch and memory fence
3949 //===----------------------------------------------------------------------===//
3951 // Prefetch intrinsic.
3952 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3953 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3954 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3955 IIC_SSE_PREFETCH>, TB;
3956 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3957 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3958 IIC_SSE_PREFETCH>, TB;
3959 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3960 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3961 IIC_SSE_PREFETCH>, TB;
3962 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3963 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3964 IIC_SSE_PREFETCH>, TB;
3967 // FIXME: How should flush instruction be modeled?
3968 let SchedRW = [WriteLoad] in {
3970 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3971 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3972 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3975 let SchedRW = [WriteNop] in {
3976 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3977 // was introduced with SSE2, it's backward compatible.
3978 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3979 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3980 OBXS, Requires<[HasSSE2]>;
3983 let SchedRW = [WriteFence] in {
3984 // Load, store, and memory fence
3985 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3986 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3987 TB, Requires<[HasSSE1]>;
3988 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3989 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3990 TB, Requires<[HasSSE2]>;
3991 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3992 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3993 TB, Requires<[HasSSE2]>;
3996 def : Pat<(X86SFence), (SFENCE)>;
3997 def : Pat<(X86LFence), (LFENCE)>;
3998 def : Pat<(X86MFence), (MFENCE)>;
4000 //===----------------------------------------------------------------------===//
4001 // SSE 1 & 2 - Load/Store XCSR register
4002 //===----------------------------------------------------------------------===//
4004 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
4005 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
4006 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
4007 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
4008 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
4009 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
4011 let Predicates = [UseSSE1] in {
4012 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
4013 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
4014 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
4015 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
4016 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
4017 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
4020 //===---------------------------------------------------------------------===//
4021 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
4022 //===---------------------------------------------------------------------===//
4024 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4026 let hasSideEffects = 0, SchedRW = [WriteMove] in {
4027 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4028 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
4030 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4031 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
4033 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4034 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4036 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4037 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4042 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4043 SchedRW = [WriteMove] in {
4044 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4045 "movdqa\t{$src, $dst|$dst, $src}", [],
4048 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4049 "movdqa\t{$src, $dst|$dst, $src}", [],
4050 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
4051 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4052 "movdqu\t{$src, $dst|$dst, $src}", [],
4055 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4056 "movdqu\t{$src, $dst|$dst, $src}", [],
4057 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
4060 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4061 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4062 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4063 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4065 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4066 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4068 let Predicates = [HasAVX] in {
4069 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4070 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4072 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4073 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4078 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4079 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
4080 (ins i128mem:$dst, VR128:$src),
4081 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4083 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
4084 (ins i256mem:$dst, VR256:$src),
4085 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4087 let Predicates = [HasAVX] in {
4088 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4089 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4091 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
4092 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4097 let SchedRW = [WriteMove] in {
4098 let hasSideEffects = 0 in
4099 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4100 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
4102 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4103 "movdqu\t{$src, $dst|$dst, $src}",
4104 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4107 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
4108 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4109 "movdqa\t{$src, $dst|$dst, $src}", [],
4112 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4113 "movdqu\t{$src, $dst|$dst, $src}",
4114 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4118 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4119 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4120 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4121 "movdqa\t{$src, $dst|$dst, $src}",
4122 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
4124 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4125 "movdqu\t{$src, $dst|$dst, $src}",
4126 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
4128 XS, Requires<[UseSSE2]>;
4131 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4132 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4133 "movdqa\t{$src, $dst|$dst, $src}",
4134 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
4136 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4137 "movdqu\t{$src, $dst|$dst, $src}",
4138 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
4140 XS, Requires<[UseSSE2]>;
4143 } // ExeDomain = SSEPackedInt
4145 let Predicates = [HasAVX] in {
4146 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4147 (VMOVDQUmr addr:$dst, VR128:$src)>;
4148 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
4149 (VMOVDQUYmr addr:$dst, VR256:$src)>;
4151 let Predicates = [UseSSE2] in
4152 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4153 (MOVDQUmr addr:$dst, VR128:$src)>;
4155 //===---------------------------------------------------------------------===//
4156 // SSE2 - Packed Integer Arithmetic Instructions
4157 //===---------------------------------------------------------------------===//
4159 let Sched = WriteVecIMul in
4160 def SSE_PMADD : OpndItins<
4161 IIC_SSE_PMADD, IIC_SSE_PMADD
4164 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4166 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
4167 RegisterClass RC, PatFrag memop_frag,
4168 X86MemOperand x86memop,
4170 bit IsCommutable = 0,
4172 let isCommutable = IsCommutable in
4173 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4174 (ins RC:$src1, RC:$src2),
4176 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4177 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4178 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
4179 Sched<[itins.Sched]>;
4180 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4181 (ins RC:$src1, x86memop:$src2),
4183 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4184 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4185 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
4186 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
4189 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
4190 Intrinsic IntId256, OpndItins itins,
4191 bit IsCommutable = 0> {
4192 let Predicates = [HasAVX] in
4193 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
4194 VR128, loadv2i64, i128mem, itins,
4195 IsCommutable, 0>, VEX_4V;
4197 let Constraints = "$src1 = $dst" in
4198 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
4199 i128mem, itins, IsCommutable, 1>;
4201 let Predicates = [HasAVX2] in
4202 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
4203 VR256, loadv4i64, i256mem, itins,
4204 IsCommutable, 0>, VEX_4V, VEX_L;
4207 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
4208 string OpcodeStr, SDNode OpNode,
4209 SDNode OpNode2, RegisterClass RC,
4210 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
4211 ShiftOpndItins itins,
4213 // src2 is always 128-bit
4214 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4215 (ins RC:$src1, VR128:$src2),
4217 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4218 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4219 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
4220 itins.rr>, Sched<[WriteVecShift]>;
4221 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4222 (ins RC:$src1, i128mem:$src2),
4224 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4225 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4226 [(set RC:$dst, (DstVT (OpNode RC:$src1,
4227 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
4228 Sched<[WriteVecShiftLd, ReadAfterLd]>;
4229 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
4230 (ins RC:$src1, u8imm:$src2),
4232 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4233 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4234 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
4235 Sched<[WriteVecShift]>;
4238 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4239 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4240 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4241 PatFrag memop_frag, X86MemOperand x86memop,
4243 bit IsCommutable = 0, bit Is2Addr = 1> {
4244 let isCommutable = IsCommutable in
4245 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4246 (ins RC:$src1, RC:$src2),
4248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4250 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4251 Sched<[itins.Sched]>;
4252 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4253 (ins RC:$src1, x86memop:$src2),
4255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4257 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4258 (bitconvert (memop_frag addr:$src2)))))]>,
4259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4261 } // ExeDomain = SSEPackedInt
4263 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4264 SSE_INTALU_ITINS_P, 1>;
4265 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4266 SSE_INTALU_ITINS_P, 1>;
4267 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4268 SSE_INTALU_ITINS_P, 1>;
4269 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4270 SSE_INTALUQ_ITINS_P, 1>;
4271 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4272 SSE_INTMUL_ITINS_P, 1>;
4273 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4274 SSE_INTMUL_ITINS_P, 1>;
4275 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4276 SSE_INTMUL_ITINS_P, 1>;
4277 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4278 SSE_INTALU_ITINS_P, 0>;
4279 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4280 SSE_INTALU_ITINS_P, 0>;
4281 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4282 SSE_INTALU_ITINS_P, 0>;
4283 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4284 SSE_INTALUQ_ITINS_P, 0>;
4285 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4286 SSE_INTALU_ITINS_P, 0>;
4287 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4288 SSE_INTALU_ITINS_P, 0>;
4289 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4290 SSE_INTALU_ITINS_P, 1>;
4291 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4292 SSE_INTALU_ITINS_P, 1>;
4293 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4294 SSE_INTALU_ITINS_P, 1>;
4295 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4296 SSE_INTALU_ITINS_P, 1>;
4299 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4300 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4301 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4302 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4303 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4304 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4305 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4306 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4307 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4308 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4309 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4310 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4311 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4312 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4313 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4314 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4315 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4316 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4317 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4318 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4320 let Predicates = [HasAVX] in
4321 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4322 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4324 let Predicates = [HasAVX2] in
4325 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4326 VR256, loadv4i64, i256mem,
4327 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4328 let Constraints = "$src1 = $dst" in
4329 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4330 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4332 //===---------------------------------------------------------------------===//
4333 // SSE2 - Packed Integer Logical Instructions
4334 //===---------------------------------------------------------------------===//
4336 let Predicates = [HasAVX] in {
4337 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4338 VR128, v8i16, v8i16, bc_v8i16,
4339 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4340 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4341 VR128, v4i32, v4i32, bc_v4i32,
4342 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4343 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4344 VR128, v2i64, v2i64, bc_v2i64,
4345 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4347 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4348 VR128, v8i16, v8i16, bc_v8i16,
4349 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4350 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4351 VR128, v4i32, v4i32, bc_v4i32,
4352 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4353 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4354 VR128, v2i64, v2i64, bc_v2i64,
4355 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4357 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4358 VR128, v8i16, v8i16, bc_v8i16,
4359 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4360 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4361 VR128, v4i32, v4i32, bc_v4i32,
4362 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4364 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4365 // 128-bit logical shifts.
4366 def VPSLLDQri : PDIi8<0x73, MRM7r,
4367 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4368 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4370 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4372 def VPSRLDQri : PDIi8<0x73, MRM3r,
4373 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4374 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4376 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4378 // PSRADQri doesn't exist in SSE[1-3].
4380 } // Predicates = [HasAVX]
4382 let Predicates = [HasAVX2] in {
4383 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4384 VR256, v16i16, v8i16, bc_v8i16,
4385 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4386 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4387 VR256, v8i32, v4i32, bc_v4i32,
4388 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4389 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4390 VR256, v4i64, v2i64, bc_v2i64,
4391 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4393 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4394 VR256, v16i16, v8i16, bc_v8i16,
4395 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4396 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4397 VR256, v8i32, v4i32, bc_v4i32,
4398 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4399 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4400 VR256, v4i64, v2i64, bc_v2i64,
4401 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4403 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4404 VR256, v16i16, v8i16, bc_v8i16,
4405 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4406 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4407 VR256, v8i32, v4i32, bc_v4i32,
4408 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4410 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4411 // 256-bit logical shifts.
4412 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4413 (outs VR256:$dst), (ins VR256:$src1, i32u8imm:$src2),
4414 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4416 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4418 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4419 (outs VR256:$dst), (ins VR256:$src1, i32u8imm:$src2),
4420 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4422 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4424 // PSRADQYri doesn't exist in SSE[1-3].
4426 } // Predicates = [HasAVX2]
4428 let Constraints = "$src1 = $dst" in {
4429 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4430 VR128, v8i16, v8i16, bc_v8i16,
4431 SSE_INTSHIFT_ITINS_P>;
4432 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4433 VR128, v4i32, v4i32, bc_v4i32,
4434 SSE_INTSHIFT_ITINS_P>;
4435 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4436 VR128, v2i64, v2i64, bc_v2i64,
4437 SSE_INTSHIFT_ITINS_P>;
4439 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4440 VR128, v8i16, v8i16, bc_v8i16,
4441 SSE_INTSHIFT_ITINS_P>;
4442 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4443 VR128, v4i32, v4i32, bc_v4i32,
4444 SSE_INTSHIFT_ITINS_P>;
4445 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4446 VR128, v2i64, v2i64, bc_v2i64,
4447 SSE_INTSHIFT_ITINS_P>;
4449 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4450 VR128, v8i16, v8i16, bc_v8i16,
4451 SSE_INTSHIFT_ITINS_P>;
4452 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4453 VR128, v4i32, v4i32, bc_v4i32,
4454 SSE_INTSHIFT_ITINS_P>;
4456 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4457 // 128-bit logical shifts.
4458 def PSLLDQri : PDIi8<0x73, MRM7r,
4459 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4460 "pslldq\t{$src2, $dst|$dst, $src2}",
4462 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4463 IIC_SSE_INTSHDQ_P_RI>;
4464 def PSRLDQri : PDIi8<0x73, MRM3r,
4465 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4466 "psrldq\t{$src2, $dst|$dst, $src2}",
4468 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4469 IIC_SSE_INTSHDQ_P_RI>;
4470 // PSRADQri doesn't exist in SSE[1-3].
4472 } // Constraints = "$src1 = $dst"
4474 let Predicates = [HasAVX] in {
4475 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4476 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4477 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4478 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4479 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4480 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4482 // Shift up / down and insert zero's.
4483 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4484 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4485 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4486 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4489 let Predicates = [HasAVX2] in {
4490 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4491 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4492 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4493 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4496 let Predicates = [UseSSE2] in {
4497 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4498 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4499 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4500 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4501 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4502 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4504 // Shift up / down and insert zero's.
4505 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4506 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4507 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4508 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4511 //===---------------------------------------------------------------------===//
4512 // SSE2 - Packed Integer Comparison Instructions
4513 //===---------------------------------------------------------------------===//
4515 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4516 SSE_INTALU_ITINS_P, 1>;
4517 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4518 SSE_INTALU_ITINS_P, 1>;
4519 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4520 SSE_INTALU_ITINS_P, 1>;
4521 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4522 SSE_INTALU_ITINS_P, 0>;
4523 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4524 SSE_INTALU_ITINS_P, 0>;
4525 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4526 SSE_INTALU_ITINS_P, 0>;
4528 //===---------------------------------------------------------------------===//
4529 // SSE2 - Packed Integer Shuffle Instructions
4530 //===---------------------------------------------------------------------===//
4532 let ExeDomain = SSEPackedInt in {
4533 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4535 let Predicates = [HasAVX] in {
4536 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4537 (ins VR128:$src1, u8imm:$src2),
4538 !strconcat("v", OpcodeStr,
4539 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4541 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4542 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4543 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4544 (ins i128mem:$src1, u8imm:$src2),
4545 !strconcat("v", OpcodeStr,
4546 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4548 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4549 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4550 Sched<[WriteShuffleLd]>;
4553 let Predicates = [HasAVX2] in {
4554 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4555 (ins VR256:$src1, u8imm:$src2),
4556 !strconcat("v", OpcodeStr,
4557 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4559 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4560 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4561 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4562 (ins i256mem:$src1, u8imm:$src2),
4563 !strconcat("v", OpcodeStr,
4564 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4566 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4567 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4568 Sched<[WriteShuffleLd]>;
4571 let Predicates = [UseSSE2] in {
4572 def ri : Ii8<0x70, MRMSrcReg,
4573 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4574 !strconcat(OpcodeStr,
4575 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4577 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4578 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4579 def mi : Ii8<0x70, MRMSrcMem,
4580 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4581 !strconcat(OpcodeStr,
4582 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4584 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4585 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4586 Sched<[WriteShuffleLd, ReadAfterLd]>;
4589 } // ExeDomain = SSEPackedInt
4591 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4592 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4593 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4595 let Predicates = [HasAVX] in {
4596 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4597 (VPSHUFDmi addr:$src1, imm:$imm)>;
4598 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4599 (VPSHUFDri VR128:$src1, imm:$imm)>;
4602 let Predicates = [UseSSE2] in {
4603 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4604 (PSHUFDmi addr:$src1, imm:$imm)>;
4605 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4606 (PSHUFDri VR128:$src1, imm:$imm)>;
4609 //===---------------------------------------------------------------------===//
4610 // Packed Integer Pack Instructions (SSE & AVX)
4611 //===---------------------------------------------------------------------===//
4613 let ExeDomain = SSEPackedInt in {
4614 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4615 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4617 def rr : PDI<opc, MRMSrcReg,
4618 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4620 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4621 !strconcat(OpcodeStr,
4622 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4624 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4625 Sched<[WriteShuffle]>;
4626 def rm : PDI<opc, MRMSrcMem,
4627 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4629 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4630 !strconcat(OpcodeStr,
4631 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4633 (OutVT (OpNode VR128:$src1,
4634 (bc_frag (memopv2i64 addr:$src2)))))]>,
4635 Sched<[WriteShuffleLd, ReadAfterLd]>;
4638 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4639 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4640 def Yrr : PDI<opc, MRMSrcReg,
4641 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4642 !strconcat(OpcodeStr,
4643 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4645 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4646 Sched<[WriteShuffle]>;
4647 def Yrm : PDI<opc, MRMSrcMem,
4648 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4649 !strconcat(OpcodeStr,
4650 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4652 (OutVT (OpNode VR256:$src1,
4653 (bc_frag (memopv4i64 addr:$src2)))))]>,
4654 Sched<[WriteShuffleLd, ReadAfterLd]>;
4657 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4658 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4660 def rr : SS48I<opc, MRMSrcReg,
4661 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4664 !strconcat(OpcodeStr,
4665 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4667 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4668 Sched<[WriteShuffle]>;
4669 def rm : SS48I<opc, MRMSrcMem,
4670 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4672 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4673 !strconcat(OpcodeStr,
4674 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4676 (OutVT (OpNode VR128:$src1,
4677 (bc_frag (memopv2i64 addr:$src2)))))]>,
4678 Sched<[WriteShuffleLd, ReadAfterLd]>;
4681 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4682 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4683 def Yrr : SS48I<opc, MRMSrcReg,
4684 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4685 !strconcat(OpcodeStr,
4686 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4688 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4689 Sched<[WriteShuffle]>;
4690 def Yrm : SS48I<opc, MRMSrcMem,
4691 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4692 !strconcat(OpcodeStr,
4693 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4695 (OutVT (OpNode VR256:$src1,
4696 (bc_frag (memopv4i64 addr:$src2)))))]>,
4697 Sched<[WriteShuffleLd, ReadAfterLd]>;
4700 let Predicates = [HasAVX] in {
4701 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4702 bc_v8i16, 0>, VEX_4V;
4703 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4704 bc_v4i32, 0>, VEX_4V;
4706 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4707 bc_v8i16, 0>, VEX_4V;
4708 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4709 bc_v4i32, 0>, VEX_4V;
4712 let Predicates = [HasAVX2] in {
4713 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4714 bc_v16i16>, VEX_4V, VEX_L;
4715 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4716 bc_v8i32>, VEX_4V, VEX_L;
4718 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4719 bc_v16i16>, VEX_4V, VEX_L;
4720 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4721 bc_v8i32>, VEX_4V, VEX_L;
4724 let Constraints = "$src1 = $dst" in {
4725 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4727 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4730 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4733 let Predicates = [HasSSE41] in
4734 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4737 } // ExeDomain = SSEPackedInt
4739 //===---------------------------------------------------------------------===//
4740 // SSE2 - Packed Integer Unpack Instructions
4741 //===---------------------------------------------------------------------===//
4743 let ExeDomain = SSEPackedInt in {
4744 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4745 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4746 def rr : PDI<opc, MRMSrcReg,
4747 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4749 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4750 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4751 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4752 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4753 def rm : PDI<opc, MRMSrcMem,
4754 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4756 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4757 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4758 [(set VR128:$dst, (OpNode VR128:$src1,
4759 (bc_frag (memopv2i64
4762 Sched<[WriteShuffleLd, ReadAfterLd]>;
4765 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4766 SDNode OpNode, PatFrag bc_frag> {
4767 def Yrr : PDI<opc, MRMSrcReg,
4768 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4769 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4770 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4771 Sched<[WriteShuffle]>;
4772 def Yrm : PDI<opc, MRMSrcMem,
4773 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4774 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4775 [(set VR256:$dst, (OpNode VR256:$src1,
4776 (bc_frag (memopv4i64 addr:$src2))))]>,
4777 Sched<[WriteShuffleLd, ReadAfterLd]>;
4780 let Predicates = [HasAVX] in {
4781 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4782 bc_v16i8, 0>, VEX_4V;
4783 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4784 bc_v8i16, 0>, VEX_4V;
4785 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4786 bc_v4i32, 0>, VEX_4V;
4787 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4788 bc_v2i64, 0>, VEX_4V;
4790 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4791 bc_v16i8, 0>, VEX_4V;
4792 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4793 bc_v8i16, 0>, VEX_4V;
4794 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4795 bc_v4i32, 0>, VEX_4V;
4796 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4797 bc_v2i64, 0>, VEX_4V;
4800 let Predicates = [HasAVX2] in {
4801 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4802 bc_v32i8>, VEX_4V, VEX_L;
4803 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4804 bc_v16i16>, VEX_4V, VEX_L;
4805 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4806 bc_v8i32>, VEX_4V, VEX_L;
4807 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4808 bc_v4i64>, VEX_4V, VEX_L;
4810 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4811 bc_v32i8>, VEX_4V, VEX_L;
4812 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4813 bc_v16i16>, VEX_4V, VEX_L;
4814 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4815 bc_v8i32>, VEX_4V, VEX_L;
4816 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4817 bc_v4i64>, VEX_4V, VEX_L;
4820 let Constraints = "$src1 = $dst" in {
4821 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4823 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4825 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4827 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4830 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4832 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4834 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4836 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4839 } // ExeDomain = SSEPackedInt
4841 //===---------------------------------------------------------------------===//
4842 // SSE2 - Packed Integer Extract and Insert
4843 //===---------------------------------------------------------------------===//
4845 let ExeDomain = SSEPackedInt in {
4846 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4847 def rri : Ii8<0xC4, MRMSrcReg,
4848 (outs VR128:$dst), (ins VR128:$src1,
4849 GR32orGR64:$src2, u8imm:$src3),
4851 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4852 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4854 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4855 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4856 def rmi : Ii8<0xC4, MRMSrcMem,
4857 (outs VR128:$dst), (ins VR128:$src1,
4858 i16mem:$src2, u8imm:$src3),
4860 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4861 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4863 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4864 imm:$src3))], IIC_SSE_PINSRW>,
4865 Sched<[WriteShuffleLd, ReadAfterLd]>;
4869 let Predicates = [HasAVX] in
4870 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4871 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4872 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4873 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4874 imm:$src2))]>, PD, VEX,
4875 Sched<[WriteShuffle]>;
4876 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4877 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4878 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4879 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4880 imm:$src2))], IIC_SSE_PEXTRW>,
4881 Sched<[WriteShuffleLd, ReadAfterLd]>;
4884 let Predicates = [HasAVX] in
4885 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4887 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4888 defm PINSRW : sse2_pinsrw, PD;
4890 } // ExeDomain = SSEPackedInt
4892 //===---------------------------------------------------------------------===//
4893 // SSE2 - Packed Mask Creation
4894 //===---------------------------------------------------------------------===//
4896 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4898 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4900 "pmovmskb\t{$src, $dst|$dst, $src}",
4901 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4902 IIC_SSE_MOVMSK>, VEX;
4904 let Predicates = [HasAVX2] in {
4905 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4907 "pmovmskb\t{$src, $dst|$dst, $src}",
4908 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4912 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4913 "pmovmskb\t{$src, $dst|$dst, $src}",
4914 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4917 } // ExeDomain = SSEPackedInt
4919 //===---------------------------------------------------------------------===//
4920 // SSE2 - Conditional Store
4921 //===---------------------------------------------------------------------===//
4923 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4925 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4926 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4927 (ins VR128:$src, VR128:$mask),
4928 "maskmovdqu\t{$mask, $src|$src, $mask}",
4929 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4930 IIC_SSE_MASKMOV>, VEX;
4931 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4932 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4933 (ins VR128:$src, VR128:$mask),
4934 "maskmovdqu\t{$mask, $src|$src, $mask}",
4935 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4936 IIC_SSE_MASKMOV>, VEX;
4938 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4939 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4940 "maskmovdqu\t{$mask, $src|$src, $mask}",
4941 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4943 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4944 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4945 "maskmovdqu\t{$mask, $src|$src, $mask}",
4946 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4949 } // ExeDomain = SSEPackedInt
4951 //===---------------------------------------------------------------------===//
4952 // SSE2 - Move Doubleword
4953 //===---------------------------------------------------------------------===//
4955 //===---------------------------------------------------------------------===//
4956 // Move Int Doubleword to Packed Double Int
4958 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4959 "movd\t{$src, $dst|$dst, $src}",
4961 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4962 VEX, Sched<[WriteMove]>;
4963 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4964 "movd\t{$src, $dst|$dst, $src}",
4966 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4968 VEX, Sched<[WriteLoad]>;
4969 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4970 "movq\t{$src, $dst|$dst, $src}",
4972 (v2i64 (scalar_to_vector GR64:$src)))],
4973 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4974 let isCodeGenOnly = 1 in
4975 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4976 "movq\t{$src, $dst|$dst, $src}",
4977 [(set FR64:$dst, (bitconvert GR64:$src))],
4978 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4980 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4981 "movd\t{$src, $dst|$dst, $src}",
4983 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4985 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4986 "movd\t{$src, $dst|$dst, $src}",
4988 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4989 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4990 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4991 "mov{d|q}\t{$src, $dst|$dst, $src}",
4993 (v2i64 (scalar_to_vector GR64:$src)))],
4994 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4995 let isCodeGenOnly = 1 in
4996 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4997 "mov{d|q}\t{$src, $dst|$dst, $src}",
4998 [(set FR64:$dst, (bitconvert GR64:$src))],
4999 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
5001 //===---------------------------------------------------------------------===//
5002 // Move Int Doubleword to Single Scalar
5004 let isCodeGenOnly = 1 in {
5005 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
5006 "movd\t{$src, $dst|$dst, $src}",
5007 [(set FR32:$dst, (bitconvert GR32:$src))],
5008 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
5010 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
5011 "movd\t{$src, $dst|$dst, $src}",
5012 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
5014 VEX, Sched<[WriteLoad]>;
5015 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
5016 "movd\t{$src, $dst|$dst, $src}",
5017 [(set FR32:$dst, (bitconvert GR32:$src))],
5018 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
5020 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
5021 "movd\t{$src, $dst|$dst, $src}",
5022 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
5023 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5026 //===---------------------------------------------------------------------===//
5027 // Move Packed Doubleword Int to Packed Double Int
5029 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5030 "movd\t{$src, $dst|$dst, $src}",
5031 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5032 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
5034 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
5035 (ins i32mem:$dst, VR128:$src),
5036 "movd\t{$src, $dst|$dst, $src}",
5037 [(store (i32 (vector_extract (v4i32 VR128:$src),
5038 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
5039 VEX, Sched<[WriteStore]>;
5040 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5041 "movd\t{$src, $dst|$dst, $src}",
5042 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5043 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
5045 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
5046 "movd\t{$src, $dst|$dst, $src}",
5047 [(store (i32 (vector_extract (v4i32 VR128:$src),
5048 (iPTR 0))), addr:$dst)],
5049 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5051 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
5052 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5054 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
5055 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5057 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
5058 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5060 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
5061 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5063 //===---------------------------------------------------------------------===//
5064 // Move Packed Doubleword Int first element to Doubleword Int
5066 let SchedRW = [WriteMove] in {
5067 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5068 "movq\t{$src, $dst|$dst, $src}",
5069 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5074 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5075 "mov{d|q}\t{$src, $dst|$dst, $src}",
5076 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5081 //===---------------------------------------------------------------------===//
5082 // Bitcast FR64 <-> GR64
5084 let isCodeGenOnly = 1 in {
5085 let Predicates = [UseAVX] in
5086 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5087 "movq\t{$src, $dst|$dst, $src}",
5088 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
5089 VEX, Sched<[WriteLoad]>;
5090 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5091 "movq\t{$src, $dst|$dst, $src}",
5092 [(set GR64:$dst, (bitconvert FR64:$src))],
5093 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
5094 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5095 "movq\t{$src, $dst|$dst, $src}",
5096 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5097 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5099 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5100 "movq\t{$src, $dst|$dst, $src}",
5101 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
5102 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5103 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5104 "mov{d|q}\t{$src, $dst|$dst, $src}",
5105 [(set GR64:$dst, (bitconvert FR64:$src))],
5106 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5107 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5108 "movq\t{$src, $dst|$dst, $src}",
5109 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5110 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5113 //===---------------------------------------------------------------------===//
5114 // Move Scalar Single to Double Int
5116 let isCodeGenOnly = 1 in {
5117 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5118 "movd\t{$src, $dst|$dst, $src}",
5119 [(set GR32:$dst, (bitconvert FR32:$src))],
5120 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
5121 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5122 "movd\t{$src, $dst|$dst, $src}",
5123 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5124 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5125 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5126 "movd\t{$src, $dst|$dst, $src}",
5127 [(set GR32:$dst, (bitconvert FR32:$src))],
5128 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5129 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5130 "movd\t{$src, $dst|$dst, $src}",
5131 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5132 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5135 //===---------------------------------------------------------------------===//
5136 // Patterns and instructions to describe movd/movq to XMM register zero-extends
5138 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
5139 let AddedComplexity = 15 in {
5140 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5141 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
5142 [(set VR128:$dst, (v2i64 (X86vzmovl
5143 (v2i64 (scalar_to_vector GR64:$src)))))],
5146 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5147 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
5148 [(set VR128:$dst, (v2i64 (X86vzmovl
5149 (v2i64 (scalar_to_vector GR64:$src)))))],
5152 } // isCodeGenOnly, SchedRW
5154 let Predicates = [UseAVX] in {
5155 let AddedComplexity = 15 in
5156 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5157 (VMOVDI2PDIrr GR32:$src)>;
5159 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
5160 let AddedComplexity = 20 in {
5161 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5162 (VMOVDI2PDIrm addr:$src)>;
5163 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5164 (VMOVDI2PDIrm addr:$src)>;
5165 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5166 (VMOVDI2PDIrm addr:$src)>;
5168 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
5169 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
5170 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
5171 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
5172 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5173 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
5174 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
5177 let Predicates = [UseSSE2] in {
5178 let AddedComplexity = 15 in
5179 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5180 (MOVDI2PDIrr GR32:$src)>;
5182 let AddedComplexity = 20 in {
5183 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5184 (MOVDI2PDIrm addr:$src)>;
5185 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5186 (MOVDI2PDIrm addr:$src)>;
5187 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5188 (MOVDI2PDIrm addr:$src)>;
5192 // These are the correct encodings of the instructions so that we know how to
5193 // read correct assembly, even though we continue to emit the wrong ones for
5194 // compatibility with Darwin's buggy assembler.
5195 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5196 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5197 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5198 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5199 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
5200 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5201 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5202 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5203 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5205 //===---------------------------------------------------------------------===//
5206 // SSE2 - Move Quadword
5207 //===---------------------------------------------------------------------===//
5209 //===---------------------------------------------------------------------===//
5210 // Move Quadword Int to Packed Quadword Int
5213 let SchedRW = [WriteLoad] in {
5214 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5215 "vmovq\t{$src, $dst|$dst, $src}",
5217 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
5218 VEX, Requires<[UseAVX]>;
5219 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5220 "movq\t{$src, $dst|$dst, $src}",
5222 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
5224 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
5227 //===---------------------------------------------------------------------===//
5228 // Move Packed Quadword Int to Quadword Int
5230 let SchedRW = [WriteStore] in {
5231 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5232 "movq\t{$src, $dst|$dst, $src}",
5233 [(store (i64 (vector_extract (v2i64 VR128:$src),
5234 (iPTR 0))), addr:$dst)],
5235 IIC_SSE_MOVDQ>, VEX;
5236 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5237 "movq\t{$src, $dst|$dst, $src}",
5238 [(store (i64 (vector_extract (v2i64 VR128:$src),
5239 (iPTR 0))), addr:$dst)],
5243 // For disassembler only
5244 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5245 SchedRW = [WriteVecLogic] in {
5246 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5247 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5248 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5249 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5252 //===---------------------------------------------------------------------===//
5253 // Store / copy lower 64-bits of a XMM register.
5255 let Predicates = [UseAVX] in
5256 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5257 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5258 let Predicates = [UseSSE2] in
5259 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5260 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5262 let isCodeGenOnly = 1, AddedComplexity = 20 in {
5263 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5264 "vmovq\t{$src, $dst|$dst, $src}",
5266 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5267 (loadi64 addr:$src))))))],
5269 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5271 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5272 "movq\t{$src, $dst|$dst, $src}",
5274 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5275 (loadi64 addr:$src))))))],
5277 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5280 let Predicates = [UseAVX], AddedComplexity = 20 in {
5281 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5282 (VMOVZQI2PQIrm addr:$src)>;
5283 def : Pat<(v2i64 (X86vzload addr:$src)),
5284 (VMOVZQI2PQIrm addr:$src)>;
5287 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5288 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5289 (MOVZQI2PQIrm addr:$src)>;
5290 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5293 let Predicates = [HasAVX] in {
5294 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5295 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5296 def : Pat<(v4i64 (X86vzload addr:$src)),
5297 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5300 //===---------------------------------------------------------------------===//
5301 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5302 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5304 let SchedRW = [WriteVecLogic] in {
5305 let AddedComplexity = 15 in
5306 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5307 "vmovq\t{$src, $dst|$dst, $src}",
5308 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5310 XS, VEX, Requires<[UseAVX]>;
5311 let AddedComplexity = 15 in
5312 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5313 "movq\t{$src, $dst|$dst, $src}",
5314 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5316 XS, Requires<[UseSSE2]>;
5319 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5320 let AddedComplexity = 20 in
5321 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5322 "vmovq\t{$src, $dst|$dst, $src}",
5323 [(set VR128:$dst, (v2i64 (X86vzmovl
5324 (loadv2i64 addr:$src))))],
5326 XS, VEX, Requires<[UseAVX]>;
5327 let AddedComplexity = 20 in {
5328 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5329 "movq\t{$src, $dst|$dst, $src}",
5330 [(set VR128:$dst, (v2i64 (X86vzmovl
5331 (loadv2i64 addr:$src))))],
5333 XS, Requires<[UseSSE2]>;
5335 } // isCodeGenOnly, SchedRW
5337 let AddedComplexity = 20 in {
5338 let Predicates = [UseAVX] in {
5339 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5340 (VMOVZPQILo2PQIrr VR128:$src)>;
5342 let Predicates = [UseSSE2] in {
5343 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5344 (MOVZPQILo2PQIrr VR128:$src)>;
5348 //===---------------------------------------------------------------------===//
5349 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5350 //===---------------------------------------------------------------------===//
5351 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5352 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5353 X86MemOperand x86memop> {
5354 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5355 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5356 [(set RC:$dst, (vt (OpNode RC:$src)))],
5357 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5358 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5359 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5360 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5361 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5364 let Predicates = [HasAVX] in {
5365 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5366 v4f32, VR128, loadv4f32, f128mem>, VEX;
5367 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5368 v4f32, VR128, loadv4f32, f128mem>, VEX;
5369 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5370 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5371 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5372 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5374 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5375 memopv4f32, f128mem>;
5376 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5377 memopv4f32, f128mem>;
5379 let Predicates = [HasAVX] in {
5380 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5381 (VMOVSHDUPrr VR128:$src)>;
5382 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5383 (VMOVSHDUPrm addr:$src)>;
5384 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5385 (VMOVSLDUPrr VR128:$src)>;
5386 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5387 (VMOVSLDUPrm addr:$src)>;
5388 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5389 (VMOVSHDUPYrr VR256:$src)>;
5390 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5391 (VMOVSHDUPYrm addr:$src)>;
5392 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5393 (VMOVSLDUPYrr VR256:$src)>;
5394 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5395 (VMOVSLDUPYrm addr:$src)>;
5398 let Predicates = [UseSSE3] in {
5399 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5400 (MOVSHDUPrr VR128:$src)>;
5401 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5402 (MOVSHDUPrm addr:$src)>;
5403 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5404 (MOVSLDUPrr VR128:$src)>;
5405 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5406 (MOVSLDUPrm addr:$src)>;
5409 //===---------------------------------------------------------------------===//
5410 // SSE3 - Replicate Double FP - MOVDDUP
5411 //===---------------------------------------------------------------------===//
5413 multiclass sse3_replicate_dfp<string OpcodeStr> {
5414 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5415 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5416 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5417 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5418 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5419 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5422 (scalar_to_vector (loadf64 addr:$src)))))],
5423 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5426 // FIXME: Merge with above classe when there're patterns for the ymm version
5427 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5428 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5429 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5430 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5431 Sched<[WriteFShuffle]>;
5432 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5433 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5436 (scalar_to_vector (loadf64 addr:$src)))))]>,
5440 let Predicates = [HasAVX] in {
5441 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5442 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5445 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5447 let Predicates = [HasAVX] in {
5448 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5449 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5450 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5451 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5452 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5453 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5454 def : Pat<(X86Movddup (bc_v2f64
5455 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5456 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5459 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5460 (VMOVDDUPYrm addr:$src)>;
5461 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5462 (VMOVDDUPYrm addr:$src)>;
5463 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5464 (VMOVDDUPYrm addr:$src)>;
5465 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5466 (VMOVDDUPYrr VR256:$src)>;
5469 let Predicates = [UseAVX, OptForSize] in {
5470 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5471 (VMOVDDUPrm addr:$src)>;
5472 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5473 (VMOVDDUPrm addr:$src)>;
5476 let Predicates = [UseSSE3] in {
5477 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5478 (MOVDDUPrm addr:$src)>;
5479 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5480 (MOVDDUPrm addr:$src)>;
5481 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5482 (MOVDDUPrm addr:$src)>;
5483 def : Pat<(X86Movddup (bc_v2f64
5484 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5485 (MOVDDUPrm addr:$src)>;
5488 //===---------------------------------------------------------------------===//
5489 // SSE3 - Move Unaligned Integer
5490 //===---------------------------------------------------------------------===//
5492 let SchedRW = [WriteLoad] in {
5493 let Predicates = [HasAVX] in {
5494 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5495 "vlddqu\t{$src, $dst|$dst, $src}",
5496 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5497 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5498 "vlddqu\t{$src, $dst|$dst, $src}",
5499 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5502 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5503 "lddqu\t{$src, $dst|$dst, $src}",
5504 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5508 //===---------------------------------------------------------------------===//
5509 // SSE3 - Arithmetic
5510 //===---------------------------------------------------------------------===//
5512 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5513 X86MemOperand x86memop, OpndItins itins,
5515 def rr : I<0xD0, MRMSrcReg,
5516 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5518 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5519 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5520 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5521 Sched<[itins.Sched]>;
5522 def rm : I<0xD0, MRMSrcMem,
5523 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5525 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5526 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5527 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5528 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5531 let Predicates = [HasAVX] in {
5532 let ExeDomain = SSEPackedSingle in {
5533 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5534 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5535 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5536 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5538 let ExeDomain = SSEPackedDouble in {
5539 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5540 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5541 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5542 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5545 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5546 let ExeDomain = SSEPackedSingle in
5547 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5548 f128mem, SSE_ALU_F32P>, XD;
5549 let ExeDomain = SSEPackedDouble in
5550 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5551 f128mem, SSE_ALU_F64P>, PD;
5554 // Patterns used to select 'addsub' instructions.
5555 let Predicates = [HasAVX] in {
5556 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5557 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5558 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5559 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5560 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5561 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5562 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5563 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5565 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5566 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5567 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 (memop addr:$rhs)))),
5568 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5569 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5570 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5571 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 (memop addr:$rhs)))),
5572 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5575 let Predicates = [UseSSE3] in {
5576 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5577 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5578 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5579 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5580 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5581 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5582 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5583 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5586 //===---------------------------------------------------------------------===//
5587 // SSE3 Instructions
5588 //===---------------------------------------------------------------------===//
5591 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5592 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5593 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5595 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5596 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5597 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5600 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5602 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5603 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5604 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5605 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5607 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5608 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5609 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5611 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5612 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5613 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5616 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5618 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5619 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5620 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5621 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5624 let Predicates = [HasAVX] in {
5625 let ExeDomain = SSEPackedSingle in {
5626 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5627 X86fhadd, 0>, VEX_4V;
5628 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5629 X86fhsub, 0>, VEX_4V;
5630 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5631 X86fhadd, 0>, VEX_4V, VEX_L;
5632 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5633 X86fhsub, 0>, VEX_4V, VEX_L;
5635 let ExeDomain = SSEPackedDouble in {
5636 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5637 X86fhadd, 0>, VEX_4V;
5638 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5639 X86fhsub, 0>, VEX_4V;
5640 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5641 X86fhadd, 0>, VEX_4V, VEX_L;
5642 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5643 X86fhsub, 0>, VEX_4V, VEX_L;
5647 let Constraints = "$src1 = $dst" in {
5648 let ExeDomain = SSEPackedSingle in {
5649 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5650 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5652 let ExeDomain = SSEPackedDouble in {
5653 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5654 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5658 //===---------------------------------------------------------------------===//
5659 // SSSE3 - Packed Absolute Instructions
5660 //===---------------------------------------------------------------------===//
5663 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5664 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5665 Intrinsic IntId128> {
5666 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5668 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5669 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5670 Sched<[WriteVecALU]>;
5672 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5674 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5677 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5678 Sched<[WriteVecALULd]>;
5681 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5682 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5683 Intrinsic IntId256> {
5684 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5686 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5687 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5688 Sched<[WriteVecALU]>;
5690 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5692 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5695 (bitconvert (memopv4i64 addr:$src))))]>,
5696 Sched<[WriteVecALULd]>;
5699 // Helper fragments to match sext vXi1 to vXiY.
5700 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5702 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5703 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5704 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5706 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5707 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5709 let Predicates = [HasAVX] in {
5710 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5711 int_x86_ssse3_pabs_b_128>, VEX;
5712 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5713 int_x86_ssse3_pabs_w_128>, VEX;
5714 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5715 int_x86_ssse3_pabs_d_128>, VEX;
5718 (bc_v2i64 (v16i1sextv16i8)),
5719 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5720 (VPABSBrr128 VR128:$src)>;
5722 (bc_v2i64 (v8i1sextv8i16)),
5723 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5724 (VPABSWrr128 VR128:$src)>;
5726 (bc_v2i64 (v4i1sextv4i32)),
5727 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5728 (VPABSDrr128 VR128:$src)>;
5731 let Predicates = [HasAVX2] in {
5732 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5733 int_x86_avx2_pabs_b>, VEX, VEX_L;
5734 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5735 int_x86_avx2_pabs_w>, VEX, VEX_L;
5736 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5737 int_x86_avx2_pabs_d>, VEX, VEX_L;
5740 (bc_v4i64 (v32i1sextv32i8)),
5741 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5742 (VPABSBrr256 VR256:$src)>;
5744 (bc_v4i64 (v16i1sextv16i16)),
5745 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5746 (VPABSWrr256 VR256:$src)>;
5748 (bc_v4i64 (v8i1sextv8i32)),
5749 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5750 (VPABSDrr256 VR256:$src)>;
5753 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5754 int_x86_ssse3_pabs_b_128>;
5755 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5756 int_x86_ssse3_pabs_w_128>;
5757 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5758 int_x86_ssse3_pabs_d_128>;
5760 let Predicates = [HasSSSE3] in {
5762 (bc_v2i64 (v16i1sextv16i8)),
5763 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5764 (PABSBrr128 VR128:$src)>;
5766 (bc_v2i64 (v8i1sextv8i16)),
5767 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5768 (PABSWrr128 VR128:$src)>;
5770 (bc_v2i64 (v4i1sextv4i32)),
5771 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5772 (PABSDrr128 VR128:$src)>;
5775 //===---------------------------------------------------------------------===//
5776 // SSSE3 - Packed Binary Operator Instructions
5777 //===---------------------------------------------------------------------===//
5779 let Sched = WriteVecALU in {
5780 def SSE_PHADDSUBD : OpndItins<
5781 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5783 def SSE_PHADDSUBSW : OpndItins<
5784 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5786 def SSE_PHADDSUBW : OpndItins<
5787 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5790 let Sched = WriteShuffle in
5791 def SSE_PSHUFB : OpndItins<
5792 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5794 let Sched = WriteVecALU in
5795 def SSE_PSIGN : OpndItins<
5796 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5798 let Sched = WriteVecIMul in
5799 def SSE_PMULHRSW : OpndItins<
5800 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5803 /// SS3I_binop_rm - Simple SSSE3 bin op
5804 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5805 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5806 X86MemOperand x86memop, OpndItins itins,
5808 let isCommutable = 1 in
5809 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5810 (ins RC:$src1, RC:$src2),
5812 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5813 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5814 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5815 Sched<[itins.Sched]>;
5816 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5817 (ins RC:$src1, x86memop:$src2),
5819 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5820 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5822 (OpVT (OpNode RC:$src1,
5823 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5824 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5827 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5828 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5829 Intrinsic IntId128, OpndItins itins,
5831 let isCommutable = 1 in
5832 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5833 (ins VR128:$src1, VR128:$src2),
5835 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5836 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5837 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5838 Sched<[itins.Sched]>;
5839 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5840 (ins VR128:$src1, i128mem:$src2),
5842 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5843 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5845 (IntId128 VR128:$src1,
5846 (bitconvert (memopv2i64 addr:$src2))))]>,
5847 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5850 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5852 X86FoldableSchedWrite Sched> {
5853 let isCommutable = 1 in
5854 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5855 (ins VR256:$src1, VR256:$src2),
5856 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5857 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5859 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5860 (ins VR256:$src1, i256mem:$src2),
5861 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5863 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5864 Sched<[Sched.Folded, ReadAfterLd]>;
5867 let ImmT = NoImm, Predicates = [HasAVX] in {
5868 let isCommutable = 0 in {
5869 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5871 SSE_PHADDSUBW, 0>, VEX_4V;
5872 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5874 SSE_PHADDSUBD, 0>, VEX_4V;
5875 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5877 SSE_PHADDSUBW, 0>, VEX_4V;
5878 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5880 SSE_PHADDSUBD, 0>, VEX_4V;
5881 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5883 SSE_PSIGN, 0>, VEX_4V;
5884 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5886 SSE_PSIGN, 0>, VEX_4V;
5887 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5889 SSE_PSIGN, 0>, VEX_4V;
5890 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5892 SSE_PSHUFB, 0>, VEX_4V;
5893 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5894 int_x86_ssse3_phadd_sw_128,
5895 SSE_PHADDSUBSW, 0>, VEX_4V;
5896 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5897 int_x86_ssse3_phsub_sw_128,
5898 SSE_PHADDSUBSW, 0>, VEX_4V;
5899 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5900 int_x86_ssse3_pmadd_ub_sw_128,
5901 SSE_PMADD, 0>, VEX_4V;
5903 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5904 int_x86_ssse3_pmul_hr_sw_128,
5905 SSE_PMULHRSW, 0>, VEX_4V;
5908 let ImmT = NoImm, Predicates = [HasAVX2] in {
5909 let isCommutable = 0 in {
5910 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5912 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5913 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5915 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5916 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5918 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5919 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5921 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5922 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5924 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5925 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5927 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5928 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5930 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5931 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5933 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5934 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5935 int_x86_avx2_phadd_sw,
5936 WriteVecALU>, VEX_4V, VEX_L;
5937 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5938 int_x86_avx2_phsub_sw,
5939 WriteVecALU>, VEX_4V, VEX_L;
5940 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5941 int_x86_avx2_pmadd_ub_sw,
5942 WriteVecIMul>, VEX_4V, VEX_L;
5944 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5945 int_x86_avx2_pmul_hr_sw,
5946 WriteVecIMul>, VEX_4V, VEX_L;
5949 // None of these have i8 immediate fields.
5950 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5951 let isCommutable = 0 in {
5952 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5953 memopv2i64, i128mem, SSE_PHADDSUBW>;
5954 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5955 memopv2i64, i128mem, SSE_PHADDSUBD>;
5956 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5957 memopv2i64, i128mem, SSE_PHADDSUBW>;
5958 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5959 memopv2i64, i128mem, SSE_PHADDSUBD>;
5960 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5961 memopv2i64, i128mem, SSE_PSIGN>;
5962 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5963 memopv2i64, i128mem, SSE_PSIGN>;
5964 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5965 memopv2i64, i128mem, SSE_PSIGN>;
5966 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5967 memopv2i64, i128mem, SSE_PSHUFB>;
5968 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5969 int_x86_ssse3_phadd_sw_128,
5971 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5972 int_x86_ssse3_phsub_sw_128,
5974 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5975 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5977 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5978 int_x86_ssse3_pmul_hr_sw_128,
5982 //===---------------------------------------------------------------------===//
5983 // SSSE3 - Packed Align Instruction Patterns
5984 //===---------------------------------------------------------------------===//
5986 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5987 let hasSideEffects = 0 in {
5988 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5989 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5991 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5993 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5994 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5996 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5997 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5999 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6001 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6002 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6006 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
6007 let hasSideEffects = 0 in {
6008 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
6009 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
6011 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6012 []>, Sched<[WriteShuffle]>;
6014 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
6015 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
6017 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6018 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6022 let Predicates = [HasAVX] in
6023 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
6024 let Predicates = [HasAVX2] in
6025 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
6026 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
6027 defm PALIGN : ssse3_palignr<"palignr">;
6029 let Predicates = [HasAVX2] in {
6030 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6031 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6032 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6033 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6034 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6035 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6036 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6037 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6040 let Predicates = [HasAVX] in {
6041 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6042 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6043 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6044 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6045 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6046 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6047 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6048 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6051 let Predicates = [UseSSSE3] in {
6052 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6053 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6054 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6055 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6056 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6057 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6058 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6059 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6062 //===---------------------------------------------------------------------===//
6063 // SSSE3 - Thread synchronization
6064 //===---------------------------------------------------------------------===//
6066 let SchedRW = [WriteSystem] in {
6067 let usesCustomInserter = 1 in {
6068 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
6069 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
6070 Requires<[HasSSE3]>;
6073 let Uses = [EAX, ECX, EDX] in
6074 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
6075 TB, Requires<[HasSSE3]>;
6076 let Uses = [ECX, EAX] in
6077 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
6078 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
6079 TB, Requires<[HasSSE3]>;
6082 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
6083 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
6085 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
6086 Requires<[Not64BitMode]>;
6087 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
6088 Requires<[In64BitMode]>;
6090 //===----------------------------------------------------------------------===//
6091 // SSE4.1 - Packed Move with Sign/Zero Extend
6092 //===----------------------------------------------------------------------===//
6094 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
6095 RegisterClass OutRC, RegisterClass InRC,
6097 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
6098 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6100 Sched<[itins.Sched]>;
6102 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
6103 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6105 itins.rm>, Sched<[itins.Sched.Folded]>;
6108 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
6109 X86MemOperand MemOp, X86MemOperand MemYOp,
6110 OpndItins SSEItins, OpndItins AVXItins,
6111 OpndItins AVX2Itins> {
6112 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
6113 let Predicates = [HasAVX] in
6114 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
6115 VR128, VR128, AVXItins>, VEX;
6116 let Predicates = [HasAVX2] in
6117 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
6118 VR256, VR128, AVX2Itins>, VEX, VEX_L;
6121 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
6122 X86MemOperand MemOp, X86MemOperand MemYOp> {
6123 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
6125 SSE_INTALU_ITINS_SHUFF_P,
6126 DEFAULT_ITINS_SHUFFLESCHED,
6127 DEFAULT_ITINS_SHUFFLESCHED>;
6128 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
6129 !strconcat("pmovzx", OpcodeStr),
6131 SSE_INTALU_ITINS_SHUFF_P,
6132 DEFAULT_ITINS_SHUFFLESCHED,
6133 DEFAULT_ITINS_SHUFFLESCHED>;
6136 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
6137 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
6138 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
6140 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
6141 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
6143 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
6146 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
6147 // Register-Register patterns
6148 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
6149 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
6150 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
6151 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
6152 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
6153 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
6155 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
6156 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
6157 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
6158 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
6160 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
6161 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
6163 // On AVX2, we also support 256bit inputs.
6164 // FIXME: remove these patterns when the old shuffle lowering goes away.
6165 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
6166 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6167 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
6168 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6169 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
6170 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6172 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
6173 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6174 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
6175 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6177 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
6178 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6180 // Simple Register-Memory patterns
6181 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6182 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6183 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6184 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6185 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6186 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6188 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6189 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6190 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6191 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6193 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6194 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6196 // AVX2 Register-Memory patterns
6197 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6198 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6199 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6200 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6201 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6202 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6203 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6204 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6206 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6207 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6208 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6209 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6210 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6211 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6212 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6213 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6215 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6216 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6217 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6218 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6219 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6220 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6221 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6222 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6224 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6225 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6226 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6227 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6228 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6229 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6230 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6231 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6233 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6234 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6235 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6236 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6237 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6238 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6239 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6240 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6242 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6243 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6244 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6245 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6246 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6247 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6248 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6249 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6252 let Predicates = [HasAVX2] in {
6253 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6254 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6257 // SSE4.1/AVX patterns.
6258 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6259 SDNode ExtOp, PatFrag ExtLoad16> {
6260 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6261 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6262 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6263 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6264 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6265 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6267 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6268 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6269 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6270 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6272 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6273 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6275 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6276 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6277 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6278 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6279 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6280 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6282 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6283 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6284 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6285 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6287 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6288 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6290 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6291 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6292 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6293 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6294 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6295 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6296 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6297 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6298 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6299 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6301 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6302 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6303 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6304 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6305 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6306 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6307 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6308 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6310 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6311 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6312 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6313 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6314 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6315 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6316 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6317 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6319 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6320 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6321 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6322 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6323 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6324 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6325 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6326 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6327 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6328 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6330 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6331 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6332 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6333 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6334 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6335 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6336 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6337 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6339 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6340 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6341 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6342 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6343 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6344 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6345 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6346 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6347 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6348 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6351 let Predicates = [HasAVX] in {
6352 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6353 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6356 let Predicates = [UseSSE41] in {
6357 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6358 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6361 //===----------------------------------------------------------------------===//
6362 // SSE4.1 - Extract Instructions
6363 //===----------------------------------------------------------------------===//
6365 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6366 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6367 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6368 (ins VR128:$src1, u8imm:$src2),
6369 !strconcat(OpcodeStr,
6370 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6371 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6373 Sched<[WriteShuffle]>;
6374 let hasSideEffects = 0, mayStore = 1,
6375 SchedRW = [WriteShuffleLd, WriteRMW] in
6376 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6377 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6378 !strconcat(OpcodeStr,
6379 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6380 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6381 imm:$src2)))), addr:$dst)]>;
6384 let Predicates = [HasAVX] in
6385 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6387 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6390 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6391 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6392 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6393 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6394 (ins VR128:$src1, u8imm:$src2),
6395 !strconcat(OpcodeStr,
6396 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6397 []>, Sched<[WriteShuffle]>;
6399 let hasSideEffects = 0, mayStore = 1,
6400 SchedRW = [WriteShuffleLd, WriteRMW] in
6401 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6402 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6403 !strconcat(OpcodeStr,
6404 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6405 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6406 imm:$src2)))), addr:$dst)]>;
6409 let Predicates = [HasAVX] in
6410 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6412 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6415 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6416 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6417 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6418 (ins VR128:$src1, u8imm:$src2),
6419 !strconcat(OpcodeStr,
6420 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6422 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6423 Sched<[WriteShuffle]>;
6424 let SchedRW = [WriteShuffleLd, WriteRMW] in
6425 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6426 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6427 !strconcat(OpcodeStr,
6428 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6429 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6433 let Predicates = [HasAVX] in
6434 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6436 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6438 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6439 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6440 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6441 (ins VR128:$src1, u8imm:$src2),
6442 !strconcat(OpcodeStr,
6443 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6445 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6446 Sched<[WriteShuffle]>, REX_W;
6447 let SchedRW = [WriteShuffleLd, WriteRMW] in
6448 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6449 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6450 !strconcat(OpcodeStr,
6451 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6452 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6453 addr:$dst)]>, REX_W;
6456 let Predicates = [HasAVX] in
6457 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6459 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6461 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6463 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6464 OpndItins itins = DEFAULT_ITINS> {
6465 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6466 (ins VR128:$src1, u8imm:$src2),
6467 !strconcat(OpcodeStr,
6468 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6469 [(set GR32orGR64:$dst,
6470 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6471 itins.rr>, Sched<[WriteFBlend]>;
6472 let SchedRW = [WriteFBlendLd, WriteRMW] in
6473 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6474 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6475 !strconcat(OpcodeStr,
6476 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6477 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6478 addr:$dst)], itins.rm>;
6481 let ExeDomain = SSEPackedSingle in {
6482 let Predicates = [UseAVX] in
6483 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6484 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6487 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6488 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6491 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6493 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6496 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6497 Requires<[UseSSE41]>;
6499 //===----------------------------------------------------------------------===//
6500 // SSE4.1 - Insert Instructions
6501 //===----------------------------------------------------------------------===//
6503 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6504 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6505 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6507 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6509 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6511 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6512 Sched<[WriteShuffle]>;
6513 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6514 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6516 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6518 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6520 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6521 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6524 let Predicates = [HasAVX] in
6525 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6526 let Constraints = "$src1 = $dst" in
6527 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6529 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6530 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6531 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6533 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6535 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6537 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6538 Sched<[WriteShuffle]>;
6539 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6540 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6542 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6544 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6546 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6547 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6550 let Predicates = [HasAVX] in
6551 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6552 let Constraints = "$src1 = $dst" in
6553 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6555 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6556 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6557 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6559 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6561 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6563 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6564 Sched<[WriteShuffle]>;
6565 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6566 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6568 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6570 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6572 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6573 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6576 let Predicates = [HasAVX] in
6577 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6578 let Constraints = "$src1 = $dst" in
6579 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6581 // insertps has a few different modes, there's the first two here below which
6582 // are optimized inserts that won't zero arbitrary elements in the destination
6583 // vector. The next one matches the intrinsic and could zero arbitrary elements
6584 // in the target vector.
6585 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6586 OpndItins itins = DEFAULT_ITINS> {
6587 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6588 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6590 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6592 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6594 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6595 Sched<[WriteFShuffle]>;
6596 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6597 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6599 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6601 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6603 (X86insertps VR128:$src1,
6604 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6605 imm:$src3))], itins.rm>,
6606 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6609 let ExeDomain = SSEPackedSingle in {
6610 let Predicates = [UseAVX] in
6611 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6612 let Constraints = "$src1 = $dst" in
6613 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6616 let Predicates = [UseSSE41] in {
6617 // If we're inserting an element from a load or a null pshuf of a load,
6618 // fold the load into the insertps instruction.
6619 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6620 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6622 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6623 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6624 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6625 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6628 let Predicates = [UseAVX] in {
6629 // If we're inserting an element from a vbroadcast of a load, fold the
6630 // load into the X86insertps instruction.
6631 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6632 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6633 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6634 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6635 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6636 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6639 //===----------------------------------------------------------------------===//
6640 // SSE4.1 - Round Instructions
6641 //===----------------------------------------------------------------------===//
6643 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6644 X86MemOperand x86memop, RegisterClass RC,
6645 PatFrag mem_frag32, PatFrag mem_frag64,
6646 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6647 let ExeDomain = SSEPackedSingle in {
6648 // Intrinsic operation, reg.
6649 // Vector intrinsic operation, reg
6650 def PSr : SS4AIi8<opcps, MRMSrcReg,
6651 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6652 !strconcat(OpcodeStr,
6653 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6654 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6655 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6657 // Vector intrinsic operation, mem
6658 def PSm : SS4AIi8<opcps, MRMSrcMem,
6659 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6660 !strconcat(OpcodeStr,
6661 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6663 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6664 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6665 } // ExeDomain = SSEPackedSingle
6667 let ExeDomain = SSEPackedDouble in {
6668 // Vector intrinsic operation, reg
6669 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6670 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6671 !strconcat(OpcodeStr,
6672 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6673 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6674 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6676 // Vector intrinsic operation, mem
6677 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6678 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6679 !strconcat(OpcodeStr,
6680 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6682 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6683 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6684 } // ExeDomain = SSEPackedDouble
6687 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6690 Intrinsic F64Int, bit Is2Addr = 1> {
6691 let ExeDomain = GenericDomain in {
6693 let hasSideEffects = 0 in
6694 def SSr : SS4AIi8<opcss, MRMSrcReg,
6695 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6697 !strconcat(OpcodeStr,
6698 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6699 !strconcat(OpcodeStr,
6700 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6701 []>, Sched<[WriteFAdd]>;
6703 // Intrinsic operation, reg.
6704 let isCodeGenOnly = 1 in
6705 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6706 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6708 !strconcat(OpcodeStr,
6709 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6710 !strconcat(OpcodeStr,
6711 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6712 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6715 // Intrinsic operation, mem.
6716 def SSm : SS4AIi8<opcss, MRMSrcMem,
6717 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6719 !strconcat(OpcodeStr,
6720 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6721 !strconcat(OpcodeStr,
6722 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6724 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6725 Sched<[WriteFAddLd, ReadAfterLd]>;
6728 let hasSideEffects = 0 in
6729 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6730 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6732 !strconcat(OpcodeStr,
6733 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6734 !strconcat(OpcodeStr,
6735 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6736 []>, Sched<[WriteFAdd]>;
6738 // Intrinsic operation, reg.
6739 let isCodeGenOnly = 1 in
6740 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6741 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6743 !strconcat(OpcodeStr,
6744 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6745 !strconcat(OpcodeStr,
6746 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6747 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6750 // Intrinsic operation, mem.
6751 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6752 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6754 !strconcat(OpcodeStr,
6755 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6756 !strconcat(OpcodeStr,
6757 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6759 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6760 Sched<[WriteFAddLd, ReadAfterLd]>;
6761 } // ExeDomain = GenericDomain
6764 // FP round - roundss, roundps, roundsd, roundpd
6765 let Predicates = [HasAVX] in {
6767 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6768 loadv4f32, loadv2f64,
6769 int_x86_sse41_round_ps,
6770 int_x86_sse41_round_pd>, VEX;
6771 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6772 loadv8f32, loadv4f64,
6773 int_x86_avx_round_ps_256,
6774 int_x86_avx_round_pd_256>, VEX, VEX_L;
6775 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6776 int_x86_sse41_round_ss,
6777 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6780 let Predicates = [UseAVX] in {
6781 def : Pat<(ffloor FR32:$src),
6782 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6783 def : Pat<(f64 (ffloor FR64:$src)),
6784 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6785 def : Pat<(f32 (fnearbyint FR32:$src)),
6786 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6787 def : Pat<(f64 (fnearbyint FR64:$src)),
6788 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6789 def : Pat<(f32 (fceil FR32:$src)),
6790 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6791 def : Pat<(f64 (fceil FR64:$src)),
6792 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6793 def : Pat<(f32 (frint FR32:$src)),
6794 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6795 def : Pat<(f64 (frint FR64:$src)),
6796 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6797 def : Pat<(f32 (ftrunc FR32:$src)),
6798 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6799 def : Pat<(f64 (ftrunc FR64:$src)),
6800 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6803 let Predicates = [HasAVX] in {
6804 def : Pat<(v4f32 (ffloor VR128:$src)),
6805 (VROUNDPSr VR128:$src, (i32 0x1))>;
6806 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6807 (VROUNDPSr VR128:$src, (i32 0xC))>;
6808 def : Pat<(v4f32 (fceil VR128:$src)),
6809 (VROUNDPSr VR128:$src, (i32 0x2))>;
6810 def : Pat<(v4f32 (frint VR128:$src)),
6811 (VROUNDPSr VR128:$src, (i32 0x4))>;
6812 def : Pat<(v4f32 (ftrunc VR128:$src)),
6813 (VROUNDPSr VR128:$src, (i32 0x3))>;
6815 def : Pat<(v2f64 (ffloor VR128:$src)),
6816 (VROUNDPDr VR128:$src, (i32 0x1))>;
6817 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6818 (VROUNDPDr VR128:$src, (i32 0xC))>;
6819 def : Pat<(v2f64 (fceil VR128:$src)),
6820 (VROUNDPDr VR128:$src, (i32 0x2))>;
6821 def : Pat<(v2f64 (frint VR128:$src)),
6822 (VROUNDPDr VR128:$src, (i32 0x4))>;
6823 def : Pat<(v2f64 (ftrunc VR128:$src)),
6824 (VROUNDPDr VR128:$src, (i32 0x3))>;
6826 def : Pat<(v8f32 (ffloor VR256:$src)),
6827 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6828 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6829 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6830 def : Pat<(v8f32 (fceil VR256:$src)),
6831 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6832 def : Pat<(v8f32 (frint VR256:$src)),
6833 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6834 def : Pat<(v8f32 (ftrunc VR256:$src)),
6835 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6837 def : Pat<(v4f64 (ffloor VR256:$src)),
6838 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6839 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6840 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6841 def : Pat<(v4f64 (fceil VR256:$src)),
6842 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6843 def : Pat<(v4f64 (frint VR256:$src)),
6844 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6845 def : Pat<(v4f64 (ftrunc VR256:$src)),
6846 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6849 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6850 memopv4f32, memopv2f64,
6851 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6852 let Constraints = "$src1 = $dst" in
6853 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6854 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6856 let Predicates = [UseSSE41] in {
6857 def : Pat<(ffloor FR32:$src),
6858 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6859 def : Pat<(f64 (ffloor FR64:$src)),
6860 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6861 def : Pat<(f32 (fnearbyint FR32:$src)),
6862 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6863 def : Pat<(f64 (fnearbyint FR64:$src)),
6864 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6865 def : Pat<(f32 (fceil FR32:$src)),
6866 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6867 def : Pat<(f64 (fceil FR64:$src)),
6868 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6869 def : Pat<(f32 (frint FR32:$src)),
6870 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6871 def : Pat<(f64 (frint FR64:$src)),
6872 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6873 def : Pat<(f32 (ftrunc FR32:$src)),
6874 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6875 def : Pat<(f64 (ftrunc FR64:$src)),
6876 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6878 def : Pat<(v4f32 (ffloor VR128:$src)),
6879 (ROUNDPSr VR128:$src, (i32 0x1))>;
6880 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6881 (ROUNDPSr VR128:$src, (i32 0xC))>;
6882 def : Pat<(v4f32 (fceil VR128:$src)),
6883 (ROUNDPSr VR128:$src, (i32 0x2))>;
6884 def : Pat<(v4f32 (frint VR128:$src)),
6885 (ROUNDPSr VR128:$src, (i32 0x4))>;
6886 def : Pat<(v4f32 (ftrunc VR128:$src)),
6887 (ROUNDPSr VR128:$src, (i32 0x3))>;
6889 def : Pat<(v2f64 (ffloor VR128:$src)),
6890 (ROUNDPDr VR128:$src, (i32 0x1))>;
6891 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6892 (ROUNDPDr VR128:$src, (i32 0xC))>;
6893 def : Pat<(v2f64 (fceil VR128:$src)),
6894 (ROUNDPDr VR128:$src, (i32 0x2))>;
6895 def : Pat<(v2f64 (frint VR128:$src)),
6896 (ROUNDPDr VR128:$src, (i32 0x4))>;
6897 def : Pat<(v2f64 (ftrunc VR128:$src)),
6898 (ROUNDPDr VR128:$src, (i32 0x3))>;
6901 //===----------------------------------------------------------------------===//
6902 // SSE4.1 - Packed Bit Test
6903 //===----------------------------------------------------------------------===//
6905 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6906 // the intel intrinsic that corresponds to this.
6907 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6908 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6909 "vptest\t{$src2, $src1|$src1, $src2}",
6910 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6911 Sched<[WriteVecLogic]>, VEX;
6912 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6913 "vptest\t{$src2, $src1|$src1, $src2}",
6914 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6915 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6917 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6918 "vptest\t{$src2, $src1|$src1, $src2}",
6919 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6920 Sched<[WriteVecLogic]>, VEX, VEX_L;
6921 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6922 "vptest\t{$src2, $src1|$src1, $src2}",
6923 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6924 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6927 let Defs = [EFLAGS] in {
6928 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6929 "ptest\t{$src2, $src1|$src1, $src2}",
6930 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6931 Sched<[WriteVecLogic]>;
6932 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6933 "ptest\t{$src2, $src1|$src1, $src2}",
6934 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6935 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6938 // The bit test instructions below are AVX only
6939 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6940 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6941 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6942 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6943 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6944 Sched<[WriteVecLogic]>, VEX;
6945 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6946 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6947 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6948 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6951 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6952 let ExeDomain = SSEPackedSingle in {
6953 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6954 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6957 let ExeDomain = SSEPackedDouble in {
6958 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6959 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6964 //===----------------------------------------------------------------------===//
6965 // SSE4.1 - Misc Instructions
6966 //===----------------------------------------------------------------------===//
6968 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6969 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6970 "popcnt{w}\t{$src, $dst|$dst, $src}",
6971 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6972 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6974 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6975 "popcnt{w}\t{$src, $dst|$dst, $src}",
6976 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6977 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6978 Sched<[WriteFAddLd]>, OpSize16, XS;
6980 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6981 "popcnt{l}\t{$src, $dst|$dst, $src}",
6982 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6983 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6986 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6987 "popcnt{l}\t{$src, $dst|$dst, $src}",
6988 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6989 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6990 Sched<[WriteFAddLd]>, OpSize32, XS;
6992 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6993 "popcnt{q}\t{$src, $dst|$dst, $src}",
6994 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6995 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6996 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6997 "popcnt{q}\t{$src, $dst|$dst, $src}",
6998 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6999 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7000 Sched<[WriteFAddLd]>, XS;
7005 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
7006 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
7008 X86FoldableSchedWrite Sched> {
7009 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7011 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7012 [(set VR128:$dst, (IntId128 VR128:$src))]>,
7014 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7016 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7018 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>,
7019 Sched<[Sched.Folded]>;
7022 // PHMIN has the same profile as PSAD, thus we use the same scheduling
7023 // model, although the naming is misleading.
7024 let Predicates = [HasAVX] in
7025 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
7026 int_x86_sse41_phminposuw,
7028 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
7029 int_x86_sse41_phminposuw,
7032 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
7033 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
7034 Intrinsic IntId128, bit Is2Addr = 1,
7035 OpndItins itins = DEFAULT_ITINS> {
7036 let isCommutable = 1 in
7037 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7038 (ins VR128:$src1, VR128:$src2),
7040 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7041 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7042 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
7043 itins.rr>, Sched<[itins.Sched]>;
7044 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7045 (ins VR128:$src1, i128mem:$src2),
7047 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7048 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7050 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
7051 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7054 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
7055 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
7057 X86FoldableSchedWrite Sched> {
7058 let isCommutable = 1 in
7059 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
7060 (ins VR256:$src1, VR256:$src2),
7061 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7062 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
7064 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
7065 (ins VR256:$src1, i256mem:$src2),
7066 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7068 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
7069 Sched<[Sched.Folded, ReadAfterLd]>;
7073 /// SS48I_binop_rm - Simple SSE41 binary operator.
7074 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7075 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7076 X86MemOperand x86memop, bit Is2Addr = 1,
7077 OpndItins itins = SSE_INTALU_ITINS_P> {
7078 let isCommutable = 1 in
7079 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7080 (ins RC:$src1, RC:$src2),
7082 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7083 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7084 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7085 Sched<[itins.Sched]>;
7086 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7087 (ins RC:$src1, x86memop:$src2),
7089 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7090 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7092 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
7093 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7096 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
7098 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
7099 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
7100 PatFrag memop_frag, X86MemOperand x86memop,
7102 bit IsCommutable = 0, bit Is2Addr = 1> {
7103 let isCommutable = IsCommutable in
7104 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7105 (ins RC:$src1, RC:$src2),
7107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7109 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
7110 Sched<[itins.Sched]>;
7111 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7112 (ins RC:$src1, x86memop:$src2),
7114 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7115 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7116 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
7117 (bitconvert (memop_frag addr:$src2)))))]>,
7118 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7121 let Predicates = [HasAVX, NoVLX] in {
7122 let isCommutable = 0 in
7123 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
7124 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7126 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
7127 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7129 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
7130 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7132 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
7133 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7135 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
7136 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7138 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
7139 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7141 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
7142 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7144 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
7145 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7147 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
7148 VR128, loadv2i64, i128mem,
7149 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
7152 let Predicates = [HasAVX2, NoVLX] in {
7153 let isCommutable = 0 in
7154 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
7155 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7157 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
7158 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7160 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
7161 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7163 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
7164 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7166 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
7167 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7169 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
7170 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7172 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
7173 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7175 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
7176 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7178 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
7179 VR256, loadv4i64, i256mem,
7180 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
7183 let Constraints = "$src1 = $dst" in {
7184 let isCommutable = 0 in
7185 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
7186 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7187 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
7188 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7189 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
7190 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7191 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
7192 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7193 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
7194 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7195 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
7196 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7197 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
7198 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7199 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7200 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7201 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
7202 VR128, memopv2i64, i128mem,
7203 SSE_INTMUL_ITINS_P, 1>;
7206 let Predicates = [HasAVX, NoVLX] in {
7207 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7208 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
7210 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7211 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7214 let Predicates = [HasAVX2] in {
7215 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7216 memopv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
7218 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7219 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7223 let Constraints = "$src1 = $dst" in {
7224 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7225 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7226 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7227 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7230 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7231 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7232 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7233 X86MemOperand x86memop, bit Is2Addr = 1,
7234 OpndItins itins = DEFAULT_ITINS> {
7235 let isCommutable = 1 in
7236 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7237 (ins RC:$src1, RC:$src2, u8imm:$src3),
7239 !strconcat(OpcodeStr,
7240 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7241 !strconcat(OpcodeStr,
7242 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7243 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7244 Sched<[itins.Sched]>;
7245 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7246 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
7248 !strconcat(OpcodeStr,
7249 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7250 !strconcat(OpcodeStr,
7251 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7254 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7255 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7258 let Predicates = [HasAVX] in {
7259 let isCommutable = 0 in {
7260 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7261 VR128, loadv2i64, i128mem, 0,
7262 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7265 let ExeDomain = SSEPackedSingle in {
7266 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7267 VR128, loadv4f32, f128mem, 0,
7268 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7269 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7270 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7271 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7274 let ExeDomain = SSEPackedDouble in {
7275 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7276 VR128, loadv2f64, f128mem, 0,
7277 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7278 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7279 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7280 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7283 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7284 VR128, loadv2i64, i128mem, 0,
7285 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7287 let ExeDomain = SSEPackedSingle in
7288 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7289 VR128, loadv4f32, f128mem, 0,
7290 SSE_DPPS_ITINS>, VEX_4V;
7291 let ExeDomain = SSEPackedDouble in
7292 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7293 VR128, loadv2f64, f128mem, 0,
7294 SSE_DPPS_ITINS>, VEX_4V;
7295 let ExeDomain = SSEPackedSingle in
7296 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7297 VR256, loadv8f32, i256mem, 0,
7298 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7301 let Predicates = [HasAVX2] in {
7302 let isCommutable = 0 in {
7303 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7304 VR256, loadv4i64, i256mem, 0,
7305 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7307 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7308 VR256, loadv4i64, i256mem, 0,
7309 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7312 let Constraints = "$src1 = $dst" in {
7313 let isCommutable = 0 in {
7314 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7315 VR128, memopv2i64, i128mem,
7316 1, SSE_MPSADBW_ITINS>;
7318 let ExeDomain = SSEPackedSingle in
7319 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7320 VR128, memopv4f32, f128mem,
7321 1, SSE_INTALU_ITINS_FBLEND_P>;
7322 let ExeDomain = SSEPackedDouble in
7323 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7324 VR128, memopv2f64, f128mem,
7325 1, SSE_INTALU_ITINS_FBLEND_P>;
7326 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7327 VR128, memopv2i64, i128mem,
7328 1, SSE_INTALU_ITINS_BLEND_P>;
7329 let ExeDomain = SSEPackedSingle in
7330 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7331 VR128, memopv4f32, f128mem, 1,
7333 let ExeDomain = SSEPackedDouble in
7334 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7335 VR128, memopv2f64, f128mem, 1,
7339 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7340 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7341 RegisterClass RC, X86MemOperand x86memop,
7342 PatFrag mem_frag, Intrinsic IntId,
7343 X86FoldableSchedWrite Sched> {
7344 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7345 (ins RC:$src1, RC:$src2, RC:$src3),
7346 !strconcat(OpcodeStr,
7347 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7348 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7349 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7352 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7353 (ins RC:$src1, x86memop:$src2, RC:$src3),
7354 !strconcat(OpcodeStr,
7355 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7357 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7359 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7360 Sched<[Sched.Folded, ReadAfterLd]>;
7363 let Predicates = [HasAVX] in {
7364 let ExeDomain = SSEPackedDouble in {
7365 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7366 loadv2f64, int_x86_sse41_blendvpd,
7368 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7369 loadv4f64, int_x86_avx_blendv_pd_256,
7370 WriteFVarBlend>, VEX_L;
7371 } // ExeDomain = SSEPackedDouble
7372 let ExeDomain = SSEPackedSingle in {
7373 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7374 loadv4f32, int_x86_sse41_blendvps,
7376 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7377 loadv8f32, int_x86_avx_blendv_ps_256,
7378 WriteFVarBlend>, VEX_L;
7379 } // ExeDomain = SSEPackedSingle
7380 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7381 loadv2i64, int_x86_sse41_pblendvb,
7385 let Predicates = [HasAVX2] in {
7386 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7387 loadv4i64, int_x86_avx2_pblendvb,
7388 WriteVarBlend>, VEX_L;
7391 let Predicates = [HasAVX] in {
7392 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7393 (v16i8 VR128:$src2))),
7394 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7395 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7396 (v4i32 VR128:$src2))),
7397 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7398 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7399 (v4f32 VR128:$src2))),
7400 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7401 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7402 (v2i64 VR128:$src2))),
7403 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7404 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7405 (v2f64 VR128:$src2))),
7406 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7407 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7408 (v8i32 VR256:$src2))),
7409 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7410 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7411 (v8f32 VR256:$src2))),
7412 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7413 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7414 (v4i64 VR256:$src2))),
7415 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7416 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7417 (v4f64 VR256:$src2))),
7418 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7420 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7422 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7423 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7425 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7427 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7429 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7430 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7432 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7433 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7435 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7438 let Predicates = [HasAVX2] in {
7439 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7440 (v32i8 VR256:$src2))),
7441 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7442 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7444 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7448 let Predicates = [UseAVX] in {
7449 let AddedComplexity = 15 in {
7450 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7451 // MOVS{S,D} to the lower bits.
7452 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7453 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7454 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7455 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7456 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7457 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7458 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7459 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7461 // Move low f32 and clear high bits.
7462 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7463 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7464 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7465 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7468 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7469 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7470 (SUBREG_TO_REG (i32 0),
7471 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7473 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7474 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7475 (SUBREG_TO_REG (i64 0),
7476 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7479 // Move low f64 and clear high bits.
7480 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7481 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7483 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7484 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7487 let Predicates = [UseSSE41] in {
7488 // With SSE41 we can use blends for these patterns.
7489 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7490 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7491 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7492 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7493 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7494 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7498 /// SS41I_ternary_int - SSE 4.1 ternary operator
7499 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7500 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7501 X86MemOperand x86memop, Intrinsic IntId,
7502 OpndItins itins = DEFAULT_ITINS> {
7503 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7504 (ins VR128:$src1, VR128:$src2),
7505 !strconcat(OpcodeStr,
7506 "\t{$src2, $dst|$dst, $src2}"),
7507 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7508 itins.rr>, Sched<[itins.Sched]>;
7510 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7511 (ins VR128:$src1, x86memop:$src2),
7512 !strconcat(OpcodeStr,
7513 "\t{$src2, $dst|$dst, $src2}"),
7516 (bitconvert (mem_frag addr:$src2)), XMM0))],
7517 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7521 let ExeDomain = SSEPackedDouble in
7522 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7523 int_x86_sse41_blendvpd,
7524 DEFAULT_ITINS_FBLENDSCHED>;
7525 let ExeDomain = SSEPackedSingle in
7526 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7527 int_x86_sse41_blendvps,
7528 DEFAULT_ITINS_FBLENDSCHED>;
7529 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7530 int_x86_sse41_pblendvb,
7531 DEFAULT_ITINS_VARBLENDSCHED>;
7533 // Aliases with the implicit xmm0 argument
7534 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7535 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7536 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7537 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7538 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7539 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7540 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7541 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7542 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7543 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7544 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7545 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7547 let Predicates = [UseSSE41] in {
7548 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7549 (v16i8 VR128:$src2))),
7550 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7551 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7552 (v4i32 VR128:$src2))),
7553 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7554 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7555 (v4f32 VR128:$src2))),
7556 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7557 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7558 (v2i64 VR128:$src2))),
7559 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7560 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7561 (v2f64 VR128:$src2))),
7562 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7564 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7566 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7567 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7569 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7570 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7572 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7576 let SchedRW = [WriteLoad] in {
7577 let Predicates = [HasAVX] in
7578 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7579 "vmovntdqa\t{$src, $dst|$dst, $src}",
7580 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7582 let Predicates = [HasAVX2] in
7583 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7584 "vmovntdqa\t{$src, $dst|$dst, $src}",
7585 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7587 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7588 "movntdqa\t{$src, $dst|$dst, $src}",
7589 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7592 //===----------------------------------------------------------------------===//
7593 // SSE4.2 - Compare Instructions
7594 //===----------------------------------------------------------------------===//
7596 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7597 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7598 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7599 X86MemOperand x86memop, bit Is2Addr = 1> {
7600 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7601 (ins RC:$src1, RC:$src2),
7603 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7604 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7605 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7606 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7607 (ins RC:$src1, x86memop:$src2),
7609 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7610 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7612 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7615 let Predicates = [HasAVX] in
7616 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7617 loadv2i64, i128mem, 0>, VEX_4V;
7619 let Predicates = [HasAVX2] in
7620 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7621 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7623 let Constraints = "$src1 = $dst" in
7624 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7625 memopv2i64, i128mem>;
7627 //===----------------------------------------------------------------------===//
7628 // SSE4.2 - String/text Processing Instructions
7629 //===----------------------------------------------------------------------===//
7631 // Packed Compare Implicit Length Strings, Return Mask
7632 multiclass pseudo_pcmpistrm<string asm> {
7633 def REG : PseudoI<(outs VR128:$dst),
7634 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7635 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7637 def MEM : PseudoI<(outs VR128:$dst),
7638 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7639 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7640 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7643 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7644 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7645 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7648 multiclass pcmpistrm_SS42AI<string asm> {
7649 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7650 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7651 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7652 []>, Sched<[WritePCmpIStrM]>;
7654 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7655 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7656 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7657 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7660 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7661 let Predicates = [HasAVX] in
7662 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7663 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7666 // Packed Compare Explicit Length Strings, Return Mask
7667 multiclass pseudo_pcmpestrm<string asm> {
7668 def REG : PseudoI<(outs VR128:$dst),
7669 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7670 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7671 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7672 def MEM : PseudoI<(outs VR128:$dst),
7673 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7674 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7675 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7678 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7679 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7680 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7683 multiclass SS42AI_pcmpestrm<string asm> {
7684 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7685 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7686 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7687 []>, Sched<[WritePCmpEStrM]>;
7689 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7690 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7691 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7692 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7695 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7696 let Predicates = [HasAVX] in
7697 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7698 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7701 // Packed Compare Implicit Length Strings, Return Index
7702 multiclass pseudo_pcmpistri<string asm> {
7703 def REG : PseudoI<(outs GR32:$dst),
7704 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7705 [(set GR32:$dst, EFLAGS,
7706 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7707 def MEM : PseudoI<(outs GR32:$dst),
7708 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7709 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7710 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7713 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7714 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7715 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7718 multiclass SS42AI_pcmpistri<string asm> {
7719 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7720 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7721 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7722 []>, Sched<[WritePCmpIStrI]>;
7724 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7725 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7726 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7727 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7730 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7731 let Predicates = [HasAVX] in
7732 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7733 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7736 // Packed Compare Explicit Length Strings, Return Index
7737 multiclass pseudo_pcmpestri<string asm> {
7738 def REG : PseudoI<(outs GR32:$dst),
7739 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7740 [(set GR32:$dst, EFLAGS,
7741 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7742 def MEM : PseudoI<(outs GR32:$dst),
7743 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7744 [(set GR32:$dst, EFLAGS,
7745 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7749 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7750 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7751 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7754 multiclass SS42AI_pcmpestri<string asm> {
7755 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7756 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7757 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7758 []>, Sched<[WritePCmpEStrI]>;
7760 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7761 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7762 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7763 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7766 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7767 let Predicates = [HasAVX] in
7768 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7769 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7772 //===----------------------------------------------------------------------===//
7773 // SSE4.2 - CRC Instructions
7774 //===----------------------------------------------------------------------===//
7776 // No CRC instructions have AVX equivalents
7778 // crc intrinsic instruction
7779 // This set of instructions are only rm, the only difference is the size
7781 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7782 RegisterClass RCIn, SDPatternOperator Int> :
7783 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7784 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7785 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7788 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7789 X86MemOperand x86memop, SDPatternOperator Int> :
7790 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7791 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7792 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7793 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7795 let Constraints = "$src1 = $dst" in {
7796 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7797 int_x86_sse42_crc32_32_8>;
7798 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7799 int_x86_sse42_crc32_32_8>;
7800 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7801 int_x86_sse42_crc32_32_16>, OpSize16;
7802 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7803 int_x86_sse42_crc32_32_16>, OpSize16;
7804 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7805 int_x86_sse42_crc32_32_32>, OpSize32;
7806 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7807 int_x86_sse42_crc32_32_32>, OpSize32;
7808 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7809 int_x86_sse42_crc32_64_64>, REX_W;
7810 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7811 int_x86_sse42_crc32_64_64>, REX_W;
7812 let hasSideEffects = 0 in {
7814 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7816 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7821 //===----------------------------------------------------------------------===//
7822 // SHA-NI Instructions
7823 //===----------------------------------------------------------------------===//
7825 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7827 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7828 (ins VR128:$src1, VR128:$src2),
7829 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7831 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7832 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7834 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7835 (ins VR128:$src1, i128mem:$src2),
7836 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7838 (set VR128:$dst, (IntId VR128:$src1,
7839 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7840 (set VR128:$dst, (IntId VR128:$src1,
7841 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7844 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7845 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7846 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7847 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7849 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7850 (i8 imm:$src3)))]>, TA;
7851 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7852 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7853 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7855 (int_x86_sha1rnds4 VR128:$src1,
7856 (bc_v4i32 (memopv2i64 addr:$src2)),
7857 (i8 imm:$src3)))]>, TA;
7859 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7860 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7861 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7864 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7866 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7867 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7870 // Aliases with explicit %xmm0
7871 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7872 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7873 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7874 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7876 //===----------------------------------------------------------------------===//
7877 // AES-NI Instructions
7878 //===----------------------------------------------------------------------===//
7880 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7881 Intrinsic IntId128, bit Is2Addr = 1> {
7882 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7883 (ins VR128:$src1, VR128:$src2),
7885 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7886 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7887 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7888 Sched<[WriteAESDecEnc]>;
7889 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7890 (ins VR128:$src1, i128mem:$src2),
7892 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7893 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7895 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
7896 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7899 // Perform One Round of an AES Encryption/Decryption Flow
7900 let Predicates = [HasAVX, HasAES] in {
7901 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7902 int_x86_aesni_aesenc, 0>, VEX_4V;
7903 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7904 int_x86_aesni_aesenclast, 0>, VEX_4V;
7905 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7906 int_x86_aesni_aesdec, 0>, VEX_4V;
7907 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7908 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7911 let Constraints = "$src1 = $dst" in {
7912 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7913 int_x86_aesni_aesenc>;
7914 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7915 int_x86_aesni_aesenclast>;
7916 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7917 int_x86_aesni_aesdec>;
7918 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7919 int_x86_aesni_aesdeclast>;
7922 // Perform the AES InvMixColumn Transformation
7923 let Predicates = [HasAVX, HasAES] in {
7924 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7926 "vaesimc\t{$src1, $dst|$dst, $src1}",
7928 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7930 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7931 (ins i128mem:$src1),
7932 "vaesimc\t{$src1, $dst|$dst, $src1}",
7933 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7934 Sched<[WriteAESIMCLd]>, VEX;
7936 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7938 "aesimc\t{$src1, $dst|$dst, $src1}",
7940 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7941 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7942 (ins i128mem:$src1),
7943 "aesimc\t{$src1, $dst|$dst, $src1}",
7944 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7945 Sched<[WriteAESIMCLd]>;
7947 // AES Round Key Generation Assist
7948 let Predicates = [HasAVX, HasAES] in {
7949 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7950 (ins VR128:$src1, u8imm:$src2),
7951 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7953 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7954 Sched<[WriteAESKeyGen]>, VEX;
7955 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7956 (ins i128mem:$src1, u8imm:$src2),
7957 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7959 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7960 Sched<[WriteAESKeyGenLd]>, VEX;
7962 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7963 (ins VR128:$src1, u8imm:$src2),
7964 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7966 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7967 Sched<[WriteAESKeyGen]>;
7968 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7969 (ins i128mem:$src1, u8imm:$src2),
7970 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7972 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7973 Sched<[WriteAESKeyGenLd]>;
7975 //===----------------------------------------------------------------------===//
7976 // PCLMUL Instructions
7977 //===----------------------------------------------------------------------===//
7979 // AVX carry-less Multiplication instructions
7980 let isCommutable = 1 in
7981 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7982 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7983 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7985 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7986 Sched<[WriteCLMul]>;
7988 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7989 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7990 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7991 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7992 (loadv2i64 addr:$src2), imm:$src3))]>,
7993 Sched<[WriteCLMulLd, ReadAfterLd]>;
7995 // Carry-less Multiplication instructions
7996 let Constraints = "$src1 = $dst" in {
7997 let isCommutable = 1 in
7998 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7999 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
8000 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8002 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
8003 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
8005 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8006 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
8007 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8008 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8009 (memopv2i64 addr:$src2), imm:$src3))],
8010 IIC_SSE_PCLMULQDQ_RM>,
8011 Sched<[WriteCLMulLd, ReadAfterLd]>;
8012 } // Constraints = "$src1 = $dst"
8015 multiclass pclmul_alias<string asm, int immop> {
8016 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8017 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
8019 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8020 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
8022 def : InstAlias<!strconcat("vpclmul", asm,
8023 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8024 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
8027 def : InstAlias<!strconcat("vpclmul", asm,
8028 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8029 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
8032 defm : pclmul_alias<"hqhq", 0x11>;
8033 defm : pclmul_alias<"hqlq", 0x01>;
8034 defm : pclmul_alias<"lqhq", 0x10>;
8035 defm : pclmul_alias<"lqlq", 0x00>;
8037 //===----------------------------------------------------------------------===//
8038 // SSE4A Instructions
8039 //===----------------------------------------------------------------------===//
8041 let Predicates = [HasSSE4A] in {
8043 let Constraints = "$src = $dst" in {
8044 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
8045 (ins VR128:$src, u8imm:$len, u8imm:$idx),
8046 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
8047 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
8049 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8050 (ins VR128:$src, VR128:$mask),
8051 "extrq\t{$mask, $src|$src, $mask}",
8052 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
8053 VR128:$mask))]>, PD;
8055 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
8056 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
8057 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
8058 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
8059 VR128:$src2, imm:$len, imm:$idx))]>, XD;
8060 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8061 (ins VR128:$src, VR128:$mask),
8062 "insertq\t{$mask, $src|$src, $mask}",
8063 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
8064 VR128:$mask))]>, XD;
8067 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
8068 "movntss\t{$src, $dst|$dst, $src}",
8069 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
8071 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
8072 "movntsd\t{$src, $dst|$dst, $src}",
8073 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
8076 //===----------------------------------------------------------------------===//
8078 //===----------------------------------------------------------------------===//
8080 //===----------------------------------------------------------------------===//
8081 // VBROADCAST - Load from memory and broadcast to all elements of the
8082 // destination operand
8084 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
8085 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
8086 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8087 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8088 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
8090 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
8091 X86MemOperand x86memop, ValueType VT,
8092 PatFrag ld_frag, SchedWrite Sched> :
8093 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8094 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8095 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
8096 Sched<[Sched]>, VEX {
8100 // AVX2 adds register forms
8101 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
8102 Intrinsic Int, SchedWrite Sched> :
8103 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8104 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8105 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
8107 let ExeDomain = SSEPackedSingle in {
8108 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
8109 f32mem, v4f32, loadf32, WriteLoad>;
8110 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
8111 f32mem, v8f32, loadf32,
8112 WriteFShuffleLd>, VEX_L;
8114 let ExeDomain = SSEPackedDouble in
8115 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
8116 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
8117 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
8118 int_x86_avx_vbroadcastf128_pd_256,
8119 WriteFShuffleLd>, VEX_L;
8121 let ExeDomain = SSEPackedSingle in {
8122 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
8123 int_x86_avx2_vbroadcast_ss_ps,
8125 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
8126 int_x86_avx2_vbroadcast_ss_ps_256,
8127 WriteFShuffle256>, VEX_L;
8129 let ExeDomain = SSEPackedDouble in
8130 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
8131 int_x86_avx2_vbroadcast_sd_pd_256,
8132 WriteFShuffle256>, VEX_L;
8134 let Predicates = [HasAVX2] in
8135 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
8136 int_x86_avx2_vbroadcasti128, WriteLoad>,
8139 let Predicates = [HasAVX] in
8140 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
8141 (VBROADCASTF128 addr:$src)>;
8144 //===----------------------------------------------------------------------===//
8145 // VINSERTF128 - Insert packed floating-point values
8147 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8148 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8149 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8150 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8151 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
8153 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
8154 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
8155 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8156 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
8159 let Predicates = [HasAVX] in {
8160 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
8162 (VINSERTF128rr VR256:$src1, VR128:$src2,
8163 (INSERT_get_vinsert128_imm VR256:$ins))>;
8164 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
8166 (VINSERTF128rr VR256:$src1, VR128:$src2,
8167 (INSERT_get_vinsert128_imm VR256:$ins))>;
8169 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
8171 (VINSERTF128rm VR256:$src1, addr:$src2,
8172 (INSERT_get_vinsert128_imm VR256:$ins))>;
8173 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
8175 (VINSERTF128rm VR256:$src1, addr:$src2,
8176 (INSERT_get_vinsert128_imm VR256:$ins))>;
8179 let Predicates = [HasAVX1Only] in {
8180 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8182 (VINSERTF128rr VR256:$src1, VR128:$src2,
8183 (INSERT_get_vinsert128_imm VR256:$ins))>;
8184 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8186 (VINSERTF128rr VR256:$src1, VR128:$src2,
8187 (INSERT_get_vinsert128_imm VR256:$ins))>;
8188 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8190 (VINSERTF128rr VR256:$src1, VR128:$src2,
8191 (INSERT_get_vinsert128_imm VR256:$ins))>;
8192 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8194 (VINSERTF128rr VR256:$src1, VR128:$src2,
8195 (INSERT_get_vinsert128_imm VR256:$ins))>;
8197 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8199 (VINSERTF128rm VR256:$src1, addr:$src2,
8200 (INSERT_get_vinsert128_imm VR256:$ins))>;
8201 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8202 (bc_v4i32 (loadv2i64 addr:$src2)),
8204 (VINSERTF128rm VR256:$src1, addr:$src2,
8205 (INSERT_get_vinsert128_imm VR256:$ins))>;
8206 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8207 (bc_v16i8 (loadv2i64 addr:$src2)),
8209 (VINSERTF128rm VR256:$src1, addr:$src2,
8210 (INSERT_get_vinsert128_imm VR256:$ins))>;
8211 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8212 (bc_v8i16 (loadv2i64 addr:$src2)),
8214 (VINSERTF128rm VR256:$src1, addr:$src2,
8215 (INSERT_get_vinsert128_imm VR256:$ins))>;
8218 //===----------------------------------------------------------------------===//
8219 // VEXTRACTF128 - Extract packed floating-point values
8221 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8222 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
8223 (ins VR256:$src1, u8imm:$src2),
8224 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8225 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
8227 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
8228 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
8229 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8230 []>, Sched<[WriteStore]>, VEX, VEX_L;
8234 let Predicates = [HasAVX] in {
8235 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8236 (v4f32 (VEXTRACTF128rr
8237 (v8f32 VR256:$src1),
8238 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8239 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8240 (v2f64 (VEXTRACTF128rr
8241 (v4f64 VR256:$src1),
8242 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8244 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
8245 (iPTR imm))), addr:$dst),
8246 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8247 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8248 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
8249 (iPTR imm))), addr:$dst),
8250 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8251 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8254 let Predicates = [HasAVX1Only] in {
8255 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8256 (v2i64 (VEXTRACTF128rr
8257 (v4i64 VR256:$src1),
8258 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8259 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8260 (v4i32 (VEXTRACTF128rr
8261 (v8i32 VR256:$src1),
8262 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8263 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8264 (v8i16 (VEXTRACTF128rr
8265 (v16i16 VR256:$src1),
8266 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8267 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8268 (v16i8 (VEXTRACTF128rr
8269 (v32i8 VR256:$src1),
8270 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8272 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8273 (iPTR imm))), addr:$dst),
8274 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8275 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8276 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8277 (iPTR imm))), addr:$dst),
8278 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8279 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8280 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8281 (iPTR imm))), addr:$dst),
8282 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8283 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8284 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8285 (iPTR imm))), addr:$dst),
8286 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8287 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8290 //===----------------------------------------------------------------------===//
8291 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8293 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8294 Intrinsic IntLd, Intrinsic IntLd256,
8295 Intrinsic IntSt, Intrinsic IntSt256> {
8296 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8297 (ins VR128:$src1, f128mem:$src2),
8298 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8299 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8301 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8302 (ins VR256:$src1, f256mem:$src2),
8303 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8304 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8306 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8307 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8308 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8309 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8310 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8311 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8312 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8313 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8316 let ExeDomain = SSEPackedSingle in
8317 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8318 int_x86_avx_maskload_ps,
8319 int_x86_avx_maskload_ps_256,
8320 int_x86_avx_maskstore_ps,
8321 int_x86_avx_maskstore_ps_256>;
8322 let ExeDomain = SSEPackedDouble in
8323 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8324 int_x86_avx_maskload_pd,
8325 int_x86_avx_maskload_pd_256,
8326 int_x86_avx_maskstore_pd,
8327 int_x86_avx_maskstore_pd_256>;
8329 //===----------------------------------------------------------------------===//
8330 // VPERMIL - Permute Single and Double Floating-Point Values
8332 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8333 RegisterClass RC, X86MemOperand x86memop_f,
8334 X86MemOperand x86memop_i, PatFrag i_frag,
8335 Intrinsic IntVar, ValueType vt> {
8336 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8337 (ins RC:$src1, RC:$src2),
8338 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8339 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8340 Sched<[WriteFShuffle]>;
8341 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8342 (ins RC:$src1, x86memop_i:$src2),
8343 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8344 [(set RC:$dst, (IntVar RC:$src1,
8345 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8346 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8348 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8349 (ins RC:$src1, u8imm:$src2),
8350 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8351 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8352 Sched<[WriteFShuffle]>;
8353 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8354 (ins x86memop_f:$src1, u8imm:$src2),
8355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8357 (vt (X86VPermilpi (memop addr:$src1), (i8 imm:$src2))))]>, VEX,
8358 Sched<[WriteFShuffleLd]>;
8361 let ExeDomain = SSEPackedSingle in {
8362 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8363 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8364 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8365 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8367 let ExeDomain = SSEPackedDouble in {
8368 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8369 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8370 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8371 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8374 let Predicates = [HasAVX] in {
8375 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8376 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8377 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8378 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8379 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8380 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8381 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8382 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8384 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8385 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8386 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8387 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8388 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8390 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8391 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8392 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8394 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8395 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8396 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8397 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8398 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8399 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8400 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8401 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8403 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8404 (VPERMILPDri VR128:$src1, imm:$imm)>;
8405 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8406 (VPERMILPDmi addr:$src1, imm:$imm)>;
8409 //===----------------------------------------------------------------------===//
8410 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8412 let ExeDomain = SSEPackedSingle in {
8413 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8414 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8415 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8416 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8417 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8418 Sched<[WriteFShuffle]>;
8419 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8420 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8421 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8422 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8423 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8424 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8427 let Predicates = [HasAVX] in {
8428 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8429 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8430 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8431 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8432 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8435 let Predicates = [HasAVX1Only] in {
8436 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8437 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8438 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8439 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8440 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8441 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8442 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8443 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8445 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8446 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8447 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8448 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8449 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8450 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8451 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8452 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8453 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8454 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8455 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8456 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8459 //===----------------------------------------------------------------------===//
8460 // VZERO - Zero YMM registers
8462 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8463 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8464 // Zero All YMM registers
8465 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8466 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8468 // Zero Upper bits of YMM registers
8469 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8470 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8473 //===----------------------------------------------------------------------===//
8474 // Half precision conversion instructions
8475 //===----------------------------------------------------------------------===//
8476 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8477 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8478 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8479 [(set RC:$dst, (Int VR128:$src))]>,
8480 T8PD, VEX, Sched<[WriteCvtF2F]>;
8481 let hasSideEffects = 0, mayLoad = 1 in
8482 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8483 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8484 Sched<[WriteCvtF2FLd]>;
8487 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8488 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8489 (ins RC:$src1, i32u8imm:$src2),
8490 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8491 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8492 TAPD, VEX, Sched<[WriteCvtF2F]>;
8493 let hasSideEffects = 0, mayStore = 1,
8494 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8495 def mr : Ii8<0x1D, MRMDestMem, (outs),
8496 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8497 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8501 let Predicates = [HasF16C] in {
8502 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8503 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8504 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8505 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8507 // Pattern match vcvtph2ps of a scalar i64 load.
8508 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8509 (VCVTPH2PSrm addr:$src)>;
8510 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8511 (VCVTPH2PSrm addr:$src)>;
8514 // Patterns for matching conversions from float to half-float and vice versa.
8515 let Predicates = [HasF16C] in {
8516 def : Pat<(fp_to_f16 FR32:$src),
8517 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8518 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8520 def : Pat<(f16_to_fp GR16:$src),
8521 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8522 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8524 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8525 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8526 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8529 //===----------------------------------------------------------------------===//
8530 // AVX2 Instructions
8531 //===----------------------------------------------------------------------===//
8533 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8534 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8535 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8536 X86MemOperand x86memop> {
8537 let isCommutable = 1 in
8538 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8539 (ins RC:$src1, RC:$src2, u8imm:$src3),
8540 !strconcat(OpcodeStr,
8541 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8542 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8543 Sched<[WriteBlend]>, VEX_4V;
8544 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8545 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8546 !strconcat(OpcodeStr,
8547 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8550 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8551 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8554 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8555 VR128, loadv2i64, i128mem>;
8556 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8557 VR256, loadv4i64, i256mem>, VEX_L;
8559 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8561 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8562 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8564 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8566 //===----------------------------------------------------------------------===//
8567 // VPBROADCAST - Load from memory and broadcast to all elements of the
8568 // destination operand
8570 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8571 X86MemOperand x86memop, PatFrag ld_frag,
8572 Intrinsic Int128, Intrinsic Int256> {
8573 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8575 [(set VR128:$dst, (Int128 VR128:$src))]>,
8576 Sched<[WriteShuffle]>, VEX;
8577 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8578 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8580 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8581 Sched<[WriteLoad]>, VEX;
8582 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8583 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8584 [(set VR256:$dst, (Int256 VR128:$src))]>,
8585 Sched<[WriteShuffle256]>, VEX, VEX_L;
8586 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8587 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8589 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8590 Sched<[WriteLoad]>, VEX, VEX_L;
8593 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8594 int_x86_avx2_pbroadcastb_128,
8595 int_x86_avx2_pbroadcastb_256>;
8596 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8597 int_x86_avx2_pbroadcastw_128,
8598 int_x86_avx2_pbroadcastw_256>;
8599 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8600 int_x86_avx2_pbroadcastd_128,
8601 int_x86_avx2_pbroadcastd_256>;
8602 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8603 int_x86_avx2_pbroadcastq_128,
8604 int_x86_avx2_pbroadcastq_256>;
8606 let Predicates = [HasAVX2] in {
8607 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8608 (VPBROADCASTBrm addr:$src)>;
8609 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8610 (VPBROADCASTBYrm addr:$src)>;
8611 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8612 (VPBROADCASTWrm addr:$src)>;
8613 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8614 (VPBROADCASTWYrm addr:$src)>;
8615 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8616 (VPBROADCASTDrm addr:$src)>;
8617 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8618 (VPBROADCASTDYrm addr:$src)>;
8619 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8620 (VPBROADCASTQrm addr:$src)>;
8621 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8622 (VPBROADCASTQYrm addr:$src)>;
8624 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8625 (VPBROADCASTBrr VR128:$src)>;
8626 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8627 (VPBROADCASTBYrr VR128:$src)>;
8628 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8629 (VPBROADCASTWrr VR128:$src)>;
8630 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8631 (VPBROADCASTWYrr VR128:$src)>;
8632 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8633 (VPBROADCASTDrr VR128:$src)>;
8634 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8635 (VPBROADCASTDYrr VR128:$src)>;
8636 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8637 (VPBROADCASTQrr VR128:$src)>;
8638 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8639 (VPBROADCASTQYrr VR128:$src)>;
8640 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8641 (VBROADCASTSSrr VR128:$src)>;
8642 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8643 (VBROADCASTSSYrr VR128:$src)>;
8644 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8645 (VPBROADCASTQrr VR128:$src)>;
8646 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8647 (VBROADCASTSDYrr VR128:$src)>;
8649 // Provide aliases for broadcast from the same regitser class that
8650 // automatically does the extract.
8651 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8652 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8654 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8655 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8657 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8658 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8660 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8661 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8663 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8664 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8666 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8667 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8670 // Provide fallback in case the load node that is used in the patterns above
8671 // is used by additional users, which prevents the pattern selection.
8672 let AddedComplexity = 20 in {
8673 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8674 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8675 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8676 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8677 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8678 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8680 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8681 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8682 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8683 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8684 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8685 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8687 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8688 (VPBROADCASTBrr (COPY_TO_REGCLASS
8689 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8691 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8692 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8693 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8696 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8697 (VPBROADCASTWrr (COPY_TO_REGCLASS
8698 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8700 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8701 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8702 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8705 // The patterns for VPBROADCASTD are not needed because they would match
8706 // the exact same thing as VBROADCASTSS patterns.
8708 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8709 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8710 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8714 // AVX1 broadcast patterns
8715 let Predicates = [HasAVX1Only] in {
8716 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8717 (VBROADCASTSSYrm addr:$src)>;
8718 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8719 (VBROADCASTSDYrm addr:$src)>;
8720 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8721 (VBROADCASTSSrm addr:$src)>;
8724 let Predicates = [HasAVX] in {
8725 // Provide fallback in case the load node that is used in the patterns above
8726 // is used by additional users, which prevents the pattern selection.
8727 let AddedComplexity = 20 in {
8728 // 128bit broadcasts:
8729 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8730 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8731 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8732 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8733 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8734 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8735 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8736 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8737 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8738 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8740 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8741 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8742 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8743 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8744 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8745 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8746 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8747 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8748 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8749 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8752 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8753 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8756 //===----------------------------------------------------------------------===//
8757 // VPERM - Permute instructions
8760 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8761 ValueType OpVT, X86FoldableSchedWrite Sched> {
8762 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8763 (ins VR256:$src1, VR256:$src2),
8764 !strconcat(OpcodeStr,
8765 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8767 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8768 Sched<[Sched]>, VEX_4V, VEX_L;
8769 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8770 (ins VR256:$src1, i256mem:$src2),
8771 !strconcat(OpcodeStr,
8772 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8774 (OpVT (X86VPermv VR256:$src1,
8775 (bitconvert (mem_frag addr:$src2)))))]>,
8776 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8779 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8780 let ExeDomain = SSEPackedSingle in
8781 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8783 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8784 ValueType OpVT, X86FoldableSchedWrite Sched> {
8785 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8786 (ins VR256:$src1, u8imm:$src2),
8787 !strconcat(OpcodeStr,
8788 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8790 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8791 Sched<[Sched]>, VEX, VEX_L;
8792 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8793 (ins i256mem:$src1, u8imm:$src2),
8794 !strconcat(OpcodeStr,
8795 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8797 (OpVT (X86VPermi (mem_frag addr:$src1),
8798 (i8 imm:$src2))))]>,
8799 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8802 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8803 WriteShuffle256>, VEX_W;
8804 let ExeDomain = SSEPackedDouble in
8805 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8806 WriteFShuffle256>, VEX_W;
8808 //===----------------------------------------------------------------------===//
8809 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8811 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8812 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8813 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8814 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8815 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8817 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8818 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8819 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8820 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8822 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8824 let Predicates = [HasAVX2] in {
8825 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8826 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8827 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8828 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8829 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8830 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8832 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8834 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8835 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8836 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8837 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8838 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8840 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8844 //===----------------------------------------------------------------------===//
8845 // VINSERTI128 - Insert packed integer values
8847 let hasSideEffects = 0 in {
8848 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8849 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8850 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8851 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8853 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8854 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8855 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8856 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8859 let Predicates = [HasAVX2] in {
8860 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8862 (VINSERTI128rr VR256:$src1, VR128:$src2,
8863 (INSERT_get_vinsert128_imm VR256:$ins))>;
8864 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8866 (VINSERTI128rr VR256:$src1, VR128:$src2,
8867 (INSERT_get_vinsert128_imm VR256:$ins))>;
8868 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8870 (VINSERTI128rr VR256:$src1, VR128:$src2,
8871 (INSERT_get_vinsert128_imm VR256:$ins))>;
8872 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8874 (VINSERTI128rr VR256:$src1, VR128:$src2,
8875 (INSERT_get_vinsert128_imm VR256:$ins))>;
8877 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8879 (VINSERTI128rm VR256:$src1, addr:$src2,
8880 (INSERT_get_vinsert128_imm VR256:$ins))>;
8881 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8882 (bc_v4i32 (loadv2i64 addr:$src2)),
8884 (VINSERTI128rm VR256:$src1, addr:$src2,
8885 (INSERT_get_vinsert128_imm VR256:$ins))>;
8886 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8887 (bc_v16i8 (loadv2i64 addr:$src2)),
8889 (VINSERTI128rm VR256:$src1, addr:$src2,
8890 (INSERT_get_vinsert128_imm VR256:$ins))>;
8891 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8892 (bc_v8i16 (loadv2i64 addr:$src2)),
8894 (VINSERTI128rm VR256:$src1, addr:$src2,
8895 (INSERT_get_vinsert128_imm VR256:$ins))>;
8898 //===----------------------------------------------------------------------===//
8899 // VEXTRACTI128 - Extract packed integer values
8901 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8902 (ins VR256:$src1, u8imm:$src2),
8903 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8905 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8906 Sched<[WriteShuffle256]>, VEX, VEX_L;
8907 let hasSideEffects = 0, mayStore = 1 in
8908 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8909 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8910 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8911 Sched<[WriteStore]>, VEX, VEX_L;
8913 let Predicates = [HasAVX2] in {
8914 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8915 (v2i64 (VEXTRACTI128rr
8916 (v4i64 VR256:$src1),
8917 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8918 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8919 (v4i32 (VEXTRACTI128rr
8920 (v8i32 VR256:$src1),
8921 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8922 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8923 (v8i16 (VEXTRACTI128rr
8924 (v16i16 VR256:$src1),
8925 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8926 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8927 (v16i8 (VEXTRACTI128rr
8928 (v32i8 VR256:$src1),
8929 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8931 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8932 (iPTR imm))), addr:$dst),
8933 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8934 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8935 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8936 (iPTR imm))), addr:$dst),
8937 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8938 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8939 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8940 (iPTR imm))), addr:$dst),
8941 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8942 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8943 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8944 (iPTR imm))), addr:$dst),
8945 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8946 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8949 //===----------------------------------------------------------------------===//
8950 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8952 multiclass avx2_pmovmask<string OpcodeStr,
8953 Intrinsic IntLd128, Intrinsic IntLd256,
8954 Intrinsic IntSt128, Intrinsic IntSt256> {
8955 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8956 (ins VR128:$src1, i128mem:$src2),
8957 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8958 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8959 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8960 (ins VR256:$src1, i256mem:$src2),
8961 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8962 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8964 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8965 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8966 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8967 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8968 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8969 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8970 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8971 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8974 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8975 int_x86_avx2_maskload_d,
8976 int_x86_avx2_maskload_d_256,
8977 int_x86_avx2_maskstore_d,
8978 int_x86_avx2_maskstore_d_256>;
8979 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8980 int_x86_avx2_maskload_q,
8981 int_x86_avx2_maskload_q_256,
8982 int_x86_avx2_maskstore_q,
8983 int_x86_avx2_maskstore_q_256>, VEX_W;
8985 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8986 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8988 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8989 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8991 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8992 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8994 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8995 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8997 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8998 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
9000 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
9001 (bc_v8f32 (v8i32 immAllZerosV)))),
9002 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
9004 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
9005 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
9008 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
9009 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
9011 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
9012 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
9014 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
9015 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
9018 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
9019 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
9021 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
9022 (bc_v4f32 (v4i32 immAllZerosV)))),
9023 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
9025 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
9026 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
9029 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
9030 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
9032 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
9033 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
9035 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
9036 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
9039 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
9040 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
9042 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
9043 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
9045 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
9046 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
9048 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
9049 (v4f64 immAllZerosV))),
9050 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
9052 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
9053 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
9056 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
9057 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9059 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
9060 (bc_v4i64 (v8i32 immAllZerosV)))),
9061 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9063 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
9064 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
9067 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
9068 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
9070 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
9071 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
9073 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
9074 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
9076 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
9077 (v2f64 immAllZerosV))),
9078 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
9080 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
9081 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
9084 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
9085 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
9087 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
9088 (bc_v2i64 (v4i32 immAllZerosV)))),
9089 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
9091 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
9092 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
9095 //===----------------------------------------------------------------------===//
9096 // Variable Bit Shifts
9098 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
9099 ValueType vt128, ValueType vt256> {
9100 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
9101 (ins VR128:$src1, VR128:$src2),
9102 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9104 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
9105 VEX_4V, Sched<[WriteVarVecShift]>;
9106 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
9107 (ins VR128:$src1, i128mem:$src2),
9108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9110 (vt128 (OpNode VR128:$src1,
9111 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
9112 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9113 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
9114 (ins VR256:$src1, VR256:$src2),
9115 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9117 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
9118 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
9119 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
9120 (ins VR256:$src1, i256mem:$src2),
9121 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9123 (vt256 (OpNode VR256:$src1,
9124 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
9125 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9128 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
9129 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
9130 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
9131 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
9132 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
9134 //===----------------------------------------------------------------------===//
9135 // VGATHER - GATHER Operations
9136 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
9137 X86MemOperand memop128, X86MemOperand memop256> {
9138 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
9139 (ins VR128:$src1, memop128:$src2, VR128:$mask),
9140 !strconcat(OpcodeStr,
9141 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9143 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
9144 (ins RC256:$src1, memop256:$src2, RC256:$mask),
9145 !strconcat(OpcodeStr,
9146 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9147 []>, VEX_4VOp3, VEX_L;
9150 let mayLoad = 1, Constraints
9151 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
9153 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
9154 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
9155 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
9156 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
9158 let ExeDomain = SSEPackedDouble in {
9159 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
9160 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
9163 let ExeDomain = SSEPackedSingle in {
9164 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
9165 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;