1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
24 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
25 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
26 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
27 [SDNPCommutative, SDNPAssociative]>;
28 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
33 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
34 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
35 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
36 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
37 def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
38 def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
39 def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
41 //===----------------------------------------------------------------------===//
42 // SSE 'Special' Instructions
43 //===----------------------------------------------------------------------===//
45 let isImplicitDef = 1 in {
46 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (outs VR128:$dst), (ins),
48 [(set VR128:$dst, (v4f32 (undef)))]>,
50 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins),
52 [(set FR32:$dst, (undef))]>, Requires<[HasSSE1]>;
53 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (outs FR64:$dst), (ins),
55 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
58 //===----------------------------------------------------------------------===//
59 // SSE Complex Patterns
60 //===----------------------------------------------------------------------===//
62 // These are 'extloads' from a scalar to the low element of a vector, zeroing
63 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
65 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
66 [SDNPHasChain, SDNPMayLoad]>;
67 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
68 [SDNPHasChain, SDNPMayLoad]>;
70 def ssmem : Operand<v4f32> {
71 let PrintMethod = "printf32mem";
72 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
74 def sdmem : Operand<v2f64> {
75 let PrintMethod = "printf64mem";
76 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
79 //===----------------------------------------------------------------------===//
80 // SSE pattern fragments
81 //===----------------------------------------------------------------------===//
83 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
84 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
85 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
86 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
88 // Like 'store', but always requires vector alignment.
89 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
90 (st node:$val, node:$ptr), [{
91 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
92 return !ST->isTruncatingStore() &&
93 ST->getAddressingMode() == ISD::UNINDEXED &&
94 ST->getAlignment() >= 16;
98 // Like 'load', but always requires vector alignment.
99 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
100 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
101 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
102 LD->getAddressingMode() == ISD::UNINDEXED &&
103 LD->getAlignment() >= 16;
107 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
108 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
109 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
110 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
111 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
112 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
114 // Like 'load', but uses special alignment checks suitable for use in
115 // memory operands in most SSE instructions, which are required to
116 // be naturally aligned on some targets but not on others.
117 // FIXME: Actually implement support for targets that don't require the
118 // alignment. This probably wants a subtarget predicate.
119 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
120 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
121 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
122 LD->getAddressingMode() == ISD::UNINDEXED &&
123 LD->getAlignment() >= 16;
127 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
128 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
129 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
130 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
131 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
132 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
134 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
136 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
137 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
138 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
139 LD->getAddressingMode() == ISD::UNINDEXED &&
140 LD->getAlignment() >= 8;
144 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
145 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop64 node:$ptr))>;
146 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
147 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
148 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
150 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
151 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
152 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
153 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
154 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
155 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
157 def fp32imm0 : PatLeaf<(f32 fpimm), [{
158 return N->isExactlyValue(+0.0);
161 def PSxLDQ_imm : SDNodeXForm<imm, [{
162 // Transformation function: imm >> 3
163 return getI32Imm(N->getValue() >> 3);
166 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
168 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
169 return getI8Imm(X86::getShuffleSHUFImmediate(N));
172 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
174 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
175 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
178 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
180 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
181 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
184 def SSE_splat_mask : PatLeaf<(build_vector), [{
185 return X86::isSplatMask(N);
186 }], SHUFFLE_get_shuf_imm>;
188 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
189 return X86::isSplatLoMask(N);
192 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
193 return X86::isMOVHLPSMask(N);
196 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
197 return X86::isMOVHLPS_v_undef_Mask(N);
200 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
201 return X86::isMOVHPMask(N);
204 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
205 return X86::isMOVLPMask(N);
208 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
209 return X86::isMOVLMask(N);
212 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
213 return X86::isMOVSHDUPMask(N);
216 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
217 return X86::isMOVSLDUPMask(N);
220 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
221 return X86::isUNPCKLMask(N);
224 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
225 return X86::isUNPCKHMask(N);
228 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
229 return X86::isUNPCKL_v_undef_Mask(N);
232 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
233 return X86::isUNPCKH_v_undef_Mask(N);
236 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
237 return X86::isPSHUFDMask(N);
238 }], SHUFFLE_get_shuf_imm>;
240 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
241 return X86::isPSHUFHWMask(N);
242 }], SHUFFLE_get_pshufhw_imm>;
244 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
245 return X86::isPSHUFLWMask(N);
246 }], SHUFFLE_get_pshuflw_imm>;
248 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
249 return X86::isPSHUFDMask(N);
250 }], SHUFFLE_get_shuf_imm>;
252 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
253 return X86::isSHUFPMask(N);
254 }], SHUFFLE_get_shuf_imm>;
256 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
257 return X86::isSHUFPMask(N);
258 }], SHUFFLE_get_shuf_imm>;
260 //===----------------------------------------------------------------------===//
261 // SSE scalar FP Instructions
262 //===----------------------------------------------------------------------===//
264 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
265 // scheduler into a branch sequence.
266 // These are expanded by the scheduler.
267 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
268 def CMOV_FR32 : I<0, Pseudo,
269 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
270 "#CMOV_FR32 PSEUDO!",
271 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
273 def CMOV_FR64 : I<0, Pseudo,
274 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
275 "#CMOV_FR64 PSEUDO!",
276 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
278 def CMOV_V4F32 : I<0, Pseudo,
279 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
280 "#CMOV_V4F32 PSEUDO!",
282 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
284 def CMOV_V2F64 : I<0, Pseudo,
285 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
286 "#CMOV_V2F64 PSEUDO!",
288 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
290 def CMOV_V2I64 : I<0, Pseudo,
291 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
292 "#CMOV_V2I64 PSEUDO!",
294 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
298 //===----------------------------------------------------------------------===//
300 //===----------------------------------------------------------------------===//
303 let neverHasSideEffects = 1 in
304 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
305 "movss\t{$src, $dst|$dst, $src}", []>;
306 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
307 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
308 "movss\t{$src, $dst|$dst, $src}",
309 [(set FR32:$dst, (loadf32 addr:$src))]>;
310 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
311 "movss\t{$src, $dst|$dst, $src}",
312 [(store FR32:$src, addr:$dst)]>;
314 // Conversion instructions
315 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
316 "cvttss2si\t{$src, $dst|$dst, $src}",
317 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
318 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
319 "cvttss2si\t{$src, $dst|$dst, $src}",
320 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
321 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
322 "cvtsi2ss\t{$src, $dst|$dst, $src}",
323 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
324 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
325 "cvtsi2ss\t{$src, $dst|$dst, $src}",
326 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
328 // Match intrinsics which expect XMM operand(s).
329 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
330 "cvtss2si\t{$src, $dst|$dst, $src}",
331 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
332 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
333 "cvtss2si\t{$src, $dst|$dst, $src}",
334 [(set GR32:$dst, (int_x86_sse_cvtss2si
335 (load addr:$src)))]>;
337 // Match intrinisics which expect MM and XMM operand(s).
338 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
339 "cvtps2pi\t{$src, $dst|$dst, $src}",
340 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
341 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
342 "cvtps2pi\t{$src, $dst|$dst, $src}",
343 [(set VR64:$dst, (int_x86_sse_cvtps2pi
344 (load addr:$src)))]>;
345 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
346 "cvttps2pi\t{$src, $dst|$dst, $src}",
347 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
348 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
349 "cvttps2pi\t{$src, $dst|$dst, $src}",
350 [(set VR64:$dst, (int_x86_sse_cvttps2pi
351 (load addr:$src)))]>;
352 let isTwoAddress = 1 in {
353 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
354 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
355 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
356 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
358 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
359 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
360 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
361 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
362 (load addr:$src2)))]>;
365 // Aliases for intrinsics
366 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
367 "cvttss2si\t{$src, $dst|$dst, $src}",
369 (int_x86_sse_cvttss2si VR128:$src))]>;
370 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
371 "cvttss2si\t{$src, $dst|$dst, $src}",
373 (int_x86_sse_cvttss2si(load addr:$src)))]>;
375 let isTwoAddress = 1 in {
376 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
377 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
378 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
379 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
381 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
382 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
383 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
384 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
385 (loadi32 addr:$src2)))]>;
388 // Comparison instructions
389 let isTwoAddress = 1 in {
390 let neverHasSideEffects = 1 in
391 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
392 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
393 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
394 let neverHasSideEffects = 1, mayLoad = 1 in
395 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
396 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
397 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
400 let Defs = [EFLAGS] in {
401 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
402 "ucomiss\t{$src2, $src1|$src1, $src2}",
403 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
404 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
405 "ucomiss\t{$src2, $src1|$src1, $src2}",
406 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
410 // Aliases to match intrinsics which expect XMM operand(s).
411 let isTwoAddress = 1 in {
412 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
413 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
414 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
415 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
416 VR128:$src, imm:$cc))]>;
417 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
418 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
419 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
420 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
421 (load addr:$src), imm:$cc))]>;
424 let Defs = [EFLAGS] in {
425 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
426 (ins VR128:$src1, VR128:$src2),
427 "ucomiss\t{$src2, $src1|$src1, $src2}",
428 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
430 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
431 (ins VR128:$src1, f128mem:$src2),
432 "ucomiss\t{$src2, $src1|$src1, $src2}",
433 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
436 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
437 (ins VR128:$src1, VR128:$src2),
438 "comiss\t{$src2, $src1|$src1, $src2}",
439 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
441 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
442 (ins VR128:$src1, f128mem:$src2),
443 "comiss\t{$src2, $src1|$src1, $src2}",
444 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
448 // Aliases of packed SSE1 instructions for scalar use. These all have names that
451 // Alias instructions that map fld0 to pxor for sse.
452 let isReMaterializable = 1 in
453 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
454 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
455 Requires<[HasSSE1]>, TB, OpSize;
457 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
459 let neverHasSideEffects = 1 in
460 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
461 "movaps\t{$src, $dst|$dst, $src}", []>;
463 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
465 let isSimpleLoad = 1 in
466 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
467 "movaps\t{$src, $dst|$dst, $src}",
468 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
470 // Alias bitwise logical operations using SSE logical ops on packed FP values.
471 let isTwoAddress = 1 in {
472 let isCommutable = 1 in {
473 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
474 "andps\t{$src2, $dst|$dst, $src2}",
475 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
476 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
477 "orps\t{$src2, $dst|$dst, $src2}",
478 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
479 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
480 "xorps\t{$src2, $dst|$dst, $src2}",
481 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
484 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
485 "andps\t{$src2, $dst|$dst, $src2}",
486 [(set FR32:$dst, (X86fand FR32:$src1,
487 (memopfsf32 addr:$src2)))]>;
488 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
489 "orps\t{$src2, $dst|$dst, $src2}",
490 [(set FR32:$dst, (X86for FR32:$src1,
491 (memopfsf32 addr:$src2)))]>;
492 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
493 "xorps\t{$src2, $dst|$dst, $src2}",
494 [(set FR32:$dst, (X86fxor FR32:$src1,
495 (memopfsf32 addr:$src2)))]>;
496 let neverHasSideEffects = 1 in {
497 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
498 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
499 "andnps\t{$src2, $dst|$dst, $src2}", []>;
502 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
503 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
504 "andnps\t{$src2, $dst|$dst, $src2}", []>;
508 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
510 /// In addition, we also have a special variant of the scalar form here to
511 /// represent the associated intrinsic operation. This form is unlike the
512 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
513 /// and leaves the top elements undefined.
515 /// These three forms can each be reg+reg or reg+mem, so there are a total of
516 /// six "instructions".
518 let isTwoAddress = 1 in {
519 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
520 SDNode OpNode, Intrinsic F32Int,
521 bit Commutable = 0> {
522 // Scalar operation, reg+reg.
523 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
524 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
525 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
526 let isCommutable = Commutable;
529 // Scalar operation, reg+mem.
530 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
531 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
532 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
534 // Vector operation, reg+reg.
535 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
536 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
537 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
538 let isCommutable = Commutable;
541 // Vector operation, reg+mem.
542 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
543 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
544 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
546 // Intrinsic operation, reg+reg.
547 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
548 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
549 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
550 let isCommutable = Commutable;
553 // Intrinsic operation, reg+mem.
554 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
555 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
556 [(set VR128:$dst, (F32Int VR128:$src1,
557 sse_load_f32:$src2))]>;
561 // Arithmetic instructions
562 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
563 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
564 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
565 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
567 /// sse1_fp_binop_rm - Other SSE1 binops
569 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
570 /// instructions for a full-vector intrinsic form. Operations that map
571 /// onto C operators don't use this form since they just use the plain
572 /// vector form instead of having a separate vector intrinsic form.
574 /// This provides a total of eight "instructions".
576 let isTwoAddress = 1 in {
577 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
581 bit Commutable = 0> {
583 // Scalar operation, reg+reg.
584 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
585 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
586 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
587 let isCommutable = Commutable;
590 // Scalar operation, reg+mem.
591 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
592 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
593 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
595 // Vector operation, reg+reg.
596 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
597 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
598 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
599 let isCommutable = Commutable;
602 // Vector operation, reg+mem.
603 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
604 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
605 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
607 // Intrinsic operation, reg+reg.
608 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
609 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
610 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
611 let isCommutable = Commutable;
614 // Intrinsic operation, reg+mem.
615 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
616 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
617 [(set VR128:$dst, (F32Int VR128:$src1,
618 sse_load_f32:$src2))]>;
620 // Vector intrinsic operation, reg+reg.
621 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
622 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
623 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
624 let isCommutable = Commutable;
627 // Vector intrinsic operation, reg+mem.
628 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
629 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
630 [(set VR128:$dst, (V4F32Int VR128:$src1, (load addr:$src2)))]>;
634 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
635 int_x86_sse_max_ss, int_x86_sse_max_ps>;
636 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
637 int_x86_sse_min_ss, int_x86_sse_min_ps>;
639 //===----------------------------------------------------------------------===//
640 // SSE packed FP Instructions
643 let neverHasSideEffects = 1 in
644 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
645 "movaps\t{$src, $dst|$dst, $src}", []>;
646 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
647 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
648 "movaps\t{$src, $dst|$dst, $src}",
649 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
651 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
652 "movaps\t{$src, $dst|$dst, $src}",
653 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
655 let neverHasSideEffects = 1 in
656 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
657 "movups\t{$src, $dst|$dst, $src}", []>;
658 let isSimpleLoad = 1 in
659 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
660 "movups\t{$src, $dst|$dst, $src}",
661 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
662 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
663 "movups\t{$src, $dst|$dst, $src}",
664 [(store (v4f32 VR128:$src), addr:$dst)]>;
666 // Intrinsic forms of MOVUPS load and store
667 let isSimpleLoad = 1 in
668 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
669 "movups\t{$src, $dst|$dst, $src}",
670 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
671 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
672 "movups\t{$src, $dst|$dst, $src}",
673 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
675 let isTwoAddress = 1 in {
676 let AddedComplexity = 20 in {
677 def MOVLPSrm : PSI<0x12, MRMSrcMem,
678 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
679 "movlps\t{$src2, $dst|$dst, $src2}",
681 (v4f32 (vector_shuffle VR128:$src1,
682 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
683 MOVLP_shuffle_mask)))]>;
684 def MOVHPSrm : PSI<0x16, MRMSrcMem,
685 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
686 "movhps\t{$src2, $dst|$dst, $src2}",
688 (v4f32 (vector_shuffle VR128:$src1,
689 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
690 MOVHP_shuffle_mask)))]>;
694 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
695 "movlps\t{$src, $dst|$dst, $src}",
696 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
697 (iPTR 0))), addr:$dst)]>;
699 // v2f64 extract element 1 is always custom lowered to unpack high to low
700 // and extract element 0 so the non-store version isn't too horrible.
701 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
702 "movhps\t{$src, $dst|$dst, $src}",
703 [(store (f64 (vector_extract
704 (v2f64 (vector_shuffle
705 (bc_v2f64 (v4f32 VR128:$src)), (undef),
706 UNPCKH_shuffle_mask)), (iPTR 0))),
709 let isTwoAddress = 1 in {
710 let AddedComplexity = 15 in {
711 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
712 "movlhps\t{$src2, $dst|$dst, $src2}",
714 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
715 MOVHP_shuffle_mask)))]>;
717 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
718 "movhlps\t{$src2, $dst|$dst, $src2}",
720 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
721 MOVHLPS_shuffle_mask)))]>;
729 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
731 /// In addition, we also have a special variant of the scalar form here to
732 /// represent the associated intrinsic operation. This form is unlike the
733 /// plain scalar form, in that it takes an entire vector (instead of a
734 /// scalar) and leaves the top elements undefined.
736 /// And, we have a special variant form for a full-vector intrinsic form.
738 /// These four forms can each have a reg or a mem operand, so there are a
739 /// total of eight "instructions".
741 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
745 bit Commutable = 0> {
746 // Scalar operation, reg.
747 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
748 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
749 [(set FR32:$dst, (OpNode FR32:$src))]> {
750 let isCommutable = Commutable;
753 // Scalar operation, mem.
754 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
755 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
756 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
758 // Vector operation, reg.
759 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
760 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
761 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
762 let isCommutable = Commutable;
765 // Vector operation, mem.
766 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
767 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
768 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
770 // Intrinsic operation, reg.
771 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
772 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
773 [(set VR128:$dst, (F32Int VR128:$src))]> {
774 let isCommutable = Commutable;
777 // Intrinsic operation, mem.
778 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
779 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
780 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
782 // Vector intrinsic operation, reg
783 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
784 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
785 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
786 let isCommutable = Commutable;
789 // Vector intrinsic operation, mem
790 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
791 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
792 [(set VR128:$dst, (V4F32Int (load addr:$src)))]>;
796 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
797 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
799 // Reciprocal approximations. Note that these typically require refinement
800 // in order to obtain suitable precision.
801 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
802 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
803 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
804 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
807 let isTwoAddress = 1 in {
808 let isCommutable = 1 in {
809 def ANDPSrr : PSI<0x54, MRMSrcReg,
810 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
811 "andps\t{$src2, $dst|$dst, $src2}",
812 [(set VR128:$dst, (v2i64
813 (and VR128:$src1, VR128:$src2)))]>;
814 def ORPSrr : PSI<0x56, MRMSrcReg,
815 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
816 "orps\t{$src2, $dst|$dst, $src2}",
817 [(set VR128:$dst, (v2i64
818 (or VR128:$src1, VR128:$src2)))]>;
819 def XORPSrr : PSI<0x57, MRMSrcReg,
820 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
821 "xorps\t{$src2, $dst|$dst, $src2}",
822 [(set VR128:$dst, (v2i64
823 (xor VR128:$src1, VR128:$src2)))]>;
826 def ANDPSrm : PSI<0x54, MRMSrcMem,
827 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
828 "andps\t{$src2, $dst|$dst, $src2}",
829 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
830 (memopv2i64 addr:$src2)))]>;
831 def ORPSrm : PSI<0x56, MRMSrcMem,
832 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
833 "orps\t{$src2, $dst|$dst, $src2}",
834 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
835 (memopv2i64 addr:$src2)))]>;
836 def XORPSrm : PSI<0x57, MRMSrcMem,
837 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
838 "xorps\t{$src2, $dst|$dst, $src2}",
839 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
840 (memopv2i64 addr:$src2)))]>;
841 def ANDNPSrr : PSI<0x55, MRMSrcReg,
842 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
843 "andnps\t{$src2, $dst|$dst, $src2}",
845 (v2i64 (and (xor VR128:$src1,
846 (bc_v2i64 (v4i32 immAllOnesV))),
848 def ANDNPSrm : PSI<0x55, MRMSrcMem,
849 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
850 "andnps\t{$src2, $dst|$dst, $src2}",
852 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
853 (bc_v2i64 (v4i32 immAllOnesV))),
854 (memopv2i64 addr:$src2))))]>;
857 let isTwoAddress = 1 in {
858 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
859 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
860 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
861 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
862 VR128:$src, imm:$cc))]>;
863 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
864 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
865 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
866 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
867 (load addr:$src), imm:$cc))]>;
870 // Shuffle and unpack instructions
871 let isTwoAddress = 1 in {
872 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
873 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
874 (outs VR128:$dst), (ins VR128:$src1,
875 VR128:$src2, i32i8imm:$src3),
876 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
878 (v4f32 (vector_shuffle
879 VR128:$src1, VR128:$src2,
880 SHUFP_shuffle_mask:$src3)))]>;
881 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
882 (outs VR128:$dst), (ins VR128:$src1,
883 f128mem:$src2, i32i8imm:$src3),
884 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
886 (v4f32 (vector_shuffle
887 VR128:$src1, (memopv4f32 addr:$src2),
888 SHUFP_shuffle_mask:$src3)))]>;
890 let AddedComplexity = 10 in {
891 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
892 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
893 "unpckhps\t{$src2, $dst|$dst, $src2}",
895 (v4f32 (vector_shuffle
896 VR128:$src1, VR128:$src2,
897 UNPCKH_shuffle_mask)))]>;
898 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
899 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
900 "unpckhps\t{$src2, $dst|$dst, $src2}",
902 (v4f32 (vector_shuffle
903 VR128:$src1, (memopv4f32 addr:$src2),
904 UNPCKH_shuffle_mask)))]>;
906 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
907 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
908 "unpcklps\t{$src2, $dst|$dst, $src2}",
910 (v4f32 (vector_shuffle
911 VR128:$src1, VR128:$src2,
912 UNPCKL_shuffle_mask)))]>;
913 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
914 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
915 "unpcklps\t{$src2, $dst|$dst, $src2}",
917 (v4f32 (vector_shuffle
918 VR128:$src1, (memopv4f32 addr:$src2),
919 UNPCKL_shuffle_mask)))]>;
924 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
925 "movmskps\t{$src, $dst|$dst, $src}",
926 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
927 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
928 "movmskpd\t{$src, $dst|$dst, $src}",
929 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
931 // Prefetching loads.
932 // TODO: no intrinsics for these?
933 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src), "prefetcht0\t$src", []>;
934 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src), "prefetcht1\t$src", []>;
935 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src), "prefetcht2\t$src", []>;
936 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src), "prefetchnta\t$src", []>;
938 // Non-temporal stores
939 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
940 "movntps\t{$src, $dst|$dst, $src}",
941 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
943 // Load, store, and memory fence
944 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
947 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
948 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
949 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
950 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
952 // Alias instructions that map zero vector to pxor / xorp* for sse.
953 let isReMaterializable = 1 in
954 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
956 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
958 // FR32 to 128-bit vector conversion.
959 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
960 "movss\t{$src, $dst|$dst, $src}",
962 (v4f32 (scalar_to_vector FR32:$src)))]>;
963 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
964 "movss\t{$src, $dst|$dst, $src}",
966 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
968 // FIXME: may not be able to eliminate this movss with coalescing the src and
969 // dest register classes are different. We really want to write this pattern
971 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
973 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
974 "movss\t{$src, $dst|$dst, $src}",
975 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
977 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
978 "movss\t{$src, $dst|$dst, $src}",
979 [(store (f32 (vector_extract (v4f32 VR128:$src),
980 (iPTR 0))), addr:$dst)]>;
983 // Move to lower bits of a VR128, leaving upper bits alone.
984 // Three operand (but two address) aliases.
985 let isTwoAddress = 1 in {
986 let neverHasSideEffects = 1 in
987 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
988 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
989 "movss\t{$src2, $dst|$dst, $src2}", []>;
991 let AddedComplexity = 15 in
992 def MOVLPSrr : SSI<0x10, MRMSrcReg,
993 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
994 "movss\t{$src2, $dst|$dst, $src2}",
996 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
997 MOVL_shuffle_mask)))]>;
1000 // Move to lower bits of a VR128 and zeroing upper bits.
1001 // Loading from memory automatically zeroing upper bits.
1002 let AddedComplexity = 20 in
1003 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1004 "movss\t{$src, $dst|$dst, $src}",
1005 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV_bc,
1006 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
1007 MOVL_shuffle_mask)))]>;
1010 //===----------------------------------------------------------------------===//
1011 // SSE2 Instructions
1012 //===----------------------------------------------------------------------===//
1014 // Move Instructions
1015 let neverHasSideEffects = 1 in
1016 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1017 "movsd\t{$src, $dst|$dst, $src}", []>;
1018 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1019 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1020 "movsd\t{$src, $dst|$dst, $src}",
1021 [(set FR64:$dst, (loadf64 addr:$src))]>;
1022 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1023 "movsd\t{$src, $dst|$dst, $src}",
1024 [(store FR64:$src, addr:$dst)]>;
1026 // Conversion instructions
1027 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1028 "cvttsd2si\t{$src, $dst|$dst, $src}",
1029 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1030 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1031 "cvttsd2si\t{$src, $dst|$dst, $src}",
1032 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1033 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1034 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1035 [(set FR32:$dst, (fround FR64:$src))]>;
1036 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1037 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1038 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1039 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1040 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1041 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1042 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1043 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1044 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1046 // SSE2 instructions with XS prefix
1047 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1048 "cvtss2sd\t{$src, $dst|$dst, $src}",
1049 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1050 Requires<[HasSSE2]>;
1051 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1052 "cvtss2sd\t{$src, $dst|$dst, $src}",
1053 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1054 Requires<[HasSSE2]>;
1056 // Match intrinsics which expect XMM operand(s).
1057 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1058 "cvtsd2si\t{$src, $dst|$dst, $src}",
1059 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1060 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1061 "cvtsd2si\t{$src, $dst|$dst, $src}",
1062 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1063 (load addr:$src)))]>;
1065 // Match intrinisics which expect MM and XMM operand(s).
1066 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1067 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1068 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1069 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1070 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1071 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1072 (load addr:$src)))]>;
1073 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1074 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1075 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1076 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1077 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1078 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1079 (load addr:$src)))]>;
1080 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1081 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1082 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1083 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1084 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1085 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1086 (load addr:$src)))]>;
1088 // Aliases for intrinsics
1089 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1090 "cvttsd2si\t{$src, $dst|$dst, $src}",
1092 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1093 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1094 "cvttsd2si\t{$src, $dst|$dst, $src}",
1095 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1096 (load addr:$src)))]>;
1098 // Comparison instructions
1099 let isTwoAddress = 1, neverHasSideEffects = 1 in {
1100 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1101 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1102 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1104 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1105 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1106 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1109 let Defs = [EFLAGS] in {
1110 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1111 "ucomisd\t{$src2, $src1|$src1, $src2}",
1112 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1113 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1114 "ucomisd\t{$src2, $src1|$src1, $src2}",
1115 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1116 (implicit EFLAGS)]>;
1119 // Aliases to match intrinsics which expect XMM operand(s).
1120 let isTwoAddress = 1 in {
1121 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1122 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1123 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1124 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1125 VR128:$src, imm:$cc))]>;
1126 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1127 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1128 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1129 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1130 (load addr:$src), imm:$cc))]>;
1133 let Defs = [EFLAGS] in {
1134 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1135 "ucomisd\t{$src2, $src1|$src1, $src2}",
1136 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1137 (implicit EFLAGS)]>;
1138 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1139 "ucomisd\t{$src2, $src1|$src1, $src2}",
1140 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1141 (implicit EFLAGS)]>;
1143 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1144 "comisd\t{$src2, $src1|$src1, $src2}",
1145 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1146 (implicit EFLAGS)]>;
1147 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1148 "comisd\t{$src2, $src1|$src1, $src2}",
1149 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1150 (implicit EFLAGS)]>;
1153 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1156 // Alias instructions that map fld0 to pxor for sse.
1157 let isReMaterializable = 1 in
1158 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1159 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1160 Requires<[HasSSE2]>, TB, OpSize;
1162 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1164 let neverHasSideEffects = 1 in
1165 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1166 "movapd\t{$src, $dst|$dst, $src}", []>;
1168 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1170 let isSimpleLoad = 1 in
1171 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1172 "movapd\t{$src, $dst|$dst, $src}",
1173 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1175 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1176 let isTwoAddress = 1 in {
1177 let isCommutable = 1 in {
1178 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1179 "andpd\t{$src2, $dst|$dst, $src2}",
1180 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1181 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1182 "orpd\t{$src2, $dst|$dst, $src2}",
1183 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1184 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1185 "xorpd\t{$src2, $dst|$dst, $src2}",
1186 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1189 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1190 "andpd\t{$src2, $dst|$dst, $src2}",
1191 [(set FR64:$dst, (X86fand FR64:$src1,
1192 (memopfsf64 addr:$src2)))]>;
1193 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1194 "orpd\t{$src2, $dst|$dst, $src2}",
1195 [(set FR64:$dst, (X86for FR64:$src1,
1196 (memopfsf64 addr:$src2)))]>;
1197 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1198 "xorpd\t{$src2, $dst|$dst, $src2}",
1199 [(set FR64:$dst, (X86fxor FR64:$src1,
1200 (memopfsf64 addr:$src2)))]>;
1202 let neverHasSideEffects = 1 in {
1203 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1204 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1205 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1207 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1208 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1209 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1213 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1215 /// In addition, we also have a special variant of the scalar form here to
1216 /// represent the associated intrinsic operation. This form is unlike the
1217 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1218 /// and leaves the top elements undefined.
1220 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1221 /// six "instructions".
1223 let isTwoAddress = 1 in {
1224 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1225 SDNode OpNode, Intrinsic F64Int,
1226 bit Commutable = 0> {
1227 // Scalar operation, reg+reg.
1228 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1229 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1230 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1231 let isCommutable = Commutable;
1234 // Scalar operation, reg+mem.
1235 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1236 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1237 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1239 // Vector operation, reg+reg.
1240 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1241 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1242 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1243 let isCommutable = Commutable;
1246 // Vector operation, reg+mem.
1247 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1248 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1249 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1251 // Intrinsic operation, reg+reg.
1252 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1253 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1254 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1255 let isCommutable = Commutable;
1258 // Intrinsic operation, reg+mem.
1259 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1260 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1261 [(set VR128:$dst, (F64Int VR128:$src1,
1262 sse_load_f64:$src2))]>;
1266 // Arithmetic instructions
1267 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1268 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1269 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1270 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1272 /// sse2_fp_binop_rm - Other SSE2 binops
1274 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1275 /// instructions for a full-vector intrinsic form. Operations that map
1276 /// onto C operators don't use this form since they just use the plain
1277 /// vector form instead of having a separate vector intrinsic form.
1279 /// This provides a total of eight "instructions".
1281 let isTwoAddress = 1 in {
1282 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1286 bit Commutable = 0> {
1288 // Scalar operation, reg+reg.
1289 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1290 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1291 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1292 let isCommutable = Commutable;
1295 // Scalar operation, reg+mem.
1296 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1297 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1298 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1300 // Vector operation, reg+reg.
1301 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1302 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1303 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1304 let isCommutable = Commutable;
1307 // Vector operation, reg+mem.
1308 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1309 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1310 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1312 // Intrinsic operation, reg+reg.
1313 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1314 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1315 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1316 let isCommutable = Commutable;
1319 // Intrinsic operation, reg+mem.
1320 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1321 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1322 [(set VR128:$dst, (F64Int VR128:$src1,
1323 sse_load_f64:$src2))]>;
1325 // Vector intrinsic operation, reg+reg.
1326 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1327 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1328 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1329 let isCommutable = Commutable;
1332 // Vector intrinsic operation, reg+mem.
1333 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1334 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1335 [(set VR128:$dst, (V2F64Int VR128:$src1, (load addr:$src2)))]>;
1339 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1340 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1341 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1342 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1344 //===----------------------------------------------------------------------===//
1345 // SSE packed FP Instructions
1347 // Move Instructions
1348 let neverHasSideEffects = 1 in
1349 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1350 "movapd\t{$src, $dst|$dst, $src}", []>;
1351 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1352 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1353 "movapd\t{$src, $dst|$dst, $src}",
1354 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1356 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1357 "movapd\t{$src, $dst|$dst, $src}",
1358 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1360 let neverHasSideEffects = 1 in
1361 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1362 "movupd\t{$src, $dst|$dst, $src}", []>;
1363 let isSimpleLoad = 1 in
1364 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1365 "movupd\t{$src, $dst|$dst, $src}",
1366 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1367 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1368 "movupd\t{$src, $dst|$dst, $src}",
1369 [(store (v2f64 VR128:$src), addr:$dst)]>;
1371 // Intrinsic forms of MOVUPD load and store
1372 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1373 "movupd\t{$src, $dst|$dst, $src}",
1374 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1375 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1376 "movupd\t{$src, $dst|$dst, $src}",
1377 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1379 let isTwoAddress = 1 in {
1380 let AddedComplexity = 20 in {
1381 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1382 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1383 "movlpd\t{$src2, $dst|$dst, $src2}",
1385 (v2f64 (vector_shuffle VR128:$src1,
1386 (scalar_to_vector (loadf64 addr:$src2)),
1387 MOVLP_shuffle_mask)))]>;
1388 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1389 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1390 "movhpd\t{$src2, $dst|$dst, $src2}",
1392 (v2f64 (vector_shuffle VR128:$src1,
1393 (scalar_to_vector (loadf64 addr:$src2)),
1394 MOVHP_shuffle_mask)))]>;
1395 } // AddedComplexity
1398 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1399 "movlpd\t{$src, $dst|$dst, $src}",
1400 [(store (f64 (vector_extract (v2f64 VR128:$src),
1401 (iPTR 0))), addr:$dst)]>;
1403 // v2f64 extract element 1 is always custom lowered to unpack high to low
1404 // and extract element 0 so the non-store version isn't too horrible.
1405 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1406 "movhpd\t{$src, $dst|$dst, $src}",
1407 [(store (f64 (vector_extract
1408 (v2f64 (vector_shuffle VR128:$src, (undef),
1409 UNPCKH_shuffle_mask)), (iPTR 0))),
1412 // SSE2 instructions without OpSize prefix
1413 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1414 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1415 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1416 TB, Requires<[HasSSE2]>;
1417 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1418 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1419 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1420 (bitconvert (memopv2i64 addr:$src))))]>,
1421 TB, Requires<[HasSSE2]>;
1423 // SSE2 instructions with XS prefix
1424 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1425 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1426 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1427 XS, Requires<[HasSSE2]>;
1428 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1429 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1430 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1431 (bitconvert (memopv2i64 addr:$src))))]>,
1432 XS, Requires<[HasSSE2]>;
1434 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1435 "cvtps2dq\t{$src, $dst|$dst, $src}",
1436 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1437 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1438 "cvtps2dq\t{$src, $dst|$dst, $src}",
1439 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1440 (load addr:$src)))]>;
1441 // SSE2 packed instructions with XS prefix
1442 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1443 "cvttps2dq\t{$src, $dst|$dst, $src}",
1444 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1445 XS, Requires<[HasSSE2]>;
1446 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1447 "cvttps2dq\t{$src, $dst|$dst, $src}",
1448 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1449 (load addr:$src)))]>,
1450 XS, Requires<[HasSSE2]>;
1452 // SSE2 packed instructions with XD prefix
1453 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1454 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1455 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1456 XD, Requires<[HasSSE2]>;
1457 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1458 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1459 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1460 (load addr:$src)))]>,
1461 XD, Requires<[HasSSE2]>;
1463 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1464 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1465 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1466 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1467 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1468 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1469 (load addr:$src)))]>;
1471 // SSE2 instructions without OpSize prefix
1472 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1473 "cvtps2pd\t{$src, $dst|$dst, $src}",
1474 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1475 TB, Requires<[HasSSE2]>;
1476 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f64mem:$src),
1477 "cvtps2pd\t{$src, $dst|$dst, $src}",
1478 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1479 (load addr:$src)))]>,
1480 TB, Requires<[HasSSE2]>;
1482 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1483 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1484 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1485 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f128mem:$src),
1486 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1487 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1488 (load addr:$src)))]>;
1490 // Match intrinsics which expect XMM operand(s).
1491 // Aliases for intrinsics
1492 let isTwoAddress = 1 in {
1493 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1494 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1495 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1496 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1498 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1499 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1500 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1501 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1502 (loadi32 addr:$src2)))]>;
1503 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1504 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1505 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1506 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1508 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1509 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1510 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1511 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1512 (load addr:$src2)))]>;
1513 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1514 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1515 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1516 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1517 VR128:$src2))]>, XS,
1518 Requires<[HasSSE2]>;
1519 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1520 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1521 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1522 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1523 (load addr:$src2)))]>, XS,
1524 Requires<[HasSSE2]>;
1529 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1531 /// In addition, we also have a special variant of the scalar form here to
1532 /// represent the associated intrinsic operation. This form is unlike the
1533 /// plain scalar form, in that it takes an entire vector (instead of a
1534 /// scalar) and leaves the top elements undefined.
1536 /// And, we have a special variant form for a full-vector intrinsic form.
1538 /// These four forms can each have a reg or a mem operand, so there are a
1539 /// total of eight "instructions".
1541 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1545 bit Commutable = 0> {
1546 // Scalar operation, reg.
1547 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1548 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1549 [(set FR64:$dst, (OpNode FR64:$src))]> {
1550 let isCommutable = Commutable;
1553 // Scalar operation, mem.
1554 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1555 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1556 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1558 // Vector operation, reg.
1559 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1560 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1561 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1562 let isCommutable = Commutable;
1565 // Vector operation, mem.
1566 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1567 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1568 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1570 // Intrinsic operation, reg.
1571 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1572 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1573 [(set VR128:$dst, (F64Int VR128:$src))]> {
1574 let isCommutable = Commutable;
1577 // Intrinsic operation, mem.
1578 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1579 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1580 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1582 // Vector intrinsic operation, reg
1583 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1584 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1585 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1586 let isCommutable = Commutable;
1589 // Vector intrinsic operation, mem
1590 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1591 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1592 [(set VR128:$dst, (V2F64Int (load addr:$src)))]>;
1596 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1597 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1599 // There is no f64 version of the reciprocal approximation instructions.
1602 let isTwoAddress = 1 in {
1603 let isCommutable = 1 in {
1604 def ANDPDrr : PDI<0x54, MRMSrcReg,
1605 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1606 "andpd\t{$src2, $dst|$dst, $src2}",
1608 (and (bc_v2i64 (v2f64 VR128:$src1)),
1609 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1610 def ORPDrr : PDI<0x56, MRMSrcReg,
1611 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1612 "orpd\t{$src2, $dst|$dst, $src2}",
1614 (or (bc_v2i64 (v2f64 VR128:$src1)),
1615 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1616 def XORPDrr : PDI<0x57, MRMSrcReg,
1617 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1618 "xorpd\t{$src2, $dst|$dst, $src2}",
1620 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1621 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1624 def ANDPDrm : PDI<0x54, MRMSrcMem,
1625 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1626 "andpd\t{$src2, $dst|$dst, $src2}",
1628 (and (bc_v2i64 (v2f64 VR128:$src1)),
1629 (memopv2i64 addr:$src2)))]>;
1630 def ORPDrm : PDI<0x56, MRMSrcMem,
1631 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1632 "orpd\t{$src2, $dst|$dst, $src2}",
1634 (or (bc_v2i64 (v2f64 VR128:$src1)),
1635 (memopv2i64 addr:$src2)))]>;
1636 def XORPDrm : PDI<0x57, MRMSrcMem,
1637 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1638 "xorpd\t{$src2, $dst|$dst, $src2}",
1640 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1641 (memopv2i64 addr:$src2)))]>;
1642 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1643 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1644 "andnpd\t{$src2, $dst|$dst, $src2}",
1646 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1647 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1648 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1649 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1650 "andnpd\t{$src2, $dst|$dst, $src2}",
1652 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1653 (memopv2i64 addr:$src2)))]>;
1656 let isTwoAddress = 1 in {
1657 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1658 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1659 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1660 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1661 VR128:$src, imm:$cc))]>;
1662 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1663 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1664 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1665 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1666 (load addr:$src), imm:$cc))]>;
1669 // Shuffle and unpack instructions
1670 let isTwoAddress = 1 in {
1671 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1672 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1673 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1674 [(set VR128:$dst, (v2f64 (vector_shuffle
1675 VR128:$src1, VR128:$src2,
1676 SHUFP_shuffle_mask:$src3)))]>;
1677 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1678 (outs VR128:$dst), (ins VR128:$src1,
1679 f128mem:$src2, i8imm:$src3),
1680 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1682 (v2f64 (vector_shuffle
1683 VR128:$src1, (memopv2f64 addr:$src2),
1684 SHUFP_shuffle_mask:$src3)))]>;
1686 let AddedComplexity = 10 in {
1687 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1688 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1689 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1691 (v2f64 (vector_shuffle
1692 VR128:$src1, VR128:$src2,
1693 UNPCKH_shuffle_mask)))]>;
1694 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1695 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1696 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1698 (v2f64 (vector_shuffle
1699 VR128:$src1, (memopv2f64 addr:$src2),
1700 UNPCKH_shuffle_mask)))]>;
1702 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1703 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1704 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1706 (v2f64 (vector_shuffle
1707 VR128:$src1, VR128:$src2,
1708 UNPCKL_shuffle_mask)))]>;
1709 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1710 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1711 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1713 (v2f64 (vector_shuffle
1714 VR128:$src1, (memopv2f64 addr:$src2),
1715 UNPCKL_shuffle_mask)))]>;
1716 } // AddedComplexity
1720 //===----------------------------------------------------------------------===//
1721 // SSE integer instructions
1723 // Move Instructions
1724 let neverHasSideEffects = 1 in
1725 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1726 "movdqa\t{$src, $dst|$dst, $src}", []>;
1727 let isSimpleLoad = 1, mayLoad = 1 in
1728 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1729 "movdqa\t{$src, $dst|$dst, $src}",
1730 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1732 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1733 "movdqa\t{$src, $dst|$dst, $src}",
1734 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1735 let isSimpleLoad = 1, mayLoad = 1 in
1736 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1737 "movdqu\t{$src, $dst|$dst, $src}",
1738 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1739 XS, Requires<[HasSSE2]>;
1741 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1742 "movdqu\t{$src, $dst|$dst, $src}",
1743 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1744 XS, Requires<[HasSSE2]>;
1746 // Intrinsic forms of MOVDQU load and store
1747 let isSimpleLoad = 1 in
1748 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1749 "movdqu\t{$src, $dst|$dst, $src}",
1750 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1751 XS, Requires<[HasSSE2]>;
1752 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1753 "movdqu\t{$src, $dst|$dst, $src}",
1754 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1755 XS, Requires<[HasSSE2]>;
1757 let isTwoAddress = 1 in {
1759 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1760 bit Commutable = 0> {
1761 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1762 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1763 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1764 let isCommutable = Commutable;
1766 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1767 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1768 [(set VR128:$dst, (IntId VR128:$src1,
1769 (bitconvert (memopv2i64 addr:$src2))))]>;
1772 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1773 string OpcodeStr, Intrinsic IntId> {
1774 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1775 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1776 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1777 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1778 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1779 [(set VR128:$dst, (IntId VR128:$src1,
1780 (bitconvert (memopv2i64 addr:$src2))))]>;
1781 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1782 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1783 [(set VR128:$dst, (IntId VR128:$src1,
1784 (scalar_to_vector (i32 imm:$src2))))]>;
1788 /// PDI_binop_rm - Simple SSE2 binary operator.
1789 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1790 ValueType OpVT, bit Commutable = 0> {
1791 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1792 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1793 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1794 let isCommutable = Commutable;
1796 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1797 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1798 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1799 (bitconvert (memopv2i64 addr:$src2)))))]>;
1802 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1804 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1805 /// to collapse (bitconvert VT to VT) into its operand.
1807 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1808 bit Commutable = 0> {
1809 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1810 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1811 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1812 let isCommutable = Commutable;
1814 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1815 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1816 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1821 // 128-bit Integer Arithmetic
1823 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1824 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1825 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1826 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1828 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1829 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1830 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1831 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1833 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1834 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1835 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1836 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1838 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1839 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1840 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1841 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1843 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1845 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1846 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1847 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1849 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1851 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1852 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1855 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1856 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1857 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1858 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1859 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1862 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1863 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1864 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1866 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1867 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1868 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1870 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1871 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1872 // PSRAQ doesn't exist in SSE[1-3].
1874 // 128-bit logical shifts.
1875 let isTwoAddress = 1, neverHasSideEffects = 1 in {
1876 def PSLLDQri : PDIi8<0x73, MRM7r,
1877 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1878 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1879 def PSRLDQri : PDIi8<0x73, MRM3r,
1880 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1881 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1882 // PSRADQri doesn't exist in SSE[1-3].
1885 let Predicates = [HasSSE2] in {
1886 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1887 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1888 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1889 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1890 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1891 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1895 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1896 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1897 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1899 let isTwoAddress = 1 in {
1900 def PANDNrr : PDI<0xDF, MRMSrcReg,
1901 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1902 "pandn\t{$src2, $dst|$dst, $src2}",
1903 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1906 def PANDNrm : PDI<0xDF, MRMSrcMem,
1907 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1908 "pandn\t{$src2, $dst|$dst, $src2}",
1909 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1910 (memopv2i64 addr:$src2))))]>;
1913 // SSE2 Integer comparison
1914 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1915 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1916 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1917 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1918 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1919 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1921 // Pack instructions
1922 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1923 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1924 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1926 // Shuffle and unpack instructions
1927 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1928 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1929 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1930 [(set VR128:$dst, (v4i32 (vector_shuffle
1931 VR128:$src1, (undef),
1932 PSHUFD_shuffle_mask:$src2)))]>;
1933 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1934 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1935 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1936 [(set VR128:$dst, (v4i32 (vector_shuffle
1937 (bc_v4i32(memopv2i64 addr:$src1)),
1939 PSHUFD_shuffle_mask:$src2)))]>;
1941 // SSE2 with ImmT == Imm8 and XS prefix.
1942 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1943 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1944 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1945 [(set VR128:$dst, (v8i16 (vector_shuffle
1946 VR128:$src1, (undef),
1947 PSHUFHW_shuffle_mask:$src2)))]>,
1948 XS, Requires<[HasSSE2]>;
1949 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1950 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1951 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1952 [(set VR128:$dst, (v8i16 (vector_shuffle
1953 (bc_v8i16 (memopv2i64 addr:$src1)),
1955 PSHUFHW_shuffle_mask:$src2)))]>,
1956 XS, Requires<[HasSSE2]>;
1958 // SSE2 with ImmT == Imm8 and XD prefix.
1959 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1960 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1961 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1962 [(set VR128:$dst, (v8i16 (vector_shuffle
1963 VR128:$src1, (undef),
1964 PSHUFLW_shuffle_mask:$src2)))]>,
1965 XD, Requires<[HasSSE2]>;
1966 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1967 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
1968 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1969 [(set VR128:$dst, (v8i16 (vector_shuffle
1970 (bc_v8i16 (memopv2i64 addr:$src1)),
1972 PSHUFLW_shuffle_mask:$src2)))]>,
1973 XD, Requires<[HasSSE2]>;
1976 let isTwoAddress = 1 in {
1977 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1978 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1979 "punpcklbw\t{$src2, $dst|$dst, $src2}",
1981 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1982 UNPCKL_shuffle_mask)))]>;
1983 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1984 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1985 "punpcklbw\t{$src2, $dst|$dst, $src2}",
1987 (v16i8 (vector_shuffle VR128:$src1,
1988 (bc_v16i8 (memopv2i64 addr:$src2)),
1989 UNPCKL_shuffle_mask)))]>;
1990 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1991 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1992 "punpcklwd\t{$src2, $dst|$dst, $src2}",
1994 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1995 UNPCKL_shuffle_mask)))]>;
1996 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1997 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1998 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2000 (v8i16 (vector_shuffle VR128:$src1,
2001 (bc_v8i16 (memopv2i64 addr:$src2)),
2002 UNPCKL_shuffle_mask)))]>;
2003 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2004 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2005 "punpckldq\t{$src2, $dst|$dst, $src2}",
2007 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2008 UNPCKL_shuffle_mask)))]>;
2009 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2010 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2011 "punpckldq\t{$src2, $dst|$dst, $src2}",
2013 (v4i32 (vector_shuffle VR128:$src1,
2014 (bc_v4i32 (memopv2i64 addr:$src2)),
2015 UNPCKL_shuffle_mask)))]>;
2016 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2017 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2018 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2020 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2021 UNPCKL_shuffle_mask)))]>;
2022 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2023 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2024 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2026 (v2i64 (vector_shuffle VR128:$src1,
2027 (memopv2i64 addr:$src2),
2028 UNPCKL_shuffle_mask)))]>;
2030 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2031 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2032 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2034 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2035 UNPCKH_shuffle_mask)))]>;
2036 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2037 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2038 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2040 (v16i8 (vector_shuffle VR128:$src1,
2041 (bc_v16i8 (memopv2i64 addr:$src2)),
2042 UNPCKH_shuffle_mask)))]>;
2043 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2044 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2045 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2047 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2048 UNPCKH_shuffle_mask)))]>;
2049 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2050 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2051 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2053 (v8i16 (vector_shuffle VR128:$src1,
2054 (bc_v8i16 (memopv2i64 addr:$src2)),
2055 UNPCKH_shuffle_mask)))]>;
2056 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2057 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2058 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2060 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2061 UNPCKH_shuffle_mask)))]>;
2062 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2063 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2064 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2066 (v4i32 (vector_shuffle VR128:$src1,
2067 (bc_v4i32 (memopv2i64 addr:$src2)),
2068 UNPCKH_shuffle_mask)))]>;
2069 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2070 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2071 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2073 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2074 UNPCKH_shuffle_mask)))]>;
2075 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2076 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2077 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2079 (v2i64 (vector_shuffle VR128:$src1,
2080 (memopv2i64 addr:$src2),
2081 UNPCKH_shuffle_mask)))]>;
2085 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2086 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2087 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2088 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2089 (iPTR imm:$src2)))]>;
2090 let isTwoAddress = 1 in {
2091 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2092 (outs VR128:$dst), (ins VR128:$src1,
2093 GR32:$src2, i32i8imm:$src3),
2094 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2096 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2097 GR32:$src2, (iPTR imm:$src3))))]>;
2098 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2099 (outs VR128:$dst), (ins VR128:$src1,
2100 i16mem:$src2, i32i8imm:$src3),
2101 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2103 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2104 (i32 (anyext (loadi16 addr:$src2))),
2105 (iPTR imm:$src3))))]>;
2109 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2110 "pmovmskb\t{$src, $dst|$dst, $src}",
2111 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2113 // Conditional store
2115 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2116 "maskmovdqu\t{$mask, $src|$src, $mask}",
2117 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2119 // Non-temporal stores
2120 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2121 "movntpd\t{$src, $dst|$dst, $src}",
2122 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2123 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2124 "movntdq\t{$src, $dst|$dst, $src}",
2125 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2126 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2127 "movnti\t{$src, $dst|$dst, $src}",
2128 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2129 TB, Requires<[HasSSE2]>;
2132 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2133 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2134 TB, Requires<[HasSSE2]>;
2136 // Load, store, and memory fence
2137 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2138 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2139 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2140 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2142 // Alias instructions that map zero vector to pxor / xorp* for sse.
2143 let isReMaterializable = 1 in
2144 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2145 "pcmpeqd\t$dst, $dst",
2146 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2148 // FR64 to 128-bit vector conversion.
2149 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2150 "movsd\t{$src, $dst|$dst, $src}",
2152 (v2f64 (scalar_to_vector FR64:$src)))]>;
2153 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2154 "movsd\t{$src, $dst|$dst, $src}",
2156 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2158 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2159 "movd\t{$src, $dst|$dst, $src}",
2161 (v4i32 (scalar_to_vector GR32:$src)))]>;
2162 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2163 "movd\t{$src, $dst|$dst, $src}",
2165 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2167 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2168 "movd\t{$src, $dst|$dst, $src}",
2169 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2171 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2172 "movd\t{$src, $dst|$dst, $src}",
2173 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2175 // SSE2 instructions with XS prefix
2176 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2177 "movq\t{$src, $dst|$dst, $src}",
2179 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2180 Requires<[HasSSE2]>;
2181 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2182 "movq\t{$src, $dst|$dst, $src}",
2183 [(store (i64 (vector_extract (v2i64 VR128:$src),
2184 (iPTR 0))), addr:$dst)]>;
2186 // FIXME: may not be able to eliminate this movss with coalescing the src and
2187 // dest register classes are different. We really want to write this pattern
2189 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2190 // (f32 FR32:$src)>;
2191 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2192 "movsd\t{$src, $dst|$dst, $src}",
2193 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2195 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2196 "movsd\t{$src, $dst|$dst, $src}",
2197 [(store (f64 (vector_extract (v2f64 VR128:$src),
2198 (iPTR 0))), addr:$dst)]>;
2199 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2200 "movd\t{$src, $dst|$dst, $src}",
2201 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2203 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2204 "movd\t{$src, $dst|$dst, $src}",
2205 [(store (i32 (vector_extract (v4i32 VR128:$src),
2206 (iPTR 0))), addr:$dst)]>;
2208 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2209 "movd\t{$src, $dst|$dst, $src}",
2210 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2211 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2212 "movd\t{$src, $dst|$dst, $src}",
2213 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2216 // Move to lower bits of a VR128, leaving upper bits alone.
2217 // Three operand (but two address) aliases.
2218 let isTwoAddress = 1 in {
2219 let neverHasSideEffects = 1 in
2220 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2221 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2222 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2224 let AddedComplexity = 15 in
2225 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2226 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2227 "movsd\t{$src2, $dst|$dst, $src2}",
2229 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2230 MOVL_shuffle_mask)))]>;
2233 // Store / copy lower 64-bits of a XMM register.
2234 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2235 "movq\t{$src, $dst|$dst, $src}",
2236 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2238 // Move to lower bits of a VR128 and zeroing upper bits.
2239 // Loading from memory automatically zeroing upper bits.
2240 let AddedComplexity = 20 in
2241 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2242 "movsd\t{$src, $dst|$dst, $src}",
2244 (v2f64 (vector_shuffle immAllZerosV_bc,
2245 (v2f64 (scalar_to_vector
2246 (loadf64 addr:$src))),
2247 MOVL_shuffle_mask)))]>;
2249 // movd / movq to XMM register zero-extends
2250 let AddedComplexity = 15 in {
2251 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2252 "movd\t{$src, $dst|$dst, $src}",
2254 (v4i32 (vector_shuffle immAllZerosV,
2255 (v4i32 (scalar_to_vector GR32:$src)),
2256 MOVL_shuffle_mask)))]>;
2257 // This is X86-64 only.
2258 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2259 "mov{d|q}\t{$src, $dst|$dst, $src}",
2261 (v2i64 (vector_shuffle immAllZerosV_bc,
2262 (v2i64 (scalar_to_vector GR64:$src)),
2263 MOVL_shuffle_mask)))]>;
2266 let AddedComplexity = 20 in {
2267 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2268 "movd\t{$src, $dst|$dst, $src}",
2270 (v4i32 (vector_shuffle immAllZerosV,
2271 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
2272 MOVL_shuffle_mask)))]>;
2273 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2274 "movq\t{$src, $dst|$dst, $src}",
2276 (v2i64 (vector_shuffle immAllZerosV_bc,
2277 (v2i64 (scalar_to_vector (loadi64 addr:$src))),
2278 MOVL_shuffle_mask)))]>, XS,
2279 Requires<[HasSSE2]>;
2282 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2283 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2284 let AddedComplexity = 15 in
2285 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2286 "movq\t{$src, $dst|$dst, $src}",
2287 [(set VR128:$dst, (v2i64 (vector_shuffle immAllZerosV_bc,
2289 MOVL_shuffle_mask)))]>,
2290 XS, Requires<[HasSSE2]>;
2292 let AddedComplexity = 20 in
2293 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2294 "movq\t{$src, $dst|$dst, $src}",
2295 [(set VR128:$dst, (v2i64 (vector_shuffle immAllZerosV_bc,
2296 (memopv2i64 addr:$src),
2297 MOVL_shuffle_mask)))]>,
2298 XS, Requires<[HasSSE2]>;
2300 //===----------------------------------------------------------------------===//
2301 // SSE3 Instructions
2302 //===----------------------------------------------------------------------===//
2304 // Move Instructions
2305 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2306 "movshdup\t{$src, $dst|$dst, $src}",
2307 [(set VR128:$dst, (v4f32 (vector_shuffle
2308 VR128:$src, (undef),
2309 MOVSHDUP_shuffle_mask)))]>;
2310 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2311 "movshdup\t{$src, $dst|$dst, $src}",
2312 [(set VR128:$dst, (v4f32 (vector_shuffle
2313 (memopv4f32 addr:$src), (undef),
2314 MOVSHDUP_shuffle_mask)))]>;
2316 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2317 "movsldup\t{$src, $dst|$dst, $src}",
2318 [(set VR128:$dst, (v4f32 (vector_shuffle
2319 VR128:$src, (undef),
2320 MOVSLDUP_shuffle_mask)))]>;
2321 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2322 "movsldup\t{$src, $dst|$dst, $src}",
2323 [(set VR128:$dst, (v4f32 (vector_shuffle
2324 (memopv4f32 addr:$src), (undef),
2325 MOVSLDUP_shuffle_mask)))]>;
2327 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2328 "movddup\t{$src, $dst|$dst, $src}",
2329 [(set VR128:$dst, (v2f64 (vector_shuffle
2330 VR128:$src, (undef),
2331 SSE_splat_lo_mask)))]>;
2332 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2333 "movddup\t{$src, $dst|$dst, $src}",
2335 (v2f64 (vector_shuffle
2336 (scalar_to_vector (loadf64 addr:$src)),
2338 SSE_splat_lo_mask)))]>;
2341 let isTwoAddress = 1 in {
2342 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2343 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2344 "addsubps\t{$src2, $dst|$dst, $src2}",
2345 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2347 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2348 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2349 "addsubps\t{$src2, $dst|$dst, $src2}",
2350 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2351 (load addr:$src2)))]>;
2352 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2353 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2354 "addsubpd\t{$src2, $dst|$dst, $src2}",
2355 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2357 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2358 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2359 "addsubpd\t{$src2, $dst|$dst, $src2}",
2360 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2361 (load addr:$src2)))]>;
2364 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2365 "lddqu\t{$src, $dst|$dst, $src}",
2366 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2369 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2370 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2371 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2372 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2373 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2374 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2375 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2376 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
2377 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2378 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2379 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2380 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2381 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2382 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2383 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2384 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
2386 let isTwoAddress = 1 in {
2387 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2388 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2389 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2390 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2391 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2392 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2393 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2394 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2397 // Thread synchronization
2398 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2399 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2400 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2401 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2403 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2404 let AddedComplexity = 15 in
2405 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2406 MOVSHDUP_shuffle_mask)),
2407 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2408 let AddedComplexity = 20 in
2409 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2410 MOVSHDUP_shuffle_mask)),
2411 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2413 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2414 let AddedComplexity = 15 in
2415 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2416 MOVSLDUP_shuffle_mask)),
2417 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2418 let AddedComplexity = 20 in
2419 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2420 MOVSLDUP_shuffle_mask)),
2421 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2423 //===----------------------------------------------------------------------===//
2424 // SSSE3 Instructions
2425 //===----------------------------------------------------------------------===//
2427 // SSSE3 Instruction Templates:
2429 // SS38I - SSSE3 instructions with T8 prefix.
2430 // SS3AI - SSSE3 instructions with TA prefix.
2432 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
2433 // uses the MMX registers. We put those instructions here because they better
2434 // fit into the SSSE3 instruction category rather than the MMX category.
2436 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
2438 : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSSE3]>;
2439 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
2441 : I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSSE3]>;
2443 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2444 let isTwoAddress = 1 in {
2445 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2446 Intrinsic IntId64, Intrinsic IntId128,
2447 bit Commutable = 0> {
2448 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2449 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2450 [(set VR64:$dst, (IntId64 VR64:$src))]> {
2451 let isCommutable = Commutable;
2453 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2454 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2456 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2458 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2460 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2461 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2463 let isCommutable = Commutable;
2465 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2467 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2470 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2474 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2475 let isTwoAddress = 1 in {
2476 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2477 Intrinsic IntId64, Intrinsic IntId128,
2478 bit Commutable = 0> {
2479 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2481 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2482 [(set VR64:$dst, (IntId64 VR64:$src))]> {
2483 let isCommutable = Commutable;
2485 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2487 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2490 (bitconvert (memopv4i16 addr:$src))))]>;
2492 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2494 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2495 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2497 let isCommutable = Commutable;
2499 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2501 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2504 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2508 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2509 let isTwoAddress = 1 in {
2510 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2511 Intrinsic IntId64, Intrinsic IntId128,
2512 bit Commutable = 0> {
2513 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2515 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2516 [(set VR64:$dst, (IntId64 VR64:$src))]> {
2517 let isCommutable = Commutable;
2519 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2521 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2524 (bitconvert (memopv2i32 addr:$src))))]>;
2526 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2528 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2529 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2531 let isCommutable = Commutable;
2533 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2535 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2538 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2542 // FIXME: are these really two-address?
2543 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2544 int_x86_ssse3_pabs_b,
2545 int_x86_ssse3_pabs_b_128>;
2546 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2547 int_x86_ssse3_pabs_w,
2548 int_x86_ssse3_pabs_w_128>;
2549 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2550 int_x86_ssse3_pabs_d,
2551 int_x86_ssse3_pabs_d_128>;
2553 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2554 let isTwoAddress = 1 in {
2555 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2556 Intrinsic IntId64, Intrinsic IntId128,
2557 bit Commutable = 0> {
2558 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2559 (ins VR64:$src1, VR64:$src2),
2560 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2561 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2562 let isCommutable = Commutable;
2564 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2565 (ins VR64:$src1, i64mem:$src2),
2566 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2568 (IntId64 VR64:$src1,
2569 (bitconvert (memopv8i8 addr:$src2))))]>;
2571 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2572 (ins VR128:$src1, VR128:$src2),
2573 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2574 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2576 let isCommutable = Commutable;
2578 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2579 (ins VR128:$src1, i128mem:$src2),
2580 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2582 (IntId128 VR128:$src1,
2583 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2587 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2588 let isTwoAddress = 1 in {
2589 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2590 Intrinsic IntId64, Intrinsic IntId128,
2591 bit Commutable = 0> {
2592 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2593 (ins VR64:$src1, VR64:$src2),
2594 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2595 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2596 let isCommutable = Commutable;
2598 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2599 (ins VR64:$src1, i64mem:$src2),
2600 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2602 (IntId64 VR64:$src1,
2603 (bitconvert (memopv4i16 addr:$src2))))]>;
2605 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2606 (ins VR128:$src1, VR128:$src2),
2607 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2608 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2610 let isCommutable = Commutable;
2612 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2613 (ins VR128:$src1, i128mem:$src2),
2614 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2616 (IntId128 VR128:$src1,
2617 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2621 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2622 let isTwoAddress = 1 in {
2623 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2624 Intrinsic IntId64, Intrinsic IntId128,
2625 bit Commutable = 0> {
2626 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2627 (ins VR64:$src1, VR64:$src2),
2628 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2629 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2630 let isCommutable = Commutable;
2632 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2633 (ins VR64:$src1, i64mem:$src2),
2634 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2636 (IntId64 VR64:$src1,
2637 (bitconvert (memopv2i32 addr:$src2))))]>;
2639 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2640 (ins VR128:$src1, VR128:$src2),
2641 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2642 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2644 let isCommutable = Commutable;
2646 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2647 (ins VR128:$src1, i128mem:$src2),
2648 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2650 (IntId128 VR128:$src1,
2651 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2655 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2656 int_x86_ssse3_phadd_w,
2657 int_x86_ssse3_phadd_w_128, 1>;
2658 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2659 int_x86_ssse3_phadd_d,
2660 int_x86_ssse3_phadd_d_128, 1>;
2661 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2662 int_x86_ssse3_phadd_sw,
2663 int_x86_ssse3_phadd_sw_128, 1>;
2664 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2665 int_x86_ssse3_phsub_w,
2666 int_x86_ssse3_phsub_w_128>;
2667 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2668 int_x86_ssse3_phsub_d,
2669 int_x86_ssse3_phsub_d_128>;
2670 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2671 int_x86_ssse3_phsub_sw,
2672 int_x86_ssse3_phsub_sw_128>;
2673 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2674 int_x86_ssse3_pmadd_ub_sw,
2675 int_x86_ssse3_pmadd_ub_sw_128, 1>;
2676 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2677 int_x86_ssse3_pmul_hr_sw,
2678 int_x86_ssse3_pmul_hr_sw_128, 1>;
2679 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2680 int_x86_ssse3_pshuf_b,
2681 int_x86_ssse3_pshuf_b_128>;
2682 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2683 int_x86_ssse3_psign_b,
2684 int_x86_ssse3_psign_b_128>;
2685 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2686 int_x86_ssse3_psign_w,
2687 int_x86_ssse3_psign_w_128>;
2688 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2689 int_x86_ssse3_psign_d,
2690 int_x86_ssse3_psign_d_128>;
2692 let isTwoAddress = 1 in {
2693 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2694 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2695 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2697 (int_x86_ssse3_palign_r
2698 VR64:$src1, VR64:$src2,
2700 def PALIGNR64rm : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2701 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2702 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2704 (int_x86_ssse3_palign_r
2706 (bitconvert (memopv2i32 addr:$src2)),
2709 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2710 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2711 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2713 (int_x86_ssse3_palign_r_128
2714 VR128:$src1, VR128:$src2,
2715 imm:$src3))]>, OpSize;
2716 def PALIGNR128rm : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2717 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2718 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2720 (int_x86_ssse3_palign_r_128
2722 (bitconvert (memopv4i32 addr:$src2)),
2723 imm:$src3))]>, OpSize;
2726 //===----------------------------------------------------------------------===//
2727 // Non-Instruction Patterns
2728 //===----------------------------------------------------------------------===//
2730 // 128-bit vector undef's.
2731 def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2732 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2733 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2734 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2735 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2736 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2738 // extload f32 -> f64. This matches load+fextend because we have a hack in
2739 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2740 // Since these loads aren't folded into the fextend, we have to match it
2742 let Predicates = [HasSSE2] in
2743 def : Pat<(fextend (loadf32 addr:$src)),
2744 (CVTSS2SDrm addr:$src)>;
2746 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
2748 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2749 Requires<[HasSSE2]>;
2750 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2751 Requires<[HasSSE2]>;
2754 let Predicates = [HasSSE2] in {
2755 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2756 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2757 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2758 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2759 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2760 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2761 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2762 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2763 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2764 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2765 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2766 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2767 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2768 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2769 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2770 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2771 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2772 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2773 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2774 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2775 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2776 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2777 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2778 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2779 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2780 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2781 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2782 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2783 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2784 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2787 // Move scalar to XMM zero-extended
2788 // movd to XMM register zero-extends
2789 let AddedComplexity = 15 in {
2790 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2791 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc,
2792 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2793 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2794 def : Pat<(v4f32 (vector_shuffle immAllZerosV_bc,
2795 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2796 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2799 // Splat v2f64 / v2i64
2800 let AddedComplexity = 10 in {
2801 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2802 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2803 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2804 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2805 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2806 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2807 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2808 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2812 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2813 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
2814 Requires<[HasSSE1]>;
2816 // Special unary SHUFPSrri case.
2817 // FIXME: when we want non two-address code, then we should use PSHUFD?
2818 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2819 SHUFP_unary_shuffle_mask:$sm)),
2820 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2821 Requires<[HasSSE1]>;
2822 // Special unary SHUFPDrri case.
2823 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2824 SHUFP_unary_shuffle_mask:$sm)),
2825 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2826 Requires<[HasSSE2]>;
2827 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2828 def : Pat<(vector_shuffle (memopv4f32 addr:$src1), (undef),
2829 SHUFP_unary_shuffle_mask:$sm),
2830 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2831 Requires<[HasSSE2]>;
2832 // Special binary v4i32 shuffle cases with SHUFPS.
2833 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2834 PSHUFD_binary_shuffle_mask:$sm)),
2835 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2836 Requires<[HasSSE2]>;
2837 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2838 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2839 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2840 Requires<[HasSSE2]>;
2841 // Special binary v2i64 shuffle cases using SHUFPDrri.
2842 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2843 SHUFP_shuffle_mask:$sm)),
2844 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2845 Requires<[HasSSE2]>;
2846 // Special unary SHUFPDrri case.
2847 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2848 SHUFP_unary_shuffle_mask:$sm)),
2849 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2850 Requires<[HasSSE2]>;
2852 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2853 let AddedComplexity = 10 in {
2854 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2855 UNPCKL_v_undef_shuffle_mask)),
2856 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2857 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2858 UNPCKL_v_undef_shuffle_mask)),
2859 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2860 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2861 UNPCKL_v_undef_shuffle_mask)),
2862 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2863 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2864 UNPCKL_v_undef_shuffle_mask)),
2865 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2868 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2869 let AddedComplexity = 10 in {
2870 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2871 UNPCKH_v_undef_shuffle_mask)),
2872 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2873 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2874 UNPCKH_v_undef_shuffle_mask)),
2875 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2876 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2877 UNPCKH_v_undef_shuffle_mask)),
2878 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2879 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2880 UNPCKH_v_undef_shuffle_mask)),
2881 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2884 let AddedComplexity = 15 in {
2885 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2886 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2887 MOVHP_shuffle_mask)),
2888 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2890 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2891 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2892 MOVHLPS_shuffle_mask)),
2893 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2895 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2896 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2897 MOVHLPS_v_undef_shuffle_mask)),
2898 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2899 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2900 MOVHLPS_v_undef_shuffle_mask)),
2901 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2904 let AddedComplexity = 20 in {
2905 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2906 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2907 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2908 MOVLP_shuffle_mask)),
2909 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2910 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2911 MOVLP_shuffle_mask)),
2912 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2913 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2914 MOVHP_shuffle_mask)),
2915 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2916 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2917 MOVHP_shuffle_mask)),
2918 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2920 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2921 MOVLP_shuffle_mask)),
2922 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2923 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2924 MOVLP_shuffle_mask)),
2925 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2926 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2927 MOVHP_shuffle_mask)),
2928 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2929 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2930 MOVLP_shuffle_mask)),
2931 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2934 let AddedComplexity = 15 in {
2935 // Setting the lowest element in the vector.
2936 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2937 MOVL_shuffle_mask)),
2938 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2939 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2940 MOVL_shuffle_mask)),
2941 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2943 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2944 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2945 MOVLP_shuffle_mask)),
2946 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2947 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2948 MOVLP_shuffle_mask)),
2949 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2952 // Set lowest element and zero upper elements.
2953 let AddedComplexity = 15 in
2954 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
2955 MOVL_shuffle_mask)),
2956 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
2959 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2960 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2961 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2962 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2963 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2964 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2965 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2966 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2967 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2968 Requires<[HasSSE2]>;
2969 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2970 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2971 Requires<[HasSSE2]>;
2972 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2973 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2974 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2975 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2976 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2977 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2978 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2979 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2980 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2981 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2982 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2983 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2984 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2985 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2986 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2987 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2989 // Some special case pandn patterns.
2990 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2992 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2993 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2995 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2996 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2998 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3000 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3001 (memopv2i64 addr:$src2))),
3002 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3003 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3004 (memopv2i64 addr:$src2))),
3005 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3006 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3007 (memopv2i64 addr:$src2))),
3008 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3010 // vector -> vector casts
3011 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3012 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3013 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3014 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3016 // Use movaps / movups for SSE integer load / store (one byte shorter).
3017 def : Pat<(alignedloadv4i32 addr:$src),
3018 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3019 def : Pat<(loadv4i32 addr:$src),
3020 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3021 def : Pat<(alignedloadv2i64 addr:$src),
3022 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3023 def : Pat<(loadv2i64 addr:$src),
3024 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3026 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3027 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3028 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3029 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3030 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3031 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3032 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3033 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3034 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3035 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3036 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3037 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3038 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3039 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3040 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3041 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3043 //===----------------------------------------------------------------------===//
3044 // SSE4.1 Instructions
3045 //===----------------------------------------------------------------------===//
3047 // SSE4.1 Instruction Templates:
3049 // SS48I - SSE 4.1 instructions with T8 prefix.
3050 // SS41AI - SSE 4.1 instructions with TA prefix.
3052 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
3054 : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE41]>;
3055 class SS4AI<bits<8> o, Format F, dag outs, dag ins, string asm,
3057 : I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE41]>;
3060 multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
3061 bits<8> opcsd, bits<8> opcpd,
3066 Intrinsic V2F64Int> {
3067 // Intrinsic operation, reg.
3068 def SSr_Int : SS4AI<opcss, MRMSrcReg,
3069 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3070 !strconcat(OpcodeStr,
3071 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3072 [(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
3075 // Intrinsic operation, mem.
3076 def SSm_Int : SS4AI<opcss, MRMSrcMem,
3077 (outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
3078 !strconcat(OpcodeStr,
3079 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3080 [(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
3083 // Vector intrinsic operation, reg
3084 def PSr_Int : SS4AI<opcps, MRMSrcReg,
3085 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3086 !strconcat(OpcodeStr,
3087 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3088 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3091 // Vector intrinsic operation, mem
3092 def PSm_Int : SS4AI<opcps, MRMSrcMem,
3093 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3094 !strconcat(OpcodeStr,
3095 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3096 [(set VR128:$dst, (V4F32Int (load addr:$src1),imm:$src2))]>,
3099 // Intrinsic operation, reg.
3100 def SDr_Int : SS4AI<opcsd, MRMSrcReg,
3101 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3102 !strconcat(OpcodeStr,
3103 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3104 [(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
3107 // Intrinsic operation, mem.
3108 def SDm_Int : SS4AI<opcsd, MRMSrcMem,
3109 (outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
3110 !strconcat(OpcodeStr,
3111 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3112 [(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
3115 // Vector intrinsic operation, reg
3116 def PDr_Int : SS4AI<opcpd, MRMSrcReg,
3117 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3118 !strconcat(OpcodeStr,
3119 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3120 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3123 // Vector intrinsic operation, mem
3124 def PDm_Int : SS4AI<opcpd, MRMSrcMem,
3125 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3126 !strconcat(OpcodeStr,
3127 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3128 [(set VR128:$dst, (V2F64Int (load addr:$src1),imm:$src2))]>,
3132 // FP round - roundss, roundps, roundsd, roundpd
3133 defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
3134 int_x86_sse41_round_ss, int_x86_sse41_round_ps,
3135 int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
3137 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3138 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3139 Intrinsic IntId128> {
3140 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3142 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3143 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3144 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3146 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3149 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3152 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3153 int_x86_sse41_phminposuw>;
3155 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3156 let isTwoAddress = 1 in {
3157 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3158 Intrinsic IntId128, bit Commutable = 0> {
3159 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3160 (ins VR128:$src1, VR128:$src2),
3161 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3162 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3164 let isCommutable = Commutable;
3166 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3167 (ins VR128:$src1, i128mem:$src2),
3168 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3170 (IntId128 VR128:$src1,
3171 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3175 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3176 int_x86_sse41_pcmpeqq, 1>;
3177 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3178 int_x86_sse41_packusdw, 0>;
3179 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3180 int_x86_sse41_pminsb, 1>;
3181 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3182 int_x86_sse41_pminsd, 1>;
3183 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3184 int_x86_sse41_pminud, 1>;
3185 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3186 int_x86_sse41_pminuw, 1>;
3187 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3188 int_x86_sse41_pmaxsb, 1>;
3189 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3190 int_x86_sse41_pmaxsd, 1>;
3191 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3192 int_x86_sse41_pmaxud, 1>;
3193 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3194 int_x86_sse41_pmaxuw, 1>;
3195 defm PMULLD : SS41I_binop_rm_int<0x40, "pmulld",
3196 int_x86_sse41_pmulld, 1>;
3197 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq",
3198 int_x86_sse41_pmuldq, 1>;
3200 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with immediate
3201 let isTwoAddress = 1 in {
3202 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3203 Intrinsic IntId128, bit Commutable = 0> {
3204 def rri128 : SS4AI<opc, MRMSrcReg, (outs VR128:$dst),
3205 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3206 !strconcat(OpcodeStr,
3207 "\t{$$src3, src2, $dst|$dst, $src2, $src3}"),
3209 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3211 let isCommutable = Commutable;
3213 def rmi128 : SS4AI<opc, MRMSrcMem, (outs VR128:$dst),
3214 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3215 !strconcat(OpcodeStr,
3216 "\t{$$src3, src2, $dst|$dst, $src2, $src3}"),
3218 (IntId128 VR128:$src1,
3219 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3224 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3225 int_x86_sse41_blendps, 0>;
3226 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3227 int_x86_sse41_blendpd, 0>;
3228 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3229 int_x86_sse41_pblendw, 0>;
3230 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3231 int_x86_sse41_dpps, 1>;
3232 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3233 int_x86_sse41_dppd, 1>;
3234 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3235 int_x86_sse41_mpsadbw, 0>;