1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
246 let isCommutable = 1 in {
247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
252 Sched<[itins.Sched]>;
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
262 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
263 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
264 string asm, string SSEVer, string FPSizeStr,
265 Operand memopr, ComplexPattern mem_cpat,
268 let isCodeGenOnly = 1 in {
269 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
271 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
272 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 [(set RC:$dst, (!cast<Intrinsic>(
274 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
275 RC:$src1, RC:$src2))], itins.rr>,
276 Sched<[itins.Sched]>;
277 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
279 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
280 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
281 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
282 SSEVer, "_", OpcodeStr, FPSizeStr))
283 RC:$src1, mem_cpat:$src2))], itins.rm>,
284 Sched<[itins.Sched.Folded, ReadAfterLd]>;
288 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
290 RegisterClass RC, ValueType vt,
291 X86MemOperand x86memop, PatFrag mem_frag,
292 Domain d, OpndItins itins, bit Is2Addr = 1> {
293 let isCommutable = 1 in
294 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
297 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
299 Sched<[itins.Sched]>;
301 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
307 Sched<[itins.Sched.Folded, ReadAfterLd]>;
310 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
311 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
312 string OpcodeStr, X86MemOperand x86memop,
313 list<dag> pat_rr, list<dag> pat_rm,
315 let isCommutable = 1, hasSideEffects = 0 in
316 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
320 pat_rr, NoItinerary, d>,
321 Sched<[WriteVecLogic]>;
322 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
326 pat_rm, NoItinerary, d>,
327 Sched<[WriteVecLogicLd, ReadAfterLd]>;
330 //===----------------------------------------------------------------------===//
331 // Non-instruction patterns
332 //===----------------------------------------------------------------------===//
334 // A vector extract of the first f32/f64 position is a subregister copy
335 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
337 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
338 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
340 // A 128-bit subvector extract from the first 256-bit vector position
341 // is a subregister copy that needs no instruction.
342 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
343 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
347 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
348 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
353 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
357 // A 128-bit subvector insert to the first 256-bit vector position
358 // is a subregister copy that needs no instruction.
359 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
360 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
374 // Implicitly promote a 32-bit scalar to a vector.
375 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
378 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 // Implicitly promote a 64-bit scalar to a vector.
380 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
382 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
383 (COPY_TO_REGCLASS FR64:$src, VR128)>;
385 // Bitcasts between 128-bit vector types. Return the original type since
386 // no instruction is needed for the conversion
387 let Predicates = [HasSSE2] in {
388 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
397 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
402 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
407 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
417 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr> {
570 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
571 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
574 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
576 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
577 VEX, VEX_LIG, Sched<[WriteStore]>;
579 let Constraints = "$src1 = $dst" in {
580 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
581 "\t{$src2, $dst|$dst, $src2}">;
584 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
586 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
590 // Loading from memory automatically zeroing upper bits.
591 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
592 PatFrag mem_pat, string OpcodeStr> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
604 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
606 let canFoldAsLoad = 1, isReMaterializable = 1 in {
607 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
609 let AddedComplexity = 20 in
610 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
614 let Predicates = [UseAVX] in {
615 let AddedComplexity = 20 in {
616 // MOVSSrm zeros the high parts of the register; represent this
617 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
618 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
619 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
620 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
621 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
622 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
625 // MOVSDrm zeros the high parts of the register; represent this
626 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
627 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
628 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
629 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
630 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
631 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzload addr:$src)),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
638 // Represent the same patterns above but in the form they appear for
640 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
641 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
642 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
643 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
644 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
645 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
646 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
647 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
648 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
650 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
651 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
652 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
654 // Extract and store.
655 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
657 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
658 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
660 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
662 // Shuffle with VMOVSS
663 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
664 (VMOVSSrr (v4i32 VR128:$src1),
665 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
666 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
667 (VMOVSSrr (v4f32 VR128:$src1),
668 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
671 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
672 (SUBREG_TO_REG (i32 0),
673 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
674 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
676 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
677 (SUBREG_TO_REG (i32 0),
678 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
679 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
682 // Shuffle with VMOVSD
683 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
689 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
690 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
693 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
694 (SUBREG_TO_REG (i32 0),
695 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
696 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
698 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
699 (SUBREG_TO_REG (i32 0),
700 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
701 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
704 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
705 // is during lowering, where it's not possible to recognize the fold cause
706 // it has two uses through a bitcast. One use disappears at isel time and the
707 // fold opportunity reappears.
708 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
714 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
715 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
718 let Predicates = [UseSSE1] in {
719 let Predicates = [NoSSE41], AddedComplexity = 15 in {
720 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
721 // MOVSS to the lower bits.
722 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
723 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
724 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
725 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
726 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
727 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
730 let AddedComplexity = 20 in {
731 // MOVSSrm already zeros the high parts of the register.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
743 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
745 // Shuffle with MOVSS
746 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
748 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
749 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
752 let Predicates = [UseSSE2] in {
753 let Predicates = [NoSSE41], AddedComplexity = 15 in {
754 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
755 // MOVSD to the lower bits.
756 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
757 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
760 let AddedComplexity = 20 in {
761 // MOVSDrm already zeros the high parts of the register.
762 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
770 def : Pat<(v2f64 (X86vzload addr:$src)),
771 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
774 // Extract and store.
775 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
777 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
779 // Shuffle with MOVSD
780 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
786 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
787 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
789 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
790 // is during lowering, where it's not possible to recognize the fold cause
791 // it has two uses through a bitcast. One use disappears at isel time and the
792 // fold opportunity reappears.
793 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
799 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
800 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
803 //===----------------------------------------------------------------------===//
804 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
805 //===----------------------------------------------------------------------===//
807 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
808 X86MemOperand x86memop, PatFrag ld_frag,
809 string asm, Domain d,
811 bit IsReMaterializable = 1> {
812 let hasSideEffects = 0 in
813 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
814 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
815 Sched<[WriteFShuffle]>;
816 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
817 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
818 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
819 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
823 let Predicates = [HasAVX, NoVLX] in {
824 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
830 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
837 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
838 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
840 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
841 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
843 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
844 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
846 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
847 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
851 let Predicates = [UseSSE1] in {
852 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
853 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
855 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
856 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
859 let Predicates = [UseSSE2] in {
860 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
861 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
863 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
864 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
868 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
869 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
870 "movaps\t{$src, $dst|$dst, $src}",
871 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
872 IIC_SSE_MOVA_P_MR>, VEX;
873 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
874 "movapd\t{$src, $dst|$dst, $src}",
875 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
876 IIC_SSE_MOVA_P_MR>, VEX;
877 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
878 "movups\t{$src, $dst|$dst, $src}",
879 [(store (v4f32 VR128:$src), addr:$dst)],
880 IIC_SSE_MOVU_P_MR>, VEX;
881 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
882 "movupd\t{$src, $dst|$dst, $src}",
883 [(store (v2f64 VR128:$src), addr:$dst)],
884 IIC_SSE_MOVU_P_MR>, VEX;
885 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
886 "movaps\t{$src, $dst|$dst, $src}",
887 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
888 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
889 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
890 "movapd\t{$src, $dst|$dst, $src}",
891 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
892 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
893 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
894 "movups\t{$src, $dst|$dst, $src}",
895 [(store (v8f32 VR256:$src), addr:$dst)],
896 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
897 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
898 "movupd\t{$src, $dst|$dst, $src}",
899 [(store (v4f64 VR256:$src), addr:$dst)],
900 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
904 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
905 SchedRW = [WriteFShuffle] in {
906 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
908 "movaps\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX;
910 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
912 "movapd\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVA_P_RR>, VEX;
914 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
916 "movups\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX;
918 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
920 "movupd\t{$src, $dst|$dst, $src}", [],
921 IIC_SSE_MOVU_P_RR>, VEX;
922 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
924 "movaps\t{$src, $dst|$dst, $src}", [],
925 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
926 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
928 "movapd\t{$src, $dst|$dst, $src}", [],
929 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
930 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
932 "movups\t{$src, $dst|$dst, $src}", [],
933 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
934 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
936 "movupd\t{$src, $dst|$dst, $src}", [],
937 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
940 let Predicates = [HasAVX] in {
941 def : Pat<(v8i32 (X86vzmovl
942 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
943 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
944 def : Pat<(v4i64 (X86vzmovl
945 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
946 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
947 def : Pat<(v8f32 (X86vzmovl
948 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
949 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
950 def : Pat<(v4f64 (X86vzmovl
951 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
952 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
956 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
957 (VMOVUPSYmr addr:$dst, VR256:$src)>;
958 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
959 (VMOVUPDYmr addr:$dst, VR256:$src)>;
961 let SchedRW = [WriteStore] in {
962 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
963 "movaps\t{$src, $dst|$dst, $src}",
964 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
966 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
967 "movapd\t{$src, $dst|$dst, $src}",
968 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
970 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
971 "movups\t{$src, $dst|$dst, $src}",
972 [(store (v4f32 VR128:$src), addr:$dst)],
974 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
975 "movupd\t{$src, $dst|$dst, $src}",
976 [(store (v2f64 VR128:$src), addr:$dst)],
981 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
982 SchedRW = [WriteFShuffle] in {
983 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
984 "movaps\t{$src, $dst|$dst, $src}", [],
986 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
987 "movapd\t{$src, $dst|$dst, $src}", [],
989 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
990 "movups\t{$src, $dst|$dst, $src}", [],
992 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
993 "movupd\t{$src, $dst|$dst, $src}", [],
997 let Predicates = [HasAVX] in {
998 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
999 (VMOVUPSmr addr:$dst, VR128:$src)>;
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (VMOVUPDmr addr:$dst, VR128:$src)>;
1004 let Predicates = [UseSSE1] in
1005 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1006 (MOVUPSmr addr:$dst, VR128:$src)>;
1007 let Predicates = [UseSSE2] in
1008 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1009 (MOVUPDmr addr:$dst, VR128:$src)>;
1011 // Use vmovaps/vmovups for AVX integer load/store.
1012 let Predicates = [HasAVX, NoVLX] in {
1013 // 128-bit load/store
1014 def : Pat<(alignedloadv2i64 addr:$src),
1015 (VMOVAPSrm addr:$src)>;
1016 def : Pat<(loadv2i64 addr:$src),
1017 (VMOVUPSrm addr:$src)>;
1019 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1026 (VMOVAPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1033 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1034 (VMOVUPSmr addr:$dst, VR128:$src)>;
1036 // 256-bit load/store
1037 def : Pat<(alignedloadv4i64 addr:$src),
1038 (VMOVAPSYrm addr:$src)>;
1039 def : Pat<(loadv4i64 addr:$src),
1040 (VMOVUPSYrm addr:$src)>;
1041 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1048 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1055 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1056 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1058 // Special patterns for storing subvector extracts of lower 128-bits
1059 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1060 def : Pat<(alignedstore (v2f64 (extract_subvector
1061 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1062 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1063 def : Pat<(alignedstore (v4f32 (extract_subvector
1064 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1065 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1066 def : Pat<(alignedstore (v2i64 (extract_subvector
1067 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1068 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1069 def : Pat<(alignedstore (v4i32 (extract_subvector
1070 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1071 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1072 def : Pat<(alignedstore (v8i16 (extract_subvector
1073 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1074 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1075 def : Pat<(alignedstore (v16i8 (extract_subvector
1076 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1077 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1079 def : Pat<(store (v2f64 (extract_subvector
1080 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1081 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1082 def : Pat<(store (v4f32 (extract_subvector
1083 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1084 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1085 def : Pat<(store (v2i64 (extract_subvector
1086 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1087 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1088 def : Pat<(store (v4i32 (extract_subvector
1089 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1090 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1091 def : Pat<(store (v8i16 (extract_subvector
1092 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1093 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1094 def : Pat<(store (v16i8 (extract_subvector
1095 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1096 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1099 // Use movaps / movups for SSE integer load / store (one byte shorter).
1100 // The instructions selected below are then converted to MOVDQA/MOVDQU
1101 // during the SSE domain pass.
1102 let Predicates = [UseSSE1] in {
1103 def : Pat<(alignedloadv2i64 addr:$src),
1104 (MOVAPSrm addr:$src)>;
1105 def : Pat<(loadv2i64 addr:$src),
1106 (MOVUPSrm addr:$src)>;
1108 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1115 (MOVAPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1122 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1123 (MOVUPSmr addr:$dst, VR128:$src)>;
1126 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1127 // bits are disregarded. FIXME: Set encoding to pseudo!
1128 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1129 let isCodeGenOnly = 1 in {
1130 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1131 "movaps\t{$src, $dst|$dst, $src}",
1132 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1133 IIC_SSE_MOVA_P_RM>, VEX;
1134 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1135 "movapd\t{$src, $dst|$dst, $src}",
1136 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1137 IIC_SSE_MOVA_P_RM>, VEX;
1138 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1139 "movaps\t{$src, $dst|$dst, $src}",
1140 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1142 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1143 "movapd\t{$src, $dst|$dst, $src}",
1144 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1149 //===----------------------------------------------------------------------===//
1150 // SSE 1 & 2 - Move Low packed FP Instructions
1151 //===----------------------------------------------------------------------===//
1153 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1154 string base_opc, string asm_opr,
1155 InstrItinClass itin> {
1156 def PSrm : PI<opc, MRMSrcMem,
1157 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1158 !strconcat(base_opc, "s", asm_opr),
1160 (psnode VR128:$src1,
1161 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1162 itin, SSEPackedSingle>, PS,
1163 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1165 def PDrm : PI<opc, MRMSrcMem,
1166 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1167 !strconcat(base_opc, "d", asm_opr),
1168 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1169 (scalar_to_vector (loadf64 addr:$src2)))))],
1170 itin, SSEPackedDouble>, PD,
1171 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1175 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1176 string base_opc, InstrItinClass itin> {
1177 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1178 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1181 let Constraints = "$src1 = $dst" in
1182 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1183 "\t{$src2, $dst|$dst, $src2}",
1187 let AddedComplexity = 20 in {
1188 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1192 let SchedRW = [WriteStore] in {
1193 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1194 "movlps\t{$src, $dst|$dst, $src}",
1195 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1196 (iPTR 0))), addr:$dst)],
1197 IIC_SSE_MOV_LH>, VEX;
1198 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1199 "movlpd\t{$src, $dst|$dst, $src}",
1200 [(store (f64 (vector_extract (v2f64 VR128:$src),
1201 (iPTR 0))), addr:$dst)],
1202 IIC_SSE_MOV_LH>, VEX;
1203 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1204 "movlps\t{$src, $dst|$dst, $src}",
1205 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1206 (iPTR 0))), addr:$dst)],
1208 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1209 "movlpd\t{$src, $dst|$dst, $src}",
1210 [(store (f64 (vector_extract (v2f64 VR128:$src),
1211 (iPTR 0))), addr:$dst)],
1215 let Predicates = [HasAVX] in {
1216 // Shuffle with VMOVLPS
1217 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1219 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1220 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1222 // Shuffle with VMOVLPD
1223 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1226 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1227 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1228 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1229 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1232 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1234 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1235 def : Pat<(store (v4i32 (X86Movlps
1236 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1237 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1238 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1240 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1243 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1246 let Predicates = [UseSSE1] in {
1247 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1248 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1249 (iPTR 0))), addr:$src1),
1250 (MOVLPSmr addr:$src1, VR128:$src2)>;
1252 // Shuffle with MOVLPS
1253 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1256 (MOVLPSrm VR128:$src1, addr:$src2)>;
1257 def : Pat<(X86Movlps VR128:$src1,
1258 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1259 (MOVLPSrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1264 (MOVLPSmr addr:$src1, VR128:$src2)>;
1265 def : Pat<(store (v4i32 (X86Movlps
1266 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1268 (MOVLPSmr addr:$src1, VR128:$src2)>;
1271 let Predicates = [UseSSE2] in {
1272 // Shuffle with MOVLPD
1273 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1276 (MOVLPDrm VR128:$src1, addr:$src2)>;
1277 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1278 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1279 (MOVLPDrm VR128:$src1, addr:$src2)>;
1282 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1284 (MOVLPDmr addr:$src1, VR128:$src2)>;
1285 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1287 (MOVLPDmr addr:$src1, VR128:$src2)>;
1290 //===----------------------------------------------------------------------===//
1291 // SSE 1 & 2 - Move Hi packed FP Instructions
1292 //===----------------------------------------------------------------------===//
1294 let AddedComplexity = 20 in {
1295 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1299 let SchedRW = [WriteStore] in {
1300 // v2f64 extract element 1 is always custom lowered to unpack high to low
1301 // and extract element 0 so the non-store version isn't too horrible.
1302 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1303 "movhps\t{$src, $dst|$dst, $src}",
1304 [(store (f64 (vector_extract
1305 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1306 (bc_v2f64 (v4f32 VR128:$src))),
1307 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1308 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1309 "movhpd\t{$src, $dst|$dst, $src}",
1310 [(store (f64 (vector_extract
1311 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1312 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1313 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1314 "movhps\t{$src, $dst|$dst, $src}",
1315 [(store (f64 (vector_extract
1316 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1317 (bc_v2f64 (v4f32 VR128:$src))),
1318 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1319 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1320 "movhpd\t{$src, $dst|$dst, $src}",
1321 [(store (f64 (vector_extract
1322 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1323 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1326 let Predicates = [HasAVX] in {
1328 def : Pat<(X86Movlhps VR128:$src1,
1329 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1330 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1331 def : Pat<(X86Movlhps VR128:$src1,
1332 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1333 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1337 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1338 // is during lowering, where it's not possible to recognize the load fold
1339 // cause it has two uses through a bitcast. One use disappears at isel time
1340 // and the fold opportunity reappears.
1341 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1342 (scalar_to_vector (loadf64 addr:$src2)))),
1343 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1344 // Also handle an i64 load because that may get selected as a faster way to
1346 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1347 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1348 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1350 def : Pat<(store (f64 (vector_extract
1351 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1352 (iPTR 0))), addr:$dst),
1353 (VMOVHPDmr addr:$dst, VR128:$src)>;
1356 let Predicates = [UseSSE1] in {
1358 def : Pat<(X86Movlhps VR128:$src1,
1359 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1360 (MOVHPSrm VR128:$src1, addr:$src2)>;
1361 def : Pat<(X86Movlhps VR128:$src1,
1362 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1363 (MOVHPSrm VR128:$src1, addr:$src2)>;
1366 let Predicates = [UseSSE2] in {
1369 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1370 // is during lowering, where it's not possible to recognize the load fold
1371 // cause it has two uses through a bitcast. One use disappears at isel time
1372 // and the fold opportunity reappears.
1373 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1374 (scalar_to_vector (loadf64 addr:$src2)))),
1375 (MOVHPDrm VR128:$src1, addr:$src2)>;
1376 // Also handle an i64 load because that may get selected as a faster way to
1378 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1379 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1380 (MOVHPDrm VR128:$src1, addr:$src2)>;
1382 def : Pat<(store (f64 (vector_extract
1383 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1384 (iPTR 0))), addr:$dst),
1385 (MOVHPDmr addr:$dst, VR128:$src)>;
1388 //===----------------------------------------------------------------------===//
1389 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1390 //===----------------------------------------------------------------------===//
1392 let AddedComplexity = 20, Predicates = [UseAVX] in {
1393 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1394 (ins VR128:$src1, VR128:$src2),
1395 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1397 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1399 VEX_4V, Sched<[WriteFShuffle]>;
1400 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1401 (ins VR128:$src1, VR128:$src2),
1402 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1404 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1406 VEX_4V, Sched<[WriteFShuffle]>;
1408 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1409 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1410 (ins VR128:$src1, VR128:$src2),
1411 "movlhps\t{$src2, $dst|$dst, $src2}",
1413 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1414 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1415 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1416 (ins VR128:$src1, VR128:$src2),
1417 "movhlps\t{$src2, $dst|$dst, $src2}",
1419 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1420 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1423 let Predicates = [UseAVX] in {
1425 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1427 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1428 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1431 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1432 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1435 let Predicates = [UseSSE1] in {
1437 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1439 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1440 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1443 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1444 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1447 //===----------------------------------------------------------------------===//
1448 // SSE 1 & 2 - Conversion Instructions
1449 //===----------------------------------------------------------------------===//
1451 def SSE_CVT_PD : OpndItins<
1452 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1455 let Sched = WriteCvtI2F in
1456 def SSE_CVT_PS : OpndItins<
1457 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1460 let Sched = WriteCvtI2F in
1461 def SSE_CVT_Scalar : OpndItins<
1462 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1465 let Sched = WriteCvtF2I in
1466 def SSE_CVT_SS2SI_32 : OpndItins<
1467 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1470 let Sched = WriteCvtF2I in
1471 def SSE_CVT_SS2SI_64 : OpndItins<
1472 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1475 let Sched = WriteCvtF2I in
1476 def SSE_CVT_SD2SI : OpndItins<
1477 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1480 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1481 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1482 string asm, OpndItins itins> {
1483 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1484 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1485 itins.rr>, Sched<[itins.Sched]>;
1486 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1487 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1488 itins.rm>, Sched<[itins.Sched.Folded]>;
1491 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1492 X86MemOperand x86memop, string asm, Domain d,
1494 let hasSideEffects = 0 in {
1495 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1496 [], itins.rr, d>, Sched<[itins.Sched]>;
1498 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1499 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1503 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1504 X86MemOperand x86memop, string asm> {
1505 let hasSideEffects = 0, Predicates = [UseAVX] in {
1506 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1507 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1508 Sched<[WriteCvtI2F]>;
1510 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1511 (ins DstRC:$src1, x86memop:$src),
1512 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1513 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1514 } // hasSideEffects = 0
1517 let Predicates = [UseAVX] in {
1518 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1519 "cvttss2si\t{$src, $dst|$dst, $src}",
1522 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1523 "cvttss2si\t{$src, $dst|$dst, $src}",
1525 XS, VEX, VEX_W, VEX_LIG;
1526 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1527 "cvttsd2si\t{$src, $dst|$dst, $src}",
1530 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1531 "cvttsd2si\t{$src, $dst|$dst, $src}",
1533 XD, VEX, VEX_W, VEX_LIG;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1537 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1541 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1545 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1549 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1550 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1552 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1553 // register, but the same isn't true when only using memory operands,
1554 // provide other assembly "l" and "q" forms to address this explicitly
1555 // where appropriate to do so.
1556 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1557 XS, VEX_4V, VEX_LIG;
1558 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1559 XS, VEX_4V, VEX_W, VEX_LIG;
1560 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1561 XD, VEX_4V, VEX_LIG;
1562 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1563 XD, VEX_4V, VEX_W, VEX_LIG;
1565 let Predicates = [UseAVX] in {
1566 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1568 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1569 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1571 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1572 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1574 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1576 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1577 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1578 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR32:$src)),
1581 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1582 def : Pat<(f32 (sint_to_fp GR64:$src)),
1583 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR32:$src)),
1585 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1586 def : Pat<(f64 (sint_to_fp GR64:$src)),
1587 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1590 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1591 "cvttss2si\t{$src, $dst|$dst, $src}",
1592 SSE_CVT_SS2SI_32>, XS;
1593 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1594 "cvttss2si\t{$src, $dst|$dst, $src}",
1595 SSE_CVT_SS2SI_64>, XS, REX_W;
1596 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1597 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1600 "cvttsd2si\t{$src, $dst|$dst, $src}",
1601 SSE_CVT_SD2SI>, XD, REX_W;
1602 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1603 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1604 SSE_CVT_Scalar>, XS;
1605 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1606 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1607 SSE_CVT_Scalar>, XS, REX_W;
1608 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1609 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1610 SSE_CVT_Scalar>, XD;
1611 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1612 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1613 SSE_CVT_Scalar>, XD, REX_W;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1617 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1621 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1622 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1625 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1629 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1630 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1632 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1634 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1635 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1637 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1638 // and/or XMM operand(s).
1640 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1641 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1642 string asm, OpndItins itins> {
1643 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1644 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1645 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1646 Sched<[itins.Sched]>;
1647 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1648 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1649 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1650 Sched<[itins.Sched.Folded]>;
1653 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1654 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1655 PatFrag ld_frag, string asm, OpndItins itins,
1657 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1659 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1660 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1661 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1662 itins.rr>, Sched<[itins.Sched]>;
1663 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1664 (ins DstRC:$src1, x86memop:$src2),
1666 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1667 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1668 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1669 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1672 let Predicates = [UseAVX] in {
1673 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1674 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1675 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1676 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1677 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1678 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1680 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1682 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1683 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1686 let isCodeGenOnly = 1 in {
1687 let Predicates = [UseAVX] in {
1688 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1689 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1690 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1691 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1692 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1693 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1695 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1696 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1697 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1698 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1699 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1700 SSE_CVT_Scalar, 0>, XD,
1703 let Constraints = "$src1 = $dst" in {
1704 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1705 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1706 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1707 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1708 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1709 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1710 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1711 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1712 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1713 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1714 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1715 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1717 } // isCodeGenOnly = 1
1721 // Aliases for intrinsics
1722 let isCodeGenOnly = 1 in {
1723 let Predicates = [UseAVX] in {
1724 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1725 ssmem, sse_load_f32, "cvttss2si",
1726 SSE_CVT_SS2SI_32>, XS, VEX;
1727 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1728 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1729 "cvttss2si", SSE_CVT_SS2SI_64>,
1731 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1732 sdmem, sse_load_f64, "cvttsd2si",
1733 SSE_CVT_SD2SI>, XD, VEX;
1734 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1735 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1736 "cvttsd2si", SSE_CVT_SD2SI>,
1739 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1740 ssmem, sse_load_f32, "cvttss2si",
1741 SSE_CVT_SS2SI_32>, XS;
1742 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1743 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1744 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1745 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1746 sdmem, sse_load_f64, "cvttsd2si",
1748 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1749 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1750 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1751 } // isCodeGenOnly = 1
1753 let Predicates = [UseAVX] in {
1754 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1755 ssmem, sse_load_f32, "cvtss2si",
1756 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1757 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1758 ssmem, sse_load_f32, "cvtss2si",
1759 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1761 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1762 ssmem, sse_load_f32, "cvtss2si",
1763 SSE_CVT_SS2SI_32>, XS;
1764 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1765 ssmem, sse_load_f32, "cvtss2si",
1766 SSE_CVT_SS2SI_64>, XS, REX_W;
1768 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1769 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1770 SSEPackedSingle, SSE_CVT_PS>,
1771 PS, VEX, Requires<[HasAVX]>;
1772 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1773 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1774 SSEPackedSingle, SSE_CVT_PS>,
1775 PS, VEX, VEX_L, Requires<[HasAVX]>;
1777 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1778 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1779 SSEPackedSingle, SSE_CVT_PS>,
1780 PS, Requires<[UseSSE2]>;
1782 let Predicates = [UseAVX] in {
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1785 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1789 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1790 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1793 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1797 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1798 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1803 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1807 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1808 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1811 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1815 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1816 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1820 // Convert scalar double to scalar single
1821 let hasSideEffects = 0, Predicates = [UseAVX] in {
1822 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1823 (ins FR64:$src1, FR64:$src2),
1824 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1825 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1826 Sched<[WriteCvtF2F]>;
1828 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1829 (ins FR64:$src1, f64mem:$src2),
1830 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1831 [], IIC_SSE_CVT_Scalar_RM>,
1832 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1833 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1836 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1839 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1840 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1841 [(set FR32:$dst, (fround FR64:$src))],
1842 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1843 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1844 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1845 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1846 IIC_SSE_CVT_Scalar_RM>,
1848 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1850 let isCodeGenOnly = 1 in {
1851 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1852 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1853 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1855 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1856 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1857 Sched<[WriteCvtF2F]>;
1858 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1859 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1860 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1861 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1862 VR128:$src1, sse_load_f64:$src2))],
1863 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1864 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1866 let Constraints = "$src1 = $dst" in {
1867 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1868 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1869 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1871 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1872 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1873 Sched<[WriteCvtF2F]>;
1874 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1875 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1876 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1877 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1878 VR128:$src1, sse_load_f64:$src2))],
1879 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1880 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1882 } // isCodeGenOnly = 1
1884 // Convert scalar single to scalar double
1885 // SSE2 instructions with XS prefix
1886 let hasSideEffects = 0, Predicates = [UseAVX] in {
1887 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1888 (ins FR32:$src1, FR32:$src2),
1889 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1890 [], IIC_SSE_CVT_Scalar_RR>,
1891 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1892 Sched<[WriteCvtF2F]>;
1894 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1895 (ins FR32:$src1, f32mem:$src2),
1896 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1897 [], IIC_SSE_CVT_Scalar_RM>,
1898 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1899 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1902 def : Pat<(f64 (fextend FR32:$src)),
1903 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1904 def : Pat<(fextend (loadf32 addr:$src)),
1905 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1907 def : Pat<(extloadf32 addr:$src),
1908 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1909 Requires<[UseAVX, OptForSize]>;
1910 def : Pat<(extloadf32 addr:$src),
1911 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1912 Requires<[UseAVX, OptForSpeed]>;
1914 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1915 "cvtss2sd\t{$src, $dst|$dst, $src}",
1916 [(set FR64:$dst, (fextend FR32:$src))],
1917 IIC_SSE_CVT_Scalar_RR>, XS,
1918 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1919 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1920 "cvtss2sd\t{$src, $dst|$dst, $src}",
1921 [(set FR64:$dst, (extloadf32 addr:$src))],
1922 IIC_SSE_CVT_Scalar_RM>, XS,
1923 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1925 // extload f32 -> f64. This matches load+fextend because we have a hack in
1926 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1928 // Since these loads aren't folded into the fextend, we have to match it
1930 def : Pat<(fextend (loadf32 addr:$src)),
1931 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1932 def : Pat<(extloadf32 addr:$src),
1933 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1935 let isCodeGenOnly = 1 in {
1936 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1937 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1938 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1940 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1941 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1942 Sched<[WriteCvtF2F]>;
1943 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1944 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1945 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1947 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1948 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1949 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1950 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1951 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1952 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1953 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1955 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1956 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1957 Sched<[WriteCvtF2F]>;
1958 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1959 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1960 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1962 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1963 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1964 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1966 } // isCodeGenOnly = 1
1968 // Convert packed single/double fp to doubleword
1969 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1970 "cvtps2dq\t{$src, $dst|$dst, $src}",
1971 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1972 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1973 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1974 "cvtps2dq\t{$src, $dst|$dst, $src}",
1976 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1977 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1978 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1979 "cvtps2dq\t{$src, $dst|$dst, $src}",
1981 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1982 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1983 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1984 "cvtps2dq\t{$src, $dst|$dst, $src}",
1986 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1987 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1988 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1989 "cvtps2dq\t{$src, $dst|$dst, $src}",
1990 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1991 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1992 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1993 "cvtps2dq\t{$src, $dst|$dst, $src}",
1995 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1996 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1999 // Convert Packed Double FP to Packed DW Integers
2000 let Predicates = [HasAVX] in {
2001 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2002 // register, but the same isn't true when using memory operands instead.
2003 // Provide other assembly rr and rm forms to address this explicitly.
2004 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2005 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2006 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2007 VEX, Sched<[WriteCvtF2I]>;
2010 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2011 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2012 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2013 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2015 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2016 Sched<[WriteCvtF2ILd]>;
2019 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2020 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2022 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2023 Sched<[WriteCvtF2I]>;
2024 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2025 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2027 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2028 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2029 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2030 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2033 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2034 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2036 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2037 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2038 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2039 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2040 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2041 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2043 // Convert with truncation packed single/double fp to doubleword
2044 // SSE2 packed instructions with XS prefix
2045 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2046 "cvttps2dq\t{$src, $dst|$dst, $src}",
2048 (int_x86_sse2_cvttps2dq VR128:$src))],
2049 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2050 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2051 "cvttps2dq\t{$src, $dst|$dst, $src}",
2052 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2053 (loadv4f32 addr:$src)))],
2054 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2055 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2056 "cvttps2dq\t{$src, $dst|$dst, $src}",
2058 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2059 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2060 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2061 "cvttps2dq\t{$src, $dst|$dst, $src}",
2062 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2063 (loadv8f32 addr:$src)))],
2064 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2065 Sched<[WriteCvtF2ILd]>;
2067 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2068 "cvttps2dq\t{$src, $dst|$dst, $src}",
2069 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2070 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2071 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2072 "cvttps2dq\t{$src, $dst|$dst, $src}",
2074 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2075 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2077 let Predicates = [HasAVX] in {
2078 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2079 (VCVTDQ2PSrr VR128:$src)>;
2080 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2081 (VCVTDQ2PSrm addr:$src)>;
2083 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2084 (VCVTDQ2PSrr VR128:$src)>;
2085 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2086 (VCVTDQ2PSrm addr:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2089 (VCVTTPS2DQrr VR128:$src)>;
2090 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2091 (VCVTTPS2DQrm addr:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2094 (VCVTDQ2PSYrr VR256:$src)>;
2095 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2096 (VCVTDQ2PSYrm addr:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2099 (VCVTTPS2DQYrr VR256:$src)>;
2100 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2101 (VCVTTPS2DQYrm addr:$src)>;
2104 let Predicates = [UseSSE2] in {
2105 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2106 (CVTDQ2PSrr VR128:$src)>;
2107 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2108 (CVTDQ2PSrm addr:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2111 (CVTDQ2PSrr VR128:$src)>;
2112 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2113 (CVTDQ2PSrm addr:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2116 (CVTTPS2DQrr VR128:$src)>;
2117 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2118 (CVTTPS2DQrm addr:$src)>;
2121 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2122 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2124 (int_x86_sse2_cvttpd2dq VR128:$src))],
2125 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2127 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2128 // register, but the same isn't true when using memory operands instead.
2129 // Provide other assembly rr and rm forms to address this explicitly.
2132 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2133 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2134 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2135 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2136 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2137 (loadv2f64 addr:$src)))],
2138 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2141 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2142 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2145 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2146 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2147 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2149 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2150 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2151 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2152 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2154 let Predicates = [HasAVX] in {
2155 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2156 (VCVTTPD2DQYrr VR256:$src)>;
2157 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2158 (VCVTTPD2DQYrm addr:$src)>;
2159 } // Predicates = [HasAVX]
2161 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2162 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2163 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2164 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2165 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2166 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2167 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2168 (memopv2f64 addr:$src)))],
2170 Sched<[WriteCvtF2ILd]>;
2172 // Convert packed single to packed double
2173 let Predicates = [HasAVX] in {
2174 // SSE2 instructions without OpSize prefix
2175 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2179 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2180 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2181 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2182 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2183 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2184 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2186 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2187 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2188 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2189 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2192 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2195 let Predicates = [UseSSE2] in {
2196 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2197 "cvtps2pd\t{$src, $dst|$dst, $src}",
2198 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2199 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2200 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2201 "cvtps2pd\t{$src, $dst|$dst, $src}",
2202 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2203 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2206 // Convert Packed DW Integers to Packed Double FP
2207 let Predicates = [HasAVX] in {
2208 let hasSideEffects = 0, mayLoad = 1 in
2209 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2210 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2211 []>, VEX, Sched<[WriteCvtI2FLd]>;
2212 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2213 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2215 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2216 Sched<[WriteCvtI2F]>;
2217 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2218 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2220 (int_x86_avx_cvtdq2_pd_256
2221 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2222 Sched<[WriteCvtI2FLd]>;
2223 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2224 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2227 Sched<[WriteCvtI2F]>;
2230 let hasSideEffects = 0, mayLoad = 1 in
2231 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2232 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2233 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2234 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2235 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2236 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2237 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2239 // AVX 256-bit register conversion intrinsics
2240 let Predicates = [HasAVX] in {
2241 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2242 (VCVTDQ2PDYrr VR128:$src)>;
2243 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2244 (VCVTDQ2PDYrm addr:$src)>;
2245 } // Predicates = [HasAVX]
2247 // Convert packed double to packed single
2248 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2249 // register, but the same isn't true when using memory operands instead.
2250 // Provide other assembly rr and rm forms to address this explicitly.
2251 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2252 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2253 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2254 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2257 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2258 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2259 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2260 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2262 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2263 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2266 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2267 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2269 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2270 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2271 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2272 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2274 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2275 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2276 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2277 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2279 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2280 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2281 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2282 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2283 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2284 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2286 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2287 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2290 // AVX 256-bit register conversion intrinsics
2291 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2292 // whenever possible to avoid declaring two versions of each one.
2293 let Predicates = [HasAVX] in {
2294 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2295 (VCVTDQ2PSYrr VR256:$src)>;
2296 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2297 (VCVTDQ2PSYrm addr:$src)>;
2299 // Match fround and fextend for 128/256-bit conversions
2300 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2301 (VCVTPD2PSrr VR128:$src)>;
2302 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2303 (VCVTPD2PSXrm addr:$src)>;
2304 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2305 (VCVTPD2PSYrr VR256:$src)>;
2306 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2307 (VCVTPD2PSYrm addr:$src)>;
2309 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2310 (VCVTPS2PDrr VR128:$src)>;
2311 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2312 (VCVTPS2PDYrr VR128:$src)>;
2313 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2314 (VCVTPS2PDYrm addr:$src)>;
2317 let Predicates = [UseSSE2] in {
2318 // Match fround and fextend for 128 conversions
2319 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2320 (CVTPD2PSrr VR128:$src)>;
2321 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2322 (CVTPD2PSrm addr:$src)>;
2324 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2325 (CVTPS2PDrr VR128:$src)>;
2328 //===----------------------------------------------------------------------===//
2329 // SSE 1 & 2 - Compare Instructions
2330 //===----------------------------------------------------------------------===//
2332 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2333 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2334 Operand CC, SDNode OpNode, ValueType VT,
2335 PatFrag ld_frag, string asm, string asm_alt,
2336 OpndItins itins, ImmLeaf immLeaf> {
2337 def rr : SIi8<0xC2, MRMSrcReg,
2338 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2339 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2340 itins.rr>, Sched<[itins.Sched]>;
2341 def rm : SIi8<0xC2, MRMSrcMem,
2342 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2343 [(set RC:$dst, (OpNode (VT RC:$src1),
2344 (ld_frag addr:$src2), immLeaf:$cc))],
2346 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2348 // Accept explicit immediate argument form instead of comparison code.
2349 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2350 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2351 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2352 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2354 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2355 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2356 IIC_SSE_ALU_F32S_RM>,
2357 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2361 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2362 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2363 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2364 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2365 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2366 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2367 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2368 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2369 XD, VEX_4V, VEX_LIG;
2371 let Constraints = "$src1 = $dst" in {
2372 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2373 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2374 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2376 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2377 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2378 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2379 SSE_ALU_F64S, i8immZExt3>, XD;
2382 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2383 Intrinsic Int, string asm, OpndItins itins,
2385 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2386 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2387 [(set VR128:$dst, (Int VR128:$src1,
2388 VR128:$src, immLeaf:$cc))],
2390 Sched<[itins.Sched]>;
2391 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2392 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2393 [(set VR128:$dst, (Int VR128:$src1,
2394 (load addr:$src), immLeaf:$cc))],
2396 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2399 let isCodeGenOnly = 1 in {
2400 // Aliases to match intrinsics which expect XMM operand(s).
2401 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2402 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2403 SSE_ALU_F32S, i8immZExt5>,
2405 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2406 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2407 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2409 let Constraints = "$src1 = $dst" in {
2410 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2411 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2412 SSE_ALU_F32S, i8immZExt3>, XS;
2413 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2414 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2415 SSE_ALU_F64S, i8immZExt3>,
2421 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2422 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2423 ValueType vt, X86MemOperand x86memop,
2424 PatFrag ld_frag, string OpcodeStr> {
2425 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2426 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2427 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2430 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2431 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2432 [(set EFLAGS, (OpNode (vt RC:$src1),
2433 (ld_frag addr:$src2)))],
2435 Sched<[WriteFAddLd, ReadAfterLd]>;
2438 let Defs = [EFLAGS] in {
2439 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2440 "ucomiss">, PS, VEX, VEX_LIG;
2441 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2442 "ucomisd">, PD, VEX, VEX_LIG;
2443 let Pattern = []<dag> in {
2444 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2445 "comiss">, PS, VEX, VEX_LIG;
2446 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2447 "comisd">, PD, VEX, VEX_LIG;
2450 let isCodeGenOnly = 1 in {
2451 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2452 load, "ucomiss">, PS, VEX;
2453 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2454 load, "ucomisd">, PD, VEX;
2456 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2457 load, "comiss">, PS, VEX;
2458 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2459 load, "comisd">, PD, VEX;
2461 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2463 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2466 let Pattern = []<dag> in {
2467 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2469 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2473 let isCodeGenOnly = 1 in {
2474 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2475 load, "ucomiss">, PS;
2476 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2477 load, "ucomisd">, PD;
2479 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2481 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2484 } // Defs = [EFLAGS]
2486 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2487 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2488 Operand CC, Intrinsic Int, string asm,
2489 string asm_alt, Domain d, ImmLeaf immLeaf,
2490 OpndItins itins = SSE_ALU_F32P> {
2491 def rri : PIi8<0xC2, MRMSrcReg,
2492 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2493 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2496 def rmi : PIi8<0xC2, MRMSrcMem,
2497 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2498 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), immLeaf:$cc))],
2500 Sched<[WriteFAddLd, ReadAfterLd]>;
2502 // Accept explicit immediate argument form instead of comparison code.
2503 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2504 def rri_alt : PIi8<0xC2, MRMSrcReg,
2505 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2506 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2508 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2509 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2510 asm_alt, [], itins.rm, d>,
2511 Sched<[WriteFAddLd, ReadAfterLd]>;
2515 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2516 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2517 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2518 SSEPackedSingle, i8immZExt5>, PS, VEX_4V;
2519 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2520 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2521 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2522 SSEPackedDouble, i8immZExt5>, PD, VEX_4V;
2523 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2524 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2525 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2526 SSEPackedSingle, i8immZExt5>, PS, VEX_4V, VEX_L;
2527 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2528 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2529 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2530 SSEPackedDouble, i8immZExt5>, PD, VEX_4V, VEX_L;
2531 let Constraints = "$src1 = $dst" in {
2532 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2533 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2534 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2535 SSEPackedSingle, i8immZExt5, SSE_ALU_F32P>, PS;
2536 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2537 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2538 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2539 SSEPackedDouble, i8immZExt5, SSE_ALU_F64P>, PD;
2542 let Predicates = [HasAVX] in {
2543 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2544 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2545 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2546 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2547 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2548 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2549 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2550 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2552 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2553 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2554 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2555 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2556 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2557 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2558 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2559 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2562 let Predicates = [UseSSE1] in {
2563 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2564 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2565 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2566 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2569 let Predicates = [UseSSE2] in {
2570 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2571 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2572 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2573 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2576 //===----------------------------------------------------------------------===//
2577 // SSE 1 & 2 - Shuffle Instructions
2578 //===----------------------------------------------------------------------===//
2580 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2581 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2582 ValueType vt, string asm, PatFrag mem_frag,
2584 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2585 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2586 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2587 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2588 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2589 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2590 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2591 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2592 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2593 Sched<[WriteFShuffle]>;
2596 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2597 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2598 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2599 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2600 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2601 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2602 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2603 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2604 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2605 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2606 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2607 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2609 let Constraints = "$src1 = $dst" in {
2610 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2611 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2612 memopv4f32, SSEPackedSingle>, PS;
2613 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2614 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2615 memopv2f64, SSEPackedDouble>, PD;
2618 let Predicates = [HasAVX] in {
2619 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2620 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2621 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2622 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2623 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2625 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2626 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2627 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2628 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2629 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2632 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2633 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2634 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2635 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2636 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2638 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2639 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2640 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2641 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2642 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2645 let Predicates = [UseSSE1] in {
2646 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2647 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2648 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2649 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2650 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2653 let Predicates = [UseSSE2] in {
2654 // Generic SHUFPD patterns
2655 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2656 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2657 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2658 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2659 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2662 //===----------------------------------------------------------------------===//
2663 // SSE 1 & 2 - Unpack FP Instructions
2664 //===----------------------------------------------------------------------===//
2666 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2667 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2668 PatFrag mem_frag, RegisterClass RC,
2669 X86MemOperand x86memop, string asm,
2671 def rr : PI<opc, MRMSrcReg,
2672 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2674 (vt (OpNode RC:$src1, RC:$src2)))],
2675 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2676 def rm : PI<opc, MRMSrcMem,
2677 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2679 (vt (OpNode RC:$src1,
2680 (mem_frag addr:$src2))))],
2682 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2685 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2686 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2687 SSEPackedSingle>, PS, VEX_4V;
2688 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2689 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2690 SSEPackedDouble>, PD, VEX_4V;
2691 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2692 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2693 SSEPackedSingle>, PS, VEX_4V;
2694 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2695 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2696 SSEPackedDouble>, PD, VEX_4V;
2698 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2699 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2700 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2701 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2702 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2704 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2705 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2706 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2707 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2708 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2709 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2711 let Constraints = "$src1 = $dst" in {
2712 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2713 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2714 SSEPackedSingle>, PS;
2715 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2716 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2717 SSEPackedDouble>, PD;
2718 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2719 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2720 SSEPackedSingle>, PS;
2721 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2722 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2723 SSEPackedDouble>, PD;
2724 } // Constraints = "$src1 = $dst"
2726 let Predicates = [HasAVX1Only] in {
2727 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2728 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2729 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2730 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2731 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2732 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2733 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2734 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2736 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2737 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2738 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2739 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2740 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2741 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2742 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2743 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2746 //===----------------------------------------------------------------------===//
2747 // SSE 1 & 2 - Extract Floating-Point Sign mask
2748 //===----------------------------------------------------------------------===//
2750 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2751 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2753 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2754 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2755 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2756 Sched<[WriteVecLogic]>;
2759 let Predicates = [HasAVX] in {
2760 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2761 "movmskps", SSEPackedSingle>, PS, VEX;
2762 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2763 "movmskpd", SSEPackedDouble>, PD, VEX;
2764 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2765 "movmskps", SSEPackedSingle>, PS,
2767 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2768 "movmskpd", SSEPackedDouble>, PD,
2771 def : Pat<(i32 (X86fgetsign FR32:$src)),
2772 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2773 def : Pat<(i64 (X86fgetsign FR32:$src)),
2774 (SUBREG_TO_REG (i64 0),
2775 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2776 def : Pat<(i32 (X86fgetsign FR64:$src)),
2777 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2778 def : Pat<(i64 (X86fgetsign FR64:$src)),
2779 (SUBREG_TO_REG (i64 0),
2780 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2783 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2784 SSEPackedSingle>, PS;
2785 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2786 SSEPackedDouble>, PD;
2788 def : Pat<(i32 (X86fgetsign FR32:$src)),
2789 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2790 Requires<[UseSSE1]>;
2791 def : Pat<(i64 (X86fgetsign FR32:$src)),
2792 (SUBREG_TO_REG (i64 0),
2793 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2794 Requires<[UseSSE1]>;
2795 def : Pat<(i32 (X86fgetsign FR64:$src)),
2796 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2797 Requires<[UseSSE2]>;
2798 def : Pat<(i64 (X86fgetsign FR64:$src)),
2799 (SUBREG_TO_REG (i64 0),
2800 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2801 Requires<[UseSSE2]>;
2803 //===---------------------------------------------------------------------===//
2804 // SSE2 - Packed Integer Logical Instructions
2805 //===---------------------------------------------------------------------===//
2807 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2809 /// PDI_binop_rm - Simple SSE2 binary operator.
2810 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2811 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2812 X86MemOperand x86memop, OpndItins itins,
2813 bit IsCommutable, bit Is2Addr> {
2814 let isCommutable = IsCommutable in
2815 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2816 (ins RC:$src1, RC:$src2),
2818 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2819 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2820 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2821 Sched<[itins.Sched]>;
2822 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2823 (ins RC:$src1, x86memop:$src2),
2825 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2826 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2827 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2828 (bitconvert (memop_frag addr:$src2)))))],
2830 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2832 } // ExeDomain = SSEPackedInt
2834 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2835 ValueType OpVT128, ValueType OpVT256,
2836 OpndItins itins, bit IsCommutable = 0> {
2837 let Predicates = [HasAVX, NoVLX] in
2838 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2839 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2841 let Constraints = "$src1 = $dst" in
2842 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2843 memopv2i64, i128mem, itins, IsCommutable, 1>;
2845 let Predicates = [HasAVX2, NoVLX] in
2846 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2847 OpVT256, VR256, loadv4i64, i256mem, itins,
2848 IsCommutable, 0>, VEX_4V, VEX_L;
2851 // These are ordered here for pattern ordering requirements with the fp versions
2853 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2854 SSE_VEC_BIT_ITINS_P, 1>;
2855 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2856 SSE_VEC_BIT_ITINS_P, 1>;
2857 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2858 SSE_VEC_BIT_ITINS_P, 1>;
2859 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2860 SSE_VEC_BIT_ITINS_P, 0>;
2862 //===----------------------------------------------------------------------===//
2863 // SSE 1 & 2 - Logical Instructions
2864 //===----------------------------------------------------------------------===//
2866 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2868 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2869 SDNode OpNode, OpndItins itins> {
2870 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2871 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2874 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2875 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2878 let Constraints = "$src1 = $dst" in {
2879 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2880 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2883 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2884 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2889 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2890 let isCodeGenOnly = 1 in {
2891 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2893 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2895 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2898 let isCommutable = 0 in
2899 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2903 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2905 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2907 let Predicates = [HasAVX, NoVLX] in {
2908 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2909 !strconcat(OpcodeStr, "ps"), f256mem,
2910 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2911 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2912 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2914 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2915 !strconcat(OpcodeStr, "pd"), f256mem,
2916 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2917 (bc_v4i64 (v4f64 VR256:$src2))))],
2918 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2919 (loadv4i64 addr:$src2)))], 0>,
2922 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2923 // are all promoted to v2i64, and the patterns are covered by the int
2924 // version. This is needed in SSE only, because v2i64 isn't supported on
2925 // SSE1, but only on SSE2.
2926 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2927 !strconcat(OpcodeStr, "ps"), f128mem, [],
2928 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2929 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2931 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2932 !strconcat(OpcodeStr, "pd"), f128mem,
2933 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2934 (bc_v2i64 (v2f64 VR128:$src2))))],
2935 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2936 (loadv2i64 addr:$src2)))], 0>,
2940 let Constraints = "$src1 = $dst" in {
2941 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2942 !strconcat(OpcodeStr, "ps"), f128mem,
2943 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2944 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2945 (memopv2i64 addr:$src2)))]>, PS;
2947 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2948 !strconcat(OpcodeStr, "pd"), f128mem,
2949 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2950 (bc_v2i64 (v2f64 VR128:$src2))))],
2951 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2952 (memopv2i64 addr:$src2)))]>, PD;
2956 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2957 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2958 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2959 let isCommutable = 0 in
2960 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2962 // AVX1 requires type coercions in order to fold loads directly into logical
2964 let Predicates = [HasAVX1Only] in {
2965 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
2966 (VANDPSYrm VR256:$src1, addr:$src2)>;
2967 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
2968 (VORPSYrm VR256:$src1, addr:$src2)>;
2969 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
2970 (VXORPSYrm VR256:$src1, addr:$src2)>;
2971 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
2972 (VANDNPSYrm VR256:$src1, addr:$src2)>;
2975 //===----------------------------------------------------------------------===//
2976 // SSE 1 & 2 - Arithmetic Instructions
2977 //===----------------------------------------------------------------------===//
2979 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2982 /// In addition, we also have a special variant of the scalar form here to
2983 /// represent the associated intrinsic operation. This form is unlike the
2984 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2985 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2987 /// These three forms can each be reg+reg or reg+mem.
2990 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2992 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2993 SDNode OpNode, SizeItins itins> {
2994 let Predicates = [HasAVX, NoVLX] in {
2995 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2996 VR128, v4f32, f128mem, loadv4f32,
2997 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
2998 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2999 VR128, v2f64, f128mem, loadv2f64,
3000 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3002 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3003 OpNode, VR256, v8f32, f256mem, loadv8f32,
3004 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3005 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3006 OpNode, VR256, v4f64, f256mem, loadv4f64,
3007 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3010 let Constraints = "$src1 = $dst" in {
3011 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3012 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3014 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3015 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3020 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3022 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3023 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3024 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3025 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3027 let Constraints = "$src1 = $dst" in {
3028 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3029 OpNode, FR32, f32mem, itins.s>, XS;
3030 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3031 OpNode, FR64, f64mem, itins.d>, XD;
3035 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3037 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3038 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3039 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3040 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3041 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3042 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3044 let Constraints = "$src1 = $dst" in {
3045 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3046 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3048 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3049 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3054 // Binary Arithmetic instructions
3055 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3056 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3057 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3058 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3059 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3060 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3061 let isCommutable = 0 in {
3062 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3063 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3064 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3065 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3066 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3067 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3068 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3069 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3070 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3071 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3072 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3073 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3076 let isCodeGenOnly = 1 in {
3077 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3078 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3079 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3080 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3083 // Patterns used to select SSE scalar fp arithmetic instructions from
3084 // a scalar fp operation followed by a blend.
3086 // These patterns know, for example, how to select an ADDSS from a
3087 // float add plus vector insert.
3089 // The effect is that the backend no longer emits unnecessary vector
3090 // insert instructions immediately after SSE scalar fp instructions
3091 // like addss or mulss.
3093 // For example, given the following code:
3094 // __m128 foo(__m128 A, __m128 B) {
3099 // previously we generated:
3100 // addss %xmm0, %xmm1
3101 // movss %xmm1, %xmm0
3104 // addss %xmm1, %xmm0
3106 let Predicates = [UseSSE1] in {
3107 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3108 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3110 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3111 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3112 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3114 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3115 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3116 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3118 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3119 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3120 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3122 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3125 let Predicates = [UseSSE2] in {
3126 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3127 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3128 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3130 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3131 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3132 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3134 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3135 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3136 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3138 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3139 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3140 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3142 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3145 let Predicates = [UseSSE41] in {
3146 // If the subtarget has SSE4.1 but not AVX, the vector insert instruction is
3147 // lowered into a X86insertps or a X86Blendi rather than a X86Movss. When
3148 // selecting SSE scalar single-precision fp arithmetic instructions, make
3149 // sure that we correctly match them.
3151 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3152 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3153 FR32:$src))), (iPTR 0))),
3154 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3155 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3156 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3157 FR32:$src))), (iPTR 0))),
3158 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3159 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3160 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3161 FR32:$src))), (iPTR 0))),
3162 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3163 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3164 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3165 FR32:$src))), (iPTR 0))),
3166 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3168 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3169 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3170 FR32:$src))), (i8 1))),
3171 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3172 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3173 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3174 FR32:$src))), (i8 1))),
3175 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3176 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3177 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3178 FR32:$src))), (i8 1))),
3179 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3180 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3181 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3182 FR32:$src))), (i8 1))),
3183 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3185 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3186 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3187 FR64:$src))), (i8 1))),
3188 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3189 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3190 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3191 FR64:$src))), (i8 1))),
3192 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3193 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3194 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3195 FR64:$src))), (i8 1))),
3196 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3197 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3198 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3199 FR64:$src))), (i8 1))),
3200 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3202 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3203 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3204 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3205 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3206 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3207 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3208 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3209 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3210 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3211 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3212 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3213 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3214 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3215 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3216 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3217 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3220 let Predicates = [HasAVX] in {
3221 // The following patterns select AVX Scalar single/double precision fp
3222 // arithmetic instructions.
3224 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3225 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3227 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3228 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3229 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3231 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3232 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3233 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3235 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3236 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3237 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3239 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3240 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3241 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3242 FR32:$src))), (iPTR 0))),
3243 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3244 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3245 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3246 FR32:$src))), (iPTR 0))),
3247 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3248 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3249 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3250 FR32:$src))), (iPTR 0))),
3251 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3252 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3253 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3254 FR32:$src))), (iPTR 0))),
3255 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3257 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3258 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3259 FR32:$src))), (i8 1))),
3260 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3261 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3262 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3263 FR32:$src))), (i8 1))),
3264 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3265 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3266 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3267 FR32:$src))), (i8 1))),
3268 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3269 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3270 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3271 FR32:$src))), (i8 1))),
3272 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3274 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3275 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3276 FR64:$src))), (i8 1))),
3277 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3278 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3279 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3280 FR64:$src))), (i8 1))),
3281 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3282 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3283 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3284 FR64:$src))), (i8 1))),
3285 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3286 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3287 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3288 FR64:$src))), (i8 1))),
3289 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3291 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3292 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3293 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3294 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3295 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3296 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3297 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3298 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3299 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3300 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3301 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3302 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3303 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3304 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3305 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3306 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3309 // Patterns used to select SSE scalar fp arithmetic instructions from
3310 // a vector packed single/double fp operation followed by a vector insert.
3312 // The effect is that the backend converts the packed fp instruction
3313 // followed by a vector insert into a single SSE scalar fp instruction.
3315 // For example, given the following code:
3316 // __m128 foo(__m128 A, __m128 B) {
3317 // __m128 C = A + B;
3318 // return (__m128) {c[0], a[1], a[2], a[3]};
3321 // previously we generated:
3322 // addps %xmm0, %xmm1
3323 // movss %xmm1, %xmm0
3326 // addss %xmm1, %xmm0
3328 let Predicates = [UseSSE1] in {
3329 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3330 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3331 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3332 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3333 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3334 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3335 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3336 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3337 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3338 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3339 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3340 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3343 let Predicates = [UseSSE2] in {
3344 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3345 // from a packed double-precision fp instruction plus movsd.
3347 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3348 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3349 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3350 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3351 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3352 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3353 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3354 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3355 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3356 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3357 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3358 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3361 let Predicates = [UseSSE41] in {
3362 // With SSE4.1 we may see these operations using X86Blendi rather than
3364 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3365 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3366 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3367 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3368 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3369 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3370 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3371 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3372 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3373 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3374 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3375 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3377 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3378 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3379 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3380 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3381 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3382 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3383 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3384 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3385 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3386 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3387 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3388 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3390 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3391 (v2f64 VR128:$dst), (i8 2))),
3392 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3393 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3394 (v2f64 VR128:$dst), (i8 2))),
3395 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3396 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3397 (v2f64 VR128:$dst), (i8 2))),
3398 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3399 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3400 (v2f64 VR128:$dst), (i8 2))),
3401 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3404 let Predicates = [HasAVX] in {
3405 // The following patterns select AVX Scalar single/double precision fp
3406 // arithmetic instructions from a packed single precision fp instruction
3407 // plus movss/movsd.
3409 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3410 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3411 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3412 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3413 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3414 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3415 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3416 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3417 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3418 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3419 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3420 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3421 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3422 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3423 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3424 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3425 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3426 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3427 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3428 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3429 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3430 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3431 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3432 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3434 // Also handle X86Blendi-based patterns.
3435 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3436 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3437 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3438 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3439 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3440 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3441 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3442 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3443 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3444 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3445 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3446 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3448 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3449 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3450 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3451 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3452 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3453 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3454 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3455 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3456 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3457 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3458 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3459 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3461 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3462 (v2f64 VR128:$dst), (i8 2))),
3463 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3464 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3465 (v2f64 VR128:$dst), (i8 2))),
3466 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3467 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3468 (v2f64 VR128:$dst), (i8 2))),
3469 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3470 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3471 (v2f64 VR128:$dst), (i8 2))),
3472 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3476 /// In addition, we also have a special variant of the scalar form here to
3477 /// represent the associated intrinsic operation. This form is unlike the
3478 /// plain scalar form, in that it takes an entire vector (instead of a
3479 /// scalar) and leaves the top elements undefined.
3481 /// And, we have a special variant form for a full-vector intrinsic form.
3483 let Sched = WriteFSqrt in {
3484 def SSE_SQRTPS : OpndItins<
3485 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3488 def SSE_SQRTSS : OpndItins<
3489 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3492 def SSE_SQRTPD : OpndItins<
3493 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3496 def SSE_SQRTSD : OpndItins<
3497 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3501 let Sched = WriteFRsqrt in {
3502 def SSE_RSQRTPS : OpndItins<
3503 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3506 def SSE_RSQRTSS : OpndItins<
3507 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3511 let Sched = WriteFRcp in {
3512 def SSE_RCPP : OpndItins<
3513 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3516 def SSE_RCPS : OpndItins<
3517 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3521 /// sse1_fp_unop_s - SSE1 unops in scalar form
3522 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3523 /// the HW instructions are 2 operand / destructive.
3524 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3526 let Predicates = [HasAVX], hasSideEffects = 0 in {
3527 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3528 (ins FR32:$src1, FR32:$src2),
3529 !strconcat("v", OpcodeStr,
3530 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3531 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3532 let mayLoad = 1 in {
3533 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3534 (ins FR32:$src1,f32mem:$src2),
3535 !strconcat("v", OpcodeStr,
3536 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3537 []>, VEX_4V, VEX_LIG,
3538 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3539 let isCodeGenOnly = 1 in
3540 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3541 (ins VR128:$src1, ssmem:$src2),
3542 !strconcat("v", OpcodeStr,
3543 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3544 []>, VEX_4V, VEX_LIG,
3545 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3549 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3550 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3551 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3552 // For scalar unary operations, fold a load into the operation
3553 // only in OptForSize mode. It eliminates an instruction, but it also
3554 // eliminates a whole-register clobber (the load), so it introduces a
3555 // partial register update condition.
3556 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3557 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3558 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3559 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3560 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3561 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3562 (ins VR128:$src1, VR128:$src2),
3563 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3564 [], itins.rr>, Sched<[itins.Sched]>;
3565 let mayLoad = 1, hasSideEffects = 0 in
3566 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3567 (ins VR128:$src1, ssmem:$src2),
3568 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3569 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3573 /// sse1_fp_unop_p - SSE1 unops in packed form.
3574 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3576 let Predicates = [HasAVX] in {
3577 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3578 !strconcat("v", OpcodeStr,
3579 "ps\t{$src, $dst|$dst, $src}"),
3580 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3581 itins.rr>, VEX, Sched<[itins.Sched]>;
3582 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3583 !strconcat("v", OpcodeStr,
3584 "ps\t{$src, $dst|$dst, $src}"),
3585 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3586 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3587 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3588 !strconcat("v", OpcodeStr,
3589 "ps\t{$src, $dst|$dst, $src}"),
3590 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3591 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3592 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3593 !strconcat("v", OpcodeStr,
3594 "ps\t{$src, $dst|$dst, $src}"),
3595 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3596 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3599 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3600 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3601 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3602 Sched<[itins.Sched]>;
3603 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3604 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3605 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3606 Sched<[itins.Sched.Folded]>;
3609 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3610 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3611 Intrinsic V4F32Int, Intrinsic V8F32Int,
3613 let isCodeGenOnly = 1 in {
3614 let Predicates = [HasAVX] in {
3615 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3616 !strconcat("v", OpcodeStr,
3617 "ps\t{$src, $dst|$dst, $src}"),
3618 [(set VR128:$dst, (V4F32Int VR128:$src))],
3619 itins.rr>, VEX, Sched<[itins.Sched]>;
3620 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3621 !strconcat("v", OpcodeStr,
3622 "ps\t{$src, $dst|$dst, $src}"),
3623 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3624 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3625 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3626 !strconcat("v", OpcodeStr,
3627 "ps\t{$src, $dst|$dst, $src}"),
3628 [(set VR256:$dst, (V8F32Int VR256:$src))],
3629 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3630 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3632 !strconcat("v", OpcodeStr,
3633 "ps\t{$src, $dst|$dst, $src}"),
3634 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3635 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3638 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3639 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3640 [(set VR128:$dst, (V4F32Int VR128:$src))],
3641 itins.rr>, Sched<[itins.Sched]>;
3642 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3643 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3644 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3645 itins.rm>, Sched<[itins.Sched.Folded]>;
3646 } // isCodeGenOnly = 1
3649 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3650 // FIXME: Combine the following sse2 classes with the sse1 classes above.
3651 // The only usage of these is for SQRT[S/P]D. See sse12_fp_binop* for example.
3652 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3653 SDNode OpNode, OpndItins itins> {
3654 let Predicates = [HasAVX], hasSideEffects = 0 in {
3655 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3656 (ins FR64:$src1, FR64:$src2),
3657 !strconcat("v", OpcodeStr,
3658 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3659 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3660 let mayLoad = 1 in {
3661 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3662 (ins FR64:$src1,f64mem:$src2),
3663 !strconcat("v", OpcodeStr,
3664 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3665 []>, VEX_4V, VEX_LIG,
3666 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3667 let isCodeGenOnly = 1 in
3668 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3669 (ins VR128:$src1, sdmem:$src2),
3670 !strconcat("v", OpcodeStr,
3671 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3672 []>, VEX_4V, VEX_LIG,
3673 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3677 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3678 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3679 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3680 Sched<[itins.Sched]>;
3681 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3682 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3683 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3684 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3685 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3686 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3688 SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3689 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
3690 [], itins.rr>, Sched<[itins.Sched]>;
3692 let mayLoad = 1, hasSideEffects = 0 in
3694 SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
3695 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
3696 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3697 } // isCodeGenOnly, Constraints
3700 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3701 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3702 SDNode OpNode, OpndItins itins> {
3703 let Predicates = [HasAVX] in {
3704 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3705 !strconcat("v", OpcodeStr,
3706 "pd\t{$src, $dst|$dst, $src}"),
3707 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3708 itins.rr>, VEX, Sched<[itins.Sched]>;
3709 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3710 !strconcat("v", OpcodeStr,
3711 "pd\t{$src, $dst|$dst, $src}"),
3712 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3713 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3714 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3715 !strconcat("v", OpcodeStr,
3716 "pd\t{$src, $dst|$dst, $src}"),
3717 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3718 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3719 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3720 !strconcat("v", OpcodeStr,
3721 "pd\t{$src, $dst|$dst, $src}"),
3722 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3723 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3726 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3727 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3728 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3729 Sched<[itins.Sched]>;
3730 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3731 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3732 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3733 Sched<[itins.Sched.Folded]>;
3737 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3738 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3739 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3740 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3742 // Reciprocal approximations. Note that these typically require refinement
3743 // in order to obtain suitable precision.
3744 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3745 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
3746 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3747 int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
3748 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3749 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3750 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3751 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3753 let Predicates = [UseAVX] in {
3754 def : Pat<(f32 (fsqrt FR32:$src)),
3755 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3756 def : Pat<(f32 (fsqrt (load addr:$src))),
3757 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3758 Requires<[HasAVX, OptForSize]>;
3759 def : Pat<(f64 (fsqrt FR64:$src)),
3760 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3761 def : Pat<(f64 (fsqrt (load addr:$src))),
3762 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3763 Requires<[HasAVX, OptForSize]>;
3765 def : Pat<(f32 (X86frsqrt FR32:$src)),
3766 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3767 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3768 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3769 Requires<[HasAVX, OptForSize]>;
3771 def : Pat<(f32 (X86frcp FR32:$src)),
3772 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3773 def : Pat<(f32 (X86frcp (load addr:$src))),
3774 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3775 Requires<[HasAVX, OptForSize]>;
3777 let Predicates = [UseAVX] in {
3778 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3779 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3780 (COPY_TO_REGCLASS VR128:$src, FR32)),
3782 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3783 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3785 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3786 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3787 (COPY_TO_REGCLASS VR128:$src, FR64)),
3789 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3790 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3793 let Predicates = [HasAVX] in {
3794 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3795 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3796 (COPY_TO_REGCLASS VR128:$src, FR32)),
3798 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3799 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3801 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3802 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3803 (COPY_TO_REGCLASS VR128:$src, FR32)),
3805 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3806 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3809 // These are unary operations, but they are modeled as having 2 source operands
3810 // because the high elements of the destination are unchanged in SSE.
3811 let Predicates = [UseSSE1] in {
3812 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3813 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3814 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3815 (RCPSSr_Int VR128:$src, VR128:$src)>;
3816 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3817 (SQRTSSr_Int VR128:$src, VR128:$src)>;
3818 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3819 (SQRTSDr_Int VR128:$src, VR128:$src)>;
3822 // There is no f64 version of the reciprocal approximation instructions.
3824 //===----------------------------------------------------------------------===//
3825 // SSE 1 & 2 - Non-temporal stores
3826 //===----------------------------------------------------------------------===//
3828 let AddedComplexity = 400 in { // Prefer non-temporal versions
3829 let SchedRW = [WriteStore] in {
3830 let Predicates = [HasAVX, NoVLX] in {
3831 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3832 (ins f128mem:$dst, VR128:$src),
3833 "movntps\t{$src, $dst|$dst, $src}",
3834 [(alignednontemporalstore (v4f32 VR128:$src),
3836 IIC_SSE_MOVNT>, VEX;
3837 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3838 (ins f128mem:$dst, VR128:$src),
3839 "movntpd\t{$src, $dst|$dst, $src}",
3840 [(alignednontemporalstore (v2f64 VR128:$src),
3842 IIC_SSE_MOVNT>, VEX;
3844 let ExeDomain = SSEPackedInt in
3845 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3846 (ins f128mem:$dst, VR128:$src),
3847 "movntdq\t{$src, $dst|$dst, $src}",
3848 [(alignednontemporalstore (v2i64 VR128:$src),
3850 IIC_SSE_MOVNT>, VEX;
3852 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3853 (ins f256mem:$dst, VR256:$src),
3854 "movntps\t{$src, $dst|$dst, $src}",
3855 [(alignednontemporalstore (v8f32 VR256:$src),
3857 IIC_SSE_MOVNT>, VEX, VEX_L;
3858 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3859 (ins f256mem:$dst, VR256:$src),
3860 "movntpd\t{$src, $dst|$dst, $src}",
3861 [(alignednontemporalstore (v4f64 VR256:$src),
3863 IIC_SSE_MOVNT>, VEX, VEX_L;
3864 let ExeDomain = SSEPackedInt in
3865 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3866 (ins f256mem:$dst, VR256:$src),
3867 "movntdq\t{$src, $dst|$dst, $src}",
3868 [(alignednontemporalstore (v4i64 VR256:$src),
3870 IIC_SSE_MOVNT>, VEX, VEX_L;
3873 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3874 "movntps\t{$src, $dst|$dst, $src}",
3875 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3877 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3878 "movntpd\t{$src, $dst|$dst, $src}",
3879 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3882 let ExeDomain = SSEPackedInt in
3883 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3884 "movntdq\t{$src, $dst|$dst, $src}",
3885 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3888 // There is no AVX form for instructions below this point
3889 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3890 "movnti{l}\t{$src, $dst|$dst, $src}",
3891 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3893 PS, Requires<[HasSSE2]>;
3894 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3895 "movnti{q}\t{$src, $dst|$dst, $src}",
3896 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3898 PS, Requires<[HasSSE2]>;
3899 } // SchedRW = [WriteStore]
3901 let Predicates = [HasAVX, NoVLX] in {
3902 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3903 (VMOVNTPSmr addr:$dst, VR128:$src)>;
3906 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3907 (MOVNTPSmr addr:$dst, VR128:$src)>;
3909 } // AddedComplexity
3911 //===----------------------------------------------------------------------===//
3912 // SSE 1 & 2 - Prefetch and memory fence
3913 //===----------------------------------------------------------------------===//
3915 // Prefetch intrinsic.
3916 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3917 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3918 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3919 IIC_SSE_PREFETCH>, TB;
3920 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3921 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3922 IIC_SSE_PREFETCH>, TB;
3923 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3924 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3925 IIC_SSE_PREFETCH>, TB;
3926 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3927 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3928 IIC_SSE_PREFETCH>, TB;
3931 // FIXME: How should flush instruction be modeled?
3932 let SchedRW = [WriteLoad] in {
3934 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3935 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3936 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3939 let SchedRW = [WriteNop] in {
3940 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3941 // was introduced with SSE2, it's backward compatible.
3942 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3943 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3944 OBXS, Requires<[HasSSE2]>;
3947 let SchedRW = [WriteFence] in {
3948 // Load, store, and memory fence
3949 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3950 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3951 TB, Requires<[HasSSE1]>;
3952 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3953 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3954 TB, Requires<[HasSSE2]>;
3955 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3956 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3957 TB, Requires<[HasSSE2]>;
3960 def : Pat<(X86SFence), (SFENCE)>;
3961 def : Pat<(X86LFence), (LFENCE)>;
3962 def : Pat<(X86MFence), (MFENCE)>;
3964 //===----------------------------------------------------------------------===//
3965 // SSE 1 & 2 - Load/Store XCSR register
3966 //===----------------------------------------------------------------------===//
3968 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3969 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3970 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3971 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3972 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3973 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3975 let Predicates = [UseSSE1] in {
3976 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3977 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3978 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3979 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3980 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3981 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3984 //===---------------------------------------------------------------------===//
3985 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3986 //===---------------------------------------------------------------------===//
3988 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3990 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3991 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3992 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3994 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3995 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3997 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3998 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4000 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4001 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4006 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4007 SchedRW = [WriteMove] in {
4008 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4009 "movdqa\t{$src, $dst|$dst, $src}", [],
4012 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4013 "movdqa\t{$src, $dst|$dst, $src}", [],
4014 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
4015 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4016 "movdqu\t{$src, $dst|$dst, $src}", [],
4019 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4020 "movdqu\t{$src, $dst|$dst, $src}", [],
4021 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
4024 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4025 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4026 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4027 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4029 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4030 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4032 let Predicates = [HasAVX] in {
4033 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4034 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4036 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4037 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4042 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4043 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
4044 (ins i128mem:$dst, VR128:$src),
4045 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4047 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
4048 (ins i256mem:$dst, VR256:$src),
4049 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4051 let Predicates = [HasAVX] in {
4052 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4053 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4055 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
4056 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4061 let SchedRW = [WriteMove] in {
4062 let hasSideEffects = 0 in
4063 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4064 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
4066 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4067 "movdqu\t{$src, $dst|$dst, $src}",
4068 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4071 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
4072 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4073 "movdqa\t{$src, $dst|$dst, $src}", [],
4076 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4077 "movdqu\t{$src, $dst|$dst, $src}",
4078 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4082 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4083 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4084 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4085 "movdqa\t{$src, $dst|$dst, $src}",
4086 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
4088 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4089 "movdqu\t{$src, $dst|$dst, $src}",
4090 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
4092 XS, Requires<[UseSSE2]>;
4095 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4096 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4097 "movdqa\t{$src, $dst|$dst, $src}",
4098 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
4100 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4101 "movdqu\t{$src, $dst|$dst, $src}",
4102 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
4104 XS, Requires<[UseSSE2]>;
4107 } // ExeDomain = SSEPackedInt
4109 let Predicates = [HasAVX] in {
4110 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4111 (VMOVDQUmr addr:$dst, VR128:$src)>;
4112 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
4113 (VMOVDQUYmr addr:$dst, VR256:$src)>;
4115 let Predicates = [UseSSE2] in
4116 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4117 (MOVDQUmr addr:$dst, VR128:$src)>;
4119 //===---------------------------------------------------------------------===//
4120 // SSE2 - Packed Integer Arithmetic Instructions
4121 //===---------------------------------------------------------------------===//
4123 let Sched = WriteVecIMul in
4124 def SSE_PMADD : OpndItins<
4125 IIC_SSE_PMADD, IIC_SSE_PMADD
4128 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4130 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
4131 RegisterClass RC, PatFrag memop_frag,
4132 X86MemOperand x86memop,
4134 bit IsCommutable = 0,
4136 let isCommutable = IsCommutable in
4137 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4138 (ins RC:$src1, RC:$src2),
4140 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4141 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4142 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
4143 Sched<[itins.Sched]>;
4144 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4145 (ins RC:$src1, x86memop:$src2),
4147 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4148 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4149 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
4150 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
4153 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
4154 Intrinsic IntId256, OpndItins itins,
4155 bit IsCommutable = 0> {
4156 let Predicates = [HasAVX] in
4157 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
4158 VR128, loadv2i64, i128mem, itins,
4159 IsCommutable, 0>, VEX_4V;
4161 let Constraints = "$src1 = $dst" in
4162 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
4163 i128mem, itins, IsCommutable, 1>;
4165 let Predicates = [HasAVX2] in
4166 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
4167 VR256, loadv4i64, i256mem, itins,
4168 IsCommutable, 0>, VEX_4V, VEX_L;
4171 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
4172 string OpcodeStr, SDNode OpNode,
4173 SDNode OpNode2, RegisterClass RC,
4174 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
4175 ShiftOpndItins itins,
4177 // src2 is always 128-bit
4178 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4179 (ins RC:$src1, VR128:$src2),
4181 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4182 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4183 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
4184 itins.rr>, Sched<[WriteVecShift]>;
4185 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4186 (ins RC:$src1, i128mem:$src2),
4188 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4189 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4190 [(set RC:$dst, (DstVT (OpNode RC:$src1,
4191 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
4192 Sched<[WriteVecShiftLd, ReadAfterLd]>;
4193 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
4194 (ins RC:$src1, u8imm:$src2),
4196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4198 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
4199 Sched<[WriteVecShift]>;
4202 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4203 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4204 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4205 PatFrag memop_frag, X86MemOperand x86memop,
4207 bit IsCommutable = 0, bit Is2Addr = 1> {
4208 let isCommutable = IsCommutable in
4209 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4210 (ins RC:$src1, RC:$src2),
4212 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4213 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4214 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4215 Sched<[itins.Sched]>;
4216 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4217 (ins RC:$src1, x86memop:$src2),
4219 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4220 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4221 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4222 (bitconvert (memop_frag addr:$src2)))))]>,
4223 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4225 } // ExeDomain = SSEPackedInt
4227 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4228 SSE_INTALU_ITINS_P, 1>;
4229 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4230 SSE_INTALU_ITINS_P, 1>;
4231 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4232 SSE_INTALU_ITINS_P, 1>;
4233 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4234 SSE_INTALUQ_ITINS_P, 1>;
4235 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4236 SSE_INTMUL_ITINS_P, 1>;
4237 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4238 SSE_INTMUL_ITINS_P, 1>;
4239 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4240 SSE_INTMUL_ITINS_P, 1>;
4241 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4242 SSE_INTALU_ITINS_P, 0>;
4243 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4244 SSE_INTALU_ITINS_P, 0>;
4245 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4246 SSE_INTALU_ITINS_P, 0>;
4247 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4248 SSE_INTALUQ_ITINS_P, 0>;
4249 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4250 SSE_INTALU_ITINS_P, 0>;
4251 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4252 SSE_INTALU_ITINS_P, 0>;
4253 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4254 SSE_INTALU_ITINS_P, 1>;
4255 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4256 SSE_INTALU_ITINS_P, 1>;
4257 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4258 SSE_INTALU_ITINS_P, 1>;
4259 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4260 SSE_INTALU_ITINS_P, 1>;
4263 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4264 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4265 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4266 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4267 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4268 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4269 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4270 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4271 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4272 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4273 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4274 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4275 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4276 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4277 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4278 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4279 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4280 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4281 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4282 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4284 let Predicates = [HasAVX] in
4285 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4286 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4288 let Predicates = [HasAVX2] in
4289 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4290 VR256, loadv4i64, i256mem,
4291 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4292 let Constraints = "$src1 = $dst" in
4293 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4294 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4296 //===---------------------------------------------------------------------===//
4297 // SSE2 - Packed Integer Logical Instructions
4298 //===---------------------------------------------------------------------===//
4300 let Predicates = [HasAVX] in {
4301 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4302 VR128, v8i16, v8i16, bc_v8i16,
4303 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4304 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4305 VR128, v4i32, v4i32, bc_v4i32,
4306 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4307 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4308 VR128, v2i64, v2i64, bc_v2i64,
4309 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4311 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4312 VR128, v8i16, v8i16, bc_v8i16,
4313 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4314 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4315 VR128, v4i32, v4i32, bc_v4i32,
4316 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4317 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4318 VR128, v2i64, v2i64, bc_v2i64,
4319 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4321 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4322 VR128, v8i16, v8i16, bc_v8i16,
4323 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4324 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4325 VR128, v4i32, v4i32, bc_v4i32,
4326 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4328 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4329 // 128-bit logical shifts.
4330 def VPSLLDQri : PDIi8<0x73, MRM7r,
4331 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4332 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4334 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4336 def VPSRLDQri : PDIi8<0x73, MRM3r,
4337 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4338 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4340 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4342 // PSRADQri doesn't exist in SSE[1-3].
4344 } // Predicates = [HasAVX]
4346 let Predicates = [HasAVX2] in {
4347 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4348 VR256, v16i16, v8i16, bc_v8i16,
4349 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4350 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4351 VR256, v8i32, v4i32, bc_v4i32,
4352 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4353 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4354 VR256, v4i64, v2i64, bc_v2i64,
4355 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4357 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4358 VR256, v16i16, v8i16, bc_v8i16,
4359 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4360 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4361 VR256, v8i32, v4i32, bc_v4i32,
4362 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4363 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4364 VR256, v4i64, v2i64, bc_v2i64,
4365 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4367 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4368 VR256, v16i16, v8i16, bc_v8i16,
4369 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4370 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4371 VR256, v8i32, v4i32, bc_v4i32,
4372 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4374 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4375 // 256-bit logical shifts.
4376 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4377 (outs VR256:$dst), (ins VR256:$src1, i32u8imm:$src2),
4378 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4380 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4382 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4383 (outs VR256:$dst), (ins VR256:$src1, i32u8imm:$src2),
4384 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4386 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4388 // PSRADQYri doesn't exist in SSE[1-3].
4390 } // Predicates = [HasAVX2]
4392 let Constraints = "$src1 = $dst" in {
4393 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4394 VR128, v8i16, v8i16, bc_v8i16,
4395 SSE_INTSHIFT_ITINS_P>;
4396 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4397 VR128, v4i32, v4i32, bc_v4i32,
4398 SSE_INTSHIFT_ITINS_P>;
4399 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4400 VR128, v2i64, v2i64, bc_v2i64,
4401 SSE_INTSHIFT_ITINS_P>;
4403 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4404 VR128, v8i16, v8i16, bc_v8i16,
4405 SSE_INTSHIFT_ITINS_P>;
4406 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4407 VR128, v4i32, v4i32, bc_v4i32,
4408 SSE_INTSHIFT_ITINS_P>;
4409 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4410 VR128, v2i64, v2i64, bc_v2i64,
4411 SSE_INTSHIFT_ITINS_P>;
4413 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4414 VR128, v8i16, v8i16, bc_v8i16,
4415 SSE_INTSHIFT_ITINS_P>;
4416 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4417 VR128, v4i32, v4i32, bc_v4i32,
4418 SSE_INTSHIFT_ITINS_P>;
4420 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4421 // 128-bit logical shifts.
4422 def PSLLDQri : PDIi8<0x73, MRM7r,
4423 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4424 "pslldq\t{$src2, $dst|$dst, $src2}",
4426 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4427 IIC_SSE_INTSHDQ_P_RI>;
4428 def PSRLDQri : PDIi8<0x73, MRM3r,
4429 (outs VR128:$dst), (ins VR128:$src1, i32u8imm:$src2),
4430 "psrldq\t{$src2, $dst|$dst, $src2}",
4432 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4433 IIC_SSE_INTSHDQ_P_RI>;
4434 // PSRADQri doesn't exist in SSE[1-3].
4436 } // Constraints = "$src1 = $dst"
4438 let Predicates = [HasAVX] in {
4439 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4440 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4441 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4442 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4443 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4444 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4446 // Shift up / down and insert zero's.
4447 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4448 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4449 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4450 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4453 let Predicates = [HasAVX2] in {
4454 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4455 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4456 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4457 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4460 let Predicates = [UseSSE2] in {
4461 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4462 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4463 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4464 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4465 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4466 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4468 // Shift up / down and insert zero's.
4469 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4470 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4471 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4472 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4475 //===---------------------------------------------------------------------===//
4476 // SSE2 - Packed Integer Comparison Instructions
4477 //===---------------------------------------------------------------------===//
4479 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4480 SSE_INTALU_ITINS_P, 1>;
4481 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4482 SSE_INTALU_ITINS_P, 1>;
4483 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4484 SSE_INTALU_ITINS_P, 1>;
4485 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4486 SSE_INTALU_ITINS_P, 0>;
4487 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4488 SSE_INTALU_ITINS_P, 0>;
4489 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4490 SSE_INTALU_ITINS_P, 0>;
4492 //===---------------------------------------------------------------------===//
4493 // SSE2 - Packed Integer Shuffle Instructions
4494 //===---------------------------------------------------------------------===//
4496 let ExeDomain = SSEPackedInt in {
4497 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4499 let Predicates = [HasAVX] in {
4500 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4501 (ins VR128:$src1, u8imm:$src2),
4502 !strconcat("v", OpcodeStr,
4503 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4505 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4506 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4507 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4508 (ins i128mem:$src1, u8imm:$src2),
4509 !strconcat("v", OpcodeStr,
4510 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4512 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4513 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4514 Sched<[WriteShuffleLd]>;
4517 let Predicates = [HasAVX2] in {
4518 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4519 (ins VR256:$src1, u8imm:$src2),
4520 !strconcat("v", OpcodeStr,
4521 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4523 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4524 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4525 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4526 (ins i256mem:$src1, u8imm:$src2),
4527 !strconcat("v", OpcodeStr,
4528 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4530 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4531 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4532 Sched<[WriteShuffleLd]>;
4535 let Predicates = [UseSSE2] in {
4536 def ri : Ii8<0x70, MRMSrcReg,
4537 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4538 !strconcat(OpcodeStr,
4539 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4541 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4542 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4543 def mi : Ii8<0x70, MRMSrcMem,
4544 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4545 !strconcat(OpcodeStr,
4546 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4548 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4549 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4550 Sched<[WriteShuffleLd, ReadAfterLd]>;
4553 } // ExeDomain = SSEPackedInt
4555 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4556 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4557 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4559 let Predicates = [HasAVX] in {
4560 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4561 (VPSHUFDmi addr:$src1, imm:$imm)>;
4562 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4563 (VPSHUFDri VR128:$src1, imm:$imm)>;
4566 let Predicates = [UseSSE2] in {
4567 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4568 (PSHUFDmi addr:$src1, imm:$imm)>;
4569 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4570 (PSHUFDri VR128:$src1, imm:$imm)>;
4573 //===---------------------------------------------------------------------===//
4574 // Packed Integer Pack Instructions (SSE & AVX)
4575 //===---------------------------------------------------------------------===//
4577 let ExeDomain = SSEPackedInt in {
4578 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4579 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4581 def rr : PDI<opc, MRMSrcReg,
4582 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4584 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4585 !strconcat(OpcodeStr,
4586 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4588 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4589 Sched<[WriteShuffle]>;
4590 def rm : PDI<opc, MRMSrcMem,
4591 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4593 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4594 !strconcat(OpcodeStr,
4595 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4597 (OutVT (OpNode VR128:$src1,
4598 (bc_frag (memopv2i64 addr:$src2)))))]>,
4599 Sched<[WriteShuffleLd, ReadAfterLd]>;
4602 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4603 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4604 def Yrr : PDI<opc, MRMSrcReg,
4605 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4606 !strconcat(OpcodeStr,
4607 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4609 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4610 Sched<[WriteShuffle]>;
4611 def Yrm : PDI<opc, MRMSrcMem,
4612 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4613 !strconcat(OpcodeStr,
4614 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4616 (OutVT (OpNode VR256:$src1,
4617 (bc_frag (memopv4i64 addr:$src2)))))]>,
4618 Sched<[WriteShuffleLd, ReadAfterLd]>;
4621 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4622 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4624 def rr : SS48I<opc, MRMSrcReg,
4625 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4627 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4628 !strconcat(OpcodeStr,
4629 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4631 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4632 Sched<[WriteShuffle]>;
4633 def rm : SS48I<opc, MRMSrcMem,
4634 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4636 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4637 !strconcat(OpcodeStr,
4638 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4640 (OutVT (OpNode VR128:$src1,
4641 (bc_frag (memopv2i64 addr:$src2)))))]>,
4642 Sched<[WriteShuffleLd, ReadAfterLd]>;
4645 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4646 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4647 def Yrr : SS48I<opc, MRMSrcReg,
4648 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4649 !strconcat(OpcodeStr,
4650 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4652 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4653 Sched<[WriteShuffle]>;
4654 def Yrm : SS48I<opc, MRMSrcMem,
4655 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4656 !strconcat(OpcodeStr,
4657 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4659 (OutVT (OpNode VR256:$src1,
4660 (bc_frag (memopv4i64 addr:$src2)))))]>,
4661 Sched<[WriteShuffleLd, ReadAfterLd]>;
4664 let Predicates = [HasAVX] in {
4665 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4666 bc_v8i16, 0>, VEX_4V;
4667 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4668 bc_v4i32, 0>, VEX_4V;
4670 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4671 bc_v8i16, 0>, VEX_4V;
4672 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4673 bc_v4i32, 0>, VEX_4V;
4676 let Predicates = [HasAVX2] in {
4677 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4678 bc_v16i16>, VEX_4V, VEX_L;
4679 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4680 bc_v8i32>, VEX_4V, VEX_L;
4682 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4683 bc_v16i16>, VEX_4V, VEX_L;
4684 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4685 bc_v8i32>, VEX_4V, VEX_L;
4688 let Constraints = "$src1 = $dst" in {
4689 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4691 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4694 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4697 let Predicates = [HasSSE41] in
4698 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4701 } // ExeDomain = SSEPackedInt
4703 //===---------------------------------------------------------------------===//
4704 // SSE2 - Packed Integer Unpack Instructions
4705 //===---------------------------------------------------------------------===//
4707 let ExeDomain = SSEPackedInt in {
4708 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4709 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4710 def rr : PDI<opc, MRMSrcReg,
4711 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4713 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4714 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4715 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4716 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4717 def rm : PDI<opc, MRMSrcMem,
4718 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4720 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4721 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4722 [(set VR128:$dst, (OpNode VR128:$src1,
4723 (bc_frag (memopv2i64
4726 Sched<[WriteShuffleLd, ReadAfterLd]>;
4729 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4730 SDNode OpNode, PatFrag bc_frag> {
4731 def Yrr : PDI<opc, MRMSrcReg,
4732 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4733 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4734 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4735 Sched<[WriteShuffle]>;
4736 def Yrm : PDI<opc, MRMSrcMem,
4737 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4738 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4739 [(set VR256:$dst, (OpNode VR256:$src1,
4740 (bc_frag (memopv4i64 addr:$src2))))]>,
4741 Sched<[WriteShuffleLd, ReadAfterLd]>;
4744 let Predicates = [HasAVX] in {
4745 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4746 bc_v16i8, 0>, VEX_4V;
4747 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4748 bc_v8i16, 0>, VEX_4V;
4749 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4750 bc_v4i32, 0>, VEX_4V;
4751 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4752 bc_v2i64, 0>, VEX_4V;
4754 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4755 bc_v16i8, 0>, VEX_4V;
4756 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4757 bc_v8i16, 0>, VEX_4V;
4758 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4759 bc_v4i32, 0>, VEX_4V;
4760 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4761 bc_v2i64, 0>, VEX_4V;
4764 let Predicates = [HasAVX2] in {
4765 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4766 bc_v32i8>, VEX_4V, VEX_L;
4767 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4768 bc_v16i16>, VEX_4V, VEX_L;
4769 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4770 bc_v8i32>, VEX_4V, VEX_L;
4771 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4772 bc_v4i64>, VEX_4V, VEX_L;
4774 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4775 bc_v32i8>, VEX_4V, VEX_L;
4776 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4777 bc_v16i16>, VEX_4V, VEX_L;
4778 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4779 bc_v8i32>, VEX_4V, VEX_L;
4780 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4781 bc_v4i64>, VEX_4V, VEX_L;
4784 let Constraints = "$src1 = $dst" in {
4785 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4787 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4789 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4791 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4794 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4796 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4798 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4800 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4803 } // ExeDomain = SSEPackedInt
4805 //===---------------------------------------------------------------------===//
4806 // SSE2 - Packed Integer Extract and Insert
4807 //===---------------------------------------------------------------------===//
4809 let ExeDomain = SSEPackedInt in {
4810 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4811 def rri : Ii8<0xC4, MRMSrcReg,
4812 (outs VR128:$dst), (ins VR128:$src1,
4813 GR32orGR64:$src2, u8imm:$src3),
4815 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4816 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4818 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4819 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4820 def rmi : Ii8<0xC4, MRMSrcMem,
4821 (outs VR128:$dst), (ins VR128:$src1,
4822 i16mem:$src2, u8imm:$src3),
4824 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4825 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4827 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4828 imm:$src3))], IIC_SSE_PINSRW>,
4829 Sched<[WriteShuffleLd, ReadAfterLd]>;
4833 let Predicates = [HasAVX] in
4834 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4835 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4836 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4837 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4838 imm:$src2))]>, PD, VEX,
4839 Sched<[WriteShuffle]>;
4840 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4841 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4842 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4843 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4844 imm:$src2))], IIC_SSE_PEXTRW>,
4845 Sched<[WriteShuffleLd, ReadAfterLd]>;
4848 let Predicates = [HasAVX] in
4849 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4851 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4852 defm PINSRW : sse2_pinsrw, PD;
4854 } // ExeDomain = SSEPackedInt
4856 //===---------------------------------------------------------------------===//
4857 // SSE2 - Packed Mask Creation
4858 //===---------------------------------------------------------------------===//
4860 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4862 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4864 "pmovmskb\t{$src, $dst|$dst, $src}",
4865 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4866 IIC_SSE_MOVMSK>, VEX;
4868 let Predicates = [HasAVX2] in {
4869 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4871 "pmovmskb\t{$src, $dst|$dst, $src}",
4872 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4876 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4877 "pmovmskb\t{$src, $dst|$dst, $src}",
4878 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4881 } // ExeDomain = SSEPackedInt
4883 //===---------------------------------------------------------------------===//
4884 // SSE2 - Conditional Store
4885 //===---------------------------------------------------------------------===//
4887 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4889 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4890 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4891 (ins VR128:$src, VR128:$mask),
4892 "maskmovdqu\t{$mask, $src|$src, $mask}",
4893 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4894 IIC_SSE_MASKMOV>, VEX;
4895 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4896 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4897 (ins VR128:$src, VR128:$mask),
4898 "maskmovdqu\t{$mask, $src|$src, $mask}",
4899 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4900 IIC_SSE_MASKMOV>, VEX;
4902 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4903 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4904 "maskmovdqu\t{$mask, $src|$src, $mask}",
4905 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4907 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4908 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4909 "maskmovdqu\t{$mask, $src|$src, $mask}",
4910 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4913 } // ExeDomain = SSEPackedInt
4915 //===---------------------------------------------------------------------===//
4916 // SSE2 - Move Doubleword
4917 //===---------------------------------------------------------------------===//
4919 //===---------------------------------------------------------------------===//
4920 // Move Int Doubleword to Packed Double Int
4922 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4923 "movd\t{$src, $dst|$dst, $src}",
4925 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4926 VEX, Sched<[WriteMove]>;
4927 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4928 "movd\t{$src, $dst|$dst, $src}",
4930 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4932 VEX, Sched<[WriteLoad]>;
4933 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4934 "movq\t{$src, $dst|$dst, $src}",
4936 (v2i64 (scalar_to_vector GR64:$src)))],
4937 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4938 let isCodeGenOnly = 1 in
4939 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4940 "movq\t{$src, $dst|$dst, $src}",
4941 [(set FR64:$dst, (bitconvert GR64:$src))],
4942 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4944 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4945 "movd\t{$src, $dst|$dst, $src}",
4947 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4949 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4950 "movd\t{$src, $dst|$dst, $src}",
4952 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4953 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4954 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4955 "mov{d|q}\t{$src, $dst|$dst, $src}",
4957 (v2i64 (scalar_to_vector GR64:$src)))],
4958 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4959 let isCodeGenOnly = 1 in
4960 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4961 "mov{d|q}\t{$src, $dst|$dst, $src}",
4962 [(set FR64:$dst, (bitconvert GR64:$src))],
4963 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4965 //===---------------------------------------------------------------------===//
4966 // Move Int Doubleword to Single Scalar
4968 let isCodeGenOnly = 1 in {
4969 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4970 "movd\t{$src, $dst|$dst, $src}",
4971 [(set FR32:$dst, (bitconvert GR32:$src))],
4972 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4974 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4975 "movd\t{$src, $dst|$dst, $src}",
4976 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4978 VEX, Sched<[WriteLoad]>;
4979 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4980 "movd\t{$src, $dst|$dst, $src}",
4981 [(set FR32:$dst, (bitconvert GR32:$src))],
4982 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4984 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4985 "movd\t{$src, $dst|$dst, $src}",
4986 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4987 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4990 //===---------------------------------------------------------------------===//
4991 // Move Packed Doubleword Int to Packed Double Int
4993 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4994 "movd\t{$src, $dst|$dst, $src}",
4995 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4996 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4998 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4999 (ins i32mem:$dst, VR128:$src),
5000 "movd\t{$src, $dst|$dst, $src}",
5001 [(store (i32 (vector_extract (v4i32 VR128:$src),
5002 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
5003 VEX, Sched<[WriteStore]>;
5004 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5005 "movd\t{$src, $dst|$dst, $src}",
5006 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5007 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
5009 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
5010 "movd\t{$src, $dst|$dst, $src}",
5011 [(store (i32 (vector_extract (v4i32 VR128:$src),
5012 (iPTR 0))), addr:$dst)],
5013 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5015 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
5016 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5018 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
5019 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5021 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
5022 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5024 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
5025 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5027 //===---------------------------------------------------------------------===//
5028 // Move Packed Doubleword Int first element to Doubleword Int
5030 let SchedRW = [WriteMove] in {
5031 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5032 "movq\t{$src, $dst|$dst, $src}",
5033 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5038 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5039 "mov{d|q}\t{$src, $dst|$dst, $src}",
5040 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5045 //===---------------------------------------------------------------------===//
5046 // Bitcast FR64 <-> GR64
5048 let isCodeGenOnly = 1 in {
5049 let Predicates = [UseAVX] in
5050 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5051 "movq\t{$src, $dst|$dst, $src}",
5052 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
5053 VEX, Sched<[WriteLoad]>;
5054 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5055 "movq\t{$src, $dst|$dst, $src}",
5056 [(set GR64:$dst, (bitconvert FR64:$src))],
5057 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
5058 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5059 "movq\t{$src, $dst|$dst, $src}",
5060 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5061 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5063 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5064 "movq\t{$src, $dst|$dst, $src}",
5065 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
5066 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5067 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5068 "mov{d|q}\t{$src, $dst|$dst, $src}",
5069 [(set GR64:$dst, (bitconvert FR64:$src))],
5070 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5071 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5072 "movq\t{$src, $dst|$dst, $src}",
5073 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5074 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5077 //===---------------------------------------------------------------------===//
5078 // Move Scalar Single to Double Int
5080 let isCodeGenOnly = 1 in {
5081 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5082 "movd\t{$src, $dst|$dst, $src}",
5083 [(set GR32:$dst, (bitconvert FR32:$src))],
5084 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
5085 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5086 "movd\t{$src, $dst|$dst, $src}",
5087 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5088 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5089 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5090 "movd\t{$src, $dst|$dst, $src}",
5091 [(set GR32:$dst, (bitconvert FR32:$src))],
5092 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5093 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5094 "movd\t{$src, $dst|$dst, $src}",
5095 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5096 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5099 //===---------------------------------------------------------------------===//
5100 // Patterns and instructions to describe movd/movq to XMM register zero-extends
5102 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
5103 let AddedComplexity = 15 in {
5104 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5105 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
5106 [(set VR128:$dst, (v2i64 (X86vzmovl
5107 (v2i64 (scalar_to_vector GR64:$src)))))],
5110 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5111 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
5112 [(set VR128:$dst, (v2i64 (X86vzmovl
5113 (v2i64 (scalar_to_vector GR64:$src)))))],
5116 } // isCodeGenOnly, SchedRW
5118 let Predicates = [UseAVX] in {
5119 let AddedComplexity = 15 in
5120 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5121 (VMOVDI2PDIrr GR32:$src)>;
5123 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
5124 let AddedComplexity = 20 in {
5125 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5126 (VMOVDI2PDIrm addr:$src)>;
5127 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5128 (VMOVDI2PDIrm addr:$src)>;
5129 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5130 (VMOVDI2PDIrm addr:$src)>;
5132 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
5133 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
5134 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
5135 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
5136 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5137 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
5138 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
5141 let Predicates = [UseSSE2] in {
5142 let AddedComplexity = 15 in
5143 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5144 (MOVDI2PDIrr GR32:$src)>;
5146 let AddedComplexity = 20 in {
5147 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5148 (MOVDI2PDIrm addr:$src)>;
5149 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5150 (MOVDI2PDIrm addr:$src)>;
5151 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5152 (MOVDI2PDIrm addr:$src)>;
5156 // These are the correct encodings of the instructions so that we know how to
5157 // read correct assembly, even though we continue to emit the wrong ones for
5158 // compatibility with Darwin's buggy assembler.
5159 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5160 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5161 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5162 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5163 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
5164 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5165 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5166 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5167 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5169 //===---------------------------------------------------------------------===//
5170 // SSE2 - Move Quadword
5171 //===---------------------------------------------------------------------===//
5173 //===---------------------------------------------------------------------===//
5174 // Move Quadword Int to Packed Quadword Int
5177 let SchedRW = [WriteLoad] in {
5178 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5179 "vmovq\t{$src, $dst|$dst, $src}",
5181 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
5182 VEX, Requires<[UseAVX]>;
5183 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5184 "movq\t{$src, $dst|$dst, $src}",
5186 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
5188 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
5191 //===---------------------------------------------------------------------===//
5192 // Move Packed Quadword Int to Quadword Int
5194 let SchedRW = [WriteStore] in {
5195 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5196 "movq\t{$src, $dst|$dst, $src}",
5197 [(store (i64 (vector_extract (v2i64 VR128:$src),
5198 (iPTR 0))), addr:$dst)],
5199 IIC_SSE_MOVDQ>, VEX;
5200 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5201 "movq\t{$src, $dst|$dst, $src}",
5202 [(store (i64 (vector_extract (v2i64 VR128:$src),
5203 (iPTR 0))), addr:$dst)],
5207 // For disassembler only
5208 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5209 SchedRW = [WriteVecLogic] in {
5210 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5211 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5212 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5213 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5216 //===---------------------------------------------------------------------===//
5217 // Store / copy lower 64-bits of a XMM register.
5219 let Predicates = [UseAVX] in
5220 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5221 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5222 let Predicates = [UseSSE2] in
5223 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5224 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5226 let isCodeGenOnly = 1, AddedComplexity = 20 in {
5227 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5228 "vmovq\t{$src, $dst|$dst, $src}",
5230 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5231 (loadi64 addr:$src))))))],
5233 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5235 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5236 "movq\t{$src, $dst|$dst, $src}",
5238 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5239 (loadi64 addr:$src))))))],
5241 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5244 let Predicates = [UseAVX], AddedComplexity = 20 in {
5245 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5246 (VMOVZQI2PQIrm addr:$src)>;
5247 def : Pat<(v2i64 (X86vzload addr:$src)),
5248 (VMOVZQI2PQIrm addr:$src)>;
5251 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5252 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5253 (MOVZQI2PQIrm addr:$src)>;
5254 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5257 let Predicates = [HasAVX] in {
5258 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5259 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5260 def : Pat<(v4i64 (X86vzload addr:$src)),
5261 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5264 //===---------------------------------------------------------------------===//
5265 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5266 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5268 let SchedRW = [WriteVecLogic] in {
5269 let AddedComplexity = 15 in
5270 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5271 "vmovq\t{$src, $dst|$dst, $src}",
5272 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5274 XS, VEX, Requires<[UseAVX]>;
5275 let AddedComplexity = 15 in
5276 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5277 "movq\t{$src, $dst|$dst, $src}",
5278 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5280 XS, Requires<[UseSSE2]>;
5283 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5284 let AddedComplexity = 20 in
5285 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5286 "vmovq\t{$src, $dst|$dst, $src}",
5287 [(set VR128:$dst, (v2i64 (X86vzmovl
5288 (loadv2i64 addr:$src))))],
5290 XS, VEX, Requires<[UseAVX]>;
5291 let AddedComplexity = 20 in {
5292 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5293 "movq\t{$src, $dst|$dst, $src}",
5294 [(set VR128:$dst, (v2i64 (X86vzmovl
5295 (loadv2i64 addr:$src))))],
5297 XS, Requires<[UseSSE2]>;
5299 } // isCodeGenOnly, SchedRW
5301 let AddedComplexity = 20 in {
5302 let Predicates = [UseAVX] in {
5303 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5304 (VMOVZPQILo2PQIrr VR128:$src)>;
5306 let Predicates = [UseSSE2] in {
5307 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5308 (MOVZPQILo2PQIrr VR128:$src)>;
5312 //===---------------------------------------------------------------------===//
5313 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5314 //===---------------------------------------------------------------------===//
5315 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5316 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5317 X86MemOperand x86memop> {
5318 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5319 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5320 [(set RC:$dst, (vt (OpNode RC:$src)))],
5321 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5322 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5323 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5324 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5325 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5328 let Predicates = [HasAVX] in {
5329 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5330 v4f32, VR128, loadv4f32, f128mem>, VEX;
5331 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5332 v4f32, VR128, loadv4f32, f128mem>, VEX;
5333 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5334 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5335 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5336 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5338 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5339 memopv4f32, f128mem>;
5340 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5341 memopv4f32, f128mem>;
5343 let Predicates = [HasAVX] in {
5344 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5345 (VMOVSHDUPrr VR128:$src)>;
5346 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5347 (VMOVSHDUPrm addr:$src)>;
5348 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5349 (VMOVSLDUPrr VR128:$src)>;
5350 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5351 (VMOVSLDUPrm addr:$src)>;
5352 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5353 (VMOVSHDUPYrr VR256:$src)>;
5354 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5355 (VMOVSHDUPYrm addr:$src)>;
5356 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5357 (VMOVSLDUPYrr VR256:$src)>;
5358 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5359 (VMOVSLDUPYrm addr:$src)>;
5362 let Predicates = [UseSSE3] in {
5363 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5364 (MOVSHDUPrr VR128:$src)>;
5365 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5366 (MOVSHDUPrm addr:$src)>;
5367 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5368 (MOVSLDUPrr VR128:$src)>;
5369 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5370 (MOVSLDUPrm addr:$src)>;
5373 //===---------------------------------------------------------------------===//
5374 // SSE3 - Replicate Double FP - MOVDDUP
5375 //===---------------------------------------------------------------------===//
5377 multiclass sse3_replicate_dfp<string OpcodeStr> {
5378 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5379 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5380 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5381 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5382 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5383 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5386 (scalar_to_vector (loadf64 addr:$src)))))],
5387 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5390 // FIXME: Merge with above classe when there're patterns for the ymm version
5391 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5392 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5393 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5394 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5395 Sched<[WriteFShuffle]>;
5396 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5400 (scalar_to_vector (loadf64 addr:$src)))))]>,
5404 let Predicates = [HasAVX] in {
5405 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5406 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5409 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5411 let Predicates = [HasAVX] in {
5412 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5413 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5414 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5415 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5416 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5417 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5418 def : Pat<(X86Movddup (bc_v2f64
5419 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5420 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5423 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5424 (VMOVDDUPYrm addr:$src)>;
5425 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5426 (VMOVDDUPYrm addr:$src)>;
5427 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5428 (VMOVDDUPYrm addr:$src)>;
5429 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5430 (VMOVDDUPYrr VR256:$src)>;
5433 let Predicates = [UseAVX, OptForSize] in {
5434 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5435 (VMOVDDUPrm addr:$src)>;
5436 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5437 (VMOVDDUPrm addr:$src)>;
5440 let Predicates = [UseSSE3] in {
5441 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5442 (MOVDDUPrm addr:$src)>;
5443 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5444 (MOVDDUPrm addr:$src)>;
5445 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5446 (MOVDDUPrm addr:$src)>;
5447 def : Pat<(X86Movddup (bc_v2f64
5448 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5449 (MOVDDUPrm addr:$src)>;
5452 //===---------------------------------------------------------------------===//
5453 // SSE3 - Move Unaligned Integer
5454 //===---------------------------------------------------------------------===//
5456 let SchedRW = [WriteLoad] in {
5457 let Predicates = [HasAVX] in {
5458 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5459 "vlddqu\t{$src, $dst|$dst, $src}",
5460 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5461 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5462 "vlddqu\t{$src, $dst|$dst, $src}",
5463 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5466 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5467 "lddqu\t{$src, $dst|$dst, $src}",
5468 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5472 //===---------------------------------------------------------------------===//
5473 // SSE3 - Arithmetic
5474 //===---------------------------------------------------------------------===//
5476 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5477 X86MemOperand x86memop, OpndItins itins,
5479 def rr : I<0xD0, MRMSrcReg,
5480 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5482 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5483 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5484 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5485 Sched<[itins.Sched]>;
5486 def rm : I<0xD0, MRMSrcMem,
5487 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5489 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5490 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5491 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5492 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5495 let Predicates = [HasAVX] in {
5496 let ExeDomain = SSEPackedSingle in {
5497 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5498 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5499 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5500 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5502 let ExeDomain = SSEPackedDouble in {
5503 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5504 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5505 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5506 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5509 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5510 let ExeDomain = SSEPackedSingle in
5511 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5512 f128mem, SSE_ALU_F32P>, XD;
5513 let ExeDomain = SSEPackedDouble in
5514 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5515 f128mem, SSE_ALU_F64P>, PD;
5518 // Patterns used to select 'addsub' instructions.
5519 let Predicates = [HasAVX] in {
5520 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5521 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5522 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5523 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5524 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5525 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5526 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5527 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5529 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5530 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5531 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 (memop addr:$rhs)))),
5532 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5533 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5534 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5535 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 (memop addr:$rhs)))),
5536 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5539 let Predicates = [UseSSE3] in {
5540 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5541 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5542 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5543 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5544 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5545 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5546 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5547 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5550 //===---------------------------------------------------------------------===//
5551 // SSE3 Instructions
5552 //===---------------------------------------------------------------------===//
5555 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5556 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5557 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5559 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5560 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5561 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5564 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5566 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5567 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5568 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5569 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5571 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5572 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5573 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5575 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5576 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5577 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5580 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5582 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5583 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5584 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5585 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5588 let Predicates = [HasAVX] in {
5589 let ExeDomain = SSEPackedSingle in {
5590 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5591 X86fhadd, 0>, VEX_4V;
5592 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5593 X86fhsub, 0>, VEX_4V;
5594 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5595 X86fhadd, 0>, VEX_4V, VEX_L;
5596 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5597 X86fhsub, 0>, VEX_4V, VEX_L;
5599 let ExeDomain = SSEPackedDouble in {
5600 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5601 X86fhadd, 0>, VEX_4V;
5602 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5603 X86fhsub, 0>, VEX_4V;
5604 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5605 X86fhadd, 0>, VEX_4V, VEX_L;
5606 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5607 X86fhsub, 0>, VEX_4V, VEX_L;
5611 let Constraints = "$src1 = $dst" in {
5612 let ExeDomain = SSEPackedSingle in {
5613 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5614 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5616 let ExeDomain = SSEPackedDouble in {
5617 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5618 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5622 //===---------------------------------------------------------------------===//
5623 // SSSE3 - Packed Absolute Instructions
5624 //===---------------------------------------------------------------------===//
5627 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5628 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5629 Intrinsic IntId128> {
5630 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5632 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5633 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5634 Sched<[WriteVecALU]>;
5636 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5638 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5641 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5642 Sched<[WriteVecALULd]>;
5645 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5646 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5647 Intrinsic IntId256> {
5648 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5650 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5651 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5652 Sched<[WriteVecALU]>;
5654 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5656 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5659 (bitconvert (memopv4i64 addr:$src))))]>,
5660 Sched<[WriteVecALULd]>;
5663 // Helper fragments to match sext vXi1 to vXiY.
5664 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5666 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5667 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5668 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5670 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5671 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5673 let Predicates = [HasAVX] in {
5674 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5675 int_x86_ssse3_pabs_b_128>, VEX;
5676 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5677 int_x86_ssse3_pabs_w_128>, VEX;
5678 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5679 int_x86_ssse3_pabs_d_128>, VEX;
5682 (bc_v2i64 (v16i1sextv16i8)),
5683 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5684 (VPABSBrr128 VR128:$src)>;
5686 (bc_v2i64 (v8i1sextv8i16)),
5687 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5688 (VPABSWrr128 VR128:$src)>;
5690 (bc_v2i64 (v4i1sextv4i32)),
5691 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5692 (VPABSDrr128 VR128:$src)>;
5695 let Predicates = [HasAVX2] in {
5696 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5697 int_x86_avx2_pabs_b>, VEX, VEX_L;
5698 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5699 int_x86_avx2_pabs_w>, VEX, VEX_L;
5700 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5701 int_x86_avx2_pabs_d>, VEX, VEX_L;
5704 (bc_v4i64 (v32i1sextv32i8)),
5705 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5706 (VPABSBrr256 VR256:$src)>;
5708 (bc_v4i64 (v16i1sextv16i16)),
5709 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5710 (VPABSWrr256 VR256:$src)>;
5712 (bc_v4i64 (v8i1sextv8i32)),
5713 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5714 (VPABSDrr256 VR256:$src)>;
5717 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5718 int_x86_ssse3_pabs_b_128>;
5719 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5720 int_x86_ssse3_pabs_w_128>;
5721 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5722 int_x86_ssse3_pabs_d_128>;
5724 let Predicates = [HasSSSE3] in {
5726 (bc_v2i64 (v16i1sextv16i8)),
5727 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5728 (PABSBrr128 VR128:$src)>;
5730 (bc_v2i64 (v8i1sextv8i16)),
5731 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5732 (PABSWrr128 VR128:$src)>;
5734 (bc_v2i64 (v4i1sextv4i32)),
5735 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5736 (PABSDrr128 VR128:$src)>;
5739 //===---------------------------------------------------------------------===//
5740 // SSSE3 - Packed Binary Operator Instructions
5741 //===---------------------------------------------------------------------===//
5743 let Sched = WriteVecALU in {
5744 def SSE_PHADDSUBD : OpndItins<
5745 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5747 def SSE_PHADDSUBSW : OpndItins<
5748 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5750 def SSE_PHADDSUBW : OpndItins<
5751 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5754 let Sched = WriteShuffle in
5755 def SSE_PSHUFB : OpndItins<
5756 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5758 let Sched = WriteVecALU in
5759 def SSE_PSIGN : OpndItins<
5760 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5762 let Sched = WriteVecIMul in
5763 def SSE_PMULHRSW : OpndItins<
5764 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5767 /// SS3I_binop_rm - Simple SSSE3 bin op
5768 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5769 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5770 X86MemOperand x86memop, OpndItins itins,
5772 let isCommutable = 1 in
5773 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5774 (ins RC:$src1, RC:$src2),
5776 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5777 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5778 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5779 Sched<[itins.Sched]>;
5780 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5781 (ins RC:$src1, x86memop:$src2),
5783 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5784 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5786 (OpVT (OpNode RC:$src1,
5787 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5788 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5791 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5792 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5793 Intrinsic IntId128, OpndItins itins,
5795 let isCommutable = 1 in
5796 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5797 (ins VR128:$src1, VR128:$src2),
5799 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5800 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5801 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5802 Sched<[itins.Sched]>;
5803 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5804 (ins VR128:$src1, i128mem:$src2),
5806 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5807 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5809 (IntId128 VR128:$src1,
5810 (bitconvert (memopv2i64 addr:$src2))))]>,
5811 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5814 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5816 X86FoldableSchedWrite Sched> {
5817 let isCommutable = 1 in
5818 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5819 (ins VR256:$src1, VR256:$src2),
5820 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5821 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5823 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5824 (ins VR256:$src1, i256mem:$src2),
5825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5827 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5828 Sched<[Sched.Folded, ReadAfterLd]>;
5831 let ImmT = NoImm, Predicates = [HasAVX] in {
5832 let isCommutable = 0 in {
5833 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5835 SSE_PHADDSUBW, 0>, VEX_4V;
5836 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5838 SSE_PHADDSUBD, 0>, VEX_4V;
5839 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5841 SSE_PHADDSUBW, 0>, VEX_4V;
5842 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5844 SSE_PHADDSUBD, 0>, VEX_4V;
5845 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5847 SSE_PSIGN, 0>, VEX_4V;
5848 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5850 SSE_PSIGN, 0>, VEX_4V;
5851 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5853 SSE_PSIGN, 0>, VEX_4V;
5854 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5856 SSE_PSHUFB, 0>, VEX_4V;
5857 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5858 int_x86_ssse3_phadd_sw_128,
5859 SSE_PHADDSUBSW, 0>, VEX_4V;
5860 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5861 int_x86_ssse3_phsub_sw_128,
5862 SSE_PHADDSUBSW, 0>, VEX_4V;
5863 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5864 int_x86_ssse3_pmadd_ub_sw_128,
5865 SSE_PMADD, 0>, VEX_4V;
5867 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5868 int_x86_ssse3_pmul_hr_sw_128,
5869 SSE_PMULHRSW, 0>, VEX_4V;
5872 let ImmT = NoImm, Predicates = [HasAVX2] in {
5873 let isCommutable = 0 in {
5874 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5876 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5877 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5879 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5880 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5882 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5883 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5885 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5886 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5888 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5889 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5891 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5892 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5894 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5895 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5897 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5898 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5899 int_x86_avx2_phadd_sw,
5900 WriteVecALU>, VEX_4V, VEX_L;
5901 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5902 int_x86_avx2_phsub_sw,
5903 WriteVecALU>, VEX_4V, VEX_L;
5904 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5905 int_x86_avx2_pmadd_ub_sw,
5906 WriteVecIMul>, VEX_4V, VEX_L;
5908 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5909 int_x86_avx2_pmul_hr_sw,
5910 WriteVecIMul>, VEX_4V, VEX_L;
5913 // None of these have i8 immediate fields.
5914 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5915 let isCommutable = 0 in {
5916 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5917 memopv2i64, i128mem, SSE_PHADDSUBW>;
5918 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5919 memopv2i64, i128mem, SSE_PHADDSUBD>;
5920 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5921 memopv2i64, i128mem, SSE_PHADDSUBW>;
5922 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5923 memopv2i64, i128mem, SSE_PHADDSUBD>;
5924 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5925 memopv2i64, i128mem, SSE_PSIGN>;
5926 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5927 memopv2i64, i128mem, SSE_PSIGN>;
5928 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5929 memopv2i64, i128mem, SSE_PSIGN>;
5930 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5931 memopv2i64, i128mem, SSE_PSHUFB>;
5932 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5933 int_x86_ssse3_phadd_sw_128,
5935 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5936 int_x86_ssse3_phsub_sw_128,
5938 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5939 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5941 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5942 int_x86_ssse3_pmul_hr_sw_128,
5946 //===---------------------------------------------------------------------===//
5947 // SSSE3 - Packed Align Instruction Patterns
5948 //===---------------------------------------------------------------------===//
5950 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5951 let hasSideEffects = 0 in {
5952 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5953 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5955 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5957 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5958 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5960 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5961 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5963 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5965 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5966 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5970 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5971 let hasSideEffects = 0 in {
5972 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5973 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5975 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5976 []>, Sched<[WriteShuffle]>;
5978 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5979 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5981 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5982 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5986 let Predicates = [HasAVX] in
5987 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5988 let Predicates = [HasAVX2] in
5989 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5990 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5991 defm PALIGN : ssse3_palignr<"palignr">;
5993 let Predicates = [HasAVX2] in {
5994 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5995 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5996 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5997 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5998 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5999 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6000 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6001 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6004 let Predicates = [HasAVX] in {
6005 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6006 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6007 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6008 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6009 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6010 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6011 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6012 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6015 let Predicates = [UseSSSE3] in {
6016 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6017 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6018 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6019 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6020 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6021 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6022 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6023 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6026 //===---------------------------------------------------------------------===//
6027 // SSSE3 - Thread synchronization
6028 //===---------------------------------------------------------------------===//
6030 let SchedRW = [WriteSystem] in {
6031 let usesCustomInserter = 1 in {
6032 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
6033 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
6034 Requires<[HasSSE3]>;
6037 let Uses = [EAX, ECX, EDX] in
6038 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
6039 TB, Requires<[HasSSE3]>;
6040 let Uses = [ECX, EAX] in
6041 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
6042 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
6043 TB, Requires<[HasSSE3]>;
6046 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
6047 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
6049 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
6050 Requires<[Not64BitMode]>;
6051 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
6052 Requires<[In64BitMode]>;
6054 //===----------------------------------------------------------------------===//
6055 // SSE4.1 - Packed Move with Sign/Zero Extend
6056 //===----------------------------------------------------------------------===//
6058 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
6059 RegisterClass OutRC, RegisterClass InRC,
6061 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
6062 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6064 Sched<[itins.Sched]>;
6066 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
6067 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6069 itins.rm>, Sched<[itins.Sched.Folded]>;
6072 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
6073 X86MemOperand MemOp, X86MemOperand MemYOp,
6074 OpndItins SSEItins, OpndItins AVXItins,
6075 OpndItins AVX2Itins> {
6076 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
6077 let Predicates = [HasAVX] in
6078 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
6079 VR128, VR128, AVXItins>, VEX;
6080 let Predicates = [HasAVX2] in
6081 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
6082 VR256, VR128, AVX2Itins>, VEX, VEX_L;
6085 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
6086 X86MemOperand MemOp, X86MemOperand MemYOp> {
6087 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
6089 SSE_INTALU_ITINS_SHUFF_P,
6090 DEFAULT_ITINS_SHUFFLESCHED,
6091 DEFAULT_ITINS_SHUFFLESCHED>;
6092 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
6093 !strconcat("pmovzx", OpcodeStr),
6095 SSE_INTALU_ITINS_SHUFF_P,
6096 DEFAULT_ITINS_SHUFFLESCHED,
6097 DEFAULT_ITINS_SHUFFLESCHED>;
6100 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
6101 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
6102 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
6104 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
6105 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
6107 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
6110 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
6111 // Register-Register patterns
6112 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
6113 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
6114 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
6115 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
6116 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
6117 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
6119 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
6120 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
6121 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
6122 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
6124 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
6125 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
6127 // On AVX2, we also support 256bit inputs.
6128 // FIXME: remove these patterns when the old shuffle lowering goes away.
6129 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
6130 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6131 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
6132 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6133 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
6134 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6136 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
6137 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6138 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
6139 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6141 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
6142 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6144 // Simple Register-Memory patterns
6145 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6146 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6147 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6148 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6149 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6150 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6152 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6153 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6154 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6155 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6157 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6158 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6160 // AVX2 Register-Memory patterns
6161 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6162 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6163 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6164 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6165 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6166 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6167 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6168 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6170 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6171 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6172 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6173 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6174 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6175 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6176 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6177 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6179 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6180 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6181 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6182 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6183 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6184 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6185 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6186 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6188 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6189 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6190 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6191 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6192 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6193 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6194 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6195 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6197 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6198 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6199 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6200 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6201 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6202 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6203 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6204 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6206 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6207 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6208 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6209 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6210 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6211 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6212 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6213 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6216 let Predicates = [HasAVX2] in {
6217 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6218 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6221 // SSE4.1/AVX patterns.
6222 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6223 SDNode ExtOp, PatFrag ExtLoad16> {
6224 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6225 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6226 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6227 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6228 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6229 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6231 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6232 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6233 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6234 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6236 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6237 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6239 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6240 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6241 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6242 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6243 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6244 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6246 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6247 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6248 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6249 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6251 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6252 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6254 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6255 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6256 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6257 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6258 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6259 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6260 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6261 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6262 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6263 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6265 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6266 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6267 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6268 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6269 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6270 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6271 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6272 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6274 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6275 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6276 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6277 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6278 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6279 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6280 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6281 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6283 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6284 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6285 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6286 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6287 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6288 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6289 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6290 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6291 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6292 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6294 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6295 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6296 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6297 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6298 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6299 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6300 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6301 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6303 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6304 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6305 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6306 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6307 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6308 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6309 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6310 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6311 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6312 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6315 let Predicates = [HasAVX] in {
6316 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6317 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6320 let Predicates = [UseSSE41] in {
6321 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6322 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6325 //===----------------------------------------------------------------------===//
6326 // SSE4.1 - Extract Instructions
6327 //===----------------------------------------------------------------------===//
6329 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6330 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6331 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6332 (ins VR128:$src1, u8imm:$src2),
6333 !strconcat(OpcodeStr,
6334 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6335 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6337 Sched<[WriteShuffle]>;
6338 let hasSideEffects = 0, mayStore = 1,
6339 SchedRW = [WriteShuffleLd, WriteRMW] in
6340 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6341 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6342 !strconcat(OpcodeStr,
6343 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6344 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6345 imm:$src2)))), addr:$dst)]>;
6348 let Predicates = [HasAVX] in
6349 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6351 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6354 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6355 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6356 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6357 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6358 (ins VR128:$src1, u8imm:$src2),
6359 !strconcat(OpcodeStr,
6360 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6361 []>, Sched<[WriteShuffle]>;
6363 let hasSideEffects = 0, mayStore = 1,
6364 SchedRW = [WriteShuffleLd, WriteRMW] in
6365 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6366 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6367 !strconcat(OpcodeStr,
6368 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6369 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6370 imm:$src2)))), addr:$dst)]>;
6373 let Predicates = [HasAVX] in
6374 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6376 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6379 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6380 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6381 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6382 (ins VR128:$src1, u8imm:$src2),
6383 !strconcat(OpcodeStr,
6384 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6386 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6387 Sched<[WriteShuffle]>;
6388 let SchedRW = [WriteShuffleLd, WriteRMW] in
6389 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6390 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6391 !strconcat(OpcodeStr,
6392 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6393 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6397 let Predicates = [HasAVX] in
6398 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6400 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6402 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6403 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6404 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6405 (ins VR128:$src1, u8imm:$src2),
6406 !strconcat(OpcodeStr,
6407 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6409 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6410 Sched<[WriteShuffle]>, REX_W;
6411 let SchedRW = [WriteShuffleLd, WriteRMW] in
6412 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6413 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6414 !strconcat(OpcodeStr,
6415 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6416 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6417 addr:$dst)]>, REX_W;
6420 let Predicates = [HasAVX] in
6421 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6423 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6425 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6427 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6428 OpndItins itins = DEFAULT_ITINS> {
6429 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6430 (ins VR128:$src1, u8imm:$src2),
6431 !strconcat(OpcodeStr,
6432 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6433 [(set GR32orGR64:$dst,
6434 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6435 itins.rr>, Sched<[WriteFBlend]>;
6436 let SchedRW = [WriteFBlendLd, WriteRMW] in
6437 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6438 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6439 !strconcat(OpcodeStr,
6440 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6441 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6442 addr:$dst)], itins.rm>;
6445 let ExeDomain = SSEPackedSingle in {
6446 let Predicates = [UseAVX] in
6447 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6448 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6451 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6452 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6455 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6457 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6460 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6461 Requires<[UseSSE41]>;
6463 //===----------------------------------------------------------------------===//
6464 // SSE4.1 - Insert Instructions
6465 //===----------------------------------------------------------------------===//
6467 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6468 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6469 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6471 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6473 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6475 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6476 Sched<[WriteShuffle]>;
6477 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6478 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6480 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6482 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6484 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6485 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6488 let Predicates = [HasAVX] in
6489 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6490 let Constraints = "$src1 = $dst" in
6491 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6493 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6494 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6495 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6497 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6499 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6501 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6502 Sched<[WriteShuffle]>;
6503 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6504 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6506 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6508 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6510 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6511 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6514 let Predicates = [HasAVX] in
6515 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6516 let Constraints = "$src1 = $dst" in
6517 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6519 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6520 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6521 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6523 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6525 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6527 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6528 Sched<[WriteShuffle]>;
6529 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6530 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6532 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6534 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6536 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6537 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6540 let Predicates = [HasAVX] in
6541 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6542 let Constraints = "$src1 = $dst" in
6543 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6545 // insertps has a few different modes, there's the first two here below which
6546 // are optimized inserts that won't zero arbitrary elements in the destination
6547 // vector. The next one matches the intrinsic and could zero arbitrary elements
6548 // in the target vector.
6549 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6550 OpndItins itins = DEFAULT_ITINS> {
6551 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6552 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6554 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6556 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6558 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6559 Sched<[WriteFShuffle]>;
6560 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6561 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6563 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6565 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6567 (X86insertps VR128:$src1,
6568 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6569 imm:$src3))], itins.rm>,
6570 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6573 let ExeDomain = SSEPackedSingle in {
6574 let Predicates = [UseAVX] in
6575 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6576 let Constraints = "$src1 = $dst" in
6577 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6580 let Predicates = [UseSSE41] in {
6581 // If we're inserting an element from a load or a null pshuf of a load,
6582 // fold the load into the insertps instruction.
6583 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6584 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6586 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6587 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6588 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6589 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6592 let Predicates = [UseAVX] in {
6593 // If we're inserting an element from a vbroadcast of a load, fold the
6594 // load into the X86insertps instruction.
6595 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6596 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6597 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6598 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6599 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6600 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6603 //===----------------------------------------------------------------------===//
6604 // SSE4.1 - Round Instructions
6605 //===----------------------------------------------------------------------===//
6607 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6608 X86MemOperand x86memop, RegisterClass RC,
6609 PatFrag mem_frag32, PatFrag mem_frag64,
6610 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6611 let ExeDomain = SSEPackedSingle in {
6612 // Intrinsic operation, reg.
6613 // Vector intrinsic operation, reg
6614 def PSr : SS4AIi8<opcps, MRMSrcReg,
6615 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6616 !strconcat(OpcodeStr,
6617 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6618 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6619 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6621 // Vector intrinsic operation, mem
6622 def PSm : SS4AIi8<opcps, MRMSrcMem,
6623 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6624 !strconcat(OpcodeStr,
6625 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6627 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6628 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6629 } // ExeDomain = SSEPackedSingle
6631 let ExeDomain = SSEPackedDouble in {
6632 // Vector intrinsic operation, reg
6633 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6634 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6635 !strconcat(OpcodeStr,
6636 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6637 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6638 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6640 // Vector intrinsic operation, mem
6641 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6642 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6643 !strconcat(OpcodeStr,
6644 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6646 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6647 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6648 } // ExeDomain = SSEPackedDouble
6651 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6654 Intrinsic F64Int, bit Is2Addr = 1> {
6655 let ExeDomain = GenericDomain in {
6657 let hasSideEffects = 0 in
6658 def SSr : SS4AIi8<opcss, MRMSrcReg,
6659 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6661 !strconcat(OpcodeStr,
6662 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6663 !strconcat(OpcodeStr,
6664 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6665 []>, Sched<[WriteFAdd]>;
6667 // Intrinsic operation, reg.
6668 let isCodeGenOnly = 1 in
6669 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6670 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6672 !strconcat(OpcodeStr,
6673 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6674 !strconcat(OpcodeStr,
6675 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6676 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6679 // Intrinsic operation, mem.
6680 def SSm : SS4AIi8<opcss, MRMSrcMem,
6681 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6683 !strconcat(OpcodeStr,
6684 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6685 !strconcat(OpcodeStr,
6686 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6688 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6689 Sched<[WriteFAddLd, ReadAfterLd]>;
6692 let hasSideEffects = 0 in
6693 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6694 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6696 !strconcat(OpcodeStr,
6697 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6698 !strconcat(OpcodeStr,
6699 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6700 []>, Sched<[WriteFAdd]>;
6702 // Intrinsic operation, reg.
6703 let isCodeGenOnly = 1 in
6704 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6705 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6707 !strconcat(OpcodeStr,
6708 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6709 !strconcat(OpcodeStr,
6710 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6711 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6714 // Intrinsic operation, mem.
6715 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6716 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6718 !strconcat(OpcodeStr,
6719 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6720 !strconcat(OpcodeStr,
6721 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6723 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6724 Sched<[WriteFAddLd, ReadAfterLd]>;
6725 } // ExeDomain = GenericDomain
6728 // FP round - roundss, roundps, roundsd, roundpd
6729 let Predicates = [HasAVX] in {
6731 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6732 loadv4f32, loadv2f64,
6733 int_x86_sse41_round_ps,
6734 int_x86_sse41_round_pd>, VEX;
6735 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6736 loadv8f32, loadv4f64,
6737 int_x86_avx_round_ps_256,
6738 int_x86_avx_round_pd_256>, VEX, VEX_L;
6739 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6740 int_x86_sse41_round_ss,
6741 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6744 let Predicates = [UseAVX] in {
6745 def : Pat<(ffloor FR32:$src),
6746 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6747 def : Pat<(f64 (ffloor FR64:$src)),
6748 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6749 def : Pat<(f32 (fnearbyint FR32:$src)),
6750 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6751 def : Pat<(f64 (fnearbyint FR64:$src)),
6752 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6753 def : Pat<(f32 (fceil FR32:$src)),
6754 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6755 def : Pat<(f64 (fceil FR64:$src)),
6756 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6757 def : Pat<(f32 (frint FR32:$src)),
6758 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6759 def : Pat<(f64 (frint FR64:$src)),
6760 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6761 def : Pat<(f32 (ftrunc FR32:$src)),
6762 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6763 def : Pat<(f64 (ftrunc FR64:$src)),
6764 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6767 let Predicates = [HasAVX] in {
6768 def : Pat<(v4f32 (ffloor VR128:$src)),
6769 (VROUNDPSr VR128:$src, (i32 0x1))>;
6770 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6771 (VROUNDPSr VR128:$src, (i32 0xC))>;
6772 def : Pat<(v4f32 (fceil VR128:$src)),
6773 (VROUNDPSr VR128:$src, (i32 0x2))>;
6774 def : Pat<(v4f32 (frint VR128:$src)),
6775 (VROUNDPSr VR128:$src, (i32 0x4))>;
6776 def : Pat<(v4f32 (ftrunc VR128:$src)),
6777 (VROUNDPSr VR128:$src, (i32 0x3))>;
6779 def : Pat<(v2f64 (ffloor VR128:$src)),
6780 (VROUNDPDr VR128:$src, (i32 0x1))>;
6781 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6782 (VROUNDPDr VR128:$src, (i32 0xC))>;
6783 def : Pat<(v2f64 (fceil VR128:$src)),
6784 (VROUNDPDr VR128:$src, (i32 0x2))>;
6785 def : Pat<(v2f64 (frint VR128:$src)),
6786 (VROUNDPDr VR128:$src, (i32 0x4))>;
6787 def : Pat<(v2f64 (ftrunc VR128:$src)),
6788 (VROUNDPDr VR128:$src, (i32 0x3))>;
6790 def : Pat<(v8f32 (ffloor VR256:$src)),
6791 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6792 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6793 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6794 def : Pat<(v8f32 (fceil VR256:$src)),
6795 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6796 def : Pat<(v8f32 (frint VR256:$src)),
6797 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6798 def : Pat<(v8f32 (ftrunc VR256:$src)),
6799 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6801 def : Pat<(v4f64 (ffloor VR256:$src)),
6802 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6803 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6804 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6805 def : Pat<(v4f64 (fceil VR256:$src)),
6806 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6807 def : Pat<(v4f64 (frint VR256:$src)),
6808 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6809 def : Pat<(v4f64 (ftrunc VR256:$src)),
6810 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6813 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6814 memopv4f32, memopv2f64,
6815 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6816 let Constraints = "$src1 = $dst" in
6817 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6818 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6820 let Predicates = [UseSSE41] in {
6821 def : Pat<(ffloor FR32:$src),
6822 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6823 def : Pat<(f64 (ffloor FR64:$src)),
6824 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6825 def : Pat<(f32 (fnearbyint FR32:$src)),
6826 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6827 def : Pat<(f64 (fnearbyint FR64:$src)),
6828 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6829 def : Pat<(f32 (fceil FR32:$src)),
6830 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6831 def : Pat<(f64 (fceil FR64:$src)),
6832 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6833 def : Pat<(f32 (frint FR32:$src)),
6834 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6835 def : Pat<(f64 (frint FR64:$src)),
6836 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6837 def : Pat<(f32 (ftrunc FR32:$src)),
6838 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6839 def : Pat<(f64 (ftrunc FR64:$src)),
6840 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6842 def : Pat<(v4f32 (ffloor VR128:$src)),
6843 (ROUNDPSr VR128:$src, (i32 0x1))>;
6844 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6845 (ROUNDPSr VR128:$src, (i32 0xC))>;
6846 def : Pat<(v4f32 (fceil VR128:$src)),
6847 (ROUNDPSr VR128:$src, (i32 0x2))>;
6848 def : Pat<(v4f32 (frint VR128:$src)),
6849 (ROUNDPSr VR128:$src, (i32 0x4))>;
6850 def : Pat<(v4f32 (ftrunc VR128:$src)),
6851 (ROUNDPSr VR128:$src, (i32 0x3))>;
6853 def : Pat<(v2f64 (ffloor VR128:$src)),
6854 (ROUNDPDr VR128:$src, (i32 0x1))>;
6855 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6856 (ROUNDPDr VR128:$src, (i32 0xC))>;
6857 def : Pat<(v2f64 (fceil VR128:$src)),
6858 (ROUNDPDr VR128:$src, (i32 0x2))>;
6859 def : Pat<(v2f64 (frint VR128:$src)),
6860 (ROUNDPDr VR128:$src, (i32 0x4))>;
6861 def : Pat<(v2f64 (ftrunc VR128:$src)),
6862 (ROUNDPDr VR128:$src, (i32 0x3))>;
6865 //===----------------------------------------------------------------------===//
6866 // SSE4.1 - Packed Bit Test
6867 //===----------------------------------------------------------------------===//
6869 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6870 // the intel intrinsic that corresponds to this.
6871 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6872 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6873 "vptest\t{$src2, $src1|$src1, $src2}",
6874 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6875 Sched<[WriteVecLogic]>, VEX;
6876 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6877 "vptest\t{$src2, $src1|$src1, $src2}",
6878 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6879 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6881 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6882 "vptest\t{$src2, $src1|$src1, $src2}",
6883 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6884 Sched<[WriteVecLogic]>, VEX, VEX_L;
6885 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6886 "vptest\t{$src2, $src1|$src1, $src2}",
6887 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6888 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6891 let Defs = [EFLAGS] in {
6892 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6893 "ptest\t{$src2, $src1|$src1, $src2}",
6894 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6895 Sched<[WriteVecLogic]>;
6896 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6897 "ptest\t{$src2, $src1|$src1, $src2}",
6898 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6899 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6902 // The bit test instructions below are AVX only
6903 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6904 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6905 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6906 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6907 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6908 Sched<[WriteVecLogic]>, VEX;
6909 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6910 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6911 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6912 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6915 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6916 let ExeDomain = SSEPackedSingle in {
6917 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6918 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6921 let ExeDomain = SSEPackedDouble in {
6922 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6923 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6928 //===----------------------------------------------------------------------===//
6929 // SSE4.1 - Misc Instructions
6930 //===----------------------------------------------------------------------===//
6932 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6933 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6934 "popcnt{w}\t{$src, $dst|$dst, $src}",
6935 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6936 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6938 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6939 "popcnt{w}\t{$src, $dst|$dst, $src}",
6940 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6941 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6942 Sched<[WriteFAddLd]>, OpSize16, XS;
6944 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6945 "popcnt{l}\t{$src, $dst|$dst, $src}",
6946 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6947 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6950 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6951 "popcnt{l}\t{$src, $dst|$dst, $src}",
6952 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6953 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6954 Sched<[WriteFAddLd]>, OpSize32, XS;
6956 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6957 "popcnt{q}\t{$src, $dst|$dst, $src}",
6958 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6959 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6960 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6961 "popcnt{q}\t{$src, $dst|$dst, $src}",
6962 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6963 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6964 Sched<[WriteFAddLd]>, XS;
6969 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6970 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6972 X86FoldableSchedWrite Sched> {
6973 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6975 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6976 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6978 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6980 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6982 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>,
6983 Sched<[Sched.Folded]>;
6986 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6987 // model, although the naming is misleading.
6988 let Predicates = [HasAVX] in
6989 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6990 int_x86_sse41_phminposuw,
6992 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6993 int_x86_sse41_phminposuw,
6996 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6997 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6998 Intrinsic IntId128, bit Is2Addr = 1,
6999 OpndItins itins = DEFAULT_ITINS> {
7000 let isCommutable = 1 in
7001 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7002 (ins VR128:$src1, VR128:$src2),
7004 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7005 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7006 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
7007 itins.rr>, Sched<[itins.Sched]>;
7008 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7009 (ins VR128:$src1, i128mem:$src2),
7011 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7012 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7014 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
7015 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7018 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
7019 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
7021 X86FoldableSchedWrite Sched> {
7022 let isCommutable = 1 in
7023 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
7024 (ins VR256:$src1, VR256:$src2),
7025 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7026 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
7028 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
7029 (ins VR256:$src1, i256mem:$src2),
7030 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7032 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
7033 Sched<[Sched.Folded, ReadAfterLd]>;
7037 /// SS48I_binop_rm - Simple SSE41 binary operator.
7038 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7039 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7040 X86MemOperand x86memop, bit Is2Addr = 1,
7041 OpndItins itins = SSE_INTALU_ITINS_P> {
7042 let isCommutable = 1 in
7043 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7044 (ins RC:$src1, RC:$src2),
7046 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7047 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7048 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7049 Sched<[itins.Sched]>;
7050 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7051 (ins RC:$src1, x86memop:$src2),
7053 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7054 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7056 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
7057 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7060 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
7062 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
7063 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
7064 PatFrag memop_frag, X86MemOperand x86memop,
7066 bit IsCommutable = 0, bit Is2Addr = 1> {
7067 let isCommutable = IsCommutable in
7068 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7069 (ins RC:$src1, RC:$src2),
7071 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7072 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7073 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
7074 Sched<[itins.Sched]>;
7075 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7076 (ins RC:$src1, x86memop:$src2),
7078 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7079 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7080 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
7081 (bitconvert (memop_frag addr:$src2)))))]>,
7082 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7085 let Predicates = [HasAVX, NoVLX] in {
7086 let isCommutable = 0 in
7087 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
7088 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7090 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
7091 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7093 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
7094 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7096 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
7097 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7099 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
7100 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7102 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
7103 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7105 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
7106 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7108 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
7109 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7111 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
7112 VR128, loadv2i64, i128mem,
7113 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
7116 let Predicates = [HasAVX2, NoVLX] in {
7117 let isCommutable = 0 in
7118 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
7119 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7121 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
7122 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7124 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
7125 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7127 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
7128 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7130 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
7131 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7133 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
7134 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7136 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
7137 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7139 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
7140 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7142 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
7143 VR256, loadv4i64, i256mem,
7144 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
7147 let Constraints = "$src1 = $dst" in {
7148 let isCommutable = 0 in
7149 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
7150 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7151 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
7152 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7153 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
7154 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7155 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
7156 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7157 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
7158 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7159 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
7160 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7161 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
7162 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7163 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7164 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7165 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
7166 VR128, memopv2i64, i128mem,
7167 SSE_INTMUL_ITINS_P, 1>;
7170 let Predicates = [HasAVX, NoVLX] in {
7171 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7172 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
7174 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7175 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7178 let Predicates = [HasAVX2] in {
7179 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7180 memopv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
7182 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7183 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7187 let Constraints = "$src1 = $dst" in {
7188 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7189 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7190 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7191 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7194 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7195 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7196 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7197 X86MemOperand x86memop, bit Is2Addr = 1,
7198 OpndItins itins = DEFAULT_ITINS> {
7199 let isCommutable = 1 in
7200 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7201 (ins RC:$src1, RC:$src2, u8imm:$src3),
7203 !strconcat(OpcodeStr,
7204 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7205 !strconcat(OpcodeStr,
7206 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7207 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7208 Sched<[itins.Sched]>;
7209 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7210 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
7212 !strconcat(OpcodeStr,
7213 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7214 !strconcat(OpcodeStr,
7215 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7218 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7219 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7222 let Predicates = [HasAVX] in {
7223 let isCommutable = 0 in {
7224 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7225 VR128, loadv2i64, i128mem, 0,
7226 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7229 let ExeDomain = SSEPackedSingle in {
7230 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7231 VR128, loadv4f32, f128mem, 0,
7232 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7233 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7234 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7235 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7238 let ExeDomain = SSEPackedDouble in {
7239 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7240 VR128, loadv2f64, f128mem, 0,
7241 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7242 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7243 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7244 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7247 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7248 VR128, loadv2i64, i128mem, 0,
7249 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7251 let ExeDomain = SSEPackedSingle in
7252 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7253 VR128, loadv4f32, f128mem, 0,
7254 SSE_DPPS_ITINS>, VEX_4V;
7255 let ExeDomain = SSEPackedDouble in
7256 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7257 VR128, loadv2f64, f128mem, 0,
7258 SSE_DPPS_ITINS>, VEX_4V;
7259 let ExeDomain = SSEPackedSingle in
7260 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7261 VR256, loadv8f32, i256mem, 0,
7262 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7265 let Predicates = [HasAVX2] in {
7266 let isCommutable = 0 in {
7267 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7268 VR256, loadv4i64, i256mem, 0,
7269 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7271 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7272 VR256, loadv4i64, i256mem, 0,
7273 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7276 let Constraints = "$src1 = $dst" in {
7277 let isCommutable = 0 in {
7278 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7279 VR128, memopv2i64, i128mem,
7280 1, SSE_MPSADBW_ITINS>;
7282 let ExeDomain = SSEPackedSingle in
7283 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7284 VR128, memopv4f32, f128mem,
7285 1, SSE_INTALU_ITINS_FBLEND_P>;
7286 let ExeDomain = SSEPackedDouble in
7287 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7288 VR128, memopv2f64, f128mem,
7289 1, SSE_INTALU_ITINS_FBLEND_P>;
7290 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7291 VR128, memopv2i64, i128mem,
7292 1, SSE_INTALU_ITINS_BLEND_P>;
7293 let ExeDomain = SSEPackedSingle in
7294 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7295 VR128, memopv4f32, f128mem, 1,
7297 let ExeDomain = SSEPackedDouble in
7298 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7299 VR128, memopv2f64, f128mem, 1,
7303 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7304 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7305 RegisterClass RC, X86MemOperand x86memop,
7306 PatFrag mem_frag, Intrinsic IntId,
7307 X86FoldableSchedWrite Sched> {
7308 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7309 (ins RC:$src1, RC:$src2, RC:$src3),
7310 !strconcat(OpcodeStr,
7311 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7312 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7313 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7316 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7317 (ins RC:$src1, x86memop:$src2, RC:$src3),
7318 !strconcat(OpcodeStr,
7319 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7321 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7323 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7324 Sched<[Sched.Folded, ReadAfterLd]>;
7327 let Predicates = [HasAVX] in {
7328 let ExeDomain = SSEPackedDouble in {
7329 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7330 loadv2f64, int_x86_sse41_blendvpd,
7332 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7333 loadv4f64, int_x86_avx_blendv_pd_256,
7334 WriteFVarBlend>, VEX_L;
7335 } // ExeDomain = SSEPackedDouble
7336 let ExeDomain = SSEPackedSingle in {
7337 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7338 loadv4f32, int_x86_sse41_blendvps,
7340 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7341 loadv8f32, int_x86_avx_blendv_ps_256,
7342 WriteFVarBlend>, VEX_L;
7343 } // ExeDomain = SSEPackedSingle
7344 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7345 loadv2i64, int_x86_sse41_pblendvb,
7349 let Predicates = [HasAVX2] in {
7350 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7351 loadv4i64, int_x86_avx2_pblendvb,
7352 WriteVarBlend>, VEX_L;
7355 let Predicates = [HasAVX] in {
7356 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7357 (v16i8 VR128:$src2))),
7358 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7359 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7360 (v4i32 VR128:$src2))),
7361 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7362 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7363 (v4f32 VR128:$src2))),
7364 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7365 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7366 (v2i64 VR128:$src2))),
7367 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7368 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7369 (v2f64 VR128:$src2))),
7370 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7371 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7372 (v8i32 VR256:$src2))),
7373 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7374 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7375 (v8f32 VR256:$src2))),
7376 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7377 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7378 (v4i64 VR256:$src2))),
7379 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7380 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7381 (v4f64 VR256:$src2))),
7382 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7384 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7386 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7387 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7389 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7391 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7393 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7394 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7396 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7397 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7399 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7402 let Predicates = [HasAVX2] in {
7403 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7404 (v32i8 VR256:$src2))),
7405 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7406 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7408 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7412 let Predicates = [UseAVX] in {
7413 let AddedComplexity = 15 in {
7414 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7415 // MOVS{S,D} to the lower bits.
7416 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7417 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7418 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7419 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7420 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7421 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7422 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7423 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7425 // Move low f32 and clear high bits.
7426 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7427 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7428 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7429 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7432 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7433 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7434 (SUBREG_TO_REG (i32 0),
7435 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7437 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7438 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7439 (SUBREG_TO_REG (i64 0),
7440 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7443 // Move low f64 and clear high bits.
7444 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7445 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7447 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7448 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7451 let Predicates = [UseSSE41] in {
7452 // With SSE41 we can use blends for these patterns.
7453 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7454 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7455 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7456 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7457 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7458 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7462 /// SS41I_ternary_int - SSE 4.1 ternary operator
7463 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7464 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7465 X86MemOperand x86memop, Intrinsic IntId,
7466 OpndItins itins = DEFAULT_ITINS> {
7467 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7468 (ins VR128:$src1, VR128:$src2),
7469 !strconcat(OpcodeStr,
7470 "\t{$src2, $dst|$dst, $src2}"),
7471 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7472 itins.rr>, Sched<[itins.Sched]>;
7474 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7475 (ins VR128:$src1, x86memop:$src2),
7476 !strconcat(OpcodeStr,
7477 "\t{$src2, $dst|$dst, $src2}"),
7480 (bitconvert (mem_frag addr:$src2)), XMM0))],
7481 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7485 let ExeDomain = SSEPackedDouble in
7486 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7487 int_x86_sse41_blendvpd,
7488 DEFAULT_ITINS_FBLENDSCHED>;
7489 let ExeDomain = SSEPackedSingle in
7490 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7491 int_x86_sse41_blendvps,
7492 DEFAULT_ITINS_FBLENDSCHED>;
7493 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7494 int_x86_sse41_pblendvb,
7495 DEFAULT_ITINS_VARBLENDSCHED>;
7497 // Aliases with the implicit xmm0 argument
7498 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7499 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7500 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7501 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7502 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7503 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7504 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7505 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7506 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7507 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7508 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7509 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7511 let Predicates = [UseSSE41] in {
7512 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7513 (v16i8 VR128:$src2))),
7514 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7515 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7516 (v4i32 VR128:$src2))),
7517 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7518 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7519 (v4f32 VR128:$src2))),
7520 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7521 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7522 (v2i64 VR128:$src2))),
7523 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7524 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7525 (v2f64 VR128:$src2))),
7526 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7528 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7530 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7531 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7533 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7534 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7536 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7540 let SchedRW = [WriteLoad] in {
7541 let Predicates = [HasAVX] in
7542 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7543 "vmovntdqa\t{$src, $dst|$dst, $src}",
7544 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7546 let Predicates = [HasAVX2] in
7547 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7548 "vmovntdqa\t{$src, $dst|$dst, $src}",
7549 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7551 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7552 "movntdqa\t{$src, $dst|$dst, $src}",
7553 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7556 //===----------------------------------------------------------------------===//
7557 // SSE4.2 - Compare Instructions
7558 //===----------------------------------------------------------------------===//
7560 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7561 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7562 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7563 X86MemOperand x86memop, bit Is2Addr = 1> {
7564 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7565 (ins RC:$src1, RC:$src2),
7567 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7568 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7569 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7570 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7571 (ins RC:$src1, x86memop:$src2),
7573 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7574 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7576 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7579 let Predicates = [HasAVX] in
7580 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7581 loadv2i64, i128mem, 0>, VEX_4V;
7583 let Predicates = [HasAVX2] in
7584 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7585 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7587 let Constraints = "$src1 = $dst" in
7588 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7589 memopv2i64, i128mem>;
7591 //===----------------------------------------------------------------------===//
7592 // SSE4.2 - String/text Processing Instructions
7593 //===----------------------------------------------------------------------===//
7595 // Packed Compare Implicit Length Strings, Return Mask
7596 multiclass pseudo_pcmpistrm<string asm> {
7597 def REG : PseudoI<(outs VR128:$dst),
7598 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7599 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7601 def MEM : PseudoI<(outs VR128:$dst),
7602 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7603 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7604 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7607 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7608 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7609 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7612 multiclass pcmpistrm_SS42AI<string asm> {
7613 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7614 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7615 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7616 []>, Sched<[WritePCmpIStrM]>;
7618 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7619 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7620 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7621 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7624 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7625 let Predicates = [HasAVX] in
7626 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7627 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7630 // Packed Compare Explicit Length Strings, Return Mask
7631 multiclass pseudo_pcmpestrm<string asm> {
7632 def REG : PseudoI<(outs VR128:$dst),
7633 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7634 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7635 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7636 def MEM : PseudoI<(outs VR128:$dst),
7637 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7638 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7639 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7642 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7643 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7644 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7647 multiclass SS42AI_pcmpestrm<string asm> {
7648 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7649 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7650 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7651 []>, Sched<[WritePCmpEStrM]>;
7653 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7654 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7655 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7656 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7659 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7660 let Predicates = [HasAVX] in
7661 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7662 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7665 // Packed Compare Implicit Length Strings, Return Index
7666 multiclass pseudo_pcmpistri<string asm> {
7667 def REG : PseudoI<(outs GR32:$dst),
7668 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7669 [(set GR32:$dst, EFLAGS,
7670 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7671 def MEM : PseudoI<(outs GR32:$dst),
7672 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7673 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7674 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7677 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7678 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7679 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7682 multiclass SS42AI_pcmpistri<string asm> {
7683 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7684 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7685 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7686 []>, Sched<[WritePCmpIStrI]>;
7688 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7689 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7690 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7691 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7694 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7695 let Predicates = [HasAVX] in
7696 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7697 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7700 // Packed Compare Explicit Length Strings, Return Index
7701 multiclass pseudo_pcmpestri<string asm> {
7702 def REG : PseudoI<(outs GR32:$dst),
7703 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7704 [(set GR32:$dst, EFLAGS,
7705 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7706 def MEM : PseudoI<(outs GR32:$dst),
7707 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7708 [(set GR32:$dst, EFLAGS,
7709 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7713 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7714 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7715 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7718 multiclass SS42AI_pcmpestri<string asm> {
7719 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7720 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7721 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7722 []>, Sched<[WritePCmpEStrI]>;
7724 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7725 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7726 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7727 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7730 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7731 let Predicates = [HasAVX] in
7732 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7733 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7736 //===----------------------------------------------------------------------===//
7737 // SSE4.2 - CRC Instructions
7738 //===----------------------------------------------------------------------===//
7740 // No CRC instructions have AVX equivalents
7742 // crc intrinsic instruction
7743 // This set of instructions are only rm, the only difference is the size
7745 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7746 RegisterClass RCIn, SDPatternOperator Int> :
7747 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7748 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7749 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7752 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7753 X86MemOperand x86memop, SDPatternOperator Int> :
7754 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7755 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7756 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7757 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7759 let Constraints = "$src1 = $dst" in {
7760 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7761 int_x86_sse42_crc32_32_8>;
7762 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7763 int_x86_sse42_crc32_32_8>;
7764 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7765 int_x86_sse42_crc32_32_16>, OpSize16;
7766 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7767 int_x86_sse42_crc32_32_16>, OpSize16;
7768 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7769 int_x86_sse42_crc32_32_32>, OpSize32;
7770 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7771 int_x86_sse42_crc32_32_32>, OpSize32;
7772 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7773 int_x86_sse42_crc32_64_64>, REX_W;
7774 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7775 int_x86_sse42_crc32_64_64>, REX_W;
7776 let hasSideEffects = 0 in {
7778 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7780 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7785 //===----------------------------------------------------------------------===//
7786 // SHA-NI Instructions
7787 //===----------------------------------------------------------------------===//
7789 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7791 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7792 (ins VR128:$src1, VR128:$src2),
7793 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7795 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7796 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7798 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7799 (ins VR128:$src1, i128mem:$src2),
7800 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7802 (set VR128:$dst, (IntId VR128:$src1,
7803 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7804 (set VR128:$dst, (IntId VR128:$src1,
7805 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7808 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7809 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7810 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7811 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7813 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7814 (i8 imm:$src3)))]>, TA;
7815 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7816 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7817 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7819 (int_x86_sha1rnds4 VR128:$src1,
7820 (bc_v4i32 (memopv2i64 addr:$src2)),
7821 (i8 imm:$src3)))]>, TA;
7823 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7824 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7825 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7828 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7830 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7831 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7834 // Aliases with explicit %xmm0
7835 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7836 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7837 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7838 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7840 //===----------------------------------------------------------------------===//
7841 // AES-NI Instructions
7842 //===----------------------------------------------------------------------===//
7844 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7845 Intrinsic IntId128, bit Is2Addr = 1> {
7846 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7847 (ins VR128:$src1, VR128:$src2),
7849 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7850 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7851 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7852 Sched<[WriteAESDecEnc]>;
7853 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7854 (ins VR128:$src1, i128mem:$src2),
7856 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7857 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7859 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
7860 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7863 // Perform One Round of an AES Encryption/Decryption Flow
7864 let Predicates = [HasAVX, HasAES] in {
7865 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7866 int_x86_aesni_aesenc, 0>, VEX_4V;
7867 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7868 int_x86_aesni_aesenclast, 0>, VEX_4V;
7869 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7870 int_x86_aesni_aesdec, 0>, VEX_4V;
7871 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7872 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7875 let Constraints = "$src1 = $dst" in {
7876 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7877 int_x86_aesni_aesenc>;
7878 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7879 int_x86_aesni_aesenclast>;
7880 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7881 int_x86_aesni_aesdec>;
7882 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7883 int_x86_aesni_aesdeclast>;
7886 // Perform the AES InvMixColumn Transformation
7887 let Predicates = [HasAVX, HasAES] in {
7888 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7890 "vaesimc\t{$src1, $dst|$dst, $src1}",
7892 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7894 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7895 (ins i128mem:$src1),
7896 "vaesimc\t{$src1, $dst|$dst, $src1}",
7897 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7898 Sched<[WriteAESIMCLd]>, VEX;
7900 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7902 "aesimc\t{$src1, $dst|$dst, $src1}",
7904 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7905 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7906 (ins i128mem:$src1),
7907 "aesimc\t{$src1, $dst|$dst, $src1}",
7908 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7909 Sched<[WriteAESIMCLd]>;
7911 // AES Round Key Generation Assist
7912 let Predicates = [HasAVX, HasAES] in {
7913 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7914 (ins VR128:$src1, u8imm:$src2),
7915 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7917 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7918 Sched<[WriteAESKeyGen]>, VEX;
7919 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7920 (ins i128mem:$src1, u8imm:$src2),
7921 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7923 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7924 Sched<[WriteAESKeyGenLd]>, VEX;
7926 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7927 (ins VR128:$src1, u8imm:$src2),
7928 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7930 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7931 Sched<[WriteAESKeyGen]>;
7932 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7933 (ins i128mem:$src1, u8imm:$src2),
7934 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7936 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7937 Sched<[WriteAESKeyGenLd]>;
7939 //===----------------------------------------------------------------------===//
7940 // PCLMUL Instructions
7941 //===----------------------------------------------------------------------===//
7943 // AVX carry-less Multiplication instructions
7944 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7945 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7946 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7948 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7949 Sched<[WriteCLMul]>;
7951 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7952 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7953 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7954 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7955 (loadv2i64 addr:$src2), imm:$src3))]>,
7956 Sched<[WriteCLMulLd, ReadAfterLd]>;
7958 // Carry-less Multiplication instructions
7959 let Constraints = "$src1 = $dst" in {
7960 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7961 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7962 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7964 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7965 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7967 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7968 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7969 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7970 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7971 (memopv2i64 addr:$src2), imm:$src3))],
7972 IIC_SSE_PCLMULQDQ_RM>,
7973 Sched<[WriteCLMulLd, ReadAfterLd]>;
7974 } // Constraints = "$src1 = $dst"
7977 multiclass pclmul_alias<string asm, int immop> {
7978 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7979 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7981 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7982 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7984 def : InstAlias<!strconcat("vpclmul", asm,
7985 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7986 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7989 def : InstAlias<!strconcat("vpclmul", asm,
7990 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7991 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7994 defm : pclmul_alias<"hqhq", 0x11>;
7995 defm : pclmul_alias<"hqlq", 0x01>;
7996 defm : pclmul_alias<"lqhq", 0x10>;
7997 defm : pclmul_alias<"lqlq", 0x00>;
7999 //===----------------------------------------------------------------------===//
8000 // SSE4A Instructions
8001 //===----------------------------------------------------------------------===//
8003 let Predicates = [HasSSE4A] in {
8005 let Constraints = "$src = $dst" in {
8006 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
8007 (ins VR128:$src, u8imm:$len, u8imm:$idx),
8008 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
8009 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
8011 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8012 (ins VR128:$src, VR128:$mask),
8013 "extrq\t{$mask, $src|$src, $mask}",
8014 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
8015 VR128:$mask))]>, PD;
8017 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
8018 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
8019 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
8020 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
8021 VR128:$src2, imm:$len, imm:$idx))]>, XD;
8022 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8023 (ins VR128:$src, VR128:$mask),
8024 "insertq\t{$mask, $src|$src, $mask}",
8025 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
8026 VR128:$mask))]>, XD;
8029 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
8030 "movntss\t{$src, $dst|$dst, $src}",
8031 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
8033 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
8034 "movntsd\t{$src, $dst|$dst, $src}",
8035 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
8038 //===----------------------------------------------------------------------===//
8040 //===----------------------------------------------------------------------===//
8042 //===----------------------------------------------------------------------===//
8043 // VBROADCAST - Load from memory and broadcast to all elements of the
8044 // destination operand
8046 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
8047 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
8048 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8049 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8050 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
8052 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
8053 X86MemOperand x86memop, ValueType VT,
8054 PatFrag ld_frag, SchedWrite Sched> :
8055 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8056 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8057 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
8058 Sched<[Sched]>, VEX {
8062 // AVX2 adds register forms
8063 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
8064 Intrinsic Int, SchedWrite Sched> :
8065 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8066 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8067 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
8069 let ExeDomain = SSEPackedSingle in {
8070 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
8071 f32mem, v4f32, loadf32, WriteLoad>;
8072 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
8073 f32mem, v8f32, loadf32,
8074 WriteFShuffleLd>, VEX_L;
8076 let ExeDomain = SSEPackedDouble in
8077 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
8078 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
8079 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
8080 int_x86_avx_vbroadcastf128_pd_256,
8081 WriteFShuffleLd>, VEX_L;
8083 let ExeDomain = SSEPackedSingle in {
8084 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
8085 int_x86_avx2_vbroadcast_ss_ps,
8087 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
8088 int_x86_avx2_vbroadcast_ss_ps_256,
8089 WriteFShuffle256>, VEX_L;
8091 let ExeDomain = SSEPackedDouble in
8092 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
8093 int_x86_avx2_vbroadcast_sd_pd_256,
8094 WriteFShuffle256>, VEX_L;
8096 let Predicates = [HasAVX2] in
8097 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
8098 int_x86_avx2_vbroadcasti128, WriteLoad>,
8101 let Predicates = [HasAVX] in
8102 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
8103 (VBROADCASTF128 addr:$src)>;
8106 //===----------------------------------------------------------------------===//
8107 // VINSERTF128 - Insert packed floating-point values
8109 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8110 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8111 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8112 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8113 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
8115 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
8116 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
8117 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8118 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
8121 let Predicates = [HasAVX] in {
8122 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
8124 (VINSERTF128rr VR256:$src1, VR128:$src2,
8125 (INSERT_get_vinsert128_imm VR256:$ins))>;
8126 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
8128 (VINSERTF128rr VR256:$src1, VR128:$src2,
8129 (INSERT_get_vinsert128_imm VR256:$ins))>;
8131 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
8133 (VINSERTF128rm VR256:$src1, addr:$src2,
8134 (INSERT_get_vinsert128_imm VR256:$ins))>;
8135 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
8137 (VINSERTF128rm VR256:$src1, addr:$src2,
8138 (INSERT_get_vinsert128_imm VR256:$ins))>;
8141 // Combine two consecutive 16-byte loads with a common destination register into
8142 // one 32-byte load to that register.
8143 let Predicates = [HasAVX, HasFastMem32] in {
8144 def : Pat<(insert_subvector
8145 (v8f32 (insert_subvector undef, (loadv4f32 addr:$src), (iPTR 0))),
8146 (loadv4f32 (add addr:$src, (iPTR 16))),
8148 (VMOVUPSYrm addr:$src)>;
8150 def : Pat<(insert_subvector
8151 (v4f64 (insert_subvector undef, (loadv2f64 addr:$src), (iPTR 0))),
8152 (loadv2f64 (add addr:$src, (iPTR 16))),
8154 (VMOVUPDYrm addr:$src)>;
8156 def : Pat<(insert_subvector
8157 (v32i8 (insert_subvector
8158 undef, (bc_v16i8 (loadv2i64 addr:$src)), (iPTR 0))),
8159 (bc_v16i8 (loadv2i64 (add addr:$src, (iPTR 16)))),
8161 (VMOVDQUYrm addr:$src)>;
8163 def : Pat<(insert_subvector
8164 (v16i16 (insert_subvector
8165 undef, (bc_v8i16 (loadv2i64 addr:$src)), (iPTR 0))),
8166 (bc_v8i16 (loadv2i64 (add addr:$src, (iPTR 16)))),
8168 (VMOVDQUYrm addr:$src)>;
8170 def : Pat<(insert_subvector
8171 (v8i32 (insert_subvector
8172 undef, (bc_v4i32 (loadv2i64 addr:$src)), (iPTR 0))),
8173 (bc_v4i32 (loadv2i64 (add addr:$src, (iPTR 16)))),
8175 (VMOVDQUYrm addr:$src)>;
8177 def : Pat<(insert_subvector
8178 (v4i64 (insert_subvector undef, (loadv2i64 addr:$src), (iPTR 0))),
8179 (loadv2i64 (add addr:$src, (iPTR 16))),
8181 (VMOVDQUYrm addr:$src)>;
8184 let Predicates = [HasAVX1Only] in {
8185 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8187 (VINSERTF128rr VR256:$src1, VR128:$src2,
8188 (INSERT_get_vinsert128_imm VR256:$ins))>;
8189 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8191 (VINSERTF128rr VR256:$src1, VR128:$src2,
8192 (INSERT_get_vinsert128_imm VR256:$ins))>;
8193 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8195 (VINSERTF128rr VR256:$src1, VR128:$src2,
8196 (INSERT_get_vinsert128_imm VR256:$ins))>;
8197 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8199 (VINSERTF128rr VR256:$src1, VR128:$src2,
8200 (INSERT_get_vinsert128_imm VR256:$ins))>;
8202 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8204 (VINSERTF128rm VR256:$src1, addr:$src2,
8205 (INSERT_get_vinsert128_imm VR256:$ins))>;
8206 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8207 (bc_v4i32 (loadv2i64 addr:$src2)),
8209 (VINSERTF128rm VR256:$src1, addr:$src2,
8210 (INSERT_get_vinsert128_imm VR256:$ins))>;
8211 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8212 (bc_v16i8 (loadv2i64 addr:$src2)),
8214 (VINSERTF128rm VR256:$src1, addr:$src2,
8215 (INSERT_get_vinsert128_imm VR256:$ins))>;
8216 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8217 (bc_v8i16 (loadv2i64 addr:$src2)),
8219 (VINSERTF128rm VR256:$src1, addr:$src2,
8220 (INSERT_get_vinsert128_imm VR256:$ins))>;
8223 //===----------------------------------------------------------------------===//
8224 // VEXTRACTF128 - Extract packed floating-point values
8226 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8227 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
8228 (ins VR256:$src1, u8imm:$src2),
8229 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8230 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
8232 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
8233 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
8234 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8235 []>, Sched<[WriteStore]>, VEX, VEX_L;
8239 let Predicates = [HasAVX] in {
8240 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8241 (v4f32 (VEXTRACTF128rr
8242 (v8f32 VR256:$src1),
8243 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8244 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8245 (v2f64 (VEXTRACTF128rr
8246 (v4f64 VR256:$src1),
8247 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8249 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
8250 (iPTR imm))), addr:$dst),
8251 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8252 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8253 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
8254 (iPTR imm))), addr:$dst),
8255 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8256 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8259 let Predicates = [HasAVX1Only] in {
8260 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8261 (v2i64 (VEXTRACTF128rr
8262 (v4i64 VR256:$src1),
8263 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8264 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8265 (v4i32 (VEXTRACTF128rr
8266 (v8i32 VR256:$src1),
8267 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8268 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8269 (v8i16 (VEXTRACTF128rr
8270 (v16i16 VR256:$src1),
8271 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8272 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8273 (v16i8 (VEXTRACTF128rr
8274 (v32i8 VR256:$src1),
8275 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8277 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8278 (iPTR imm))), addr:$dst),
8279 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8280 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8281 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8282 (iPTR imm))), addr:$dst),
8283 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8284 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8285 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8286 (iPTR imm))), addr:$dst),
8287 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8288 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8289 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8290 (iPTR imm))), addr:$dst),
8291 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8292 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8295 //===----------------------------------------------------------------------===//
8296 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8298 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8299 Intrinsic IntLd, Intrinsic IntLd256,
8300 Intrinsic IntSt, Intrinsic IntSt256> {
8301 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8302 (ins VR128:$src1, f128mem:$src2),
8303 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8304 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8306 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8307 (ins VR256:$src1, f256mem:$src2),
8308 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8309 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8311 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8312 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8313 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8314 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8315 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8316 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8318 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8321 let ExeDomain = SSEPackedSingle in
8322 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8323 int_x86_avx_maskload_ps,
8324 int_x86_avx_maskload_ps_256,
8325 int_x86_avx_maskstore_ps,
8326 int_x86_avx_maskstore_ps_256>;
8327 let ExeDomain = SSEPackedDouble in
8328 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8329 int_x86_avx_maskload_pd,
8330 int_x86_avx_maskload_pd_256,
8331 int_x86_avx_maskstore_pd,
8332 int_x86_avx_maskstore_pd_256>;
8334 //===----------------------------------------------------------------------===//
8335 // VPERMIL - Permute Single and Double Floating-Point Values
8337 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8338 RegisterClass RC, X86MemOperand x86memop_f,
8339 X86MemOperand x86memop_i, PatFrag i_frag,
8340 Intrinsic IntVar, ValueType vt> {
8341 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8342 (ins RC:$src1, RC:$src2),
8343 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8344 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8345 Sched<[WriteFShuffle]>;
8346 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8347 (ins RC:$src1, x86memop_i:$src2),
8348 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8349 [(set RC:$dst, (IntVar RC:$src1,
8350 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8351 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8353 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8354 (ins RC:$src1, u8imm:$src2),
8355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8356 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8357 Sched<[WriteFShuffle]>;
8358 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8359 (ins x86memop_f:$src1, u8imm:$src2),
8360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8362 (vt (X86VPermilpi (memop addr:$src1), (i8 imm:$src2))))]>, VEX,
8363 Sched<[WriteFShuffleLd]>;
8366 let ExeDomain = SSEPackedSingle in {
8367 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8368 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8369 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8370 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8372 let ExeDomain = SSEPackedDouble in {
8373 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8374 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8375 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8376 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8379 let Predicates = [HasAVX] in {
8380 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8381 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8382 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8383 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8384 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8385 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8386 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8387 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8389 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8390 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8391 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8392 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8393 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8395 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8396 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8397 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8399 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8400 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8401 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8402 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8403 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8404 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8405 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8406 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8408 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8409 (VPERMILPDri VR128:$src1, imm:$imm)>;
8410 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8411 (VPERMILPDmi addr:$src1, imm:$imm)>;
8414 //===----------------------------------------------------------------------===//
8415 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8417 let ExeDomain = SSEPackedSingle in {
8418 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8419 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8420 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8421 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8422 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8423 Sched<[WriteFShuffle]>;
8424 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8425 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8426 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8427 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8428 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8429 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8432 let Predicates = [HasAVX] in {
8433 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8434 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8435 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8436 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8437 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8440 let Predicates = [HasAVX1Only] in {
8441 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8442 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8443 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8444 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8445 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8446 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8447 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8448 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8450 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8451 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8452 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8453 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8454 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8455 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8456 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8457 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8458 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8459 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8460 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8461 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8464 //===----------------------------------------------------------------------===//
8465 // VZERO - Zero YMM registers
8467 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8468 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8469 // Zero All YMM registers
8470 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8471 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8473 // Zero Upper bits of YMM registers
8474 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8475 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8478 //===----------------------------------------------------------------------===//
8479 // Half precision conversion instructions
8480 //===----------------------------------------------------------------------===//
8481 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8482 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8483 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8484 [(set RC:$dst, (Int VR128:$src))]>,
8485 T8PD, VEX, Sched<[WriteCvtF2F]>;
8486 let hasSideEffects = 0, mayLoad = 1 in
8487 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8488 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8489 Sched<[WriteCvtF2FLd]>;
8492 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8493 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8494 (ins RC:$src1, i32u8imm:$src2),
8495 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8496 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8497 TAPD, VEX, Sched<[WriteCvtF2F]>;
8498 let hasSideEffects = 0, mayStore = 1,
8499 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8500 def mr : Ii8<0x1D, MRMDestMem, (outs),
8501 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8502 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8506 let Predicates = [HasF16C] in {
8507 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8508 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8509 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8510 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8512 // Pattern match vcvtph2ps of a scalar i64 load.
8513 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8514 (VCVTPH2PSrm addr:$src)>;
8515 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8516 (VCVTPH2PSrm addr:$src)>;
8519 // Patterns for matching conversions from float to half-float and vice versa.
8520 let Predicates = [HasF16C] in {
8521 def : Pat<(fp_to_f16 FR32:$src),
8522 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8523 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8525 def : Pat<(f16_to_fp GR16:$src),
8526 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8527 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8529 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8530 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8531 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8534 //===----------------------------------------------------------------------===//
8535 // AVX2 Instructions
8536 //===----------------------------------------------------------------------===//
8538 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8539 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8540 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8541 X86MemOperand x86memop> {
8542 let isCommutable = 1 in
8543 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8544 (ins RC:$src1, RC:$src2, u8imm:$src3),
8545 !strconcat(OpcodeStr,
8546 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8547 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8548 Sched<[WriteBlend]>, VEX_4V;
8549 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8550 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8551 !strconcat(OpcodeStr,
8552 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8555 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8556 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8559 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8560 VR128, loadv2i64, i128mem>;
8561 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8562 VR256, loadv4i64, i256mem>, VEX_L;
8564 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8566 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8567 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8569 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8571 //===----------------------------------------------------------------------===//
8572 // VPBROADCAST - Load from memory and broadcast to all elements of the
8573 // destination operand
8575 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8576 X86MemOperand x86memop, PatFrag ld_frag,
8577 Intrinsic Int128, Intrinsic Int256> {
8578 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8579 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8580 [(set VR128:$dst, (Int128 VR128:$src))]>,
8581 Sched<[WriteShuffle]>, VEX;
8582 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8583 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8585 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8586 Sched<[WriteLoad]>, VEX;
8587 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8588 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8589 [(set VR256:$dst, (Int256 VR128:$src))]>,
8590 Sched<[WriteShuffle256]>, VEX, VEX_L;
8591 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8592 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8594 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8595 Sched<[WriteLoad]>, VEX, VEX_L;
8598 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8599 int_x86_avx2_pbroadcastb_128,
8600 int_x86_avx2_pbroadcastb_256>;
8601 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8602 int_x86_avx2_pbroadcastw_128,
8603 int_x86_avx2_pbroadcastw_256>;
8604 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8605 int_x86_avx2_pbroadcastd_128,
8606 int_x86_avx2_pbroadcastd_256>;
8607 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8608 int_x86_avx2_pbroadcastq_128,
8609 int_x86_avx2_pbroadcastq_256>;
8611 let Predicates = [HasAVX2] in {
8612 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8613 (VPBROADCASTBrm addr:$src)>;
8614 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8615 (VPBROADCASTBYrm addr:$src)>;
8616 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8617 (VPBROADCASTWrm addr:$src)>;
8618 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8619 (VPBROADCASTWYrm addr:$src)>;
8620 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8621 (VPBROADCASTDrm addr:$src)>;
8622 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8623 (VPBROADCASTDYrm addr:$src)>;
8624 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8625 (VPBROADCASTQrm addr:$src)>;
8626 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8627 (VPBROADCASTQYrm addr:$src)>;
8629 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8630 (VPBROADCASTBrr VR128:$src)>;
8631 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8632 (VPBROADCASTBYrr VR128:$src)>;
8633 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8634 (VPBROADCASTWrr VR128:$src)>;
8635 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8636 (VPBROADCASTWYrr VR128:$src)>;
8637 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8638 (VPBROADCASTDrr VR128:$src)>;
8639 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8640 (VPBROADCASTDYrr VR128:$src)>;
8641 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8642 (VPBROADCASTQrr VR128:$src)>;
8643 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8644 (VPBROADCASTQYrr VR128:$src)>;
8645 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8646 (VBROADCASTSSrr VR128:$src)>;
8647 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8648 (VBROADCASTSSYrr VR128:$src)>;
8649 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8650 (VPBROADCASTQrr VR128:$src)>;
8651 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8652 (VBROADCASTSDYrr VR128:$src)>;
8654 // Provide aliases for broadcast from the same regitser class that
8655 // automatically does the extract.
8656 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8657 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8659 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8660 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8662 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8663 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8665 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8666 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8668 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8669 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8671 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8672 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8675 // Provide fallback in case the load node that is used in the patterns above
8676 // is used by additional users, which prevents the pattern selection.
8677 let AddedComplexity = 20 in {
8678 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8679 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8680 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8681 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8682 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8683 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8685 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8686 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8687 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8688 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8689 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8690 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8692 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8693 (VPBROADCASTBrr (COPY_TO_REGCLASS
8694 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8696 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8697 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8698 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8701 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8702 (VPBROADCASTWrr (COPY_TO_REGCLASS
8703 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8705 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8706 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8707 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8710 // The patterns for VPBROADCASTD are not needed because they would match
8711 // the exact same thing as VBROADCASTSS patterns.
8713 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8714 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8715 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8719 // AVX1 broadcast patterns
8720 let Predicates = [HasAVX1Only] in {
8721 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8722 (VBROADCASTSSYrm addr:$src)>;
8723 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8724 (VBROADCASTSDYrm addr:$src)>;
8725 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8726 (VBROADCASTSSrm addr:$src)>;
8729 let Predicates = [HasAVX] in {
8730 // Provide fallback in case the load node that is used in the patterns above
8731 // is used by additional users, which prevents the pattern selection.
8732 let AddedComplexity = 20 in {
8733 // 128bit broadcasts:
8734 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8735 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8736 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8737 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8738 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8739 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8740 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8741 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8742 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8743 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8745 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8746 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8747 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8748 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8749 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8750 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8751 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8752 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8753 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8754 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8757 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8758 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8761 //===----------------------------------------------------------------------===//
8762 // VPERM - Permute instructions
8765 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8766 ValueType OpVT, X86FoldableSchedWrite Sched> {
8767 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8768 (ins VR256:$src1, VR256:$src2),
8769 !strconcat(OpcodeStr,
8770 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8772 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8773 Sched<[Sched]>, VEX_4V, VEX_L;
8774 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8775 (ins VR256:$src1, i256mem:$src2),
8776 !strconcat(OpcodeStr,
8777 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8779 (OpVT (X86VPermv VR256:$src1,
8780 (bitconvert (mem_frag addr:$src2)))))]>,
8781 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8784 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8785 let ExeDomain = SSEPackedSingle in
8786 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8788 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8789 ValueType OpVT, X86FoldableSchedWrite Sched> {
8790 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8791 (ins VR256:$src1, u8imm:$src2),
8792 !strconcat(OpcodeStr,
8793 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8795 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8796 Sched<[Sched]>, VEX, VEX_L;
8797 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8798 (ins i256mem:$src1, u8imm:$src2),
8799 !strconcat(OpcodeStr,
8800 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8802 (OpVT (X86VPermi (mem_frag addr:$src1),
8803 (i8 imm:$src2))))]>,
8804 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8807 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8808 WriteShuffle256>, VEX_W;
8809 let ExeDomain = SSEPackedDouble in
8810 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8811 WriteFShuffle256>, VEX_W;
8813 //===----------------------------------------------------------------------===//
8814 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8816 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8817 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8818 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8819 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8820 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8822 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8823 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8824 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8825 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8827 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8829 let Predicates = [HasAVX2] in {
8830 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8831 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8832 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8833 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8834 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8835 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8837 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8839 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8840 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8841 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8842 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8843 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8845 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8849 //===----------------------------------------------------------------------===//
8850 // VINSERTI128 - Insert packed integer values
8852 let hasSideEffects = 0 in {
8853 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8854 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8855 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8856 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8858 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8859 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8860 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8861 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8864 let Predicates = [HasAVX2] in {
8865 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8867 (VINSERTI128rr VR256:$src1, VR128:$src2,
8868 (INSERT_get_vinsert128_imm VR256:$ins))>;
8869 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8871 (VINSERTI128rr VR256:$src1, VR128:$src2,
8872 (INSERT_get_vinsert128_imm VR256:$ins))>;
8873 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8875 (VINSERTI128rr VR256:$src1, VR128:$src2,
8876 (INSERT_get_vinsert128_imm VR256:$ins))>;
8877 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8879 (VINSERTI128rr VR256:$src1, VR128:$src2,
8880 (INSERT_get_vinsert128_imm VR256:$ins))>;
8882 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8884 (VINSERTI128rm VR256:$src1, addr:$src2,
8885 (INSERT_get_vinsert128_imm VR256:$ins))>;
8886 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8887 (bc_v4i32 (loadv2i64 addr:$src2)),
8889 (VINSERTI128rm VR256:$src1, addr:$src2,
8890 (INSERT_get_vinsert128_imm VR256:$ins))>;
8891 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8892 (bc_v16i8 (loadv2i64 addr:$src2)),
8894 (VINSERTI128rm VR256:$src1, addr:$src2,
8895 (INSERT_get_vinsert128_imm VR256:$ins))>;
8896 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8897 (bc_v8i16 (loadv2i64 addr:$src2)),
8899 (VINSERTI128rm VR256:$src1, addr:$src2,
8900 (INSERT_get_vinsert128_imm VR256:$ins))>;
8903 //===----------------------------------------------------------------------===//
8904 // VEXTRACTI128 - Extract packed integer values
8906 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8907 (ins VR256:$src1, u8imm:$src2),
8908 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8910 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8911 Sched<[WriteShuffle256]>, VEX, VEX_L;
8912 let hasSideEffects = 0, mayStore = 1 in
8913 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8914 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8915 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8916 Sched<[WriteStore]>, VEX, VEX_L;
8918 let Predicates = [HasAVX2] in {
8919 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8920 (v2i64 (VEXTRACTI128rr
8921 (v4i64 VR256:$src1),
8922 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8923 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8924 (v4i32 (VEXTRACTI128rr
8925 (v8i32 VR256:$src1),
8926 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8927 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8928 (v8i16 (VEXTRACTI128rr
8929 (v16i16 VR256:$src1),
8930 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8931 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8932 (v16i8 (VEXTRACTI128rr
8933 (v32i8 VR256:$src1),
8934 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8936 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8937 (iPTR imm))), addr:$dst),
8938 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8939 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8940 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8941 (iPTR imm))), addr:$dst),
8942 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8943 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8944 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8945 (iPTR imm))), addr:$dst),
8946 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8947 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8948 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8949 (iPTR imm))), addr:$dst),
8950 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8951 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8954 //===----------------------------------------------------------------------===//
8955 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8957 multiclass avx2_pmovmask<string OpcodeStr,
8958 Intrinsic IntLd128, Intrinsic IntLd256,
8959 Intrinsic IntSt128, Intrinsic IntSt256> {
8960 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8961 (ins VR128:$src1, i128mem:$src2),
8962 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8963 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8964 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8965 (ins VR256:$src1, i256mem:$src2),
8966 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8967 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8969 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8970 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8971 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8972 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8973 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8974 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8975 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8976 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8979 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8980 int_x86_avx2_maskload_d,
8981 int_x86_avx2_maskload_d_256,
8982 int_x86_avx2_maskstore_d,
8983 int_x86_avx2_maskstore_d_256>;
8984 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8985 int_x86_avx2_maskload_q,
8986 int_x86_avx2_maskload_q_256,
8987 int_x86_avx2_maskstore_q,
8988 int_x86_avx2_maskstore_q_256>, VEX_W;
8990 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8991 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8993 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8994 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8996 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8997 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8999 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
9000 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
9002 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
9003 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
9005 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
9006 (bc_v8f32 (v8i32 immAllZerosV)))),
9007 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
9009 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
9010 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
9013 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
9014 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
9016 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
9017 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
9019 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
9020 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
9023 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
9024 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
9026 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
9027 (bc_v4f32 (v4i32 immAllZerosV)))),
9028 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
9030 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
9031 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
9034 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
9035 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
9037 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
9038 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
9040 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
9041 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
9044 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
9045 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
9047 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
9048 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
9050 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
9051 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
9053 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
9054 (v4f64 immAllZerosV))),
9055 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
9057 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
9058 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
9061 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
9062 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9064 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
9065 (bc_v4i64 (v8i32 immAllZerosV)))),
9066 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9068 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
9069 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
9072 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
9073 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
9075 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
9076 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
9078 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
9079 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
9081 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
9082 (v2f64 immAllZerosV))),
9083 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
9085 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
9086 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
9089 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
9090 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
9092 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
9093 (bc_v2i64 (v4i32 immAllZerosV)))),
9094 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
9096 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
9097 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
9100 //===----------------------------------------------------------------------===//
9101 // Variable Bit Shifts
9103 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
9104 ValueType vt128, ValueType vt256> {
9105 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
9106 (ins VR128:$src1, VR128:$src2),
9107 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9109 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
9110 VEX_4V, Sched<[WriteVarVecShift]>;
9111 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
9112 (ins VR128:$src1, i128mem:$src2),
9113 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9115 (vt128 (OpNode VR128:$src1,
9116 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
9117 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9118 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
9119 (ins VR256:$src1, VR256:$src2),
9120 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9122 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
9123 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
9124 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
9125 (ins VR256:$src1, i256mem:$src2),
9126 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9128 (vt256 (OpNode VR256:$src1,
9129 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
9130 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9133 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
9134 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
9135 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
9136 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
9137 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
9139 //===----------------------------------------------------------------------===//
9140 // VGATHER - GATHER Operations
9141 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
9142 X86MemOperand memop128, X86MemOperand memop256> {
9143 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
9144 (ins VR128:$src1, memop128:$src2, VR128:$mask),
9145 !strconcat(OpcodeStr,
9146 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9148 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
9149 (ins RC256:$src1, memop256:$src2, RC256:$mask),
9150 !strconcat(OpcodeStr,
9151 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9152 []>, VEX_4VOp3, VEX_L;
9155 let mayLoad = 1, Constraints
9156 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
9158 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
9159 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
9160 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
9161 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
9163 let ExeDomain = SSEPackedDouble in {
9164 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
9165 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
9168 let ExeDomain = SSEPackedSingle in {
9169 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
9170 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;