1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
22 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
23 [SDNPCommutative, SDNPAssociative]>;
24 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
25 [SDNPCommutative, SDNPAssociative]>;
26 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
28 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
30 def X86s2vec : SDNode<"X86ISD::S2VEC",
31 SDTypeProfile<1, 1, []>, []>;
32 def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
33 SDTypeProfile<1, 1, []>, []>;
34 def X86pextrw : SDNode<"X86ISD::PEXTRW",
35 SDTypeProfile<1, 2, []>, []>;
36 def X86pinsrw : SDNode<"X86ISD::PINSRW",
37 SDTypeProfile<1, 3, []>, []>;
39 //===----------------------------------------------------------------------===//
40 // SSE pattern fragments
41 //===----------------------------------------------------------------------===//
43 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
44 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
46 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
47 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
48 def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
49 def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
50 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
51 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
53 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
54 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
55 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
56 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
57 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
58 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
60 def fp32imm0 : PatLeaf<(f32 fpimm), [{
61 return N->isExactlyValue(+0.0);
64 def PSxLDQ_imm : SDNodeXForm<imm, [{
65 // Transformation function: imm >> 3
66 return getI32Imm(N->getValue() >> 3);
69 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
71 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
72 return getI8Imm(X86::getShuffleSHUFImmediate(N));
75 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
77 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
78 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
81 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
83 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
84 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
87 def SSE_splat_mask : PatLeaf<(build_vector), [{
88 return X86::isSplatMask(N);
89 }], SHUFFLE_get_shuf_imm>;
91 def SSE_splat_v2_mask : PatLeaf<(build_vector), [{
92 return X86::isSplatMask(N);
95 def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
96 return X86::isMOVLHPSMask(N);
99 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
100 return X86::isMOVHLPSMask(N);
103 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
104 return X86::isMOVHPMask(N);
107 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
108 return X86::isMOVLPMask(N);
111 def MOVS_shuffle_mask : PatLeaf<(build_vector), [{
112 return X86::isMOVSMask(N);
115 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
116 return X86::isMOVSHDUPMask(N);
119 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
120 return X86::isMOVSLDUPMask(N);
123 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
124 return X86::isUNPCKLMask(N);
127 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
128 return X86::isUNPCKHMask(N);
131 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
132 return X86::isUNPCKL_v_undef_Mask(N);
135 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isPSHUFDMask(N);
137 }], SHUFFLE_get_shuf_imm>;
139 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isPSHUFHWMask(N);
141 }], SHUFFLE_get_pshufhw_imm>;
143 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isPSHUFLWMask(N);
145 }], SHUFFLE_get_pshuflw_imm>;
147 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
148 return X86::isPSHUFDMask(N);
149 }], SHUFFLE_get_shuf_imm>;
151 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
152 return X86::isSHUFPMask(N);
153 }], SHUFFLE_get_shuf_imm>;
155 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
156 return X86::isSHUFPMask(N);
157 }], SHUFFLE_get_shuf_imm>;
159 //===----------------------------------------------------------------------===//
160 // SSE scalar FP Instructions
161 //===----------------------------------------------------------------------===//
163 // Instruction templates
164 // SSI - SSE1 instructions with XS prefix.
165 // SDI - SSE2 instructions with XD prefix.
166 // PSI - SSE1 instructions with TB prefix.
167 // PDI - SSE2 instructions with TB and OpSize prefixes.
168 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
169 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
170 // S3I - SSE3 instructions with TB and OpSize prefixes.
171 // S3SI - SSE3 instructions with XS prefix.
172 // S3DI - SSE3 instructions with XD prefix.
173 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
174 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
175 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
176 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
177 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
178 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
179 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
180 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
181 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
182 : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasSSE1]> {
183 let Pattern = pattern;
185 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
186 : X86Inst<o, F, Imm8, ops, asm>, TB, OpSize, Requires<[HasSSE2]> {
187 let Pattern = pattern;
189 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
190 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
191 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
192 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
193 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
194 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
196 //===----------------------------------------------------------------------===//
197 // Helpers for defining instructions that directly correspond to intrinsics.
198 class SS_Intr<bits<8> o, string asm, Intrinsic IntId>
199 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
200 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
201 class SS_Intm<bits<8> o, string asm, Intrinsic IntId>
202 : SSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
203 [(set VR128:$dst, (v4f32 (IntId (load addr:$src))))]>;
204 class SD_Intr<bits<8> o, string asm, Intrinsic IntId>
205 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
206 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
207 class SD_Intm<bits<8> o, string asm, Intrinsic IntId>
208 : SDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
209 [(set VR128:$dst, (v2f64 (IntId (load addr:$src))))]>;
211 class SS_Intrr<bits<8> o, string asm, Intrinsic IntId>
212 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
213 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
214 class SS_Intrm<bits<8> o, string asm, Intrinsic IntId>
215 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
216 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
217 class SD_Intrr<bits<8> o, string asm, Intrinsic IntId>
218 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
219 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
220 class SD_Intrm<bits<8> o, string asm, Intrinsic IntId>
221 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
222 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
224 class PS_Intr<bits<8> o, string asm, Intrinsic IntId>
225 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
226 [(set VR128:$dst, (IntId VR128:$src))]>;
227 class PS_Intm<bits<8> o, string asm, Intrinsic IntId>
228 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
229 [(set VR128:$dst, (IntId (loadv4f32 addr:$src)))]>;
230 class PD_Intr<bits<8> o, string asm, Intrinsic IntId>
231 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
232 [(set VR128:$dst, (IntId VR128:$src))]>;
233 class PD_Intm<bits<8> o, string asm, Intrinsic IntId>
234 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
235 [(set VR128:$dst, (IntId (loadv2f64 addr:$src)))]>;
237 class PS_Intrr<bits<8> o, string asm, Intrinsic IntId>
238 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
239 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
240 class PS_Intrm<bits<8> o, string asm, Intrinsic IntId>
241 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
242 [(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))]>;
243 class PD_Intrr<bits<8> o, string asm, Intrinsic IntId>
244 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
245 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
246 class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
247 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
248 [(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
250 class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
251 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
252 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
253 class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
254 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
255 [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
256 (loadv4f32 addr:$src2))))]>;
257 class S3_Intrr<bits<8> o, string asm, Intrinsic IntId>
258 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
259 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
260 class S3_Intrm<bits<8> o, string asm, Intrinsic IntId>
261 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
262 [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
263 (loadv2f64 addr:$src2))))]>;
265 // Some 'special' instructions
266 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
267 "#IMPLICIT_DEF $dst",
268 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
269 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
270 "#IMPLICIT_DEF $dst",
271 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
273 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
274 // scheduler into a branch sequence.
275 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
276 def CMOV_FR32 : I<0, Pseudo,
277 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
278 "#CMOV_FR32 PSEUDO!",
279 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
280 def CMOV_FR64 : I<0, Pseudo,
281 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
282 "#CMOV_FR64 PSEUDO!",
283 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
284 def CMOV_V4F32 : I<0, Pseudo,
285 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
286 "#CMOV_V4F32 PSEUDO!",
288 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
289 def CMOV_V2F64 : I<0, Pseudo,
290 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
291 "#CMOV_V2F64 PSEUDO!",
293 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
294 def CMOV_V2I64 : I<0, Pseudo,
295 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
296 "#CMOV_V2I64 PSEUDO!",
298 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
302 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
303 "movss {$src, $dst|$dst, $src}", []>;
304 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
305 "movss {$src, $dst|$dst, $src}",
306 [(set FR32:$dst, (loadf32 addr:$src))]>;
307 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
308 "movsd {$src, $dst|$dst, $src}", []>;
309 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
310 "movsd {$src, $dst|$dst, $src}",
311 [(set FR64:$dst, (loadf64 addr:$src))]>;
313 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
314 "movss {$src, $dst|$dst, $src}",
315 [(store FR32:$src, addr:$dst)]>;
316 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
317 "movsd {$src, $dst|$dst, $src}",
318 [(store FR64:$src, addr:$dst)]>;
320 // Arithmetic instructions
321 let isTwoAddress = 1 in {
322 let isCommutable = 1 in {
323 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
324 "addss {$src2, $dst|$dst, $src2}",
325 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
326 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
327 "addsd {$src2, $dst|$dst, $src2}",
328 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
329 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
330 "mulss {$src2, $dst|$dst, $src2}",
331 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
332 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
333 "mulsd {$src2, $dst|$dst, $src2}",
334 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
337 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
338 "addss {$src2, $dst|$dst, $src2}",
339 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
340 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
341 "addsd {$src2, $dst|$dst, $src2}",
342 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
343 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
344 "mulss {$src2, $dst|$dst, $src2}",
345 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
346 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
347 "mulsd {$src2, $dst|$dst, $src2}",
348 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
350 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
351 "divss {$src2, $dst|$dst, $src2}",
352 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
353 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
354 "divss {$src2, $dst|$dst, $src2}",
355 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
356 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
357 "divsd {$src2, $dst|$dst, $src2}",
358 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
359 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
360 "divsd {$src2, $dst|$dst, $src2}",
361 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
363 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
364 "subss {$src2, $dst|$dst, $src2}",
365 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
366 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
367 "subss {$src2, $dst|$dst, $src2}",
368 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
369 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
370 "subsd {$src2, $dst|$dst, $src2}",
371 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
372 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
373 "subsd {$src2, $dst|$dst, $src2}",
374 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
377 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
378 "sqrtss {$src, $dst|$dst, $src}",
379 [(set FR32:$dst, (fsqrt FR32:$src))]>;
380 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
381 "sqrtss {$src, $dst|$dst, $src}",
382 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
383 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
384 "sqrtsd {$src, $dst|$dst, $src}",
385 [(set FR64:$dst, (fsqrt FR64:$src))]>;
386 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
387 "sqrtsd {$src, $dst|$dst, $src}",
388 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
390 def RSQRTSSr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
391 "rsqrtss {$src, $dst|$dst, $src}", []>;
392 def RSQRTSSm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
393 "rsqrtss {$src, $dst|$dst, $src}", []>;
394 def RCPSSr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
395 "rcpss {$src, $dst|$dst, $src}", []>;
396 def RCPSSm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
397 "rcpss {$src, $dst|$dst, $src}", []>;
399 let isTwoAddress = 1 in {
400 def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
401 "maxss {$src2, $dst|$dst, $src2}", []>;
402 def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
403 "maxss {$src2, $dst|$dst, $src2}", []>;
404 def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
405 "maxsd {$src2, $dst|$dst, $src2}", []>;
406 def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
407 "maxsd {$src2, $dst|$dst, $src2}", []>;
408 def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
409 "minss {$src2, $dst|$dst, $src2}", []>;
410 def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
411 "minss {$src2, $dst|$dst, $src2}", []>;
412 def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
413 "minsd {$src2, $dst|$dst, $src2}", []>;
414 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
415 "minsd {$src2, $dst|$dst, $src2}", []>;
418 // Aliases to match intrinsics which expect XMM operand(s).
419 let isTwoAddress = 1 in {
420 let isCommutable = 1 in {
421 def Int_ADDSSrr : SS_Intrr<0x58, "addss {$src2, $dst|$dst, $src2}",
423 def Int_ADDSDrr : SD_Intrr<0x58, "addsd {$src2, $dst|$dst, $src2}",
424 int_x86_sse2_add_sd>;
425 def Int_MULSSrr : SS_Intrr<0x59, "mulss {$src2, $dst|$dst, $src2}",
427 def Int_MULSDrr : SD_Intrr<0x59, "mulsd {$src2, $dst|$dst, $src2}",
428 int_x86_sse2_mul_sd>;
431 def Int_ADDSSrm : SS_Intrm<0x58, "addss {$src2, $dst|$dst, $src2}",
433 def Int_ADDSDrm : SD_Intrm<0x58, "addsd {$src2, $dst|$dst, $src2}",
434 int_x86_sse2_add_sd>;
435 def Int_MULSSrm : SS_Intrm<0x59, "mulss {$src2, $dst|$dst, $src2}",
437 def Int_MULSDrm : SD_Intrm<0x59, "mulsd {$src2, $dst|$dst, $src2}",
438 int_x86_sse2_mul_sd>;
440 def Int_DIVSSrr : SS_Intrr<0x5E, "divss {$src2, $dst|$dst, $src2}",
442 def Int_DIVSSrm : SS_Intrm<0x5E, "divss {$src2, $dst|$dst, $src2}",
444 def Int_DIVSDrr : SD_Intrr<0x5E, "divsd {$src2, $dst|$dst, $src2}",
445 int_x86_sse2_div_sd>;
446 def Int_DIVSDrm : SD_Intrm<0x5E, "divsd {$src2, $dst|$dst, $src2}",
447 int_x86_sse2_div_sd>;
449 def Int_SUBSSrr : SS_Intrr<0x5C, "subss {$src2, $dst|$dst, $src2}",
451 def Int_SUBSSrm : SS_Intrm<0x5C, "subss {$src2, $dst|$dst, $src2}",
453 def Int_SUBSDrr : SD_Intrr<0x5C, "subsd {$src2, $dst|$dst, $src2}",
454 int_x86_sse2_sub_sd>;
455 def Int_SUBSDrm : SD_Intrm<0x5C, "subsd {$src2, $dst|$dst, $src2}",
456 int_x86_sse2_sub_sd>;
459 def Int_SQRTSSr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}",
460 int_x86_sse_sqrt_ss>;
461 def Int_SQRTSSm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}",
462 int_x86_sse_sqrt_ss>;
463 def Int_SQRTSDr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}",
464 int_x86_sse2_sqrt_sd>;
465 def Int_SQRTSDm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}",
466 int_x86_sse2_sqrt_sd>;
468 def Int_RSQRTSSr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}",
469 int_x86_sse_rsqrt_ss>;
470 def Int_RSQRTSSm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}",
471 int_x86_sse_rsqrt_ss>;
472 def Int_RCPSSr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}",
474 def Int_RCPSSm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}",
477 let isTwoAddress = 1 in {
478 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}",
480 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}",
482 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
483 int_x86_sse2_max_sd>;
484 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
485 int_x86_sse2_max_sd>;
486 def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}",
488 def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}",
490 def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}",
491 int_x86_sse2_min_sd>;
492 def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}",
493 int_x86_sse2_min_sd>;
496 // Conversion instructions
497 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
498 "cvttss2si {$src, $dst|$dst, $src}",
499 [(set R32:$dst, (fp_to_sint FR32:$src))]>;
500 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
501 "cvttss2si {$src, $dst|$dst, $src}",
502 [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
503 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
504 "cvttsd2si {$src, $dst|$dst, $src}",
505 [(set R32:$dst, (fp_to_sint FR64:$src))]>;
506 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
507 "cvttsd2si {$src, $dst|$dst, $src}",
508 [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
509 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
510 "cvtsd2ss {$src, $dst|$dst, $src}",
511 [(set FR32:$dst, (fround FR64:$src))]>;
512 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
513 "cvtsd2ss {$src, $dst|$dst, $src}",
514 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
515 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
516 "cvtsi2ss {$src, $dst|$dst, $src}",
517 [(set FR32:$dst, (sint_to_fp R32:$src))]>;
518 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
519 "cvtsi2ss {$src, $dst|$dst, $src}",
520 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
521 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
522 "cvtsi2sd {$src, $dst|$dst, $src}",
523 [(set FR64:$dst, (sint_to_fp R32:$src))]>;
524 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
525 "cvtsi2sd {$src, $dst|$dst, $src}",
526 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
528 // SSE2 instructions with XS prefix
529 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
530 "cvtss2sd {$src, $dst|$dst, $src}",
531 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
533 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
534 "cvtss2sd {$src, $dst|$dst, $src}",
535 [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
538 // Match intrinsics which expect XMM operand(s).
539 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
540 "cvtss2si {$src, $dst|$dst, $src}",
541 [(set R32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
542 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
543 "cvtss2si {$src, $dst|$dst, $src}",
544 [(set R32:$dst, (int_x86_sse_cvtss2si
545 (loadv4f32 addr:$src)))]>;
546 def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
547 "cvtsd2si {$src, $dst|$dst, $src}",
548 [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
549 def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
550 "cvtsd2si {$src, $dst|$dst, $src}",
551 [(set R32:$dst, (int_x86_sse2_cvtsd2si
552 (loadv2f64 addr:$src)))]>;
554 // Aliases for intrinsics
555 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
556 "cvttss2si {$src, $dst|$dst, $src}",
557 [(set R32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
558 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
559 "cvttss2si {$src, $dst|$dst, $src}",
560 [(set R32:$dst, (int_x86_sse_cvttss2si
561 (loadv4f32 addr:$src)))]>;
562 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
563 "cvttsd2si {$src, $dst|$dst, $src}",
564 [(set R32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
565 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
566 "cvttsd2si {$src, $dst|$dst, $src}",
567 [(set R32:$dst, (int_x86_sse2_cvttsd2si
568 (loadv2f64 addr:$src)))]>;
570 let isTwoAddress = 1 in {
571 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
572 (ops VR128:$dst, VR128:$src1, R32:$src2),
573 "cvtsi2ss {$src2, $dst|$dst, $src2}",
574 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
576 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
577 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
578 "cvtsi2ss {$src2, $dst|$dst, $src2}",
579 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
580 (loadi32 addr:$src2)))]>;
583 // Comparison instructions
584 let isTwoAddress = 1 in {
585 def CMPSSrr : SSI<0xC2, MRMSrcReg,
586 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
587 "cmp${cc}ss {$src, $dst|$dst, $src}",
589 def CMPSSrm : SSI<0xC2, MRMSrcMem,
590 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
591 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
592 def CMPSDrr : SDI<0xC2, MRMSrcReg,
593 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
594 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
595 def CMPSDrm : SDI<0xC2, MRMSrcMem,
596 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
597 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
600 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
601 "ucomiss {$src2, $src1|$src1, $src2}",
602 [(X86cmp FR32:$src1, FR32:$src2)]>;
603 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
604 "ucomiss {$src2, $src1|$src1, $src2}",
605 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
606 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
607 "ucomisd {$src2, $src1|$src1, $src2}",
608 [(X86cmp FR64:$src1, FR64:$src2)]>;
609 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
610 "ucomisd {$src2, $src1|$src1, $src2}",
611 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
613 // Aliases to match intrinsics which expect XMM operand(s).
614 let isTwoAddress = 1 in {
615 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
616 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
617 "cmp${cc}ss {$src, $dst|$dst, $src}",
618 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
619 VR128:$src, imm:$cc))]>;
620 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
621 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
622 "cmp${cc}ss {$src, $dst|$dst, $src}",
623 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
624 (load addr:$src), imm:$cc))]>;
625 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
626 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
627 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
628 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
629 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
630 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
633 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
634 "ucomiss {$src2, $src1|$src1, $src2}",
635 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
636 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
637 "ucomiss {$src2, $src1|$src1, $src2}",
638 [(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
639 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
640 "ucomisd {$src2, $src1|$src1, $src2}",
641 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
642 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
643 "ucomisd {$src2, $src1|$src1, $src2}",
644 [(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
646 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
647 "comiss {$src2, $src1|$src1, $src2}",
648 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
649 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
650 "comiss {$src2, $src1|$src1, $src2}",
651 [(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
652 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
653 "comisd {$src2, $src1|$src1, $src2}",
654 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
655 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
656 "comisd {$src2, $src1|$src1, $src2}",
657 [(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
659 // Aliases of packed instructions for scalar use. These all have names that
662 // Alias instructions that map fld0 to pxor for sse.
663 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
664 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
665 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
666 Requires<[HasSSE1]>, TB, OpSize;
667 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
668 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
669 Requires<[HasSSE2]>, TB, OpSize;
671 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
672 // Upper bits are disregarded.
673 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
674 "movaps {$src, $dst|$dst, $src}", []>;
675 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
676 "movapd {$src, $dst|$dst, $src}", []>;
678 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
679 // Upper bits are disregarded.
680 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
681 "movaps {$src, $dst|$dst, $src}",
682 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
683 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
684 "movapd {$src, $dst|$dst, $src}",
685 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
687 // Alias bitwise logical operations using SSE logical ops on packed FP values.
688 let isTwoAddress = 1 in {
689 let isCommutable = 1 in {
690 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
691 "andps {$src2, $dst|$dst, $src2}",
692 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
693 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
694 "andpd {$src2, $dst|$dst, $src2}",
695 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
696 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
697 "orps {$src2, $dst|$dst, $src2}", []>;
698 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
699 "orpd {$src2, $dst|$dst, $src2}", []>;
700 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
701 "xorps {$src2, $dst|$dst, $src2}",
702 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
703 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
704 "xorpd {$src2, $dst|$dst, $src2}",
705 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
707 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
708 "andps {$src2, $dst|$dst, $src2}",
709 [(set FR32:$dst, (X86fand FR32:$src1,
710 (X86loadpf32 addr:$src2)))]>;
711 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
712 "andpd {$src2, $dst|$dst, $src2}",
713 [(set FR64:$dst, (X86fand FR64:$src1,
714 (X86loadpf64 addr:$src2)))]>;
715 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
716 "orps {$src2, $dst|$dst, $src2}", []>;
717 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
718 "orpd {$src2, $dst|$dst, $src2}", []>;
719 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
720 "xorps {$src2, $dst|$dst, $src2}",
721 [(set FR32:$dst, (X86fxor FR32:$src1,
722 (X86loadpf32 addr:$src2)))]>;
723 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
724 "xorpd {$src2, $dst|$dst, $src2}",
725 [(set FR64:$dst, (X86fxor FR64:$src1,
726 (X86loadpf64 addr:$src2)))]>;
728 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
729 "andnps {$src2, $dst|$dst, $src2}", []>;
730 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
731 "andnps {$src2, $dst|$dst, $src2}", []>;
732 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
733 "andnpd {$src2, $dst|$dst, $src2}", []>;
734 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
735 "andnpd {$src2, $dst|$dst, $src2}", []>;
738 //===----------------------------------------------------------------------===//
739 // SSE packed FP Instructions
740 //===----------------------------------------------------------------------===//
742 // Some 'special' instructions
743 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
744 "#IMPLICIT_DEF $dst",
745 [(set VR128:$dst, (v4f32 (undef)))]>,
749 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
750 "movaps {$src, $dst|$dst, $src}", []>;
751 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
752 "movaps {$src, $dst|$dst, $src}",
753 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
754 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
755 "movapd {$src, $dst|$dst, $src}", []>;
756 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
757 "movapd {$src, $dst|$dst, $src}",
758 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
760 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
761 "movaps {$src, $dst|$dst, $src}",
762 [(store (v4f32 VR128:$src), addr:$dst)]>;
763 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
764 "movapd {$src, $dst|$dst, $src}",
765 [(store (v2f64 VR128:$src), addr:$dst)]>;
767 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
768 "movups {$src, $dst|$dst, $src}", []>;
769 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
770 "movups {$src, $dst|$dst, $src}",
771 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
772 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
773 "movups {$src, $dst|$dst, $src}",
774 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
775 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
776 "movupd {$src, $dst|$dst, $src}", []>;
777 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
778 "movupd {$src, $dst|$dst, $src}",
779 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
780 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
781 "movupd {$src, $dst|$dst, $src}",
782 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
784 let isTwoAddress = 1 in {
785 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
786 "movlps {$src2, $dst|$dst, $src2}",
788 (v4f32 (vector_shuffle VR128:$src1,
789 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
790 MOVLP_shuffle_mask)))]>;
791 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
792 "movlpd {$src2, $dst|$dst, $src2}",
794 (v2f64 (vector_shuffle VR128:$src1,
795 (scalar_to_vector (loadf64 addr:$src2)),
796 MOVLP_shuffle_mask)))]>;
797 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
798 "movhps {$src2, $dst|$dst, $src2}",
800 (v4f32 (vector_shuffle VR128:$src1,
801 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
802 MOVHP_shuffle_mask)))]>;
803 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
804 "movhpd {$src2, $dst|$dst, $src2}",
806 (v2f64 (vector_shuffle VR128:$src1,
807 (scalar_to_vector (loadf64 addr:$src2)),
808 MOVHP_shuffle_mask)))]>;
811 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
812 "movlps {$src, $dst|$dst, $src}",
813 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
814 (i32 0))), addr:$dst)]>;
815 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
816 "movlpd {$src, $dst|$dst, $src}",
817 [(store (f64 (vector_extract (v2f64 VR128:$src),
818 (i32 0))), addr:$dst)]>;
820 // v2f64 extract element 1 is always custom lowered to unpack high to low
821 // and extract element 0 so the non-store version isn't too horrible.
822 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
823 "movhps {$src, $dst|$dst, $src}",
824 [(store (f64 (vector_extract
825 (v2f64 (vector_shuffle
826 (bc_v2f64 (v4f32 VR128:$src)), (undef),
827 UNPCKH_shuffle_mask)), (i32 0))),
829 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
830 "movhpd {$src, $dst|$dst, $src}",
831 [(store (f64 (vector_extract
832 (v2f64 (vector_shuffle VR128:$src, (undef),
833 UNPCKH_shuffle_mask)), (i32 0))),
836 let isTwoAddress = 1 in {
837 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
838 "movlhps {$src2, $dst|$dst, $src2}",
840 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
841 MOVLHPS_shuffle_mask)))]>;
843 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
844 "movhlps {$src2, $dst|$dst, $src2}",
846 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
847 MOVHLPS_shuffle_mask)))]>;
850 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
851 "movshdup {$src, $dst|$dst, $src}",
852 [(set VR128:$dst, (v4f32 (vector_shuffle
854 MOVSHDUP_shuffle_mask)))]>;
855 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
856 "movshdup {$src, $dst|$dst, $src}",
857 [(set VR128:$dst, (v4f32 (vector_shuffle
858 (loadv4f32 addr:$src), (undef),
859 MOVSHDUP_shuffle_mask)))]>;
861 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
862 "movsldup {$src, $dst|$dst, $src}",
863 [(set VR128:$dst, (v4f32 (vector_shuffle
865 MOVSLDUP_shuffle_mask)))]>;
866 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
867 "movsldup {$src, $dst|$dst, $src}",
868 [(set VR128:$dst, (v4f32 (vector_shuffle
869 (loadv4f32 addr:$src), (undef),
870 MOVSLDUP_shuffle_mask)))]>;
872 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
873 "movddup {$src, $dst|$dst, $src}",
874 [(set VR128:$dst, (v2f64 (vector_shuffle
876 SSE_splat_v2_mask)))]>;
877 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
878 "movddup {$src, $dst|$dst, $src}",
879 [(set VR128:$dst, (v2f64 (vector_shuffle
880 (scalar_to_vector (loadf64 addr:$src)),
882 SSE_splat_v2_mask)))]>;
884 // SSE2 instructions without OpSize prefix
885 def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
886 "cvtdq2ps {$src, $dst|$dst, $src}",
887 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
888 TB, Requires<[HasSSE2]>;
889 def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
890 "cvtdq2ps {$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
892 (bc_v4i32 (loadv2i64 addr:$src))))]>,
893 TB, Requires<[HasSSE2]>;
895 // SSE2 instructions with XS prefix
896 def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
897 "cvtdq2pd {$src, $dst|$dst, $src}",
898 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
899 XS, Requires<[HasSSE2]>;
900 def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
901 "cvtdq2pd {$src, $dst|$dst, $src}",
902 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
903 (bc_v4i32 (loadv2i64 addr:$src))))]>,
904 XS, Requires<[HasSSE2]>;
906 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
907 "cvtps2dq {$src, $dst|$dst, $src}",
908 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
909 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
910 "cvtps2dq {$src, $dst|$dst, $src}",
911 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
912 (loadv4f32 addr:$src)))]>;
913 // SSE2 packed instructions with XS prefix
914 def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
915 "cvttps2dq {$src, $dst|$dst, $src}",
916 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
917 XS, Requires<[HasSSE2]>;
918 def CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
919 "cvttps2dq {$src, $dst|$dst, $src}",
920 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
921 (loadv4f32 addr:$src)))]>,
922 XS, Requires<[HasSSE2]>;
924 // SSE2 packed instructions with XD prefix
925 def CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
926 "cvtpd2dq {$src, $dst|$dst, $src}",
927 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
928 XD, Requires<[HasSSE2]>;
929 def CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
930 "cvtpd2dq {$src, $dst|$dst, $src}",
931 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
932 (loadv2f64 addr:$src)))]>,
933 XD, Requires<[HasSSE2]>;
934 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
935 "cvttpd2dq {$src, $dst|$dst, $src}",
936 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
937 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
938 "cvttpd2dq {$src, $dst|$dst, $src}",
939 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
940 (loadv2f64 addr:$src)))]>;
942 // SSE2 instructions without OpSize prefix
943 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
944 "cvtps2pd {$src, $dst|$dst, $src}",
945 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
946 TB, Requires<[HasSSE2]>;
947 def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
948 "cvtps2pd {$src, $dst|$dst, $src}",
949 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
950 (loadv4f32 addr:$src)))]>,
951 TB, Requires<[HasSSE2]>;
953 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
954 "cvtpd2ps {$src, $dst|$dst, $src}",
955 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
956 def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
957 "cvtpd2ps {$src, $dst|$dst, $src}",
958 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
959 (loadv2f64 addr:$src)))]>;
961 // Match intrinsics which expect XMM operand(s).
962 // Aliases for intrinsics
963 let isTwoAddress = 1 in {
964 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
965 (ops VR128:$dst, VR128:$src1, R32:$src2),
966 "cvtsi2sd {$src2, $dst|$dst, $src2}",
967 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
969 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
970 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
971 "cvtsi2sd {$src2, $dst|$dst, $src2}",
972 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
973 (loadi32 addr:$src2)))]>;
974 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
975 (ops VR128:$dst, VR128:$src1, VR128:$src2),
976 "cvtsd2ss {$src2, $dst|$dst, $src2}",
977 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
979 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
980 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
981 "cvtsd2ss {$src2, $dst|$dst, $src2}",
982 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
983 (loadv2f64 addr:$src2)))]>;
984 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
985 (ops VR128:$dst, VR128:$src1, VR128:$src2),
986 "cvtss2sd {$src2, $dst|$dst, $src2}",
987 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
990 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
991 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
992 "cvtss2sd {$src2, $dst|$dst, $src2}",
993 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
994 (loadv4f32 addr:$src2)))]>, XS,
999 let isTwoAddress = 1 in {
1000 let isCommutable = 1 in {
1001 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1002 "addps {$src2, $dst|$dst, $src2}",
1003 [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
1004 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1005 "addpd {$src2, $dst|$dst, $src2}",
1006 [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
1007 def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1008 "mulps {$src2, $dst|$dst, $src2}",
1009 [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
1010 def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1011 "mulpd {$src2, $dst|$dst, $src2}",
1012 [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
1015 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1016 "addps {$src2, $dst|$dst, $src2}",
1017 [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
1018 (load addr:$src2))))]>;
1019 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1020 "addpd {$src2, $dst|$dst, $src2}",
1021 [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
1022 (load addr:$src2))))]>;
1023 def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1024 "mulps {$src2, $dst|$dst, $src2}",
1025 [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
1026 (load addr:$src2))))]>;
1027 def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1028 "mulpd {$src2, $dst|$dst, $src2}",
1029 [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
1030 (load addr:$src2))))]>;
1032 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1033 "divps {$src2, $dst|$dst, $src2}",
1034 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
1035 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1036 "divps {$src2, $dst|$dst, $src2}",
1037 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
1038 (load addr:$src2))))]>;
1039 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1040 "divpd {$src2, $dst|$dst, $src2}",
1041 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
1042 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1043 "divpd {$src2, $dst|$dst, $src2}",
1044 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
1045 (load addr:$src2))))]>;
1047 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1048 "subps {$src2, $dst|$dst, $src2}",
1049 [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
1050 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1051 "subps {$src2, $dst|$dst, $src2}",
1052 [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
1053 (load addr:$src2))))]>;
1054 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1055 "subpd {$src2, $dst|$dst, $src2}",
1056 [(set VR128:$dst, (v2f64 (fsub VR128:$src1, VR128:$src2)))]>;
1057 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1058 "subpd {$src2, $dst|$dst, $src2}",
1059 [(set VR128:$dst, (v2f64 (fsub VR128:$src1,
1060 (load addr:$src2))))]>;
1062 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
1063 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1064 "addsubps {$src2, $dst|$dst, $src2}",
1065 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1067 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
1068 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1069 "addsubps {$src2, $dst|$dst, $src2}",
1070 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1071 (loadv4f32 addr:$src2)))]>;
1072 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
1073 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1074 "addsubpd {$src2, $dst|$dst, $src2}",
1075 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1077 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
1078 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1079 "addsubpd {$src2, $dst|$dst, $src2}",
1080 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1081 (loadv2f64 addr:$src2)))]>;
1084 def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
1085 int_x86_sse_sqrt_ps>;
1086 def SQRTPSm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}",
1087 int_x86_sse_sqrt_ps>;
1088 def SQRTPDr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1089 int_x86_sse2_sqrt_pd>;
1090 def SQRTPDm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1091 int_x86_sse2_sqrt_pd>;
1093 def RSQRTPSr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1094 int_x86_sse_rsqrt_ps>;
1095 def RSQRTPSm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1096 int_x86_sse_rsqrt_ps>;
1097 def RCPPSr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}",
1098 int_x86_sse_rcp_ps>;
1099 def RCPPSm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}",
1100 int_x86_sse_rcp_ps>;
1102 let isTwoAddress = 1 in {
1103 def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1104 int_x86_sse_max_ps>;
1105 def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1106 int_x86_sse_max_ps>;
1107 def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1108 int_x86_sse2_max_pd>;
1109 def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1110 int_x86_sse2_max_pd>;
1111 def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}",
1112 int_x86_sse_min_ps>;
1113 def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}",
1114 int_x86_sse_min_ps>;
1115 def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1116 int_x86_sse2_min_pd>;
1117 def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1118 int_x86_sse2_min_pd>;
1122 let isTwoAddress = 1 in {
1123 let isCommutable = 1 in {
1124 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1125 "andps {$src2, $dst|$dst, $src2}",
1126 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1127 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1128 "andpd {$src2, $dst|$dst, $src2}",
1130 (and (bc_v2i64 (v2f64 VR128:$src1)),
1131 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1132 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1133 "orps {$src2, $dst|$dst, $src2}",
1134 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1135 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1136 "orpd {$src2, $dst|$dst, $src2}",
1138 (or (bc_v2i64 (v2f64 VR128:$src1)),
1139 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1140 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1141 "xorps {$src2, $dst|$dst, $src2}",
1142 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1143 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1144 "xorpd {$src2, $dst|$dst, $src2}",
1146 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1147 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1149 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1150 "andps {$src2, $dst|$dst, $src2}",
1151 [(set VR128:$dst, (and VR128:$src1,
1152 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1153 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1154 "andpd {$src2, $dst|$dst, $src2}",
1156 (and (bc_v2i64 (v2f64 VR128:$src1)),
1157 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1158 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1159 "orps {$src2, $dst|$dst, $src2}",
1160 [(set VR128:$dst, (or VR128:$src1,
1161 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1162 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1163 "orpd {$src2, $dst|$dst, $src2}",
1165 (or (bc_v2i64 (v2f64 VR128:$src1)),
1166 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1167 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1168 "xorps {$src2, $dst|$dst, $src2}",
1169 [(set VR128:$dst, (xor VR128:$src1,
1170 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1171 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1172 "xorpd {$src2, $dst|$dst, $src2}",
1174 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1175 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1176 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1177 "andnps {$src2, $dst|$dst, $src2}",
1178 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1179 (bc_v2i64 (v4i32 immAllOnesV))),
1181 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1182 "andnps {$src2, $dst|$dst, $src2}",
1183 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1184 (bc_v2i64 (v4i32 immAllOnesV))),
1185 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1186 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1187 "andnpd {$src2, $dst|$dst, $src2}",
1189 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1190 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1191 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1192 "andnpd {$src2, $dst|$dst, $src2}",
1194 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1195 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1198 let isTwoAddress = 1 in {
1199 def CMPPSrr : PSIi8<0xC2, MRMSrcReg,
1200 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1201 "cmp${cc}ps {$src, $dst|$dst, $src}",
1202 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1203 VR128:$src, imm:$cc))]>;
1204 def CMPPSrm : PSIi8<0xC2, MRMSrcMem,
1205 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1206 "cmp${cc}ps {$src, $dst|$dst, $src}",
1207 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1208 (load addr:$src), imm:$cc))]>;
1209 def CMPPDrr : PDIi8<0xC2, MRMSrcReg,
1210 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1211 "cmp${cc}pd {$src, $dst|$dst, $src}",
1212 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1213 VR128:$src, imm:$cc))]>;
1214 def CMPPDrm : PDIi8<0xC2, MRMSrcMem,
1215 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1216 "cmp${cc}pd {$src, $dst|$dst, $src}",
1217 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1218 (load addr:$src), imm:$cc))]>;
1221 // Shuffle and unpack instructions
1222 let isTwoAddress = 1 in {
1223 def SHUFPSrr : PSIi8<0xC6, MRMSrcReg,
1224 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1225 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1226 [(set VR128:$dst, (v4f32 (vector_shuffle
1227 VR128:$src1, VR128:$src2,
1228 SHUFP_shuffle_mask:$src3)))]>;
1229 def SHUFPSrm : PSIi8<0xC6, MRMSrcMem,
1230 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1231 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1232 [(set VR128:$dst, (v4f32 (vector_shuffle
1233 VR128:$src1, (load addr:$src2),
1234 SHUFP_shuffle_mask:$src3)))]>;
1235 def SHUFPDrr : PDIi8<0xC6, MRMSrcReg,
1236 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1237 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1238 [(set VR128:$dst, (v2f64 (vector_shuffle
1239 VR128:$src1, VR128:$src2,
1240 SHUFP_shuffle_mask:$src3)))]>;
1241 def SHUFPDrm : PDIi8<0xC6, MRMSrcMem,
1242 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1243 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1244 [(set VR128:$dst, (v2f64 (vector_shuffle
1245 VR128:$src1, (load addr:$src2),
1246 SHUFP_shuffle_mask:$src3)))]>;
1248 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1249 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1250 "unpckhps {$src2, $dst|$dst, $src2}",
1251 [(set VR128:$dst, (v4f32 (vector_shuffle
1252 VR128:$src1, VR128:$src2,
1253 UNPCKH_shuffle_mask)))]>;
1254 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1255 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1256 "unpckhps {$src2, $dst|$dst, $src2}",
1257 [(set VR128:$dst, (v4f32 (vector_shuffle
1258 VR128:$src1, (load addr:$src2),
1259 UNPCKH_shuffle_mask)))]>;
1260 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1261 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1262 "unpckhpd {$src2, $dst|$dst, $src2}",
1263 [(set VR128:$dst, (v2f64 (vector_shuffle
1264 VR128:$src1, VR128:$src2,
1265 UNPCKH_shuffle_mask)))]>;
1266 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1267 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1268 "unpckhpd {$src2, $dst|$dst, $src2}",
1269 [(set VR128:$dst, (v2f64 (vector_shuffle
1270 VR128:$src1, (load addr:$src2),
1271 UNPCKH_shuffle_mask)))]>;
1273 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1274 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1275 "unpcklps {$src2, $dst|$dst, $src2}",
1276 [(set VR128:$dst, (v4f32 (vector_shuffle
1277 VR128:$src1, VR128:$src2,
1278 UNPCKL_shuffle_mask)))]>;
1279 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1280 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1281 "unpcklps {$src2, $dst|$dst, $src2}",
1282 [(set VR128:$dst, (v4f32 (vector_shuffle
1283 VR128:$src1, (load addr:$src2),
1284 UNPCKL_shuffle_mask)))]>;
1285 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1286 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1287 "unpcklpd {$src2, $dst|$dst, $src2}",
1288 [(set VR128:$dst, (v2f64 (vector_shuffle
1289 VR128:$src1, VR128:$src2,
1290 UNPCKL_shuffle_mask)))]>;
1291 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1292 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1293 "unpcklpd {$src2, $dst|$dst, $src2}",
1294 [(set VR128:$dst, (v2f64 (vector_shuffle
1295 VR128:$src1, (load addr:$src2),
1296 UNPCKL_shuffle_mask)))]>;
1300 let isTwoAddress = 1 in {
1301 def HADDPSrr : S3D_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1302 int_x86_sse3_hadd_ps>;
1303 def HADDPSrm : S3D_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1304 int_x86_sse3_hadd_ps>;
1305 def HADDPDrr : S3_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1306 int_x86_sse3_hadd_pd>;
1307 def HADDPDrm : S3_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1308 int_x86_sse3_hadd_pd>;
1309 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1310 int_x86_sse3_hsub_ps>;
1311 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1312 int_x86_sse3_hsub_ps>;
1313 def HSUBPDrr : S3_Intrr<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1314 int_x86_sse3_hsub_pd>;
1315 def HSUBPDrm : S3_Intrm<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1316 int_x86_sse3_hsub_pd>;
1319 //===----------------------------------------------------------------------===//
1320 // SSE integer instructions
1321 //===----------------------------------------------------------------------===//
1323 // Move Instructions
1324 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1325 "movdqa {$src, $dst|$dst, $src}", []>;
1326 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1327 "movdqa {$src, $dst|$dst, $src}",
1328 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1329 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1330 "movdqa {$src, $dst|$dst, $src}",
1331 [(store (v2i64 VR128:$src), addr:$dst)]>;
1332 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1333 "movdqu {$src, $dst|$dst, $src}",
1334 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1335 XS, Requires<[HasSSE2]>;
1336 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1337 "movdqu {$src, $dst|$dst, $src}",
1338 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1339 XS, Requires<[HasSSE2]>;
1340 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1341 "lddqu {$src, $dst|$dst, $src}",
1342 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
1344 // 128-bit Integer Arithmetic
1345 let isTwoAddress = 1 in {
1346 let isCommutable = 1 in {
1347 def PADDBrr : PDI<0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1348 "paddb {$src2, $dst|$dst, $src2}",
1349 [(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))]>;
1350 def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1351 "paddw {$src2, $dst|$dst, $src2}",
1352 [(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))]>;
1353 def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1354 "paddd {$src2, $dst|$dst, $src2}",
1355 [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
1357 def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1358 "paddq {$src2, $dst|$dst, $src2}",
1359 [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
1361 def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1362 "paddb {$src2, $dst|$dst, $src2}",
1363 [(set VR128:$dst, (add VR128:$src1,
1364 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1365 def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1366 "paddw {$src2, $dst|$dst, $src2}",
1367 [(set VR128:$dst, (add VR128:$src1,
1368 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1369 def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1370 "paddd {$src2, $dst|$dst, $src2}",
1371 [(set VR128:$dst, (add VR128:$src1,
1372 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1373 def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1374 "paddd {$src2, $dst|$dst, $src2}",
1375 [(set VR128:$dst, (add VR128:$src1,
1376 (loadv2i64 addr:$src2)))]>;
1378 let isCommutable = 1 in {
1379 def PADDSBrr : PDI<0xEC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1380 "paddsb {$src2, $dst|$dst, $src2}",
1381 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1383 def PADDSWrr : PDI<0xED, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1384 "paddsw {$src2, $dst|$dst, $src2}",
1385 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1387 def PADDUSBrr : PDI<0xDC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1388 "paddusb {$src2, $dst|$dst, $src2}",
1389 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1391 def PADDUSWrr : PDI<0xDD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1392 "paddusw {$src2, $dst|$dst, $src2}",
1393 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1396 def PADDSBrm : PDI<0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1397 "paddsb {$src2, $dst|$dst, $src2}",
1398 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1399 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1400 def PADDSWrm : PDI<0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1401 "paddsw {$src2, $dst|$dst, $src2}",
1402 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1403 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1404 def PADDUSBrm : PDI<0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1405 "paddusb {$src2, $dst|$dst, $src2}",
1406 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1407 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1408 def PADDUSWrm : PDI<0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1409 "paddusw {$src2, $dst|$dst, $src2}",
1410 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1411 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1414 def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1415 "psubb {$src2, $dst|$dst, $src2}",
1416 [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
1417 def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1418 "psubw {$src2, $dst|$dst, $src2}",
1419 [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))]>;
1420 def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1421 "psubd {$src2, $dst|$dst, $src2}",
1422 [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
1423 def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1424 "psubq {$src2, $dst|$dst, $src2}",
1425 [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
1427 def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1428 "psubb {$src2, $dst|$dst, $src2}",
1429 [(set VR128:$dst, (sub VR128:$src1,
1430 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1431 def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1432 "psubw {$src2, $dst|$dst, $src2}",
1433 [(set VR128:$dst, (sub VR128:$src1,
1434 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1435 def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1436 "psubd {$src2, $dst|$dst, $src2}",
1437 [(set VR128:$dst, (sub VR128:$src1,
1438 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1439 def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1440 "psubd {$src2, $dst|$dst, $src2}",
1441 [(set VR128:$dst, (sub VR128:$src1,
1442 (loadv2i64 addr:$src2)))]>;
1444 def PSUBSBrr : PDI<0xE8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1445 "psubsb {$src2, $dst|$dst, $src2}",
1446 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1448 def PSUBSWrr : PDI<0xE9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1449 "psubsw {$src2, $dst|$dst, $src2}",
1450 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1452 def PSUBUSBrr : PDI<0xD8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1453 "psubusb {$src2, $dst|$dst, $src2}",
1454 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1456 def PSUBUSWrr : PDI<0xD9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1457 "psubusw {$src2, $dst|$dst, $src2}",
1458 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1461 def PSUBSBrm : PDI<0xE8, MRMSrcMem,
1462 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1463 "psubsb {$src2, $dst|$dst, $src2}",
1464 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1465 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1466 def PSUBSWrm : PDI<0xE9, MRMSrcMem,
1467 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1468 "psubsw {$src2, $dst|$dst, $src2}",
1469 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1470 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1471 def PSUBUSBrm : PDI<0xD8, MRMSrcMem,
1472 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1473 "psubusb {$src2, $dst|$dst, $src2}",
1474 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1475 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1476 def PSUBUSWrm : PDI<0xD9, MRMSrcMem,
1477 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1478 "psubusw {$src2, $dst|$dst, $src2}",
1479 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1480 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1482 let isCommutable = 1 in {
1483 def PMULHUWrr : PDI<0xE4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1484 "pmulhuw {$src2, $dst|$dst, $src2}",
1485 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1487 def PMULHWrr : PDI<0xE5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1488 "pmulhw {$src2, $dst|$dst, $src2}",
1489 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1491 def PMULLWrr : PDI<0xD5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1492 "pmullw {$src2, $dst|$dst, $src2}",
1493 [(set VR128:$dst, (v8i16 (mul VR128:$src1, VR128:$src2)))]>;
1494 def PMULUDQrr : PDI<0xF4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1495 "pmuludq {$src2, $dst|$dst, $src2}",
1496 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1499 def PMULHUWrm : PDI<0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1500 "pmulhuw {$src2, $dst|$dst, $src2}",
1501 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1502 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1503 def PMULHWrm : PDI<0xE5, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1504 "pmulhw {$src2, $dst|$dst, $src2}",
1505 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1506 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1507 def PMULLWrm : PDI<0xD5, MRMSrcMem,
1508 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1509 "pmullw {$src2, $dst|$dst, $src2}",
1510 [(set VR128:$dst, (v8i16 (mul VR128:$src1,
1511 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1512 def PMULUDQrm : PDI<0xF4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1513 "pmuludq {$src2, $dst|$dst, $src2}",
1514 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1515 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1517 let isCommutable = 1 in {
1518 def PMADDWDrr : PDI<0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1519 "pmaddwd {$src2, $dst|$dst, $src2}",
1520 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1523 def PMADDWDrm : PDI<0xF5, MRMSrcMem,
1524 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1525 "pmaddwd {$src2, $dst|$dst, $src2}",
1526 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1527 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1529 let isCommutable = 1 in {
1530 def PAVGBrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1531 "pavgb {$src2, $dst|$dst, $src2}",
1532 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1534 def PAVGWrr : PDI<0xE3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1535 "pavgw {$src2, $dst|$dst, $src2}",
1536 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1539 def PAVGBrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1540 "pavgb {$src2, $dst|$dst, $src2}",
1541 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1542 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1543 def PAVGWrm : PDI<0xE3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1544 "pavgw {$src2, $dst|$dst, $src2}",
1545 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1546 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1548 let isCommutable = 1 in {
1549 def PMAXUBrr : PDI<0xDE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1550 "pmaxub {$src2, $dst|$dst, $src2}",
1551 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1553 def PMAXSWrr : PDI<0xEE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1554 "pmaxsw {$src2, $dst|$dst, $src2}",
1555 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1558 def PMAXUBrm : PDI<0xDE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1559 "pmaxub {$src2, $dst|$dst, $src2}",
1560 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1561 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1562 def PMAXSWrm : PDI<0xEE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1563 "pmaxsw {$src2, $dst|$dst, $src2}",
1564 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1565 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1567 let isCommutable = 1 in {
1568 def PMINUBrr : PDI<0xDA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1569 "pminub {$src2, $dst|$dst, $src2}",
1570 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1572 def PMINSWrr : PDI<0xEA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1573 "pminsw {$src2, $dst|$dst, $src2}",
1574 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1577 def PMINUBrm : PDI<0xDA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1578 "pminub {$src2, $dst|$dst, $src2}",
1579 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1580 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1581 def PMINSWrm : PDI<0xEA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1582 "pminsw {$src2, $dst|$dst, $src2}",
1583 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1584 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1587 let isCommutable = 1 in {
1588 def PSADBWrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1589 "psadbw {$src2, $dst|$dst, $src2}",
1590 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1593 def PSADBWrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1594 "psadbw {$src2, $dst|$dst, $src2}",
1595 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1596 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1599 let isTwoAddress = 1 in {
1600 def PSLLWrr : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1601 "psllw {$src2, $dst|$dst, $src2}",
1602 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1604 def PSLLWrm : PDIi8<0xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1605 "psllw {$src2, $dst|$dst, $src2}",
1606 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1607 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1608 def PSLLWri : PDIi8<0x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1609 "psllw {$src2, $dst|$dst, $src2}",
1610 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1611 (scalar_to_vector (i32 imm:$src2))))]>;
1612 def PSLLDrr : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1613 "pslld {$src2, $dst|$dst, $src2}",
1614 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1616 def PSLLDrm : PDIi8<0xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1617 "pslld {$src2, $dst|$dst, $src2}",
1618 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1619 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1620 def PSLLDri : PDIi8<0x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1621 "pslld {$src2, $dst|$dst, $src2}",
1622 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1623 (scalar_to_vector (i32 imm:$src2))))]>;
1624 def PSLLQrr : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1625 "psllq {$src2, $dst|$dst, $src2}",
1626 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1628 def PSLLQrm : PDIi8<0xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1629 "psllq {$src2, $dst|$dst, $src2}",
1630 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1631 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1632 def PSLLQri : PDIi8<0x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1633 "psllq {$src2, $dst|$dst, $src2}",
1634 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1635 (scalar_to_vector (i32 imm:$src2))))]>;
1636 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1637 "pslldq {$src2, $dst|$dst, $src2}", []>;
1639 def PSRLWrr : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1640 "psrlw {$src2, $dst|$dst, $src2}",
1641 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1643 def PSRLWrm : PDIi8<0xD1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1644 "psrlw {$src2, $dst|$dst, $src2}",
1645 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1646 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1647 def PSRLWri : PDIi8<0x71, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1648 "psrlw {$src2, $dst|$dst, $src2}",
1649 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1650 (scalar_to_vector (i32 imm:$src2))))]>;
1651 def PSRLDrr : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1652 "psrld {$src2, $dst|$dst, $src2}",
1653 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1655 def PSRLDrm : PDIi8<0xD2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1656 "psrld {$src2, $dst|$dst, $src2}",
1657 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1658 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1659 def PSRLDri : PDIi8<0x72, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1660 "psrld {$src2, $dst|$dst, $src2}",
1661 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1662 (scalar_to_vector (i32 imm:$src2))))]>;
1663 def PSRLQrr : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1664 "psrlq {$src2, $dst|$dst, $src2}",
1665 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1667 def PSRLQrm : PDIi8<0xD3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1668 "psrlq {$src2, $dst|$dst, $src2}",
1669 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1670 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1671 def PSRLQri : PDIi8<0x73, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1672 "psrlq {$src2, $dst|$dst, $src2}",
1673 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1674 (scalar_to_vector (i32 imm:$src2))))]>;
1675 def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1676 "psrldq {$src2, $dst|$dst, $src2}", []>;
1678 def PSRAWrr : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1679 "psraw {$src2, $dst|$dst, $src2}",
1680 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1682 def PSRAWrm : PDIi8<0xE1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1683 "psraw {$src2, $dst|$dst, $src2}",
1684 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1685 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1686 def PSRAWri : PDIi8<0x71, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1687 "psraw {$src2, $dst|$dst, $src2}",
1688 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1689 (scalar_to_vector (i32 imm:$src2))))]>;
1690 def PSRADrr : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1691 "psrad {$src2, $dst|$dst, $src2}",
1692 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1694 def PSRADrm : PDIi8<0xE2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1695 "psrad {$src2, $dst|$dst, $src2}",
1696 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1697 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1698 def PSRADri : PDIi8<0x72, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1699 "psrad {$src2, $dst|$dst, $src2}",
1700 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1701 (scalar_to_vector (i32 imm:$src2))))]>;
1705 let isTwoAddress = 1 in {
1706 let isCommutable = 1 in {
1707 def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1708 "pand {$src2, $dst|$dst, $src2}",
1709 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1710 def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1711 "por {$src2, $dst|$dst, $src2}",
1712 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1713 def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1714 "pxor {$src2, $dst|$dst, $src2}",
1715 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1718 def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1719 "pand {$src2, $dst|$dst, $src2}",
1720 [(set VR128:$dst, (v2i64 (and VR128:$src1,
1721 (load addr:$src2))))]>;
1722 def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1723 "por {$src2, $dst|$dst, $src2}",
1724 [(set VR128:$dst, (v2i64 (or VR128:$src1,
1725 (load addr:$src2))))]>;
1726 def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1727 "pxor {$src2, $dst|$dst, $src2}",
1728 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
1729 (load addr:$src2))))]>;
1731 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1732 "pandn {$src2, $dst|$dst, $src2}",
1733 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1736 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1737 "pandn {$src2, $dst|$dst, $src2}",
1738 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1739 (load addr:$src2))))]>;
1742 // SSE2 Integer comparison
1743 let isTwoAddress = 1 in {
1744 def PCMPEQBrr : PDI<0x74, MRMSrcReg,
1745 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1746 "pcmpeqb {$src2, $dst|$dst, $src2}",
1747 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1749 def PCMPEQBrm : PDI<0x74, MRMSrcMem,
1750 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1751 "pcmpeqb {$src2, $dst|$dst, $src2}",
1752 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1753 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1754 def PCMPEQWrr : PDI<0x75, MRMSrcReg,
1755 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1756 "pcmpeqw {$src2, $dst|$dst, $src2}",
1757 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1759 def PCMPEQWrm : PDI<0x75, MRMSrcMem,
1760 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1761 "pcmpeqw {$src2, $dst|$dst, $src2}",
1762 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1763 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1764 def PCMPEQDrr : PDI<0x76, MRMSrcReg,
1765 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1766 "pcmpeqd {$src2, $dst|$dst, $src2}",
1767 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1769 def PCMPEQDrm : PDI<0x76, MRMSrcMem,
1770 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1771 "pcmpeqd {$src2, $dst|$dst, $src2}",
1772 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1773 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1775 def PCMPGTBrr : PDI<0x64, MRMSrcReg,
1776 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1777 "pcmpgtb {$src2, $dst|$dst, $src2}",
1778 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1780 def PCMPGTBrm : PDI<0x64, MRMSrcMem,
1781 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1782 "pcmpgtb {$src2, $dst|$dst, $src2}",
1783 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1784 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1785 def PCMPGTWrr : PDI<0x65, MRMSrcReg,
1786 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1787 "pcmpgtw {$src2, $dst|$dst, $src2}",
1788 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1790 def PCMPGTWrm : PDI<0x65, MRMSrcMem,
1791 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1792 "pcmpgtw {$src2, $dst|$dst, $src2}",
1793 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1794 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1795 def PCMPGTDrr : PDI<0x66, MRMSrcReg,
1796 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1797 "pcmpgtd {$src2, $dst|$dst, $src2}",
1798 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1800 def PCMPGTDrm : PDI<0x66, MRMSrcMem,
1801 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1802 "pcmpgtd {$src2, $dst|$dst, $src2}",
1803 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1804 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1807 // Pack instructions
1808 let isTwoAddress = 1 in {
1809 def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1811 "packsswb {$src2, $dst|$dst, $src2}",
1812 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1815 def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1817 "packsswb {$src2, $dst|$dst, $src2}",
1818 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1820 (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
1821 def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1823 "packssdw {$src2, $dst|$dst, $src2}",
1824 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1827 def PACKSSDWrm : PDI<0x6B, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1829 "packssdw {$src2, $dst|$dst, $src2}",
1830 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1832 (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
1833 def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1835 "packuswb {$src2, $dst|$dst, $src2}",
1836 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1839 def PACKUSWBrm : PDI<0x67, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1841 "packuswb {$src2, $dst|$dst, $src2}",
1842 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1844 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1847 // Shuffle and unpack instructions
1848 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1849 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1850 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1851 [(set VR128:$dst, (v4i32 (vector_shuffle
1852 VR128:$src1, (undef),
1853 PSHUFD_shuffle_mask:$src2)))]>;
1854 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1855 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1856 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1857 [(set VR128:$dst, (v4i32 (vector_shuffle
1858 (bc_v4i32 (loadv2i64 addr:$src1)),
1860 PSHUFD_shuffle_mask:$src2)))]>;
1862 // SSE2 with ImmT == Imm8 and XS prefix.
1863 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1864 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1865 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1866 [(set VR128:$dst, (v8i16 (vector_shuffle
1867 VR128:$src1, (undef),
1868 PSHUFHW_shuffle_mask:$src2)))]>,
1869 XS, Requires<[HasSSE2]>;
1870 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1871 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1872 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1873 [(set VR128:$dst, (v8i16 (vector_shuffle
1874 (bc_v8i16 (loadv2i64 addr:$src1)),
1876 PSHUFHW_shuffle_mask:$src2)))]>,
1877 XS, Requires<[HasSSE2]>;
1879 // SSE2 with ImmT == Imm8 and XD prefix.
1880 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1881 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1882 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1883 [(set VR128:$dst, (v8i16 (vector_shuffle
1884 VR128:$src1, (undef),
1885 PSHUFLW_shuffle_mask:$src2)))]>,
1886 XD, Requires<[HasSSE2]>;
1887 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1888 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1889 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1890 [(set VR128:$dst, (v8i16 (vector_shuffle
1891 (bc_v8i16 (loadv2i64 addr:$src1)),
1893 PSHUFLW_shuffle_mask:$src2)))]>,
1894 XD, Requires<[HasSSE2]>;
1896 let isTwoAddress = 1 in {
1897 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1898 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1899 "punpcklbw {$src2, $dst|$dst, $src2}",
1901 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1902 UNPCKL_shuffle_mask)))]>;
1903 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1904 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1905 "punpcklbw {$src2, $dst|$dst, $src2}",
1907 (v16i8 (vector_shuffle VR128:$src1,
1908 (bc_v16i8 (loadv2i64 addr:$src2)),
1909 UNPCKL_shuffle_mask)))]>;
1910 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1911 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1912 "punpcklwd {$src2, $dst|$dst, $src2}",
1914 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1915 UNPCKL_shuffle_mask)))]>;
1916 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1917 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1918 "punpcklwd {$src2, $dst|$dst, $src2}",
1920 (v8i16 (vector_shuffle VR128:$src1,
1921 (bc_v8i16 (loadv2i64 addr:$src2)),
1922 UNPCKL_shuffle_mask)))]>;
1923 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1924 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1925 "punpckldq {$src2, $dst|$dst, $src2}",
1927 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1928 UNPCKL_shuffle_mask)))]>;
1929 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1930 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1931 "punpckldq {$src2, $dst|$dst, $src2}",
1933 (v4i32 (vector_shuffle VR128:$src1,
1934 (bc_v4i32 (loadv2i64 addr:$src2)),
1935 UNPCKL_shuffle_mask)))]>;
1936 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1937 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1938 "punpcklqdq {$src2, $dst|$dst, $src2}",
1940 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1941 UNPCKL_shuffle_mask)))]>;
1942 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1943 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1944 "punpcklqdq {$src2, $dst|$dst, $src2}",
1946 (v2i64 (vector_shuffle VR128:$src1,
1947 (loadv2i64 addr:$src2),
1948 UNPCKL_shuffle_mask)))]>;
1950 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1951 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1952 "punpckhbw {$src2, $dst|$dst, $src2}",
1954 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1955 UNPCKH_shuffle_mask)))]>;
1956 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1957 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1958 "punpckhbw {$src2, $dst|$dst, $src2}",
1960 (v16i8 (vector_shuffle VR128:$src1,
1961 (bc_v16i8 (loadv2i64 addr:$src2)),
1962 UNPCKH_shuffle_mask)))]>;
1963 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1964 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1965 "punpckhwd {$src2, $dst|$dst, $src2}",
1967 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1968 UNPCKH_shuffle_mask)))]>;
1969 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1970 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1971 "punpckhwd {$src2, $dst|$dst, $src2}",
1973 (v8i16 (vector_shuffle VR128:$src1,
1974 (bc_v8i16 (loadv2i64 addr:$src2)),
1975 UNPCKH_shuffle_mask)))]>;
1976 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1977 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1978 "punpckhdq {$src2, $dst|$dst, $src2}",
1980 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1981 UNPCKH_shuffle_mask)))]>;
1982 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1983 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1984 "punpckhdq {$src2, $dst|$dst, $src2}",
1986 (v4i32 (vector_shuffle VR128:$src1,
1987 (bc_v4i32 (loadv2i64 addr:$src2)),
1988 UNPCKH_shuffle_mask)))]>;
1989 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1990 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1991 "punpckhdq {$src2, $dst|$dst, $src2}",
1993 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1994 UNPCKH_shuffle_mask)))]>;
1995 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1996 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1997 "punpckhqdq {$src2, $dst|$dst, $src2}",
1999 (v2i64 (vector_shuffle VR128:$src1,
2000 (loadv2i64 addr:$src2),
2001 UNPCKH_shuffle_mask)))]>;
2005 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2006 (ops R32:$dst, VR128:$src1, i32i8imm:$src2),
2007 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
2008 [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1),
2009 (i32 imm:$src2)))]>;
2010 def PEXTRWmi : PDIi8<0xC5, MRMSrcMem,
2011 (ops R32:$dst, i128mem:$src1, i32i8imm:$src2),
2012 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
2013 [(set R32:$dst, (X86pextrw
2014 (bc_v8i16 (loadv2i64 addr:$src1)),
2015 (i32 imm:$src2)))]>;
2017 let isTwoAddress = 1 in {
2018 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2019 (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
2020 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2021 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2022 R32:$src2, (i32 imm:$src3))))]>;
2023 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2024 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
2025 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2027 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2028 (i32 (anyext (loadi16 addr:$src2))),
2029 (i32 imm:$src3))))]>;
2032 //===----------------------------------------------------------------------===//
2033 // Miscellaneous Instructions
2034 //===----------------------------------------------------------------------===//
2037 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
2038 "movmskps {$src, $dst|$dst, $src}",
2039 [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
2040 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
2041 "movmskpd {$src, $dst|$dst, $src}",
2042 [(set R32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
2044 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
2045 "pmovmskb {$src, $dst|$dst, $src}",
2046 [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2048 // Conditional store
2049 def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
2050 "maskmovdqu {$mask, $src|$src, $mask}",
2051 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
2054 // Prefetching loads
2055 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
2056 "prefetcht0 $src", []>;
2057 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
2058 "prefetcht1 $src", []>;
2059 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
2060 "prefetcht2 $src", []>;
2061 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
2062 "prefetchtnta $src", []>;
2064 // Non-temporal stores
2065 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2066 "movntps {$src, $dst|$dst, $src}",
2067 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2068 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2069 "movntpd {$src, $dst|$dst, $src}",
2070 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2071 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
2072 "movntdq {$src, $dst|$dst, $src}",
2073 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2074 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
2075 "movnti {$src, $dst|$dst, $src}",
2076 [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>,
2077 TB, Requires<[HasSSE2]>;
2080 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
2081 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
2082 TB, Requires<[HasSSE2]>;
2084 // Load, store, and memory fence
2085 def SFENCE : I<0xAE, MRM7m, (ops),
2086 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
2087 def LFENCE : I<0xAE, MRM5m, (ops),
2088 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2089 def MFENCE : I<0xAE, MRM6m, (ops),
2090 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2093 def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src),
2095 [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
2096 def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
2098 [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
2100 // Thread synchronization
2101 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
2102 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,
2103 TB, Requires<[HasSSE3]>;
2104 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
2105 [(int_x86_sse3_mwait ECX, EAX)]>,
2106 TB, Requires<[HasSSE3]>;
2108 //===----------------------------------------------------------------------===//
2109 // Alias Instructions
2110 //===----------------------------------------------------------------------===//
2112 // Alias instructions that map zero vector to pxor / xorp* for sse.
2113 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2114 def V_SET0_PI : PDI<0xEF, MRMInitReg, (ops VR128:$dst),
2116 [(set VR128:$dst, (v2i64 immAllZerosV))]>;
2117 def V_SET0_PS : PSI<0x57, MRMInitReg, (ops VR128:$dst),
2119 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2120 def V_SET0_PD : PDI<0x57, MRMInitReg, (ops VR128:$dst),
2122 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2124 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
2125 "pcmpeqd $dst, $dst",
2126 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
2128 // FR32 / FR64 to 128-bit vector conversion.
2129 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
2130 "movss {$src, $dst|$dst, $src}",
2132 (v4f32 (scalar_to_vector FR32:$src)))]>;
2133 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2134 "movss {$src, $dst|$dst, $src}",
2136 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
2137 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
2138 "movsd {$src, $dst|$dst, $src}",
2140 (v2f64 (scalar_to_vector FR64:$src)))]>;
2141 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2142 "movsd {$src, $dst|$dst, $src}",
2144 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2146 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
2147 "movd {$src, $dst|$dst, $src}",
2149 (v4i32 (scalar_to_vector R32:$src)))]>;
2150 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2151 "movd {$src, $dst|$dst, $src}",
2153 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2154 // SSE2 instructions with XS prefix
2155 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
2156 "movq {$src, $dst|$dst, $src}",
2158 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
2159 Requires<[HasSSE2]>;
2160 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2161 "movq {$src, $dst|$dst, $src}",
2163 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2164 Requires<[HasSSE2]>;
2165 // FIXME: may not be able to eliminate this movss with coalescing the src and
2166 // dest register classes are different. We really want to write this pattern
2168 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (i32 0))),
2169 // (f32 FR32:$src)>;
2170 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
2171 "movss {$src, $dst|$dst, $src}",
2172 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
2174 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
2175 "movss {$src, $dst|$dst, $src}",
2176 [(store (f32 (vector_extract (v4f32 VR128:$src),
2177 (i32 0))), addr:$dst)]>;
2178 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
2179 "movsd {$src, $dst|$dst, $src}",
2180 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2182 def MOVPDI2DIrr : PDI<0x7E, MRMSrcReg, (ops R32:$dst, VR128:$src),
2183 "movd {$src, $dst|$dst, $src}",
2184 [(set R32:$dst, (vector_extract (v4i32 VR128:$src),
2186 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
2187 "movd {$src, $dst|$dst, $src}",
2188 [(store (i32 (vector_extract (v4i32 VR128:$src),
2189 (i32 0))), addr:$dst)]>;
2191 // Move to lower bits of a VR128, leaving upper bits alone.
2192 // Three operand (but two address) aliases.
2193 let isTwoAddress = 1 in {
2194 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
2195 "movss {$src2, $dst|$dst, $src2}", []>;
2196 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
2197 "movsd {$src2, $dst|$dst, $src2}", []>;
2198 def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2),
2199 "movd {$src2, $dst|$dst, $src2}", []>;
2201 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2202 "movss {$src2, $dst|$dst, $src2}",
2204 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2205 MOVS_shuffle_mask)))]>;
2206 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2207 "movsd {$src2, $dst|$dst, $src2}",
2209 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2210 MOVS_shuffle_mask)))]>;
2213 // Store / copy lower 64-bits of a XMM register.
2214 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
2215 "movq {$src, $dst|$dst, $src}",
2216 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2218 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2219 def MOVLQ128rr : PDI<0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2220 "movq {$src, $dst|$dst, $src}",
2221 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>;
2223 // Move to lower bits of a VR128 and zeroing upper bits.
2224 // Loading from memory automatically zeroing upper bits.
2225 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2226 "movss {$src, $dst|$dst, $src}",
2228 (v4f32 (X86zexts2vec (loadf32 addr:$src))))]>;
2229 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2230 "movsd {$src, $dst|$dst, $src}",
2232 (v2f64 (X86zexts2vec (loadf64 addr:$src))))]>;
2233 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2234 "movd {$src, $dst|$dst, $src}",
2236 (v4i32 (X86zexts2vec (loadi32 addr:$src))))]>;
2237 def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2238 "movq {$src, $dst|$dst, $src}",
2240 (bc_v2i64 (v2f64 (X86zexts2vec
2241 (loadf64 addr:$src)))))]>;
2243 //===----------------------------------------------------------------------===//
2244 // Non-Instruction Patterns
2245 //===----------------------------------------------------------------------===//
2247 // 128-bit vector undef's.
2248 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2249 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2250 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2251 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2252 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2254 // 128-bit vector all zero's.
2255 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0_PI))>, Requires<[HasSSE2]>;
2256 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0_PI))>, Requires<[HasSSE2]>;
2257 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0_PI))>, Requires<[HasSSE2]>;
2259 // 128-bit vector all one's.
2260 def : Pat<(v16i8 immAllOnesV), (v16i8 (V_SETALLONES))>, Requires<[HasSSE2]>;
2261 def : Pat<(v8i16 immAllOnesV), (v8i16 (V_SETALLONES))>, Requires<[HasSSE2]>;
2262 def : Pat<(v4i32 immAllOnesV), (v4i32 (V_SETALLONES))>, Requires<[HasSSE2]>;
2263 def : Pat<(v2i64 immAllOnesV), (v2i64 (V_SETALLONES))>, Requires<[HasSSE2]>;
2264 def : Pat<(v4f32 immAllOnesV), (v4f32 (V_SETALLONES))>, Requires<[HasSSE1]>;
2266 // Store 128-bit integer vector values.
2267 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2268 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2269 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2270 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2271 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2272 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2274 // Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
2276 def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
2277 Requires<[HasSSE2]>;
2278 def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
2279 Requires<[HasSSE2]>;
2282 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
2283 Requires<[HasSSE2]>;
2284 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>,
2285 Requires<[HasSSE2]>;
2286 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>,
2287 Requires<[HasSSE2]>;
2288 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>,
2289 Requires<[HasSSE2]>;
2290 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>,
2291 Requires<[HasSSE2]>;
2292 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2293 Requires<[HasSSE2]>;
2294 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2295 Requires<[HasSSE2]>;
2296 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2297 Requires<[HasSSE2]>;
2298 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>,
2299 Requires<[HasSSE2]>;
2300 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
2301 Requires<[HasSSE2]>;
2302 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2303 Requires<[HasSSE2]>;
2304 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
2305 Requires<[HasSSE2]>;
2306 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2307 Requires<[HasSSE2]>;
2308 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>,
2309 Requires<[HasSSE2]>;
2310 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>,
2311 Requires<[HasSSE2]>;
2312 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2313 Requires<[HasSSE2]>;
2314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
2315 Requires<[HasSSE2]>;
2316 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2317 Requires<[HasSSE2]>;
2318 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>,
2319 Requires<[HasSSE2]>;
2320 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>,
2321 Requires<[HasSSE2]>;
2322 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>,
2323 Requires<[HasSSE2]>;
2324 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
2325 Requires<[HasSSE2]>;
2326 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>,
2327 Requires<[HasSSE2]>;
2328 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>,
2329 Requires<[HasSSE2]>;
2330 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>,
2331 Requires<[HasSSE2]>;
2332 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>,
2333 Requires<[HasSSE2]>;
2334 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>,
2335 Requires<[HasSSE2]>;
2336 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>,
2337 Requires<[HasSSE2]>;
2338 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>,
2339 Requires<[HasSSE2]>;
2340 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>,
2341 Requires<[HasSSE2]>;
2343 // Zeroing a VR128 then do a MOVS* to the lower bits.
2344 def : Pat<(v2f64 (X86zexts2vec FR64:$src)),
2345 (MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>;
2346 def : Pat<(v4f32 (X86zexts2vec FR32:$src)),
2347 (MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>;
2348 def : Pat<(v4i32 (X86zexts2vec R32:$src)),
2349 (MOVLDI2PDIrr (V_SET0_PI), R32:$src)>, Requires<[HasSSE2]>;
2350 def : Pat<(v8i16 (X86zexts2vec R16:$src)),
2351 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr16 R16:$src))>, Requires<[HasSSE2]>;
2352 def : Pat<(v16i8 (X86zexts2vec R8:$src)),
2353 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
2355 // Splat v2f64 / v2i64
2356 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2357 (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
2358 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2359 (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
2362 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2363 (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
2364 Requires<[HasSSE1]>;
2366 // Special unary SHUFPSrr case.
2367 // FIXME: when we want non two-address code, then we should use PSHUFD?
2368 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2369 SHUFP_unary_shuffle_mask:$sm),
2370 (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm))>,
2371 Requires<[HasSSE1]>;
2372 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2373 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
2374 SHUFP_unary_shuffle_mask:$sm),
2375 (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm))>,
2376 Requires<[HasSSE2]>;
2377 // Special binary v4i32 shuffle cases with SHUFPS.
2378 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2379 PSHUFD_binary_shuffle_mask:$sm),
2380 (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
2381 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
2382 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2383 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2384 (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
2385 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
2387 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2388 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2389 UNPCKL_v_undef_shuffle_mask)),
2390 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2391 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2392 UNPCKL_v_undef_shuffle_mask)),
2393 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2394 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2395 UNPCKL_v_undef_shuffle_mask)),
2396 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2397 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2398 UNPCKL_v_undef_shuffle_mask)),
2399 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2401 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2402 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2403 MOVSHDUP_shuffle_mask)),
2404 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2405 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2406 MOVSHDUP_shuffle_mask)),
2407 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2409 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2410 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2411 MOVSLDUP_shuffle_mask)),
2412 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2413 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2414 MOVSLDUP_shuffle_mask)),
2415 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2417 // 128-bit logical shifts
2418 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2419 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2420 Requires<[HasSSE2]>;
2421 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2422 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2423 Requires<[HasSSE2]>;
2425 // Some special case pandn patterns.
2426 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2428 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2429 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2431 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2432 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2434 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2436 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2437 (load addr:$src2))),
2438 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2439 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2440 (load addr:$src2))),
2441 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2442 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2443 (load addr:$src2))),
2444 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;