1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>,
74 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
76 //===----------------------------------------------------------------------===//
77 // SSE Complex Patterns
78 //===----------------------------------------------------------------------===//
80 // These are 'extloads' from a scalar to the low element of a vector, zeroing
81 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
83 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
84 [SDNPHasChain, SDNPMayLoad]>;
85 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
86 [SDNPHasChain, SDNPMayLoad]>;
88 def ssmem : Operand<v4f32> {
89 let PrintMethod = "printf32mem";
90 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
91 let ParserMatchClass = X86MemAsmOperand;
93 def sdmem : Operand<v2f64> {
94 let PrintMethod = "printf64mem";
95 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
96 let ParserMatchClass = X86MemAsmOperand;
99 //===----------------------------------------------------------------------===//
100 // SSE pattern fragments
101 //===----------------------------------------------------------------------===//
103 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
104 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
105 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
106 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
108 // Like 'store', but always requires vector alignment.
109 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
110 (store node:$val, node:$ptr), [{
111 return cast<StoreSDNode>(N)->getAlignment() >= 16;
114 // Like 'load', but always requires vector alignment.
115 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
116 return cast<LoadSDNode>(N)->getAlignment() >= 16;
119 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
120 (f32 (alignedload node:$ptr))>;
121 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
122 (f64 (alignedload node:$ptr))>;
123 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
124 (v4f32 (alignedload node:$ptr))>;
125 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
126 (v2f64 (alignedload node:$ptr))>;
127 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
128 (v4i32 (alignedload node:$ptr))>;
129 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
130 (v2i64 (alignedload node:$ptr))>;
132 // Like 'load', but uses special alignment checks suitable for use in
133 // memory operands in most SSE instructions, which are required to
134 // be naturally aligned on some targets but not on others.
135 // FIXME: Actually implement support for targets that don't require the
136 // alignment. This probably wants a subtarget predicate.
137 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
138 return cast<LoadSDNode>(N)->getAlignment() >= 16;
141 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
142 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
143 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
144 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
145 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
146 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
147 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
149 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
151 // FIXME: 8 byte alignment for mmx reads is not required
152 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
153 return cast<LoadSDNode>(N)->getAlignment() >= 8;
156 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
157 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
158 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
159 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
161 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
162 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
163 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
164 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
165 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
166 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
168 def vzmovl_v2i64 : PatFrag<(ops node:$src),
169 (bitconvert (v2i64 (X86vzmovl
170 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
171 def vzmovl_v4i32 : PatFrag<(ops node:$src),
172 (bitconvert (v4i32 (X86vzmovl
173 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
175 def vzload_v2i64 : PatFrag<(ops node:$src),
176 (bitconvert (v2i64 (X86vzload node:$src)))>;
179 def fp32imm0 : PatLeaf<(f32 fpimm), [{
180 return N->isExactlyValue(+0.0);
183 // BYTE_imm - Transform bit immediates into byte immediates.
184 def BYTE_imm : SDNodeXForm<imm, [{
185 // Transformation function: imm >> 3
186 return getI32Imm(N->getZExtValue() >> 3);
189 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
191 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
192 return getI8Imm(X86::getShuffleSHUFImmediate(N));
195 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
197 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
198 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
201 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
203 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
204 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
207 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
209 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
210 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
213 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
214 (vector_shuffle node:$lhs, node:$rhs), [{
215 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
216 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
219 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
220 (vector_shuffle node:$lhs, node:$rhs), [{
221 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
224 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
225 (vector_shuffle node:$lhs, node:$rhs), [{
226 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
229 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
230 (vector_shuffle node:$lhs, node:$rhs), [{
231 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
234 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
235 (vector_shuffle node:$lhs, node:$rhs), [{
236 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
239 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
240 (vector_shuffle node:$lhs, node:$rhs), [{
241 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
244 def movl : PatFrag<(ops node:$lhs, node:$rhs),
245 (vector_shuffle node:$lhs, node:$rhs), [{
246 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
249 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
250 (vector_shuffle node:$lhs, node:$rhs), [{
251 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
254 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
255 (vector_shuffle node:$lhs, node:$rhs), [{
256 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
259 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
260 (vector_shuffle node:$lhs, node:$rhs), [{
261 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
264 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
265 (vector_shuffle node:$lhs, node:$rhs), [{
266 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
269 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
270 (vector_shuffle node:$lhs, node:$rhs), [{
271 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
274 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
275 (vector_shuffle node:$lhs, node:$rhs), [{
276 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
279 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
280 (vector_shuffle node:$lhs, node:$rhs), [{
281 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
282 }], SHUFFLE_get_shuf_imm>;
284 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
285 (vector_shuffle node:$lhs, node:$rhs), [{
286 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
287 }], SHUFFLE_get_shuf_imm>;
289 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
290 (vector_shuffle node:$lhs, node:$rhs), [{
291 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
292 }], SHUFFLE_get_pshufhw_imm>;
294 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
295 (vector_shuffle node:$lhs, node:$rhs), [{
296 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
297 }], SHUFFLE_get_pshuflw_imm>;
299 def palign : PatFrag<(ops node:$lhs, node:$rhs),
300 (vector_shuffle node:$lhs, node:$rhs), [{
301 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
302 }], SHUFFLE_get_palign_imm>;
304 //===----------------------------------------------------------------------===//
305 // SSE scalar FP Instructions
306 //===----------------------------------------------------------------------===//
308 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
309 // instruction selection into a branch sequence.
310 let Uses = [EFLAGS], usesCustomInserter = 1 in {
311 def CMOV_FR32 : I<0, Pseudo,
312 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
313 "#CMOV_FR32 PSEUDO!",
314 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
316 def CMOV_FR64 : I<0, Pseudo,
317 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
318 "#CMOV_FR64 PSEUDO!",
319 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
321 def CMOV_V4F32 : I<0, Pseudo,
322 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
323 "#CMOV_V4F32 PSEUDO!",
325 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
327 def CMOV_V2F64 : I<0, Pseudo,
328 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
329 "#CMOV_V2F64 PSEUDO!",
331 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
333 def CMOV_V2I64 : I<0, Pseudo,
334 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
335 "#CMOV_V2I64 PSEUDO!",
337 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
341 //===----------------------------------------------------------------------===//
343 //===----------------------------------------------------------------------===//
346 let neverHasSideEffects = 1 in
347 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
348 "movss\t{$src, $dst|$dst, $src}", []>;
349 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
350 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
351 "movss\t{$src, $dst|$dst, $src}",
352 [(set FR32:$dst, (loadf32 addr:$src))]>;
353 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
354 "movss\t{$src, $dst|$dst, $src}",
355 [(store FR32:$src, addr:$dst)]>;
357 // Conversion instructions
358 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
359 "cvttss2si\t{$src, $dst|$dst, $src}",
360 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
361 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
362 "cvttss2si\t{$src, $dst|$dst, $src}",
363 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
364 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
365 "cvtsi2ss\t{$src, $dst|$dst, $src}",
366 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
367 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
368 "cvtsi2ss\t{$src, $dst|$dst, $src}",
369 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
371 // Match intrinsics which expect XMM operand(s).
372 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
373 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
374 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
375 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
377 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
378 "cvtss2si\t{$src, $dst|$dst, $src}",
379 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
380 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
381 "cvtss2si\t{$src, $dst|$dst, $src}",
382 [(set GR32:$dst, (int_x86_sse_cvtss2si
383 (load addr:$src)))]>;
385 // Match intrinisics which expect MM and XMM operand(s).
386 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
387 "cvtps2pi\t{$src, $dst|$dst, $src}",
388 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
389 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
390 "cvtps2pi\t{$src, $dst|$dst, $src}",
391 [(set VR64:$dst, (int_x86_sse_cvtps2pi
392 (load addr:$src)))]>;
393 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
394 "cvttps2pi\t{$src, $dst|$dst, $src}",
395 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
396 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
397 "cvttps2pi\t{$src, $dst|$dst, $src}",
398 [(set VR64:$dst, (int_x86_sse_cvttps2pi
399 (load addr:$src)))]>;
400 let Constraints = "$src1 = $dst" in {
401 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
402 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
403 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
404 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
406 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
407 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
408 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
409 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
410 (load addr:$src2)))]>;
413 // Aliases for intrinsics
414 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
415 "cvttss2si\t{$src, $dst|$dst, $src}",
417 (int_x86_sse_cvttss2si VR128:$src))]>;
418 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
419 "cvttss2si\t{$src, $dst|$dst, $src}",
421 (int_x86_sse_cvttss2si(load addr:$src)))]>;
423 let Constraints = "$src1 = $dst" in {
424 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
425 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
426 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
427 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
429 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
430 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
431 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
432 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
433 (loadi32 addr:$src2)))]>;
436 // Comparison instructions
437 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
438 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
439 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
440 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
442 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
443 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
444 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
447 let Defs = [EFLAGS] in {
448 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
449 "ucomiss\t{$src2, $src1|$src1, $src2}",
450 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
451 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
452 "ucomiss\t{$src2, $src1|$src1, $src2}",
453 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
456 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
457 "comiss\t{$src2, $src1|$src1, $src2}", []>;
458 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
459 "comiss\t{$src2, $src1|$src1, $src2}", []>;
463 // Aliases to match intrinsics which expect XMM operand(s).
464 let Constraints = "$src1 = $dst" in {
465 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
467 (ins VR128:$src1, VR128:$src, SSECC:$cc),
468 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
469 [(set VR128:$dst, (int_x86_sse_cmp_ss
471 VR128:$src, imm:$cc))]>;
472 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
474 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
475 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
476 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
477 (load addr:$src), imm:$cc))]>;
480 let Defs = [EFLAGS] in {
481 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
482 "ucomiss\t{$src2, $src1|$src1, $src2}",
483 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
485 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
486 "ucomiss\t{$src2, $src1|$src1, $src2}",
487 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
490 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
491 "comiss\t{$src2, $src1|$src1, $src2}",
492 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
494 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
495 "comiss\t{$src2, $src1|$src1, $src2}",
496 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
500 // Aliases of packed SSE1 instructions for scalar use. These all have names
501 // that start with 'Fs'.
503 // Alias instructions that map fld0 to pxor for sse.
504 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
506 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
507 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
508 Requires<[HasSSE1]>, TB, OpSize;
510 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
512 let neverHasSideEffects = 1 in
513 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
514 "movaps\t{$src, $dst|$dst, $src}", []>;
516 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
518 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
519 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
520 "movaps\t{$src, $dst|$dst, $src}",
521 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
523 // Alias bitwise logical operations using SSE logical ops on packed FP values.
524 let Constraints = "$src1 = $dst" in {
525 let isCommutable = 1 in {
526 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
527 (ins FR32:$src1, FR32:$src2),
528 "andps\t{$src2, $dst|$dst, $src2}",
529 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
530 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
531 (ins FR32:$src1, FR32:$src2),
532 "orps\t{$src2, $dst|$dst, $src2}",
533 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
534 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
535 (ins FR32:$src1, FR32:$src2),
536 "xorps\t{$src2, $dst|$dst, $src2}",
537 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
540 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
541 (ins FR32:$src1, f128mem:$src2),
542 "andps\t{$src2, $dst|$dst, $src2}",
543 [(set FR32:$dst, (X86fand FR32:$src1,
544 (memopfsf32 addr:$src2)))]>;
545 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
546 (ins FR32:$src1, f128mem:$src2),
547 "orps\t{$src2, $dst|$dst, $src2}",
548 [(set FR32:$dst, (X86for FR32:$src1,
549 (memopfsf32 addr:$src2)))]>;
550 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
551 (ins FR32:$src1, f128mem:$src2),
552 "xorps\t{$src2, $dst|$dst, $src2}",
553 [(set FR32:$dst, (X86fxor FR32:$src1,
554 (memopfsf32 addr:$src2)))]>;
556 let neverHasSideEffects = 1 in {
557 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
558 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
559 "andnps\t{$src2, $dst|$dst, $src2}", []>;
561 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
562 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
563 "andnps\t{$src2, $dst|$dst, $src2}", []>;
567 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
569 /// In addition, we also have a special variant of the scalar form here to
570 /// represent the associated intrinsic operation. This form is unlike the
571 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
572 /// and leaves the top elements unmodified (therefore these cannot be commuted).
574 /// These three forms can each be reg+reg or reg+mem, so there are a total of
575 /// six "instructions".
577 let Constraints = "$src1 = $dst" in {
578 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
579 SDNode OpNode, Intrinsic F32Int,
580 bit Commutable = 0> {
581 // Scalar operation, reg+reg.
582 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
583 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
584 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
585 let isCommutable = Commutable;
588 // Scalar operation, reg+mem.
589 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
590 (ins FR32:$src1, f32mem:$src2),
591 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
592 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
594 // Vector operation, reg+reg.
595 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
596 (ins VR128:$src1, VR128:$src2),
597 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
598 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
599 let isCommutable = Commutable;
602 // Vector operation, reg+mem.
603 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
604 (ins VR128:$src1, f128mem:$src2),
605 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
606 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
608 // Intrinsic operation, reg+reg.
609 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
610 (ins VR128:$src1, VR128:$src2),
611 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
612 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
614 // Intrinsic operation, reg+mem.
615 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
616 (ins VR128:$src1, ssmem:$src2),
617 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
618 [(set VR128:$dst, (F32Int VR128:$src1,
619 sse_load_f32:$src2))]>;
623 // Arithmetic instructions
624 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
625 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
626 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
627 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
629 /// sse1_fp_binop_rm - Other SSE1 binops
631 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
632 /// instructions for a full-vector intrinsic form. Operations that map
633 /// onto C operators don't use this form since they just use the plain
634 /// vector form instead of having a separate vector intrinsic form.
636 /// This provides a total of eight "instructions".
638 let Constraints = "$src1 = $dst" in {
639 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
643 bit Commutable = 0> {
645 // Scalar operation, reg+reg.
646 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
647 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
648 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
649 let isCommutable = Commutable;
652 // Scalar operation, reg+mem.
653 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
654 (ins FR32:$src1, f32mem:$src2),
655 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
656 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
658 // Vector operation, reg+reg.
659 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
660 (ins VR128:$src1, VR128:$src2),
661 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
662 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
663 let isCommutable = Commutable;
666 // Vector operation, reg+mem.
667 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
668 (ins VR128:$src1, f128mem:$src2),
669 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
670 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
672 // Intrinsic operation, reg+reg.
673 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
674 (ins VR128:$src1, VR128:$src2),
675 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
676 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
677 let isCommutable = Commutable;
680 // Intrinsic operation, reg+mem.
681 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
682 (ins VR128:$src1, ssmem:$src2),
683 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
684 [(set VR128:$dst, (F32Int VR128:$src1,
685 sse_load_f32:$src2))]>;
687 // Vector intrinsic operation, reg+reg.
688 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
689 (ins VR128:$src1, VR128:$src2),
690 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
691 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
692 let isCommutable = Commutable;
695 // Vector intrinsic operation, reg+mem.
696 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
697 (ins VR128:$src1, f128mem:$src2),
698 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
699 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
703 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
704 int_x86_sse_max_ss, int_x86_sse_max_ps>;
705 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
706 int_x86_sse_min_ss, int_x86_sse_min_ps>;
708 //===----------------------------------------------------------------------===//
709 // SSE packed FP Instructions
712 let neverHasSideEffects = 1 in
713 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
714 "movaps\t{$src, $dst|$dst, $src}", []>;
715 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
716 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
717 "movaps\t{$src, $dst|$dst, $src}",
718 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
720 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
721 "movaps\t{$src, $dst|$dst, $src}",
722 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
724 let neverHasSideEffects = 1 in
725 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
726 "movups\t{$src, $dst|$dst, $src}", []>;
727 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
728 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
729 "movups\t{$src, $dst|$dst, $src}",
730 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
731 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
732 "movups\t{$src, $dst|$dst, $src}",
733 [(store (v4f32 VR128:$src), addr:$dst)]>;
735 // Intrinsic forms of MOVUPS load and store
736 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
737 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
738 "movups\t{$src, $dst|$dst, $src}",
739 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
740 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
741 "movups\t{$src, $dst|$dst, $src}",
742 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
744 let Constraints = "$src1 = $dst" in {
745 let AddedComplexity = 20 in {
746 def MOVLPSrm : PSI<0x12, MRMSrcMem,
747 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
748 "movlps\t{$src2, $dst|$dst, $src2}",
751 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
752 def MOVHPSrm : PSI<0x16, MRMSrcMem,
753 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
754 "movhps\t{$src2, $dst|$dst, $src2}",
756 (movlhps VR128:$src1,
757 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
759 } // Constraints = "$src1 = $dst"
762 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
763 "movlps\t{$src, $dst|$dst, $src}",
764 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
765 (iPTR 0))), addr:$dst)]>;
767 // v2f64 extract element 1 is always custom lowered to unpack high to low
768 // and extract element 0 so the non-store version isn't too horrible.
769 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
770 "movhps\t{$src, $dst|$dst, $src}",
771 [(store (f64 (vector_extract
772 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
773 (undef)), (iPTR 0))), addr:$dst)]>;
775 let Constraints = "$src1 = $dst" in {
776 let AddedComplexity = 20 in {
777 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
778 (ins VR128:$src1, VR128:$src2),
779 "movlhps\t{$src2, $dst|$dst, $src2}",
781 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
783 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
784 (ins VR128:$src1, VR128:$src2),
785 "movhlps\t{$src2, $dst|$dst, $src2}",
787 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
789 } // Constraints = "$src1 = $dst"
791 let AddedComplexity = 20 in {
792 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
793 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
794 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
795 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
802 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
804 /// In addition, we also have a special variant of the scalar form here to
805 /// represent the associated intrinsic operation. This form is unlike the
806 /// plain scalar form, in that it takes an entire vector (instead of a
807 /// scalar) and leaves the top elements undefined.
809 /// And, we have a special variant form for a full-vector intrinsic form.
811 /// These four forms can each have a reg or a mem operand, so there are a
812 /// total of eight "instructions".
814 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
818 bit Commutable = 0> {
819 // Scalar operation, reg.
820 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
821 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
822 [(set FR32:$dst, (OpNode FR32:$src))]> {
823 let isCommutable = Commutable;
826 // Scalar operation, mem.
827 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
828 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
829 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
830 Requires<[HasSSE1, OptForSize]>;
832 // Vector operation, reg.
833 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
834 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
835 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
836 let isCommutable = Commutable;
839 // Vector operation, mem.
840 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
841 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
842 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
844 // Intrinsic operation, reg.
845 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
846 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
847 [(set VR128:$dst, (F32Int VR128:$src))]> {
848 let isCommutable = Commutable;
851 // Intrinsic operation, mem.
852 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
853 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
854 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
856 // Vector intrinsic operation, reg
857 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
858 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
859 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
860 let isCommutable = Commutable;
863 // Vector intrinsic operation, mem
864 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
865 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
866 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
870 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
871 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
873 // Reciprocal approximations. Note that these typically require refinement
874 // in order to obtain suitable precision.
875 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
876 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
877 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
878 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
881 let Constraints = "$src1 = $dst" in {
882 let isCommutable = 1 in {
883 def ANDPSrr : PSI<0x54, MRMSrcReg,
884 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
885 "andps\t{$src2, $dst|$dst, $src2}",
886 [(set VR128:$dst, (v2i64
887 (and VR128:$src1, VR128:$src2)))]>;
888 def ORPSrr : PSI<0x56, MRMSrcReg,
889 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
890 "orps\t{$src2, $dst|$dst, $src2}",
891 [(set VR128:$dst, (v2i64
892 (or VR128:$src1, VR128:$src2)))]>;
893 def XORPSrr : PSI<0x57, MRMSrcReg,
894 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
895 "xorps\t{$src2, $dst|$dst, $src2}",
896 [(set VR128:$dst, (v2i64
897 (xor VR128:$src1, VR128:$src2)))]>;
900 def ANDPSrm : PSI<0x54, MRMSrcMem,
901 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
902 "andps\t{$src2, $dst|$dst, $src2}",
903 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
904 (memopv2i64 addr:$src2)))]>;
905 def ORPSrm : PSI<0x56, MRMSrcMem,
906 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
907 "orps\t{$src2, $dst|$dst, $src2}",
908 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
909 (memopv2i64 addr:$src2)))]>;
910 def XORPSrm : PSI<0x57, MRMSrcMem,
911 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
912 "xorps\t{$src2, $dst|$dst, $src2}",
913 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
914 (memopv2i64 addr:$src2)))]>;
915 def ANDNPSrr : PSI<0x55, MRMSrcReg,
916 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
917 "andnps\t{$src2, $dst|$dst, $src2}",
919 (v2i64 (and (xor VR128:$src1,
920 (bc_v2i64 (v4i32 immAllOnesV))),
922 def ANDNPSrm : PSI<0x55, MRMSrcMem,
923 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
924 "andnps\t{$src2, $dst|$dst, $src2}",
926 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
927 (bc_v2i64 (v4i32 immAllOnesV))),
928 (memopv2i64 addr:$src2))))]>;
931 let Constraints = "$src1 = $dst" in {
932 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
933 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
934 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
935 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
936 VR128:$src, imm:$cc))]>;
937 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
938 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
939 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
940 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
941 (memop addr:$src), imm:$cc))]>;
943 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
944 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
945 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
946 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
948 // Shuffle and unpack instructions
949 let Constraints = "$src1 = $dst" in {
950 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
951 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
952 (outs VR128:$dst), (ins VR128:$src1,
953 VR128:$src2, i8imm:$src3),
954 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
956 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
957 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
958 (outs VR128:$dst), (ins VR128:$src1,
959 f128mem:$src2, i8imm:$src3),
960 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
963 VR128:$src1, (memopv4f32 addr:$src2))))]>;
965 let AddedComplexity = 10 in {
966 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
967 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
968 "unpckhps\t{$src2, $dst|$dst, $src2}",
970 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
971 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
972 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
973 "unpckhps\t{$src2, $dst|$dst, $src2}",
975 (v4f32 (unpckh VR128:$src1,
976 (memopv4f32 addr:$src2))))]>;
978 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
979 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
980 "unpcklps\t{$src2, $dst|$dst, $src2}",
982 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
983 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
984 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
985 "unpcklps\t{$src2, $dst|$dst, $src2}",
987 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
989 } // Constraints = "$src1 = $dst"
992 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
993 "movmskps\t{$src, $dst|$dst, $src}",
994 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
995 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
996 "movmskpd\t{$src, $dst|$dst, $src}",
997 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
999 // Prefetch intrinsic.
1000 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1001 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1002 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1003 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1004 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1005 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1006 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1007 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1009 // Non-temporal stores
1010 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1011 "movntps\t{$src, $dst|$dst, $src}",
1012 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1014 // Load, store, and memory fence
1015 def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
1018 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1019 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1020 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1021 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1023 // Alias instructions that map zero vector to pxor / xorp* for sse.
1024 // We set canFoldAsLoad because this can be converted to a constant-pool
1025 // load of an all-zeros value if folding it would be beneficial.
1026 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1027 isCodeGenOnly = 1 in
1028 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
1029 "xorps\t$dst, $dst",
1030 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1032 let Predicates = [HasSSE1] in {
1033 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1034 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1035 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1036 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1037 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1040 // FR32 to 128-bit vector conversion.
1041 let isAsCheapAsAMove = 1 in
1042 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1043 "movss\t{$src, $dst|$dst, $src}",
1045 (v4f32 (scalar_to_vector FR32:$src)))]>;
1046 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1047 "movss\t{$src, $dst|$dst, $src}",
1049 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1051 // FIXME: may not be able to eliminate this movss with coalescing the src and
1052 // dest register classes are different. We really want to write this pattern
1054 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1055 // (f32 FR32:$src)>;
1056 let isAsCheapAsAMove = 1 in
1057 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1058 "movss\t{$src, $dst|$dst, $src}",
1059 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1061 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1062 "movss\t{$src, $dst|$dst, $src}",
1063 [(store (f32 (vector_extract (v4f32 VR128:$src),
1064 (iPTR 0))), addr:$dst)]>;
1067 // Move to lower bits of a VR128, leaving upper bits alone.
1068 // Three operand (but two address) aliases.
1069 let Constraints = "$src1 = $dst" in {
1070 let neverHasSideEffects = 1 in
1071 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1072 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1073 "movss\t{$src2, $dst|$dst, $src2}", []>;
1075 let AddedComplexity = 15 in
1076 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1077 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1078 "movss\t{$src2, $dst|$dst, $src2}",
1080 (v4f32 (movl VR128:$src1, VR128:$src2)))]>;
1083 // Move to lower bits of a VR128 and zeroing upper bits.
1084 // Loading from memory automatically zeroing upper bits.
1085 let AddedComplexity = 20 in
1086 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1087 "movss\t{$src, $dst|$dst, $src}",
1088 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1089 (loadf32 addr:$src))))))]>;
1091 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1092 (MOVZSS2PSrm addr:$src)>;
1094 //===---------------------------------------------------------------------===//
1095 // SSE2 Instructions
1096 //===---------------------------------------------------------------------===//
1098 // Move Instructions
1099 let neverHasSideEffects = 1 in
1100 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1101 "movsd\t{$src, $dst|$dst, $src}", []>;
1102 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1103 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1104 "movsd\t{$src, $dst|$dst, $src}",
1105 [(set FR64:$dst, (loadf64 addr:$src))]>;
1106 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1107 "movsd\t{$src, $dst|$dst, $src}",
1108 [(store FR64:$src, addr:$dst)]>;
1110 // Conversion instructions
1111 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1112 "cvttsd2si\t{$src, $dst|$dst, $src}",
1113 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1114 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1115 "cvttsd2si\t{$src, $dst|$dst, $src}",
1116 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1117 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1118 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1119 [(set FR32:$dst, (fround FR64:$src))]>;
1120 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1121 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1122 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1123 Requires<[HasSSE2, OptForSize]>;
1124 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1125 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1126 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1127 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1128 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1129 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1131 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1132 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1133 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1134 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1135 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1136 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1137 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1138 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1139 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1140 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1141 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1142 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1143 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1144 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1145 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1146 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1147 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1148 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1149 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1150 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1152 // SSE2 instructions with XS prefix
1153 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1154 "cvtss2sd\t{$src, $dst|$dst, $src}",
1155 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1156 Requires<[HasSSE2]>;
1157 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1158 "cvtss2sd\t{$src, $dst|$dst, $src}",
1159 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1160 Requires<[HasSSE2, OptForSize]>;
1162 def : Pat<(extloadf32 addr:$src),
1163 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1165 // Match intrinsics which expect XMM operand(s).
1166 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1167 "cvtsd2si\t{$src, $dst|$dst, $src}",
1168 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1169 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1170 "cvtsd2si\t{$src, $dst|$dst, $src}",
1171 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1172 (load addr:$src)))]>;
1174 // Match intrinisics which expect MM and XMM operand(s).
1175 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1176 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1177 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1178 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1179 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1180 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1181 (memop addr:$src)))]>;
1182 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1183 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1184 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1185 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1186 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1187 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1188 (memop addr:$src)))]>;
1189 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1190 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1191 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1192 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1193 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1194 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1195 (load addr:$src)))]>;
1197 // Aliases for intrinsics
1198 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1199 "cvttsd2si\t{$src, $dst|$dst, $src}",
1201 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1202 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1203 "cvttsd2si\t{$src, $dst|$dst, $src}",
1204 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1205 (load addr:$src)))]>;
1207 // Comparison instructions
1208 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1209 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1210 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1211 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1213 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1214 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1215 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1218 let Defs = [EFLAGS] in {
1219 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1220 "ucomisd\t{$src2, $src1|$src1, $src2}",
1221 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1222 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1223 "ucomisd\t{$src2, $src1|$src1, $src2}",
1224 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1225 (implicit EFLAGS)]>;
1226 } // Defs = [EFLAGS]
1228 // Aliases to match intrinsics which expect XMM operand(s).
1229 let Constraints = "$src1 = $dst" in {
1230 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1232 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1233 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1234 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1235 VR128:$src, imm:$cc))]>;
1236 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1238 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1239 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1240 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1241 (load addr:$src), imm:$cc))]>;
1244 let Defs = [EFLAGS] in {
1245 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1246 "ucomisd\t{$src2, $src1|$src1, $src2}",
1247 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1248 (implicit EFLAGS)]>;
1249 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1250 "ucomisd\t{$src2, $src1|$src1, $src2}",
1251 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1252 (implicit EFLAGS)]>;
1254 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1255 "comisd\t{$src2, $src1|$src1, $src2}",
1256 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1257 (implicit EFLAGS)]>;
1258 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1259 "comisd\t{$src2, $src1|$src1, $src2}",
1260 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1261 (implicit EFLAGS)]>;
1262 } // Defs = [EFLAGS]
1264 // Aliases of packed SSE2 instructions for scalar use. These all have names
1265 // that start with 'Fs'.
1267 // Alias instructions that map fld0 to pxor for sse.
1268 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1269 canFoldAsLoad = 1 in
1270 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1271 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1272 Requires<[HasSSE2]>, TB, OpSize;
1274 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1276 let neverHasSideEffects = 1 in
1277 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1278 "movapd\t{$src, $dst|$dst, $src}", []>;
1280 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1282 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1283 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1284 "movapd\t{$src, $dst|$dst, $src}",
1285 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1287 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1288 let Constraints = "$src1 = $dst" in {
1289 let isCommutable = 1 in {
1290 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1291 (ins FR64:$src1, FR64:$src2),
1292 "andpd\t{$src2, $dst|$dst, $src2}",
1293 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1294 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1295 (ins FR64:$src1, FR64:$src2),
1296 "orpd\t{$src2, $dst|$dst, $src2}",
1297 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1298 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1299 (ins FR64:$src1, FR64:$src2),
1300 "xorpd\t{$src2, $dst|$dst, $src2}",
1301 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1304 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1305 (ins FR64:$src1, f128mem:$src2),
1306 "andpd\t{$src2, $dst|$dst, $src2}",
1307 [(set FR64:$dst, (X86fand FR64:$src1,
1308 (memopfsf64 addr:$src2)))]>;
1309 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1310 (ins FR64:$src1, f128mem:$src2),
1311 "orpd\t{$src2, $dst|$dst, $src2}",
1312 [(set FR64:$dst, (X86for FR64:$src1,
1313 (memopfsf64 addr:$src2)))]>;
1314 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1315 (ins FR64:$src1, f128mem:$src2),
1316 "xorpd\t{$src2, $dst|$dst, $src2}",
1317 [(set FR64:$dst, (X86fxor FR64:$src1,
1318 (memopfsf64 addr:$src2)))]>;
1320 let neverHasSideEffects = 1 in {
1321 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1322 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1323 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1325 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1326 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1327 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1331 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1333 /// In addition, we also have a special variant of the scalar form here to
1334 /// represent the associated intrinsic operation. This form is unlike the
1335 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1336 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1338 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1339 /// six "instructions".
1341 let Constraints = "$src1 = $dst" in {
1342 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1343 SDNode OpNode, Intrinsic F64Int,
1344 bit Commutable = 0> {
1345 // Scalar operation, reg+reg.
1346 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1347 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1348 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1349 let isCommutable = Commutable;
1352 // Scalar operation, reg+mem.
1353 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1354 (ins FR64:$src1, f64mem:$src2),
1355 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1356 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1358 // Vector operation, reg+reg.
1359 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1360 (ins VR128:$src1, VR128:$src2),
1361 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1362 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1363 let isCommutable = Commutable;
1366 // Vector operation, reg+mem.
1367 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1368 (ins VR128:$src1, f128mem:$src2),
1369 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1370 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1372 // Intrinsic operation, reg+reg.
1373 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1374 (ins VR128:$src1, VR128:$src2),
1375 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1376 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1378 // Intrinsic operation, reg+mem.
1379 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1380 (ins VR128:$src1, sdmem:$src2),
1381 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1382 [(set VR128:$dst, (F64Int VR128:$src1,
1383 sse_load_f64:$src2))]>;
1387 // Arithmetic instructions
1388 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1389 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1390 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1391 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1393 /// sse2_fp_binop_rm - Other SSE2 binops
1395 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1396 /// instructions for a full-vector intrinsic form. Operations that map
1397 /// onto C operators don't use this form since they just use the plain
1398 /// vector form instead of having a separate vector intrinsic form.
1400 /// This provides a total of eight "instructions".
1402 let Constraints = "$src1 = $dst" in {
1403 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1407 bit Commutable = 0> {
1409 // Scalar operation, reg+reg.
1410 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1411 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1412 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1413 let isCommutable = Commutable;
1416 // Scalar operation, reg+mem.
1417 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1418 (ins FR64:$src1, f64mem:$src2),
1419 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1420 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1422 // Vector operation, reg+reg.
1423 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1424 (ins VR128:$src1, VR128:$src2),
1425 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1426 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1427 let isCommutable = Commutable;
1430 // Vector operation, reg+mem.
1431 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1432 (ins VR128:$src1, f128mem:$src2),
1433 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1434 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1436 // Intrinsic operation, reg+reg.
1437 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1438 (ins VR128:$src1, VR128:$src2),
1439 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1440 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1441 let isCommutable = Commutable;
1444 // Intrinsic operation, reg+mem.
1445 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1446 (ins VR128:$src1, sdmem:$src2),
1447 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1448 [(set VR128:$dst, (F64Int VR128:$src1,
1449 sse_load_f64:$src2))]>;
1451 // Vector intrinsic operation, reg+reg.
1452 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1453 (ins VR128:$src1, VR128:$src2),
1454 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1455 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1456 let isCommutable = Commutable;
1459 // Vector intrinsic operation, reg+mem.
1460 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1461 (ins VR128:$src1, f128mem:$src2),
1462 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1463 [(set VR128:$dst, (V2F64Int VR128:$src1,
1464 (memopv2f64 addr:$src2)))]>;
1468 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1469 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1470 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1471 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1473 //===---------------------------------------------------------------------===//
1474 // SSE packed FP Instructions
1476 // Move Instructions
1477 let neverHasSideEffects = 1 in
1478 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1479 "movapd\t{$src, $dst|$dst, $src}", []>;
1480 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1481 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1482 "movapd\t{$src, $dst|$dst, $src}",
1483 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1485 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1486 "movapd\t{$src, $dst|$dst, $src}",
1487 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1489 let neverHasSideEffects = 1 in
1490 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1491 "movupd\t{$src, $dst|$dst, $src}", []>;
1492 let canFoldAsLoad = 1 in
1493 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1494 "movupd\t{$src, $dst|$dst, $src}",
1495 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1496 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1497 "movupd\t{$src, $dst|$dst, $src}",
1498 [(store (v2f64 VR128:$src), addr:$dst)]>;
1500 // Intrinsic forms of MOVUPD load and store
1501 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1502 "movupd\t{$src, $dst|$dst, $src}",
1503 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1504 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1505 "movupd\t{$src, $dst|$dst, $src}",
1506 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1508 let Constraints = "$src1 = $dst" in {
1509 let AddedComplexity = 20 in {
1510 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1511 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1512 "movlpd\t{$src2, $dst|$dst, $src2}",
1514 (v2f64 (movlp VR128:$src1,
1515 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1516 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1517 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1518 "movhpd\t{$src2, $dst|$dst, $src2}",
1520 (v2f64 (movlhps VR128:$src1,
1521 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1522 } // AddedComplexity
1523 } // Constraints = "$src1 = $dst"
1525 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1526 "movlpd\t{$src, $dst|$dst, $src}",
1527 [(store (f64 (vector_extract (v2f64 VR128:$src),
1528 (iPTR 0))), addr:$dst)]>;
1530 // v2f64 extract element 1 is always custom lowered to unpack high to low
1531 // and extract element 0 so the non-store version isn't too horrible.
1532 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1533 "movhpd\t{$src, $dst|$dst, $src}",
1534 [(store (f64 (vector_extract
1535 (v2f64 (unpckh VR128:$src, (undef))),
1536 (iPTR 0))), addr:$dst)]>;
1538 // SSE2 instructions without OpSize prefix
1539 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1540 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1541 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1542 TB, Requires<[HasSSE2]>;
1543 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1544 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1545 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1546 (bitconvert (memopv2i64 addr:$src))))]>,
1547 TB, Requires<[HasSSE2]>;
1549 // SSE2 instructions with XS prefix
1550 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1551 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1552 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1553 XS, Requires<[HasSSE2]>;
1554 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1555 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1556 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1557 (bitconvert (memopv2i64 addr:$src))))]>,
1558 XS, Requires<[HasSSE2]>;
1560 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1561 "cvtps2dq\t{$src, $dst|$dst, $src}",
1562 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1563 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1564 "cvtps2dq\t{$src, $dst|$dst, $src}",
1565 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1566 (memop addr:$src)))]>;
1567 // SSE2 packed instructions with XS prefix
1568 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1569 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1570 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1571 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1573 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1574 "cvttps2dq\t{$src, $dst|$dst, $src}",
1576 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1577 XS, Requires<[HasSSE2]>;
1578 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1579 "cvttps2dq\t{$src, $dst|$dst, $src}",
1580 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1581 (memop addr:$src)))]>,
1582 XS, Requires<[HasSSE2]>;
1584 // SSE2 packed instructions with XD prefix
1585 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1586 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1587 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1588 XD, Requires<[HasSSE2]>;
1589 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1590 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1591 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1592 (memop addr:$src)))]>,
1593 XD, Requires<[HasSSE2]>;
1595 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1596 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1597 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1598 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1599 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1600 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1601 (memop addr:$src)))]>;
1603 // SSE2 instructions without OpSize prefix
1604 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1605 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1606 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1607 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1609 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1610 "cvtps2pd\t{$src, $dst|$dst, $src}",
1611 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1612 TB, Requires<[HasSSE2]>;
1613 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1614 "cvtps2pd\t{$src, $dst|$dst, $src}",
1615 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1616 (load addr:$src)))]>,
1617 TB, Requires<[HasSSE2]>;
1619 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1620 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1621 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1622 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1625 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1626 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1627 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1628 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1629 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1630 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1631 (memop addr:$src)))]>;
1633 // Match intrinsics which expect XMM operand(s).
1634 // Aliases for intrinsics
1635 let Constraints = "$src1 = $dst" in {
1636 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1637 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1638 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1639 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1641 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1642 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1643 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1644 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1645 (loadi32 addr:$src2)))]>;
1646 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1647 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1648 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1649 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1651 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1652 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1653 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1654 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1655 (load addr:$src2)))]>;
1656 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1657 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1658 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1659 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1660 VR128:$src2))]>, XS,
1661 Requires<[HasSSE2]>;
1662 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1663 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1664 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1665 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1666 (load addr:$src2)))]>, XS,
1667 Requires<[HasSSE2]>;
1672 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1674 /// In addition, we also have a special variant of the scalar form here to
1675 /// represent the associated intrinsic operation. This form is unlike the
1676 /// plain scalar form, in that it takes an entire vector (instead of a
1677 /// scalar) and leaves the top elements undefined.
1679 /// And, we have a special variant form for a full-vector intrinsic form.
1681 /// These four forms can each have a reg or a mem operand, so there are a
1682 /// total of eight "instructions".
1684 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1688 bit Commutable = 0> {
1689 // Scalar operation, reg.
1690 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1691 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1692 [(set FR64:$dst, (OpNode FR64:$src))]> {
1693 let isCommutable = Commutable;
1696 // Scalar operation, mem.
1697 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1698 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1699 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1701 // Vector operation, reg.
1702 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1703 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1704 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1705 let isCommutable = Commutable;
1708 // Vector operation, mem.
1709 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1710 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1711 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1713 // Intrinsic operation, reg.
1714 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1715 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1716 [(set VR128:$dst, (F64Int VR128:$src))]> {
1717 let isCommutable = Commutable;
1720 // Intrinsic operation, mem.
1721 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1722 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1723 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1725 // Vector intrinsic operation, reg
1726 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1727 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1728 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1729 let isCommutable = Commutable;
1732 // Vector intrinsic operation, mem
1733 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1734 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1735 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1739 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1740 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1742 // There is no f64 version of the reciprocal approximation instructions.
1745 let Constraints = "$src1 = $dst" in {
1746 let isCommutable = 1 in {
1747 def ANDPDrr : PDI<0x54, MRMSrcReg,
1748 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1749 "andpd\t{$src2, $dst|$dst, $src2}",
1751 (and (bc_v2i64 (v2f64 VR128:$src1)),
1752 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1753 def ORPDrr : PDI<0x56, MRMSrcReg,
1754 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1755 "orpd\t{$src2, $dst|$dst, $src2}",
1757 (or (bc_v2i64 (v2f64 VR128:$src1)),
1758 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1759 def XORPDrr : PDI<0x57, MRMSrcReg,
1760 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1761 "xorpd\t{$src2, $dst|$dst, $src2}",
1763 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1764 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1767 def ANDPDrm : PDI<0x54, MRMSrcMem,
1768 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1769 "andpd\t{$src2, $dst|$dst, $src2}",
1771 (and (bc_v2i64 (v2f64 VR128:$src1)),
1772 (memopv2i64 addr:$src2)))]>;
1773 def ORPDrm : PDI<0x56, MRMSrcMem,
1774 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1775 "orpd\t{$src2, $dst|$dst, $src2}",
1777 (or (bc_v2i64 (v2f64 VR128:$src1)),
1778 (memopv2i64 addr:$src2)))]>;
1779 def XORPDrm : PDI<0x57, MRMSrcMem,
1780 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1781 "xorpd\t{$src2, $dst|$dst, $src2}",
1783 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1784 (memopv2i64 addr:$src2)))]>;
1785 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1786 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1787 "andnpd\t{$src2, $dst|$dst, $src2}",
1789 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1790 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1791 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1792 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1793 "andnpd\t{$src2, $dst|$dst, $src2}",
1795 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1796 (memopv2i64 addr:$src2)))]>;
1799 let Constraints = "$src1 = $dst" in {
1800 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1801 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1802 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1803 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1804 VR128:$src, imm:$cc))]>;
1805 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1806 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1807 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1808 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1809 (memop addr:$src), imm:$cc))]>;
1811 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1812 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1813 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1814 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1816 // Shuffle and unpack instructions
1817 let Constraints = "$src1 = $dst" in {
1818 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1819 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1820 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1822 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1823 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1824 (outs VR128:$dst), (ins VR128:$src1,
1825 f128mem:$src2, i8imm:$src3),
1826 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1829 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1831 let AddedComplexity = 10 in {
1832 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1833 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1834 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1836 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1837 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1838 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1839 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1841 (v2f64 (unpckh VR128:$src1,
1842 (memopv2f64 addr:$src2))))]>;
1844 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1845 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1846 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1848 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1849 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1850 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1851 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1853 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1854 } // AddedComplexity
1855 } // Constraints = "$src1 = $dst"
1858 //===---------------------------------------------------------------------===//
1859 // SSE integer instructions
1861 // Move Instructions
1862 let neverHasSideEffects = 1 in
1863 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1864 "movdqa\t{$src, $dst|$dst, $src}", []>;
1865 let canFoldAsLoad = 1, mayLoad = 1 in
1866 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1867 "movdqa\t{$src, $dst|$dst, $src}",
1868 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1870 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1871 "movdqa\t{$src, $dst|$dst, $src}",
1872 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1873 let canFoldAsLoad = 1, mayLoad = 1 in
1874 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1875 "movdqu\t{$src, $dst|$dst, $src}",
1876 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1877 XS, Requires<[HasSSE2]>;
1879 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1880 "movdqu\t{$src, $dst|$dst, $src}",
1881 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1882 XS, Requires<[HasSSE2]>;
1884 // Intrinsic forms of MOVDQU load and store
1885 let canFoldAsLoad = 1 in
1886 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1887 "movdqu\t{$src, $dst|$dst, $src}",
1888 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1889 XS, Requires<[HasSSE2]>;
1890 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1891 "movdqu\t{$src, $dst|$dst, $src}",
1892 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1893 XS, Requires<[HasSSE2]>;
1895 let Constraints = "$src1 = $dst" in {
1897 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1898 bit Commutable = 0> {
1899 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1900 (ins VR128:$src1, VR128:$src2),
1901 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1902 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1903 let isCommutable = Commutable;
1905 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1906 (ins VR128:$src1, i128mem:$src2),
1907 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1908 [(set VR128:$dst, (IntId VR128:$src1,
1909 (bitconvert (memopv2i64
1913 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1915 Intrinsic IntId, Intrinsic IntId2> {
1916 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1917 (ins VR128:$src1, VR128:$src2),
1918 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1919 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1920 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1921 (ins VR128:$src1, i128mem:$src2),
1922 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1923 [(set VR128:$dst, (IntId VR128:$src1,
1924 (bitconvert (memopv2i64 addr:$src2))))]>;
1925 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
1926 (ins VR128:$src1, i32i8imm:$src2),
1927 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1928 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1931 /// PDI_binop_rm - Simple SSE2 binary operator.
1932 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1933 ValueType OpVT, bit Commutable = 0> {
1934 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1935 (ins VR128:$src1, VR128:$src2),
1936 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1937 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1938 let isCommutable = Commutable;
1940 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1941 (ins VR128:$src1, i128mem:$src2),
1942 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1943 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1944 (bitconvert (memopv2i64 addr:$src2)))))]>;
1947 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1949 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1950 /// to collapse (bitconvert VT to VT) into its operand.
1952 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1953 bit Commutable = 0> {
1954 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1955 (ins VR128:$src1, VR128:$src2),
1956 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1957 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1958 let isCommutable = Commutable;
1960 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1961 (ins VR128:$src1, i128mem:$src2),
1962 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1963 [(set VR128:$dst, (OpNode VR128:$src1,
1964 (memopv2i64 addr:$src2)))]>;
1967 } // Constraints = "$src1 = $dst"
1969 // 128-bit Integer Arithmetic
1971 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1972 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1973 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1974 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1976 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1977 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1978 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1979 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1981 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1982 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1983 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1984 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1986 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1987 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1988 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1989 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1991 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1993 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1994 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1995 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1997 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1999 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2000 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2003 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2004 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2005 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2006 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2007 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2010 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2011 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2012 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2013 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2014 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2015 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2017 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2018 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2019 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2020 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2021 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2022 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2024 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2025 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2026 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2027 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2029 // 128-bit logical shifts.
2030 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
2031 def PSLLDQri : PDIi8<0x73, MRM7r,
2032 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2033 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2034 def PSRLDQri : PDIi8<0x73, MRM3r,
2035 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2036 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2037 // PSRADQri doesn't exist in SSE[1-3].
2040 let Predicates = [HasSSE2] in {
2041 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2042 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2043 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2044 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2045 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2046 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2047 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2048 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2049 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2050 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2052 // Shift up / down and insert zero's.
2053 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2054 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2055 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2056 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2060 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2061 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2062 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2064 let Constraints = "$src1 = $dst" in {
2065 def PANDNrr : PDI<0xDF, MRMSrcReg,
2066 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2067 "pandn\t{$src2, $dst|$dst, $src2}",
2068 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2071 def PANDNrm : PDI<0xDF, MRMSrcMem,
2072 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2073 "pandn\t{$src2, $dst|$dst, $src2}",
2074 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2075 (memopv2i64 addr:$src2))))]>;
2078 // SSE2 Integer comparison
2079 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2080 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2081 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2082 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2083 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2084 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2086 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2087 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2088 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2089 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2090 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2091 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2092 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2093 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2094 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2095 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2096 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2097 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2099 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2100 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2101 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2102 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2103 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2104 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2105 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2106 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2107 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2108 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2109 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2110 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2113 // Pack instructions
2114 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2115 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2116 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2118 // Shuffle and unpack instructions
2119 let AddedComplexity = 5 in {
2120 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2121 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2122 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2123 [(set VR128:$dst, (v4i32 (pshufd:$src2
2124 VR128:$src1, (undef))))]>;
2125 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2126 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2127 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2128 [(set VR128:$dst, (v4i32 (pshufd:$src2
2129 (bc_v4i32 (memopv2i64 addr:$src1)),
2133 // SSE2 with ImmT == Imm8 and XS prefix.
2134 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2135 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2136 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2137 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2139 XS, Requires<[HasSSE2]>;
2140 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2141 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2142 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2143 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2144 (bc_v8i16 (memopv2i64 addr:$src1)),
2146 XS, Requires<[HasSSE2]>;
2148 // SSE2 with ImmT == Imm8 and XD prefix.
2149 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2150 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2151 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2152 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2154 XD, Requires<[HasSSE2]>;
2155 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2156 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2157 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2158 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2159 (bc_v8i16 (memopv2i64 addr:$src1)),
2161 XD, Requires<[HasSSE2]>;
2164 let Constraints = "$src1 = $dst" in {
2165 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2166 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2167 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2169 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2170 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2171 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2172 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2174 (unpckl VR128:$src1,
2175 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2176 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2177 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2178 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2180 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2181 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2182 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2183 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2185 (unpckl VR128:$src1,
2186 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2187 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2188 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2189 "punpckldq\t{$src2, $dst|$dst, $src2}",
2191 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2192 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2193 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2194 "punpckldq\t{$src2, $dst|$dst, $src2}",
2196 (unpckl VR128:$src1,
2197 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2198 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2199 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2200 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2202 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2203 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2204 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2205 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2207 (v2i64 (unpckl VR128:$src1,
2208 (memopv2i64 addr:$src2))))]>;
2210 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2211 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2212 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2214 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2215 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2216 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2217 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2219 (unpckh VR128:$src1,
2220 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2221 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2222 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2223 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2225 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2226 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2227 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2228 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2230 (unpckh VR128:$src1,
2231 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2232 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2233 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2234 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2236 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2237 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2238 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2239 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2241 (unpckh VR128:$src1,
2242 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2243 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2244 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2245 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2247 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2248 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2249 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2250 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2252 (v2i64 (unpckh VR128:$src1,
2253 (memopv2i64 addr:$src2))))]>;
2257 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2258 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2259 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2260 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2262 let Constraints = "$src1 = $dst" in {
2263 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2264 (outs VR128:$dst), (ins VR128:$src1,
2265 GR32:$src2, i32i8imm:$src3),
2266 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2268 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2269 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2270 (outs VR128:$dst), (ins VR128:$src1,
2271 i16mem:$src2, i32i8imm:$src3),
2272 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2274 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2279 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2280 "pmovmskb\t{$src, $dst|$dst, $src}",
2281 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2283 // Conditional store
2285 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2286 "maskmovdqu\t{$mask, $src|$src, $mask}",
2287 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2290 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2291 "maskmovdqu\t{$mask, $src|$src, $mask}",
2292 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2294 // Non-temporal stores
2295 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2296 "movntpd\t{$src, $dst|$dst, $src}",
2297 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2298 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2299 "movntdq\t{$src, $dst|$dst, $src}",
2300 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2301 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2302 "movnti\t{$src, $dst|$dst, $src}",
2303 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2304 TB, Requires<[HasSSE2]>;
2307 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2308 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2309 TB, Requires<[HasSSE2]>;
2311 // Load, store, and memory fence
2312 def LFENCE : I<0xAE, MRM5r, (outs), (ins),
2313 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2314 def MFENCE : I<0xAE, MRM6r, (outs), (ins),
2315 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2317 //TODO: custom lower this so as to never even generate the noop
2318 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2320 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2321 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2322 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2325 // Alias instructions that map zero vector to pxor / xorp* for sse.
2326 // We set canFoldAsLoad because this can be converted to a constant-pool
2327 // load of an all-ones value if folding it would be beneficial.
2328 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2329 isCodeGenOnly = 1 in
2330 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2331 "pcmpeqd\t$dst, $dst",
2332 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2334 // FR64 to 128-bit vector conversion.
2335 let isAsCheapAsAMove = 1 in
2336 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2337 "movsd\t{$src, $dst|$dst, $src}",
2339 (v2f64 (scalar_to_vector FR64:$src)))]>;
2340 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2341 "movsd\t{$src, $dst|$dst, $src}",
2343 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2345 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2346 "movd\t{$src, $dst|$dst, $src}",
2348 (v4i32 (scalar_to_vector GR32:$src)))]>;
2349 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2350 "movd\t{$src, $dst|$dst, $src}",
2352 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2354 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2355 "movd\t{$src, $dst|$dst, $src}",
2356 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2358 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2359 "movd\t{$src, $dst|$dst, $src}",
2360 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2362 // SSE2 instructions with XS prefix
2363 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2364 "movq\t{$src, $dst|$dst, $src}",
2366 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2367 Requires<[HasSSE2]>;
2368 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2369 "movq\t{$src, $dst|$dst, $src}",
2370 [(store (i64 (vector_extract (v2i64 VR128:$src),
2371 (iPTR 0))), addr:$dst)]>;
2373 // FIXME: may not be able to eliminate this movss with coalescing the src and
2374 // dest register classes are different. We really want to write this pattern
2376 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2377 // (f32 FR32:$src)>;
2378 let isAsCheapAsAMove = 1 in
2379 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2380 "movsd\t{$src, $dst|$dst, $src}",
2381 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2383 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2384 "movsd\t{$src, $dst|$dst, $src}",
2385 [(store (f64 (vector_extract (v2f64 VR128:$src),
2386 (iPTR 0))), addr:$dst)]>;
2387 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2388 "movd\t{$src, $dst|$dst, $src}",
2389 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2391 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2392 "movd\t{$src, $dst|$dst, $src}",
2393 [(store (i32 (vector_extract (v4i32 VR128:$src),
2394 (iPTR 0))), addr:$dst)]>;
2396 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2397 "movd\t{$src, $dst|$dst, $src}",
2398 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2399 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2400 "movd\t{$src, $dst|$dst, $src}",
2401 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2404 // Move to lower bits of a VR128, leaving upper bits alone.
2405 // Three operand (but two address) aliases.
2406 let Constraints = "$src1 = $dst" in {
2407 let neverHasSideEffects = 1 in
2408 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2409 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2410 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2412 let AddedComplexity = 15 in
2413 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2414 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2415 "movsd\t{$src2, $dst|$dst, $src2}",
2417 (v2f64 (movl VR128:$src1, VR128:$src2)))]>;
2420 // Store / copy lower 64-bits of a XMM register.
2421 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2422 "movq\t{$src, $dst|$dst, $src}",
2423 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2425 // Move to lower bits of a VR128 and zeroing upper bits.
2426 // Loading from memory automatically zeroing upper bits.
2427 let AddedComplexity = 20 in {
2428 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2429 "movsd\t{$src, $dst|$dst, $src}",
2431 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2432 (loadf64 addr:$src))))))]>;
2434 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2435 (MOVZSD2PDrm addr:$src)>;
2436 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2437 (MOVZSD2PDrm addr:$src)>;
2438 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2441 // movd / movq to XMM register zero-extends
2442 let AddedComplexity = 15 in {
2443 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2444 "movd\t{$src, $dst|$dst, $src}",
2445 [(set VR128:$dst, (v4i32 (X86vzmovl
2446 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2447 // This is X86-64 only.
2448 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2449 "mov{d|q}\t{$src, $dst|$dst, $src}",
2450 [(set VR128:$dst, (v2i64 (X86vzmovl
2451 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2454 let AddedComplexity = 20 in {
2455 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2456 "movd\t{$src, $dst|$dst, $src}",
2458 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2459 (loadi32 addr:$src))))))]>;
2461 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2462 (MOVZDI2PDIrm addr:$src)>;
2463 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2464 (MOVZDI2PDIrm addr:$src)>;
2465 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2466 (MOVZDI2PDIrm addr:$src)>;
2468 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2469 "movq\t{$src, $dst|$dst, $src}",
2471 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2472 (loadi64 addr:$src))))))]>, XS,
2473 Requires<[HasSSE2]>;
2475 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2476 (MOVZQI2PQIrm addr:$src)>;
2477 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2478 (MOVZQI2PQIrm addr:$src)>;
2479 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2482 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2483 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2484 let AddedComplexity = 15 in
2485 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2486 "movq\t{$src, $dst|$dst, $src}",
2487 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2488 XS, Requires<[HasSSE2]>;
2490 let AddedComplexity = 20 in {
2491 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2492 "movq\t{$src, $dst|$dst, $src}",
2493 [(set VR128:$dst, (v2i64 (X86vzmovl
2494 (loadv2i64 addr:$src))))]>,
2495 XS, Requires<[HasSSE2]>;
2497 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2498 (MOVZPQILo2PQIrm addr:$src)>;
2501 // Instructions for the disassembler
2502 // xr = XMM register
2505 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2506 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2508 //===---------------------------------------------------------------------===//
2509 // SSE3 Instructions
2510 //===---------------------------------------------------------------------===//
2512 // Move Instructions
2513 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2514 "movshdup\t{$src, $dst|$dst, $src}",
2515 [(set VR128:$dst, (v4f32 (movshdup
2516 VR128:$src, (undef))))]>;
2517 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2518 "movshdup\t{$src, $dst|$dst, $src}",
2519 [(set VR128:$dst, (movshdup
2520 (memopv4f32 addr:$src), (undef)))]>;
2522 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2523 "movsldup\t{$src, $dst|$dst, $src}",
2524 [(set VR128:$dst, (v4f32 (movsldup
2525 VR128:$src, (undef))))]>;
2526 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2527 "movsldup\t{$src, $dst|$dst, $src}",
2528 [(set VR128:$dst, (movsldup
2529 (memopv4f32 addr:$src), (undef)))]>;
2531 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2532 "movddup\t{$src, $dst|$dst, $src}",
2533 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2534 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2535 "movddup\t{$src, $dst|$dst, $src}",
2537 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2540 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2542 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2544 let AddedComplexity = 5 in {
2545 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2546 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2547 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2548 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2549 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2550 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2551 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2552 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2556 let Constraints = "$src1 = $dst" in {
2557 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2558 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2559 "addsubps\t{$src2, $dst|$dst, $src2}",
2560 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2562 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2563 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2564 "addsubps\t{$src2, $dst|$dst, $src2}",
2565 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2566 (memop addr:$src2)))]>;
2567 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2568 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2569 "addsubpd\t{$src2, $dst|$dst, $src2}",
2570 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2572 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2573 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2574 "addsubpd\t{$src2, $dst|$dst, $src2}",
2575 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2576 (memop addr:$src2)))]>;
2579 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2580 "lddqu\t{$src, $dst|$dst, $src}",
2581 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2584 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2585 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2586 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2587 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2588 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2589 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2590 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2591 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2592 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2593 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2594 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2595 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2596 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2597 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2598 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2599 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2601 let Constraints = "$src1 = $dst" in {
2602 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2603 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2604 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2605 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2606 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2607 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2608 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2609 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2612 // Thread synchronization
2613 def MONITOR : I<0x01, MRM1r, (outs), (ins), "monitor",
2614 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2615 def MWAIT : I<0x01, MRM1r, (outs), (ins), "mwait",
2616 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2618 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2619 let AddedComplexity = 15 in
2620 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2621 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2622 let AddedComplexity = 20 in
2623 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2624 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2626 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2627 let AddedComplexity = 15 in
2628 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2629 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2630 let AddedComplexity = 20 in
2631 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2632 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2634 //===---------------------------------------------------------------------===//
2635 // SSSE3 Instructions
2636 //===---------------------------------------------------------------------===//
2638 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2639 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2640 Intrinsic IntId64, Intrinsic IntId128> {
2641 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2642 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2643 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2645 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2646 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2648 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2650 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2652 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2653 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2656 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2658 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2661 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2664 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2665 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2666 Intrinsic IntId64, Intrinsic IntId128> {
2667 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2669 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2670 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2672 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2674 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2677 (bitconvert (memopv4i16 addr:$src))))]>;
2679 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2681 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2682 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2685 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2687 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2690 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2693 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2694 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2695 Intrinsic IntId64, Intrinsic IntId128> {
2696 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2698 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2699 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2701 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2703 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2706 (bitconvert (memopv2i32 addr:$src))))]>;
2708 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2710 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2711 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2714 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2716 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2719 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2722 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2723 int_x86_ssse3_pabs_b,
2724 int_x86_ssse3_pabs_b_128>;
2725 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2726 int_x86_ssse3_pabs_w,
2727 int_x86_ssse3_pabs_w_128>;
2728 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2729 int_x86_ssse3_pabs_d,
2730 int_x86_ssse3_pabs_d_128>;
2732 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2733 let Constraints = "$src1 = $dst" in {
2734 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2735 Intrinsic IntId64, Intrinsic IntId128,
2736 bit Commutable = 0> {
2737 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2738 (ins VR64:$src1, VR64:$src2),
2739 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2740 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2741 let isCommutable = Commutable;
2743 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2744 (ins VR64:$src1, i64mem:$src2),
2745 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2747 (IntId64 VR64:$src1,
2748 (bitconvert (memopv8i8 addr:$src2))))]>;
2750 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2751 (ins VR128:$src1, VR128:$src2),
2752 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2753 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2755 let isCommutable = Commutable;
2757 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2758 (ins VR128:$src1, i128mem:$src2),
2759 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2761 (IntId128 VR128:$src1,
2762 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2766 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2767 let Constraints = "$src1 = $dst" in {
2768 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2769 Intrinsic IntId64, Intrinsic IntId128,
2770 bit Commutable = 0> {
2771 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2772 (ins VR64:$src1, VR64:$src2),
2773 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2774 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2775 let isCommutable = Commutable;
2777 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2778 (ins VR64:$src1, i64mem:$src2),
2779 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2781 (IntId64 VR64:$src1,
2782 (bitconvert (memopv4i16 addr:$src2))))]>;
2784 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2785 (ins VR128:$src1, VR128:$src2),
2786 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2787 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2789 let isCommutable = Commutable;
2791 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2792 (ins VR128:$src1, i128mem:$src2),
2793 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2795 (IntId128 VR128:$src1,
2796 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2800 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2801 let Constraints = "$src1 = $dst" in {
2802 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2803 Intrinsic IntId64, Intrinsic IntId128,
2804 bit Commutable = 0> {
2805 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2806 (ins VR64:$src1, VR64:$src2),
2807 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2808 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2809 let isCommutable = Commutable;
2811 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2812 (ins VR64:$src1, i64mem:$src2),
2813 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2815 (IntId64 VR64:$src1,
2816 (bitconvert (memopv2i32 addr:$src2))))]>;
2818 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2819 (ins VR128:$src1, VR128:$src2),
2820 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2821 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2823 let isCommutable = Commutable;
2825 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2826 (ins VR128:$src1, i128mem:$src2),
2827 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2829 (IntId128 VR128:$src1,
2830 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2834 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2835 int_x86_ssse3_phadd_w,
2836 int_x86_ssse3_phadd_w_128>;
2837 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2838 int_x86_ssse3_phadd_d,
2839 int_x86_ssse3_phadd_d_128>;
2840 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2841 int_x86_ssse3_phadd_sw,
2842 int_x86_ssse3_phadd_sw_128>;
2843 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2844 int_x86_ssse3_phsub_w,
2845 int_x86_ssse3_phsub_w_128>;
2846 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2847 int_x86_ssse3_phsub_d,
2848 int_x86_ssse3_phsub_d_128>;
2849 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2850 int_x86_ssse3_phsub_sw,
2851 int_x86_ssse3_phsub_sw_128>;
2852 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2853 int_x86_ssse3_pmadd_ub_sw,
2854 int_x86_ssse3_pmadd_ub_sw_128>;
2855 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2856 int_x86_ssse3_pmul_hr_sw,
2857 int_x86_ssse3_pmul_hr_sw_128, 1>;
2858 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2859 int_x86_ssse3_pshuf_b,
2860 int_x86_ssse3_pshuf_b_128>;
2861 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2862 int_x86_ssse3_psign_b,
2863 int_x86_ssse3_psign_b_128>;
2864 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2865 int_x86_ssse3_psign_w,
2866 int_x86_ssse3_psign_w_128>;
2867 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2868 int_x86_ssse3_psign_d,
2869 int_x86_ssse3_psign_d_128>;
2871 let Constraints = "$src1 = $dst" in {
2872 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2873 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2874 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2876 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2877 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2878 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2881 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2882 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2883 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2885 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2886 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2887 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2891 // palignr patterns.
2892 def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)),
2893 (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>,
2894 Requires<[HasSSSE3]>;
2895 def : Pat<(int_x86_ssse3_palign_r VR64:$src1,
2896 (memop64 addr:$src2),
2898 (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2899 Requires<[HasSSSE3]>;
2901 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)),
2902 (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>,
2903 Requires<[HasSSSE3]>;
2904 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1,
2905 (memopv2i64 addr:$src2),
2907 (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2908 Requires<[HasSSSE3]>;
2910 let AddedComplexity = 5 in {
2911 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2912 (PALIGNR128rr VR128:$src2, VR128:$src1,
2913 (SHUFFLE_get_palign_imm VR128:$src3))>,
2914 Requires<[HasSSSE3]>;
2915 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2916 (PALIGNR128rr VR128:$src2, VR128:$src1,
2917 (SHUFFLE_get_palign_imm VR128:$src3))>,
2918 Requires<[HasSSSE3]>;
2919 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2920 (PALIGNR128rr VR128:$src2, VR128:$src1,
2921 (SHUFFLE_get_palign_imm VR128:$src3))>,
2922 Requires<[HasSSSE3]>;
2923 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2924 (PALIGNR128rr VR128:$src2, VR128:$src1,
2925 (SHUFFLE_get_palign_imm VR128:$src3))>,
2926 Requires<[HasSSSE3]>;
2929 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2930 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2931 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2932 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2934 //===---------------------------------------------------------------------===//
2935 // Non-Instruction Patterns
2936 //===---------------------------------------------------------------------===//
2938 // extload f32 -> f64. This matches load+fextend because we have a hack in
2939 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2941 // Since these loads aren't folded into the fextend, we have to match it
2943 let Predicates = [HasSSE2] in
2944 def : Pat<(fextend (loadf32 addr:$src)),
2945 (CVTSS2SDrm addr:$src)>;
2948 let Predicates = [HasSSE2] in {
2949 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2950 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2951 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2952 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2953 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2954 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2955 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2956 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2957 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2958 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2959 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2960 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2961 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2962 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2963 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2964 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2965 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2966 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2967 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2968 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2969 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2970 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2971 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2972 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2973 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2974 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2975 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2976 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2977 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2978 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2981 // Move scalar to XMM zero-extended
2982 // movd to XMM register zero-extends
2983 let AddedComplexity = 15 in {
2984 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2985 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2986 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2987 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2988 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>;
2989 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2990 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2991 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2992 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2995 // Splat v2f64 / v2i64
2996 let AddedComplexity = 10 in {
2997 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2998 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2999 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3000 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3001 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3002 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3003 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3004 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3007 // Special unary SHUFPSrri case.
3008 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3009 (SHUFPSrri VR128:$src1, VR128:$src1,
3010 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3011 Requires<[HasSSE1]>;
3012 let AddedComplexity = 5 in
3013 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3014 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3015 Requires<[HasSSE2]>;
3016 // Special unary SHUFPDrri case.
3017 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3018 (SHUFPDrri VR128:$src1, VR128:$src1,
3019 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3020 Requires<[HasSSE2]>;
3021 // Special unary SHUFPDrri case.
3022 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3023 (SHUFPDrri VR128:$src1, VR128:$src1,
3024 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3025 Requires<[HasSSE2]>;
3026 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3027 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3028 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3029 Requires<[HasSSE2]>;
3031 // Special binary v4i32 shuffle cases with SHUFPS.
3032 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3033 (SHUFPSrri VR128:$src1, VR128:$src2,
3034 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3035 Requires<[HasSSE2]>;
3036 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3037 (SHUFPSrmi VR128:$src1, addr:$src2,
3038 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3039 Requires<[HasSSE2]>;
3040 // Special binary v2i64 shuffle cases using SHUFPDrri.
3041 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3042 (SHUFPDrri VR128:$src1, VR128:$src2,
3043 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3044 Requires<[HasSSE2]>;
3046 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3047 let AddedComplexity = 15 in {
3048 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3049 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3050 Requires<[OptForSpeed, HasSSE2]>;
3051 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3052 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3053 Requires<[OptForSpeed, HasSSE2]>;
3055 let AddedComplexity = 10 in {
3056 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3057 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
3058 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3059 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3060 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3061 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3062 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3063 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3066 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3067 let AddedComplexity = 15 in {
3068 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3069 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3070 Requires<[OptForSpeed, HasSSE2]>;
3071 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3072 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3073 Requires<[OptForSpeed, HasSSE2]>;
3075 let AddedComplexity = 10 in {
3076 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3077 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
3078 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3079 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3080 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3081 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3082 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3083 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3086 let AddedComplexity = 20 in {
3087 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3088 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3089 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3091 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3092 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3093 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3095 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3096 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3097 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3098 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3099 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3102 let AddedComplexity = 20 in {
3103 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3104 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3105 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3106 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3107 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3108 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3109 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3110 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3111 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3114 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3115 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3116 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3117 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3118 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3119 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3121 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3122 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3123 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3125 let AddedComplexity = 15 in {
3126 // Setting the lowest element in the vector.
3127 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3128 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3129 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3130 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3132 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3133 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3134 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3135 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3136 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3139 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3140 // fall back to this for SSE1)
3141 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3142 (SHUFPSrri VR128:$src2, VR128:$src1,
3143 (SHUFFLE_get_shuf_imm VR128:$src3))>, Requires<[HasSSE1]>;
3145 // Set lowest element and zero upper elements.
3146 let AddedComplexity = 15 in
3147 def : Pat<(v2f64 (movl immAllZerosV_bc, VR128:$src)),
3148 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3149 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3150 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3152 // Some special case pandn patterns.
3153 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3155 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3156 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3158 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3159 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3161 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3163 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3164 (memop addr:$src2))),
3165 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3166 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3167 (memop addr:$src2))),
3168 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3169 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3170 (memop addr:$src2))),
3171 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3173 // vector -> vector casts
3174 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3175 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3176 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3177 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3178 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3179 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3180 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3181 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3183 // Use movaps / movups for SSE integer load / store (one byte shorter).
3184 def : Pat<(alignedloadv4i32 addr:$src),
3185 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3186 def : Pat<(loadv4i32 addr:$src),
3187 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3188 def : Pat<(alignedloadv2i64 addr:$src),
3189 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3190 def : Pat<(loadv2i64 addr:$src),
3191 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3193 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3194 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3195 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3196 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3197 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3198 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3199 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3200 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3201 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3202 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3203 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3204 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3205 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3206 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3207 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3208 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3210 //===----------------------------------------------------------------------===//
3211 // SSE4.1 Instructions
3212 //===----------------------------------------------------------------------===//
3214 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3217 Intrinsic V2F64Int> {
3218 // Intrinsic operation, reg.
3219 // Vector intrinsic operation, reg
3220 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3221 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3222 !strconcat(OpcodeStr,
3223 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3224 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3227 // Vector intrinsic operation, mem
3228 def PSm_Int : Ii8<opcps, MRMSrcMem,
3229 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3230 !strconcat(OpcodeStr,
3231 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3233 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3235 Requires<[HasSSE41]>;
3237 // Vector intrinsic operation, reg
3238 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3239 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3240 !strconcat(OpcodeStr,
3241 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3242 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3245 // Vector intrinsic operation, mem
3246 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3247 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3248 !strconcat(OpcodeStr,
3249 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3251 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3255 let Constraints = "$src1 = $dst" in {
3256 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3260 // Intrinsic operation, reg.
3261 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3263 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3264 !strconcat(OpcodeStr,
3265 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3267 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3270 // Intrinsic operation, mem.
3271 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3273 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3274 !strconcat(OpcodeStr,
3275 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3277 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3280 // Intrinsic operation, reg.
3281 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3283 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3284 !strconcat(OpcodeStr,
3285 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3287 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3290 // Intrinsic operation, mem.
3291 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3293 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3294 !strconcat(OpcodeStr,
3295 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3297 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3302 // FP round - roundss, roundps, roundsd, roundpd
3303 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3304 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3305 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3306 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3308 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3309 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3310 Intrinsic IntId128> {
3311 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3313 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3314 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3315 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3317 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3320 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3323 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3324 int_x86_sse41_phminposuw>;
3326 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3327 let Constraints = "$src1 = $dst" in {
3328 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3329 Intrinsic IntId128, bit Commutable = 0> {
3330 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3331 (ins VR128:$src1, VR128:$src2),
3332 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3333 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3335 let isCommutable = Commutable;
3337 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3338 (ins VR128:$src1, i128mem:$src2),
3339 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3341 (IntId128 VR128:$src1,
3342 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3346 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3347 int_x86_sse41_pcmpeqq, 1>;
3348 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3349 int_x86_sse41_packusdw, 0>;
3350 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3351 int_x86_sse41_pminsb, 1>;
3352 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3353 int_x86_sse41_pminsd, 1>;
3354 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3355 int_x86_sse41_pminud, 1>;
3356 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3357 int_x86_sse41_pminuw, 1>;
3358 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3359 int_x86_sse41_pmaxsb, 1>;
3360 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3361 int_x86_sse41_pmaxsd, 1>;
3362 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3363 int_x86_sse41_pmaxud, 1>;
3364 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3365 int_x86_sse41_pmaxuw, 1>;
3367 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3369 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3370 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3371 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3372 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3374 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3375 let Constraints = "$src1 = $dst" in {
3376 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3377 SDNode OpNode, Intrinsic IntId128,
3378 bit Commutable = 0> {
3379 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3380 (ins VR128:$src1, VR128:$src2),
3381 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3382 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3383 VR128:$src2))]>, OpSize {
3384 let isCommutable = Commutable;
3386 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3387 (ins VR128:$src1, VR128:$src2),
3388 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3389 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3391 let isCommutable = Commutable;
3393 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3394 (ins VR128:$src1, i128mem:$src2),
3395 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3397 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3398 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3399 (ins VR128:$src1, i128mem:$src2),
3400 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3402 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3406 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3407 int_x86_sse41_pmulld, 1>;
3409 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3410 let Constraints = "$src1 = $dst" in {
3411 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3412 Intrinsic IntId128, bit Commutable = 0> {
3413 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3414 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3415 !strconcat(OpcodeStr,
3416 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3418 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3420 let isCommutable = Commutable;
3422 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3423 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3424 !strconcat(OpcodeStr,
3425 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3427 (IntId128 VR128:$src1,
3428 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3433 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3434 int_x86_sse41_blendps, 0>;
3435 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3436 int_x86_sse41_blendpd, 0>;
3437 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3438 int_x86_sse41_pblendw, 0>;
3439 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3440 int_x86_sse41_dpps, 1>;
3441 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3442 int_x86_sse41_dppd, 1>;
3443 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3444 int_x86_sse41_mpsadbw, 1>;
3447 /// SS41I_ternary_int - SSE 4.1 ternary operator
3448 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3449 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3450 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3451 (ins VR128:$src1, VR128:$src2),
3452 !strconcat(OpcodeStr,
3453 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3454 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3457 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3458 (ins VR128:$src1, i128mem:$src2),
3459 !strconcat(OpcodeStr,
3460 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3463 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3467 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3468 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3469 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3472 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3473 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3474 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3475 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3477 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3478 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3480 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3484 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3485 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3486 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3487 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3488 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3489 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3491 // Common patterns involving scalar load.
3492 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3493 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3494 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3495 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3497 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3498 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3499 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3500 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3502 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3503 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3504 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3505 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3507 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3508 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3509 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3510 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3512 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3513 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3514 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3515 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3517 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3518 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3519 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3520 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3523 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3524 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3525 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3526 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3528 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3529 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3531 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3535 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3536 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3537 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3538 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3540 // Common patterns involving scalar load
3541 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3542 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3543 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3544 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3546 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3547 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3548 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3549 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3552 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3553 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3554 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3555 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3557 // Expecting a i16 load any extended to i32 value.
3558 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3559 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3560 [(set VR128:$dst, (IntId (bitconvert
3561 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3565 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3566 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3568 // Common patterns involving scalar load
3569 def : Pat<(int_x86_sse41_pmovsxbq
3570 (bitconvert (v4i32 (X86vzmovl
3571 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3572 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3574 def : Pat<(int_x86_sse41_pmovzxbq
3575 (bitconvert (v4i32 (X86vzmovl
3576 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3577 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3580 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3581 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3582 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3583 (ins VR128:$src1, i32i8imm:$src2),
3584 !strconcat(OpcodeStr,
3585 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3586 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3588 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3589 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3590 !strconcat(OpcodeStr,
3591 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3594 // There's an AssertZext in the way of writing the store pattern
3595 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3598 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3601 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3602 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3603 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3604 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3605 !strconcat(OpcodeStr,
3606 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3609 // There's an AssertZext in the way of writing the store pattern
3610 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3613 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3616 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3617 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3618 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3619 (ins VR128:$src1, i32i8imm:$src2),
3620 !strconcat(OpcodeStr,
3621 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3623 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3624 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3625 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3626 !strconcat(OpcodeStr,
3627 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3628 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3629 addr:$dst)]>, OpSize;
3632 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3635 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3637 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3638 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3639 (ins VR128:$src1, i32i8imm:$src2),
3640 !strconcat(OpcodeStr,
3641 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3643 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3645 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3646 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3647 !strconcat(OpcodeStr,
3648 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3649 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3650 addr:$dst)]>, OpSize;
3653 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3655 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3656 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3659 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3660 Requires<[HasSSE41]>;
3662 let Constraints = "$src1 = $dst" in {
3663 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3664 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3665 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3666 !strconcat(OpcodeStr,
3667 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3669 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3670 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3671 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3672 !strconcat(OpcodeStr,
3673 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3675 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3676 imm:$src3))]>, OpSize;
3680 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3682 let Constraints = "$src1 = $dst" in {
3683 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3684 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3685 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3686 !strconcat(OpcodeStr,
3687 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3689 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3691 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3692 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3693 !strconcat(OpcodeStr,
3694 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3696 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3697 imm:$src3)))]>, OpSize;
3701 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3703 // insertps has a few different modes, there's the first two here below which
3704 // are optimized inserts that won't zero arbitrary elements in the destination
3705 // vector. The next one matches the intrinsic and could zero arbitrary elements
3706 // in the target vector.
3707 let Constraints = "$src1 = $dst" in {
3708 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3709 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3710 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3711 !strconcat(OpcodeStr,
3712 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3714 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3716 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3717 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3718 !strconcat(OpcodeStr,
3719 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3721 (X86insrtps VR128:$src1,
3722 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3723 imm:$src3))]>, OpSize;
3727 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3729 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3730 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3732 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3733 // the intel intrinsic that corresponds to this.
3734 let Defs = [EFLAGS] in {
3735 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3736 "ptest \t{$src2, $src1|$src1, $src2}",
3737 [(X86ptest VR128:$src1, VR128:$src2),
3738 (implicit EFLAGS)]>, OpSize;
3739 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3740 "ptest \t{$src2, $src1|$src1, $src2}",
3741 [(X86ptest VR128:$src1, (load addr:$src2)),
3742 (implicit EFLAGS)]>, OpSize;
3745 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3746 "movntdqa\t{$src, $dst|$dst, $src}",
3747 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3750 //===----------------------------------------------------------------------===//
3751 // SSE4.2 Instructions
3752 //===----------------------------------------------------------------------===//
3754 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3755 let Constraints = "$src1 = $dst" in {
3756 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3757 Intrinsic IntId128, bit Commutable = 0> {
3758 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3759 (ins VR128:$src1, VR128:$src2),
3760 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3761 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3763 let isCommutable = Commutable;
3765 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3766 (ins VR128:$src1, i128mem:$src2),
3767 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3769 (IntId128 VR128:$src1,
3770 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3774 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3776 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3777 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3778 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3779 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3781 // crc intrinsic instruction
3782 // This set of instructions are only rm, the only difference is the size
3784 let Constraints = "$src1 = $dst" in {
3785 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3786 (ins GR32:$src1, i8mem:$src2),
3787 "crc32 \t{$src2, $src1|$src1, $src2}",
3789 (int_x86_sse42_crc32_8 GR32:$src1,
3790 (load addr:$src2)))]>, OpSize;
3791 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3792 (ins GR32:$src1, GR8:$src2),
3793 "crc32 \t{$src2, $src1|$src1, $src2}",
3795 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>,
3797 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3798 (ins GR32:$src1, i16mem:$src2),
3799 "crc32 \t{$src2, $src1|$src1, $src2}",
3801 (int_x86_sse42_crc32_16 GR32:$src1,
3802 (load addr:$src2)))]>,
3804 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3805 (ins GR32:$src1, GR16:$src2),
3806 "crc32 \t{$src2, $src1|$src1, $src2}",
3808 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3810 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3811 (ins GR32:$src1, i32mem:$src2),
3812 "crc32 \t{$src2, $src1|$src1, $src2}",
3814 (int_x86_sse42_crc32_32 GR32:$src1,
3815 (load addr:$src2)))]>, OpSize;
3816 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3817 (ins GR32:$src1, GR32:$src2),
3818 "crc32 \t{$src2, $src1|$src1, $src2}",
3820 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>,
3822 def CRC64m64 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3823 (ins GR64:$src1, i64mem:$src2),
3824 "crc32 \t{$src2, $src1|$src1, $src2}",
3826 (int_x86_sse42_crc32_64 GR64:$src1,
3827 (load addr:$src2)))]>,
3829 def CRC64r64 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3830 (ins GR64:$src1, GR64:$src2),
3831 "crc32 \t{$src2, $src1|$src1, $src2}",
3833 (int_x86_sse42_crc32_64 GR64:$src1, GR64:$src2))]>,
3837 // String/text processing instructions.
3838 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3839 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3840 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3841 "#PCMPISTRM128rr PSEUDO!",
3842 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3843 imm:$src3))]>, OpSize;
3844 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3845 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3846 "#PCMPISTRM128rm PSEUDO!",
3847 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3848 imm:$src3))]>, OpSize;
3851 let Defs = [XMM0, EFLAGS] in {
3852 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3853 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3854 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3855 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3856 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3857 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3860 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3861 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3862 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3863 "#PCMPESTRM128rr PSEUDO!",
3865 (int_x86_sse42_pcmpestrm128
3866 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3868 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3869 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3870 "#PCMPESTRM128rm PSEUDO!",
3871 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3872 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3876 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3877 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3878 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3879 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3880 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3881 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3882 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3885 let Defs = [ECX, EFLAGS] in {
3886 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3887 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3888 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3889 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3890 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3891 (implicit EFLAGS)]>, OpSize;
3892 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3893 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3894 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3895 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3896 (implicit EFLAGS)]>, OpSize;
3900 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3901 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3902 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3903 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3904 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3905 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3907 let Defs = [ECX, EFLAGS] in {
3908 let Uses = [EAX, EDX] in {
3909 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3910 def rr : SS42AI<0x61, MRMSrcReg, (outs),
3911 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3912 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3913 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
3914 (implicit EFLAGS)]>, OpSize;
3915 def rm : SS42AI<0x61, MRMSrcMem, (outs),
3916 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3917 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3919 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
3920 (implicit EFLAGS)]>, OpSize;
3925 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
3926 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
3927 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
3928 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
3929 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
3930 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;