1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
371 // SSE 1 & 2 Instructions Classes
372 //===----------------------------------------------------------------------===//
374 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
375 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
376 RegisterClass RC, X86MemOperand x86memop> {
377 let isCommutable = 1 in {
378 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
379 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
381 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
382 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
385 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
386 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
387 string asm, string SSEVer, string FPSizeStr,
388 Operand memopr, ComplexPattern mem_cpat> {
389 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
390 asm, [(set RC:$dst, (
391 !nameconcat<Intrinsic>("int_x86_sse",
392 !strconcat(SSEVer, !strconcat("_",
393 !strconcat(OpcodeStr, FPSizeStr))))
394 RC:$src1, RC:$src2))]>;
395 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
396 asm, [(set RC:$dst, (
397 !nameconcat<Intrinsic>("int_x86_sse",
398 !strconcat(SSEVer, !strconcat("_",
399 !strconcat(OpcodeStr, FPSizeStr))))
400 RC:$src1, mem_cpat:$src2))]>;
403 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
404 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
405 RegisterClass RC, ValueType vt,
406 X86MemOperand x86memop, PatFrag mem_frag,
407 Domain d, bit MayLoad = 0> {
408 let isCommutable = 1 in
409 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
410 OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
411 let mayLoad = MayLoad in
412 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
413 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
414 (mem_frag addr:$src2)))],d>;
417 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
418 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
419 string OpcodeStr, X86MemOperand x86memop,
420 list<dag> pat_rr, list<dag> pat_rm> {
421 let isCommutable = 1 in
422 def rr : PI<opc, MRMSrcReg, (outs RC:$dst),
423 (ins RC:$src1, RC:$src2), OpcodeStr, pat_rr, d>;
424 def rm : PI<opc, MRMSrcMem, (outs RC:$dst),
425 (ins RC:$src1, x86memop:$src2), OpcodeStr, pat_rm, d>;
428 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
429 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
430 string asm, string SSEVer, string FPSizeStr,
431 X86MemOperand x86memop, PatFrag mem_frag,
433 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
434 asm, [(set RC:$dst, (
435 !nameconcat<Intrinsic>("int_x86_sse",
436 !strconcat(SSEVer, !strconcat("_",
437 !strconcat(OpcodeStr, FPSizeStr))))
438 RC:$src1, RC:$src2))], d>;
439 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
440 asm, [(set RC:$dst, (
441 !nameconcat<Intrinsic>("int_x86_sse",
442 !strconcat(SSEVer, !strconcat("_",
443 !strconcat(OpcodeStr, FPSizeStr))))
444 RC:$src1, (mem_frag addr:$src2)))], d>;
447 /// sse12_unpack_interleave - SSE 1 & 2 unpack and interleave
448 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
449 PatFrag mem_frag, RegisterClass RC,
450 X86MemOperand x86memop, string asm,
452 def rr : PI<opc, MRMSrcReg,
453 (outs RC:$dst), (ins RC:$src1, RC:$src2),
455 (vt (OpNode RC:$src1, RC:$src2)))], d>;
456 def rm : PI<opc, MRMSrcMem,
457 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
459 (vt (OpNode RC:$src1,
460 (mem_frag addr:$src2))))], d>;
463 //===----------------------------------------------------------------------===//
465 //===----------------------------------------------------------------------===//
467 // Conversion Instructions
469 // Match intrinsics which expect XMM operand(s).
470 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
471 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
472 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
473 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
475 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
476 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
477 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
478 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
480 // Aliases for intrinsics
481 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
482 "cvttss2si\t{$src, $dst|$dst, $src}",
484 (int_x86_sse_cvttss2si VR128:$src))]>;
485 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
486 "cvttss2si\t{$src, $dst|$dst, $src}",
488 (int_x86_sse_cvttss2si(load addr:$src)))]>;
490 let Constraints = "$src1 = $dst" in {
491 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
492 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
493 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
494 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
496 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
497 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
498 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
499 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
500 (loadi32 addr:$src2)))]>;
503 // Compare Instructions
504 let Defs = [EFLAGS] in {
505 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
506 "comiss\t{$src2, $src1|$src1, $src2}", []>;
507 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
508 "comiss\t{$src2, $src1|$src1, $src2}", []>;
511 //===----------------------------------------------------------------------===//
512 // SSE 1 & 2 - Move Instructions
513 //===----------------------------------------------------------------------===//
515 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
516 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
517 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
519 // Loading from memory automatically zeroing upper bits.
520 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
521 PatFrag mem_pat, string OpcodeStr> :
522 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
523 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
524 [(set RC:$dst, (mem_pat addr:$src))]>;
526 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
527 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
528 // is used instead. Register-to-register movss/movsd is not modeled as an
529 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
530 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
531 let isAsmParserOnly = 1 in {
532 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
533 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
534 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
535 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
537 let canFoldAsLoad = 1, isReMaterializable = 1 in {
538 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
540 let AddedComplexity = 20 in
541 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
545 let Constraints = "$src1 = $dst" in {
546 def MOVSSrr : sse12_move_rr<FR32, v4f32,
547 "movss\t{$src2, $dst|$dst, $src2}">, XS;
548 def MOVSDrr : sse12_move_rr<FR64, v2f64,
549 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
552 let canFoldAsLoad = 1, isReMaterializable = 1 in {
553 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
555 let AddedComplexity = 20 in
556 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
559 let AddedComplexity = 15 in {
560 // Extract the low 32-bit value from one vector and insert it into another.
561 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
562 (MOVSSrr (v4f32 VR128:$src1),
563 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
564 // Extract the low 64-bit value from one vector and insert it into another.
565 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
566 (MOVSDrr (v2f64 VR128:$src1),
567 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
570 // Implicitly promote a 32-bit scalar to a vector.
571 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
572 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
573 // Implicitly promote a 64-bit scalar to a vector.
574 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
575 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
577 let AddedComplexity = 20 in {
578 // MOVSSrm zeros the high parts of the register; represent this
579 // with SUBREG_TO_REG.
580 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
581 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
582 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
583 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
584 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
585 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
586 // MOVSDrm zeros the high parts of the register; represent this
587 // with SUBREG_TO_REG.
588 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
589 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
590 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
591 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
592 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
593 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
594 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
595 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
596 def : Pat<(v2f64 (X86vzload addr:$src)),
597 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
600 // Store scalar value to memory.
601 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
602 "movss\t{$src, $dst|$dst, $src}",
603 [(store FR32:$src, addr:$dst)]>;
604 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
605 "movsd\t{$src, $dst|$dst, $src}",
606 [(store FR64:$src, addr:$dst)]>;
608 let isAsmParserOnly = 1 in {
609 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
610 "movss\t{$src, $dst|$dst, $src}",
611 [(store FR32:$src, addr:$dst)]>, XS, VEX_4V;
612 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
613 "movsd\t{$src, $dst|$dst, $src}",
614 [(store FR64:$src, addr:$dst)]>, XD, VEX_4V;
617 // Extract and store.
618 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
621 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
622 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
625 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
627 //===----------------------------------------------------------------------===//
628 // SSE 1 & 2 - Conversion Instructions
629 //===----------------------------------------------------------------------===//
631 // Conversion instructions
632 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
633 "cvttss2si\t{$src, $dst|$dst, $src}",
634 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
635 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
636 "cvttss2si\t{$src, $dst|$dst, $src}",
637 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
638 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
639 "cvttsd2si\t{$src, $dst|$dst, $src}",
640 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
641 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
642 "cvttsd2si\t{$src, $dst|$dst, $src}",
643 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
645 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
646 "cvtsi2ss\t{$src, $dst|$dst, $src}",
647 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
648 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
649 "cvtsi2ss\t{$src, $dst|$dst, $src}",
650 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
651 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
652 "cvtsi2sd\t{$src, $dst|$dst, $src}",
653 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
654 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
655 "cvtsi2sd\t{$src, $dst|$dst, $src}",
656 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
658 // Match intrinsics which expect XMM operand(s).
659 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
660 "cvtss2si\t{$src, $dst|$dst, $src}",
661 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
662 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
663 "cvtss2si\t{$src, $dst|$dst, $src}",
664 [(set GR32:$dst, (int_x86_sse_cvtss2si
665 (load addr:$src)))]>;
666 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
667 "cvtsd2si\t{$src, $dst|$dst, $src}",
668 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
669 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
670 "cvtsd2si\t{$src, $dst|$dst, $src}",
671 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
672 (load addr:$src)))]>;
674 // Match intrinsics which expect MM and XMM operand(s).
675 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
676 "cvtps2pi\t{$src, $dst|$dst, $src}",
677 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
678 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
679 "cvtps2pi\t{$src, $dst|$dst, $src}",
680 [(set VR64:$dst, (int_x86_sse_cvtps2pi
681 (load addr:$src)))]>;
682 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
683 "cvtpd2pi\t{$src, $dst|$dst, $src}",
684 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
685 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
686 "cvtpd2pi\t{$src, $dst|$dst, $src}",
687 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
688 (memop addr:$src)))]>;
690 // Match intrinsics which expect MM and XMM operand(s).
691 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
692 "cvttps2pi\t{$src, $dst|$dst, $src}",
693 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
694 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
695 "cvttps2pi\t{$src, $dst|$dst, $src}",
696 [(set VR64:$dst, (int_x86_sse_cvttps2pi
697 (load addr:$src)))]>;
698 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
699 "cvttpd2pi\t{$src, $dst|$dst, $src}",
700 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
701 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
702 "cvttpd2pi\t{$src, $dst|$dst, $src}",
703 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
704 (memop addr:$src)))]>;
706 let Constraints = "$src1 = $dst" in {
707 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
708 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
709 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
710 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
712 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
713 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
714 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
715 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
716 (load addr:$src2)))]>;
719 //===----------------------------------------------------------------------===//
720 // SSE 1 & 2 - Compare Instructions
721 //===----------------------------------------------------------------------===//
723 // Comparison instructions
724 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
725 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
726 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
727 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
729 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
730 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
731 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
733 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
734 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
735 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
737 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
738 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
739 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
741 // Accept explicit immediate argument form instead of comparison code.
742 let isAsmParserOnly = 1 in {
743 def CMPSSrr_alt : SSIi8<0xC2, MRMSrcReg,
744 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
745 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
747 def CMPSSrm_alt : SSIi8<0xC2, MRMSrcMem,
748 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
749 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
751 def CMPSDrr_alt : SDIi8<0xC2, MRMSrcReg,
752 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
753 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
755 def CMPSDrm_alt : SDIi8<0xC2, MRMSrcMem,
756 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
757 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
761 let Defs = [EFLAGS] in {
762 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
763 "ucomiss\t{$src2, $src1|$src1, $src2}",
764 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
765 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
766 "ucomiss\t{$src2, $src1|$src1, $src2}",
767 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
768 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
769 "ucomisd\t{$src2, $src1|$src1, $src2}",
770 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
771 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
772 "ucomisd\t{$src2, $src1|$src1, $src2}",
773 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
776 // Aliases to match intrinsics which expect XMM operand(s).
777 let Constraints = "$src1 = $dst" in {
778 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
780 (ins VR128:$src1, VR128:$src, SSECC:$cc),
781 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
782 [(set VR128:$dst, (int_x86_sse_cmp_ss
784 VR128:$src, imm:$cc))]>;
785 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
787 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
788 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
789 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
790 (load addr:$src), imm:$cc))]>;
792 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
794 (ins VR128:$src1, VR128:$src, SSECC:$cc),
795 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
796 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
797 VR128:$src, imm:$cc))]>;
798 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
800 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
801 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
802 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
803 (load addr:$src), imm:$cc))]>;
806 let Defs = [EFLAGS] in {
807 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
808 "ucomiss\t{$src2, $src1|$src1, $src2}",
809 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
811 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
812 "ucomiss\t{$src2, $src1|$src1, $src2}",
813 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
814 (load addr:$src2)))]>;
815 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
816 "ucomisd\t{$src2, $src1|$src1, $src2}",
817 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
819 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
820 "ucomisd\t{$src2, $src1|$src1, $src2}",
821 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
822 (load addr:$src2)))]>;
824 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
825 "comiss\t{$src2, $src1|$src1, $src2}",
826 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
828 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
829 "comiss\t{$src2, $src1|$src1, $src2}",
830 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
831 (load addr:$src2)))]>;
832 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
833 "comisd\t{$src2, $src1|$src1, $src2}",
834 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
836 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
837 "comisd\t{$src2, $src1|$src1, $src2}",
838 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
839 (load addr:$src2)))]>;
842 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
843 // names that start with 'Fs'.
845 // Alias instructions that map fld0 to pxor for sse.
846 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
847 canFoldAsLoad = 1 in {
848 // FIXME: Set encoding to pseudo!
849 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
850 [(set FR32:$dst, fp32imm0)]>,
851 Requires<[HasSSE1]>, TB, OpSize;
852 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
853 [(set FR64:$dst, fpimm0)]>,
854 Requires<[HasSSE2]>, TB, OpSize;
857 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
858 // bits are disregarded.
859 let neverHasSideEffects = 1 in {
860 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
861 "movaps\t{$src, $dst|$dst, $src}", []>;
862 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
863 "movapd\t{$src, $dst|$dst, $src}", []>;
866 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
867 // bits are disregarded.
868 let canFoldAsLoad = 1, isReMaterializable = 1 in {
869 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
870 "movaps\t{$src, $dst|$dst, $src}",
871 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
872 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
873 "movapd\t{$src, $dst|$dst, $src}",
874 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
877 //===----------------------------------------------------------------------===//
878 // SSE 1 & 2 - Logical Instructions
879 //===----------------------------------------------------------------------===//
881 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
883 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
884 SDNode OpNode, bit MayLoad = 0> {
885 let isAsmParserOnly = 1 in {
886 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
887 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR32,
888 f32, f128mem, memopfsf32, SSEPackedSingle, MayLoad>, VEX_4V;
890 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
891 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR64,
892 f64, f128mem, memopfsf64, SSEPackedDouble, MayLoad>, OpSize,
896 let Constraints = "$src1 = $dst" in {
897 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
898 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, FR32, f32,
899 f128mem, memopfsf32, SSEPackedSingle, MayLoad>, TB;
901 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
902 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, FR64, f64,
903 f128mem, memopfsf64, SSEPackedDouble, MayLoad>, TB, OpSize;
907 // Alias bitwise logical operations using SSE logical ops on packed FP values.
908 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
909 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
910 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
912 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
913 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
915 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
917 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
918 SDNode OpNode, int HasPat = 0,
919 list<list<dag>> Pattern = []> {
920 let isAsmParserOnly = 1 in {
921 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
922 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
924 !if(HasPat, Pattern[0], // rr
925 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
927 !if(HasPat, Pattern[2], // rm
928 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
929 (memopv2i64 addr:$src2)))])>,
932 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
933 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
935 !if(HasPat, Pattern[1], // rr
936 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
939 !if(HasPat, Pattern[3], // rm
940 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
941 (memopv2i64 addr:$src2)))])>,
944 let Constraints = "$src1 = $dst" in {
945 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
946 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), f128mem,
947 !if(HasPat, Pattern[0], // rr
948 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
950 !if(HasPat, Pattern[2], // rm
951 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
952 (memopv2i64 addr:$src2)))])>, TB;
954 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
955 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), f128mem,
956 !if(HasPat, Pattern[1], // rr
957 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
960 !if(HasPat, Pattern[3], // rm
961 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
962 (memopv2i64 addr:$src2)))])>,
967 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
968 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
969 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
970 let isCommutable = 0 in
971 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
973 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
974 (bc_v2i64 (v4i32 immAllOnesV))),
977 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
978 (bc_v2i64 (v2f64 VR128:$src2))))],
980 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
981 (bc_v2i64 (v4i32 immAllOnesV))),
982 (memopv2i64 addr:$src2))))],
984 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
985 (memopv2i64 addr:$src2)))]]>;
987 //===----------------------------------------------------------------------===//
988 // SSE 1 & 2 - Arithmetic Instructions
989 //===----------------------------------------------------------------------===//
991 /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
994 /// In addition, we also have a special variant of the scalar form here to
995 /// represent the associated intrinsic operation. This form is unlike the
996 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
997 /// and leaves the top elements unmodified (therefore these cannot be commuted).
999 /// These three forms can each be reg+reg or reg+mem.
1001 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
1004 let isAsmParserOnly = 1 in {
1005 defm V#NAME#SS : sse12_fp_scalar<opc,
1006 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1007 OpNode, FR32, f32mem>, XS, VEX_4V;
1009 defm V#NAME#SD : sse12_fp_scalar<opc,
1010 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1011 OpNode, FR64, f64mem>, XD, VEX_4V;
1013 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1014 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1015 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
1018 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1019 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1020 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
1023 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1024 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1025 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
1027 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1028 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1029 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
1032 let Constraints = "$src1 = $dst" in {
1033 defm SS : sse12_fp_scalar<opc,
1034 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1035 OpNode, FR32, f32mem>, XS;
1037 defm SD : sse12_fp_scalar<opc,
1038 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1039 OpNode, FR64, f64mem>, XD;
1041 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1042 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
1043 f128mem, memopv4f32, SSEPackedSingle>, TB;
1045 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1046 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
1047 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1049 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1050 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1051 "", "_ss", ssmem, sse_load_f32>, XS;
1053 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1054 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1055 "2", "_sd", sdmem, sse_load_f64>, XD;
1059 // Arithmetic instructions
1060 defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd>;
1061 defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul>;
1063 let isCommutable = 0 in {
1064 defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
1065 defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
1068 /// sse12_fp_binop_rm - Other SSE 1 & 2 binops
1070 /// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
1071 /// instructions for a full-vector intrinsic form. Operations that map
1072 /// onto C operators don't use this form since they just use the plain
1073 /// vector form instead of having a separate vector intrinsic form.
1075 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
1078 let isAsmParserOnly = 1 in {
1079 // Scalar operation, reg+reg.
1080 defm V#NAME#SS : sse12_fp_scalar<opc,
1081 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1082 OpNode, FR32, f32mem>, XS, VEX_4V;
1084 defm V#NAME#SD : sse12_fp_scalar<opc,
1085 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1086 OpNode, FR64, f64mem>, XD, VEX_4V;
1088 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1089 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1090 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
1093 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1094 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1095 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
1098 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1099 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1100 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
1102 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1103 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1104 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
1106 defm V#NAME#PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1107 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1108 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, VEX_4V;
1110 defm V#NAME#PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1111 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1112 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, OpSize,
1116 let Constraints = "$src1 = $dst" in {
1117 // Scalar operation, reg+reg.
1118 defm SS : sse12_fp_scalar<opc,
1119 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1120 OpNode, FR32, f32mem>, XS;
1121 defm SD : sse12_fp_scalar<opc,
1122 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1123 OpNode, FR64, f64mem>, XD;
1124 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1125 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
1126 f128mem, memopv4f32, SSEPackedSingle>, TB;
1128 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1129 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
1130 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1132 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1133 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1134 "", "_ss", ssmem, sse_load_f32>, XS;
1136 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1137 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1138 "2", "_sd", sdmem, sse_load_f64>, XD;
1140 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1141 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
1142 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, TB;
1144 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1145 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1146 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1150 let isCommutable = 0 in {
1151 defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
1152 defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
1155 //===----------------------------------------------------------------------===//
1156 // SSE packed FP Instructions
1158 // Move Instructions
1159 let neverHasSideEffects = 1 in
1160 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1161 "movaps\t{$src, $dst|$dst, $src}", []>;
1162 let canFoldAsLoad = 1, isReMaterializable = 1 in
1163 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1164 "movaps\t{$src, $dst|$dst, $src}",
1165 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
1167 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1168 "movaps\t{$src, $dst|$dst, $src}",
1169 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
1171 let neverHasSideEffects = 1 in
1172 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1173 "movups\t{$src, $dst|$dst, $src}", []>;
1174 let canFoldAsLoad = 1, isReMaterializable = 1 in
1175 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1176 "movups\t{$src, $dst|$dst, $src}",
1177 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
1178 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1179 "movups\t{$src, $dst|$dst, $src}",
1180 [(store (v4f32 VR128:$src), addr:$dst)]>;
1182 // Intrinsic forms of MOVUPS load and store
1183 let canFoldAsLoad = 1, isReMaterializable = 1 in
1184 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1185 "movups\t{$src, $dst|$dst, $src}",
1186 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
1187 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1188 "movups\t{$src, $dst|$dst, $src}",
1189 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
1191 let Constraints = "$src1 = $dst" in {
1192 let AddedComplexity = 20 in {
1193 def MOVLPSrm : PSI<0x12, MRMSrcMem,
1194 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1195 "movlps\t{$src2, $dst|$dst, $src2}",
1198 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
1199 def MOVHPSrm : PSI<0x16, MRMSrcMem,
1200 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1201 "movhps\t{$src2, $dst|$dst, $src2}",
1203 (movlhps VR128:$src1,
1204 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
1205 } // AddedComplexity
1206 } // Constraints = "$src1 = $dst"
1209 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1210 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1212 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1213 "movlps\t{$src, $dst|$dst, $src}",
1214 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1215 (iPTR 0))), addr:$dst)]>;
1217 // v2f64 extract element 1 is always custom lowered to unpack high to low
1218 // and extract element 0 so the non-store version isn't too horrible.
1219 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1220 "movhps\t{$src, $dst|$dst, $src}",
1221 [(store (f64 (vector_extract
1222 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1223 (undef)), (iPTR 0))), addr:$dst)]>;
1225 let Constraints = "$src1 = $dst" in {
1226 let AddedComplexity = 20 in {
1227 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1228 (ins VR128:$src1, VR128:$src2),
1229 "movlhps\t{$src2, $dst|$dst, $src2}",
1231 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1233 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1234 (ins VR128:$src1, VR128:$src2),
1235 "movhlps\t{$src2, $dst|$dst, $src2}",
1237 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1238 } // AddedComplexity
1239 } // Constraints = "$src1 = $dst"
1241 let AddedComplexity = 20 in {
1242 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1243 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1244 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1245 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1252 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
1254 /// In addition, we also have a special variant of the scalar form here to
1255 /// represent the associated intrinsic operation. This form is unlike the
1256 /// plain scalar form, in that it takes an entire vector (instead of a
1257 /// scalar) and leaves the top elements undefined.
1259 /// And, we have a special variant form for a full-vector intrinsic form.
1261 /// These four forms can each have a reg or a mem operand, so there are a
1262 /// total of eight "instructions".
1264 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
1268 bit Commutable = 0> {
1269 // Scalar operation, reg.
1270 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1271 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1272 [(set FR32:$dst, (OpNode FR32:$src))]> {
1273 let isCommutable = Commutable;
1276 // Scalar operation, mem.
1277 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1278 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1279 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1280 Requires<[HasSSE1, OptForSize]>;
1282 // Vector operation, reg.
1283 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1284 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1285 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
1286 let isCommutable = Commutable;
1289 // Vector operation, mem.
1290 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1291 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1292 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1294 // Intrinsic operation, reg.
1295 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1296 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1297 [(set VR128:$dst, (F32Int VR128:$src))]> {
1298 let isCommutable = Commutable;
1301 // Intrinsic operation, mem.
1302 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1303 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1304 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1306 // Vector intrinsic operation, reg
1307 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1308 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1309 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
1310 let isCommutable = Commutable;
1313 // Vector intrinsic operation, mem
1314 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1315 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1316 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1320 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
1321 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
1323 // Reciprocal approximations. Note that these typically require refinement
1324 // in order to obtain suitable precision.
1325 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
1326 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
1327 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
1328 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
1330 let Constraints = "$src1 = $dst" in {
1331 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1332 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1333 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1334 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1335 VR128:$src, imm:$cc))]>;
1336 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1337 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1338 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1339 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1340 (memop addr:$src), imm:$cc))]>;
1341 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1342 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1343 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1344 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1345 VR128:$src, imm:$cc))]>;
1346 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1347 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1348 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1349 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1350 (memop addr:$src), imm:$cc))]>;
1352 // Accept explicit immediate argument form instead of comparison code.
1353 let isAsmParserOnly = 1 in {
1354 def CMPPSrri_alt : PSIi8<0xC2, MRMSrcReg,
1355 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1356 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1357 def CMPPSrmi_alt : PSIi8<0xC2, MRMSrcMem,
1358 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1359 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1360 def CMPPDrri_alt : PDIi8<0xC2, MRMSrcReg,
1361 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1362 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1363 def CMPPDrmi_alt : PDIi8<0xC2, MRMSrcMem,
1364 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1365 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1368 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1369 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1370 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1371 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1372 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1373 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1374 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1375 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1377 // Shuffle and unpack instructions
1378 let Constraints = "$src1 = $dst" in {
1379 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1380 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1381 (outs VR128:$dst), (ins VR128:$src1,
1382 VR128:$src2, i8imm:$src3),
1383 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1385 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1386 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1387 (outs VR128:$dst), (ins VR128:$src1,
1388 f128mem:$src2, i8imm:$src3),
1389 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1392 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1393 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1394 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1395 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1397 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1398 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1399 (outs VR128:$dst), (ins VR128:$src1,
1400 f128mem:$src2, i8imm:$src3),
1401 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1404 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1406 let AddedComplexity = 10 in {
1407 let Constraints = "", isAsmParserOnly = 1 in {
1408 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1409 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1410 SSEPackedSingle>, VEX_4V;
1411 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1412 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1413 SSEPackedDouble>, OpSize, VEX_4V;
1414 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1415 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1416 SSEPackedSingle>, VEX_4V;
1417 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1418 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1419 SSEPackedDouble>, OpSize, VEX_4V;
1421 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1422 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1423 SSEPackedSingle>, TB;
1424 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1425 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1426 SSEPackedDouble>, TB, OpSize;
1427 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1428 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1429 SSEPackedSingle>, TB;
1430 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1431 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1432 SSEPackedDouble>, TB, OpSize;
1433 } // AddedComplexity
1434 } // Constraints = "$src1 = $dst"
1437 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1438 "movmskps\t{$src, $dst|$dst, $src}",
1439 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1440 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1441 "movmskpd\t{$src, $dst|$dst, $src}",
1442 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1444 // Prefetch intrinsic.
1445 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1446 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1447 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1448 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1449 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1450 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1451 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1452 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1454 // Non-temporal stores
1455 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1456 "movntps\t{$src, $dst|$dst, $src}",
1457 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1459 let AddedComplexity = 400 in { // Prefer non-temporal versions
1460 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1461 "movntps\t{$src, $dst|$dst, $src}",
1462 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1464 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1465 "movntdq\t{$src, $dst|$dst, $src}",
1466 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1468 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1469 "movnti\t{$src, $dst|$dst, $src}",
1470 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1471 TB, Requires<[HasSSE2]>;
1473 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1474 "movnti\t{$src, $dst|$dst, $src}",
1475 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1476 TB, Requires<[HasSSE2]>;
1479 // Load, store, and memory fence
1480 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1481 TB, Requires<[HasSSE1]>;
1484 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1485 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1486 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1487 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1489 // Alias instructions that map zero vector to pxor / xorp* for sse.
1490 // We set canFoldAsLoad because this can be converted to a constant-pool
1491 // load of an all-zeros value if folding it would be beneficial.
1492 // FIXME: Change encoding to pseudo!
1493 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1494 isCodeGenOnly = 1 in {
1495 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1496 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1497 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1498 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1499 let ExeDomain = SSEPackedInt in
1500 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1501 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1504 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
1505 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
1506 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
1508 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1509 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1511 //===---------------------------------------------------------------------===//
1512 // SSE2 Instructions
1513 //===---------------------------------------------------------------------===//
1515 // Conversion instructions
1516 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1517 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1518 [(set FR32:$dst, (fround FR64:$src))]>;
1519 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1520 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1521 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1522 Requires<[HasSSE2, OptForSize]>;
1524 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1525 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1526 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1527 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1528 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1529 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1530 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1531 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1533 // SSE2 instructions with XS prefix
1534 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1535 "cvtss2sd\t{$src, $dst|$dst, $src}",
1536 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1537 Requires<[HasSSE2]>;
1538 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1539 "cvtss2sd\t{$src, $dst|$dst, $src}",
1540 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1541 Requires<[HasSSE2, OptForSize]>;
1543 def : Pat<(extloadf32 addr:$src),
1544 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1545 Requires<[HasSSE2, OptForSpeed]>;
1547 // Match intrinsics which expect MM and XMM operand(s).
1548 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1549 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1550 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1551 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1552 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1553 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1554 (load addr:$src)))]>;
1556 // Aliases for intrinsics
1557 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1558 "cvttsd2si\t{$src, $dst|$dst, $src}",
1560 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1561 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1562 "cvttsd2si\t{$src, $dst|$dst, $src}",
1563 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1564 (load addr:$src)))]>;
1566 //===---------------------------------------------------------------------===//
1567 // SSE packed FP Instructions
1569 // Move Instructions
1570 let neverHasSideEffects = 1 in
1571 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1572 "movapd\t{$src, $dst|$dst, $src}", []>;
1573 let canFoldAsLoad = 1, isReMaterializable = 1 in
1574 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1575 "movapd\t{$src, $dst|$dst, $src}",
1576 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1578 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1579 "movapd\t{$src, $dst|$dst, $src}",
1580 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1582 let neverHasSideEffects = 1 in
1583 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1584 "movupd\t{$src, $dst|$dst, $src}", []>;
1585 let canFoldAsLoad = 1 in
1586 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1587 "movupd\t{$src, $dst|$dst, $src}",
1588 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1589 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1590 "movupd\t{$src, $dst|$dst, $src}",
1591 [(store (v2f64 VR128:$src), addr:$dst)]>;
1593 // Intrinsic forms of MOVUPD load and store
1594 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1595 "movupd\t{$src, $dst|$dst, $src}",
1596 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1597 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1598 "movupd\t{$src, $dst|$dst, $src}",
1599 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1601 let Constraints = "$src1 = $dst" in {
1602 let AddedComplexity = 20 in {
1603 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1604 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1605 "movlpd\t{$src2, $dst|$dst, $src2}",
1607 (v2f64 (movlp VR128:$src1,
1608 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1609 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1610 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1611 "movhpd\t{$src2, $dst|$dst, $src2}",
1613 (v2f64 (movlhps VR128:$src1,
1614 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1615 } // AddedComplexity
1616 } // Constraints = "$src1 = $dst"
1618 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1619 "movlpd\t{$src, $dst|$dst, $src}",
1620 [(store (f64 (vector_extract (v2f64 VR128:$src),
1621 (iPTR 0))), addr:$dst)]>;
1623 // v2f64 extract element 1 is always custom lowered to unpack high to low
1624 // and extract element 0 so the non-store version isn't too horrible.
1625 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1626 "movhpd\t{$src, $dst|$dst, $src}",
1627 [(store (f64 (vector_extract
1628 (v2f64 (unpckh VR128:$src, (undef))),
1629 (iPTR 0))), addr:$dst)]>;
1631 // SSE2 instructions without OpSize prefix
1632 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1633 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1634 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1635 TB, Requires<[HasSSE2]>;
1636 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1637 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1638 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1639 (bitconvert (memopv2i64 addr:$src))))]>,
1640 TB, Requires<[HasSSE2]>;
1642 // SSE2 instructions with XS prefix
1643 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1644 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1645 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1646 XS, Requires<[HasSSE2]>;
1647 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1648 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1649 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1650 (bitconvert (memopv2i64 addr:$src))))]>,
1651 XS, Requires<[HasSSE2]>;
1653 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1654 "cvtps2dq\t{$src, $dst|$dst, $src}",
1655 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1656 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1657 "cvtps2dq\t{$src, $dst|$dst, $src}",
1658 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1659 (memop addr:$src)))]>;
1660 // SSE2 packed instructions with XS prefix
1661 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1662 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1663 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1664 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1666 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1667 "cvttps2dq\t{$src, $dst|$dst, $src}",
1669 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1670 XS, Requires<[HasSSE2]>;
1671 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1672 "cvttps2dq\t{$src, $dst|$dst, $src}",
1673 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1674 (memop addr:$src)))]>,
1675 XS, Requires<[HasSSE2]>;
1677 // SSE2 packed instructions with XD prefix
1678 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1679 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1680 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1681 XD, Requires<[HasSSE2]>;
1682 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1683 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1684 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1685 (memop addr:$src)))]>,
1686 XD, Requires<[HasSSE2]>;
1688 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1689 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1690 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1691 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1692 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1693 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1694 (memop addr:$src)))]>;
1696 // SSE2 instructions without OpSize prefix
1697 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1698 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1699 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1700 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1702 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1703 "cvtps2pd\t{$src, $dst|$dst, $src}",
1704 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1705 TB, Requires<[HasSSE2]>;
1706 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1707 "cvtps2pd\t{$src, $dst|$dst, $src}",
1708 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1709 (load addr:$src)))]>,
1710 TB, Requires<[HasSSE2]>;
1712 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1713 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1714 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1715 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1718 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1719 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1720 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1721 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1722 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1723 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1724 (memop addr:$src)))]>;
1726 // Match intrinsics which expect XMM operand(s).
1727 // Aliases for intrinsics
1728 let Constraints = "$src1 = $dst" in {
1729 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1730 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1731 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1732 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1734 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1735 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1736 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1737 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1738 (loadi32 addr:$src2)))]>;
1739 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1740 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1741 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1742 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1744 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1745 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1746 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1747 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1748 (load addr:$src2)))]>;
1749 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1750 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1751 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1752 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1753 VR128:$src2))]>, XS,
1754 Requires<[HasSSE2]>;
1755 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1756 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1757 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1758 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1759 (load addr:$src2)))]>, XS,
1760 Requires<[HasSSE2]>;
1765 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1767 /// In addition, we also have a special variant of the scalar form here to
1768 /// represent the associated intrinsic operation. This form is unlike the
1769 /// plain scalar form, in that it takes an entire vector (instead of a
1770 /// scalar) and leaves the top elements undefined.
1772 /// And, we have a special variant form for a full-vector intrinsic form.
1774 /// These four forms can each have a reg or a mem operand, so there are a
1775 /// total of eight "instructions".
1777 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1781 bit Commutable = 0> {
1782 // Scalar operation, reg.
1783 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1784 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1785 [(set FR64:$dst, (OpNode FR64:$src))]> {
1786 let isCommutable = Commutable;
1789 // Scalar operation, mem.
1790 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1791 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1792 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1794 // Vector operation, reg.
1795 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1796 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1797 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1798 let isCommutable = Commutable;
1801 // Vector operation, mem.
1802 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1803 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1804 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1806 // Intrinsic operation, reg.
1807 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1808 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1809 [(set VR128:$dst, (F64Int VR128:$src))]> {
1810 let isCommutable = Commutable;
1813 // Intrinsic operation, mem.
1814 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1815 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1816 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1818 // Vector intrinsic operation, reg
1819 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1820 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1821 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1822 let isCommutable = Commutable;
1825 // Vector intrinsic operation, mem
1826 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1827 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1828 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1832 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1833 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1835 // There is no f64 version of the reciprocal approximation instructions.
1837 //===---------------------------------------------------------------------===//
1838 // SSE integer instructions
1839 let ExeDomain = SSEPackedInt in {
1841 // Move Instructions
1842 let neverHasSideEffects = 1 in
1843 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1844 "movdqa\t{$src, $dst|$dst, $src}", []>;
1845 let canFoldAsLoad = 1, mayLoad = 1 in
1846 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1847 "movdqa\t{$src, $dst|$dst, $src}",
1848 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1850 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1851 "movdqa\t{$src, $dst|$dst, $src}",
1852 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1853 let canFoldAsLoad = 1, mayLoad = 1 in
1854 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1855 "movdqu\t{$src, $dst|$dst, $src}",
1856 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1857 XS, Requires<[HasSSE2]>;
1859 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1860 "movdqu\t{$src, $dst|$dst, $src}",
1861 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1862 XS, Requires<[HasSSE2]>;
1864 // Intrinsic forms of MOVDQU load and store
1865 let canFoldAsLoad = 1 in
1866 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1867 "movdqu\t{$src, $dst|$dst, $src}",
1868 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1869 XS, Requires<[HasSSE2]>;
1870 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1871 "movdqu\t{$src, $dst|$dst, $src}",
1872 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1873 XS, Requires<[HasSSE2]>;
1875 let Constraints = "$src1 = $dst" in {
1877 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1878 bit Commutable = 0> {
1879 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1880 (ins VR128:$src1, VR128:$src2),
1881 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1882 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1883 let isCommutable = Commutable;
1885 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1886 (ins VR128:$src1, i128mem:$src2),
1887 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1888 [(set VR128:$dst, (IntId VR128:$src1,
1889 (bitconvert (memopv2i64
1893 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1895 Intrinsic IntId, Intrinsic IntId2> {
1896 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1897 (ins VR128:$src1, VR128:$src2),
1898 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1899 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1900 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1901 (ins VR128:$src1, i128mem:$src2),
1902 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1903 [(set VR128:$dst, (IntId VR128:$src1,
1904 (bitconvert (memopv2i64 addr:$src2))))]>;
1905 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
1906 (ins VR128:$src1, i32i8imm:$src2),
1907 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1908 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1911 /// PDI_binop_rm - Simple SSE2 binary operator.
1912 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1913 ValueType OpVT, bit Commutable = 0> {
1914 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1915 (ins VR128:$src1, VR128:$src2),
1916 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1917 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1918 let isCommutable = Commutable;
1920 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1921 (ins VR128:$src1, i128mem:$src2),
1922 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1923 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1924 (bitconvert (memopv2i64 addr:$src2)))))]>;
1927 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1929 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1930 /// to collapse (bitconvert VT to VT) into its operand.
1932 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1933 bit Commutable = 0> {
1934 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1935 (ins VR128:$src1, VR128:$src2),
1936 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1937 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1938 let isCommutable = Commutable;
1940 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1941 (ins VR128:$src1, i128mem:$src2),
1942 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1943 [(set VR128:$dst, (OpNode VR128:$src1,
1944 (memopv2i64 addr:$src2)))]>;
1947 } // Constraints = "$src1 = $dst"
1948 } // ExeDomain = SSEPackedInt
1950 // 128-bit Integer Arithmetic
1952 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1953 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1954 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1955 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1957 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1958 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1959 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1960 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1962 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1963 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1964 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1965 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1967 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1968 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1969 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1970 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1972 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1974 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1975 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1976 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1978 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1980 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1981 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1984 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1985 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1986 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1987 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1988 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
1991 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1992 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1993 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1994 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1995 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1996 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1998 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1999 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2000 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2001 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2002 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2003 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2005 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2006 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2007 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2008 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2010 // 128-bit logical shifts.
2011 let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
2012 ExeDomain = SSEPackedInt in {
2013 def PSLLDQri : PDIi8<0x73, MRM7r,
2014 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2015 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2016 def PSRLDQri : PDIi8<0x73, MRM3r,
2017 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2018 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2019 // PSRADQri doesn't exist in SSE[1-3].
2022 let Predicates = [HasSSE2] in {
2023 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2024 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2025 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2026 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2027 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2028 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2029 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2030 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2031 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2032 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2034 // Shift up / down and insert zero's.
2035 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2036 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2037 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2038 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2042 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2043 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2044 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2046 let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
2047 def PANDNrr : PDI<0xDF, MRMSrcReg,
2048 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2049 "pandn\t{$src2, $dst|$dst, $src2}",
2050 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2053 def PANDNrm : PDI<0xDF, MRMSrcMem,
2054 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2055 "pandn\t{$src2, $dst|$dst, $src2}",
2056 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2057 (memopv2i64 addr:$src2))))]>;
2060 // SSE2 Integer comparison
2061 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2062 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2063 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2064 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2065 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2066 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2068 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2069 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2070 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2071 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2072 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2073 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2074 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2075 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2076 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2077 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2078 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2079 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2081 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2082 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2083 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2084 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2085 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2086 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2087 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2088 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2089 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2090 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2091 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2092 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2095 // Pack instructions
2096 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2097 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2098 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2100 let ExeDomain = SSEPackedInt in {
2102 // Shuffle and unpack instructions
2103 let AddedComplexity = 5 in {
2104 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2105 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2106 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2107 [(set VR128:$dst, (v4i32 (pshufd:$src2
2108 VR128:$src1, (undef))))]>;
2109 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2110 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2111 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2112 [(set VR128:$dst, (v4i32 (pshufd:$src2
2113 (bc_v4i32 (memopv2i64 addr:$src1)),
2117 // SSE2 with ImmT == Imm8 and XS prefix.
2118 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2119 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2120 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2121 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2123 XS, Requires<[HasSSE2]>;
2124 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2125 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2126 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2127 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2128 (bc_v8i16 (memopv2i64 addr:$src1)),
2130 XS, Requires<[HasSSE2]>;
2132 // SSE2 with ImmT == Imm8 and XD prefix.
2133 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2134 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2135 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2136 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2138 XD, Requires<[HasSSE2]>;
2139 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2140 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2141 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2142 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2143 (bc_v8i16 (memopv2i64 addr:$src1)),
2145 XD, Requires<[HasSSE2]>;
2147 // Unpack instructions
2148 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2149 PatFrag unp_frag, PatFrag bc_frag> {
2150 def rr : PDI<opc, MRMSrcReg,
2151 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2152 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2153 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2154 def rm : PDI<opc, MRMSrcMem,
2155 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2156 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2157 [(set VR128:$dst, (unp_frag VR128:$src1,
2158 (bc_frag (memopv2i64
2162 let Constraints = "$src1 = $dst" in {
2163 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2164 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2165 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2167 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2168 /// knew to collapse (bitconvert VT to VT) into its operand.
2169 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2170 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2171 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2173 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2174 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2175 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2176 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2178 (v2i64 (unpckl VR128:$src1,
2179 (memopv2i64 addr:$src2))))]>;
2181 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2182 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2183 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2185 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2186 /// knew to collapse (bitconvert VT to VT) into its operand.
2187 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2188 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2189 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2191 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2192 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2193 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2194 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2196 (v2i64 (unpckh VR128:$src1,
2197 (memopv2i64 addr:$src2))))]>;
2201 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2202 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2203 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2204 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2206 let Constraints = "$src1 = $dst" in {
2207 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2208 (outs VR128:$dst), (ins VR128:$src1,
2209 GR32:$src2, i32i8imm:$src3),
2210 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2212 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2213 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2214 (outs VR128:$dst), (ins VR128:$src1,
2215 i16mem:$src2, i32i8imm:$src3),
2216 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2218 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2223 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2224 "pmovmskb\t{$src, $dst|$dst, $src}",
2225 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2227 // Conditional store
2229 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2230 "maskmovdqu\t{$mask, $src|$src, $mask}",
2231 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2234 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2235 "maskmovdqu\t{$mask, $src|$src, $mask}",
2236 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2238 } // ExeDomain = SSEPackedInt
2240 // Non-temporal stores
2241 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2242 "movntpd\t{$src, $dst|$dst, $src}",
2243 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2244 let ExeDomain = SSEPackedInt in
2245 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2246 "movntdq\t{$src, $dst|$dst, $src}",
2247 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2248 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2249 "movnti\t{$src, $dst|$dst, $src}",
2250 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2251 TB, Requires<[HasSSE2]>;
2253 let AddedComplexity = 400 in { // Prefer non-temporal versions
2254 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2255 "movntpd\t{$src, $dst|$dst, $src}",
2256 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2258 let ExeDomain = SSEPackedInt in
2259 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2260 "movntdq\t{$src, $dst|$dst, $src}",
2261 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2265 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2266 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2267 TB, Requires<[HasSSE2]>;
2269 // Load, store, and memory fence
2270 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2271 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2272 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2273 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2275 // Pause. This "instruction" is encoded as "rep; nop", so even though it
2276 // was introduced with SSE2, it's backward compatible.
2277 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
2279 //TODO: custom lower this so as to never even generate the noop
2280 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2282 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2283 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2284 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2287 // Alias instructions that map zero vector to pxor / xorp* for sse.
2288 // We set canFoldAsLoad because this can be converted to a constant-pool
2289 // load of an all-ones value if folding it would be beneficial.
2290 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2291 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2292 // FIXME: Change encoding to pseudo.
2293 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2294 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2296 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2297 "movd\t{$src, $dst|$dst, $src}",
2299 (v4i32 (scalar_to_vector GR32:$src)))]>;
2300 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2301 "movd\t{$src, $dst|$dst, $src}",
2303 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2305 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2306 "movd\t{$src, $dst|$dst, $src}",
2307 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2309 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2310 "movd\t{$src, $dst|$dst, $src}",
2311 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2313 // SSE2 instructions with XS prefix
2314 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2315 "movq\t{$src, $dst|$dst, $src}",
2317 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2318 Requires<[HasSSE2]>;
2319 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2320 "movq\t{$src, $dst|$dst, $src}",
2321 [(store (i64 (vector_extract (v2i64 VR128:$src),
2322 (iPTR 0))), addr:$dst)]>;
2324 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2325 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2327 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2328 "movd\t{$src, $dst|$dst, $src}",
2329 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2331 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2332 "movd\t{$src, $dst|$dst, $src}",
2333 [(store (i32 (vector_extract (v4i32 VR128:$src),
2334 (iPTR 0))), addr:$dst)]>;
2336 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2337 "movd\t{$src, $dst|$dst, $src}",
2338 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2339 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2340 "movd\t{$src, $dst|$dst, $src}",
2341 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2343 // Store / copy lower 64-bits of a XMM register.
2344 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2345 "movq\t{$src, $dst|$dst, $src}",
2346 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2348 // movd / movq to XMM register zero-extends
2349 let AddedComplexity = 15 in {
2350 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2351 "movd\t{$src, $dst|$dst, $src}",
2352 [(set VR128:$dst, (v4i32 (X86vzmovl
2353 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2354 // This is X86-64 only.
2355 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2356 "mov{d|q}\t{$src, $dst|$dst, $src}",
2357 [(set VR128:$dst, (v2i64 (X86vzmovl
2358 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2361 let AddedComplexity = 20 in {
2362 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2363 "movd\t{$src, $dst|$dst, $src}",
2365 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2366 (loadi32 addr:$src))))))]>;
2368 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2369 (MOVZDI2PDIrm addr:$src)>;
2370 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2371 (MOVZDI2PDIrm addr:$src)>;
2372 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2373 (MOVZDI2PDIrm addr:$src)>;
2375 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2376 "movq\t{$src, $dst|$dst, $src}",
2378 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2379 (loadi64 addr:$src))))))]>, XS,
2380 Requires<[HasSSE2]>;
2382 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2383 (MOVZQI2PQIrm addr:$src)>;
2384 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2385 (MOVZQI2PQIrm addr:$src)>;
2386 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2389 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2390 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2391 let AddedComplexity = 15 in
2392 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2393 "movq\t{$src, $dst|$dst, $src}",
2394 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2395 XS, Requires<[HasSSE2]>;
2397 let AddedComplexity = 20 in {
2398 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2399 "movq\t{$src, $dst|$dst, $src}",
2400 [(set VR128:$dst, (v2i64 (X86vzmovl
2401 (loadv2i64 addr:$src))))]>,
2402 XS, Requires<[HasSSE2]>;
2404 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2405 (MOVZPQILo2PQIrm addr:$src)>;
2408 // Instructions for the disassembler
2409 // xr = XMM register
2412 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2413 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2415 //===---------------------------------------------------------------------===//
2416 // SSE3 Instructions
2417 //===---------------------------------------------------------------------===//
2419 // Conversion Instructions
2420 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2421 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
2422 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2423 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
2424 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2425 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
2426 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2427 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
2429 // Move Instructions
2430 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2431 "movshdup\t{$src, $dst|$dst, $src}",
2432 [(set VR128:$dst, (v4f32 (movshdup
2433 VR128:$src, (undef))))]>;
2434 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2435 "movshdup\t{$src, $dst|$dst, $src}",
2436 [(set VR128:$dst, (movshdup
2437 (memopv4f32 addr:$src), (undef)))]>;
2439 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2440 "movsldup\t{$src, $dst|$dst, $src}",
2441 [(set VR128:$dst, (v4f32 (movsldup
2442 VR128:$src, (undef))))]>;
2443 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2444 "movsldup\t{$src, $dst|$dst, $src}",
2445 [(set VR128:$dst, (movsldup
2446 (memopv4f32 addr:$src), (undef)))]>;
2448 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2449 "movddup\t{$src, $dst|$dst, $src}",
2450 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2451 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2452 "movddup\t{$src, $dst|$dst, $src}",
2454 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2457 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2459 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2461 let AddedComplexity = 5 in {
2462 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2463 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2464 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2465 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2466 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2467 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2468 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2469 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2473 let Constraints = "$src1 = $dst" in {
2474 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2475 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2476 "addsubps\t{$src2, $dst|$dst, $src2}",
2477 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2479 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2480 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2481 "addsubps\t{$src2, $dst|$dst, $src2}",
2482 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2483 (memop addr:$src2)))]>;
2484 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2485 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2486 "addsubpd\t{$src2, $dst|$dst, $src2}",
2487 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2489 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2490 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2491 "addsubpd\t{$src2, $dst|$dst, $src2}",
2492 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2493 (memop addr:$src2)))]>;
2496 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2497 "lddqu\t{$src, $dst|$dst, $src}",
2498 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2501 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2502 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2503 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2504 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2505 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2506 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2507 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2508 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2509 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2510 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2511 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2512 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2513 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2514 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2515 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2516 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2518 let Constraints = "$src1 = $dst" in {
2519 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2520 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2521 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2522 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2523 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2524 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2525 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2526 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2529 // Thread synchronization
2530 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2531 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2532 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2533 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2535 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2536 let AddedComplexity = 15 in
2537 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2538 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2539 let AddedComplexity = 20 in
2540 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2541 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2543 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2544 let AddedComplexity = 15 in
2545 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2546 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2547 let AddedComplexity = 20 in
2548 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2549 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2551 //===---------------------------------------------------------------------===//
2552 // SSSE3 Instructions
2553 //===---------------------------------------------------------------------===//
2555 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2556 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2557 Intrinsic IntId64, Intrinsic IntId128> {
2558 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2559 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2560 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2562 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2563 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2565 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2567 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2569 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2570 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2573 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2578 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2581 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2582 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2583 Intrinsic IntId64, Intrinsic IntId128> {
2584 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2586 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2587 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2589 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2591 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2594 (bitconvert (memopv4i16 addr:$src))))]>;
2596 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2599 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2602 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2604 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2607 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2610 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2611 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2612 Intrinsic IntId64, Intrinsic IntId128> {
2613 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2615 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2616 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2618 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2620 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2623 (bitconvert (memopv2i32 addr:$src))))]>;
2625 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2627 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2628 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2631 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2633 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2636 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2639 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2640 int_x86_ssse3_pabs_b,
2641 int_x86_ssse3_pabs_b_128>;
2642 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2643 int_x86_ssse3_pabs_w,
2644 int_x86_ssse3_pabs_w_128>;
2645 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2646 int_x86_ssse3_pabs_d,
2647 int_x86_ssse3_pabs_d_128>;
2649 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2650 let Constraints = "$src1 = $dst" in {
2651 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2652 Intrinsic IntId64, Intrinsic IntId128,
2653 bit Commutable = 0> {
2654 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2655 (ins VR64:$src1, VR64:$src2),
2656 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2657 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2658 let isCommutable = Commutable;
2660 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2661 (ins VR64:$src1, i64mem:$src2),
2662 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2664 (IntId64 VR64:$src1,
2665 (bitconvert (memopv8i8 addr:$src2))))]>;
2667 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2668 (ins VR128:$src1, VR128:$src2),
2669 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2670 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2672 let isCommutable = Commutable;
2674 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2675 (ins VR128:$src1, i128mem:$src2),
2676 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2678 (IntId128 VR128:$src1,
2679 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2683 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2684 let Constraints = "$src1 = $dst" in {
2685 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2686 Intrinsic IntId64, Intrinsic IntId128,
2687 bit Commutable = 0> {
2688 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2689 (ins VR64:$src1, VR64:$src2),
2690 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2691 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2692 let isCommutable = Commutable;
2694 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2695 (ins VR64:$src1, i64mem:$src2),
2696 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2698 (IntId64 VR64:$src1,
2699 (bitconvert (memopv4i16 addr:$src2))))]>;
2701 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2702 (ins VR128:$src1, VR128:$src2),
2703 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2704 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2706 let isCommutable = Commutable;
2708 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2709 (ins VR128:$src1, i128mem:$src2),
2710 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2712 (IntId128 VR128:$src1,
2713 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2717 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2718 let Constraints = "$src1 = $dst" in {
2719 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2720 Intrinsic IntId64, Intrinsic IntId128,
2721 bit Commutable = 0> {
2722 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2723 (ins VR64:$src1, VR64:$src2),
2724 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2725 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2726 let isCommutable = Commutable;
2728 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2729 (ins VR64:$src1, i64mem:$src2),
2730 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2732 (IntId64 VR64:$src1,
2733 (bitconvert (memopv2i32 addr:$src2))))]>;
2735 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2736 (ins VR128:$src1, VR128:$src2),
2737 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2738 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2740 let isCommutable = Commutable;
2742 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2743 (ins VR128:$src1, i128mem:$src2),
2744 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2746 (IntId128 VR128:$src1,
2747 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2751 let ImmT = NoImm in { // None of these have i8 immediate fields.
2752 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2753 int_x86_ssse3_phadd_w,
2754 int_x86_ssse3_phadd_w_128>;
2755 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2756 int_x86_ssse3_phadd_d,
2757 int_x86_ssse3_phadd_d_128>;
2758 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2759 int_x86_ssse3_phadd_sw,
2760 int_x86_ssse3_phadd_sw_128>;
2761 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2762 int_x86_ssse3_phsub_w,
2763 int_x86_ssse3_phsub_w_128>;
2764 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2765 int_x86_ssse3_phsub_d,
2766 int_x86_ssse3_phsub_d_128>;
2767 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2768 int_x86_ssse3_phsub_sw,
2769 int_x86_ssse3_phsub_sw_128>;
2770 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2771 int_x86_ssse3_pmadd_ub_sw,
2772 int_x86_ssse3_pmadd_ub_sw_128>;
2773 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2774 int_x86_ssse3_pmul_hr_sw,
2775 int_x86_ssse3_pmul_hr_sw_128, 1>;
2777 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2778 int_x86_ssse3_pshuf_b,
2779 int_x86_ssse3_pshuf_b_128>;
2780 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2781 int_x86_ssse3_psign_b,
2782 int_x86_ssse3_psign_b_128>;
2783 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2784 int_x86_ssse3_psign_w,
2785 int_x86_ssse3_psign_w_128>;
2786 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2787 int_x86_ssse3_psign_d,
2788 int_x86_ssse3_psign_d_128>;
2791 // palignr patterns.
2792 let Constraints = "$src1 = $dst" in {
2793 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2794 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2795 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2797 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2798 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2799 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2802 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2803 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2804 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2806 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2807 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2808 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2812 let AddedComplexity = 5 in {
2814 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
2815 (PALIGNR64rr VR64:$src2, VR64:$src1,
2816 (SHUFFLE_get_palign_imm VR64:$src3))>,
2817 Requires<[HasSSSE3]>;
2818 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
2819 (PALIGNR64rr VR64:$src2, VR64:$src1,
2820 (SHUFFLE_get_palign_imm VR64:$src3))>,
2821 Requires<[HasSSSE3]>;
2822 def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
2823 (PALIGNR64rr VR64:$src2, VR64:$src1,
2824 (SHUFFLE_get_palign_imm VR64:$src3))>,
2825 Requires<[HasSSSE3]>;
2826 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
2827 (PALIGNR64rr VR64:$src2, VR64:$src1,
2828 (SHUFFLE_get_palign_imm VR64:$src3))>,
2829 Requires<[HasSSSE3]>;
2830 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
2831 (PALIGNR64rr VR64:$src2, VR64:$src1,
2832 (SHUFFLE_get_palign_imm VR64:$src3))>,
2833 Requires<[HasSSSE3]>;
2835 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2836 (PALIGNR128rr VR128:$src2, VR128:$src1,
2837 (SHUFFLE_get_palign_imm VR128:$src3))>,
2838 Requires<[HasSSSE3]>;
2839 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2840 (PALIGNR128rr VR128:$src2, VR128:$src1,
2841 (SHUFFLE_get_palign_imm VR128:$src3))>,
2842 Requires<[HasSSSE3]>;
2843 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2844 (PALIGNR128rr VR128:$src2, VR128:$src1,
2845 (SHUFFLE_get_palign_imm VR128:$src3))>,
2846 Requires<[HasSSSE3]>;
2847 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2848 (PALIGNR128rr VR128:$src2, VR128:$src1,
2849 (SHUFFLE_get_palign_imm VR128:$src3))>,
2850 Requires<[HasSSSE3]>;
2853 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2854 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2855 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2856 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2858 //===---------------------------------------------------------------------===//
2859 // Non-Instruction Patterns
2860 //===---------------------------------------------------------------------===//
2862 // extload f32 -> f64. This matches load+fextend because we have a hack in
2863 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2865 // Since these loads aren't folded into the fextend, we have to match it
2867 let Predicates = [HasSSE2] in
2868 def : Pat<(fextend (loadf32 addr:$src)),
2869 (CVTSS2SDrm addr:$src)>;
2872 let Predicates = [HasSSE2] in {
2873 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2874 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2875 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2876 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2877 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2878 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2879 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2880 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2881 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2882 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2883 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2884 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2885 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2886 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2887 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2888 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2889 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2890 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2891 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2892 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2893 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2894 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2895 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2896 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2897 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2898 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2899 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2900 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2901 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2902 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2905 // Move scalar to XMM zero-extended
2906 // movd to XMM register zero-extends
2907 let AddedComplexity = 15 in {
2908 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2909 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2910 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
2911 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2912 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
2913 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2914 (MOVSSrr (v4f32 (V_SET0PS)),
2915 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
2916 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2917 (MOVSSrr (v4i32 (V_SET0PI)),
2918 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
2921 // Splat v2f64 / v2i64
2922 let AddedComplexity = 10 in {
2923 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2924 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2925 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
2926 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2927 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
2928 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2929 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
2930 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2933 // Special unary SHUFPSrri case.
2934 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2935 (SHUFPSrri VR128:$src1, VR128:$src1,
2936 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2937 let AddedComplexity = 5 in
2938 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
2939 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2940 Requires<[HasSSE2]>;
2941 // Special unary SHUFPDrri case.
2942 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2943 (SHUFPDrri VR128:$src1, VR128:$src1,
2944 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2945 Requires<[HasSSE2]>;
2946 // Special unary SHUFPDrri case.
2947 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2948 (SHUFPDrri VR128:$src1, VR128:$src1,
2949 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2950 Requires<[HasSSE2]>;
2951 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2952 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
2953 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2954 Requires<[HasSSE2]>;
2956 // Special binary v4i32 shuffle cases with SHUFPS.
2957 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2958 (SHUFPSrri VR128:$src1, VR128:$src2,
2959 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2960 Requires<[HasSSE2]>;
2961 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
2962 (SHUFPSrmi VR128:$src1, addr:$src2,
2963 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2964 Requires<[HasSSE2]>;
2965 // Special binary v2i64 shuffle cases using SHUFPDrri.
2966 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2967 (SHUFPDrri VR128:$src1, VR128:$src2,
2968 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2969 Requires<[HasSSE2]>;
2971 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2972 let AddedComplexity = 15 in {
2973 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
2974 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2975 Requires<[OptForSpeed, HasSSE2]>;
2976 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
2977 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2978 Requires<[OptForSpeed, HasSSE2]>;
2980 let AddedComplexity = 10 in {
2981 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
2982 (UNPCKLPSrr VR128:$src, VR128:$src)>;
2983 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
2984 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
2985 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
2986 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
2987 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
2988 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
2991 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2992 let AddedComplexity = 15 in {
2993 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
2994 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2995 Requires<[OptForSpeed, HasSSE2]>;
2996 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
2997 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2998 Requires<[OptForSpeed, HasSSE2]>;
3000 let AddedComplexity = 10 in {
3001 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3002 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3003 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3004 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3005 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3006 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3007 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3008 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3011 let AddedComplexity = 20 in {
3012 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3013 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3014 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3016 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3017 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3018 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3020 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3021 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3022 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3023 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3024 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3027 let AddedComplexity = 20 in {
3028 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3029 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3030 (MOVLPSrm VR128:$src1, addr:$src2)>;
3031 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3032 (MOVLPDrm VR128:$src1, addr:$src2)>;
3033 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3034 (MOVLPSrm VR128:$src1, addr:$src2)>;
3035 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3036 (MOVLPDrm VR128:$src1, addr:$src2)>;
3039 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3040 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3041 (MOVLPSmr addr:$src1, VR128:$src2)>;
3042 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3043 (MOVLPDmr addr:$src1, VR128:$src2)>;
3044 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3046 (MOVLPSmr addr:$src1, VR128:$src2)>;
3047 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3048 (MOVLPDmr addr:$src1, VR128:$src2)>;
3050 let AddedComplexity = 15 in {
3051 // Setting the lowest element in the vector.
3052 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3053 (MOVSSrr (v4i32 VR128:$src1),
3054 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3055 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3056 (MOVSDrr (v2i64 VR128:$src1),
3057 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3059 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3060 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3061 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3062 Requires<[HasSSE2]>;
3063 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3064 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3065 Requires<[HasSSE2]>;
3068 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3069 // fall back to this for SSE1)
3070 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3071 (SHUFPSrri VR128:$src2, VR128:$src1,
3072 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3074 // Set lowest element and zero upper elements.
3075 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3076 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3078 // Some special case pandn patterns.
3079 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3081 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3082 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3084 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3085 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3087 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3089 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3090 (memop addr:$src2))),
3091 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3092 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3093 (memop addr:$src2))),
3094 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3095 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3096 (memop addr:$src2))),
3097 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3099 // vector -> vector casts
3100 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3101 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3102 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3103 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3104 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3105 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3106 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3107 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3109 // Use movaps / movups for SSE integer load / store (one byte shorter).
3110 def : Pat<(alignedloadv4i32 addr:$src),
3111 (MOVAPSrm addr:$src)>;
3112 def : Pat<(loadv4i32 addr:$src),
3113 (MOVUPSrm addr:$src)>;
3114 def : Pat<(alignedloadv2i64 addr:$src),
3115 (MOVAPSrm addr:$src)>;
3116 def : Pat<(loadv2i64 addr:$src),
3117 (MOVUPSrm addr:$src)>;
3119 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3120 (MOVAPSmr addr:$dst, VR128:$src)>;
3121 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3122 (MOVAPSmr addr:$dst, VR128:$src)>;
3123 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3124 (MOVAPSmr addr:$dst, VR128:$src)>;
3125 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3126 (MOVAPSmr addr:$dst, VR128:$src)>;
3127 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3128 (MOVUPSmr addr:$dst, VR128:$src)>;
3129 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3130 (MOVUPSmr addr:$dst, VR128:$src)>;
3131 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3132 (MOVUPSmr addr:$dst, VR128:$src)>;
3133 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3134 (MOVUPSmr addr:$dst, VR128:$src)>;
3136 //===----------------------------------------------------------------------===//
3137 // SSE4.1 Instructions
3138 //===----------------------------------------------------------------------===//
3140 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3143 Intrinsic V2F64Int> {
3144 // Intrinsic operation, reg.
3145 // Vector intrinsic operation, reg
3146 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3147 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3148 !strconcat(OpcodeStr,
3149 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3150 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3153 // Vector intrinsic operation, mem
3154 def PSm_Int : Ii8<opcps, MRMSrcMem,
3155 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3156 !strconcat(OpcodeStr,
3157 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3159 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3161 Requires<[HasSSE41]>;
3163 // Vector intrinsic operation, reg
3164 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3165 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3166 !strconcat(OpcodeStr,
3167 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3168 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3171 // Vector intrinsic operation, mem
3172 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3173 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3174 !strconcat(OpcodeStr,
3175 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3177 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3181 let Constraints = "$src1 = $dst" in {
3182 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3186 // Intrinsic operation, reg.
3187 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3189 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3190 !strconcat(OpcodeStr,
3191 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3193 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3196 // Intrinsic operation, mem.
3197 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3199 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3200 !strconcat(OpcodeStr,
3201 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3203 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3206 // Intrinsic operation, reg.
3207 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3209 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3210 !strconcat(OpcodeStr,
3211 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3213 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3216 // Intrinsic operation, mem.
3217 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3219 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3220 !strconcat(OpcodeStr,
3221 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3223 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3228 // FP round - roundss, roundps, roundsd, roundpd
3229 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3230 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3231 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3232 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3234 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3235 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3236 Intrinsic IntId128> {
3237 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3239 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3240 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3241 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3243 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3246 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3249 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3250 int_x86_sse41_phminposuw>;
3252 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3253 let Constraints = "$src1 = $dst" in {
3254 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3255 Intrinsic IntId128, bit Commutable = 0> {
3256 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3257 (ins VR128:$src1, VR128:$src2),
3258 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3259 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3261 let isCommutable = Commutable;
3263 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3264 (ins VR128:$src1, i128mem:$src2),
3265 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3267 (IntId128 VR128:$src1,
3268 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3272 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3273 int_x86_sse41_pcmpeqq, 1>;
3274 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3275 int_x86_sse41_packusdw, 0>;
3276 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3277 int_x86_sse41_pminsb, 1>;
3278 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3279 int_x86_sse41_pminsd, 1>;
3280 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3281 int_x86_sse41_pminud, 1>;
3282 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3283 int_x86_sse41_pminuw, 1>;
3284 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3285 int_x86_sse41_pmaxsb, 1>;
3286 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3287 int_x86_sse41_pmaxsd, 1>;
3288 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3289 int_x86_sse41_pmaxud, 1>;
3290 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3291 int_x86_sse41_pmaxuw, 1>;
3293 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3295 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3296 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3297 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3298 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3300 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3301 let Constraints = "$src1 = $dst" in {
3302 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3303 SDNode OpNode, Intrinsic IntId128,
3304 bit Commutable = 0> {
3305 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3306 (ins VR128:$src1, VR128:$src2),
3307 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3308 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3309 VR128:$src2))]>, OpSize {
3310 let isCommutable = Commutable;
3312 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3313 (ins VR128:$src1, VR128:$src2),
3314 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3315 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3317 let isCommutable = Commutable;
3319 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3320 (ins VR128:$src1, i128mem:$src2),
3321 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3323 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3324 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3325 (ins VR128:$src1, i128mem:$src2),
3326 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3328 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3333 /// SS48I_binop_rm - Simple SSE41 binary operator.
3334 let Constraints = "$src1 = $dst" in {
3335 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3336 ValueType OpVT, bit Commutable = 0> {
3337 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3338 (ins VR128:$src1, VR128:$src2),
3339 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3340 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3342 let isCommutable = Commutable;
3344 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3345 (ins VR128:$src1, i128mem:$src2),
3346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3347 [(set VR128:$dst, (OpNode VR128:$src1,
3348 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3353 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3355 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3356 let Constraints = "$src1 = $dst" in {
3357 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3358 Intrinsic IntId128, bit Commutable = 0> {
3359 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3360 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3361 !strconcat(OpcodeStr,
3362 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3364 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3366 let isCommutable = Commutable;
3368 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3369 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3370 !strconcat(OpcodeStr,
3371 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3373 (IntId128 VR128:$src1,
3374 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3379 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3380 int_x86_sse41_blendps, 0>;
3381 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3382 int_x86_sse41_blendpd, 0>;
3383 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3384 int_x86_sse41_pblendw, 0>;
3385 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3386 int_x86_sse41_dpps, 1>;
3387 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3388 int_x86_sse41_dppd, 1>;
3389 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3390 int_x86_sse41_mpsadbw, 0>;
3393 /// SS41I_ternary_int - SSE 4.1 ternary operator
3394 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3395 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3396 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3397 (ins VR128:$src1, VR128:$src2),
3398 !strconcat(OpcodeStr,
3399 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3400 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3403 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3404 (ins VR128:$src1, i128mem:$src2),
3405 !strconcat(OpcodeStr,
3406 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3409 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3413 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3414 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3415 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3418 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3419 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3420 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3421 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3423 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3424 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3426 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3430 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3431 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3432 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3433 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3434 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3435 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3437 // Common patterns involving scalar load.
3438 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3439 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3440 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3441 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3443 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3444 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3445 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3446 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3448 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3449 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3450 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3451 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3453 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3454 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3455 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3456 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3458 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3459 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3460 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3461 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3463 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3464 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3465 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3466 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3469 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3470 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3471 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3472 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3474 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3475 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3477 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3481 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3482 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3483 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3484 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3486 // Common patterns involving scalar load
3487 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3488 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3489 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3490 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3492 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3493 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3494 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3495 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3498 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3499 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3500 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3501 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3503 // Expecting a i16 load any extended to i32 value.
3504 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3505 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3506 [(set VR128:$dst, (IntId (bitconvert
3507 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3511 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3512 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3514 // Common patterns involving scalar load
3515 def : Pat<(int_x86_sse41_pmovsxbq
3516 (bitconvert (v4i32 (X86vzmovl
3517 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3518 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3520 def : Pat<(int_x86_sse41_pmovzxbq
3521 (bitconvert (v4i32 (X86vzmovl
3522 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3523 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3526 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3527 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3528 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3529 (ins VR128:$src1, i32i8imm:$src2),
3530 !strconcat(OpcodeStr,
3531 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3532 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3534 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3535 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3536 !strconcat(OpcodeStr,
3537 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3540 // There's an AssertZext in the way of writing the store pattern
3541 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3544 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3547 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3548 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3549 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3550 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3551 !strconcat(OpcodeStr,
3552 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3555 // There's an AssertZext in the way of writing the store pattern
3556 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3559 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3562 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3563 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3564 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3565 (ins VR128:$src1, i32i8imm:$src2),
3566 !strconcat(OpcodeStr,
3567 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3569 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3570 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3571 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3572 !strconcat(OpcodeStr,
3573 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3574 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3575 addr:$dst)]>, OpSize;
3578 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3581 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3583 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3584 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3585 (ins VR128:$src1, i32i8imm:$src2),
3586 !strconcat(OpcodeStr,
3587 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3589 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3591 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3592 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3593 !strconcat(OpcodeStr,
3594 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3595 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3596 addr:$dst)]>, OpSize;
3599 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3601 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3602 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3605 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3606 Requires<[HasSSE41]>;
3608 let Constraints = "$src1 = $dst" in {
3609 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3610 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3611 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3612 !strconcat(OpcodeStr,
3613 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3615 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3616 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3617 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3618 !strconcat(OpcodeStr,
3619 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3621 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3622 imm:$src3))]>, OpSize;
3626 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3628 let Constraints = "$src1 = $dst" in {
3629 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3630 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3631 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3632 !strconcat(OpcodeStr,
3633 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3635 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3637 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3638 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3639 !strconcat(OpcodeStr,
3640 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3642 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3643 imm:$src3)))]>, OpSize;
3647 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3649 // insertps has a few different modes, there's the first two here below which
3650 // are optimized inserts that won't zero arbitrary elements in the destination
3651 // vector. The next one matches the intrinsic and could zero arbitrary elements
3652 // in the target vector.
3653 let Constraints = "$src1 = $dst" in {
3654 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3655 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3656 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3657 !strconcat(OpcodeStr,
3658 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3660 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3662 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3663 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3664 !strconcat(OpcodeStr,
3665 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3667 (X86insrtps VR128:$src1,
3668 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3669 imm:$src3))]>, OpSize;
3673 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3675 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3676 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3678 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3679 // the intel intrinsic that corresponds to this.
3680 let Defs = [EFLAGS] in {
3681 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3682 "ptest \t{$src2, $src1|$src1, $src2}",
3683 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
3685 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3686 "ptest \t{$src2, $src1|$src1, $src2}",
3687 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
3691 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3692 "movntdqa\t{$src, $dst|$dst, $src}",
3693 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3697 //===----------------------------------------------------------------------===//
3698 // SSE4.2 Instructions
3699 //===----------------------------------------------------------------------===//
3701 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3702 let Constraints = "$src1 = $dst" in {
3703 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3704 Intrinsic IntId128, bit Commutable = 0> {
3705 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3706 (ins VR128:$src1, VR128:$src2),
3707 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3708 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3710 let isCommutable = Commutable;
3712 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3713 (ins VR128:$src1, i128mem:$src2),
3714 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3716 (IntId128 VR128:$src1,
3717 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3721 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3723 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3724 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3725 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3726 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3728 // crc intrinsic instruction
3729 // This set of instructions are only rm, the only difference is the size
3731 let Constraints = "$src1 = $dst" in {
3732 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3733 (ins GR32:$src1, i8mem:$src2),
3734 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3736 (int_x86_sse42_crc32_8 GR32:$src1,
3737 (load addr:$src2)))]>;
3738 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3739 (ins GR32:$src1, GR8:$src2),
3740 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3742 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3743 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3744 (ins GR32:$src1, i16mem:$src2),
3745 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3747 (int_x86_sse42_crc32_16 GR32:$src1,
3748 (load addr:$src2)))]>,
3750 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3751 (ins GR32:$src1, GR16:$src2),
3752 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3754 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3756 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3757 (ins GR32:$src1, i32mem:$src2),
3758 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3760 (int_x86_sse42_crc32_32 GR32:$src1,
3761 (load addr:$src2)))]>;
3762 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3763 (ins GR32:$src1, GR32:$src2),
3764 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3766 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3767 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3768 (ins GR64:$src1, i8mem:$src2),
3769 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3771 (int_x86_sse42_crc64_8 GR64:$src1,
3772 (load addr:$src2)))]>,
3774 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3775 (ins GR64:$src1, GR8:$src2),
3776 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3778 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3780 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3781 (ins GR64:$src1, i64mem:$src2),
3782 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3784 (int_x86_sse42_crc64_64 GR64:$src1,
3785 (load addr:$src2)))]>,
3787 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3788 (ins GR64:$src1, GR64:$src2),
3789 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3791 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3795 // String/text processing instructions.
3796 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3797 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3798 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3799 "#PCMPISTRM128rr PSEUDO!",
3800 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3801 imm:$src3))]>, OpSize;
3802 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3803 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3804 "#PCMPISTRM128rm PSEUDO!",
3805 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3806 imm:$src3))]>, OpSize;
3809 let Defs = [XMM0, EFLAGS] in {
3810 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3811 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3812 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3813 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3814 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3815 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3818 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3819 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3820 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3821 "#PCMPESTRM128rr PSEUDO!",
3823 (int_x86_sse42_pcmpestrm128
3824 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3826 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3827 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3828 "#PCMPESTRM128rm PSEUDO!",
3829 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3830 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3834 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3835 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3836 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3837 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3838 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3839 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3840 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3843 let Defs = [ECX, EFLAGS] in {
3844 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3845 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3846 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3847 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3848 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3849 (implicit EFLAGS)]>, OpSize;
3850 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3851 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3852 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3853 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3854 (implicit EFLAGS)]>, OpSize;
3858 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3859 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3860 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3861 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3862 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3863 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3865 let Defs = [ECX, EFLAGS] in {
3866 let Uses = [EAX, EDX] in {
3867 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3868 def rr : SS42AI<0x61, MRMSrcReg, (outs),
3869 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3870 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3871 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
3872 (implicit EFLAGS)]>, OpSize;
3873 def rm : SS42AI<0x61, MRMSrcMem, (outs),
3874 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3875 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3877 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
3878 (implicit EFLAGS)]>, OpSize;
3883 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
3884 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
3885 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
3886 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
3887 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
3888 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
3890 //===----------------------------------------------------------------------===//
3891 // AES-NI Instructions
3892 //===----------------------------------------------------------------------===//
3894 let Constraints = "$src1 = $dst" in {
3895 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
3896 Intrinsic IntId128, bit Commutable = 0> {
3897 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
3898 (ins VR128:$src1, VR128:$src2),
3899 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3900 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3902 let isCommutable = Commutable;
3904 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
3905 (ins VR128:$src1, i128mem:$src2),
3906 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3908 (IntId128 VR128:$src1,
3909 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3913 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
3914 int_x86_aesni_aesenc>;
3915 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
3916 int_x86_aesni_aesenclast>;
3917 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
3918 int_x86_aesni_aesdec>;
3919 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
3920 int_x86_aesni_aesdeclast>;
3922 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
3923 (AESENCrr VR128:$src1, VR128:$src2)>;
3924 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
3925 (AESENCrm VR128:$src1, addr:$src2)>;
3926 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
3927 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
3928 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
3929 (AESENCLASTrm VR128:$src1, addr:$src2)>;
3930 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
3931 (AESDECrr VR128:$src1, VR128:$src2)>;
3932 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
3933 (AESDECrm VR128:$src1, addr:$src2)>;
3934 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
3935 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
3936 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
3937 (AESDECLASTrm VR128:$src1, addr:$src2)>;
3939 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
3941 "aesimc\t{$src1, $dst|$dst, $src1}",
3943 (int_x86_aesni_aesimc VR128:$src1))]>,
3946 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
3947 (ins i128mem:$src1),
3948 "aesimc\t{$src1, $dst|$dst, $src1}",
3950 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
3953 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
3954 (ins VR128:$src1, i8imm:$src2),
3955 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3957 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
3959 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
3960 (ins i128mem:$src1, i8imm:$src2),
3961 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3963 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),