1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>,
74 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
76 //===----------------------------------------------------------------------===//
77 // SSE Complex Patterns
78 //===----------------------------------------------------------------------===//
80 // These are 'extloads' from a scalar to the low element of a vector, zeroing
81 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
83 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
84 [SDNPHasChain, SDNPMayLoad]>;
85 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
86 [SDNPHasChain, SDNPMayLoad]>;
88 def ssmem : Operand<v4f32> {
89 let PrintMethod = "printf32mem";
90 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
91 let ParserMatchClass = X86MemAsmOperand;
93 def sdmem : Operand<v2f64> {
94 let PrintMethod = "printf64mem";
95 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
96 let ParserMatchClass = X86MemAsmOperand;
99 //===----------------------------------------------------------------------===//
100 // SSE pattern fragments
101 //===----------------------------------------------------------------------===//
103 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
104 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
105 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
106 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
108 // Like 'store', but always requires vector alignment.
109 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
110 (store node:$val, node:$ptr), [{
111 return cast<StoreSDNode>(N)->getAlignment() >= 16;
114 // Like 'load', but always requires vector alignment.
115 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
116 return cast<LoadSDNode>(N)->getAlignment() >= 16;
119 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
120 (f32 (alignedload node:$ptr))>;
121 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
122 (f64 (alignedload node:$ptr))>;
123 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
124 (v4f32 (alignedload node:$ptr))>;
125 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
126 (v2f64 (alignedload node:$ptr))>;
127 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
128 (v4i32 (alignedload node:$ptr))>;
129 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
130 (v2i64 (alignedload node:$ptr))>;
132 // Like 'load', but uses special alignment checks suitable for use in
133 // memory operands in most SSE instructions, which are required to
134 // be naturally aligned on some targets but not on others. If the subtarget
135 // allows unaligned accesses, match any load, though this may require
136 // setting a feature bit in the processor (on startup, for example).
137 // Opteron 10h and later implement such a feature.
138 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
139 return Subtarget->hasVectorUAMem()
140 || cast<LoadSDNode>(N)->getAlignment() >= 16;
143 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
144 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
145 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
146 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
147 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
148 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
149 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
151 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
153 // FIXME: 8 byte alignment for mmx reads is not required
154 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
155 return cast<LoadSDNode>(N)->getAlignment() >= 8;
158 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
159 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
160 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
161 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
164 // Like 'store', but requires the non-temporal bit to be set
165 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
166 (st node:$val, node:$ptr), [{
167 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
168 return ST->isNonTemporal();
172 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
173 (st node:$val, node:$ptr), [{
174 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
175 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
176 ST->getAddressingMode() == ISD::UNINDEXED &&
177 ST->getAlignment() >= 16;
181 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
182 (st node:$val, node:$ptr), [{
183 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
184 return ST->isNonTemporal() &&
185 ST->getAlignment() < 16;
189 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
190 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
191 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
192 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
193 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
194 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
196 def vzmovl_v2i64 : PatFrag<(ops node:$src),
197 (bitconvert (v2i64 (X86vzmovl
198 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
199 def vzmovl_v4i32 : PatFrag<(ops node:$src),
200 (bitconvert (v4i32 (X86vzmovl
201 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
203 def vzload_v2i64 : PatFrag<(ops node:$src),
204 (bitconvert (v2i64 (X86vzload node:$src)))>;
207 def fp32imm0 : PatLeaf<(f32 fpimm), [{
208 return N->isExactlyValue(+0.0);
211 // BYTE_imm - Transform bit immediates into byte immediates.
212 def BYTE_imm : SDNodeXForm<imm, [{
213 // Transformation function: imm >> 3
214 return getI32Imm(N->getZExtValue() >> 3);
217 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
219 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
220 return getI8Imm(X86::getShuffleSHUFImmediate(N));
223 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
225 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
226 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
229 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
231 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
232 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
235 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
237 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
238 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
241 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
242 (vector_shuffle node:$lhs, node:$rhs), [{
243 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
244 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
247 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
248 (vector_shuffle node:$lhs, node:$rhs), [{
249 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
252 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
253 (vector_shuffle node:$lhs, node:$rhs), [{
254 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
257 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
258 (vector_shuffle node:$lhs, node:$rhs), [{
259 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
262 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
263 (vector_shuffle node:$lhs, node:$rhs), [{
264 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
267 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
268 (vector_shuffle node:$lhs, node:$rhs), [{
269 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
272 def movl : PatFrag<(ops node:$lhs, node:$rhs),
273 (vector_shuffle node:$lhs, node:$rhs), [{
274 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
277 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
278 (vector_shuffle node:$lhs, node:$rhs), [{
279 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
282 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
283 (vector_shuffle node:$lhs, node:$rhs), [{
284 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
287 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
288 (vector_shuffle node:$lhs, node:$rhs), [{
289 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
292 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
293 (vector_shuffle node:$lhs, node:$rhs), [{
294 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
297 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
298 (vector_shuffle node:$lhs, node:$rhs), [{
299 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
302 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
303 (vector_shuffle node:$lhs, node:$rhs), [{
304 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
307 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
308 (vector_shuffle node:$lhs, node:$rhs), [{
309 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
310 }], SHUFFLE_get_shuf_imm>;
312 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
313 (vector_shuffle node:$lhs, node:$rhs), [{
314 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
315 }], SHUFFLE_get_shuf_imm>;
317 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
318 (vector_shuffle node:$lhs, node:$rhs), [{
319 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
320 }], SHUFFLE_get_pshufhw_imm>;
322 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
323 (vector_shuffle node:$lhs, node:$rhs), [{
324 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
325 }], SHUFFLE_get_pshuflw_imm>;
327 def palign : PatFrag<(ops node:$lhs, node:$rhs),
328 (vector_shuffle node:$lhs, node:$rhs), [{
329 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
330 }], SHUFFLE_get_palign_imm>;
332 //===----------------------------------------------------------------------===//
333 // SSE scalar FP Instructions
334 //===----------------------------------------------------------------------===//
336 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
337 // instruction selection into a branch sequence.
338 let Uses = [EFLAGS], usesCustomInserter = 1 in {
339 def CMOV_FR32 : I<0, Pseudo,
340 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
341 "#CMOV_FR32 PSEUDO!",
342 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
344 def CMOV_FR64 : I<0, Pseudo,
345 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
346 "#CMOV_FR64 PSEUDO!",
347 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
349 def CMOV_V4F32 : I<0, Pseudo,
350 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
351 "#CMOV_V4F32 PSEUDO!",
353 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
355 def CMOV_V2F64 : I<0, Pseudo,
356 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
357 "#CMOV_V2F64 PSEUDO!",
359 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
361 def CMOV_V2I64 : I<0, Pseudo,
362 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
363 "#CMOV_V2I64 PSEUDO!",
365 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
369 //===----------------------------------------------------------------------===//
371 //===----------------------------------------------------------------------===//
373 // Move Instructions. Register-to-register movss is not used for FR32
374 // register copies because it's a partial register update; FsMOVAPSrr is
375 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
376 // because INSERT_SUBREG requires that the insert be implementable in terms of
377 // a copy, and just mentioned, we don't use movss for copies.
378 let Constraints = "$src1 = $dst" in
379 def MOVSSrr : SSI<0x10, MRMSrcReg,
380 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
381 "movss\t{$src2, $dst|$dst, $src2}",
383 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
385 // Extract the low 32-bit value from one vector and insert it into another.
386 let AddedComplexity = 15 in
387 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
388 (MOVSSrr (v4f32 VR128:$src1),
389 (EXTRACT_SUBREG (v4f32 VR128:$src2), x86_subreg_ss))>;
391 // Implicitly promote a 32-bit scalar to a vector.
392 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
393 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, x86_subreg_ss)>;
395 // Loading from memory automatically zeroing upper bits.
396 let canFoldAsLoad = 1, isReMaterializable = 1 in
397 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
398 "movss\t{$src, $dst|$dst, $src}",
399 [(set FR32:$dst, (loadf32 addr:$src))]>;
401 // MOVSSrm zeros the high parts of the register; represent this
402 // with SUBREG_TO_REG.
403 let AddedComplexity = 20 in {
404 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
405 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
406 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
407 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
408 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
409 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
412 // Store scalar value to memory.
413 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
414 "movss\t{$src, $dst|$dst, $src}",
415 [(store FR32:$src, addr:$dst)]>;
417 // Extract and store.
418 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
421 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
423 // Conversion instructions
424 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
425 "cvttss2si\t{$src, $dst|$dst, $src}",
426 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
427 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
428 "cvttss2si\t{$src, $dst|$dst, $src}",
429 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
430 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
431 "cvtsi2ss\t{$src, $dst|$dst, $src}",
432 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
433 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
434 "cvtsi2ss\t{$src, $dst|$dst, $src}",
435 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
437 // Match intrinsics which expect XMM operand(s).
438 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
439 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
440 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
441 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
443 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
444 "cvtss2si\t{$src, $dst|$dst, $src}",
445 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
446 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
447 "cvtss2si\t{$src, $dst|$dst, $src}",
448 [(set GR32:$dst, (int_x86_sse_cvtss2si
449 (load addr:$src)))]>;
451 // Match intrinisics which expect MM and XMM operand(s).
452 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
453 "cvtps2pi\t{$src, $dst|$dst, $src}",
454 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
455 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
456 "cvtps2pi\t{$src, $dst|$dst, $src}",
457 [(set VR64:$dst, (int_x86_sse_cvtps2pi
458 (load addr:$src)))]>;
459 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
460 "cvttps2pi\t{$src, $dst|$dst, $src}",
461 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
462 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
463 "cvttps2pi\t{$src, $dst|$dst, $src}",
464 [(set VR64:$dst, (int_x86_sse_cvttps2pi
465 (load addr:$src)))]>;
466 let Constraints = "$src1 = $dst" in {
467 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
468 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
469 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
470 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
472 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
473 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
474 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
475 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
476 (load addr:$src2)))]>;
479 // Aliases for intrinsics
480 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
481 "cvttss2si\t{$src, $dst|$dst, $src}",
483 (int_x86_sse_cvttss2si VR128:$src))]>;
484 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
485 "cvttss2si\t{$src, $dst|$dst, $src}",
487 (int_x86_sse_cvttss2si(load addr:$src)))]>;
489 let Constraints = "$src1 = $dst" in {
490 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
491 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
492 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
493 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
495 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
496 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
497 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
498 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
499 (loadi32 addr:$src2)))]>;
502 // Comparison instructions
503 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
504 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
505 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
506 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
508 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
509 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
510 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
513 let Defs = [EFLAGS] in {
514 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
515 "ucomiss\t{$src2, $src1|$src1, $src2}",
516 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
517 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
518 "ucomiss\t{$src2, $src1|$src1, $src2}",
519 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
522 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
523 "comiss\t{$src2, $src1|$src1, $src2}", []>;
524 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
525 "comiss\t{$src2, $src1|$src1, $src2}", []>;
529 // Aliases to match intrinsics which expect XMM operand(s).
530 let Constraints = "$src1 = $dst" in {
531 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
533 (ins VR128:$src1, VR128:$src, SSECC:$cc),
534 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
535 [(set VR128:$dst, (int_x86_sse_cmp_ss
537 VR128:$src, imm:$cc))]>;
538 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
540 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
541 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
542 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
543 (load addr:$src), imm:$cc))]>;
546 let Defs = [EFLAGS] in {
547 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
548 "ucomiss\t{$src2, $src1|$src1, $src2}",
549 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
551 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
552 "ucomiss\t{$src2, $src1|$src1, $src2}",
553 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
556 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
557 "comiss\t{$src2, $src1|$src1, $src2}",
558 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
560 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
561 "comiss\t{$src2, $src1|$src1, $src2}",
562 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
566 // Aliases of packed SSE1 instructions for scalar use. These all have names
567 // that start with 'Fs'.
569 // Alias instructions that map fld0 to pxor for sse.
570 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
572 // FIXME: Set encoding to pseudo!
573 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
574 [(set FR32:$dst, fp32imm0)]>,
575 Requires<[HasSSE1]>, TB, OpSize;
577 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
579 let neverHasSideEffects = 1 in
580 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
581 "movaps\t{$src, $dst|$dst, $src}", []>;
583 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
585 let canFoldAsLoad = 1, isReMaterializable = 1 in
586 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
587 "movaps\t{$src, $dst|$dst, $src}",
588 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
590 // Alias bitwise logical operations using SSE logical ops on packed FP values.
591 let Constraints = "$src1 = $dst" in {
592 let isCommutable = 1 in {
593 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
594 (ins FR32:$src1, FR32:$src2),
595 "andps\t{$src2, $dst|$dst, $src2}",
596 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
597 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
598 (ins FR32:$src1, FR32:$src2),
599 "orps\t{$src2, $dst|$dst, $src2}",
600 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
601 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
602 (ins FR32:$src1, FR32:$src2),
603 "xorps\t{$src2, $dst|$dst, $src2}",
604 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
607 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
608 (ins FR32:$src1, f128mem:$src2),
609 "andps\t{$src2, $dst|$dst, $src2}",
610 [(set FR32:$dst, (X86fand FR32:$src1,
611 (memopfsf32 addr:$src2)))]>;
612 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
613 (ins FR32:$src1, f128mem:$src2),
614 "orps\t{$src2, $dst|$dst, $src2}",
615 [(set FR32:$dst, (X86for FR32:$src1,
616 (memopfsf32 addr:$src2)))]>;
617 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
618 (ins FR32:$src1, f128mem:$src2),
619 "xorps\t{$src2, $dst|$dst, $src2}",
620 [(set FR32:$dst, (X86fxor FR32:$src1,
621 (memopfsf32 addr:$src2)))]>;
623 let neverHasSideEffects = 1 in {
624 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
625 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
626 "andnps\t{$src2, $dst|$dst, $src2}", []>;
628 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
629 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
630 "andnps\t{$src2, $dst|$dst, $src2}", []>;
634 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
636 /// In addition, we also have a special variant of the scalar form here to
637 /// represent the associated intrinsic operation. This form is unlike the
638 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
639 /// and leaves the top elements unmodified (therefore these cannot be commuted).
641 /// These three forms can each be reg+reg or reg+mem, so there are a total of
642 /// six "instructions".
644 let Constraints = "$src1 = $dst" in {
645 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
646 SDNode OpNode, Intrinsic F32Int,
647 bit Commutable = 0> {
648 // Scalar operation, reg+reg.
649 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
650 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
651 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
652 let isCommutable = Commutable;
655 // Scalar operation, reg+mem.
656 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
657 (ins FR32:$src1, f32mem:$src2),
658 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
659 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
661 // Vector operation, reg+reg.
662 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
663 (ins VR128:$src1, VR128:$src2),
664 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
665 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
666 let isCommutable = Commutable;
669 // Vector operation, reg+mem.
670 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
671 (ins VR128:$src1, f128mem:$src2),
672 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
673 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
675 // Intrinsic operation, reg+reg.
676 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
677 (ins VR128:$src1, VR128:$src2),
678 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
679 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
681 // Intrinsic operation, reg+mem.
682 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
683 (ins VR128:$src1, ssmem:$src2),
684 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
685 [(set VR128:$dst, (F32Int VR128:$src1,
686 sse_load_f32:$src2))]>;
690 // Arithmetic instructions
691 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
692 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
693 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
694 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
696 /// sse1_fp_binop_rm - Other SSE1 binops
698 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
699 /// instructions for a full-vector intrinsic form. Operations that map
700 /// onto C operators don't use this form since they just use the plain
701 /// vector form instead of having a separate vector intrinsic form.
703 /// This provides a total of eight "instructions".
705 let Constraints = "$src1 = $dst" in {
706 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
710 bit Commutable = 0> {
712 // Scalar operation, reg+reg.
713 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
714 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
715 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
716 let isCommutable = Commutable;
719 // Scalar operation, reg+mem.
720 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
721 (ins FR32:$src1, f32mem:$src2),
722 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
723 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
725 // Vector operation, reg+reg.
726 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
727 (ins VR128:$src1, VR128:$src2),
728 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
729 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
730 let isCommutable = Commutable;
733 // Vector operation, reg+mem.
734 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
735 (ins VR128:$src1, f128mem:$src2),
736 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
737 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
739 // Intrinsic operation, reg+reg.
740 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
741 (ins VR128:$src1, VR128:$src2),
742 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
743 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
744 let isCommutable = Commutable;
747 // Intrinsic operation, reg+mem.
748 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
749 (ins VR128:$src1, ssmem:$src2),
750 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
751 [(set VR128:$dst, (F32Int VR128:$src1,
752 sse_load_f32:$src2))]>;
754 // Vector intrinsic operation, reg+reg.
755 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
756 (ins VR128:$src1, VR128:$src2),
757 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
758 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
759 let isCommutable = Commutable;
762 // Vector intrinsic operation, reg+mem.
763 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
764 (ins VR128:$src1, f128mem:$src2),
765 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
766 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
770 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
771 int_x86_sse_max_ss, int_x86_sse_max_ps>;
772 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
773 int_x86_sse_min_ss, int_x86_sse_min_ps>;
775 //===----------------------------------------------------------------------===//
776 // SSE packed FP Instructions
779 let neverHasSideEffects = 1 in
780 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
781 "movaps\t{$src, $dst|$dst, $src}", []>;
782 let canFoldAsLoad = 1, isReMaterializable = 1 in
783 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
784 "movaps\t{$src, $dst|$dst, $src}",
785 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
787 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
788 "movaps\t{$src, $dst|$dst, $src}",
789 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
791 let neverHasSideEffects = 1 in
792 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
793 "movups\t{$src, $dst|$dst, $src}", []>;
794 let canFoldAsLoad = 1, isReMaterializable = 1 in
795 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
796 "movups\t{$src, $dst|$dst, $src}",
797 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
798 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
799 "movups\t{$src, $dst|$dst, $src}",
800 [(store (v4f32 VR128:$src), addr:$dst)]>;
802 // Intrinsic forms of MOVUPS load and store
803 let canFoldAsLoad = 1, isReMaterializable = 1 in
804 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
805 "movups\t{$src, $dst|$dst, $src}",
806 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
807 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
808 "movups\t{$src, $dst|$dst, $src}",
809 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
811 let Constraints = "$src1 = $dst" in {
812 let AddedComplexity = 20 in {
813 def MOVLPSrm : PSI<0x12, MRMSrcMem,
814 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
815 "movlps\t{$src2, $dst|$dst, $src2}",
818 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
819 def MOVHPSrm : PSI<0x16, MRMSrcMem,
820 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
821 "movhps\t{$src2, $dst|$dst, $src2}",
823 (movlhps VR128:$src1,
824 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
826 } // Constraints = "$src1 = $dst"
829 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
830 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
832 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
833 "movlps\t{$src, $dst|$dst, $src}",
834 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
835 (iPTR 0))), addr:$dst)]>;
837 // v2f64 extract element 1 is always custom lowered to unpack high to low
838 // and extract element 0 so the non-store version isn't too horrible.
839 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
840 "movhps\t{$src, $dst|$dst, $src}",
841 [(store (f64 (vector_extract
842 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
843 (undef)), (iPTR 0))), addr:$dst)]>;
845 let Constraints = "$src1 = $dst" in {
846 let AddedComplexity = 20 in {
847 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
848 (ins VR128:$src1, VR128:$src2),
849 "movlhps\t{$src2, $dst|$dst, $src2}",
851 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
853 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
854 (ins VR128:$src1, VR128:$src2),
855 "movhlps\t{$src2, $dst|$dst, $src2}",
857 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
859 } // Constraints = "$src1 = $dst"
861 let AddedComplexity = 20 in {
862 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
863 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
864 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
865 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
872 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
874 /// In addition, we also have a special variant of the scalar form here to
875 /// represent the associated intrinsic operation. This form is unlike the
876 /// plain scalar form, in that it takes an entire vector (instead of a
877 /// scalar) and leaves the top elements undefined.
879 /// And, we have a special variant form for a full-vector intrinsic form.
881 /// These four forms can each have a reg or a mem operand, so there are a
882 /// total of eight "instructions".
884 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
888 bit Commutable = 0> {
889 // Scalar operation, reg.
890 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
891 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
892 [(set FR32:$dst, (OpNode FR32:$src))]> {
893 let isCommutable = Commutable;
896 // Scalar operation, mem.
897 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
898 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
899 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
900 Requires<[HasSSE1, OptForSize]>;
902 // Vector operation, reg.
903 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
904 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
905 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
906 let isCommutable = Commutable;
909 // Vector operation, mem.
910 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
911 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
912 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
914 // Intrinsic operation, reg.
915 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
916 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
917 [(set VR128:$dst, (F32Int VR128:$src))]> {
918 let isCommutable = Commutable;
921 // Intrinsic operation, mem.
922 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
923 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
924 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
926 // Vector intrinsic operation, reg
927 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
928 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
929 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
930 let isCommutable = Commutable;
933 // Vector intrinsic operation, mem
934 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
935 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
936 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
940 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
941 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
943 // Reciprocal approximations. Note that these typically require refinement
944 // in order to obtain suitable precision.
945 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
946 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
947 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
948 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
951 let Constraints = "$src1 = $dst" in {
952 let isCommutable = 1 in {
953 def ANDPSrr : PSI<0x54, MRMSrcReg,
954 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
955 "andps\t{$src2, $dst|$dst, $src2}",
956 [(set VR128:$dst, (v2i64
957 (and VR128:$src1, VR128:$src2)))]>;
958 def ORPSrr : PSI<0x56, MRMSrcReg,
959 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
960 "orps\t{$src2, $dst|$dst, $src2}",
961 [(set VR128:$dst, (v2i64
962 (or VR128:$src1, VR128:$src2)))]>;
963 def XORPSrr : PSI<0x57, MRMSrcReg,
964 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
965 "xorps\t{$src2, $dst|$dst, $src2}",
966 [(set VR128:$dst, (v2i64
967 (xor VR128:$src1, VR128:$src2)))]>;
970 def ANDPSrm : PSI<0x54, MRMSrcMem,
971 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
972 "andps\t{$src2, $dst|$dst, $src2}",
973 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
974 (memopv2i64 addr:$src2)))]>;
975 def ORPSrm : PSI<0x56, MRMSrcMem,
976 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
977 "orps\t{$src2, $dst|$dst, $src2}",
978 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
979 (memopv2i64 addr:$src2)))]>;
980 def XORPSrm : PSI<0x57, MRMSrcMem,
981 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
982 "xorps\t{$src2, $dst|$dst, $src2}",
983 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
984 (memopv2i64 addr:$src2)))]>;
985 def ANDNPSrr : PSI<0x55, MRMSrcReg,
986 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
987 "andnps\t{$src2, $dst|$dst, $src2}",
989 (v2i64 (and (xor VR128:$src1,
990 (bc_v2i64 (v4i32 immAllOnesV))),
992 def ANDNPSrm : PSI<0x55, MRMSrcMem,
993 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
994 "andnps\t{$src2, $dst|$dst, $src2}",
996 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
997 (bc_v2i64 (v4i32 immAllOnesV))),
998 (memopv2i64 addr:$src2))))]>;
1001 let Constraints = "$src1 = $dst" in {
1002 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1003 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1004 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1005 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1006 VR128:$src, imm:$cc))]>;
1007 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1008 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1009 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1010 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1011 (memop addr:$src), imm:$cc))]>;
1013 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1014 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1015 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1016 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1018 // Shuffle and unpack instructions
1019 let Constraints = "$src1 = $dst" in {
1020 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1021 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1022 (outs VR128:$dst), (ins VR128:$src1,
1023 VR128:$src2, i8imm:$src3),
1024 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1026 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1027 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1028 (outs VR128:$dst), (ins VR128:$src1,
1029 f128mem:$src2, i8imm:$src3),
1030 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1033 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1035 let AddedComplexity = 10 in {
1036 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1037 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1038 "unpckhps\t{$src2, $dst|$dst, $src2}",
1040 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1041 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1042 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1043 "unpckhps\t{$src2, $dst|$dst, $src2}",
1045 (v4f32 (unpckh VR128:$src1,
1046 (memopv4f32 addr:$src2))))]>;
1048 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1049 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1050 "unpcklps\t{$src2, $dst|$dst, $src2}",
1052 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1053 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1054 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1055 "unpcklps\t{$src2, $dst|$dst, $src2}",
1057 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1058 } // AddedComplexity
1059 } // Constraints = "$src1 = $dst"
1062 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1063 "movmskps\t{$src, $dst|$dst, $src}",
1064 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1065 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1066 "movmskpd\t{$src, $dst|$dst, $src}",
1067 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1069 // Prefetch intrinsic.
1070 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1071 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1072 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1073 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1074 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1075 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1076 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1077 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1079 // Non-temporal stores
1080 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1081 "movntps\t{$src, $dst|$dst, $src}",
1082 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1084 let AddedComplexity = 400 in { // Prefer non-temporal versions
1085 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1086 "movntps\t{$src, $dst|$dst, $src}",
1087 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1089 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1090 "movntdq\t{$src, $dst|$dst, $src}",
1091 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1093 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1094 "movnti\t{$src, $dst|$dst, $src}",
1095 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1096 TB, Requires<[HasSSE2]>;
1098 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1099 "movnti\t{$src, $dst|$dst, $src}",
1100 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1101 TB, Requires<[HasSSE2]>;
1104 // Load, store, and memory fence
1105 def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
1108 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1109 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1110 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1111 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1113 // Alias instructions that map zero vector to pxor / xorp* for sse.
1114 // We set canFoldAsLoad because this can be converted to a constant-pool
1115 // load of an all-zeros value if folding it would be beneficial.
1116 // FIXME: Change encoding to pseudo!
1117 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1118 isCodeGenOnly = 1 in
1119 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1120 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1122 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1123 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1124 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1125 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1126 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1128 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1129 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
1131 //===---------------------------------------------------------------------===//
1132 // SSE2 Instructions
1133 //===---------------------------------------------------------------------===//
1135 // Move Instructions. Register-to-register movsd is not used for FR64
1136 // register copies because it's a partial register update; FsMOVAPDrr is
1137 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1138 // because INSERT_SUBREG requires that the insert be implementable in terms of
1139 // a copy, and just mentioned, we don't use movsd for copies.
1140 let Constraints = "$src1 = $dst" in
1141 def MOVSDrr : SDI<0x10, MRMSrcReg,
1142 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1143 "movsd\t{$src2, $dst|$dst, $src2}",
1145 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1147 // Extract the low 64-bit value from one vector and insert it into another.
1148 let AddedComplexity = 15 in
1149 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1150 (MOVSDrr (v2f64 VR128:$src1),
1151 (EXTRACT_SUBREG (v2f64 VR128:$src2), x86_subreg_sd))>;
1153 // Implicitly promote a 64-bit scalar to a vector.
1154 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1155 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, x86_subreg_sd)>;
1157 // Loading from memory automatically zeroing upper bits.
1158 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1159 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1160 "movsd\t{$src, $dst|$dst, $src}",
1161 [(set FR64:$dst, (loadf64 addr:$src))]>;
1163 // MOVSDrm zeros the high parts of the register; represent this
1164 // with SUBREG_TO_REG.
1165 let AddedComplexity = 20 in {
1166 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1167 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1168 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1169 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1170 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1171 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1172 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1173 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1174 def : Pat<(v2f64 (X86vzload addr:$src)),
1175 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1178 // Store scalar value to memory.
1179 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1180 "movsd\t{$src, $dst|$dst, $src}",
1181 [(store FR64:$src, addr:$dst)]>;
1183 // Extract and store.
1184 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1187 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
1189 // Conversion instructions
1190 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1191 "cvttsd2si\t{$src, $dst|$dst, $src}",
1192 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1193 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1194 "cvttsd2si\t{$src, $dst|$dst, $src}",
1195 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1196 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1197 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1198 [(set FR32:$dst, (fround FR64:$src))]>;
1199 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1200 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1201 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1202 Requires<[HasSSE2, OptForSize]>;
1203 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1204 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1205 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1206 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1207 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1208 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1210 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1211 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1212 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1213 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1214 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1215 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1216 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1217 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1218 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1219 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1220 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1221 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1222 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1223 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1224 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1225 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1226 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1227 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1228 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1229 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1231 // SSE2 instructions with XS prefix
1232 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1233 "cvtss2sd\t{$src, $dst|$dst, $src}",
1234 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1235 Requires<[HasSSE2]>;
1236 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1237 "cvtss2sd\t{$src, $dst|$dst, $src}",
1238 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1239 Requires<[HasSSE2, OptForSize]>;
1241 def : Pat<(extloadf32 addr:$src),
1242 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1243 Requires<[HasSSE2, OptForSpeed]>;
1245 // Match intrinsics which expect XMM operand(s).
1246 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1247 "cvtsd2si\t{$src, $dst|$dst, $src}",
1248 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1249 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1250 "cvtsd2si\t{$src, $dst|$dst, $src}",
1251 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1252 (load addr:$src)))]>;
1254 // Match intrinisics which expect MM and XMM operand(s).
1255 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1256 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1257 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1258 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1259 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1260 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1261 (memop addr:$src)))]>;
1262 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1263 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1264 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1265 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1266 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1267 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1268 (memop addr:$src)))]>;
1269 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1270 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1271 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1272 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1273 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1274 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1275 (load addr:$src)))]>;
1277 // Aliases for intrinsics
1278 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1279 "cvttsd2si\t{$src, $dst|$dst, $src}",
1281 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1282 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1283 "cvttsd2si\t{$src, $dst|$dst, $src}",
1284 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1285 (load addr:$src)))]>;
1287 // Comparison instructions
1288 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1289 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1290 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1291 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1293 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1294 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1295 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1298 let Defs = [EFLAGS] in {
1299 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1300 "ucomisd\t{$src2, $src1|$src1, $src2}",
1301 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1302 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1303 "ucomisd\t{$src2, $src1|$src1, $src2}",
1304 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1305 (implicit EFLAGS)]>;
1306 } // Defs = [EFLAGS]
1308 // Aliases to match intrinsics which expect XMM operand(s).
1309 let Constraints = "$src1 = $dst" in {
1310 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1312 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1313 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1314 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1315 VR128:$src, imm:$cc))]>;
1316 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1318 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1319 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1320 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1321 (load addr:$src), imm:$cc))]>;
1324 let Defs = [EFLAGS] in {
1325 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1326 "ucomisd\t{$src2, $src1|$src1, $src2}",
1327 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1328 (implicit EFLAGS)]>;
1329 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1330 "ucomisd\t{$src2, $src1|$src1, $src2}",
1331 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1332 (implicit EFLAGS)]>;
1334 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1335 "comisd\t{$src2, $src1|$src1, $src2}",
1336 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1337 (implicit EFLAGS)]>;
1338 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1339 "comisd\t{$src2, $src1|$src1, $src2}",
1340 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1341 (implicit EFLAGS)]>;
1342 } // Defs = [EFLAGS]
1344 // Aliases of packed SSE2 instructions for scalar use. These all have names
1345 // that start with 'Fs'.
1347 // Alias instructions that map fld0 to pxor for sse.
1348 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1349 canFoldAsLoad = 1 in
1350 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1351 [(set FR64:$dst, fpimm0)]>,
1352 Requires<[HasSSE2]>, TB, OpSize;
1354 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1356 let neverHasSideEffects = 1 in
1357 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1358 "movapd\t{$src, $dst|$dst, $src}", []>;
1360 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1362 let canFoldAsLoad = 1, isReMaterializable = 1 in
1363 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1364 "movapd\t{$src, $dst|$dst, $src}",
1365 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1367 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1368 let Constraints = "$src1 = $dst" in {
1369 let isCommutable = 1 in {
1370 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1371 (ins FR64:$src1, FR64:$src2),
1372 "andpd\t{$src2, $dst|$dst, $src2}",
1373 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1374 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1375 (ins FR64:$src1, FR64:$src2),
1376 "orpd\t{$src2, $dst|$dst, $src2}",
1377 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1378 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1379 (ins FR64:$src1, FR64:$src2),
1380 "xorpd\t{$src2, $dst|$dst, $src2}",
1381 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1384 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1385 (ins FR64:$src1, f128mem:$src2),
1386 "andpd\t{$src2, $dst|$dst, $src2}",
1387 [(set FR64:$dst, (X86fand FR64:$src1,
1388 (memopfsf64 addr:$src2)))]>;
1389 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1390 (ins FR64:$src1, f128mem:$src2),
1391 "orpd\t{$src2, $dst|$dst, $src2}",
1392 [(set FR64:$dst, (X86for FR64:$src1,
1393 (memopfsf64 addr:$src2)))]>;
1394 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1395 (ins FR64:$src1, f128mem:$src2),
1396 "xorpd\t{$src2, $dst|$dst, $src2}",
1397 [(set FR64:$dst, (X86fxor FR64:$src1,
1398 (memopfsf64 addr:$src2)))]>;
1400 let neverHasSideEffects = 1 in {
1401 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1402 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1403 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1405 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1406 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1407 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1411 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1413 /// In addition, we also have a special variant of the scalar form here to
1414 /// represent the associated intrinsic operation. This form is unlike the
1415 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1416 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1418 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1419 /// six "instructions".
1421 let Constraints = "$src1 = $dst" in {
1422 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1423 SDNode OpNode, Intrinsic F64Int,
1424 bit Commutable = 0> {
1425 // Scalar operation, reg+reg.
1426 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1427 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1428 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1429 let isCommutable = Commutable;
1432 // Scalar operation, reg+mem.
1433 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1434 (ins FR64:$src1, f64mem:$src2),
1435 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1436 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1438 // Vector operation, reg+reg.
1439 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1440 (ins VR128:$src1, VR128:$src2),
1441 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1442 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1443 let isCommutable = Commutable;
1446 // Vector operation, reg+mem.
1447 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1448 (ins VR128:$src1, f128mem:$src2),
1449 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1450 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1452 // Intrinsic operation, reg+reg.
1453 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1454 (ins VR128:$src1, VR128:$src2),
1455 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1456 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1458 // Intrinsic operation, reg+mem.
1459 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1460 (ins VR128:$src1, sdmem:$src2),
1461 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1462 [(set VR128:$dst, (F64Int VR128:$src1,
1463 sse_load_f64:$src2))]>;
1467 // Arithmetic instructions
1468 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1469 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1470 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1471 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1473 /// sse2_fp_binop_rm - Other SSE2 binops
1475 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1476 /// instructions for a full-vector intrinsic form. Operations that map
1477 /// onto C operators don't use this form since they just use the plain
1478 /// vector form instead of having a separate vector intrinsic form.
1480 /// This provides a total of eight "instructions".
1482 let Constraints = "$src1 = $dst" in {
1483 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1487 bit Commutable = 0> {
1489 // Scalar operation, reg+reg.
1490 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1491 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1492 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1493 let isCommutable = Commutable;
1496 // Scalar operation, reg+mem.
1497 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1498 (ins FR64:$src1, f64mem:$src2),
1499 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1500 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1502 // Vector operation, reg+reg.
1503 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1504 (ins VR128:$src1, VR128:$src2),
1505 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1506 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1507 let isCommutable = Commutable;
1510 // Vector operation, reg+mem.
1511 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1512 (ins VR128:$src1, f128mem:$src2),
1513 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1514 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1516 // Intrinsic operation, reg+reg.
1517 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1518 (ins VR128:$src1, VR128:$src2),
1519 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1520 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1521 let isCommutable = Commutable;
1524 // Intrinsic operation, reg+mem.
1525 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1526 (ins VR128:$src1, sdmem:$src2),
1527 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1528 [(set VR128:$dst, (F64Int VR128:$src1,
1529 sse_load_f64:$src2))]>;
1531 // Vector intrinsic operation, reg+reg.
1532 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1533 (ins VR128:$src1, VR128:$src2),
1534 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1535 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1536 let isCommutable = Commutable;
1539 // Vector intrinsic operation, reg+mem.
1540 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1541 (ins VR128:$src1, f128mem:$src2),
1542 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1543 [(set VR128:$dst, (V2F64Int VR128:$src1,
1544 (memopv2f64 addr:$src2)))]>;
1548 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1549 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1550 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1551 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1553 //===---------------------------------------------------------------------===//
1554 // SSE packed FP Instructions
1556 // Move Instructions
1557 let neverHasSideEffects = 1 in
1558 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1559 "movapd\t{$src, $dst|$dst, $src}", []>;
1560 let canFoldAsLoad = 1, isReMaterializable = 1 in
1561 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1562 "movapd\t{$src, $dst|$dst, $src}",
1563 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1565 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1566 "movapd\t{$src, $dst|$dst, $src}",
1567 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1569 let neverHasSideEffects = 1 in
1570 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1571 "movupd\t{$src, $dst|$dst, $src}", []>;
1572 let canFoldAsLoad = 1 in
1573 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1574 "movupd\t{$src, $dst|$dst, $src}",
1575 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1576 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1577 "movupd\t{$src, $dst|$dst, $src}",
1578 [(store (v2f64 VR128:$src), addr:$dst)]>;
1580 // Intrinsic forms of MOVUPD load and store
1581 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1582 "movupd\t{$src, $dst|$dst, $src}",
1583 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1584 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1585 "movupd\t{$src, $dst|$dst, $src}",
1586 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1588 let Constraints = "$src1 = $dst" in {
1589 let AddedComplexity = 20 in {
1590 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1591 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1592 "movlpd\t{$src2, $dst|$dst, $src2}",
1594 (v2f64 (movlp VR128:$src1,
1595 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1596 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1597 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1598 "movhpd\t{$src2, $dst|$dst, $src2}",
1600 (v2f64 (movlhps VR128:$src1,
1601 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1602 } // AddedComplexity
1603 } // Constraints = "$src1 = $dst"
1605 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1606 "movlpd\t{$src, $dst|$dst, $src}",
1607 [(store (f64 (vector_extract (v2f64 VR128:$src),
1608 (iPTR 0))), addr:$dst)]>;
1610 // v2f64 extract element 1 is always custom lowered to unpack high to low
1611 // and extract element 0 so the non-store version isn't too horrible.
1612 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1613 "movhpd\t{$src, $dst|$dst, $src}",
1614 [(store (f64 (vector_extract
1615 (v2f64 (unpckh VR128:$src, (undef))),
1616 (iPTR 0))), addr:$dst)]>;
1618 // SSE2 instructions without OpSize prefix
1619 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1620 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1621 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1622 TB, Requires<[HasSSE2]>;
1623 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1624 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1625 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1626 (bitconvert (memopv2i64 addr:$src))))]>,
1627 TB, Requires<[HasSSE2]>;
1629 // SSE2 instructions with XS prefix
1630 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1631 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1632 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1633 XS, Requires<[HasSSE2]>;
1634 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1635 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1636 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1637 (bitconvert (memopv2i64 addr:$src))))]>,
1638 XS, Requires<[HasSSE2]>;
1640 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1641 "cvtps2dq\t{$src, $dst|$dst, $src}",
1642 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1643 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1644 "cvtps2dq\t{$src, $dst|$dst, $src}",
1645 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1646 (memop addr:$src)))]>;
1647 // SSE2 packed instructions with XS prefix
1648 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1649 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1650 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1651 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1653 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1654 "cvttps2dq\t{$src, $dst|$dst, $src}",
1656 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1657 XS, Requires<[HasSSE2]>;
1658 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1659 "cvttps2dq\t{$src, $dst|$dst, $src}",
1660 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1661 (memop addr:$src)))]>,
1662 XS, Requires<[HasSSE2]>;
1664 // SSE2 packed instructions with XD prefix
1665 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1666 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1667 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1668 XD, Requires<[HasSSE2]>;
1669 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1670 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1671 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1672 (memop addr:$src)))]>,
1673 XD, Requires<[HasSSE2]>;
1675 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1676 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1677 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1678 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1679 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1680 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1681 (memop addr:$src)))]>;
1683 // SSE2 instructions without OpSize prefix
1684 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1685 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1686 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1687 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1689 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1690 "cvtps2pd\t{$src, $dst|$dst, $src}",
1691 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1692 TB, Requires<[HasSSE2]>;
1693 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1694 "cvtps2pd\t{$src, $dst|$dst, $src}",
1695 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1696 (load addr:$src)))]>,
1697 TB, Requires<[HasSSE2]>;
1699 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1700 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1701 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1702 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1705 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1706 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1707 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1708 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1709 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1710 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1711 (memop addr:$src)))]>;
1713 // Match intrinsics which expect XMM operand(s).
1714 // Aliases for intrinsics
1715 let Constraints = "$src1 = $dst" in {
1716 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1717 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1718 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1719 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1721 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1722 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1723 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1724 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1725 (loadi32 addr:$src2)))]>;
1726 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1727 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1728 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1729 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1731 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1732 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1733 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1734 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1735 (load addr:$src2)))]>;
1736 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1737 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1738 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1739 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1740 VR128:$src2))]>, XS,
1741 Requires<[HasSSE2]>;
1742 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1743 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1744 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1745 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1746 (load addr:$src2)))]>, XS,
1747 Requires<[HasSSE2]>;
1752 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1754 /// In addition, we also have a special variant of the scalar form here to
1755 /// represent the associated intrinsic operation. This form is unlike the
1756 /// plain scalar form, in that it takes an entire vector (instead of a
1757 /// scalar) and leaves the top elements undefined.
1759 /// And, we have a special variant form for a full-vector intrinsic form.
1761 /// These four forms can each have a reg or a mem operand, so there are a
1762 /// total of eight "instructions".
1764 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1768 bit Commutable = 0> {
1769 // Scalar operation, reg.
1770 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1771 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1772 [(set FR64:$dst, (OpNode FR64:$src))]> {
1773 let isCommutable = Commutable;
1776 // Scalar operation, mem.
1777 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1778 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1779 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1781 // Vector operation, reg.
1782 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1783 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1784 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1785 let isCommutable = Commutable;
1788 // Vector operation, mem.
1789 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1790 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1791 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1793 // Intrinsic operation, reg.
1794 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1795 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1796 [(set VR128:$dst, (F64Int VR128:$src))]> {
1797 let isCommutable = Commutable;
1800 // Intrinsic operation, mem.
1801 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1802 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1803 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1805 // Vector intrinsic operation, reg
1806 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1807 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1808 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1809 let isCommutable = Commutable;
1812 // Vector intrinsic operation, mem
1813 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1814 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1815 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1819 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1820 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1822 // There is no f64 version of the reciprocal approximation instructions.
1825 let Constraints = "$src1 = $dst" in {
1826 let isCommutable = 1 in {
1827 def ANDPDrr : PDI<0x54, MRMSrcReg,
1828 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1829 "andpd\t{$src2, $dst|$dst, $src2}",
1831 (and (bc_v2i64 (v2f64 VR128:$src1)),
1832 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1833 def ORPDrr : PDI<0x56, MRMSrcReg,
1834 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1835 "orpd\t{$src2, $dst|$dst, $src2}",
1837 (or (bc_v2i64 (v2f64 VR128:$src1)),
1838 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1839 def XORPDrr : PDI<0x57, MRMSrcReg,
1840 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1841 "xorpd\t{$src2, $dst|$dst, $src2}",
1843 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1844 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1847 def ANDPDrm : PDI<0x54, MRMSrcMem,
1848 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1849 "andpd\t{$src2, $dst|$dst, $src2}",
1851 (and (bc_v2i64 (v2f64 VR128:$src1)),
1852 (memopv2i64 addr:$src2)))]>;
1853 def ORPDrm : PDI<0x56, MRMSrcMem,
1854 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1855 "orpd\t{$src2, $dst|$dst, $src2}",
1857 (or (bc_v2i64 (v2f64 VR128:$src1)),
1858 (memopv2i64 addr:$src2)))]>;
1859 def XORPDrm : PDI<0x57, MRMSrcMem,
1860 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1861 "xorpd\t{$src2, $dst|$dst, $src2}",
1863 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1864 (memopv2i64 addr:$src2)))]>;
1865 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 "andnpd\t{$src2, $dst|$dst, $src2}",
1869 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1870 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1871 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1872 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1873 "andnpd\t{$src2, $dst|$dst, $src2}",
1875 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1876 (memopv2i64 addr:$src2)))]>;
1879 let Constraints = "$src1 = $dst" in {
1880 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1881 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1882 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1883 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1884 VR128:$src, imm:$cc))]>;
1885 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1886 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1887 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1888 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1889 (memop addr:$src), imm:$cc))]>;
1891 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1892 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1893 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1894 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1896 // Shuffle and unpack instructions
1897 let Constraints = "$src1 = $dst" in {
1898 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1899 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1900 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1902 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1903 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1904 (outs VR128:$dst), (ins VR128:$src1,
1905 f128mem:$src2, i8imm:$src3),
1906 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1909 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1911 let AddedComplexity = 10 in {
1912 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1913 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1914 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1916 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1917 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1918 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1919 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1921 (v2f64 (unpckh VR128:$src1,
1922 (memopv2f64 addr:$src2))))]>;
1924 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1925 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1926 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1928 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1929 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1930 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1931 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1933 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1934 } // AddedComplexity
1935 } // Constraints = "$src1 = $dst"
1938 //===---------------------------------------------------------------------===//
1939 // SSE integer instructions
1941 // Move Instructions
1942 let neverHasSideEffects = 1 in
1943 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1944 "movdqa\t{$src, $dst|$dst, $src}", []>;
1945 let canFoldAsLoad = 1, mayLoad = 1 in
1946 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1947 "movdqa\t{$src, $dst|$dst, $src}",
1948 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1950 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1951 "movdqa\t{$src, $dst|$dst, $src}",
1952 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1953 let canFoldAsLoad = 1, mayLoad = 1 in
1954 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1955 "movdqu\t{$src, $dst|$dst, $src}",
1956 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1957 XS, Requires<[HasSSE2]>;
1959 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1960 "movdqu\t{$src, $dst|$dst, $src}",
1961 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1962 XS, Requires<[HasSSE2]>;
1964 // Intrinsic forms of MOVDQU load and store
1965 let canFoldAsLoad = 1 in
1966 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1967 "movdqu\t{$src, $dst|$dst, $src}",
1968 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1969 XS, Requires<[HasSSE2]>;
1970 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1971 "movdqu\t{$src, $dst|$dst, $src}",
1972 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1973 XS, Requires<[HasSSE2]>;
1975 let Constraints = "$src1 = $dst" in {
1977 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1978 bit Commutable = 0> {
1979 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1980 (ins VR128:$src1, VR128:$src2),
1981 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1982 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1983 let isCommutable = Commutable;
1985 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1986 (ins VR128:$src1, i128mem:$src2),
1987 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1988 [(set VR128:$dst, (IntId VR128:$src1,
1989 (bitconvert (memopv2i64
1993 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1995 Intrinsic IntId, Intrinsic IntId2> {
1996 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1997 (ins VR128:$src1, VR128:$src2),
1998 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1999 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2000 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2001 (ins VR128:$src1, i128mem:$src2),
2002 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2003 [(set VR128:$dst, (IntId VR128:$src1,
2004 (bitconvert (memopv2i64 addr:$src2))))]>;
2005 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2006 (ins VR128:$src1, i32i8imm:$src2),
2007 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2008 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2011 /// PDI_binop_rm - Simple SSE2 binary operator.
2012 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2013 ValueType OpVT, bit Commutable = 0> {
2014 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2015 (ins VR128:$src1, VR128:$src2),
2016 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2017 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
2018 let isCommutable = Commutable;
2020 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2021 (ins VR128:$src1, i128mem:$src2),
2022 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2023 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2024 (bitconvert (memopv2i64 addr:$src2)))))]>;
2027 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2029 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2030 /// to collapse (bitconvert VT to VT) into its operand.
2032 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2033 bit Commutable = 0> {
2034 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2035 (ins VR128:$src1, VR128:$src2),
2036 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2037 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
2038 let isCommutable = Commutable;
2040 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2041 (ins VR128:$src1, i128mem:$src2),
2042 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2043 [(set VR128:$dst, (OpNode VR128:$src1,
2044 (memopv2i64 addr:$src2)))]>;
2047 } // Constraints = "$src1 = $dst"
2049 // 128-bit Integer Arithmetic
2051 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2052 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2053 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2054 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2056 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2057 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2058 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2059 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2061 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2062 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2063 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2064 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2066 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2067 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2068 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2069 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2071 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2073 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2074 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
2075 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2077 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2079 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2080 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2083 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2084 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2085 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2086 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2087 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2090 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2091 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2092 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2093 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2094 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2095 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2097 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2098 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2099 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2100 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2101 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2102 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2104 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2105 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2106 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2107 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2109 // 128-bit logical shifts.
2110 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
2111 def PSLLDQri : PDIi8<0x73, MRM7r,
2112 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2113 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2114 def PSRLDQri : PDIi8<0x73, MRM3r,
2115 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2116 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2117 // PSRADQri doesn't exist in SSE[1-3].
2120 let Predicates = [HasSSE2] in {
2121 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2122 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2123 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2124 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2125 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2126 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2127 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2128 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2129 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2130 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2132 // Shift up / down and insert zero's.
2133 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2134 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2135 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2136 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2140 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2141 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2142 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2144 let Constraints = "$src1 = $dst" in {
2145 def PANDNrr : PDI<0xDF, MRMSrcReg,
2146 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2147 "pandn\t{$src2, $dst|$dst, $src2}",
2148 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2151 def PANDNrm : PDI<0xDF, MRMSrcMem,
2152 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2153 "pandn\t{$src2, $dst|$dst, $src2}",
2154 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2155 (memopv2i64 addr:$src2))))]>;
2158 // SSE2 Integer comparison
2159 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2160 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2161 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2162 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2163 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2164 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2166 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2167 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2168 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2169 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2170 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2171 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2172 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2173 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2174 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2175 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2176 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2177 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2179 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2180 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2181 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2182 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2183 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2184 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2185 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2186 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2187 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2188 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2189 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2190 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2193 // Pack instructions
2194 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2195 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2196 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2198 // Shuffle and unpack instructions
2199 let AddedComplexity = 5 in {
2200 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2201 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2202 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2203 [(set VR128:$dst, (v4i32 (pshufd:$src2
2204 VR128:$src1, (undef))))]>;
2205 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2206 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2207 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2208 [(set VR128:$dst, (v4i32 (pshufd:$src2
2209 (bc_v4i32 (memopv2i64 addr:$src1)),
2213 // SSE2 with ImmT == Imm8 and XS prefix.
2214 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2215 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2216 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2217 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2219 XS, Requires<[HasSSE2]>;
2220 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2221 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2222 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2223 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2224 (bc_v8i16 (memopv2i64 addr:$src1)),
2226 XS, Requires<[HasSSE2]>;
2228 // SSE2 with ImmT == Imm8 and XD prefix.
2229 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2230 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2231 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2232 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2234 XD, Requires<[HasSSE2]>;
2235 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2236 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2237 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2238 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2239 (bc_v8i16 (memopv2i64 addr:$src1)),
2241 XD, Requires<[HasSSE2]>;
2244 let Constraints = "$src1 = $dst" in {
2245 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2246 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2247 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2249 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2250 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2251 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2252 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2254 (unpckl VR128:$src1,
2255 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2256 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2257 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2258 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2260 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2261 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2262 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2263 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2265 (unpckl VR128:$src1,
2266 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2267 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2268 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2269 "punpckldq\t{$src2, $dst|$dst, $src2}",
2271 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2272 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2273 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2274 "punpckldq\t{$src2, $dst|$dst, $src2}",
2276 (unpckl VR128:$src1,
2277 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2278 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2279 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2280 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2282 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2283 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2284 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2285 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2287 (v2i64 (unpckl VR128:$src1,
2288 (memopv2i64 addr:$src2))))]>;
2290 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2291 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2292 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2294 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2295 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2296 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2297 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2299 (unpckh VR128:$src1,
2300 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2301 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2302 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2303 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2305 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2306 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2307 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2308 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2310 (unpckh VR128:$src1,
2311 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2312 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2313 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2314 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2316 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2317 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2318 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2319 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2321 (unpckh VR128:$src1,
2322 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2323 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2324 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2325 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2327 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2328 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2329 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2330 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2332 (v2i64 (unpckh VR128:$src1,
2333 (memopv2i64 addr:$src2))))]>;
2337 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2338 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2339 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2340 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2342 let Constraints = "$src1 = $dst" in {
2343 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2344 (outs VR128:$dst), (ins VR128:$src1,
2345 GR32:$src2, i32i8imm:$src3),
2346 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2348 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2349 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2350 (outs VR128:$dst), (ins VR128:$src1,
2351 i16mem:$src2, i32i8imm:$src3),
2352 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2354 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2359 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2360 "pmovmskb\t{$src, $dst|$dst, $src}",
2361 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2363 // Conditional store
2365 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2366 "maskmovdqu\t{$mask, $src|$src, $mask}",
2367 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2370 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2371 "maskmovdqu\t{$mask, $src|$src, $mask}",
2372 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2374 // Non-temporal stores
2375 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2376 "movntpd\t{$src, $dst|$dst, $src}",
2377 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2378 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2379 "movntdq\t{$src, $dst|$dst, $src}",
2380 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2381 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2382 "movnti\t{$src, $dst|$dst, $src}",
2383 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2384 TB, Requires<[HasSSE2]>;
2386 let AddedComplexity = 400 in { // Prefer non-temporal versions
2387 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2388 "movntpd\t{$src, $dst|$dst, $src}",
2389 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2391 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2392 "movntdq\t{$src, $dst|$dst, $src}",
2393 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2397 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2398 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2399 TB, Requires<[HasSSE2]>;
2401 // Load, store, and memory fence
2402 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2403 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2404 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2405 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2407 //TODO: custom lower this so as to never even generate the noop
2408 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2410 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2411 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2412 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2415 // Alias instructions that map zero vector to pxor / xorp* for sse.
2416 // We set canFoldAsLoad because this can be converted to a constant-pool
2417 // load of an all-ones value if folding it would be beneficial.
2418 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2419 isCodeGenOnly = 1 in
2420 // FIXME: Change encoding to pseudo.
2421 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2422 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2424 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2425 "movd\t{$src, $dst|$dst, $src}",
2427 (v4i32 (scalar_to_vector GR32:$src)))]>;
2428 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2429 "movd\t{$src, $dst|$dst, $src}",
2431 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2433 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2434 "movd\t{$src, $dst|$dst, $src}",
2435 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2437 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2438 "movd\t{$src, $dst|$dst, $src}",
2439 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2441 // SSE2 instructions with XS prefix
2442 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2443 "movq\t{$src, $dst|$dst, $src}",
2445 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2446 Requires<[HasSSE2]>;
2447 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2448 "movq\t{$src, $dst|$dst, $src}",
2449 [(store (i64 (vector_extract (v2i64 VR128:$src),
2450 (iPTR 0))), addr:$dst)]>;
2452 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2453 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
2455 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2456 "movd\t{$src, $dst|$dst, $src}",
2457 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2459 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2460 "movd\t{$src, $dst|$dst, $src}",
2461 [(store (i32 (vector_extract (v4i32 VR128:$src),
2462 (iPTR 0))), addr:$dst)]>;
2464 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2465 "movd\t{$src, $dst|$dst, $src}",
2466 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2467 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2468 "movd\t{$src, $dst|$dst, $src}",
2469 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2471 // Store / copy lower 64-bits of a XMM register.
2472 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2473 "movq\t{$src, $dst|$dst, $src}",
2474 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2476 // movd / movq to XMM register zero-extends
2477 let AddedComplexity = 15 in {
2478 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2479 "movd\t{$src, $dst|$dst, $src}",
2480 [(set VR128:$dst, (v4i32 (X86vzmovl
2481 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2482 // This is X86-64 only.
2483 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2484 "mov{d|q}\t{$src, $dst|$dst, $src}",
2485 [(set VR128:$dst, (v2i64 (X86vzmovl
2486 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2489 let AddedComplexity = 20 in {
2490 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2491 "movd\t{$src, $dst|$dst, $src}",
2493 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2494 (loadi32 addr:$src))))))]>;
2496 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2497 (MOVZDI2PDIrm addr:$src)>;
2498 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2499 (MOVZDI2PDIrm addr:$src)>;
2500 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2501 (MOVZDI2PDIrm addr:$src)>;
2503 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2504 "movq\t{$src, $dst|$dst, $src}",
2506 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2507 (loadi64 addr:$src))))))]>, XS,
2508 Requires<[HasSSE2]>;
2510 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2511 (MOVZQI2PQIrm addr:$src)>;
2512 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2513 (MOVZQI2PQIrm addr:$src)>;
2514 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2517 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2518 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2519 let AddedComplexity = 15 in
2520 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2521 "movq\t{$src, $dst|$dst, $src}",
2522 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2523 XS, Requires<[HasSSE2]>;
2525 let AddedComplexity = 20 in {
2526 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2527 "movq\t{$src, $dst|$dst, $src}",
2528 [(set VR128:$dst, (v2i64 (X86vzmovl
2529 (loadv2i64 addr:$src))))]>,
2530 XS, Requires<[HasSSE2]>;
2532 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2533 (MOVZPQILo2PQIrm addr:$src)>;
2536 // Instructions for the disassembler
2537 // xr = XMM register
2540 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2541 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2543 //===---------------------------------------------------------------------===//
2544 // SSE3 Instructions
2545 //===---------------------------------------------------------------------===//
2547 // Move Instructions
2548 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2549 "movshdup\t{$src, $dst|$dst, $src}",
2550 [(set VR128:$dst, (v4f32 (movshdup
2551 VR128:$src, (undef))))]>;
2552 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2553 "movshdup\t{$src, $dst|$dst, $src}",
2554 [(set VR128:$dst, (movshdup
2555 (memopv4f32 addr:$src), (undef)))]>;
2557 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2558 "movsldup\t{$src, $dst|$dst, $src}",
2559 [(set VR128:$dst, (v4f32 (movsldup
2560 VR128:$src, (undef))))]>;
2561 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2562 "movsldup\t{$src, $dst|$dst, $src}",
2563 [(set VR128:$dst, (movsldup
2564 (memopv4f32 addr:$src), (undef)))]>;
2566 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2567 "movddup\t{$src, $dst|$dst, $src}",
2568 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2569 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2570 "movddup\t{$src, $dst|$dst, $src}",
2572 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2575 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2577 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2579 let AddedComplexity = 5 in {
2580 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2581 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2582 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2583 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2584 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2585 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2586 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2587 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2591 let Constraints = "$src1 = $dst" in {
2592 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2593 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2594 "addsubps\t{$src2, $dst|$dst, $src2}",
2595 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2597 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2598 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2599 "addsubps\t{$src2, $dst|$dst, $src2}",
2600 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2601 (memop addr:$src2)))]>;
2602 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2603 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2604 "addsubpd\t{$src2, $dst|$dst, $src2}",
2605 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2607 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2608 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2609 "addsubpd\t{$src2, $dst|$dst, $src2}",
2610 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2611 (memop addr:$src2)))]>;
2614 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2615 "lddqu\t{$src, $dst|$dst, $src}",
2616 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2619 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2620 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2621 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2622 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2623 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2624 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2625 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2626 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2627 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2628 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2629 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2630 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2631 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2632 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2633 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2634 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2636 let Constraints = "$src1 = $dst" in {
2637 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2638 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2639 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2640 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2641 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2642 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2643 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2644 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2647 // Thread synchronization
2648 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2649 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2650 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2651 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2653 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2654 let AddedComplexity = 15 in
2655 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2656 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2657 let AddedComplexity = 20 in
2658 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2659 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2661 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2662 let AddedComplexity = 15 in
2663 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2664 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2665 let AddedComplexity = 20 in
2666 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2667 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2669 //===---------------------------------------------------------------------===//
2670 // SSSE3 Instructions
2671 //===---------------------------------------------------------------------===//
2673 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2674 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2675 Intrinsic IntId64, Intrinsic IntId128> {
2676 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2677 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2678 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2680 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2681 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2683 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2685 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2687 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2688 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2691 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2693 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2696 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2699 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2700 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2701 Intrinsic IntId64, Intrinsic IntId128> {
2702 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2704 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2705 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2707 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2709 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2712 (bitconvert (memopv4i16 addr:$src))))]>;
2714 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2716 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2717 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2720 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2722 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2725 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2728 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2729 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2730 Intrinsic IntId64, Intrinsic IntId128> {
2731 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2733 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2734 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2736 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2738 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2741 (bitconvert (memopv2i32 addr:$src))))]>;
2743 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2745 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2746 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2749 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2751 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2754 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2757 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2758 int_x86_ssse3_pabs_b,
2759 int_x86_ssse3_pabs_b_128>;
2760 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2761 int_x86_ssse3_pabs_w,
2762 int_x86_ssse3_pabs_w_128>;
2763 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2764 int_x86_ssse3_pabs_d,
2765 int_x86_ssse3_pabs_d_128>;
2767 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2768 let Constraints = "$src1 = $dst" in {
2769 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2770 Intrinsic IntId64, Intrinsic IntId128,
2771 bit Commutable = 0> {
2772 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2773 (ins VR64:$src1, VR64:$src2),
2774 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2775 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2776 let isCommutable = Commutable;
2778 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2779 (ins VR64:$src1, i64mem:$src2),
2780 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2782 (IntId64 VR64:$src1,
2783 (bitconvert (memopv8i8 addr:$src2))))]>;
2785 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2786 (ins VR128:$src1, VR128:$src2),
2787 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2788 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2790 let isCommutable = Commutable;
2792 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2793 (ins VR128:$src1, i128mem:$src2),
2794 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2796 (IntId128 VR128:$src1,
2797 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2801 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2802 let Constraints = "$src1 = $dst" in {
2803 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2804 Intrinsic IntId64, Intrinsic IntId128,
2805 bit Commutable = 0> {
2806 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2807 (ins VR64:$src1, VR64:$src2),
2808 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2809 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2810 let isCommutable = Commutable;
2812 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2813 (ins VR64:$src1, i64mem:$src2),
2814 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2816 (IntId64 VR64:$src1,
2817 (bitconvert (memopv4i16 addr:$src2))))]>;
2819 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2820 (ins VR128:$src1, VR128:$src2),
2821 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2822 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2824 let isCommutable = Commutable;
2826 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2827 (ins VR128:$src1, i128mem:$src2),
2828 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2830 (IntId128 VR128:$src1,
2831 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2835 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2836 let Constraints = "$src1 = $dst" in {
2837 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2838 Intrinsic IntId64, Intrinsic IntId128,
2839 bit Commutable = 0> {
2840 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2841 (ins VR64:$src1, VR64:$src2),
2842 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2843 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2844 let isCommutable = Commutable;
2846 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2847 (ins VR64:$src1, i64mem:$src2),
2848 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2850 (IntId64 VR64:$src1,
2851 (bitconvert (memopv2i32 addr:$src2))))]>;
2853 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2854 (ins VR128:$src1, VR128:$src2),
2855 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2856 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2858 let isCommutable = Commutable;
2860 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2861 (ins VR128:$src1, i128mem:$src2),
2862 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2864 (IntId128 VR128:$src1,
2865 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2869 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2870 int_x86_ssse3_phadd_w,
2871 int_x86_ssse3_phadd_w_128>;
2872 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2873 int_x86_ssse3_phadd_d,
2874 int_x86_ssse3_phadd_d_128>;
2875 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2876 int_x86_ssse3_phadd_sw,
2877 int_x86_ssse3_phadd_sw_128>;
2878 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2879 int_x86_ssse3_phsub_w,
2880 int_x86_ssse3_phsub_w_128>;
2881 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2882 int_x86_ssse3_phsub_d,
2883 int_x86_ssse3_phsub_d_128>;
2884 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2885 int_x86_ssse3_phsub_sw,
2886 int_x86_ssse3_phsub_sw_128>;
2887 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2888 int_x86_ssse3_pmadd_ub_sw,
2889 int_x86_ssse3_pmadd_ub_sw_128>;
2890 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2891 int_x86_ssse3_pmul_hr_sw,
2892 int_x86_ssse3_pmul_hr_sw_128, 1>;
2893 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2894 int_x86_ssse3_pshuf_b,
2895 int_x86_ssse3_pshuf_b_128>;
2896 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2897 int_x86_ssse3_psign_b,
2898 int_x86_ssse3_psign_b_128>;
2899 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2900 int_x86_ssse3_psign_w,
2901 int_x86_ssse3_psign_w_128>;
2902 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2903 int_x86_ssse3_psign_d,
2904 int_x86_ssse3_psign_d_128>;
2906 let Constraints = "$src1 = $dst" in {
2907 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2908 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2909 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2911 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2912 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2913 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2916 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2917 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2918 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2920 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2921 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2922 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2926 // palignr patterns.
2927 def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)),
2928 (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>,
2929 Requires<[HasSSSE3]>;
2930 def : Pat<(int_x86_ssse3_palign_r VR64:$src1,
2931 (memop64 addr:$src2),
2933 (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2934 Requires<[HasSSSE3]>;
2936 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)),
2937 (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>,
2938 Requires<[HasSSSE3]>;
2939 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1,
2940 (memopv2i64 addr:$src2),
2942 (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2943 Requires<[HasSSSE3]>;
2945 let AddedComplexity = 5 in {
2946 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2947 (PALIGNR128rr VR128:$src2, VR128:$src1,
2948 (SHUFFLE_get_palign_imm VR128:$src3))>,
2949 Requires<[HasSSSE3]>;
2950 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2951 (PALIGNR128rr VR128:$src2, VR128:$src1,
2952 (SHUFFLE_get_palign_imm VR128:$src3))>,
2953 Requires<[HasSSSE3]>;
2954 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2955 (PALIGNR128rr VR128:$src2, VR128:$src1,
2956 (SHUFFLE_get_palign_imm VR128:$src3))>,
2957 Requires<[HasSSSE3]>;
2958 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2959 (PALIGNR128rr VR128:$src2, VR128:$src1,
2960 (SHUFFLE_get_palign_imm VR128:$src3))>,
2961 Requires<[HasSSSE3]>;
2964 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2965 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2966 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2967 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2969 //===---------------------------------------------------------------------===//
2970 // Non-Instruction Patterns
2971 //===---------------------------------------------------------------------===//
2973 // extload f32 -> f64. This matches load+fextend because we have a hack in
2974 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2976 // Since these loads aren't folded into the fextend, we have to match it
2978 let Predicates = [HasSSE2] in
2979 def : Pat<(fextend (loadf32 addr:$src)),
2980 (CVTSS2SDrm addr:$src)>;
2983 let Predicates = [HasSSE2] in {
2984 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2985 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2986 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2987 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2988 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2989 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2990 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2991 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2992 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2993 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2994 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2995 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2996 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2997 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2998 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2999 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3000 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3001 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3002 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3003 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3004 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3005 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3006 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3007 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3008 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3009 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3010 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3011 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3012 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3013 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3016 // Move scalar to XMM zero-extended
3017 // movd to XMM register zero-extends
3018 let AddedComplexity = 15 in {
3019 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3020 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3021 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
3022 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3023 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
3024 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3025 (MOVSSrr (v4f32 (V_SET0)),
3026 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss)))>;
3027 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3028 (MOVSSrr (v4i32 (V_SET0)),
3029 (EXTRACT_SUBREG (v4i32 VR128:$src), x86_subreg_ss))>;
3032 // Splat v2f64 / v2i64
3033 let AddedComplexity = 10 in {
3034 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3035 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3036 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3037 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3038 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3039 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3040 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3041 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3044 // Special unary SHUFPSrri case.
3045 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3046 (SHUFPSrri VR128:$src1, VR128:$src1,
3047 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3048 let AddedComplexity = 5 in
3049 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3050 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3051 Requires<[HasSSE2]>;
3052 // Special unary SHUFPDrri case.
3053 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3054 (SHUFPDrri VR128:$src1, VR128:$src1,
3055 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3056 Requires<[HasSSE2]>;
3057 // Special unary SHUFPDrri case.
3058 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3059 (SHUFPDrri VR128:$src1, VR128:$src1,
3060 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3061 Requires<[HasSSE2]>;
3062 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3063 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3064 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3065 Requires<[HasSSE2]>;
3067 // Special binary v4i32 shuffle cases with SHUFPS.
3068 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3069 (SHUFPSrri VR128:$src1, VR128:$src2,
3070 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3071 Requires<[HasSSE2]>;
3072 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3073 (SHUFPSrmi VR128:$src1, addr:$src2,
3074 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3075 Requires<[HasSSE2]>;
3076 // Special binary v2i64 shuffle cases using SHUFPDrri.
3077 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3078 (SHUFPDrri VR128:$src1, VR128:$src2,
3079 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3080 Requires<[HasSSE2]>;
3082 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3083 let AddedComplexity = 15 in {
3084 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3085 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3086 Requires<[OptForSpeed, HasSSE2]>;
3087 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3088 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3089 Requires<[OptForSpeed, HasSSE2]>;
3091 let AddedComplexity = 10 in {
3092 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3093 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3094 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3095 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3096 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3097 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3098 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3099 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3102 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3103 let AddedComplexity = 15 in {
3104 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3105 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3106 Requires<[OptForSpeed, HasSSE2]>;
3107 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3108 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3109 Requires<[OptForSpeed, HasSSE2]>;
3111 let AddedComplexity = 10 in {
3112 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3113 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3114 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3115 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3116 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3117 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3118 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3119 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3122 let AddedComplexity = 20 in {
3123 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3124 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3125 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3127 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3128 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3129 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3131 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3132 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3133 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3134 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3135 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3138 let AddedComplexity = 20 in {
3139 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3140 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3141 (MOVLPSrm VR128:$src1, addr:$src2)>;
3142 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3143 (MOVLPDrm VR128:$src1, addr:$src2)>;
3144 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3145 (MOVLPSrm VR128:$src1, addr:$src2)>;
3146 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3147 (MOVLPDrm VR128:$src1, addr:$src2)>;
3150 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3151 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3152 (MOVLPSmr addr:$src1, VR128:$src2)>;
3153 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3154 (MOVLPDmr addr:$src1, VR128:$src2)>;
3155 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3157 (MOVLPSmr addr:$src1, VR128:$src2)>;
3158 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3159 (MOVLPDmr addr:$src1, VR128:$src2)>;
3161 let AddedComplexity = 15 in {
3162 // Setting the lowest element in the vector.
3163 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3164 (MOVSSrr (v4i32 VR128:$src1),
3165 (EXTRACT_SUBREG (v4i32 VR128:$src2), x86_subreg_ss))>;
3166 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3167 (MOVSDrr (v2i64 VR128:$src1),
3168 (EXTRACT_SUBREG (v2i64 VR128:$src2), x86_subreg_sd))>;
3170 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3171 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3172 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3173 Requires<[HasSSE2]>;
3174 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3175 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3176 Requires<[HasSSE2]>;
3179 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3180 // fall back to this for SSE1)
3181 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3182 (SHUFPSrri VR128:$src2, VR128:$src1,
3183 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3185 // Set lowest element and zero upper elements.
3186 let AddedComplexity = 15 in
3187 def : Pat<(v2f64 (movl immAllZerosV_bc, VR128:$src)),
3188 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3189 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3190 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3192 // Some special case pandn patterns.
3193 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3195 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3196 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3198 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3199 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3201 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3203 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3204 (memop addr:$src2))),
3205 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3206 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3207 (memop addr:$src2))),
3208 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3209 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3210 (memop addr:$src2))),
3211 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3213 // vector -> vector casts
3214 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3215 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3216 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3217 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3218 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3219 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3220 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3221 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3223 // Use movaps / movups for SSE integer load / store (one byte shorter).
3224 def : Pat<(alignedloadv4i32 addr:$src),
3225 (MOVAPSrm addr:$src)>;
3226 def : Pat<(loadv4i32 addr:$src),
3227 (MOVUPSrm addr:$src)>;
3228 def : Pat<(alignedloadv2i64 addr:$src),
3229 (MOVAPSrm addr:$src)>;
3230 def : Pat<(loadv2i64 addr:$src),
3231 (MOVUPSrm addr:$src)>;
3233 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3234 (MOVAPSmr addr:$dst, VR128:$src)>;
3235 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3236 (MOVAPSmr addr:$dst, VR128:$src)>;
3237 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3238 (MOVAPSmr addr:$dst, VR128:$src)>;
3239 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3240 (MOVAPSmr addr:$dst, VR128:$src)>;
3241 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3242 (MOVUPSmr addr:$dst, VR128:$src)>;
3243 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3244 (MOVUPSmr addr:$dst, VR128:$src)>;
3245 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3246 (MOVUPSmr addr:$dst, VR128:$src)>;
3247 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3248 (MOVUPSmr addr:$dst, VR128:$src)>;
3250 //===----------------------------------------------------------------------===//
3251 // SSE4.1 Instructions
3252 //===----------------------------------------------------------------------===//
3254 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3257 Intrinsic V2F64Int> {
3258 // Intrinsic operation, reg.
3259 // Vector intrinsic operation, reg
3260 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3261 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3262 !strconcat(OpcodeStr,
3263 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3264 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3267 // Vector intrinsic operation, mem
3268 def PSm_Int : Ii8<opcps, MRMSrcMem,
3269 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3270 !strconcat(OpcodeStr,
3271 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3273 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3275 Requires<[HasSSE41]>;
3277 // Vector intrinsic operation, reg
3278 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3279 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3280 !strconcat(OpcodeStr,
3281 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3282 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3285 // Vector intrinsic operation, mem
3286 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3287 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3288 !strconcat(OpcodeStr,
3289 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3291 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3295 let Constraints = "$src1 = $dst" in {
3296 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3300 // Intrinsic operation, reg.
3301 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3303 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3304 !strconcat(OpcodeStr,
3305 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3307 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3310 // Intrinsic operation, mem.
3311 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3313 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3314 !strconcat(OpcodeStr,
3315 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3317 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3320 // Intrinsic operation, reg.
3321 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3323 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3324 !strconcat(OpcodeStr,
3325 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3327 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3330 // Intrinsic operation, mem.
3331 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3333 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3334 !strconcat(OpcodeStr,
3335 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3337 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3342 // FP round - roundss, roundps, roundsd, roundpd
3343 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3344 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3345 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3346 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3348 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3349 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3350 Intrinsic IntId128> {
3351 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3353 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3354 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3355 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3357 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3360 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3363 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3364 int_x86_sse41_phminposuw>;
3366 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3367 let Constraints = "$src1 = $dst" in {
3368 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3369 Intrinsic IntId128, bit Commutable = 0> {
3370 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3371 (ins VR128:$src1, VR128:$src2),
3372 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3373 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3375 let isCommutable = Commutable;
3377 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3378 (ins VR128:$src1, i128mem:$src2),
3379 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3381 (IntId128 VR128:$src1,
3382 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3386 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3387 int_x86_sse41_pcmpeqq, 1>;
3388 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3389 int_x86_sse41_packusdw, 0>;
3390 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3391 int_x86_sse41_pminsb, 1>;
3392 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3393 int_x86_sse41_pminsd, 1>;
3394 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3395 int_x86_sse41_pminud, 1>;
3396 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3397 int_x86_sse41_pminuw, 1>;
3398 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3399 int_x86_sse41_pmaxsb, 1>;
3400 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3401 int_x86_sse41_pmaxsd, 1>;
3402 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3403 int_x86_sse41_pmaxud, 1>;
3404 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3405 int_x86_sse41_pmaxuw, 1>;
3407 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3409 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3410 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3411 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3412 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3414 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3415 let Constraints = "$src1 = $dst" in {
3416 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3417 SDNode OpNode, Intrinsic IntId128,
3418 bit Commutable = 0> {
3419 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3420 (ins VR128:$src1, VR128:$src2),
3421 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3422 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3423 VR128:$src2))]>, OpSize {
3424 let isCommutable = Commutable;
3426 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3427 (ins VR128:$src1, VR128:$src2),
3428 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3429 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3431 let isCommutable = Commutable;
3433 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3434 (ins VR128:$src1, i128mem:$src2),
3435 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3437 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3438 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3439 (ins VR128:$src1, i128mem:$src2),
3440 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3442 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3446 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3447 int_x86_sse41_pmulld, 1>;
3449 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3450 let Constraints = "$src1 = $dst" in {
3451 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3452 Intrinsic IntId128, bit Commutable = 0> {
3453 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3454 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3455 !strconcat(OpcodeStr,
3456 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3458 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3460 let isCommutable = Commutable;
3462 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3463 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3464 !strconcat(OpcodeStr,
3465 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3467 (IntId128 VR128:$src1,
3468 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3473 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3474 int_x86_sse41_blendps, 0>;
3475 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3476 int_x86_sse41_blendpd, 0>;
3477 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3478 int_x86_sse41_pblendw, 0>;
3479 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3480 int_x86_sse41_dpps, 1>;
3481 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3482 int_x86_sse41_dppd, 1>;
3483 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3484 int_x86_sse41_mpsadbw, 1>;
3487 /// SS41I_ternary_int - SSE 4.1 ternary operator
3488 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3489 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3490 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3491 (ins VR128:$src1, VR128:$src2),
3492 !strconcat(OpcodeStr,
3493 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3494 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3497 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3498 (ins VR128:$src1, i128mem:$src2),
3499 !strconcat(OpcodeStr,
3500 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3503 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3507 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3508 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3509 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3512 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3513 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3514 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3515 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3517 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3520 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3524 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3525 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3526 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3527 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3528 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3529 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3531 // Common patterns involving scalar load.
3532 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3533 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3534 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3535 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3537 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3538 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3539 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3540 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3542 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3543 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3544 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3545 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3547 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3548 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3549 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3550 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3552 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3553 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3554 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3555 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3557 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3558 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3559 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3560 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3563 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3564 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3565 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3566 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3568 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3569 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3571 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3575 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3576 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3577 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3578 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3580 // Common patterns involving scalar load
3581 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3582 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3583 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3584 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3586 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3587 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3588 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3589 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3592 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3593 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3595 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3597 // Expecting a i16 load any extended to i32 value.
3598 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3599 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3600 [(set VR128:$dst, (IntId (bitconvert
3601 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3605 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3606 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3608 // Common patterns involving scalar load
3609 def : Pat<(int_x86_sse41_pmovsxbq
3610 (bitconvert (v4i32 (X86vzmovl
3611 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3612 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3614 def : Pat<(int_x86_sse41_pmovzxbq
3615 (bitconvert (v4i32 (X86vzmovl
3616 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3617 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3620 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3621 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3622 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3623 (ins VR128:$src1, i32i8imm:$src2),
3624 !strconcat(OpcodeStr,
3625 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3626 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3628 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3629 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3630 !strconcat(OpcodeStr,
3631 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3634 // There's an AssertZext in the way of writing the store pattern
3635 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3638 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3641 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3642 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3643 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3644 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3645 !strconcat(OpcodeStr,
3646 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3649 // There's an AssertZext in the way of writing the store pattern
3650 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3653 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3656 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3657 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3658 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3659 (ins VR128:$src1, i32i8imm:$src2),
3660 !strconcat(OpcodeStr,
3661 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3663 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3664 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3665 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3666 !strconcat(OpcodeStr,
3667 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3668 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3669 addr:$dst)]>, OpSize;
3672 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3675 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3677 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3678 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3679 (ins VR128:$src1, i32i8imm:$src2),
3680 !strconcat(OpcodeStr,
3681 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3683 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3685 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3686 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3687 !strconcat(OpcodeStr,
3688 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3689 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3690 addr:$dst)]>, OpSize;
3693 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3695 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3696 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3699 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3700 Requires<[HasSSE41]>;
3702 let Constraints = "$src1 = $dst" in {
3703 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3704 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3705 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3706 !strconcat(OpcodeStr,
3707 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3709 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3710 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3711 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3712 !strconcat(OpcodeStr,
3713 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3715 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3716 imm:$src3))]>, OpSize;
3720 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3722 let Constraints = "$src1 = $dst" in {
3723 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3724 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3725 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3726 !strconcat(OpcodeStr,
3727 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3729 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3731 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3732 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3733 !strconcat(OpcodeStr,
3734 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3736 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3737 imm:$src3)))]>, OpSize;
3741 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3743 // insertps has a few different modes, there's the first two here below which
3744 // are optimized inserts that won't zero arbitrary elements in the destination
3745 // vector. The next one matches the intrinsic and could zero arbitrary elements
3746 // in the target vector.
3747 let Constraints = "$src1 = $dst" in {
3748 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3749 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3750 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3751 !strconcat(OpcodeStr,
3752 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3754 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3756 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3757 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3758 !strconcat(OpcodeStr,
3759 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3761 (X86insrtps VR128:$src1,
3762 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3763 imm:$src3))]>, OpSize;
3767 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3769 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3770 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3772 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3773 // the intel intrinsic that corresponds to this.
3774 let Defs = [EFLAGS] in {
3775 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3776 "ptest \t{$src2, $src1|$src1, $src2}",
3777 [(X86ptest VR128:$src1, VR128:$src2),
3778 (implicit EFLAGS)]>, OpSize;
3779 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3780 "ptest \t{$src2, $src1|$src1, $src2}",
3781 [(X86ptest VR128:$src1, (load addr:$src2)),
3782 (implicit EFLAGS)]>, OpSize;
3785 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3786 "movntdqa\t{$src, $dst|$dst, $src}",
3787 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3791 //===----------------------------------------------------------------------===//
3792 // SSE4.2 Instructions
3793 //===----------------------------------------------------------------------===//
3795 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3796 let Constraints = "$src1 = $dst" in {
3797 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3798 Intrinsic IntId128, bit Commutable = 0> {
3799 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3800 (ins VR128:$src1, VR128:$src2),
3801 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3802 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3804 let isCommutable = Commutable;
3806 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3807 (ins VR128:$src1, i128mem:$src2),
3808 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3810 (IntId128 VR128:$src1,
3811 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3815 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3817 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3818 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3819 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3820 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3822 // crc intrinsic instruction
3823 // This set of instructions are only rm, the only difference is the size
3825 let Constraints = "$src1 = $dst" in {
3826 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3827 (ins GR32:$src1, i8mem:$src2),
3828 "crc32 \t{$src2, $src1|$src1, $src2}",
3830 (int_x86_sse42_crc32_8 GR32:$src1,
3831 (load addr:$src2)))]>, OpSize;
3832 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3833 (ins GR32:$src1, GR8:$src2),
3834 "crc32 \t{$src2, $src1|$src1, $src2}",
3836 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>,
3838 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3839 (ins GR32:$src1, i16mem:$src2),
3840 "crc32 \t{$src2, $src1|$src1, $src2}",
3842 (int_x86_sse42_crc32_16 GR32:$src1,
3843 (load addr:$src2)))]>,
3845 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3846 (ins GR32:$src1, GR16:$src2),
3847 "crc32 \t{$src2, $src1|$src1, $src2}",
3849 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3851 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3852 (ins GR32:$src1, i32mem:$src2),
3853 "crc32 \t{$src2, $src1|$src1, $src2}",
3855 (int_x86_sse42_crc32_32 GR32:$src1,
3856 (load addr:$src2)))]>, OpSize;
3857 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3858 (ins GR32:$src1, GR32:$src2),
3859 "crc32 \t{$src2, $src1|$src1, $src2}",
3861 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>,
3863 def CRC64m64 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3864 (ins GR64:$src1, i64mem:$src2),
3865 "crc32 \t{$src2, $src1|$src1, $src2}",
3867 (int_x86_sse42_crc32_64 GR64:$src1,
3868 (load addr:$src2)))]>,
3870 def CRC64r64 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3871 (ins GR64:$src1, GR64:$src2),
3872 "crc32 \t{$src2, $src1|$src1, $src2}",
3874 (int_x86_sse42_crc32_64 GR64:$src1, GR64:$src2))]>,
3878 // String/text processing instructions.
3879 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3880 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3881 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3882 "#PCMPISTRM128rr PSEUDO!",
3883 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3884 imm:$src3))]>, OpSize;
3885 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3886 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3887 "#PCMPISTRM128rm PSEUDO!",
3888 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3889 imm:$src3))]>, OpSize;
3892 let Defs = [XMM0, EFLAGS] in {
3893 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3894 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3895 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3896 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3897 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3898 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3901 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3902 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3903 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3904 "#PCMPESTRM128rr PSEUDO!",
3906 (int_x86_sse42_pcmpestrm128
3907 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3909 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3910 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3911 "#PCMPESTRM128rm PSEUDO!",
3912 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3913 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3917 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3918 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3919 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3920 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3921 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3922 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3923 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3926 let Defs = [ECX, EFLAGS] in {
3927 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3928 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3929 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3930 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3931 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3932 (implicit EFLAGS)]>, OpSize;
3933 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3934 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3935 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3936 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3937 (implicit EFLAGS)]>, OpSize;
3941 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3942 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3943 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3944 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3945 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3946 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3948 let Defs = [ECX, EFLAGS] in {
3949 let Uses = [EAX, EDX] in {
3950 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3951 def rr : SS42AI<0x61, MRMSrcReg, (outs),
3952 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3953 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3954 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
3955 (implicit EFLAGS)]>, OpSize;
3956 def rm : SS42AI<0x61, MRMSrcMem, (outs),
3957 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3958 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3960 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
3961 (implicit EFLAGS)]>, OpSize;
3966 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
3967 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
3968 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
3969 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
3970 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
3971 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;