1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 // Implicitly promote a 32-bit scalar to a vector.
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (COPY_TO_REGCLASS FR32:$src, VR128)>;
287 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
288 (COPY_TO_REGCLASS FR32:$src, VR128)>;
289 // Implicitly promote a 64-bit scalar to a vector.
290 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
291 (COPY_TO_REGCLASS FR64:$src, VR128)>;
292 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
293 (COPY_TO_REGCLASS FR64:$src, VR128)>;
295 // Bitcasts between 128-bit vector types. Return the original type since
296 // no instruction is needed for the conversion
297 let Predicates = [HasSSE2] in {
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 // Bitcasts between 256-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasAVX] in {
333 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
334 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 // Alias instructions that map fld0 to pxor for sse.
366 // This is expanded by ExpandPostRAPseudos.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
369 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
370 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
371 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
372 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 //===----------------------------------------------------------------------===//
376 // AVX & SSE - Zero/One Vectors
377 //===----------------------------------------------------------------------===//
379 // Alias instruction that maps zero vector to pxor / xorp* for sse.
380 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
381 // swizzled by ExecutionDepsFix to pxor.
382 // We set canFoldAsLoad because this can be converted to a constant-pool
383 // load of an all-zeros value if folding it would be beneficial.
384 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
385 isPseudo = 1, neverHasSideEffects = 1 in {
386 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
389 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
390 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
391 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
392 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
394 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397 // The same as done above but for AVX. The 256-bit ISA does not support PI,
398 // and doesn't need it because on sandy bridge the register is set to zero
399 // at the rename stage without using any execution unit, so SET0PSY
400 // and SET0PDY can be used for vector int instructions without penalty
401 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
402 // JIT implementatioan, it does not expand the instructions below like
403 // X86MCInstLower does.
404 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
405 isCodeGenOnly = 1 in {
406 let Predicates = [HasAVX] in {
407 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
408 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
409 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
410 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
412 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
413 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
417 let Predicates = [HasAVX2], AddedComplexity = 5 in {
418 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
419 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
420 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
421 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
424 // AVX has no support for 256-bit integer instructions, but since the 128-bit
425 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
426 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
438 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
440 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
445 // JIT implementation, it does not expand the instructions below like
446 // X86MCInstLower does.
447 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
448 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
449 let Predicates = [HasAVX] in
450 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
451 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
452 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
453 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
454 let Predicates = [HasAVX2] in
455 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
456 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
460 //===----------------------------------------------------------------------===//
461 // SSE 1 & 2 - Move FP Scalar Instructions
463 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
464 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
465 // is used instead. Register-to-register movss/movsd is not modeled as an
466 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
467 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
468 //===----------------------------------------------------------------------===//
470 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
471 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
472 [(set VR128:$dst, (vt (OpNode VR128:$src1,
473 (scalar_to_vector RC:$src2))))],
476 // Loading from memory automatically zeroing upper bits.
477 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
478 PatFrag mem_pat, string OpcodeStr> :
479 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
481 [(set RC:$dst, (mem_pat addr:$src))],
485 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
486 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
488 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
489 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
492 // For the disassembler
493 let isCodeGenOnly = 1 in {
494 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
495 (ins VR128:$src1, FR32:$src2),
496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
499 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
500 (ins VR128:$src1, FR64:$src2),
501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
506 let canFoldAsLoad = 1, isReMaterializable = 1 in {
507 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
509 let AddedComplexity = 20 in
510 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
514 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
515 "movss\t{$src, $dst|$dst, $src}",
516 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
518 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
519 "movsd\t{$src, $dst|$dst, $src}",
520 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
524 let Constraints = "$src1 = $dst" in {
525 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
526 "movss\t{$src2, $dst|$dst, $src2}">, XS;
527 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
528 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
530 // For the disassembler
531 let isCodeGenOnly = 1 in {
532 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
533 (ins VR128:$src1, FR32:$src2),
534 "movss\t{$src2, $dst|$dst, $src2}", [],
535 IIC_SSE_MOV_S_RR>, XS;
536 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
537 (ins VR128:$src1, FR64:$src2),
538 "movsd\t{$src2, $dst|$dst, $src2}", [],
539 IIC_SSE_MOV_S_RR>, XD;
543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
544 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
546 let AddedComplexity = 20 in
547 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
550 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
551 "movss\t{$src, $dst|$dst, $src}",
552 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
553 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
554 "movsd\t{$src, $dst|$dst, $src}",
555 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
558 let Predicates = [HasAVX] in {
559 let AddedComplexity = 15 in {
560 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
561 // MOVS{S,D} to the lower bits.
562 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
563 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
564 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
565 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
566 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
567 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
568 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
569 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
571 // Move low f32 and clear high bits.
572 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
573 (SUBREG_TO_REG (i32 0),
574 (VMOVSSrr (v4f32 (V_SET0)),
575 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
576 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
577 (SUBREG_TO_REG (i32 0),
578 (VMOVSSrr (v4i32 (V_SET0)),
579 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
582 let AddedComplexity = 20 in {
583 // MOVSSrm zeros the high parts of the register; represent this
584 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
585 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
586 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
587 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
588 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
589 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
590 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
592 // MOVSDrm zeros the high parts of the register; represent this
593 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
594 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
595 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
596 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
597 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
598 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
599 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
600 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
601 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
602 def : Pat<(v2f64 (X86vzload addr:$src)),
603 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
605 // Represent the same patterns above but in the form they appear for
607 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
608 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
609 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
610 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
611 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
612 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
613 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
614 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
615 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
617 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
618 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
619 (SUBREG_TO_REG (i32 0),
620 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
622 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
623 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
624 (SUBREG_TO_REG (i64 0),
625 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
627 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
628 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
629 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
631 // Move low f64 and clear high bits.
632 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
633 (SUBREG_TO_REG (i32 0),
634 (VMOVSDrr (v2f64 (V_SET0)),
635 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
637 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
638 (SUBREG_TO_REG (i32 0),
639 (VMOVSDrr (v2i64 (V_SET0)),
640 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
642 // Extract and store.
643 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
645 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
646 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
648 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
650 // Shuffle with VMOVSS
651 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
652 (VMOVSSrr (v4i32 VR128:$src1),
653 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
654 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
655 (VMOVSSrr (v4f32 VR128:$src1),
656 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
659 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
660 (SUBREG_TO_REG (i32 0),
661 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
662 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
664 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
665 (SUBREG_TO_REG (i32 0),
666 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
667 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
670 // Shuffle with VMOVSD
671 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
672 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
673 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
674 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
675 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
676 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
677 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
678 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
681 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
682 (SUBREG_TO_REG (i32 0),
683 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
684 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
686 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
687 (SUBREG_TO_REG (i32 0),
688 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
689 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
693 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
694 // is during lowering, where it's not possible to recognize the fold cause
695 // it has two uses through a bitcast. One use disappears at isel time and the
696 // fold opportunity reappears.
697 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
698 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
699 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
700 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
701 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
702 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
703 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
704 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
707 let Predicates = [HasSSE1] in {
708 let AddedComplexity = 15 in {
709 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
710 // MOVSS to the lower bits.
711 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
712 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
713 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
714 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
715 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
716 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
719 let AddedComplexity = 20 in {
720 // MOVSSrm already zeros the high parts of the register.
721 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
722 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
723 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
724 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
725 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
726 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
729 // Extract and store.
730 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
732 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
734 // Shuffle with MOVSS
735 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
736 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
737 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
738 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
741 let Predicates = [HasSSE2] in {
742 let AddedComplexity = 15 in {
743 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
744 // MOVSD to the lower bits.
745 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
746 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
749 let AddedComplexity = 20 in {
750 // MOVSDrm already zeros the high parts of the register.
751 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
752 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
753 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
754 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
755 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
756 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
757 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
758 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
759 def : Pat<(v2f64 (X86vzload addr:$src)),
760 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
763 // Extract and store.
764 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
766 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
768 // Shuffle with MOVSD
769 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
770 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
771 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
772 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
773 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
774 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
775 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
776 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
778 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
779 // is during lowering, where it's not possible to recognize the fold cause
780 // it has two uses through a bitcast. One use disappears at isel time and the
781 // fold opportunity reappears.
782 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
786 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
787 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
788 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
789 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
792 //===----------------------------------------------------------------------===//
793 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
794 //===----------------------------------------------------------------------===//
796 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
797 X86MemOperand x86memop, PatFrag ld_frag,
798 string asm, Domain d,
800 bit IsReMaterializable = 1> {
801 let neverHasSideEffects = 1 in
802 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
803 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
804 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
805 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
806 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
807 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
810 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
811 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
813 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
814 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
816 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
817 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
819 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
820 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
823 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
824 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
826 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
827 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
829 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
830 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
832 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
833 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
848 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
849 "movaps\t{$src, $dst|$dst, $src}",
850 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
851 IIC_SSE_MOVA_P_MR>, VEX;
852 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
853 "movapd\t{$src, $dst|$dst, $src}",
854 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
855 IIC_SSE_MOVA_P_MR>, VEX;
856 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
857 "movups\t{$src, $dst|$dst, $src}",
858 [(store (v4f32 VR128:$src), addr:$dst)],
859 IIC_SSE_MOVU_P_MR>, VEX;
860 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
861 "movupd\t{$src, $dst|$dst, $src}",
862 [(store (v2f64 VR128:$src), addr:$dst)],
863 IIC_SSE_MOVU_P_MR>, VEX;
864 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
865 "movaps\t{$src, $dst|$dst, $src}",
866 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
867 IIC_SSE_MOVA_P_MR>, VEX;
868 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
869 "movapd\t{$src, $dst|$dst, $src}",
870 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
871 IIC_SSE_MOVA_P_MR>, VEX;
872 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
873 "movups\t{$src, $dst|$dst, $src}",
874 [(store (v8f32 VR256:$src), addr:$dst)],
875 IIC_SSE_MOVU_P_MR>, VEX;
876 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
877 "movupd\t{$src, $dst|$dst, $src}",
878 [(store (v4f64 VR256:$src), addr:$dst)],
879 IIC_SSE_MOVU_P_MR>, VEX;
882 let isCodeGenOnly = 1 in {
883 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
885 "movaps\t{$src, $dst|$dst, $src}", [],
886 IIC_SSE_MOVA_P_RR>, VEX;
887 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
889 "movapd\t{$src, $dst|$dst, $src}", [],
890 IIC_SSE_MOVA_P_RR>, VEX;
891 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
893 "movups\t{$src, $dst|$dst, $src}", [],
894 IIC_SSE_MOVU_P_RR>, VEX;
895 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
897 "movupd\t{$src, $dst|$dst, $src}", [],
898 IIC_SSE_MOVU_P_RR>, VEX;
899 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
901 "movaps\t{$src, $dst|$dst, $src}", [],
902 IIC_SSE_MOVA_P_RR>, VEX;
903 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
905 "movapd\t{$src, $dst|$dst, $src}", [],
906 IIC_SSE_MOVA_P_RR>, VEX;
907 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
909 "movups\t{$src, $dst|$dst, $src}", [],
910 IIC_SSE_MOVU_P_RR>, VEX;
911 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
913 "movupd\t{$src, $dst|$dst, $src}", [],
914 IIC_SSE_MOVU_P_RR>, VEX;
917 let Predicates = [HasAVX] in {
918 def : Pat<(v8i32 (X86vzmovl
919 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
920 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
921 def : Pat<(v4i64 (X86vzmovl
922 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
923 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
924 def : Pat<(v8f32 (X86vzmovl
925 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
926 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
927 def : Pat<(v4f64 (X86vzmovl
928 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
929 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
933 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
934 (VMOVUPSYmr addr:$dst, VR256:$src)>;
935 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
936 (VMOVUPDYmr addr:$dst, VR256:$src)>;
938 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
939 "movaps\t{$src, $dst|$dst, $src}",
940 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
942 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
943 "movapd\t{$src, $dst|$dst, $src}",
944 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
946 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
947 "movups\t{$src, $dst|$dst, $src}",
948 [(store (v4f32 VR128:$src), addr:$dst)],
950 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
951 "movupd\t{$src, $dst|$dst, $src}",
952 [(store (v2f64 VR128:$src), addr:$dst)],
956 let isCodeGenOnly = 1 in {
957 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
958 "movaps\t{$src, $dst|$dst, $src}", [],
960 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
961 "movapd\t{$src, $dst|$dst, $src}", [],
963 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
964 "movups\t{$src, $dst|$dst, $src}", [],
966 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
967 "movupd\t{$src, $dst|$dst, $src}", [],
971 let Predicates = [HasAVX] in {
972 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
973 (VMOVUPSmr addr:$dst, VR128:$src)>;
974 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
975 (VMOVUPDmr addr:$dst, VR128:$src)>;
978 let Predicates = [HasSSE1] in
979 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
980 (MOVUPSmr addr:$dst, VR128:$src)>;
981 let Predicates = [HasSSE2] in
982 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
983 (MOVUPDmr addr:$dst, VR128:$src)>;
985 // Use vmovaps/vmovups for AVX integer load/store.
986 let Predicates = [HasAVX] in {
987 // 128-bit load/store
988 def : Pat<(alignedloadv2i64 addr:$src),
989 (VMOVAPSrm addr:$src)>;
990 def : Pat<(loadv2i64 addr:$src),
991 (VMOVUPSrm addr:$src)>;
993 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
994 (VMOVAPSmr addr:$dst, VR128:$src)>;
995 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
996 (VMOVAPSmr addr:$dst, VR128:$src)>;
997 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
998 (VMOVAPSmr addr:$dst, VR128:$src)>;
999 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1000 (VMOVAPSmr addr:$dst, VR128:$src)>;
1001 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1002 (VMOVUPSmr addr:$dst, VR128:$src)>;
1003 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1004 (VMOVUPSmr addr:$dst, VR128:$src)>;
1005 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1006 (VMOVUPSmr addr:$dst, VR128:$src)>;
1007 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1008 (VMOVUPSmr addr:$dst, VR128:$src)>;
1010 // 256-bit load/store
1011 def : Pat<(alignedloadv4i64 addr:$src),
1012 (VMOVAPSYrm addr:$src)>;
1013 def : Pat<(loadv4i64 addr:$src),
1014 (VMOVUPSYrm addr:$src)>;
1015 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1016 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1017 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1018 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1019 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1020 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1021 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1022 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1023 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1024 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1025 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1026 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1027 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1028 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1029 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1030 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1033 // Use movaps / movups for SSE integer load / store (one byte shorter).
1034 // The instructions selected below are then converted to MOVDQA/MOVDQU
1035 // during the SSE domain pass.
1036 let Predicates = [HasSSE1] in {
1037 def : Pat<(alignedloadv2i64 addr:$src),
1038 (MOVAPSrm addr:$src)>;
1039 def : Pat<(loadv2i64 addr:$src),
1040 (MOVUPSrm addr:$src)>;
1042 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1043 (MOVAPSmr addr:$dst, VR128:$src)>;
1044 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1045 (MOVAPSmr addr:$dst, VR128:$src)>;
1046 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1047 (MOVAPSmr addr:$dst, VR128:$src)>;
1048 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1049 (MOVAPSmr addr:$dst, VR128:$src)>;
1050 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1051 (MOVUPSmr addr:$dst, VR128:$src)>;
1052 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1053 (MOVUPSmr addr:$dst, VR128:$src)>;
1054 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1055 (MOVUPSmr addr:$dst, VR128:$src)>;
1056 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1057 (MOVUPSmr addr:$dst, VR128:$src)>;
1060 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1061 // bits are disregarded. FIXME: Set encoding to pseudo!
1062 let neverHasSideEffects = 1 in {
1063 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1064 "movaps\t{$src, $dst|$dst, $src}", [],
1065 IIC_SSE_MOVA_P_RR>, VEX;
1066 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1067 "movapd\t{$src, $dst|$dst, $src}", [],
1068 IIC_SSE_MOVA_P_RR>, VEX;
1069 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1070 "movaps\t{$src, $dst|$dst, $src}", [],
1072 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1073 "movapd\t{$src, $dst|$dst, $src}", [],
1077 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1078 // bits are disregarded. FIXME: Set encoding to pseudo!
1079 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1080 let isCodeGenOnly = 1 in {
1081 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1082 "movaps\t{$src, $dst|$dst, $src}",
1083 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1084 IIC_SSE_MOVA_P_RM>, VEX;
1085 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1086 "movapd\t{$src, $dst|$dst, $src}",
1087 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1088 IIC_SSE_MOVA_P_RM>, VEX;
1090 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1091 "movaps\t{$src, $dst|$dst, $src}",
1092 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1094 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1095 "movapd\t{$src, $dst|$dst, $src}",
1096 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1100 //===----------------------------------------------------------------------===//
1101 // SSE 1 & 2 - Move Low packed FP Instructions
1102 //===----------------------------------------------------------------------===//
1104 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1105 SDNode psnode, SDNode pdnode, string base_opc,
1106 string asm_opr, InstrItinClass itin> {
1107 def PSrm : PI<opc, MRMSrcMem,
1108 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1109 !strconcat(base_opc, "s", asm_opr),
1112 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1113 itin, SSEPackedSingle>, TB;
1115 def PDrm : PI<opc, MRMSrcMem,
1116 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1117 !strconcat(base_opc, "d", asm_opr),
1118 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1119 (scalar_to_vector (loadf64 addr:$src2)))))],
1120 itin, SSEPackedDouble>, TB, OpSize;
1123 let AddedComplexity = 20 in {
1124 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1125 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1126 IIC_SSE_MOV_LH>, VEX_4V;
1128 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1129 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1130 "\t{$src2, $dst|$dst, $src2}",
1134 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1135 "movlps\t{$src, $dst|$dst, $src}",
1136 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1137 (iPTR 0))), addr:$dst)],
1138 IIC_SSE_MOV_LH>, VEX;
1139 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1140 "movlpd\t{$src, $dst|$dst, $src}",
1141 [(store (f64 (vector_extract (v2f64 VR128:$src),
1142 (iPTR 0))), addr:$dst)],
1143 IIC_SSE_MOV_LH>, VEX;
1144 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1145 "movlps\t{$src, $dst|$dst, $src}",
1146 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1147 (iPTR 0))), addr:$dst)],
1149 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1150 "movlpd\t{$src, $dst|$dst, $src}",
1151 [(store (f64 (vector_extract (v2f64 VR128:$src),
1152 (iPTR 0))), addr:$dst)],
1155 let Predicates = [HasAVX] in {
1156 // Shuffle with VMOVLPS
1157 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1158 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1159 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1160 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1162 // Shuffle with VMOVLPD
1163 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1164 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1165 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1166 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1169 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1171 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1172 def : Pat<(store (v4i32 (X86Movlps
1173 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1174 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1175 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1177 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1178 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1180 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1183 let Predicates = [HasSSE1] in {
1184 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1185 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1186 (iPTR 0))), addr:$src1),
1187 (MOVLPSmr addr:$src1, VR128:$src2)>;
1189 // Shuffle with MOVLPS
1190 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1191 (MOVLPSrm VR128:$src1, addr:$src2)>;
1192 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1193 (MOVLPSrm VR128:$src1, addr:$src2)>;
1194 def : Pat<(X86Movlps VR128:$src1,
1195 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1196 (MOVLPSrm VR128:$src1, addr:$src2)>;
1199 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1201 (MOVLPSmr addr:$src1, VR128:$src2)>;
1202 def : Pat<(store (v4i32 (X86Movlps
1203 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1205 (MOVLPSmr addr:$src1, VR128:$src2)>;
1208 let Predicates = [HasSSE2] in {
1209 // Shuffle with MOVLPD
1210 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1211 (MOVLPDrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1213 (MOVLPDrm VR128:$src1, addr:$src2)>;
1216 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1218 (MOVLPDmr addr:$src1, VR128:$src2)>;
1219 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1221 (MOVLPDmr addr:$src1, VR128:$src2)>;
1224 //===----------------------------------------------------------------------===//
1225 // SSE 1 & 2 - Move Hi packed FP Instructions
1226 //===----------------------------------------------------------------------===//
1228 let AddedComplexity = 20 in {
1229 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1230 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1231 IIC_SSE_MOV_LH>, VEX_4V;
1233 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1234 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1235 "\t{$src2, $dst|$dst, $src2}",
1239 // v2f64 extract element 1 is always custom lowered to unpack high to low
1240 // and extract element 0 so the non-store version isn't too horrible.
1241 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1242 "movhps\t{$src, $dst|$dst, $src}",
1243 [(store (f64 (vector_extract
1244 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1245 (bc_v2f64 (v4f32 VR128:$src))),
1246 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1247 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1248 "movhpd\t{$src, $dst|$dst, $src}",
1249 [(store (f64 (vector_extract
1250 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1251 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1252 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1253 "movhps\t{$src, $dst|$dst, $src}",
1254 [(store (f64 (vector_extract
1255 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1256 (bc_v2f64 (v4f32 VR128:$src))),
1257 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1258 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1259 "movhpd\t{$src, $dst|$dst, $src}",
1260 [(store (f64 (vector_extract
1261 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1262 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1264 let Predicates = [HasAVX] in {
1266 def : Pat<(X86Movlhps VR128:$src1,
1267 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1268 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1269 def : Pat<(X86Movlhps VR128:$src1,
1270 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1271 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1273 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1274 // is during lowering, where it's not possible to recognize the load fold
1275 // cause it has two uses through a bitcast. One use disappears at isel time
1276 // and the fold opportunity reappears.
1277 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1278 (scalar_to_vector (loadf64 addr:$src2)))),
1279 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1282 let Predicates = [HasSSE1] in {
1284 def : Pat<(X86Movlhps VR128:$src1,
1285 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1286 (MOVHPSrm VR128:$src1, addr:$src2)>;
1287 def : Pat<(X86Movlhps VR128:$src1,
1288 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1289 (MOVHPSrm VR128:$src1, addr:$src2)>;
1292 let Predicates = [HasSSE2] in {
1293 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1294 // is during lowering, where it's not possible to recognize the load fold
1295 // cause it has two uses through a bitcast. One use disappears at isel time
1296 // and the fold opportunity reappears.
1297 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1298 (scalar_to_vector (loadf64 addr:$src2)))),
1299 (MOVHPDrm VR128:$src1, addr:$src2)>;
1302 //===----------------------------------------------------------------------===//
1303 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1304 //===----------------------------------------------------------------------===//
1306 let AddedComplexity = 20 in {
1307 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1308 (ins VR128:$src1, VR128:$src2),
1309 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1311 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1314 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1315 (ins VR128:$src1, VR128:$src2),
1316 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1318 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1322 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1323 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1324 (ins VR128:$src1, VR128:$src2),
1325 "movlhps\t{$src2, $dst|$dst, $src2}",
1327 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1329 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1330 (ins VR128:$src1, VR128:$src2),
1331 "movhlps\t{$src2, $dst|$dst, $src2}",
1333 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1337 let Predicates = [HasAVX] in {
1339 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1340 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1341 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1342 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1345 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1346 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1349 let Predicates = [HasSSE1] in {
1351 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1352 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1353 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1354 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1357 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1358 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1361 //===----------------------------------------------------------------------===//
1362 // SSE 1 & 2 - Conversion Instructions
1363 //===----------------------------------------------------------------------===//
1365 def SSE_CVT_PD : OpndItins<
1366 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1369 def SSE_CVT_PS : OpndItins<
1370 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1373 def SSE_CVT_Scalar : OpndItins<
1374 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1377 def SSE_CVT_SS2SI_32 : OpndItins<
1378 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1381 def SSE_CVT_SS2SI_64 : OpndItins<
1382 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1385 def SSE_CVT_SD2SI : OpndItins<
1386 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1389 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1390 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1391 string asm, OpndItins itins> {
1392 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1393 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1395 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1396 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1400 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1401 X86MemOperand x86memop, string asm, Domain d,
1403 let neverHasSideEffects = 1 in {
1404 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1407 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1412 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1413 X86MemOperand x86memop, string asm> {
1414 let neverHasSideEffects = 1 in {
1415 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1416 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1418 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1419 (ins DstRC:$src1, x86memop:$src),
1420 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1421 } // neverHasSideEffects = 1
1424 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1425 "cvttss2si\t{$src, $dst|$dst, $src}",
1428 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1429 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1431 XS, VEX, VEX_W, VEX_LIG;
1432 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1433 "cvttsd2si\t{$src, $dst|$dst, $src}",
1436 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1437 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1439 XD, VEX, VEX_W, VEX_LIG;
1441 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1442 // register, but the same isn't true when only using memory operands,
1443 // provide other assembly "l" and "q" forms to address this explicitly
1444 // where appropriate to do so.
1445 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1446 XS, VEX_4V, VEX_LIG;
1447 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1448 XS, VEX_4V, VEX_W, VEX_LIG;
1449 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1450 XD, VEX_4V, VEX_LIG;
1451 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1452 XD, VEX_4V, VEX_W, VEX_LIG;
1454 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1455 (VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
1456 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1457 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1459 let Predicates = [HasAVX], AddedComplexity = 1 in {
1460 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1461 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1462 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1463 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1464 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1465 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1466 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1467 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1469 def : Pat<(f32 (sint_to_fp GR32:$src)),
1470 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1471 def : Pat<(f32 (sint_to_fp GR64:$src)),
1472 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1473 def : Pat<(f64 (sint_to_fp GR32:$src)),
1474 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1475 def : Pat<(f64 (sint_to_fp GR64:$src)),
1476 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1479 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1480 "cvttss2si\t{$src, $dst|$dst, $src}",
1481 SSE_CVT_SS2SI_32>, XS;
1482 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1483 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1484 SSE_CVT_SS2SI_64>, XS, REX_W;
1485 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1486 "cvttsd2si\t{$src, $dst|$dst, $src}",
1488 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1489 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1490 SSE_CVT_SD2SI>, XD, REX_W;
1491 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1492 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1493 SSE_CVT_Scalar>, XS;
1494 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1495 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1496 SSE_CVT_Scalar>, XS, REX_W;
1497 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1498 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1499 SSE_CVT_Scalar>, XD;
1500 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1501 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1502 SSE_CVT_Scalar>, XD, REX_W;
1504 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1505 // and/or XMM operand(s).
1507 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1508 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1509 string asm, OpndItins itins> {
1510 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1511 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1512 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1513 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1514 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1515 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>;
1518 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1519 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1520 PatFrag ld_frag, string asm, OpndItins itins,
1522 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1524 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1525 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1526 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1528 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1529 (ins DstRC:$src1, x86memop:$src2),
1531 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1532 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1533 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1537 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1538 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si{l}",
1539 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1540 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1541 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si{q}",
1542 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1544 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1545 sdmem, sse_load_f64, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1546 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1547 sdmem, sse_load_f64, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1550 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1551 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1552 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1553 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1554 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1555 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1557 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1558 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1559 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1560 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1561 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1562 SSE_CVT_Scalar, 0>, XD,
1565 let Constraints = "$src1 = $dst" in {
1566 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1567 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1568 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1569 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1570 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1571 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1572 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1573 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1574 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1575 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1576 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1577 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1582 // Aliases for intrinsics
1583 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1584 ssmem, sse_load_f32, "cvttss2si",
1585 SSE_CVT_SS2SI_32>, XS, VEX;
1586 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1587 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1588 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1590 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1591 sdmem, sse_load_f64, "cvttsd2si",
1592 SSE_CVT_SD2SI>, XD, VEX;
1593 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1594 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1595 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1597 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1598 ssmem, sse_load_f32, "cvttss2si",
1599 SSE_CVT_SS2SI_32>, XS;
1600 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1601 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1602 "cvttss2si{q}", SSE_CVT_SS2SI_64>, XS, REX_W;
1603 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1604 sdmem, sse_load_f64, "cvttsd2si",
1606 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1607 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1608 "cvttsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1610 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1611 ssmem, sse_load_f32, "cvtss2si{l}",
1612 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1613 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1614 ssmem, sse_load_f32, "cvtss2si{q}",
1615 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1617 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1618 ssmem, sse_load_f32, "cvtss2si{l}",
1619 SSE_CVT_SS2SI_32>, XS;
1620 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1621 ssmem, sse_load_f32, "cvtss2si{q}",
1622 SSE_CVT_SS2SI_64>, XS, REX_W;
1624 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1625 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1626 SSEPackedSingle, SSE_CVT_PS>,
1627 TB, VEX, Requires<[HasAVX]>;
1628 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1629 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1630 SSEPackedSingle, SSE_CVT_PS>,
1631 TB, VEX, Requires<[HasAVX]>;
1633 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1634 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1635 SSEPackedSingle, SSE_CVT_PS>,
1636 TB, Requires<[HasSSE2]>;
1640 // Convert scalar double to scalar single
1641 let neverHasSideEffects = 1 in {
1642 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1643 (ins FR64:$src1, FR64:$src2),
1644 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1645 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1647 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1648 (ins FR64:$src1, f64mem:$src2),
1649 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1650 [], IIC_SSE_CVT_Scalar_RM>,
1651 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1654 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1657 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1658 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1659 [(set FR32:$dst, (fround FR64:$src))],
1660 IIC_SSE_CVT_Scalar_RR>;
1661 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1662 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1663 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1664 IIC_SSE_CVT_Scalar_RM>,
1666 Requires<[HasSSE2, OptForSize]>;
1668 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1669 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1670 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1672 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1673 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
1674 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1675 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1676 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1677 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1678 VR128:$src1, sse_load_f64:$src2))],
1679 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
1681 let Constraints = "$src1 = $dst" in {
1682 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1683 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1684 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1686 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1687 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[HasSSE2]>;
1688 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1689 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1690 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1691 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1692 VR128:$src1, sse_load_f64:$src2))],
1693 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[HasSSE2]>;
1696 // Convert scalar single to scalar double
1697 // SSE2 instructions with XS prefix
1698 let neverHasSideEffects = 1 in {
1699 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1700 (ins FR32:$src1, FR32:$src2),
1701 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1702 [], IIC_SSE_CVT_Scalar_RR>,
1703 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1705 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1706 (ins FR32:$src1, f32mem:$src2),
1707 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1708 [], IIC_SSE_CVT_Scalar_RM>,
1709 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1712 let AddedComplexity = 1 in { // give AVX priority
1713 def : Pat<(f64 (fextend FR32:$src)),
1714 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1715 def : Pat<(fextend (loadf32 addr:$src)),
1716 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1718 def : Pat<(extloadf32 addr:$src),
1719 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1720 Requires<[HasAVX, OptForSize]>;
1721 def : Pat<(extloadf32 addr:$src),
1722 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1723 Requires<[HasAVX, OptForSpeed]>;
1724 } // AddedComplexity = 1
1726 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1727 "cvtss2sd\t{$src, $dst|$dst, $src}",
1728 [(set FR64:$dst, (fextend FR32:$src))],
1729 IIC_SSE_CVT_Scalar_RR>, XS,
1730 Requires<[HasSSE2]>;
1731 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1732 "cvtss2sd\t{$src, $dst|$dst, $src}",
1733 [(set FR64:$dst, (extloadf32 addr:$src))],
1734 IIC_SSE_CVT_Scalar_RM>, XS,
1735 Requires<[HasSSE2, OptForSize]>;
1737 // extload f32 -> f64. This matches load+fextend because we have a hack in
1738 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1740 // Since these loads aren't folded into the fextend, we have to match it
1742 def : Pat<(fextend (loadf32 addr:$src)),
1743 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1744 def : Pat<(extloadf32 addr:$src),
1745 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1747 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1748 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1749 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1751 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1752 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
1753 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1754 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1755 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1757 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1758 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
1759 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1760 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1761 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1762 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1764 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1765 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[HasSSE2]>;
1766 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1767 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1768 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1770 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1771 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[HasSSE2]>;
1774 // Convert packed single/double fp to doubleword
1775 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1776 "cvtps2dq\t{$src, $dst|$dst, $src}",
1777 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1778 IIC_SSE_CVT_PS_RR>, VEX;
1779 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1780 "cvtps2dq\t{$src, $dst|$dst, $src}",
1782 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1783 IIC_SSE_CVT_PS_RM>, VEX;
1784 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1785 "cvtps2dq\t{$src, $dst|$dst, $src}",
1787 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1788 IIC_SSE_CVT_PS_RR>, VEX;
1789 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1790 "cvtps2dq\t{$src, $dst|$dst, $src}",
1792 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1793 IIC_SSE_CVT_PS_RM>, VEX;
1794 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1795 "cvtps2dq\t{$src, $dst|$dst, $src}",
1796 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1798 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1799 "cvtps2dq\t{$src, $dst|$dst, $src}",
1801 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1805 // Convert Packed Double FP to Packed DW Integers
1806 let Predicates = [HasAVX] in {
1807 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1808 // register, but the same isn't true when using memory operands instead.
1809 // Provide other assembly rr and rm forms to address this explicitly.
1810 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1811 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1812 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1816 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1817 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1818 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1819 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1821 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
1824 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1825 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1827 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX;
1828 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1829 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1831 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1833 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1834 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1837 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1838 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1840 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1842 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1843 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1844 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1847 // Convert with truncation packed single/double fp to doubleword
1848 // SSE2 packed instructions with XS prefix
1849 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1850 "cvttps2dq\t{$src, $dst|$dst, $src}",
1852 (int_x86_sse2_cvttps2dq VR128:$src))],
1853 IIC_SSE_CVT_PS_RR>, VEX;
1854 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1855 "cvttps2dq\t{$src, $dst|$dst, $src}",
1856 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1857 (memopv4f32 addr:$src)))],
1858 IIC_SSE_CVT_PS_RM>, VEX;
1859 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1860 "cvttps2dq\t{$src, $dst|$dst, $src}",
1862 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1863 IIC_SSE_CVT_PS_RR>, VEX;
1864 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1865 "cvttps2dq\t{$src, $dst|$dst, $src}",
1866 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1867 (memopv8f32 addr:$src)))],
1868 IIC_SSE_CVT_PS_RM>, VEX;
1870 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1871 "cvttps2dq\t{$src, $dst|$dst, $src}",
1873 (int_x86_sse2_cvttps2dq VR128:$src))],
1875 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1876 "cvttps2dq\t{$src, $dst|$dst, $src}",
1878 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1881 let Predicates = [HasAVX] in {
1882 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1883 (VCVTDQ2PSrr VR128:$src)>;
1884 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1885 (VCVTDQ2PSrm addr:$src)>;
1887 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1888 (VCVTDQ2PSrr VR128:$src)>;
1889 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1890 (VCVTDQ2PSrm addr:$src)>;
1892 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1893 (VCVTTPS2DQrr VR128:$src)>;
1894 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1895 (VCVTTPS2DQrm addr:$src)>;
1897 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1898 (VCVTDQ2PSYrr VR256:$src)>;
1899 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1900 (VCVTDQ2PSYrm addr:$src)>;
1902 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1903 (VCVTTPS2DQYrr VR256:$src)>;
1904 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1905 (VCVTTPS2DQYrm addr:$src)>;
1908 let Predicates = [HasSSE2] in {
1909 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1910 (CVTDQ2PSrr VR128:$src)>;
1911 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1912 (CVTDQ2PSrm addr:$src)>;
1914 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1915 (CVTDQ2PSrr VR128:$src)>;
1916 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1917 (CVTDQ2PSrm addr:$src)>;
1919 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1920 (CVTTPS2DQrr VR128:$src)>;
1921 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1922 (CVTTPS2DQrm addr:$src)>;
1925 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1926 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1928 (int_x86_sse2_cvttpd2dq VR128:$src))],
1929 IIC_SSE_CVT_PD_RR>, VEX;
1931 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1932 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1933 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1935 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1936 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1937 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1938 (memopv2f64 addr:$src)))],
1941 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1942 // register, but the same isn't true when using memory operands instead.
1943 // Provide other assembly rr and rm forms to address this explicitly.
1946 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
1947 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
1948 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1949 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
1950 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1951 (memopv2f64 addr:$src)))],
1952 IIC_SSE_CVT_PD_RM>, VEX;
1955 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1956 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1958 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
1959 IIC_SSE_CVT_PD_RR>, VEX;
1960 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1961 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1963 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
1964 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1965 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
1966 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
1968 let Predicates = [HasAVX] in {
1969 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
1970 (VCVTTPD2DQYrr VR256:$src)>;
1971 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
1972 (VCVTTPD2DQYrm addr:$src)>;
1973 } // Predicates = [HasAVX]
1975 // Convert packed single to packed double
1976 let Predicates = [HasAVX] in {
1977 // SSE2 instructions without OpSize prefix
1978 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1979 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1980 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
1981 IIC_SSE_CVT_PD_RR>, TB, VEX;
1982 let neverHasSideEffects = 1, mayLoad = 1 in
1983 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1984 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
1985 IIC_SSE_CVT_PD_RM>, TB, VEX;
1986 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1987 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1989 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
1990 IIC_SSE_CVT_PD_RR>, TB, VEX;
1991 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1992 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1994 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
1995 IIC_SSE_CVT_PD_RM>, TB, VEX;
1998 let Predicates = [HasSSE2] in {
1999 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2000 "cvtps2pd\t{$src, $dst|$dst, $src}",
2001 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2002 IIC_SSE_CVT_PD_RR>, TB;
2003 let neverHasSideEffects = 1, mayLoad = 1 in
2004 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2005 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2006 IIC_SSE_CVT_PD_RM>, TB;
2009 // Convert Packed DW Integers to Packed Double FP
2010 let Predicates = [HasAVX] in {
2011 let neverHasSideEffects = 1, mayLoad = 1 in
2012 def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2013 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2015 def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2016 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2018 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
2019 def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2020 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2022 (int_x86_avx_cvtdq2_pd_256
2023 (bitconvert (memopv2i64 addr:$src))))]>, VEX;
2024 def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2025 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2027 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX;
2030 let neverHasSideEffects = 1, mayLoad = 1 in
2031 def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2032 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2034 def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2035 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2036 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2039 // AVX 256-bit register conversion intrinsics
2040 let Predicates = [HasAVX] in {
2041 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2042 (VCVTDQ2PDYrr VR128:$src)>;
2043 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2044 (VCVTDQ2PDYrm addr:$src)>;
2045 } // Predicates = [HasAVX]
2047 // Convert packed double to packed single
2048 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2049 // register, but the same isn't true when using memory operands instead.
2050 // Provide other assembly rr and rm forms to address this explicitly.
2051 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2052 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2053 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2054 IIC_SSE_CVT_PD_RR>, VEX;
2057 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2058 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2059 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2060 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2062 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2063 IIC_SSE_CVT_PD_RM>, VEX;
2066 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2067 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2069 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2070 IIC_SSE_CVT_PD_RR>, VEX;
2071 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2072 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2074 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2075 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2076 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2077 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2079 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2080 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2081 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2083 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2084 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2086 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2090 // AVX 256-bit register conversion intrinsics
2091 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2092 // whenever possible to avoid declaring two versions of each one.
2093 let Predicates = [HasAVX] in {
2094 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2095 (VCVTDQ2PSYrr VR256:$src)>;
2096 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2097 (VCVTDQ2PSYrm addr:$src)>;
2099 // Match fround and fextend for 128/256-bit conversions
2100 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2101 (VCVTPD2PSYrr VR256:$src)>;
2102 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2103 (VCVTPD2PSYrm addr:$src)>;
2105 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2106 (VCVTPS2PDYrr VR128:$src)>;
2107 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2108 (VCVTPS2PDYrm addr:$src)>;
2111 //===----------------------------------------------------------------------===//
2112 // SSE 1 & 2 - Compare Instructions
2113 //===----------------------------------------------------------------------===//
2115 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2116 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2117 Operand CC, SDNode OpNode, ValueType VT,
2118 PatFrag ld_frag, string asm, string asm_alt,
2120 def rr : SIi8<0xC2, MRMSrcReg,
2121 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2122 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2124 def rm : SIi8<0xC2, MRMSrcMem,
2125 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2126 [(set RC:$dst, (OpNode (VT RC:$src1),
2127 (ld_frag addr:$src2), imm:$cc))],
2130 // Accept explicit immediate argument form instead of comparison code.
2131 let neverHasSideEffects = 1 in {
2132 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2133 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2134 IIC_SSE_ALU_F32S_RR>;
2136 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2137 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2138 IIC_SSE_ALU_F32S_RM>;
2142 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2143 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2144 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2146 XS, VEX_4V, VEX_LIG;
2147 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2148 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2149 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2150 SSE_ALU_F32S>, // same latency as 32 bit compare
2151 XD, VEX_4V, VEX_LIG;
2153 let Constraints = "$src1 = $dst" in {
2154 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2155 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2156 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2158 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2159 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2160 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2161 SSE_ALU_F32S>, // same latency as 32 bit compare
2165 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2166 Intrinsic Int, string asm, OpndItins itins> {
2167 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2168 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2169 [(set VR128:$dst, (Int VR128:$src1,
2170 VR128:$src, imm:$cc))],
2172 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2173 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2174 [(set VR128:$dst, (Int VR128:$src1,
2175 (load addr:$src), imm:$cc))],
2179 // Aliases to match intrinsics which expect XMM operand(s).
2180 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2181 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2184 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2185 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2186 SSE_ALU_F32S>, // same latency as f32
2188 let Constraints = "$src1 = $dst" in {
2189 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2190 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2192 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2193 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2194 SSE_ALU_F32S>, // same latency as f32
2199 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2200 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2201 ValueType vt, X86MemOperand x86memop,
2202 PatFrag ld_frag, string OpcodeStr, Domain d> {
2203 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2204 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2205 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2206 IIC_SSE_COMIS_RR, d>;
2207 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2208 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2209 [(set EFLAGS, (OpNode (vt RC:$src1),
2210 (ld_frag addr:$src2)))],
2211 IIC_SSE_COMIS_RM, d>;
2214 let Defs = [EFLAGS] in {
2215 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2216 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2217 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2218 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2220 let Pattern = []<dag> in {
2221 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2222 "comiss", SSEPackedSingle>, TB, VEX,
2224 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2225 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2229 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2230 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2231 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2232 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2234 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2235 load, "comiss", SSEPackedSingle>, TB, VEX;
2236 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2237 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2238 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2239 "ucomiss", SSEPackedSingle>, TB;
2240 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2241 "ucomisd", SSEPackedDouble>, TB, OpSize;
2243 let Pattern = []<dag> in {
2244 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2245 "comiss", SSEPackedSingle>, TB;
2246 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2247 "comisd", SSEPackedDouble>, TB, OpSize;
2250 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2251 load, "ucomiss", SSEPackedSingle>, TB;
2252 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2253 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2255 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2256 "comiss", SSEPackedSingle>, TB;
2257 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2258 "comisd", SSEPackedDouble>, TB, OpSize;
2259 } // Defs = [EFLAGS]
2261 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2262 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2263 Operand CC, Intrinsic Int, string asm,
2264 string asm_alt, Domain d> {
2265 def rri : PIi8<0xC2, MRMSrcReg,
2266 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2267 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2268 IIC_SSE_CMPP_RR, d>;
2269 def rmi : PIi8<0xC2, MRMSrcMem,
2270 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2271 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2272 IIC_SSE_CMPP_RM, d>;
2274 // Accept explicit immediate argument form instead of comparison code.
2275 let neverHasSideEffects = 1 in {
2276 def rri_alt : PIi8<0xC2, MRMSrcReg,
2277 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2278 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2279 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2280 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2281 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2285 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2286 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2287 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2288 SSEPackedSingle>, TB, VEX_4V;
2289 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2290 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2291 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2292 SSEPackedDouble>, TB, OpSize, VEX_4V;
2293 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2294 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2295 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2296 SSEPackedSingle>, TB, VEX_4V;
2297 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2298 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2299 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2300 SSEPackedDouble>, TB, OpSize, VEX_4V;
2301 let Constraints = "$src1 = $dst" in {
2302 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2303 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2304 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2305 SSEPackedSingle>, TB;
2306 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2307 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2308 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2309 SSEPackedDouble>, TB, OpSize;
2312 let Predicates = [HasAVX] in {
2313 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2314 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2315 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2316 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2317 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2318 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2319 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2320 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2322 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2323 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2324 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2325 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2326 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2327 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2328 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2329 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2332 let Predicates = [HasSSE1] in {
2333 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2334 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2335 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2336 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2339 let Predicates = [HasSSE2] in {
2340 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2341 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2342 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2343 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2346 //===----------------------------------------------------------------------===//
2347 // SSE 1 & 2 - Shuffle Instructions
2348 //===----------------------------------------------------------------------===//
2350 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2351 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2352 ValueType vt, string asm, PatFrag mem_frag,
2353 Domain d, bit IsConvertibleToThreeAddress = 0> {
2354 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2355 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2356 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2357 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2358 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2359 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2360 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2361 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2362 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2365 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2366 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2367 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2368 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2369 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2370 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2371 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2372 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2373 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2374 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2375 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2376 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2378 let Constraints = "$src1 = $dst" in {
2379 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2380 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2381 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2383 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2384 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2385 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2389 let Predicates = [HasAVX] in {
2390 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2391 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2392 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2393 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2394 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2396 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2397 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2398 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2399 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2400 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2403 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2404 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2405 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2406 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2407 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2409 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2410 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2411 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2412 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2413 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2416 let Predicates = [HasSSE1] in {
2417 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2418 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2419 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2420 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2421 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2424 let Predicates = [HasSSE2] in {
2425 // Generic SHUFPD patterns
2426 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2427 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2428 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2429 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2430 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2433 //===----------------------------------------------------------------------===//
2434 // SSE 1 & 2 - Unpack Instructions
2435 //===----------------------------------------------------------------------===//
2437 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2438 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2439 PatFrag mem_frag, RegisterClass RC,
2440 X86MemOperand x86memop, string asm,
2442 def rr : PI<opc, MRMSrcReg,
2443 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2445 (vt (OpNode RC:$src1, RC:$src2)))],
2447 def rm : PI<opc, MRMSrcMem,
2448 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2450 (vt (OpNode RC:$src1,
2451 (mem_frag addr:$src2))))],
2455 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2456 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2457 SSEPackedSingle>, TB, VEX_4V;
2458 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2459 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2460 SSEPackedDouble>, TB, OpSize, VEX_4V;
2461 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2462 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2463 SSEPackedSingle>, TB, VEX_4V;
2464 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2465 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2466 SSEPackedDouble>, TB, OpSize, VEX_4V;
2468 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2469 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2470 SSEPackedSingle>, TB, VEX_4V;
2471 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2472 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2473 SSEPackedDouble>, TB, OpSize, VEX_4V;
2474 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2475 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2476 SSEPackedSingle>, TB, VEX_4V;
2477 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2478 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2479 SSEPackedDouble>, TB, OpSize, VEX_4V;
2481 let Constraints = "$src1 = $dst" in {
2482 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2483 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2484 SSEPackedSingle>, TB;
2485 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2486 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2487 SSEPackedDouble>, TB, OpSize;
2488 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2489 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2490 SSEPackedSingle>, TB;
2491 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2492 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2493 SSEPackedDouble>, TB, OpSize;
2494 } // Constraints = "$src1 = $dst"
2496 let Predicates = [HasAVX], AddedComplexity = 1 in {
2497 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2498 // problem is during lowering, where it's not possible to recognize the load
2499 // fold cause it has two uses through a bitcast. One use disappears at isel
2500 // time and the fold opportunity reappears.
2501 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2502 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2505 let Predicates = [HasSSE2] in {
2506 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2507 // problem is during lowering, where it's not possible to recognize the load
2508 // fold cause it has two uses through a bitcast. One use disappears at isel
2509 // time and the fold opportunity reappears.
2510 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2511 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2514 //===----------------------------------------------------------------------===//
2515 // SSE 1 & 2 - Extract Floating-Point Sign mask
2516 //===----------------------------------------------------------------------===//
2518 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2519 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2521 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2522 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2523 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2524 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2526 IIC_SSE_MOVMSK, d>, REX_W;
2529 let Predicates = [HasAVX] in {
2530 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2531 "movmskps", SSEPackedSingle>, TB, VEX;
2532 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2533 "movmskpd", SSEPackedDouble>, TB,
2535 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2536 "movmskps", SSEPackedSingle>, TB, VEX;
2537 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2538 "movmskpd", SSEPackedDouble>, TB,
2541 def : Pat<(i32 (X86fgetsign FR32:$src)),
2542 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2543 def : Pat<(i64 (X86fgetsign FR32:$src)),
2544 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2545 def : Pat<(i32 (X86fgetsign FR64:$src)),
2546 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2547 def : Pat<(i64 (X86fgetsign FR64:$src)),
2548 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2551 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2552 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2553 SSEPackedSingle>, TB, VEX;
2554 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2555 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2556 SSEPackedDouble>, TB,
2558 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2559 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2560 SSEPackedSingle>, TB, VEX;
2561 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2562 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2563 SSEPackedDouble>, TB,
2567 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2568 SSEPackedSingle>, TB;
2569 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2570 SSEPackedDouble>, TB, OpSize;
2572 def : Pat<(i32 (X86fgetsign FR32:$src)),
2573 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2574 Requires<[HasSSE1]>;
2575 def : Pat<(i64 (X86fgetsign FR32:$src)),
2576 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2577 Requires<[HasSSE1]>;
2578 def : Pat<(i32 (X86fgetsign FR64:$src)),
2579 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2580 Requires<[HasSSE2]>;
2581 def : Pat<(i64 (X86fgetsign FR64:$src)),
2582 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2583 Requires<[HasSSE2]>;
2585 //===---------------------------------------------------------------------===//
2586 // SSE2 - Packed Integer Logical Instructions
2587 //===---------------------------------------------------------------------===//
2589 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2591 /// PDI_binop_rm - Simple SSE2 binary operator.
2592 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2593 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2594 X86MemOperand x86memop,
2596 bit IsCommutable = 0,
2598 let isCommutable = IsCommutable in
2599 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2600 (ins RC:$src1, RC:$src2),
2602 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2603 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2604 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2605 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2606 (ins RC:$src1, x86memop:$src2),
2608 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2609 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2610 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2611 (bitconvert (memop_frag addr:$src2)))))],
2614 } // ExeDomain = SSEPackedInt
2616 // These are ordered here for pattern ordering requirements with the fp versions
2618 let Predicates = [HasAVX] in {
2619 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2620 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2621 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2622 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2623 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2624 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2625 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2626 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2629 let Constraints = "$src1 = $dst" in {
2630 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2631 i128mem, SSE_BIT_ITINS_P, 1>;
2632 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2633 i128mem, SSE_BIT_ITINS_P, 1>;
2634 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2635 i128mem, SSE_BIT_ITINS_P, 1>;
2636 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2637 i128mem, SSE_BIT_ITINS_P, 0>;
2638 } // Constraints = "$src1 = $dst"
2640 let Predicates = [HasAVX2] in {
2641 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2642 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2643 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2644 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2645 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2646 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2647 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2648 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2651 //===----------------------------------------------------------------------===//
2652 // SSE 1 & 2 - Logical Instructions
2653 //===----------------------------------------------------------------------===//
2655 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2657 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2658 SDNode OpNode, OpndItins itins> {
2659 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2660 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2663 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2664 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2667 let Constraints = "$src1 = $dst" in {
2668 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2669 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2672 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2673 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2678 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2679 let mayLoad = 0 in {
2680 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2682 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2684 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2688 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2689 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2692 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2694 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2696 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2697 // are all promoted to v2i64, and the patterns are covered by the int
2698 // version. This is needed in SSE only, because v2i64 isn't supported on
2699 // SSE1, but only on SSE2.
2700 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2701 !strconcat(OpcodeStr, "ps"), f128mem, [],
2702 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2703 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2705 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2706 !strconcat(OpcodeStr, "pd"), f128mem,
2707 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2708 (bc_v2i64 (v2f64 VR128:$src2))))],
2709 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2710 (memopv2i64 addr:$src2)))], 0>,
2712 let Constraints = "$src1 = $dst" in {
2713 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2714 !strconcat(OpcodeStr, "ps"), f128mem,
2715 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2716 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2717 (memopv2i64 addr:$src2)))]>, TB;
2719 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2720 !strconcat(OpcodeStr, "pd"), f128mem,
2721 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2722 (bc_v2i64 (v2f64 VR128:$src2))))],
2723 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2724 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2728 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2730 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2732 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2733 !strconcat(OpcodeStr, "ps"), f256mem,
2734 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2735 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2736 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2738 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2739 !strconcat(OpcodeStr, "pd"), f256mem,
2740 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2741 (bc_v4i64 (v4f64 VR256:$src2))))],
2742 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2743 (memopv4i64 addr:$src2)))], 0>,
2747 // AVX 256-bit packed logical ops forms
2748 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2749 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2750 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2751 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2753 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2754 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2755 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2756 let isCommutable = 0 in
2757 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2759 //===----------------------------------------------------------------------===//
2760 // SSE 1 & 2 - Arithmetic Instructions
2761 //===----------------------------------------------------------------------===//
2763 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2766 /// In addition, we also have a special variant of the scalar form here to
2767 /// represent the associated intrinsic operation. This form is unlike the
2768 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2769 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2771 /// These three forms can each be reg+reg or reg+mem.
2774 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2776 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2779 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2780 OpNode, FR32, f32mem,
2781 itins.s, Is2Addr>, XS;
2782 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2783 OpNode, FR64, f64mem,
2784 itins.d, Is2Addr>, XD;
2787 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2790 let mayLoad = 0 in {
2791 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2792 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2794 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2795 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2800 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2803 let mayLoad = 0 in {
2804 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2805 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2807 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2808 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2813 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2816 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2817 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2818 itins.s, Is2Addr>, XS;
2819 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2820 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2821 itins.d, Is2Addr>, XD;
2824 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2827 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2828 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2829 SSEPackedSingle, itins.s, Is2Addr>,
2832 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2833 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2834 SSEPackedDouble, itins.d, Is2Addr>,
2838 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2840 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2841 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2842 SSEPackedSingle, itins.s, 0>, TB;
2844 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2845 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2846 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2849 // Binary Arithmetic instructions
2850 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2851 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2853 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2854 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2856 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2857 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2859 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2860 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2863 let isCommutable = 0 in {
2864 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2865 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2867 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2868 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>, VEX_4V;
2869 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2870 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2872 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2873 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2875 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2876 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2878 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2879 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2880 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2881 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2883 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2884 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2886 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2887 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2888 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2889 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2893 let Constraints = "$src1 = $dst" in {
2894 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2895 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2896 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2897 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2898 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2899 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2901 let isCommutable = 0 in {
2902 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2903 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2904 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2905 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2906 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2907 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2908 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2909 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2910 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2911 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2912 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2913 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2914 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2915 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2920 /// In addition, we also have a special variant of the scalar form here to
2921 /// represent the associated intrinsic operation. This form is unlike the
2922 /// plain scalar form, in that it takes an entire vector (instead of a
2923 /// scalar) and leaves the top elements undefined.
2925 /// And, we have a special variant form for a full-vector intrinsic form.
2927 def SSE_SQRTP : OpndItins<
2928 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2931 def SSE_SQRTS : OpndItins<
2932 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2935 def SSE_RCPP : OpndItins<
2936 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
2939 def SSE_RCPS : OpndItins<
2940 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
2943 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2944 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2945 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
2946 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2947 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2948 [(set FR32:$dst, (OpNode FR32:$src))]>;
2949 // For scalar unary operations, fold a load into the operation
2950 // only in OptForSize mode. It eliminates an instruction, but it also
2951 // eliminates a whole-register clobber (the load), so it introduces a
2952 // partial register update condition.
2953 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2954 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2955 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
2956 Requires<[HasSSE1, OptForSize]>;
2957 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2958 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2959 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
2960 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2961 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2962 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
2965 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2966 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2967 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2968 !strconcat(OpcodeStr,
2969 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2971 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2972 !strconcat(OpcodeStr,
2973 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2974 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2975 (ins VR128:$src1, ssmem:$src2),
2976 !strconcat(OpcodeStr,
2977 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2980 /// sse1_fp_unop_p - SSE1 unops in packed form.
2981 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2983 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2984 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2985 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
2986 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2987 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2988 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
2991 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2992 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
2994 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2995 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2996 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
2998 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2999 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3000 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3004 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3005 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3006 Intrinsic V4F32Int, OpndItins itins> {
3007 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3008 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3009 [(set VR128:$dst, (V4F32Int VR128:$src))],
3011 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3012 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3013 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3017 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3018 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3019 Intrinsic V4F32Int, OpndItins itins> {
3020 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3021 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3022 [(set VR256:$dst, (V4F32Int VR256:$src))],
3024 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3025 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3026 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3030 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3031 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3032 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3033 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3034 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3035 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3036 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3037 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3038 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3039 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3040 Requires<[HasSSE2, OptForSize]>;
3041 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3042 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3043 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3044 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3045 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3046 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3049 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3050 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3051 let neverHasSideEffects = 1 in {
3052 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3053 !strconcat(OpcodeStr,
3054 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3056 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3057 !strconcat(OpcodeStr,
3058 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3060 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3061 (ins VR128:$src1, sdmem:$src2),
3062 !strconcat(OpcodeStr,
3063 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3066 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3067 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3068 SDNode OpNode, OpndItins itins> {
3069 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3070 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3071 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3072 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3073 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3074 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3077 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3078 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3080 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3081 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3082 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3084 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3085 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3086 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3090 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3091 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3092 Intrinsic V2F64Int, OpndItins itins> {
3093 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3094 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3095 [(set VR128:$dst, (V2F64Int VR128:$src))],
3097 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3098 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3099 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3103 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3104 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3105 Intrinsic V2F64Int, OpndItins itins> {
3106 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3107 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3108 [(set VR256:$dst, (V2F64Int VR256:$src))],
3110 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3111 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3112 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3116 let Predicates = [HasAVX] in {
3118 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3119 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3121 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3122 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3123 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3124 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3125 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3127 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3129 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3131 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3135 // Reciprocal approximations. Note that these typically require refinement
3136 // in order to obtain suitable precision.
3137 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3138 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3139 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3140 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3142 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3145 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3146 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3147 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3148 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3150 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3154 let AddedComplexity = 1 in {
3155 def : Pat<(f32 (fsqrt FR32:$src)),
3156 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3157 def : Pat<(f32 (fsqrt (load addr:$src))),
3158 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3159 Requires<[HasAVX, OptForSize]>;
3160 def : Pat<(f64 (fsqrt FR64:$src)),
3161 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3162 def : Pat<(f64 (fsqrt (load addr:$src))),
3163 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3164 Requires<[HasAVX, OptForSize]>;
3166 def : Pat<(f32 (X86frsqrt FR32:$src)),
3167 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3168 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3169 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3170 Requires<[HasAVX, OptForSize]>;
3172 def : Pat<(f32 (X86frcp FR32:$src)),
3173 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3174 def : Pat<(f32 (X86frcp (load addr:$src))),
3175 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3176 Requires<[HasAVX, OptForSize]>;
3179 let Predicates = [HasAVX], AddedComplexity = 1 in {
3180 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3181 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3182 (COPY_TO_REGCLASS VR128:$src, FR32)),
3184 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3185 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3187 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3188 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3189 (COPY_TO_REGCLASS VR128:$src, FR64)),
3191 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3192 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3194 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3195 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3196 (COPY_TO_REGCLASS VR128:$src, FR32)),
3198 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3199 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3201 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3202 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3203 (COPY_TO_REGCLASS VR128:$src, FR32)),
3205 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3206 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3210 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3212 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3213 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3214 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3216 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3217 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3219 // Reciprocal approximations. Note that these typically require refinement
3220 // in order to obtain suitable precision.
3221 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3223 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3224 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3226 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3228 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3229 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3231 // There is no f64 version of the reciprocal approximation instructions.
3233 //===----------------------------------------------------------------------===//
3234 // SSE 1 & 2 - Non-temporal stores
3235 //===----------------------------------------------------------------------===//
3237 let AddedComplexity = 400 in { // Prefer non-temporal versions
3238 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3239 (ins f128mem:$dst, VR128:$src),
3240 "movntps\t{$src, $dst|$dst, $src}",
3241 [(alignednontemporalstore (v4f32 VR128:$src),
3243 IIC_SSE_MOVNT>, VEX;
3244 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3245 (ins f128mem:$dst, VR128:$src),
3246 "movntpd\t{$src, $dst|$dst, $src}",
3247 [(alignednontemporalstore (v2f64 VR128:$src),
3249 IIC_SSE_MOVNT>, VEX;
3251 let ExeDomain = SSEPackedInt in
3252 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3253 (ins f128mem:$dst, VR128:$src),
3254 "movntdq\t{$src, $dst|$dst, $src}",
3255 [(alignednontemporalstore (v2i64 VR128:$src),
3257 IIC_SSE_MOVNT>, VEX;
3259 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3260 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3262 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3263 (ins f256mem:$dst, VR256:$src),
3264 "movntps\t{$src, $dst|$dst, $src}",
3265 [(alignednontemporalstore (v8f32 VR256:$src),
3267 IIC_SSE_MOVNT>, VEX;
3268 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3269 (ins f256mem:$dst, VR256:$src),
3270 "movntpd\t{$src, $dst|$dst, $src}",
3271 [(alignednontemporalstore (v4f64 VR256:$src),
3273 IIC_SSE_MOVNT>, VEX;
3274 let ExeDomain = SSEPackedInt in
3275 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3276 (ins f256mem:$dst, VR256:$src),
3277 "movntdq\t{$src, $dst|$dst, $src}",
3278 [(alignednontemporalstore (v4i64 VR256:$src),
3280 IIC_SSE_MOVNT>, VEX;
3283 let AddedComplexity = 400 in { // Prefer non-temporal versions
3284 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3285 "movntps\t{$src, $dst|$dst, $src}",
3286 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3288 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3289 "movntpd\t{$src, $dst|$dst, $src}",
3290 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3293 let ExeDomain = SSEPackedInt in
3294 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3295 "movntdq\t{$src, $dst|$dst, $src}",
3296 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3299 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3300 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3302 // There is no AVX form for instructions below this point
3303 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3304 "movnti{l}\t{$src, $dst|$dst, $src}",
3305 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3307 TB, Requires<[HasSSE2]>;
3308 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3309 "movnti{q}\t{$src, $dst|$dst, $src}",
3310 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3312 TB, Requires<[HasSSE2]>;
3315 //===----------------------------------------------------------------------===//
3316 // SSE 1 & 2 - Prefetch and memory fence
3317 //===----------------------------------------------------------------------===//
3319 // Prefetch intrinsic.
3320 let Predicates = [HasSSE1] in {
3321 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3322 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3323 IIC_SSE_PREFETCH>, TB;
3324 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3325 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3326 IIC_SSE_PREFETCH>, TB;
3327 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3328 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3329 IIC_SSE_PREFETCH>, TB;
3330 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3331 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3332 IIC_SSE_PREFETCH>, TB;
3336 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3337 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3338 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3340 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3341 // was introduced with SSE2, it's backward compatible.
3342 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3344 // Load, store, and memory fence
3345 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3346 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3347 TB, Requires<[HasSSE1]>;
3348 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3349 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3350 TB, Requires<[HasSSE2]>;
3351 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3352 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3353 TB, Requires<[HasSSE2]>;
3355 def : Pat<(X86SFence), (SFENCE)>;
3356 def : Pat<(X86LFence), (LFENCE)>;
3357 def : Pat<(X86MFence), (MFENCE)>;
3359 //===----------------------------------------------------------------------===//
3360 // SSE 1 & 2 - Load/Store XCSR register
3361 //===----------------------------------------------------------------------===//
3363 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3364 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3365 IIC_SSE_LDMXCSR>, VEX;
3366 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3367 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3368 IIC_SSE_STMXCSR>, VEX;
3370 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3371 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3373 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3374 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3377 //===---------------------------------------------------------------------===//
3378 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3379 //===---------------------------------------------------------------------===//
3381 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3383 let neverHasSideEffects = 1 in {
3384 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3385 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3387 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3388 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3391 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3392 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3394 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3395 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3399 let isCodeGenOnly = 1 in {
3400 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3401 "movdqa\t{$src, $dst|$dst, $src}", [],
3404 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3405 "movdqa\t{$src, $dst|$dst, $src}", [],
3408 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3409 "movdqu\t{$src, $dst|$dst, $src}", [],
3412 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3413 "movdqu\t{$src, $dst|$dst, $src}", [],
3418 let canFoldAsLoad = 1, mayLoad = 1 in {
3419 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3420 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3422 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3423 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3425 let Predicates = [HasAVX] in {
3426 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3427 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3429 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3430 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3435 let mayStore = 1 in {
3436 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3437 (ins i128mem:$dst, VR128:$src),
3438 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3440 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3441 (ins i256mem:$dst, VR256:$src),
3442 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3444 let Predicates = [HasAVX] in {
3445 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3446 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3448 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3449 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3454 let neverHasSideEffects = 1 in
3455 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3456 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3458 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3459 "movdqu\t{$src, $dst|$dst, $src}",
3460 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3463 let isCodeGenOnly = 1 in {
3464 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3465 "movdqa\t{$src, $dst|$dst, $src}", [],
3468 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3469 "movdqu\t{$src, $dst|$dst, $src}",
3470 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3473 let canFoldAsLoad = 1, mayLoad = 1 in {
3474 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3475 "movdqa\t{$src, $dst|$dst, $src}",
3476 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3478 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3479 "movdqu\t{$src, $dst|$dst, $src}",
3480 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3482 XS, Requires<[HasSSE2]>;
3485 let mayStore = 1 in {
3486 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3487 "movdqa\t{$src, $dst|$dst, $src}",
3488 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3490 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3491 "movdqu\t{$src, $dst|$dst, $src}",
3492 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3494 XS, Requires<[HasSSE2]>;
3497 // Intrinsic forms of MOVDQU load and store
3498 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3499 "vmovdqu\t{$src, $dst|$dst, $src}",
3500 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3502 XS, VEX, Requires<[HasAVX]>;
3504 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3505 "movdqu\t{$src, $dst|$dst, $src}",
3506 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3508 XS, Requires<[HasSSE2]>;
3510 } // ExeDomain = SSEPackedInt
3512 let Predicates = [HasAVX] in {
3513 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3514 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3517 //===---------------------------------------------------------------------===//
3518 // SSE2 - Packed Integer Arithmetic Instructions
3519 //===---------------------------------------------------------------------===//
3521 def SSE_PMADD : OpndItins<
3522 IIC_SSE_PMADD, IIC_SSE_PMADD
3525 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3527 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3528 RegisterClass RC, PatFrag memop_frag,
3529 X86MemOperand x86memop,
3531 bit IsCommutable = 0,
3533 let isCommutable = IsCommutable in
3534 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3535 (ins RC:$src1, RC:$src2),
3537 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3538 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3539 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3540 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3541 (ins RC:$src1, x86memop:$src2),
3543 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3544 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3545 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3549 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3550 string OpcodeStr, SDNode OpNode,
3551 SDNode OpNode2, RegisterClass RC,
3552 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3553 ShiftOpndItins itins,
3555 // src2 is always 128-bit
3556 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3557 (ins RC:$src1, VR128:$src2),
3559 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3560 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3561 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3563 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3564 (ins RC:$src1, i128mem:$src2),
3566 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3567 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3568 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3569 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3570 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3571 (ins RC:$src1, i32i8imm:$src2),
3573 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3574 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3575 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3578 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3579 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3580 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3581 PatFrag memop_frag, X86MemOperand x86memop,
3583 bit IsCommutable = 0, bit Is2Addr = 1> {
3584 let isCommutable = IsCommutable in
3585 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3586 (ins RC:$src1, RC:$src2),
3588 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3589 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3590 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3591 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3592 (ins RC:$src1, x86memop:$src2),
3594 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3595 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3596 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3597 (bitconvert (memop_frag addr:$src2)))))]>;
3599 } // ExeDomain = SSEPackedInt
3601 // 128-bit Integer Arithmetic
3603 let Predicates = [HasAVX] in {
3604 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3605 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3607 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3608 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3609 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3610 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3611 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3612 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3613 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3614 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3615 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3616 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3617 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3618 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3619 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3620 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3621 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3622 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3623 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3624 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3628 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3629 VR128, memopv2i64, i128mem,
3630 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3631 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3632 VR128, memopv2i64, i128mem,
3633 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3634 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3635 VR128, memopv2i64, i128mem,
3636 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3637 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3638 VR128, memopv2i64, i128mem,
3639 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3640 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3641 VR128, memopv2i64, i128mem,
3642 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3643 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3644 VR128, memopv2i64, i128mem,
3645 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3646 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3647 VR128, memopv2i64, i128mem,
3648 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3649 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3650 VR128, memopv2i64, i128mem,
3651 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3652 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3653 VR128, memopv2i64, i128mem,
3654 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3655 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3656 VR128, memopv2i64, i128mem,
3657 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3658 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3659 VR128, memopv2i64, i128mem,
3660 SSE_PMADD, 1, 0>, VEX_4V;
3661 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3662 VR128, memopv2i64, i128mem,
3663 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3664 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3665 VR128, memopv2i64, i128mem,
3666 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3667 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3668 VR128, memopv2i64, i128mem,
3669 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3670 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3671 VR128, memopv2i64, i128mem,
3672 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3673 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3674 VR128, memopv2i64, i128mem,
3675 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3676 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3677 VR128, memopv2i64, i128mem,
3678 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3679 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3680 VR128, memopv2i64, i128mem,
3681 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3684 let Predicates = [HasAVX2] in {
3685 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3686 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3687 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3688 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3689 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3690 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3691 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3692 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3693 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3694 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3695 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3696 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3697 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3698 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3699 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3700 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3701 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3702 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3703 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3704 VR256, memopv4i64, i256mem,
3705 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3708 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3709 VR256, memopv4i64, i256mem,
3710 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3711 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3712 VR256, memopv4i64, i256mem,
3713 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3714 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3715 VR256, memopv4i64, i256mem,
3716 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3717 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3718 VR256, memopv4i64, i256mem,
3719 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3720 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3721 VR256, memopv4i64, i256mem,
3722 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3723 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3724 VR256, memopv4i64, i256mem,
3725 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3726 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3727 VR256, memopv4i64, i256mem,
3728 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3729 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3730 VR256, memopv4i64, i256mem,
3731 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3732 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3733 VR256, memopv4i64, i256mem,
3734 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3735 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3736 VR256, memopv4i64, i256mem,
3737 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3738 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3739 VR256, memopv4i64, i256mem,
3740 SSE_PMADD, 1, 0>, VEX_4V;
3741 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3742 VR256, memopv4i64, i256mem,
3743 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3744 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3745 VR256, memopv4i64, i256mem,
3746 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3747 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3748 VR256, memopv4i64, i256mem,
3749 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3750 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3751 VR256, memopv4i64, i256mem,
3752 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3753 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3754 VR256, memopv4i64, i256mem,
3755 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3756 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3757 VR256, memopv4i64, i256mem,
3758 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3759 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3760 VR256, memopv4i64, i256mem,
3761 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3764 let Constraints = "$src1 = $dst" in {
3765 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3766 i128mem, SSE_INTALU_ITINS_P, 1>;
3767 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3768 i128mem, SSE_INTALU_ITINS_P, 1>;
3769 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3770 i128mem, SSE_INTALU_ITINS_P, 1>;
3771 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3772 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3773 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3774 i128mem, SSE_INTMUL_ITINS_P, 1>;
3775 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3776 i128mem, SSE_INTALU_ITINS_P>;
3777 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3778 i128mem, SSE_INTALU_ITINS_P>;
3779 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3780 i128mem, SSE_INTALU_ITINS_P>;
3781 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3782 i128mem, SSE_INTALUQ_ITINS_P>;
3783 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3784 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3787 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3788 VR128, memopv2i64, i128mem,
3789 SSE_INTALU_ITINS_P>;
3790 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3791 VR128, memopv2i64, i128mem,
3792 SSE_INTALU_ITINS_P>;
3793 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3794 VR128, memopv2i64, i128mem,
3795 SSE_INTALU_ITINS_P>;
3796 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3797 VR128, memopv2i64, i128mem,
3798 SSE_INTALU_ITINS_P>;
3799 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3800 VR128, memopv2i64, i128mem,
3801 SSE_INTALU_ITINS_P, 1>;
3802 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3803 VR128, memopv2i64, i128mem,
3804 SSE_INTALU_ITINS_P, 1>;
3805 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3806 VR128, memopv2i64, i128mem,
3807 SSE_INTALU_ITINS_P, 1>;
3808 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3809 VR128, memopv2i64, i128mem,
3810 SSE_INTALU_ITINS_P, 1>;
3811 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3812 VR128, memopv2i64, i128mem,
3813 SSE_INTMUL_ITINS_P, 1>;
3814 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3815 VR128, memopv2i64, i128mem,
3816 SSE_INTMUL_ITINS_P, 1>;
3817 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3818 VR128, memopv2i64, i128mem,
3820 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3821 VR128, memopv2i64, i128mem,
3822 SSE_INTALU_ITINS_P, 1>;
3823 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3824 VR128, memopv2i64, i128mem,
3825 SSE_INTALU_ITINS_P, 1>;
3826 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3827 VR128, memopv2i64, i128mem,
3828 SSE_INTALU_ITINS_P, 1>;
3829 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3830 VR128, memopv2i64, i128mem,
3831 SSE_INTALU_ITINS_P, 1>;
3832 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3833 VR128, memopv2i64, i128mem,
3834 SSE_INTALU_ITINS_P, 1>;
3835 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3836 VR128, memopv2i64, i128mem,
3837 SSE_INTALU_ITINS_P, 1>;
3838 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3839 VR128, memopv2i64, i128mem,
3840 SSE_INTALU_ITINS_P, 1>;
3842 } // Constraints = "$src1 = $dst"
3844 //===---------------------------------------------------------------------===//
3845 // SSE2 - Packed Integer Logical Instructions
3846 //===---------------------------------------------------------------------===//
3848 let Predicates = [HasAVX] in {
3849 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3850 VR128, v8i16, v8i16, bc_v8i16,
3851 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3852 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3853 VR128, v4i32, v4i32, bc_v4i32,
3854 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3855 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3856 VR128, v2i64, v2i64, bc_v2i64,
3857 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3859 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3860 VR128, v8i16, v8i16, bc_v8i16,
3861 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3862 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3863 VR128, v4i32, v4i32, bc_v4i32,
3864 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3865 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3866 VR128, v2i64, v2i64, bc_v2i64,
3867 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3869 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3870 VR128, v8i16, v8i16, bc_v8i16,
3871 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3872 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3873 VR128, v4i32, v4i32, bc_v4i32,
3874 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3876 let ExeDomain = SSEPackedInt in {
3877 // 128-bit logical shifts.
3878 def VPSLLDQri : PDIi8<0x73, MRM7r,
3879 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3880 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3882 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3884 def VPSRLDQri : PDIi8<0x73, MRM3r,
3885 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3886 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3888 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3890 // PSRADQri doesn't exist in SSE[1-3].
3892 } // Predicates = [HasAVX]
3894 let Predicates = [HasAVX2] in {
3895 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3896 VR256, v16i16, v8i16, bc_v8i16,
3897 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3898 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3899 VR256, v8i32, v4i32, bc_v4i32,
3900 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3901 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3902 VR256, v4i64, v2i64, bc_v2i64,
3903 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3905 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3906 VR256, v16i16, v8i16, bc_v8i16,
3907 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3908 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3909 VR256, v8i32, v4i32, bc_v4i32,
3910 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3911 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3912 VR256, v4i64, v2i64, bc_v2i64,
3913 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3915 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3916 VR256, v16i16, v8i16, bc_v8i16,
3917 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3918 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3919 VR256, v8i32, v4i32, bc_v4i32,
3920 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3922 let ExeDomain = SSEPackedInt in {
3923 // 256-bit logical shifts.
3924 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3925 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3926 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3928 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3930 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3931 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3932 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3934 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3936 // PSRADQYri doesn't exist in SSE[1-3].
3938 } // Predicates = [HasAVX2]
3940 let Constraints = "$src1 = $dst" in {
3941 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3942 VR128, v8i16, v8i16, bc_v8i16,
3943 SSE_INTSHIFT_ITINS_P>;
3944 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3945 VR128, v4i32, v4i32, bc_v4i32,
3946 SSE_INTSHIFT_ITINS_P>;
3947 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3948 VR128, v2i64, v2i64, bc_v2i64,
3949 SSE_INTSHIFT_ITINS_P>;
3951 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3952 VR128, v8i16, v8i16, bc_v8i16,
3953 SSE_INTSHIFT_ITINS_P>;
3954 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3955 VR128, v4i32, v4i32, bc_v4i32,
3956 SSE_INTSHIFT_ITINS_P>;
3957 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3958 VR128, v2i64, v2i64, bc_v2i64,
3959 SSE_INTSHIFT_ITINS_P>;
3961 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3962 VR128, v8i16, v8i16, bc_v8i16,
3963 SSE_INTSHIFT_ITINS_P>;
3964 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3965 VR128, v4i32, v4i32, bc_v4i32,
3966 SSE_INTSHIFT_ITINS_P>;
3968 let ExeDomain = SSEPackedInt in {
3969 // 128-bit logical shifts.
3970 def PSLLDQri : PDIi8<0x73, MRM7r,
3971 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3972 "pslldq\t{$src2, $dst|$dst, $src2}",
3974 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
3975 def PSRLDQri : PDIi8<0x73, MRM3r,
3976 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3977 "psrldq\t{$src2, $dst|$dst, $src2}",
3979 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
3980 // PSRADQri doesn't exist in SSE[1-3].
3982 } // Constraints = "$src1 = $dst"
3984 let Predicates = [HasAVX] in {
3985 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3986 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3987 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3988 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3989 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3990 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3992 // Shift up / down and insert zero's.
3993 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3994 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3995 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3996 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3999 let Predicates = [HasAVX2] in {
4000 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4001 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4002 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4003 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4006 let Predicates = [HasSSE2] in {
4007 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4008 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4009 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4010 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4011 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4012 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4014 // Shift up / down and insert zero's.
4015 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4016 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4017 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4018 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4021 //===---------------------------------------------------------------------===//
4022 // SSE2 - Packed Integer Comparison Instructions
4023 //===---------------------------------------------------------------------===//
4025 let Predicates = [HasAVX] in {
4026 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4027 VR128, memopv2i64, i128mem,
4028 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4029 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4030 VR128, memopv2i64, i128mem,
4031 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4032 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4033 VR128, memopv2i64, i128mem,
4034 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4035 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4036 VR128, memopv2i64, i128mem,
4037 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4038 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4039 VR128, memopv2i64, i128mem,
4040 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4041 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4042 VR128, memopv2i64, i128mem,
4043 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4046 let Predicates = [HasAVX2] in {
4047 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4048 VR256, memopv4i64, i256mem,
4049 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4050 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4051 VR256, memopv4i64, i256mem,
4052 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4053 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4054 VR256, memopv4i64, i256mem,
4055 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4056 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4057 VR256, memopv4i64, i256mem,
4058 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4059 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4060 VR256, memopv4i64, i256mem,
4061 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4062 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4063 VR256, memopv4i64, i256mem,
4064 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4067 let Constraints = "$src1 = $dst" in {
4068 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4069 VR128, memopv2i64, i128mem,
4070 SSE_INTALU_ITINS_P, 1>;
4071 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4072 VR128, memopv2i64, i128mem,
4073 SSE_INTALU_ITINS_P, 1>;
4074 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4075 VR128, memopv2i64, i128mem,
4076 SSE_INTALU_ITINS_P, 1>;
4077 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4078 VR128, memopv2i64, i128mem,
4079 SSE_INTALU_ITINS_P>;
4080 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4081 VR128, memopv2i64, i128mem,
4082 SSE_INTALU_ITINS_P>;
4083 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4084 VR128, memopv2i64, i128mem,
4085 SSE_INTALU_ITINS_P>;
4086 } // Constraints = "$src1 = $dst"
4088 //===---------------------------------------------------------------------===//
4089 // SSE2 - Packed Integer Pack Instructions
4090 //===---------------------------------------------------------------------===//
4092 let Predicates = [HasAVX] in {
4093 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4094 VR128, memopv2i64, i128mem,
4095 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4096 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4097 VR128, memopv2i64, i128mem,
4098 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4099 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4100 VR128, memopv2i64, i128mem,
4101 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4104 let Predicates = [HasAVX2] in {
4105 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4106 VR256, memopv4i64, i256mem,
4107 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4108 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4109 VR256, memopv4i64, i256mem,
4110 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4111 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4112 VR256, memopv4i64, i256mem,
4113 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4116 let Constraints = "$src1 = $dst" in {
4117 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4118 VR128, memopv2i64, i128mem,
4119 SSE_INTALU_ITINS_P>;
4120 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4121 VR128, memopv2i64, i128mem,
4122 SSE_INTALU_ITINS_P>;
4123 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4124 VR128, memopv2i64, i128mem,
4125 SSE_INTALU_ITINS_P>;
4126 } // Constraints = "$src1 = $dst"
4128 //===---------------------------------------------------------------------===//
4129 // SSE2 - Packed Integer Shuffle Instructions
4130 //===---------------------------------------------------------------------===//
4132 let ExeDomain = SSEPackedInt in {
4133 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4134 def ri : Ii8<0x70, MRMSrcReg,
4135 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4136 !strconcat(OpcodeStr,
4137 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4138 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4140 def mi : Ii8<0x70, MRMSrcMem,
4141 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4142 !strconcat(OpcodeStr,
4143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4145 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4150 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4151 def Yri : Ii8<0x70, MRMSrcReg,
4152 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4153 !strconcat(OpcodeStr,
4154 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4155 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4156 def Ymi : Ii8<0x70, MRMSrcMem,
4157 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4158 !strconcat(OpcodeStr,
4159 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4161 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4162 (i8 imm:$src2))))]>;
4164 } // ExeDomain = SSEPackedInt
4166 let Predicates = [HasAVX] in {
4167 let AddedComplexity = 5 in
4168 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4170 // SSE2 with ImmT == Imm8 and XS prefix.
4171 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4173 // SSE2 with ImmT == Imm8 and XD prefix.
4174 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4176 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4177 (VPSHUFDmi addr:$src1, imm:$imm)>;
4178 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4179 (VPSHUFDri VR128:$src1, imm:$imm)>;
4182 let Predicates = [HasAVX2] in {
4183 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4184 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4185 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4188 let Predicates = [HasSSE2] in {
4189 let AddedComplexity = 5 in
4190 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4192 // SSE2 with ImmT == Imm8 and XS prefix.
4193 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4195 // SSE2 with ImmT == Imm8 and XD prefix.
4196 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4198 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4199 (PSHUFDmi addr:$src1, imm:$imm)>;
4200 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4201 (PSHUFDri VR128:$src1, imm:$imm)>;
4204 //===---------------------------------------------------------------------===//
4205 // SSE2 - Packed Integer Unpack Instructions
4206 //===---------------------------------------------------------------------===//
4208 let ExeDomain = SSEPackedInt in {
4209 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4210 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4211 def rr : PDI<opc, MRMSrcReg,
4212 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4214 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4215 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4216 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4218 def rm : PDI<opc, MRMSrcMem,
4219 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4221 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4222 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4223 [(set VR128:$dst, (OpNode VR128:$src1,
4224 (bc_frag (memopv2i64
4229 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4230 SDNode OpNode, PatFrag bc_frag> {
4231 def Yrr : PDI<opc, MRMSrcReg,
4232 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4233 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4234 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4235 def Yrm : PDI<opc, MRMSrcMem,
4236 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4237 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4238 [(set VR256:$dst, (OpNode VR256:$src1,
4239 (bc_frag (memopv4i64 addr:$src2))))]>;
4242 let Predicates = [HasAVX] in {
4243 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4244 bc_v16i8, 0>, VEX_4V;
4245 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4246 bc_v8i16, 0>, VEX_4V;
4247 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4248 bc_v4i32, 0>, VEX_4V;
4249 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4250 bc_v2i64, 0>, VEX_4V;
4252 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4253 bc_v16i8, 0>, VEX_4V;
4254 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4255 bc_v8i16, 0>, VEX_4V;
4256 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4257 bc_v4i32, 0>, VEX_4V;
4258 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4259 bc_v2i64, 0>, VEX_4V;
4262 let Predicates = [HasAVX2] in {
4263 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4265 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4267 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4269 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4272 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4274 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4276 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4278 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4282 let Constraints = "$src1 = $dst" in {
4283 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4285 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4287 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4289 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4292 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4294 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4296 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4298 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4301 } // ExeDomain = SSEPackedInt
4303 // Patterns for using AVX1 instructions with integer vectors
4304 // Here to give AVX2 priority
4305 let Predicates = [HasAVX] in {
4306 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4307 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4308 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4309 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4310 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4311 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4312 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4313 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4315 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4316 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4317 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4318 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4319 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4320 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4321 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4322 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4325 //===---------------------------------------------------------------------===//
4326 // SSE2 - Packed Integer Extract and Insert
4327 //===---------------------------------------------------------------------===//
4329 let ExeDomain = SSEPackedInt in {
4330 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4331 def rri : Ii8<0xC4, MRMSrcReg,
4332 (outs VR128:$dst), (ins VR128:$src1,
4333 GR32:$src2, i32i8imm:$src3),
4335 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4336 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4338 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4339 def rmi : Ii8<0xC4, MRMSrcMem,
4340 (outs VR128:$dst), (ins VR128:$src1,
4341 i16mem:$src2, i32i8imm:$src3),
4343 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4344 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4346 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4347 imm:$src3))], IIC_SSE_PINSRW>;
4351 let Predicates = [HasAVX] in
4352 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4353 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4354 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4355 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4356 imm:$src2))]>, TB, OpSize, VEX;
4357 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4358 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4359 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4360 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4361 imm:$src2))], IIC_SSE_PEXTRW>;
4364 let Predicates = [HasAVX] in {
4365 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4366 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4367 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4368 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4369 []>, TB, OpSize, VEX_4V;
4372 let Constraints = "$src1 = $dst" in
4373 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4375 } // ExeDomain = SSEPackedInt
4377 //===---------------------------------------------------------------------===//
4378 // SSE2 - Packed Mask Creation
4379 //===---------------------------------------------------------------------===//
4381 let ExeDomain = SSEPackedInt in {
4383 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4384 "pmovmskb\t{$src, $dst|$dst, $src}",
4385 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4386 IIC_SSE_MOVMSK>, VEX;
4387 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4388 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4390 let Predicates = [HasAVX2] in {
4391 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4392 "pmovmskb\t{$src, $dst|$dst, $src}",
4393 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4394 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4395 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4398 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4399 "pmovmskb\t{$src, $dst|$dst, $src}",
4400 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4403 } // ExeDomain = SSEPackedInt
4405 //===---------------------------------------------------------------------===//
4406 // SSE2 - Conditional Store
4407 //===---------------------------------------------------------------------===//
4409 let ExeDomain = SSEPackedInt in {
4412 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4413 (ins VR128:$src, VR128:$mask),
4414 "maskmovdqu\t{$mask, $src|$src, $mask}",
4415 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4416 IIC_SSE_MASKMOV>, VEX;
4418 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4419 (ins VR128:$src, VR128:$mask),
4420 "maskmovdqu\t{$mask, $src|$src, $mask}",
4421 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4422 IIC_SSE_MASKMOV>, VEX;
4425 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4426 "maskmovdqu\t{$mask, $src|$src, $mask}",
4427 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4430 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4431 "maskmovdqu\t{$mask, $src|$src, $mask}",
4432 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4435 } // ExeDomain = SSEPackedInt
4437 //===---------------------------------------------------------------------===//
4438 // SSE2 - Move Doubleword
4439 //===---------------------------------------------------------------------===//
4441 //===---------------------------------------------------------------------===//
4442 // Move Int Doubleword to Packed Double Int
4444 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4445 "movd\t{$src, $dst|$dst, $src}",
4447 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4449 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4450 "movd\t{$src, $dst|$dst, $src}",
4452 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4455 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4456 "mov{d|q}\t{$src, $dst|$dst, $src}",
4458 (v2i64 (scalar_to_vector GR64:$src)))],
4459 IIC_SSE_MOVDQ>, VEX;
4460 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4461 "mov{d|q}\t{$src, $dst|$dst, $src}",
4462 [(set FR64:$dst, (bitconvert GR64:$src))],
4463 IIC_SSE_MOVDQ>, VEX;
4465 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4466 "movd\t{$src, $dst|$dst, $src}",
4468 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4469 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4470 "movd\t{$src, $dst|$dst, $src}",
4472 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4474 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4475 "mov{d|q}\t{$src, $dst|$dst, $src}",
4477 (v2i64 (scalar_to_vector GR64:$src)))],
4479 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4480 "mov{d|q}\t{$src, $dst|$dst, $src}",
4481 [(set FR64:$dst, (bitconvert GR64:$src))],
4484 //===---------------------------------------------------------------------===//
4485 // Move Int Doubleword to Single Scalar
4487 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4488 "movd\t{$src, $dst|$dst, $src}",
4489 [(set FR32:$dst, (bitconvert GR32:$src))],
4490 IIC_SSE_MOVDQ>, VEX;
4492 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4493 "movd\t{$src, $dst|$dst, $src}",
4494 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4497 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4498 "movd\t{$src, $dst|$dst, $src}",
4499 [(set FR32:$dst, (bitconvert GR32:$src))],
4502 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4503 "movd\t{$src, $dst|$dst, $src}",
4504 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4507 //===---------------------------------------------------------------------===//
4508 // Move Packed Doubleword Int to Packed Double Int
4510 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4511 "movd\t{$src, $dst|$dst, $src}",
4512 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4513 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4514 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4515 (ins i32mem:$dst, VR128:$src),
4516 "movd\t{$src, $dst|$dst, $src}",
4517 [(store (i32 (vector_extract (v4i32 VR128:$src),
4518 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4520 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4521 "movd\t{$src, $dst|$dst, $src}",
4522 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4523 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4524 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4525 "movd\t{$src, $dst|$dst, $src}",
4526 [(store (i32 (vector_extract (v4i32 VR128:$src),
4527 (iPTR 0))), addr:$dst)],
4530 //===---------------------------------------------------------------------===//
4531 // Move Packed Doubleword Int first element to Doubleword Int
4533 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4534 "mov{d|q}\t{$src, $dst|$dst, $src}",
4535 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4538 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4540 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4541 "mov{d|q}\t{$src, $dst|$dst, $src}",
4542 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4546 //===---------------------------------------------------------------------===//
4547 // Bitcast FR64 <-> GR64
4549 let Predicates = [HasAVX] in
4550 def VMOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4551 "vmovq\t{$src, $dst|$dst, $src}",
4552 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4554 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4555 "mov{d|q}\t{$src, $dst|$dst, $src}",
4556 [(set GR64:$dst, (bitconvert FR64:$src))],
4557 IIC_SSE_MOVDQ>, VEX;
4558 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4559 "movq\t{$src, $dst|$dst, $src}",
4560 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4561 IIC_SSE_MOVDQ>, VEX;
4563 def MOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4564 "movq\t{$src, $dst|$dst, $src}",
4565 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4567 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4568 "mov{d|q}\t{$src, $dst|$dst, $src}",
4569 [(set GR64:$dst, (bitconvert FR64:$src))],
4571 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4572 "movq\t{$src, $dst|$dst, $src}",
4573 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4576 //===---------------------------------------------------------------------===//
4577 // Move Scalar Single to Double Int
4579 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4580 "movd\t{$src, $dst|$dst, $src}",
4581 [(set GR32:$dst, (bitconvert FR32:$src))],
4582 IIC_SSE_MOVD_ToGP>, VEX;
4583 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4584 "movd\t{$src, $dst|$dst, $src}",
4585 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4586 IIC_SSE_MOVDQ>, VEX;
4587 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4588 "movd\t{$src, $dst|$dst, $src}",
4589 [(set GR32:$dst, (bitconvert FR32:$src))],
4591 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4592 "movd\t{$src, $dst|$dst, $src}",
4593 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4596 //===---------------------------------------------------------------------===//
4597 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4599 let AddedComplexity = 15 in {
4600 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4601 "movd\t{$src, $dst|$dst, $src}",
4602 [(set VR128:$dst, (v4i32 (X86vzmovl
4603 (v4i32 (scalar_to_vector GR32:$src)))))],
4604 IIC_SSE_MOVDQ>, VEX;
4605 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4606 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4607 [(set VR128:$dst, (v2i64 (X86vzmovl
4608 (v2i64 (scalar_to_vector GR64:$src)))))],
4612 let AddedComplexity = 15 in {
4613 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4614 "movd\t{$src, $dst|$dst, $src}",
4615 [(set VR128:$dst, (v4i32 (X86vzmovl
4616 (v4i32 (scalar_to_vector GR32:$src)))))],
4618 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4619 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4620 [(set VR128:$dst, (v2i64 (X86vzmovl
4621 (v2i64 (scalar_to_vector GR64:$src)))))],
4625 let AddedComplexity = 20 in {
4626 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4627 "movd\t{$src, $dst|$dst, $src}",
4629 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4630 (loadi32 addr:$src))))))],
4631 IIC_SSE_MOVDQ>, VEX;
4632 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4633 "movd\t{$src, $dst|$dst, $src}",
4635 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4636 (loadi32 addr:$src))))))],
4640 let Predicates = [HasAVX] in {
4641 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4642 let AddedComplexity = 20 in {
4643 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4644 (VMOVZDI2PDIrm addr:$src)>;
4645 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4646 (VMOVZDI2PDIrm addr:$src)>;
4648 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4649 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4650 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4651 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4652 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4653 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4654 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4657 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4658 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4659 (MOVZDI2PDIrm addr:$src)>;
4660 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4661 (MOVZDI2PDIrm addr:$src)>;
4664 // These are the correct encodings of the instructions so that we know how to
4665 // read correct assembly, even though we continue to emit the wrong ones for
4666 // compatibility with Darwin's buggy assembler.
4667 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4668 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4669 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4670 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4671 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4672 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4673 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4674 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4675 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4676 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4677 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4678 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4680 //===---------------------------------------------------------------------===//
4681 // SSE2 - Move Quadword
4682 //===---------------------------------------------------------------------===//
4684 //===---------------------------------------------------------------------===//
4685 // Move Quadword Int to Packed Quadword Int
4687 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4688 "vmovq\t{$src, $dst|$dst, $src}",
4690 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4691 VEX, Requires<[HasAVX]>;
4692 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4693 "movq\t{$src, $dst|$dst, $src}",
4695 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4697 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4699 //===---------------------------------------------------------------------===//
4700 // Move Packed Quadword Int to Quadword Int
4702 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4703 "movq\t{$src, $dst|$dst, $src}",
4704 [(store (i64 (vector_extract (v2i64 VR128:$src),
4705 (iPTR 0))), addr:$dst)],
4706 IIC_SSE_MOVDQ>, VEX;
4707 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4708 "movq\t{$src, $dst|$dst, $src}",
4709 [(store (i64 (vector_extract (v2i64 VR128:$src),
4710 (iPTR 0))), addr:$dst)],
4713 //===---------------------------------------------------------------------===//
4714 // Store / copy lower 64-bits of a XMM register.
4716 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4717 "movq\t{$src, $dst|$dst, $src}",
4718 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4719 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4720 "movq\t{$src, $dst|$dst, $src}",
4721 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4724 let AddedComplexity = 20 in
4725 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4726 "vmovq\t{$src, $dst|$dst, $src}",
4728 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4729 (loadi64 addr:$src))))))],
4731 XS, VEX, Requires<[HasAVX]>;
4733 let AddedComplexity = 20 in
4734 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4735 "movq\t{$src, $dst|$dst, $src}",
4737 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4738 (loadi64 addr:$src))))))],
4740 XS, Requires<[HasSSE2]>;
4742 let Predicates = [HasAVX], AddedComplexity = 20 in {
4743 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4744 (VMOVZQI2PQIrm addr:$src)>;
4745 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4746 (VMOVZQI2PQIrm addr:$src)>;
4747 def : Pat<(v2i64 (X86vzload addr:$src)),
4748 (VMOVZQI2PQIrm addr:$src)>;
4751 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4752 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4753 (MOVZQI2PQIrm addr:$src)>;
4754 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4755 (MOVZQI2PQIrm addr:$src)>;
4756 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4759 let Predicates = [HasAVX] in {
4760 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4761 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4762 def : Pat<(v4i64 (X86vzload addr:$src)),
4763 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4766 //===---------------------------------------------------------------------===//
4767 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4768 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4770 let AddedComplexity = 15 in
4771 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4772 "vmovq\t{$src, $dst|$dst, $src}",
4773 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4775 XS, VEX, Requires<[HasAVX]>;
4776 let AddedComplexity = 15 in
4777 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4778 "movq\t{$src, $dst|$dst, $src}",
4779 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4781 XS, Requires<[HasSSE2]>;
4783 let AddedComplexity = 20 in
4784 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4785 "vmovq\t{$src, $dst|$dst, $src}",
4786 [(set VR128:$dst, (v2i64 (X86vzmovl
4787 (loadv2i64 addr:$src))))],
4789 XS, VEX, Requires<[HasAVX]>;
4790 let AddedComplexity = 20 in {
4791 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4792 "movq\t{$src, $dst|$dst, $src}",
4793 [(set VR128:$dst, (v2i64 (X86vzmovl
4794 (loadv2i64 addr:$src))))],
4796 XS, Requires<[HasSSE2]>;
4799 let AddedComplexity = 20 in {
4800 let Predicates = [HasAVX] in {
4801 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4802 (VMOVZPQILo2PQIrm addr:$src)>;
4803 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4804 (VMOVZPQILo2PQIrr VR128:$src)>;
4806 let Predicates = [HasSSE2] in {
4807 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4808 (MOVZPQILo2PQIrm addr:$src)>;
4809 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4810 (MOVZPQILo2PQIrr VR128:$src)>;
4814 // Instructions to match in the assembler
4815 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4816 "movq\t{$src, $dst|$dst, $src}", [],
4817 IIC_SSE_MOVDQ>, VEX, VEX_W;
4818 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4819 "movq\t{$src, $dst|$dst, $src}", [],
4820 IIC_SSE_MOVDQ>, VEX, VEX_W;
4821 // Recognize "movd" with GR64 destination, but encode as a "movq"
4822 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4823 "movd\t{$src, $dst|$dst, $src}", [],
4824 IIC_SSE_MOVDQ>, VEX, VEX_W;
4826 // Instructions for the disassembler
4827 // xr = XMM register
4830 let Predicates = [HasAVX] in
4831 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4832 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4833 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4834 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4836 //===---------------------------------------------------------------------===//
4837 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4838 //===---------------------------------------------------------------------===//
4839 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4840 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4841 X86MemOperand x86memop> {
4842 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4844 [(set RC:$dst, (vt (OpNode RC:$src)))],
4846 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4848 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4852 let Predicates = [HasAVX] in {
4853 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4854 v4f32, VR128, memopv4f32, f128mem>, VEX;
4855 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4856 v4f32, VR128, memopv4f32, f128mem>, VEX;
4857 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4858 v8f32, VR256, memopv8f32, f256mem>, VEX;
4859 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4860 v8f32, VR256, memopv8f32, f256mem>, VEX;
4862 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4863 memopv4f32, f128mem>;
4864 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4865 memopv4f32, f128mem>;
4867 let Predicates = [HasAVX] in {
4868 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4869 (VMOVSHDUPrr VR128:$src)>;
4870 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4871 (VMOVSHDUPrm addr:$src)>;
4872 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4873 (VMOVSLDUPrr VR128:$src)>;
4874 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4875 (VMOVSLDUPrm addr:$src)>;
4876 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4877 (VMOVSHDUPYrr VR256:$src)>;
4878 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4879 (VMOVSHDUPYrm addr:$src)>;
4880 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4881 (VMOVSLDUPYrr VR256:$src)>;
4882 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4883 (VMOVSLDUPYrm addr:$src)>;
4886 let Predicates = [HasSSE3] in {
4887 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4888 (MOVSHDUPrr VR128:$src)>;
4889 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4890 (MOVSHDUPrm addr:$src)>;
4891 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4892 (MOVSLDUPrr VR128:$src)>;
4893 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4894 (MOVSLDUPrm addr:$src)>;
4897 //===---------------------------------------------------------------------===//
4898 // SSE3 - Replicate Double FP - MOVDDUP
4899 //===---------------------------------------------------------------------===//
4901 multiclass sse3_replicate_dfp<string OpcodeStr> {
4902 let neverHasSideEffects = 1 in
4903 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4904 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4905 [], IIC_SSE_MOV_LH>;
4906 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4907 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4910 (scalar_to_vector (loadf64 addr:$src)))))],
4914 // FIXME: Merge with above classe when there're patterns for the ymm version
4915 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4916 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4917 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4918 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4919 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4920 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4923 (scalar_to_vector (loadf64 addr:$src)))))]>;
4926 let Predicates = [HasAVX] in {
4927 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4928 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4931 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4933 let Predicates = [HasAVX] in {
4934 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4935 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4936 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4937 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4938 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4939 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4940 def : Pat<(X86Movddup (bc_v2f64
4941 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4942 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4945 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4946 (VMOVDDUPYrm addr:$src)>;
4947 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4948 (VMOVDDUPYrm addr:$src)>;
4949 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4950 (VMOVDDUPYrm addr:$src)>;
4951 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4952 (VMOVDDUPYrr VR256:$src)>;
4955 let Predicates = [HasSSE3] in {
4956 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4957 (MOVDDUPrm addr:$src)>;
4958 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4959 (MOVDDUPrm addr:$src)>;
4960 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4961 (MOVDDUPrm addr:$src)>;
4962 def : Pat<(X86Movddup (bc_v2f64
4963 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4964 (MOVDDUPrm addr:$src)>;
4967 //===---------------------------------------------------------------------===//
4968 // SSE3 - Move Unaligned Integer
4969 //===---------------------------------------------------------------------===//
4971 let Predicates = [HasAVX] in {
4972 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4973 "vlddqu\t{$src, $dst|$dst, $src}",
4974 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4975 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4976 "vlddqu\t{$src, $dst|$dst, $src}",
4977 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4979 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4980 "lddqu\t{$src, $dst|$dst, $src}",
4981 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4984 //===---------------------------------------------------------------------===//
4985 // SSE3 - Arithmetic
4986 //===---------------------------------------------------------------------===//
4988 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4989 X86MemOperand x86memop, OpndItins itins,
4991 def rr : I<0xD0, MRMSrcReg,
4992 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4994 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4995 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4996 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
4997 def rm : I<0xD0, MRMSrcMem,
4998 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5000 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5001 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5002 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5005 let Predicates = [HasAVX] in {
5006 let ExeDomain = SSEPackedSingle in {
5007 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5008 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5009 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5010 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5012 let ExeDomain = SSEPackedDouble in {
5013 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5014 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5015 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5016 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5019 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5020 let ExeDomain = SSEPackedSingle in
5021 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5022 f128mem, SSE_ALU_F32P>, TB, XD;
5023 let ExeDomain = SSEPackedDouble in
5024 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5025 f128mem, SSE_ALU_F64P>, TB, OpSize;
5028 //===---------------------------------------------------------------------===//
5029 // SSE3 Instructions
5030 //===---------------------------------------------------------------------===//
5033 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5034 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5035 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5037 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5038 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5039 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5041 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5043 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5044 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5045 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5046 IIC_SSE_HADDSUB_RM>;
5048 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5049 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5050 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5052 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5053 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5054 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5056 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5058 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5059 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5060 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5061 IIC_SSE_HADDSUB_RM>;
5064 let Predicates = [HasAVX] in {
5065 let ExeDomain = SSEPackedSingle in {
5066 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5067 X86fhadd, 0>, VEX_4V;
5068 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5069 X86fhsub, 0>, VEX_4V;
5070 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5071 X86fhadd, 0>, VEX_4V;
5072 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5073 X86fhsub, 0>, VEX_4V;
5075 let ExeDomain = SSEPackedDouble in {
5076 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5077 X86fhadd, 0>, VEX_4V;
5078 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5079 X86fhsub, 0>, VEX_4V;
5080 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5081 X86fhadd, 0>, VEX_4V;
5082 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5083 X86fhsub, 0>, VEX_4V;
5087 let Constraints = "$src1 = $dst" in {
5088 let ExeDomain = SSEPackedSingle in {
5089 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5090 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5092 let ExeDomain = SSEPackedDouble in {
5093 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5094 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5098 //===---------------------------------------------------------------------===//
5099 // SSSE3 - Packed Absolute Instructions
5100 //===---------------------------------------------------------------------===//
5103 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5104 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5105 Intrinsic IntId128> {
5106 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5108 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5109 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5112 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5117 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5121 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5122 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5123 Intrinsic IntId256> {
5124 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5126 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5127 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5130 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5132 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5135 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5138 let Predicates = [HasAVX] in {
5139 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5140 int_x86_ssse3_pabs_b_128>, VEX;
5141 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5142 int_x86_ssse3_pabs_w_128>, VEX;
5143 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5144 int_x86_ssse3_pabs_d_128>, VEX;
5147 let Predicates = [HasAVX2] in {
5148 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5149 int_x86_avx2_pabs_b>, VEX;
5150 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5151 int_x86_avx2_pabs_w>, VEX;
5152 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5153 int_x86_avx2_pabs_d>, VEX;
5156 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5157 int_x86_ssse3_pabs_b_128>;
5158 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5159 int_x86_ssse3_pabs_w_128>;
5160 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5161 int_x86_ssse3_pabs_d_128>;
5163 //===---------------------------------------------------------------------===//
5164 // SSSE3 - Packed Binary Operator Instructions
5165 //===---------------------------------------------------------------------===//
5167 def SSE_PHADDSUBD : OpndItins<
5168 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5170 def SSE_PHADDSUBSW : OpndItins<
5171 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5173 def SSE_PHADDSUBW : OpndItins<
5174 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5176 def SSE_PSHUFB : OpndItins<
5177 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5179 def SSE_PSIGN : OpndItins<
5180 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5182 def SSE_PMULHRSW : OpndItins<
5183 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5186 /// SS3I_binop_rm - Simple SSSE3 bin op
5187 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5188 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5189 X86MemOperand x86memop, OpndItins itins,
5191 let isCommutable = 1 in
5192 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5193 (ins RC:$src1, RC:$src2),
5195 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5196 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5197 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5199 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5200 (ins RC:$src1, x86memop:$src2),
5202 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5203 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5205 (OpVT (OpNode RC:$src1,
5206 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5209 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5210 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5211 Intrinsic IntId128, OpndItins itins,
5213 let isCommutable = 1 in
5214 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5215 (ins VR128:$src1, VR128:$src2),
5217 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5218 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5219 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5221 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5222 (ins VR128:$src1, i128mem:$src2),
5224 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5225 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5227 (IntId128 VR128:$src1,
5228 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5231 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5232 Intrinsic IntId256> {
5233 let isCommutable = 1 in
5234 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5235 (ins VR256:$src1, VR256:$src2),
5236 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5237 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5239 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5240 (ins VR256:$src1, i256mem:$src2),
5241 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5243 (IntId256 VR256:$src1,
5244 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5247 let ImmT = NoImm, Predicates = [HasAVX] in {
5248 let isCommutable = 0 in {
5249 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5250 memopv2i64, i128mem,
5251 SSE_PHADDSUBW, 0>, VEX_4V;
5252 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5253 memopv2i64, i128mem,
5254 SSE_PHADDSUBD, 0>, VEX_4V;
5255 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5256 memopv2i64, i128mem,
5257 SSE_PHADDSUBW, 0>, VEX_4V;
5258 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5259 memopv2i64, i128mem,
5260 SSE_PHADDSUBD, 0>, VEX_4V;
5261 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5262 memopv2i64, i128mem,
5263 SSE_PSIGN, 0>, VEX_4V;
5264 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5265 memopv2i64, i128mem,
5266 SSE_PSIGN, 0>, VEX_4V;
5267 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5268 memopv2i64, i128mem,
5269 SSE_PSIGN, 0>, VEX_4V;
5270 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5271 memopv2i64, i128mem,
5272 SSE_PSHUFB, 0>, VEX_4V;
5273 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5274 int_x86_ssse3_phadd_sw_128,
5275 SSE_PHADDSUBSW, 0>, VEX_4V;
5276 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5277 int_x86_ssse3_phsub_sw_128,
5278 SSE_PHADDSUBSW, 0>, VEX_4V;
5279 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5280 int_x86_ssse3_pmadd_ub_sw_128,
5281 SSE_PMADD, 0>, VEX_4V;
5283 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5284 int_x86_ssse3_pmul_hr_sw_128,
5285 SSE_PMULHRSW, 0>, VEX_4V;
5288 let ImmT = NoImm, Predicates = [HasAVX2] in {
5289 let isCommutable = 0 in {
5290 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5291 memopv4i64, i256mem,
5292 SSE_PHADDSUBW, 0>, VEX_4V;
5293 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5294 memopv4i64, i256mem,
5295 SSE_PHADDSUBW, 0>, VEX_4V;
5296 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5297 memopv4i64, i256mem,
5298 SSE_PHADDSUBW, 0>, VEX_4V;
5299 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5300 memopv4i64, i256mem,
5301 SSE_PHADDSUBW, 0>, VEX_4V;
5302 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5303 memopv4i64, i256mem,
5304 SSE_PHADDSUBW, 0>, VEX_4V;
5305 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5306 memopv4i64, i256mem,
5307 SSE_PHADDSUBW, 0>, VEX_4V;
5308 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5309 memopv4i64, i256mem,
5310 SSE_PHADDSUBW, 0>, VEX_4V;
5311 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5312 memopv4i64, i256mem,
5313 SSE_PHADDSUBW, 0>, VEX_4V;
5314 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5315 int_x86_avx2_phadd_sw>, VEX_4V;
5316 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5317 int_x86_avx2_phsub_sw>, VEX_4V;
5318 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5319 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5321 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5322 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5325 // None of these have i8 immediate fields.
5326 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5327 let isCommutable = 0 in {
5328 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5329 memopv2i64, i128mem, SSE_PHADDSUBW>;
5330 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5331 memopv2i64, i128mem, SSE_PHADDSUBD>;
5332 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5333 memopv2i64, i128mem, SSE_PHADDSUBW>;
5334 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5335 memopv2i64, i128mem, SSE_PHADDSUBD>;
5336 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5337 memopv2i64, i128mem, SSE_PSIGN>;
5338 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5339 memopv2i64, i128mem, SSE_PSIGN>;
5340 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5341 memopv2i64, i128mem, SSE_PSIGN>;
5342 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5343 memopv2i64, i128mem, SSE_PSHUFB>;
5344 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5345 int_x86_ssse3_phadd_sw_128,
5347 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5348 int_x86_ssse3_phsub_sw_128,
5350 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5351 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5353 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5354 int_x86_ssse3_pmul_hr_sw_128,
5358 //===---------------------------------------------------------------------===//
5359 // SSSE3 - Packed Align Instruction Patterns
5360 //===---------------------------------------------------------------------===//
5362 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5363 let neverHasSideEffects = 1 in {
5364 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5365 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5367 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5369 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5370 [], IIC_SSE_PALIGNR>, OpSize;
5372 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5373 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5375 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5377 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5378 [], IIC_SSE_PALIGNR>, OpSize;
5382 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5383 let neverHasSideEffects = 1 in {
5384 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5385 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5387 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5390 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5391 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5393 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5398 let Predicates = [HasAVX] in
5399 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5400 let Predicates = [HasAVX2] in
5401 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5402 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5403 defm PALIGN : ssse3_palign<"palignr">;
5405 let Predicates = [HasAVX2] in {
5406 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5407 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5408 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5409 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5410 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5411 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5412 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5413 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5416 let Predicates = [HasAVX] in {
5417 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5418 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5419 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5420 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5421 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5422 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5423 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5424 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5427 let Predicates = [HasSSSE3] in {
5428 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5429 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5430 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5431 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5432 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5433 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5434 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5435 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5438 //===---------------------------------------------------------------------===//
5439 // SSSE3 - Thread synchronization
5440 //===---------------------------------------------------------------------===//
5442 let usesCustomInserter = 1 in {
5443 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5444 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5445 Requires<[HasSSE3]>;
5446 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5447 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5448 Requires<[HasSSE3]>;
5451 let Uses = [EAX, ECX, EDX] in
5452 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5453 TB, Requires<[HasSSE3]>;
5454 let Uses = [ECX, EAX] in
5455 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", [], IIC_SSE_MWAIT>,
5456 TB, Requires<[HasSSE3]>;
5458 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5459 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5461 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5462 Requires<[In32BitMode]>;
5463 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5464 Requires<[In64BitMode]>;
5466 //===----------------------------------------------------------------------===//
5467 // SSE4.1 - Packed Move with Sign/Zero Extend
5468 //===----------------------------------------------------------------------===//
5470 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5471 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5472 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5473 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5475 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5476 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5478 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5482 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5484 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5485 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5486 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5488 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5489 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5490 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5493 let Predicates = [HasAVX] in {
5494 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5496 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5498 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5500 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5502 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5504 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5508 let Predicates = [HasAVX2] in {
5509 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5510 int_x86_avx2_pmovsxbw>, VEX;
5511 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5512 int_x86_avx2_pmovsxwd>, VEX;
5513 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5514 int_x86_avx2_pmovsxdq>, VEX;
5515 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5516 int_x86_avx2_pmovzxbw>, VEX;
5517 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5518 int_x86_avx2_pmovzxwd>, VEX;
5519 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5520 int_x86_avx2_pmovzxdq>, VEX;
5523 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5524 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5525 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5526 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5527 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5528 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5530 let Predicates = [HasAVX] in {
5531 // Common patterns involving scalar load.
5532 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5533 (VPMOVSXBWrm addr:$src)>;
5534 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5535 (VPMOVSXBWrm addr:$src)>;
5537 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5538 (VPMOVSXWDrm addr:$src)>;
5539 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5540 (VPMOVSXWDrm addr:$src)>;
5542 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5543 (VPMOVSXDQrm addr:$src)>;
5544 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5545 (VPMOVSXDQrm addr:$src)>;
5547 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5548 (VPMOVZXBWrm addr:$src)>;
5549 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5550 (VPMOVZXBWrm addr:$src)>;
5552 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5553 (VPMOVZXWDrm addr:$src)>;
5554 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5555 (VPMOVZXWDrm addr:$src)>;
5557 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5558 (VPMOVZXDQrm addr:$src)>;
5559 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5560 (VPMOVZXDQrm addr:$src)>;
5563 let Predicates = [HasSSE41] in {
5564 // Common patterns involving scalar load.
5565 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5566 (PMOVSXBWrm addr:$src)>;
5567 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5568 (PMOVSXBWrm addr:$src)>;
5570 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5571 (PMOVSXWDrm addr:$src)>;
5572 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5573 (PMOVSXWDrm addr:$src)>;
5575 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5576 (PMOVSXDQrm addr:$src)>;
5577 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5578 (PMOVSXDQrm addr:$src)>;
5580 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5581 (PMOVZXBWrm addr:$src)>;
5582 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5583 (PMOVZXBWrm addr:$src)>;
5585 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5586 (PMOVZXWDrm addr:$src)>;
5587 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5588 (PMOVZXWDrm addr:$src)>;
5590 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5591 (PMOVZXDQrm addr:$src)>;
5592 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5593 (PMOVZXDQrm addr:$src)>;
5596 let Predicates = [HasAVX2] in {
5597 let AddedComplexity = 15 in {
5598 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5599 (VPMOVZXDQYrr VR128:$src)>;
5600 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5601 (VPMOVZXWDYrr VR128:$src)>;
5604 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5605 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5608 let Predicates = [HasAVX] in {
5609 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5610 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5613 let Predicates = [HasSSE41] in {
5614 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5615 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5619 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5620 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5621 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5622 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5624 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5625 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5627 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5631 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5633 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5634 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5635 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5637 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5638 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5640 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5644 let Predicates = [HasAVX] in {
5645 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5647 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5649 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5651 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5655 let Predicates = [HasAVX2] in {
5656 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5657 int_x86_avx2_pmovsxbd>, VEX;
5658 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5659 int_x86_avx2_pmovsxwq>, VEX;
5660 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5661 int_x86_avx2_pmovzxbd>, VEX;
5662 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5663 int_x86_avx2_pmovzxwq>, VEX;
5666 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5667 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5668 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5669 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5671 let Predicates = [HasAVX] in {
5672 // Common patterns involving scalar load
5673 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5674 (VPMOVSXBDrm addr:$src)>;
5675 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5676 (VPMOVSXWQrm addr:$src)>;
5678 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5679 (VPMOVZXBDrm addr:$src)>;
5680 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5681 (VPMOVZXWQrm addr:$src)>;
5684 let Predicates = [HasSSE41] in {
5685 // Common patterns involving scalar load
5686 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5687 (PMOVSXBDrm addr:$src)>;
5688 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5689 (PMOVSXWQrm addr:$src)>;
5691 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5692 (PMOVZXBDrm addr:$src)>;
5693 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5694 (PMOVZXWQrm addr:$src)>;
5697 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5698 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5699 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5700 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5702 // Expecting a i16 load any extended to i32 value.
5703 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5704 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5705 [(set VR128:$dst, (IntId (bitconvert
5706 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5710 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5712 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5713 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5714 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5716 // Expecting a i16 load any extended to i32 value.
5717 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5718 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5719 [(set VR256:$dst, (IntId (bitconvert
5720 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5724 let Predicates = [HasAVX] in {
5725 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5727 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5730 let Predicates = [HasAVX2] in {
5731 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5732 int_x86_avx2_pmovsxbq>, VEX;
5733 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5734 int_x86_avx2_pmovzxbq>, VEX;
5736 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5737 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5739 let Predicates = [HasAVX] in {
5740 // Common patterns involving scalar load
5741 def : Pat<(int_x86_sse41_pmovsxbq
5742 (bitconvert (v4i32 (X86vzmovl
5743 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5744 (VPMOVSXBQrm addr:$src)>;
5746 def : Pat<(int_x86_sse41_pmovzxbq
5747 (bitconvert (v4i32 (X86vzmovl
5748 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5749 (VPMOVZXBQrm addr:$src)>;
5752 let Predicates = [HasSSE41] in {
5753 // Common patterns involving scalar load
5754 def : Pat<(int_x86_sse41_pmovsxbq
5755 (bitconvert (v4i32 (X86vzmovl
5756 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5757 (PMOVSXBQrm addr:$src)>;
5759 def : Pat<(int_x86_sse41_pmovzxbq
5760 (bitconvert (v4i32 (X86vzmovl
5761 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5762 (PMOVZXBQrm addr:$src)>;
5765 //===----------------------------------------------------------------------===//
5766 // SSE4.1 - Extract Instructions
5767 //===----------------------------------------------------------------------===//
5769 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5770 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5771 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5772 (ins VR128:$src1, i32i8imm:$src2),
5773 !strconcat(OpcodeStr,
5774 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5775 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5777 let neverHasSideEffects = 1, mayStore = 1 in
5778 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5779 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5780 !strconcat(OpcodeStr,
5781 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5784 // There's an AssertZext in the way of writing the store pattern
5785 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5788 let Predicates = [HasAVX] in {
5789 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5790 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5791 (ins VR128:$src1, i32i8imm:$src2),
5792 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5795 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5798 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5799 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5800 let neverHasSideEffects = 1, mayStore = 1 in
5801 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5802 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5803 !strconcat(OpcodeStr,
5804 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5807 // There's an AssertZext in the way of writing the store pattern
5808 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5811 let Predicates = [HasAVX] in
5812 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5814 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5817 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5818 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5819 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5820 (ins VR128:$src1, i32i8imm:$src2),
5821 !strconcat(OpcodeStr,
5822 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5824 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5825 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5826 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5827 !strconcat(OpcodeStr,
5828 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5829 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5830 addr:$dst)]>, OpSize;
5833 let Predicates = [HasAVX] in
5834 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5836 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5838 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5839 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5840 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5841 (ins VR128:$src1, i32i8imm:$src2),
5842 !strconcat(OpcodeStr,
5843 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5845 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5846 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5847 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5848 !strconcat(OpcodeStr,
5849 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5850 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5851 addr:$dst)]>, OpSize, REX_W;
5854 let Predicates = [HasAVX] in
5855 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5857 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5859 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5861 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5862 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5863 (ins VR128:$src1, i32i8imm:$src2),
5864 !strconcat(OpcodeStr,
5865 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5867 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5869 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5870 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5871 !strconcat(OpcodeStr,
5872 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5873 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5874 addr:$dst)]>, OpSize;
5877 let ExeDomain = SSEPackedSingle in {
5878 let Predicates = [HasAVX] in {
5879 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5880 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5881 (ins VR128:$src1, i32i8imm:$src2),
5882 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5885 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5888 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5889 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5892 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5894 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5897 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5898 Requires<[HasSSE41]>;
5900 //===----------------------------------------------------------------------===//
5901 // SSE4.1 - Insert Instructions
5902 //===----------------------------------------------------------------------===//
5904 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5905 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5906 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5908 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5910 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5912 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5913 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5914 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5916 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5918 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5920 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5921 imm:$src3))]>, OpSize;
5924 let Predicates = [HasAVX] in
5925 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5926 let Constraints = "$src1 = $dst" in
5927 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5929 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5930 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5931 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5933 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5935 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5937 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5939 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5940 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5942 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5944 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5946 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5947 imm:$src3)))]>, OpSize;
5950 let Predicates = [HasAVX] in
5951 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5952 let Constraints = "$src1 = $dst" in
5953 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5955 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5956 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5957 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5959 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5961 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5963 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5965 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5966 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5968 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5970 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5972 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5973 imm:$src3)))]>, OpSize;
5976 let Predicates = [HasAVX] in
5977 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5978 let Constraints = "$src1 = $dst" in
5979 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5981 // insertps has a few different modes, there's the first two here below which
5982 // are optimized inserts that won't zero arbitrary elements in the destination
5983 // vector. The next one matches the intrinsic and could zero arbitrary elements
5984 // in the target vector.
5985 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5986 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5987 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5989 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5991 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5993 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5995 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5996 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5998 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6000 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6002 (X86insrtps VR128:$src1,
6003 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6004 imm:$src3))]>, OpSize;
6007 let ExeDomain = SSEPackedSingle in {
6008 let Predicates = [HasAVX] in
6009 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6010 let Constraints = "$src1 = $dst" in
6011 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6014 //===----------------------------------------------------------------------===//
6015 // SSE4.1 - Round Instructions
6016 //===----------------------------------------------------------------------===//
6018 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6019 X86MemOperand x86memop, RegisterClass RC,
6020 PatFrag mem_frag32, PatFrag mem_frag64,
6021 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6022 let ExeDomain = SSEPackedSingle in {
6023 // Intrinsic operation, reg.
6024 // Vector intrinsic operation, reg
6025 def PSr : SS4AIi8<opcps, MRMSrcReg,
6026 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6027 !strconcat(OpcodeStr,
6028 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6029 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6032 // Vector intrinsic operation, mem
6033 def PSm : SS4AIi8<opcps, MRMSrcMem,
6034 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6035 !strconcat(OpcodeStr,
6036 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6038 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6040 } // ExeDomain = SSEPackedSingle
6042 let ExeDomain = SSEPackedDouble in {
6043 // Vector intrinsic operation, reg
6044 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6045 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6046 !strconcat(OpcodeStr,
6047 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6048 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6051 // Vector intrinsic operation, mem
6052 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6053 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6054 !strconcat(OpcodeStr,
6055 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6057 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6059 } // ExeDomain = SSEPackedDouble
6062 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6065 Intrinsic F64Int, bit Is2Addr = 1> {
6066 let ExeDomain = GenericDomain in {
6068 def SSr : SS4AIi8<opcss, MRMSrcReg,
6069 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6071 !strconcat(OpcodeStr,
6072 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6073 !strconcat(OpcodeStr,
6074 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6077 // Intrinsic operation, reg.
6078 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6079 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6081 !strconcat(OpcodeStr,
6082 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6083 !strconcat(OpcodeStr,
6084 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6085 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6088 // Intrinsic operation, mem.
6089 def SSm : SS4AIi8<opcss, MRMSrcMem,
6090 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6092 !strconcat(OpcodeStr,
6093 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6094 !strconcat(OpcodeStr,
6095 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6097 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6101 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6102 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6104 !strconcat(OpcodeStr,
6105 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6106 !strconcat(OpcodeStr,
6107 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6110 // Intrinsic operation, reg.
6111 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6112 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6114 !strconcat(OpcodeStr,
6115 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6116 !strconcat(OpcodeStr,
6117 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6118 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6121 // Intrinsic operation, mem.
6122 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6123 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6125 !strconcat(OpcodeStr,
6126 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6127 !strconcat(OpcodeStr,
6128 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6130 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6132 } // ExeDomain = GenericDomain
6135 // FP round - roundss, roundps, roundsd, roundpd
6136 let Predicates = [HasAVX] in {
6138 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6139 memopv4f32, memopv2f64,
6140 int_x86_sse41_round_ps,
6141 int_x86_sse41_round_pd>, VEX;
6142 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6143 memopv8f32, memopv4f64,
6144 int_x86_avx_round_ps_256,
6145 int_x86_avx_round_pd_256>, VEX;
6146 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6147 int_x86_sse41_round_ss,
6148 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6150 def : Pat<(ffloor FR32:$src),
6151 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6152 def : Pat<(f64 (ffloor FR64:$src)),
6153 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6154 def : Pat<(f32 (fnearbyint FR32:$src)),
6155 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6156 def : Pat<(f64 (fnearbyint FR64:$src)),
6157 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6158 def : Pat<(f32 (fceil FR32:$src)),
6159 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6160 def : Pat<(f64 (fceil FR64:$src)),
6161 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6162 def : Pat<(f32 (frint FR32:$src)),
6163 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6164 def : Pat<(f64 (frint FR64:$src)),
6165 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6166 def : Pat<(f32 (ftrunc FR32:$src)),
6167 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6168 def : Pat<(f64 (ftrunc FR64:$src)),
6169 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6172 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6173 memopv4f32, memopv2f64,
6174 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6175 let Constraints = "$src1 = $dst" in
6176 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6177 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6179 def : Pat<(ffloor FR32:$src),
6180 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6181 def : Pat<(f64 (ffloor FR64:$src)),
6182 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6183 def : Pat<(f32 (fnearbyint FR32:$src)),
6184 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6185 def : Pat<(f64 (fnearbyint FR64:$src)),
6186 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6187 def : Pat<(f32 (fceil FR32:$src)),
6188 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6189 def : Pat<(f64 (fceil FR64:$src)),
6190 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6191 def : Pat<(f32 (frint FR32:$src)),
6192 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6193 def : Pat<(f64 (frint FR64:$src)),
6194 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6195 def : Pat<(f32 (ftrunc FR32:$src)),
6196 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6197 def : Pat<(f64 (ftrunc FR64:$src)),
6198 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6200 //===----------------------------------------------------------------------===//
6201 // SSE4.1 - Packed Bit Test
6202 //===----------------------------------------------------------------------===//
6204 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6205 // the intel intrinsic that corresponds to this.
6206 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6207 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6208 "vptest\t{$src2, $src1|$src1, $src2}",
6209 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6211 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6212 "vptest\t{$src2, $src1|$src1, $src2}",
6213 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6216 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6217 "vptest\t{$src2, $src1|$src1, $src2}",
6218 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6220 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6221 "vptest\t{$src2, $src1|$src1, $src2}",
6222 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6226 let Defs = [EFLAGS] in {
6227 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6228 "ptest\t{$src2, $src1|$src1, $src2}",
6229 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6231 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6232 "ptest\t{$src2, $src1|$src1, $src2}",
6233 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6237 // The bit test instructions below are AVX only
6238 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6239 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6240 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6241 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6242 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6243 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6244 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6245 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6249 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6250 let ExeDomain = SSEPackedSingle in {
6251 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6252 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6254 let ExeDomain = SSEPackedDouble in {
6255 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6256 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6260 //===----------------------------------------------------------------------===//
6261 // SSE4.1 - Misc Instructions
6262 //===----------------------------------------------------------------------===//
6264 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6265 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6266 "popcnt{w}\t{$src, $dst|$dst, $src}",
6267 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6269 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6270 "popcnt{w}\t{$src, $dst|$dst, $src}",
6271 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6272 (implicit EFLAGS)]>, OpSize, XS;
6274 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6275 "popcnt{l}\t{$src, $dst|$dst, $src}",
6276 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6278 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6279 "popcnt{l}\t{$src, $dst|$dst, $src}",
6280 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6281 (implicit EFLAGS)]>, XS;
6283 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6284 "popcnt{q}\t{$src, $dst|$dst, $src}",
6285 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6287 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6288 "popcnt{q}\t{$src, $dst|$dst, $src}",
6289 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6290 (implicit EFLAGS)]>, XS;
6295 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6296 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6297 Intrinsic IntId128> {
6298 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6300 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6301 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6302 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6304 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6307 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6310 let Predicates = [HasAVX] in
6311 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6312 int_x86_sse41_phminposuw>, VEX;
6313 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6314 int_x86_sse41_phminposuw>;
6316 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6317 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6318 Intrinsic IntId128, bit Is2Addr = 1> {
6319 let isCommutable = 1 in
6320 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6321 (ins VR128:$src1, VR128:$src2),
6323 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6324 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6325 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6326 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6327 (ins VR128:$src1, i128mem:$src2),
6329 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6330 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6332 (IntId128 VR128:$src1,
6333 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6336 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6337 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6338 Intrinsic IntId256> {
6339 let isCommutable = 1 in
6340 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6341 (ins VR256:$src1, VR256:$src2),
6342 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6343 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6344 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6345 (ins VR256:$src1, i256mem:$src2),
6346 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6348 (IntId256 VR256:$src1,
6349 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6352 let Predicates = [HasAVX] in {
6353 let isCommutable = 0 in
6354 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6356 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6358 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6360 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6362 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6364 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6366 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6368 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6370 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6372 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6376 let Predicates = [HasAVX2] in {
6377 let isCommutable = 0 in
6378 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6379 int_x86_avx2_packusdw>, VEX_4V;
6380 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6381 int_x86_avx2_pmins_b>, VEX_4V;
6382 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6383 int_x86_avx2_pmins_d>, VEX_4V;
6384 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6385 int_x86_avx2_pminu_d>, VEX_4V;
6386 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6387 int_x86_avx2_pminu_w>, VEX_4V;
6388 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6389 int_x86_avx2_pmaxs_b>, VEX_4V;
6390 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6391 int_x86_avx2_pmaxs_d>, VEX_4V;
6392 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6393 int_x86_avx2_pmaxu_d>, VEX_4V;
6394 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6395 int_x86_avx2_pmaxu_w>, VEX_4V;
6396 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6397 int_x86_avx2_pmul_dq>, VEX_4V;
6400 let Constraints = "$src1 = $dst" in {
6401 let isCommutable = 0 in
6402 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6403 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6404 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6405 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6406 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6407 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6408 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6409 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6410 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6411 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6414 /// SS48I_binop_rm - Simple SSE41 binary operator.
6415 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6416 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6417 X86MemOperand x86memop, bit Is2Addr = 1> {
6418 let isCommutable = 1 in
6419 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6420 (ins RC:$src1, RC:$src2),
6422 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6423 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6424 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6425 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6426 (ins RC:$src1, x86memop:$src2),
6428 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6429 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6431 (OpVT (OpNode RC:$src1,
6432 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6435 let Predicates = [HasAVX] in {
6436 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6437 memopv2i64, i128mem, 0>, VEX_4V;
6438 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6439 memopv2i64, i128mem, 0>, VEX_4V;
6441 let Predicates = [HasAVX2] in {
6442 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6443 memopv4i64, i256mem, 0>, VEX_4V;
6444 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6445 memopv4i64, i256mem, 0>, VEX_4V;
6448 let Constraints = "$src1 = $dst" in {
6449 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6450 memopv2i64, i128mem>;
6451 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6452 memopv2i64, i128mem>;
6455 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6456 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6457 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6458 X86MemOperand x86memop, bit Is2Addr = 1> {
6459 let isCommutable = 1 in
6460 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6461 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6463 !strconcat(OpcodeStr,
6464 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6465 !strconcat(OpcodeStr,
6466 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6467 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6469 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6470 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6472 !strconcat(OpcodeStr,
6473 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6474 !strconcat(OpcodeStr,
6475 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6478 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6482 let Predicates = [HasAVX] in {
6483 let isCommutable = 0 in {
6484 let ExeDomain = SSEPackedSingle in {
6485 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6486 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6487 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6488 int_x86_avx_blend_ps_256, VR256, memopv8f32, f256mem, 0>, VEX_4V;
6490 let ExeDomain = SSEPackedDouble in {
6491 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6492 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6493 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6494 int_x86_avx_blend_pd_256, VR256, memopv4f64, f256mem, 0>, VEX_4V;
6496 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6497 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6498 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6499 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6501 let ExeDomain = SSEPackedSingle in
6502 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6503 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6504 let ExeDomain = SSEPackedDouble in
6505 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6506 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6507 let ExeDomain = SSEPackedSingle in
6508 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6509 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6512 let Predicates = [HasAVX2] in {
6513 let isCommutable = 0 in {
6514 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6515 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6516 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6517 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6521 let Constraints = "$src1 = $dst" in {
6522 let isCommutable = 0 in {
6523 let ExeDomain = SSEPackedSingle in
6524 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6525 VR128, memopv4f32, f128mem>;
6526 let ExeDomain = SSEPackedDouble in
6527 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6528 VR128, memopv2f64, f128mem>;
6529 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6530 VR128, memopv2i64, i128mem>;
6531 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6532 VR128, memopv2i64, i128mem>;
6534 let ExeDomain = SSEPackedSingle in
6535 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6536 VR128, memopv4f32, f128mem>;
6537 let ExeDomain = SSEPackedDouble in
6538 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6539 VR128, memopv2f64, f128mem>;
6542 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6543 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6544 RegisterClass RC, X86MemOperand x86memop,
6545 PatFrag mem_frag, Intrinsic IntId> {
6546 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6547 (ins RC:$src1, RC:$src2, RC:$src3),
6548 !strconcat(OpcodeStr,
6549 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6550 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6551 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6553 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6554 (ins RC:$src1, x86memop:$src2, RC:$src3),
6555 !strconcat(OpcodeStr,
6556 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6558 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6560 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6563 let Predicates = [HasAVX] in {
6564 let ExeDomain = SSEPackedDouble in {
6565 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6566 memopv2f64, int_x86_sse41_blendvpd>;
6567 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6568 memopv4f64, int_x86_avx_blendv_pd_256>;
6569 } // ExeDomain = SSEPackedDouble
6570 let ExeDomain = SSEPackedSingle in {
6571 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6572 memopv4f32, int_x86_sse41_blendvps>;
6573 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6574 memopv8f32, int_x86_avx_blendv_ps_256>;
6575 } // ExeDomain = SSEPackedSingle
6576 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6577 memopv2i64, int_x86_sse41_pblendvb>;
6580 let Predicates = [HasAVX2] in {
6581 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6582 memopv4i64, int_x86_avx2_pblendvb>;
6585 let Predicates = [HasAVX] in {
6586 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6587 (v16i8 VR128:$src2))),
6588 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6589 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6590 (v4i32 VR128:$src2))),
6591 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6592 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6593 (v4f32 VR128:$src2))),
6594 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6595 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6596 (v2i64 VR128:$src2))),
6597 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6598 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6599 (v2f64 VR128:$src2))),
6600 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6601 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6602 (v8i32 VR256:$src2))),
6603 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6604 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6605 (v8f32 VR256:$src2))),
6606 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6607 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6608 (v4i64 VR256:$src2))),
6609 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6610 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6611 (v4f64 VR256:$src2))),
6612 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6614 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6616 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6617 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6619 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6621 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6623 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6624 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6626 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6627 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6629 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6632 let Predicates = [HasAVX2] in {
6633 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6634 (v32i8 VR256:$src2))),
6635 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6636 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6638 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6641 /// SS41I_ternary_int - SSE 4.1 ternary operator
6642 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6643 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6644 X86MemOperand x86memop, Intrinsic IntId> {
6645 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6646 (ins VR128:$src1, VR128:$src2),
6647 !strconcat(OpcodeStr,
6648 "\t{$src2, $dst|$dst, $src2}"),
6649 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6652 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6653 (ins VR128:$src1, x86memop:$src2),
6654 !strconcat(OpcodeStr,
6655 "\t{$src2, $dst|$dst, $src2}"),
6658 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6662 let ExeDomain = SSEPackedDouble in
6663 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
6664 int_x86_sse41_blendvpd>;
6665 let ExeDomain = SSEPackedSingle in
6666 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
6667 int_x86_sse41_blendvps>;
6668 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
6669 int_x86_sse41_pblendvb>;
6671 // Aliases with the implicit xmm0 argument
6672 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6673 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
6674 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6675 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
6676 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6677 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
6678 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6679 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
6680 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6681 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
6682 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6683 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
6685 let Predicates = [HasSSE41] in {
6686 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6687 (v16i8 VR128:$src2))),
6688 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6689 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6690 (v4i32 VR128:$src2))),
6691 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6692 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6693 (v4f32 VR128:$src2))),
6694 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6695 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6696 (v2i64 VR128:$src2))),
6697 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6698 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6699 (v2f64 VR128:$src2))),
6700 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6702 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6704 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6705 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6707 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6708 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6710 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6714 let Predicates = [HasAVX] in
6715 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6716 "vmovntdqa\t{$src, $dst|$dst, $src}",
6717 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6719 let Predicates = [HasAVX2] in
6720 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6721 "vmovntdqa\t{$src, $dst|$dst, $src}",
6722 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6724 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6725 "movntdqa\t{$src, $dst|$dst, $src}",
6726 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6729 //===----------------------------------------------------------------------===//
6730 // SSE4.2 - Compare Instructions
6731 //===----------------------------------------------------------------------===//
6733 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6734 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6735 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6736 X86MemOperand x86memop, bit Is2Addr = 1> {
6737 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6738 (ins RC:$src1, RC:$src2),
6740 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6741 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6742 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6744 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6745 (ins RC:$src1, x86memop:$src2),
6747 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6748 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6750 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6753 let Predicates = [HasAVX] in
6754 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6755 memopv2i64, i128mem, 0>, VEX_4V;
6757 let Predicates = [HasAVX2] in
6758 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6759 memopv4i64, i256mem, 0>, VEX_4V;
6761 let Constraints = "$src1 = $dst" in
6762 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6763 memopv2i64, i128mem>;
6765 //===----------------------------------------------------------------------===//
6766 // SSE4.2 - String/text Processing Instructions
6767 //===----------------------------------------------------------------------===//
6769 // Packed Compare Implicit Length Strings, Return Mask
6770 multiclass pseudo_pcmpistrm<string asm> {
6771 def REG : PseudoI<(outs VR128:$dst),
6772 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6773 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6775 def MEM : PseudoI<(outs VR128:$dst),
6776 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6777 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6778 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6781 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6782 let AddedComplexity = 1 in
6783 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6784 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6787 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6788 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6789 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6790 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6792 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6793 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6794 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6797 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6798 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6799 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6800 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6802 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6803 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6804 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6807 // Packed Compare Explicit Length Strings, Return Mask
6808 multiclass pseudo_pcmpestrm<string asm> {
6809 def REG : PseudoI<(outs VR128:$dst),
6810 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6811 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6812 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6813 def MEM : PseudoI<(outs VR128:$dst),
6814 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6815 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6816 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6819 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6820 let AddedComplexity = 1 in
6821 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6822 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6825 let Predicates = [HasAVX],
6826 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6827 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6828 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6829 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6831 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6832 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6833 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6836 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6837 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6838 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6839 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6841 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6842 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6843 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6846 // Packed Compare Implicit Length Strings, Return Index
6847 let Defs = [ECX, EFLAGS] in {
6848 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6849 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6850 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6851 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6852 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6853 (implicit EFLAGS)]>, OpSize;
6854 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6855 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6856 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6857 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6858 (implicit EFLAGS)]>, OpSize;
6862 let Predicates = [HasAVX] in {
6863 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6865 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6867 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6869 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6871 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6873 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6877 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6878 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6879 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6880 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6881 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6882 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6884 // Packed Compare Explicit Length Strings, Return Index
6885 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6886 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6887 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6888 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6889 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6890 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6891 (implicit EFLAGS)]>, OpSize;
6892 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6893 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6894 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6896 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6897 (implicit EFLAGS)]>, OpSize;
6901 let Predicates = [HasAVX] in {
6902 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6904 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6906 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6908 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6910 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6912 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6916 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6917 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6918 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6919 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6920 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6921 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6923 //===----------------------------------------------------------------------===//
6924 // SSE4.2 - CRC Instructions
6925 //===----------------------------------------------------------------------===//
6927 // No CRC instructions have AVX equivalents
6929 // crc intrinsic instruction
6930 // This set of instructions are only rm, the only difference is the size
6932 let Constraints = "$src1 = $dst" in {
6933 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6934 (ins GR32:$src1, i8mem:$src2),
6935 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6937 (int_x86_sse42_crc32_32_8 GR32:$src1,
6938 (load addr:$src2)))]>;
6939 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6940 (ins GR32:$src1, GR8:$src2),
6941 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6943 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6944 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6945 (ins GR32:$src1, i16mem:$src2),
6946 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6948 (int_x86_sse42_crc32_32_16 GR32:$src1,
6949 (load addr:$src2)))]>,
6951 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6952 (ins GR32:$src1, GR16:$src2),
6953 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6955 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6957 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6958 (ins GR32:$src1, i32mem:$src2),
6959 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6961 (int_x86_sse42_crc32_32_32 GR32:$src1,
6962 (load addr:$src2)))]>;
6963 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6964 (ins GR32:$src1, GR32:$src2),
6965 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6967 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6968 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6969 (ins GR64:$src1, i8mem:$src2),
6970 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6972 (int_x86_sse42_crc32_64_8 GR64:$src1,
6973 (load addr:$src2)))]>,
6975 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6976 (ins GR64:$src1, GR8:$src2),
6977 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6979 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6981 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6982 (ins GR64:$src1, i64mem:$src2),
6983 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6985 (int_x86_sse42_crc32_64_64 GR64:$src1,
6986 (load addr:$src2)))]>,
6988 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6989 (ins GR64:$src1, GR64:$src2),
6990 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6992 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6996 //===----------------------------------------------------------------------===//
6997 // AES-NI Instructions
6998 //===----------------------------------------------------------------------===//
7000 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7001 Intrinsic IntId128, bit Is2Addr = 1> {
7002 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7003 (ins VR128:$src1, VR128:$src2),
7005 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7006 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7007 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7009 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7010 (ins VR128:$src1, i128mem:$src2),
7012 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7013 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7015 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7018 // Perform One Round of an AES Encryption/Decryption Flow
7019 let Predicates = [HasAVX, HasAES] in {
7020 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7021 int_x86_aesni_aesenc, 0>, VEX_4V;
7022 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7023 int_x86_aesni_aesenclast, 0>, VEX_4V;
7024 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7025 int_x86_aesni_aesdec, 0>, VEX_4V;
7026 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7027 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7030 let Constraints = "$src1 = $dst" in {
7031 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7032 int_x86_aesni_aesenc>;
7033 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7034 int_x86_aesni_aesenclast>;
7035 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7036 int_x86_aesni_aesdec>;
7037 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7038 int_x86_aesni_aesdeclast>;
7041 // Perform the AES InvMixColumn Transformation
7042 let Predicates = [HasAVX, HasAES] in {
7043 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7045 "vaesimc\t{$src1, $dst|$dst, $src1}",
7047 (int_x86_aesni_aesimc VR128:$src1))]>,
7049 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7050 (ins i128mem:$src1),
7051 "vaesimc\t{$src1, $dst|$dst, $src1}",
7052 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7055 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7057 "aesimc\t{$src1, $dst|$dst, $src1}",
7059 (int_x86_aesni_aesimc VR128:$src1))]>,
7061 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7062 (ins i128mem:$src1),
7063 "aesimc\t{$src1, $dst|$dst, $src1}",
7064 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7067 // AES Round Key Generation Assist
7068 let Predicates = [HasAVX, HasAES] in {
7069 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7070 (ins VR128:$src1, i8imm:$src2),
7071 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7073 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7075 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7076 (ins i128mem:$src1, i8imm:$src2),
7077 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7079 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7082 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7083 (ins VR128:$src1, i8imm:$src2),
7084 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7086 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7088 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7089 (ins i128mem:$src1, i8imm:$src2),
7090 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7092 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7095 //===----------------------------------------------------------------------===//
7096 // PCLMUL Instructions
7097 //===----------------------------------------------------------------------===//
7099 // AVX carry-less Multiplication instructions
7100 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7101 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7102 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7104 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7106 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7107 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7108 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7109 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7110 (memopv2i64 addr:$src2), imm:$src3))]>;
7112 // Carry-less Multiplication instructions
7113 let Constraints = "$src1 = $dst" in {
7114 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7115 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7116 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7118 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7120 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7121 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7122 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7123 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7124 (memopv2i64 addr:$src2), imm:$src3))]>;
7125 } // Constraints = "$src1 = $dst"
7128 multiclass pclmul_alias<string asm, int immop> {
7129 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7130 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7132 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7133 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7135 def : InstAlias<!strconcat("vpclmul", asm,
7136 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7137 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7139 def : InstAlias<!strconcat("vpclmul", asm,
7140 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7141 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7143 defm : pclmul_alias<"hqhq", 0x11>;
7144 defm : pclmul_alias<"hqlq", 0x01>;
7145 defm : pclmul_alias<"lqhq", 0x10>;
7146 defm : pclmul_alias<"lqlq", 0x00>;
7148 //===----------------------------------------------------------------------===//
7149 // SSE4A Instructions
7150 //===----------------------------------------------------------------------===//
7152 let Predicates = [HasSSE4A] in {
7154 let Constraints = "$src = $dst" in {
7155 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7156 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7157 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7158 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7159 imm:$idx))]>, TB, OpSize;
7160 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7161 (ins VR128:$src, VR128:$mask),
7162 "extrq\t{$mask, $src|$src, $mask}",
7163 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7164 VR128:$mask))]>, TB, OpSize;
7166 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7167 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7168 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7169 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7170 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7171 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7172 (ins VR128:$src, VR128:$mask),
7173 "insertq\t{$mask, $src|$src, $mask}",
7174 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7175 VR128:$mask))]>, XD;
7178 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7179 "movntss\t{$src, $dst|$dst, $src}",
7180 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7182 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7183 "movntsd\t{$src, $dst|$dst, $src}",
7184 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7187 //===----------------------------------------------------------------------===//
7189 //===----------------------------------------------------------------------===//
7191 //===----------------------------------------------------------------------===//
7192 // VBROADCAST - Load from memory and broadcast to all elements of the
7193 // destination operand
7195 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7196 X86MemOperand x86memop, Intrinsic Int> :
7197 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7198 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7199 [(set RC:$dst, (Int addr:$src))]>, VEX;
7201 // AVX2 adds register forms
7202 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7204 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7205 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7206 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7208 let ExeDomain = SSEPackedSingle in {
7209 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7210 int_x86_avx_vbroadcast_ss>;
7211 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7212 int_x86_avx_vbroadcast_ss_256>;
7214 let ExeDomain = SSEPackedDouble in
7215 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7216 int_x86_avx_vbroadcast_sd_256>;
7217 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7218 int_x86_avx_vbroadcastf128_pd_256>;
7220 let ExeDomain = SSEPackedSingle in {
7221 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7222 int_x86_avx2_vbroadcast_ss_ps>;
7223 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7224 int_x86_avx2_vbroadcast_ss_ps_256>;
7226 let ExeDomain = SSEPackedDouble in
7227 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7228 int_x86_avx2_vbroadcast_sd_pd_256>;
7230 let Predicates = [HasAVX2] in
7231 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7232 int_x86_avx2_vbroadcasti128>;
7234 let Predicates = [HasAVX] in
7235 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7236 (VBROADCASTF128 addr:$src)>;
7239 //===----------------------------------------------------------------------===//
7240 // VINSERTF128 - Insert packed floating-point values
7242 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7243 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7244 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7245 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7248 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7249 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7250 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7254 let Predicates = [HasAVX] in {
7255 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7257 (VINSERTF128rr VR256:$src1, VR128:$src2,
7258 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7259 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7261 (VINSERTF128rr VR256:$src1, VR128:$src2,
7262 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7263 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7265 (VINSERTF128rr VR256:$src1, VR128:$src2,
7266 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7267 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7269 (VINSERTF128rr VR256:$src1, VR128:$src2,
7270 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7271 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7273 (VINSERTF128rr VR256:$src1, VR128:$src2,
7274 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7275 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7277 (VINSERTF128rr VR256:$src1, VR128:$src2,
7278 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7280 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7282 (VINSERTF128rm VR256:$src1, addr:$src2,
7283 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7284 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7286 (VINSERTF128rm VR256:$src1, addr:$src2,
7287 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7288 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7290 (VINSERTF128rm VR256:$src1, addr:$src2,
7291 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7294 //===----------------------------------------------------------------------===//
7295 // VEXTRACTF128 - Extract packed floating-point values
7297 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7298 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7299 (ins VR256:$src1, i8imm:$src2),
7300 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7303 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7304 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7305 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7309 // Extract and store.
7310 let Predicates = [HasAVX] in {
7311 def : Pat<(alignedstore (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2), addr:$dst),
7312 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7313 def : Pat<(alignedstore (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2), addr:$dst),
7314 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7315 def : Pat<(alignedstore (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2), addr:$dst),
7316 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7318 def : Pat<(int_x86_sse_storeu_ps addr:$dst, (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2)),
7319 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7320 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2)),
7321 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7322 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, (bc_v16i8 (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2))),
7323 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7327 let Predicates = [HasAVX] in {
7328 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7329 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7330 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7331 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7332 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7333 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7335 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7336 (v4f32 (VEXTRACTF128rr
7337 (v8f32 VR256:$src1),
7338 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7339 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7340 (v2f64 (VEXTRACTF128rr
7341 (v4f64 VR256:$src1),
7342 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7343 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7344 (v2i64 (VEXTRACTF128rr
7345 (v4i64 VR256:$src1),
7346 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7347 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7348 (v4i32 (VEXTRACTF128rr
7349 (v8i32 VR256:$src1),
7350 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7351 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7352 (v8i16 (VEXTRACTF128rr
7353 (v16i16 VR256:$src1),
7354 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7355 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7356 (v16i8 (VEXTRACTF128rr
7357 (v32i8 VR256:$src1),
7358 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7361 //===----------------------------------------------------------------------===//
7362 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7364 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7365 Intrinsic IntLd, Intrinsic IntLd256,
7366 Intrinsic IntSt, Intrinsic IntSt256> {
7367 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7368 (ins VR128:$src1, f128mem:$src2),
7369 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7370 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7372 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7373 (ins VR256:$src1, f256mem:$src2),
7374 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7375 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7377 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7378 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7379 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7380 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7381 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7382 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7383 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7384 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7387 let ExeDomain = SSEPackedSingle in
7388 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7389 int_x86_avx_maskload_ps,
7390 int_x86_avx_maskload_ps_256,
7391 int_x86_avx_maskstore_ps,
7392 int_x86_avx_maskstore_ps_256>;
7393 let ExeDomain = SSEPackedDouble in
7394 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7395 int_x86_avx_maskload_pd,
7396 int_x86_avx_maskload_pd_256,
7397 int_x86_avx_maskstore_pd,
7398 int_x86_avx_maskstore_pd_256>;
7400 //===----------------------------------------------------------------------===//
7401 // VPERMIL - Permute Single and Double Floating-Point Values
7403 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7404 RegisterClass RC, X86MemOperand x86memop_f,
7405 X86MemOperand x86memop_i, PatFrag i_frag,
7406 Intrinsic IntVar, ValueType vt> {
7407 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7408 (ins RC:$src1, RC:$src2),
7409 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7410 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7411 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7412 (ins RC:$src1, x86memop_i:$src2),
7413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7414 [(set RC:$dst, (IntVar RC:$src1,
7415 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7417 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7418 (ins RC:$src1, i8imm:$src2),
7419 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7420 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7421 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7422 (ins x86memop_f:$src1, i8imm:$src2),
7423 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7425 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7428 let ExeDomain = SSEPackedSingle in {
7429 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7430 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7431 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7432 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7434 let ExeDomain = SSEPackedDouble in {
7435 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7436 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7437 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7438 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7441 let Predicates = [HasAVX] in {
7442 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7443 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7444 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7445 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7446 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7448 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7449 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7450 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7452 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7453 (VPERMILPDri VR128:$src1, imm:$imm)>;
7454 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7455 (VPERMILPDmi addr:$src1, imm:$imm)>;
7458 //===----------------------------------------------------------------------===//
7459 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7461 let ExeDomain = SSEPackedSingle in {
7462 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7463 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7464 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7465 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7466 (i8 imm:$src3))))]>, VEX_4V;
7467 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7468 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7469 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7470 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7471 (i8 imm:$src3)))]>, VEX_4V;
7474 let Predicates = [HasAVX] in {
7475 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7476 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7477 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7478 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7479 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7480 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7481 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7482 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7483 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7484 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7486 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7487 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7488 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7489 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7490 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7491 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7492 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7493 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7494 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7495 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7496 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7497 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7498 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7499 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7500 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7501 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7502 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7503 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7506 //===----------------------------------------------------------------------===//
7507 // VZERO - Zero YMM registers
7509 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7510 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7511 // Zero All YMM registers
7512 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7513 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7515 // Zero Upper bits of YMM registers
7516 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7517 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7520 //===----------------------------------------------------------------------===//
7521 // Half precision conversion instructions
7522 //===----------------------------------------------------------------------===//
7523 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7524 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7525 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7526 [(set RC:$dst, (Int VR128:$src))]>,
7528 let neverHasSideEffects = 1, mayLoad = 1 in
7529 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7530 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7533 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7534 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7535 (ins RC:$src1, i32i8imm:$src2),
7536 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7537 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7539 let neverHasSideEffects = 1, mayStore = 1 in
7540 def mr : Ii8<0x1D, MRMDestMem, (outs),
7541 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7542 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7546 let Predicates = [HasAVX, HasF16C] in {
7547 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7548 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7549 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7550 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7553 //===----------------------------------------------------------------------===//
7554 // AVX2 Instructions
7555 //===----------------------------------------------------------------------===//
7557 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7558 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7559 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7560 X86MemOperand x86memop> {
7561 let isCommutable = 1 in
7562 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7563 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7564 !strconcat(OpcodeStr,
7565 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7566 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7568 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7569 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7570 !strconcat(OpcodeStr,
7571 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7574 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7578 let isCommutable = 0 in {
7579 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7580 VR128, memopv2i64, i128mem>;
7581 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7582 VR256, memopv4i64, i256mem>;
7585 //===----------------------------------------------------------------------===//
7586 // VPBROADCAST - Load from memory and broadcast to all elements of the
7587 // destination operand
7589 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7590 X86MemOperand x86memop, PatFrag ld_frag,
7591 Intrinsic Int128, Intrinsic Int256> {
7592 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7593 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7594 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7595 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7598 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7599 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7600 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7601 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7602 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7603 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7605 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7608 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7609 int_x86_avx2_pbroadcastb_128,
7610 int_x86_avx2_pbroadcastb_256>;
7611 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7612 int_x86_avx2_pbroadcastw_128,
7613 int_x86_avx2_pbroadcastw_256>;
7614 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7615 int_x86_avx2_pbroadcastd_128,
7616 int_x86_avx2_pbroadcastd_256>;
7617 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7618 int_x86_avx2_pbroadcastq_128,
7619 int_x86_avx2_pbroadcastq_256>;
7621 let Predicates = [HasAVX2] in {
7622 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7623 (VPBROADCASTBrm addr:$src)>;
7624 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7625 (VPBROADCASTBYrm addr:$src)>;
7626 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7627 (VPBROADCASTWrm addr:$src)>;
7628 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7629 (VPBROADCASTWYrm addr:$src)>;
7630 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7631 (VPBROADCASTDrm addr:$src)>;
7632 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7633 (VPBROADCASTDYrm addr:$src)>;
7634 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7635 (VPBROADCASTQrm addr:$src)>;
7636 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7637 (VPBROADCASTQYrm addr:$src)>;
7639 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
7640 (VPBROADCASTBrr VR128:$src)>;
7641 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
7642 (VPBROADCASTBYrr VR128:$src)>;
7643 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
7644 (VPBROADCASTWrr VR128:$src)>;
7645 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
7646 (VPBROADCASTWYrr VR128:$src)>;
7647 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
7648 (VPBROADCASTDrr VR128:$src)>;
7649 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
7650 (VPBROADCASTDYrr VR128:$src)>;
7651 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
7652 (VPBROADCASTQrr VR128:$src)>;
7653 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
7654 (VPBROADCASTQYrr VR128:$src)>;
7655 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
7656 (VBROADCASTSSrr VR128:$src)>;
7657 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
7658 (VBROADCASTSSYrr VR128:$src)>;
7659 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
7660 (VPBROADCASTQrr VR128:$src)>;
7661 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
7662 (VBROADCASTSDYrr VR128:$src)>;
7664 // Provide fallback in case the load node that is used in the patterns above
7665 // is used by additional users, which prevents the pattern selection.
7666 let AddedComplexity = 20 in {
7667 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7668 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7669 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7670 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7671 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7672 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
7674 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7675 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7676 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7677 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7678 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7679 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
7683 // AVX1 broadcast patterns
7684 let Predicates = [HasAVX] in {
7685 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7686 (VBROADCASTSSYrm addr:$src)>;
7687 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7688 (VBROADCASTSDYrm addr:$src)>;
7689 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7690 (VBROADCASTSSYrm addr:$src)>;
7691 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7692 (VBROADCASTSDYrm addr:$src)>;
7693 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7694 (VBROADCASTSSrm addr:$src)>;
7695 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7696 (VBROADCASTSSrm addr:$src)>;
7698 // Provide fallback in case the load node that is used in the patterns above
7699 // is used by additional users, which prevents the pattern selection.
7700 let AddedComplexity = 20 in {
7701 // 128bit broadcasts:
7702 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7703 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
7704 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7705 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7706 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
7707 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
7708 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7709 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7710 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
7711 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
7713 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7714 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
7715 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7716 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7717 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
7718 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
7719 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7720 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7721 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
7722 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
7726 //===----------------------------------------------------------------------===//
7727 // VPERM - Permute instructions
7730 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7732 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7733 (ins VR256:$src1, VR256:$src2),
7734 !strconcat(OpcodeStr,
7735 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7737 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7738 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7739 (ins VR256:$src1, i256mem:$src2),
7740 !strconcat(OpcodeStr,
7741 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7743 (OpVT (X86VPermv VR256:$src1,
7744 (bitconvert (mem_frag addr:$src2)))))]>,
7748 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7749 let ExeDomain = SSEPackedSingle in
7750 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7752 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7754 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7755 (ins VR256:$src1, i8imm:$src2),
7756 !strconcat(OpcodeStr,
7757 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7759 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7760 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7761 (ins i256mem:$src1, i8imm:$src2),
7762 !strconcat(OpcodeStr,
7763 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7765 (OpVT (X86VPermi (mem_frag addr:$src1),
7766 (i8 imm:$src2))))]>, VEX;
7769 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7770 let ExeDomain = SSEPackedDouble in
7771 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7773 //===----------------------------------------------------------------------===//
7774 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7776 let AddedComplexity = 1 in {
7777 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7778 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7779 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7780 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7781 (i8 imm:$src3))))]>, VEX_4V;
7782 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7783 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7784 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7785 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7786 (i8 imm:$src3)))]>, VEX_4V;
7789 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7790 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7791 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7792 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7793 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7794 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7795 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7797 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7799 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7800 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7801 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7802 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7803 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7805 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7809 //===----------------------------------------------------------------------===//
7810 // VINSERTI128 - Insert packed integer values
7812 let neverHasSideEffects = 1 in {
7813 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7814 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7815 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7818 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7819 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7820 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7824 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7825 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7827 (VINSERTI128rr VR256:$src1, VR128:$src2,
7828 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7829 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7831 (VINSERTI128rr VR256:$src1, VR128:$src2,
7832 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7833 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7835 (VINSERTI128rr VR256:$src1, VR128:$src2,
7836 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7837 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7839 (VINSERTI128rr VR256:$src1, VR128:$src2,
7840 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7843 //===----------------------------------------------------------------------===//
7844 // VEXTRACTI128 - Extract packed integer values
7846 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7847 (ins VR256:$src1, i8imm:$src2),
7848 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7850 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7852 let neverHasSideEffects = 1, mayStore = 1 in
7853 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7854 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7855 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7857 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7858 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7859 (v2i64 (VEXTRACTI128rr
7860 (v4i64 VR256:$src1),
7861 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7862 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7863 (v4i32 (VEXTRACTI128rr
7864 (v8i32 VR256:$src1),
7865 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7866 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7867 (v8i16 (VEXTRACTI128rr
7868 (v16i16 VR256:$src1),
7869 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7870 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7871 (v16i8 (VEXTRACTI128rr
7872 (v32i8 VR256:$src1),
7873 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7876 //===----------------------------------------------------------------------===//
7877 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7879 multiclass avx2_pmovmask<string OpcodeStr,
7880 Intrinsic IntLd128, Intrinsic IntLd256,
7881 Intrinsic IntSt128, Intrinsic IntSt256> {
7882 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7883 (ins VR128:$src1, i128mem:$src2),
7884 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7885 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7886 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7887 (ins VR256:$src1, i256mem:$src2),
7888 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7889 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7890 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7891 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7892 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7893 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7894 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7895 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7896 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7897 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7900 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7901 int_x86_avx2_maskload_d,
7902 int_x86_avx2_maskload_d_256,
7903 int_x86_avx2_maskstore_d,
7904 int_x86_avx2_maskstore_d_256>;
7905 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7906 int_x86_avx2_maskload_q,
7907 int_x86_avx2_maskload_q_256,
7908 int_x86_avx2_maskstore_q,
7909 int_x86_avx2_maskstore_q_256>, VEX_W;
7912 //===----------------------------------------------------------------------===//
7913 // Variable Bit Shifts
7915 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7916 ValueType vt128, ValueType vt256> {
7917 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7918 (ins VR128:$src1, VR128:$src2),
7919 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7921 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7923 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7924 (ins VR128:$src1, i128mem:$src2),
7925 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7927 (vt128 (OpNode VR128:$src1,
7928 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7930 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7931 (ins VR256:$src1, VR256:$src2),
7932 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7934 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
7936 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7937 (ins VR256:$src1, i256mem:$src2),
7938 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7940 (vt256 (OpNode VR256:$src1,
7941 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
7945 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
7946 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
7947 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
7948 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
7949 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
7951 //===----------------------------------------------------------------------===//
7952 // VGATHER - GATHER Operations
7953 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
7954 X86MemOperand memop128, X86MemOperand memop256> {
7955 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
7956 (ins VR128:$src1, memop128:$src2, VR128:$mask),
7957 !strconcat(OpcodeStr,
7958 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
7960 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
7961 (ins RC256:$src1, memop256:$src2, RC256:$mask),
7962 !strconcat(OpcodeStr,
7963 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
7964 []>, VEX_4VOp3, VEX_L;
7967 let Constraints = "$src1 = $dst, $mask = $mask_wb" in {
7968 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
7969 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
7970 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
7971 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
7972 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
7973 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
7974 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
7975 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;