1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // Non-instruction patterns
120 //===----------------------------------------------------------------------===//
122 // A vector extract of the first f32 position is a subregister copy
123 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
124 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
126 // A 128-bit subvector extract from the first 256-bit vector position
127 // is a subregister copy that needs no instruction.
128 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
129 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
130 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
131 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
133 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
134 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
135 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
136 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
138 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
139 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
140 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
141 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
143 // A 128-bit subvector insert to the first 256-bit vector position
144 // is a subregister copy that needs no instruction.
145 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
146 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
147 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
148 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
149 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
158 // Implicitly promote a 32-bit scalar to a vector.
159 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
160 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
161 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
162 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
163 // Implicitly promote a 64-bit scalar to a vector.
164 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
165 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
166 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
167 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
169 // Bitcasts between 128-bit vector types. Return the original type since
170 // no instruction is needed for the conversion
171 let Predicates = [HasXMMInt] in {
172 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
173 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
174 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
175 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
178 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
179 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
183 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
184 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
188 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
189 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
193 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
194 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
198 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
199 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
204 // Bitcasts between 256-bit vector types. Return the original type since
205 // no instruction is needed for the conversion
206 let Predicates = [HasAVX] in {
207 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
208 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
209 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
210 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
213 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
214 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
218 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
219 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
223 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
224 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
228 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
229 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
233 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
234 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
239 //===----------------------------------------------------------------------===//
240 // AVX & SSE - Zero/One Vectors
241 //===----------------------------------------------------------------------===//
243 // Alias instructions that map zero vector to pxor / xorp* for sse.
244 // We set canFoldAsLoad because this can be converted to a constant-pool
245 // load of an all-zeros value if folding it would be beneficial.
246 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
247 // JIT implementation, it does not expand the instructions below like
248 // X86MCInstLower does.
249 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
250 isCodeGenOnly = 1 in {
251 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
252 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
253 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
254 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
255 let ExeDomain = SSEPackedInt in
256 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
257 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
260 // The same as done above but for AVX. The 128-bit versions are the
261 // same, but re-encoded. The 256-bit does not support PI version, and
262 // doesn't need it because on sandy bridge the register is set to zero
263 // at the rename stage without using any execution unit, so SET0PSY
264 // and SET0PDY can be used for vector int instructions without penalty
265 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
266 // JIT implementatioan, it does not expand the instructions below like
267 // X86MCInstLower does.
268 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
269 isCodeGenOnly = 1, Predicates = [HasAVX] in {
270 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
271 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
272 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
273 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
274 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
275 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
276 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
277 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
278 let ExeDomain = SSEPackedInt in
279 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
280 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
283 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
284 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
285 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
287 // AVX has no support for 256-bit integer instructions, but since the 128-bit
288 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
289 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
290 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
291 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
293 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
294 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
295 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
297 //===----------------------------------------------------------------------===//
298 // SSE 1 & 2 - Move Instructions
299 //===----------------------------------------------------------------------===//
301 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
302 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
303 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
305 // Loading from memory automatically zeroing upper bits.
306 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
307 PatFrag mem_pat, string OpcodeStr> :
308 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
309 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
310 [(set RC:$dst, (mem_pat addr:$src))]>;
312 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
313 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
314 // is used instead. Register-to-register movss/movsd is not modeled as an
315 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
316 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
317 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
318 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
319 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
320 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
322 let canFoldAsLoad = 1, isReMaterializable = 1 in {
323 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
325 let AddedComplexity = 20 in
326 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
329 let Constraints = "$src1 = $dst" in {
330 def MOVSSrr : sse12_move_rr<FR32, v4f32,
331 "movss\t{$src2, $dst|$dst, $src2}">, XS;
332 def MOVSDrr : sse12_move_rr<FR64, v2f64,
333 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
336 let canFoldAsLoad = 1, isReMaterializable = 1 in {
337 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
339 let AddedComplexity = 20 in
340 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
343 let AddedComplexity = 15 in {
344 // Extract the low 32-bit value from one vector and insert it into another.
345 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
346 (MOVSSrr (v4f32 VR128:$src1),
347 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
348 // Extract the low 64-bit value from one vector and insert it into another.
349 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
350 (MOVSDrr (v2f64 VR128:$src1),
351 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
354 let AddedComplexity = 20 in {
355 let Predicates = [HasSSE1] in {
356 // MOVSSrm zeros the high parts of the register; represent this
357 // with SUBREG_TO_REG.
358 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
359 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
360 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
361 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
362 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
363 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
365 let Predicates = [HasSSE2] in {
366 // MOVSDrm zeros the high parts of the register; represent this
367 // with SUBREG_TO_REG.
368 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
369 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
370 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
371 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
372 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
373 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
374 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
375 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
376 def : Pat<(v2f64 (X86vzload addr:$src)),
377 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
381 let AddedComplexity = 20, Predicates = [HasAVX] in {
382 // MOVSSrm zeros the high parts of the register; represent this
383 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
384 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
385 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
386 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
387 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
388 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
389 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
390 // MOVSDrm zeros the high parts of the register; represent this
391 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
392 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
393 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
394 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
395 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
396 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
397 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
398 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
399 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
400 def : Pat<(v2f64 (X86vzload addr:$src)),
401 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
402 // Represent the same patterns above but in the form they appear for
404 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
405 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
406 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
407 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
408 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
409 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
412 // Store scalar value to memory.
413 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
414 "movss\t{$src, $dst|$dst, $src}",
415 [(store FR32:$src, addr:$dst)]>;
416 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
417 "movsd\t{$src, $dst|$dst, $src}",
418 [(store FR64:$src, addr:$dst)]>;
420 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
421 "movss\t{$src, $dst|$dst, $src}",
422 [(store FR32:$src, addr:$dst)]>, XS, VEX;
423 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
424 "movsd\t{$src, $dst|$dst, $src}",
425 [(store FR64:$src, addr:$dst)]>, XD, VEX;
427 // Extract and store.
428 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
431 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
432 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
435 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
437 // Move Aligned/Unaligned floating point values
438 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
439 X86MemOperand x86memop, PatFrag ld_frag,
440 string asm, Domain d,
441 bit IsReMaterializable = 1> {
442 let neverHasSideEffects = 1 in
443 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
444 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
445 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
446 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
447 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
448 [(set RC:$dst, (ld_frag addr:$src))], d>;
451 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
452 "movaps", SSEPackedSingle>, TB, VEX;
453 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
454 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
455 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
456 "movups", SSEPackedSingle>, TB, VEX;
457 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
458 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
460 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
461 "movaps", SSEPackedSingle>, TB, VEX;
462 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
463 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
464 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
465 "movups", SSEPackedSingle>, TB, VEX;
466 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
467 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
468 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
469 "movaps", SSEPackedSingle>, TB;
470 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
471 "movapd", SSEPackedDouble>, TB, OpSize;
472 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
473 "movups", SSEPackedSingle>, TB;
474 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
475 "movupd", SSEPackedDouble, 0>, TB, OpSize;
477 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
478 "movaps\t{$src, $dst|$dst, $src}",
479 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
480 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
481 "movapd\t{$src, $dst|$dst, $src}",
482 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
483 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
484 "movups\t{$src, $dst|$dst, $src}",
485 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
486 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
487 "movupd\t{$src, $dst|$dst, $src}",
488 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
489 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
490 "movaps\t{$src, $dst|$dst, $src}",
491 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
492 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
493 "movapd\t{$src, $dst|$dst, $src}",
494 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
495 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
496 "movups\t{$src, $dst|$dst, $src}",
497 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
498 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
499 "movupd\t{$src, $dst|$dst, $src}",
500 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
502 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
503 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
504 (VMOVUPSYmr addr:$dst, VR256:$src)>;
506 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
507 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
508 (VMOVUPDYmr addr:$dst, VR256:$src)>;
510 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
511 "movaps\t{$src, $dst|$dst, $src}",
512 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
513 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
514 "movapd\t{$src, $dst|$dst, $src}",
515 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
516 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
517 "movups\t{$src, $dst|$dst, $src}",
518 [(store (v4f32 VR128:$src), addr:$dst)]>;
519 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
520 "movupd\t{$src, $dst|$dst, $src}",
521 [(store (v2f64 VR128:$src), addr:$dst)]>;
523 // Intrinsic forms of MOVUPS/D load and store
524 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
525 (ins f128mem:$dst, VR128:$src),
526 "movups\t{$src, $dst|$dst, $src}",
527 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
528 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
529 (ins f128mem:$dst, VR128:$src),
530 "movupd\t{$src, $dst|$dst, $src}",
531 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
533 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
534 "movups\t{$src, $dst|$dst, $src}",
535 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
536 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
537 "movupd\t{$src, $dst|$dst, $src}",
538 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
540 // Move Low/High packed floating point values
541 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
542 PatFrag mov_frag, string base_opc,
544 def PSrm : PI<opc, MRMSrcMem,
545 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
546 !strconcat(base_opc, "s", asm_opr),
549 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
550 SSEPackedSingle>, TB;
552 def PDrm : PI<opc, MRMSrcMem,
553 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
554 !strconcat(base_opc, "d", asm_opr),
555 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
556 (scalar_to_vector (loadf64 addr:$src2)))))],
557 SSEPackedDouble>, TB, OpSize;
560 let AddedComplexity = 20 in {
561 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
562 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
563 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
564 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
566 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
567 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
568 "\t{$src2, $dst|$dst, $src2}">;
569 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
570 "\t{$src2, $dst|$dst, $src2}">;
573 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
574 "movlps\t{$src, $dst|$dst, $src}",
575 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
576 (iPTR 0))), addr:$dst)]>, VEX;
577 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
578 "movlpd\t{$src, $dst|$dst, $src}",
579 [(store (f64 (vector_extract (v2f64 VR128:$src),
580 (iPTR 0))), addr:$dst)]>, VEX;
581 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
582 "movlps\t{$src, $dst|$dst, $src}",
583 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
584 (iPTR 0))), addr:$dst)]>;
585 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
586 "movlpd\t{$src, $dst|$dst, $src}",
587 [(store (f64 (vector_extract (v2f64 VR128:$src),
588 (iPTR 0))), addr:$dst)]>;
590 // v2f64 extract element 1 is always custom lowered to unpack high to low
591 // and extract element 0 so the non-store version isn't too horrible.
592 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
593 "movhps\t{$src, $dst|$dst, $src}",
594 [(store (f64 (vector_extract
595 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
596 (undef)), (iPTR 0))), addr:$dst)]>,
598 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
599 "movhpd\t{$src, $dst|$dst, $src}",
600 [(store (f64 (vector_extract
601 (v2f64 (unpckh VR128:$src, (undef))),
602 (iPTR 0))), addr:$dst)]>,
604 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
605 "movhps\t{$src, $dst|$dst, $src}",
606 [(store (f64 (vector_extract
607 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
608 (undef)), (iPTR 0))), addr:$dst)]>;
609 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
610 "movhpd\t{$src, $dst|$dst, $src}",
611 [(store (f64 (vector_extract
612 (v2f64 (unpckh VR128:$src, (undef))),
613 (iPTR 0))), addr:$dst)]>;
615 let AddedComplexity = 20 in {
616 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
617 (ins VR128:$src1, VR128:$src2),
618 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
620 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
622 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
623 (ins VR128:$src1, VR128:$src2),
624 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
626 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
629 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
630 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
631 (ins VR128:$src1, VR128:$src2),
632 "movlhps\t{$src2, $dst|$dst, $src2}",
634 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
635 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
636 (ins VR128:$src1, VR128:$src2),
637 "movhlps\t{$src2, $dst|$dst, $src2}",
639 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
642 let Predicates = [HasAVX] in {
644 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
645 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
646 def : Pat<(X86Movlhps VR128:$src1,
647 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
648 (VMOVHPSrm VR128:$src1, addr:$src2)>;
649 def : Pat<(X86Movlhps VR128:$src1,
650 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
651 (VMOVHPSrm VR128:$src1, addr:$src2)>;
654 let AddedComplexity = 20 in {
655 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
656 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
657 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
658 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
660 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
661 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
662 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
664 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
665 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
666 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
667 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
668 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
669 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
672 let AddedComplexity = 20 in {
673 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
674 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
675 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
677 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
678 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
679 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
680 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
681 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
684 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
685 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
686 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
687 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
690 let Predicates = [HasSSE1] in {
692 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
693 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
694 def : Pat<(X86Movlhps VR128:$src1,
695 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
696 (MOVHPSrm VR128:$src1, addr:$src2)>;
697 def : Pat<(X86Movlhps VR128:$src1,
698 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
699 (MOVHPSrm VR128:$src1, addr:$src2)>;
702 let AddedComplexity = 20 in {
703 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
704 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
705 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
706 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
708 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
709 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
710 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
712 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
713 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
714 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
715 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
716 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
717 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
720 let AddedComplexity = 20 in {
721 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
722 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
723 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
725 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
726 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
727 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
728 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
729 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
732 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
733 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
734 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
735 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
738 //===----------------------------------------------------------------------===//
739 // SSE 1 & 2 - Conversion Instructions
740 //===----------------------------------------------------------------------===//
742 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
743 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
745 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
746 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
747 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
748 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
751 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
752 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
753 string asm, Domain d> {
754 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
755 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
756 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
757 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
760 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
761 X86MemOperand x86memop, string asm> {
762 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
763 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
764 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
765 (ins DstRC:$src1, x86memop:$src),
766 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
769 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
770 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
771 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
772 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
774 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
775 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
776 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
777 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
780 // The assembler can recognize rr 64-bit instructions by seeing a rxx
781 // register, but the same isn't true when only using memory operands,
782 // provide other assembly "l" and "q" forms to address this explicitly
783 // where appropriate to do so.
784 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
786 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
788 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
790 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
792 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
795 let Predicates = [HasAVX] in {
796 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
797 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
798 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
799 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
800 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
801 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
802 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
803 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
805 def : Pat<(f32 (sint_to_fp GR32:$src)),
806 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
807 def : Pat<(f32 (sint_to_fp GR64:$src)),
808 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
809 def : Pat<(f64 (sint_to_fp GR32:$src)),
810 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
811 def : Pat<(f64 (sint_to_fp GR64:$src)),
812 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
815 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
816 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
817 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
818 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
819 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
820 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
821 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
822 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
823 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
824 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
825 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
826 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
827 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
828 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
829 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
830 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
832 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
833 // and/or XMM operand(s).
835 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
836 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
838 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
839 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
840 [(set DstRC:$dst, (Int SrcRC:$src))]>;
841 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
842 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
843 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
846 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
847 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
848 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
849 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
851 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
852 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
853 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
854 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
855 (ins DstRC:$src1, x86memop:$src2),
857 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
858 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
859 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
862 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
863 f128mem, load, "cvtsd2si">, XD, VEX;
864 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
865 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
868 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
869 // Get rid of this hack or rename the intrinsics, there are several
870 // intructions that only match with the intrinsic form, why create duplicates
871 // to let them be recognized by the assembler?
872 let Pattern = []<dag> in {
873 defm VCVTSD2SI : sse12_cvt_s<0x2D, FR64, GR32, undef, f64mem, load,
874 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
875 defm VCVTSD2SI64 : sse12_cvt_s<0x2D, FR64, GR64, undef, f64mem, load,
876 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
878 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
879 f128mem, load, "cvtsd2si{l}">, XD;
880 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
881 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
884 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
885 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
886 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
887 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
889 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
890 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
891 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
892 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
895 let Constraints = "$src1 = $dst" in {
896 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
897 int_x86_sse_cvtsi2ss, i32mem, loadi32,
899 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
900 int_x86_sse_cvtsi642ss, i64mem, loadi64,
901 "cvtsi2ss{q}">, XS, REX_W;
902 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
903 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
905 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
906 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
907 "cvtsi2sd">, XD, REX_W;
912 // Aliases for intrinsics
913 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
914 f32mem, load, "cvttss2si">, XS, VEX;
915 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
916 int_x86_sse_cvttss2si64, f32mem, load,
917 "cvttss2si">, XS, VEX, VEX_W;
918 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
919 f128mem, load, "cvttsd2si">, XD, VEX;
920 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
921 int_x86_sse2_cvttsd2si64, f128mem, load,
922 "cvttsd2si">, XD, VEX, VEX_W;
923 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
924 f32mem, load, "cvttss2si">, XS;
925 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
926 int_x86_sse_cvttss2si64, f32mem, load,
927 "cvttss2si{q}">, XS, REX_W;
928 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
929 f128mem, load, "cvttsd2si">, XD;
930 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
931 int_x86_sse2_cvttsd2si64, f128mem, load,
932 "cvttsd2si{q}">, XD, REX_W;
934 let Pattern = []<dag> in {
935 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
936 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
937 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
938 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
940 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
941 "cvtdq2ps\t{$src, $dst|$dst, $src}",
942 SSEPackedSingle>, TB, VEX;
943 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
944 "cvtdq2ps\t{$src, $dst|$dst, $src}",
945 SSEPackedSingle>, TB, VEX;
948 let Pattern = []<dag> in {
949 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
950 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
951 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
952 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
953 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
954 "cvtdq2ps\t{$src, $dst|$dst, $src}",
955 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
958 let Predicates = [HasSSE1] in {
959 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
960 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
961 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
962 (CVTSS2SIrm addr:$src)>;
963 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
964 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
965 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
966 (CVTSS2SI64rm addr:$src)>;
969 let Predicates = [HasAVX] in {
970 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
971 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
972 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
973 (VCVTSS2SIrm addr:$src)>;
974 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
975 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
976 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
977 (VCVTSS2SI64rm addr:$src)>;
982 // Convert scalar double to scalar single
983 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
984 (ins FR64:$src1, FR64:$src2),
985 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
987 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
988 (ins FR64:$src1, f64mem:$src2),
989 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
990 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
991 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
994 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
995 "cvtsd2ss\t{$src, $dst|$dst, $src}",
996 [(set FR32:$dst, (fround FR64:$src))]>;
997 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
998 "cvtsd2ss\t{$src, $dst|$dst, $src}",
999 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1000 Requires<[HasSSE2, OptForSize]>;
1002 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1003 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1005 let Constraints = "$src1 = $dst" in
1006 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1007 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1009 // Convert scalar single to scalar double
1010 // SSE2 instructions with XS prefix
1011 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1012 (ins FR32:$src1, FR32:$src2),
1013 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1014 []>, XS, Requires<[HasAVX]>, VEX_4V;
1015 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1016 (ins FR32:$src1, f32mem:$src2),
1017 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1018 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
1020 let Predicates = [HasAVX] in {
1021 def : Pat<(f64 (fextend FR32:$src)),
1022 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1023 def : Pat<(fextend (loadf32 addr:$src)),
1024 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1025 def : Pat<(extloadf32 addr:$src),
1026 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1029 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1030 "cvtss2sd\t{$src, $dst|$dst, $src}",
1031 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1032 Requires<[HasSSE2]>;
1033 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1034 "cvtss2sd\t{$src, $dst|$dst, $src}",
1035 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1036 Requires<[HasSSE2, OptForSize]>;
1038 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1039 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1040 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1041 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1042 VR128:$src2))]>, XS, VEX_4V,
1044 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1045 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1046 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1047 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1048 (load addr:$src2)))]>, XS, VEX_4V,
1050 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1051 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1052 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1053 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1054 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1055 VR128:$src2))]>, XS,
1056 Requires<[HasSSE2]>;
1057 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1058 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1059 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1060 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1061 (load addr:$src2)))]>, XS,
1062 Requires<[HasSSE2]>;
1065 def : Pat<(extloadf32 addr:$src),
1066 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1067 Requires<[HasSSE2, OptForSpeed]>;
1069 // Convert doubleword to packed single/double fp
1070 // SSE2 instructions without OpSize prefix
1071 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1072 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1073 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1074 TB, VEX, Requires<[HasAVX]>;
1075 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1076 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1077 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1078 (bitconvert (memopv2i64 addr:$src))))]>,
1079 TB, VEX, Requires<[HasAVX]>;
1080 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1081 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1082 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1083 TB, Requires<[HasSSE2]>;
1084 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1085 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1086 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1087 (bitconvert (memopv2i64 addr:$src))))]>,
1088 TB, Requires<[HasSSE2]>;
1090 // FIXME: why the non-intrinsic version is described as SSE3?
1091 // SSE2 instructions with XS prefix
1092 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1093 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1094 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1095 XS, VEX, Requires<[HasAVX]>;
1096 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1097 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1098 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1099 (bitconvert (memopv2i64 addr:$src))))]>,
1100 XS, VEX, Requires<[HasAVX]>;
1101 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1102 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1103 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1104 XS, Requires<[HasSSE2]>;
1105 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1106 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1107 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1108 (bitconvert (memopv2i64 addr:$src))))]>,
1109 XS, Requires<[HasSSE2]>;
1112 // Convert packed single/double fp to doubleword
1113 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1114 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1115 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1116 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1117 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1118 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1119 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1120 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1121 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1122 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1123 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1124 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1126 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1127 "cvtps2dq\t{$src, $dst|$dst, $src}",
1128 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1130 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1132 "cvtps2dq\t{$src, $dst|$dst, $src}",
1133 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1134 (memop addr:$src)))]>, VEX;
1135 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1136 "cvtps2dq\t{$src, $dst|$dst, $src}",
1137 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1138 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1139 "cvtps2dq\t{$src, $dst|$dst, $src}",
1140 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1141 (memop addr:$src)))]>;
1143 // SSE2 packed instructions with XD prefix
1144 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1145 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1146 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1147 XD, VEX, Requires<[HasAVX]>;
1148 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1149 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1150 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1151 (memop addr:$src)))]>,
1152 XD, VEX, Requires<[HasAVX]>;
1153 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1154 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1155 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1156 XD, Requires<[HasSSE2]>;
1157 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1158 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1159 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1160 (memop addr:$src)))]>,
1161 XD, Requires<[HasSSE2]>;
1164 // Convert with truncation packed single/double fp to doubleword
1165 // SSE2 packed instructions with XS prefix
1166 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1167 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1168 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1169 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1170 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1171 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1172 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1173 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1174 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1175 "cvttps2dq\t{$src, $dst|$dst, $src}",
1177 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1178 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1179 "cvttps2dq\t{$src, $dst|$dst, $src}",
1181 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1183 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1184 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1186 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1187 XS, VEX, Requires<[HasAVX]>;
1188 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1189 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1190 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1191 (memop addr:$src)))]>,
1192 XS, VEX, Requires<[HasAVX]>;
1194 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1195 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
1196 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1197 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
1199 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1200 (Int_VCVTDQ2PSrr VR128:$src)>, Requires<[HasAVX]>;
1201 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1202 (VCVTTPS2DQrr VR128:$src)>, Requires<[HasAVX]>;
1203 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1204 (VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
1205 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1206 (VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
1208 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
1210 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1211 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1213 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1215 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1216 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1217 (memop addr:$src)))]>, VEX;
1218 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1219 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1220 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1221 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1222 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1223 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1224 (memop addr:$src)))]>;
1226 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1227 // register, but the same isn't true when using memory operands instead.
1228 // Provide other assembly rr and rm forms to address this explicitly.
1229 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1230 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1231 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1232 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1235 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1236 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1237 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1238 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1241 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1242 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1243 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1244 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1246 // Convert packed single to packed double
1247 let Predicates = [HasAVX] in {
1248 // SSE2 instructions without OpSize prefix
1249 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1250 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1251 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1252 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1253 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1254 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1255 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1256 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1258 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1259 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1260 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1261 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1263 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1264 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1265 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1266 TB, VEX, Requires<[HasAVX]>;
1267 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1268 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1269 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1270 (load addr:$src)))]>,
1271 TB, VEX, Requires<[HasAVX]>;
1272 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1273 "cvtps2pd\t{$src, $dst|$dst, $src}",
1274 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1275 TB, Requires<[HasSSE2]>;
1276 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1277 "cvtps2pd\t{$src, $dst|$dst, $src}",
1278 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1279 (load addr:$src)))]>,
1280 TB, Requires<[HasSSE2]>;
1282 // Convert packed double to packed single
1283 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1284 // register, but the same isn't true when using memory operands instead.
1285 // Provide other assembly rr and rm forms to address this explicitly.
1286 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1287 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1288 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1289 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1292 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1293 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1294 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1295 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1298 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1299 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1300 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1301 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1302 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1303 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1304 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1305 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1308 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1309 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1310 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1311 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1313 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1314 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1315 (memop addr:$src)))]>;
1316 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1317 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1318 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1319 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1320 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1321 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1322 (memop addr:$src)))]>;
1324 // AVX 256-bit register conversion intrinsics
1325 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1326 // whenever possible to avoid declaring two versions of each one.
1327 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1328 (VCVTDQ2PSYrr VR256:$src)>;
1329 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1330 (VCVTDQ2PSYrm addr:$src)>;
1332 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1333 (VCVTPD2PSYrr VR256:$src)>;
1334 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1335 (VCVTPD2PSYrm addr:$src)>;
1337 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1338 (VCVTPS2DQYrr VR256:$src)>;
1339 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1340 (VCVTPS2DQYrm addr:$src)>;
1342 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1343 (VCVTPS2PDYrr VR128:$src)>;
1344 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1345 (VCVTPS2PDYrm addr:$src)>;
1347 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1348 (VCVTTPD2DQYrr VR256:$src)>;
1349 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1350 (VCVTTPD2DQYrm addr:$src)>;
1352 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1353 (VCVTTPS2DQYrr VR256:$src)>;
1354 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1355 (VCVTTPS2DQYrm addr:$src)>;
1357 // Match fround and fextend for 128/256-bit conversions
1358 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1359 (VCVTPD2PSYrr VR256:$src)>;
1360 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1361 (VCVTPD2PSYrm addr:$src)>;
1363 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1364 (VCVTPS2PDYrr VR128:$src)>;
1365 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1366 (VCVTPS2PDYrm addr:$src)>;
1368 //===----------------------------------------------------------------------===//
1369 // SSE 1 & 2 - Compare Instructions
1370 //===----------------------------------------------------------------------===//
1372 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1373 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1374 string asm, string asm_alt> {
1375 let isAsmParserOnly = 1 in {
1376 def rr : SIi8<0xC2, MRMSrcReg,
1377 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1380 def rm : SIi8<0xC2, MRMSrcMem,
1381 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1385 // Accept explicit immediate argument form instead of comparison code.
1386 def rr_alt : SIi8<0xC2, MRMSrcReg,
1387 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1390 def rm_alt : SIi8<0xC2, MRMSrcMem,
1391 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1395 let neverHasSideEffects = 1 in {
1396 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1397 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1398 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1400 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1401 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1402 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1406 let Constraints = "$src1 = $dst" in {
1407 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1408 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1409 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1410 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1411 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1412 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1413 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1414 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1415 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1416 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1417 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1418 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1419 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1420 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1421 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1422 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1424 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1425 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1426 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1427 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1428 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1429 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1430 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1431 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1432 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1433 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1434 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1435 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1436 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1439 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1440 Intrinsic Int, string asm> {
1441 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1442 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1443 [(set VR128:$dst, (Int VR128:$src1,
1444 VR128:$src, imm:$cc))]>;
1445 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1446 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1447 [(set VR128:$dst, (Int VR128:$src1,
1448 (load addr:$src), imm:$cc))]>;
1451 // Aliases to match intrinsics which expect XMM operand(s).
1452 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1453 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1455 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1456 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1458 let Constraints = "$src1 = $dst" in {
1459 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1460 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1461 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1462 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1466 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1467 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1468 ValueType vt, X86MemOperand x86memop,
1469 PatFrag ld_frag, string OpcodeStr, Domain d> {
1470 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1471 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1472 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1473 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1474 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1475 [(set EFLAGS, (OpNode (vt RC:$src1),
1476 (ld_frag addr:$src2)))], d>;
1479 let Defs = [EFLAGS] in {
1480 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1481 "ucomiss", SSEPackedSingle>, TB, VEX;
1482 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1483 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
1484 let Pattern = []<dag> in {
1485 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1486 "comiss", SSEPackedSingle>, TB, VEX;
1487 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1488 "comisd", SSEPackedDouble>, TB, OpSize, VEX;
1491 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1492 load, "ucomiss", SSEPackedSingle>, TB, VEX;
1493 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1494 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
1496 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1497 load, "comiss", SSEPackedSingle>, TB, VEX;
1498 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1499 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
1500 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1501 "ucomiss", SSEPackedSingle>, TB;
1502 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1503 "ucomisd", SSEPackedDouble>, TB, OpSize;
1505 let Pattern = []<dag> in {
1506 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1507 "comiss", SSEPackedSingle>, TB;
1508 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1509 "comisd", SSEPackedDouble>, TB, OpSize;
1512 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1513 load, "ucomiss", SSEPackedSingle>, TB;
1514 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1515 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1517 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1518 "comiss", SSEPackedSingle>, TB;
1519 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1520 "comisd", SSEPackedDouble>, TB, OpSize;
1521 } // Defs = [EFLAGS]
1523 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1524 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1525 Intrinsic Int, string asm, string asm_alt,
1527 let isAsmParserOnly = 1 in {
1528 def rri : PIi8<0xC2, MRMSrcReg,
1529 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1530 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1531 def rmi : PIi8<0xC2, MRMSrcMem,
1532 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1533 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1536 // Accept explicit immediate argument form instead of comparison code.
1537 def rri_alt : PIi8<0xC2, MRMSrcReg,
1538 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1540 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1541 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1545 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1546 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1547 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1548 SSEPackedSingle>, TB, VEX_4V;
1549 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1550 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1551 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1552 SSEPackedDouble>, TB, OpSize, VEX_4V;
1553 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1554 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1555 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1556 SSEPackedSingle>, TB, VEX_4V;
1557 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1558 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1559 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1560 SSEPackedDouble>, TB, OpSize, VEX_4V;
1561 let Constraints = "$src1 = $dst" in {
1562 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1563 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1564 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1565 SSEPackedSingle>, TB;
1566 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1567 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1568 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1569 SSEPackedDouble>, TB, OpSize;
1572 let Predicates = [HasSSE1] in {
1573 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1574 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1575 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1576 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1579 let Predicates = [HasSSE2] in {
1580 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1581 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1582 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1583 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1586 let Predicates = [HasAVX] in {
1587 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1588 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1589 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1590 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1591 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1592 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1593 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1594 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1596 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
1597 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
1598 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
1599 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
1600 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
1601 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
1602 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
1603 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
1606 //===----------------------------------------------------------------------===//
1607 // SSE 1 & 2 - Shuffle Instructions
1608 //===----------------------------------------------------------------------===//
1610 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1611 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1612 ValueType vt, string asm, PatFrag mem_frag,
1613 Domain d, bit IsConvertibleToThreeAddress = 0> {
1614 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1615 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1616 [(set RC:$dst, (vt (shufp:$src3
1617 RC:$src1, (mem_frag addr:$src2))))], d>;
1618 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1619 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1620 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1622 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1625 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1626 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1627 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1628 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1629 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1630 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1631 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1632 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1633 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1634 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1635 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1636 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1638 let Constraints = "$src1 = $dst" in {
1639 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1640 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1641 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1643 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1644 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1645 memopv2f64, SSEPackedDouble>, TB, OpSize;
1648 let Predicates = [HasSSE1] in {
1649 def : Pat<(v4f32 (X86Shufps VR128:$src1,
1650 (memopv4f32 addr:$src2), (i8 imm:$imm))),
1651 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1652 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1653 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1654 def : Pat<(v4i32 (X86Shufps VR128:$src1,
1655 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
1656 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1657 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1658 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1659 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
1660 // fall back to this for SSE1)
1661 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
1662 (SHUFPSrri VR128:$src2, VR128:$src1,
1663 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1664 // Special unary SHUFPSrri case.
1665 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
1666 (SHUFPSrri VR128:$src1, VR128:$src1,
1667 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1670 let Predicates = [HasSSE2] in {
1671 // Special binary v4i32 shuffle cases with SHUFPS.
1672 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
1673 (SHUFPSrri VR128:$src1, VR128:$src2,
1674 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1675 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
1676 (bc_v4i32 (memopv2i64 addr:$src2)))),
1677 (SHUFPSrmi VR128:$src1, addr:$src2,
1678 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1679 // Special unary SHUFPDrri cases.
1680 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
1681 (SHUFPDrri VR128:$src1, VR128:$src1,
1682 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1683 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
1684 (SHUFPDrri VR128:$src1, VR128:$src1,
1685 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1686 // Special binary v2i64 shuffle cases using SHUFPDrri.
1687 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
1688 (SHUFPDrri VR128:$src1, VR128:$src2,
1689 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1690 // Generic SHUFPD patterns
1691 def : Pat<(v2f64 (X86Shufps VR128:$src1,
1692 (memopv2f64 addr:$src2), (i8 imm:$imm))),
1693 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
1694 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1695 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1696 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1697 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1700 let Predicates = [HasAVX] in {
1701 def : Pat<(v4f32 (X86Shufps VR128:$src1,
1702 (memopv4f32 addr:$src2), (i8 imm:$imm))),
1703 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1704 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1705 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1706 def : Pat<(v4i32 (X86Shufps VR128:$src1,
1707 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
1708 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
1709 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1710 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
1711 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
1712 // fall back to this for SSE1)
1713 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
1714 (VSHUFPSrri VR128:$src2, VR128:$src1,
1715 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1716 // Special unary SHUFPSrri case.
1717 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
1718 (VSHUFPSrri VR128:$src1, VR128:$src1,
1719 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1720 // Special binary v4i32 shuffle cases with SHUFPS.
1721 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
1722 (VSHUFPSrri VR128:$src1, VR128:$src2,
1723 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1724 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
1725 (bc_v4i32 (memopv2i64 addr:$src2)))),
1726 (VSHUFPSrmi VR128:$src1, addr:$src2,
1727 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1728 // Special unary SHUFPDrri cases.
1729 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
1730 (VSHUFPDrri VR128:$src1, VR128:$src1,
1731 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1732 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
1733 (VSHUFPDrri VR128:$src1, VR128:$src1,
1734 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1735 // Special binary v2i64 shuffle cases using SHUFPDrri.
1736 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
1737 (VSHUFPDrri VR128:$src1, VR128:$src2,
1738 (SHUFFLE_get_shuf_imm VR128:$src3))>;
1740 def : Pat<(v2f64 (X86Shufps VR128:$src1,
1741 (memopv2f64 addr:$src2), (i8 imm:$imm))),
1742 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
1743 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1744 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1745 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
1746 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
1749 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
1750 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
1751 def : Pat<(v8i32 (X86Shufps VR256:$src1,
1752 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
1753 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
1755 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
1756 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
1757 def : Pat<(v8f32 (X86Shufps VR256:$src1,
1758 (memopv8f32 addr:$src2), (i8 imm:$imm))),
1759 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
1761 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
1762 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
1763 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
1764 (memopv4i64 addr:$src2), (i8 imm:$imm))),
1765 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
1767 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
1768 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
1769 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
1770 (memopv4f64 addr:$src2), (i8 imm:$imm))),
1771 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
1774 //===----------------------------------------------------------------------===//
1775 // SSE 1 & 2 - Unpack Instructions
1776 //===----------------------------------------------------------------------===//
1778 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1779 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1780 PatFrag mem_frag, RegisterClass RC,
1781 X86MemOperand x86memop, string asm,
1783 def rr : PI<opc, MRMSrcReg,
1784 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1786 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1787 def rm : PI<opc, MRMSrcMem,
1788 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1790 (vt (OpNode RC:$src1,
1791 (mem_frag addr:$src2))))], d>;
1794 let AddedComplexity = 10 in {
1795 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1796 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1797 SSEPackedSingle>, TB, VEX_4V;
1798 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1799 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1800 SSEPackedDouble>, TB, OpSize, VEX_4V;
1801 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1802 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1803 SSEPackedSingle>, TB, VEX_4V;
1804 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1805 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1806 SSEPackedDouble>, TB, OpSize, VEX_4V;
1808 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1809 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1810 SSEPackedSingle>, TB, VEX_4V;
1811 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1812 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1813 SSEPackedDouble>, TB, OpSize, VEX_4V;
1814 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1815 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1816 SSEPackedSingle>, TB, VEX_4V;
1817 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1818 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1819 SSEPackedDouble>, TB, OpSize, VEX_4V;
1821 let Constraints = "$src1 = $dst" in {
1822 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1823 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1824 SSEPackedSingle>, TB;
1825 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1826 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1827 SSEPackedDouble>, TB, OpSize;
1828 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1829 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1830 SSEPackedSingle>, TB;
1831 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1832 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1833 SSEPackedDouble>, TB, OpSize;
1834 } // Constraints = "$src1 = $dst"
1835 } // AddedComplexity
1837 let Predicates = [HasSSE1] in {
1838 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
1839 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
1840 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
1841 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
1842 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
1843 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
1844 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
1845 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
1848 let Predicates = [HasSSE2] in {
1849 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
1850 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
1851 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
1852 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
1853 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
1854 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
1855 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
1856 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
1858 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
1859 // problem is during lowering, where it's not possible to recognize the load
1860 // fold cause it has two uses through a bitcast. One use disappears at isel
1861 // time and the fold opportunity reappears.
1862 def : Pat<(v2f64 (X86Movddup VR128:$src)),
1863 (UNPCKLPDrr VR128:$src, VR128:$src)>;
1865 let AddedComplexity = 10 in
1866 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
1867 (UNPCKLPDrr VR128:$src, VR128:$src)>;
1870 let Predicates = [HasAVX] in {
1871 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
1872 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
1873 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
1874 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
1875 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
1876 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
1877 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
1878 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
1880 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
1881 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
1882 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
1883 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
1884 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
1885 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
1886 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
1887 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
1888 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
1889 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
1890 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
1891 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
1892 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
1893 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
1894 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
1895 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
1897 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
1898 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
1899 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
1900 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
1901 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
1902 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
1903 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
1904 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
1906 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
1907 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
1908 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
1909 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
1910 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
1911 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
1912 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
1913 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
1914 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
1915 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
1916 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
1917 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
1918 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
1919 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
1920 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
1921 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
1923 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
1924 // problem is during lowering, where it's not possible to recognize the load
1925 // fold cause it has two uses through a bitcast. One use disappears at isel
1926 // time and the fold opportunity reappears.
1927 def : Pat<(v2f64 (X86Movddup VR128:$src)),
1928 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
1929 let AddedComplexity = 10 in
1930 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
1931 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
1934 //===----------------------------------------------------------------------===//
1935 // SSE 1 & 2 - Extract Floating-Point Sign mask
1936 //===----------------------------------------------------------------------===//
1938 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1939 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1941 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1942 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1943 [(set GR32:$dst, (Int RC:$src))], d>;
1944 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1945 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1948 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1949 SSEPackedSingle>, TB;
1950 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1951 SSEPackedDouble>, TB, OpSize;
1953 def : Pat<(i32 (X86fgetsign FR32:$src)),
1954 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1955 sub_ss))>, Requires<[HasSSE1]>;
1956 def : Pat<(i64 (X86fgetsign FR32:$src)),
1957 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1958 sub_ss))>, Requires<[HasSSE1]>;
1959 def : Pat<(i32 (X86fgetsign FR64:$src)),
1960 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1961 sub_sd))>, Requires<[HasSSE2]>;
1962 def : Pat<(i64 (X86fgetsign FR64:$src)),
1963 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1964 sub_sd))>, Requires<[HasSSE2]>;
1966 let Predicates = [HasAVX] in {
1967 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1968 "movmskps", SSEPackedSingle>, TB, VEX;
1969 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1970 "movmskpd", SSEPackedDouble>, TB, OpSize,
1972 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1973 "movmskps", SSEPackedSingle>, TB, VEX;
1974 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1975 "movmskpd", SSEPackedDouble>, TB, OpSize,
1978 def : Pat<(i32 (X86fgetsign FR32:$src)),
1979 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1981 def : Pat<(i64 (X86fgetsign FR32:$src)),
1982 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1984 def : Pat<(i32 (X86fgetsign FR64:$src)),
1985 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1987 def : Pat<(i64 (X86fgetsign FR64:$src)),
1988 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1992 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1993 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
1994 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1995 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize,
1997 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1998 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
1999 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2000 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize,
2004 //===----------------------------------------------------------------------===//
2005 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
2006 //===----------------------------------------------------------------------===//
2008 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
2009 // names that start with 'Fs'.
2011 // Alias instructions that map fld0 to pxor for sse.
2012 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
2013 canFoldAsLoad = 1 in {
2014 // FIXME: Set encoding to pseudo!
2015 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
2016 [(set FR32:$dst, fp32imm0)]>,
2017 Requires<[HasSSE1]>, TB, OpSize;
2018 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
2019 [(set FR64:$dst, fpimm0)]>,
2020 Requires<[HasSSE2]>, TB, OpSize;
2021 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
2022 [(set FR32:$dst, fp32imm0)]>,
2023 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
2024 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
2025 [(set FR64:$dst, fpimm0)]>,
2026 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
2029 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
2030 // bits are disregarded.
2031 let neverHasSideEffects = 1 in {
2032 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2033 "movaps\t{$src, $dst|$dst, $src}", []>;
2034 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2035 "movapd\t{$src, $dst|$dst, $src}", []>;
2038 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
2039 // bits are disregarded.
2040 let canFoldAsLoad = 1, isReMaterializable = 1 in {
2041 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
2042 "movaps\t{$src, $dst|$dst, $src}",
2043 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
2044 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
2045 "movapd\t{$src, $dst|$dst, $src}",
2046 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
2049 //===----------------------------------------------------------------------===//
2050 // SSE 1 & 2 - Logical Instructions
2051 //===----------------------------------------------------------------------===//
2053 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2055 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2057 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2058 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2060 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2061 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2063 let Constraints = "$src1 = $dst" in {
2064 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2065 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2067 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2068 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2072 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2073 let mayLoad = 0 in {
2074 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2075 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2076 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2079 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2080 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2082 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2084 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2086 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2087 // are all promoted to v2i64, and the patterns are covered by the int
2088 // version. This is needed in SSE only, because v2i64 isn't supported on
2089 // SSE1, but only on SSE2.
2090 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2091 !strconcat(OpcodeStr, "ps"), f128mem, [],
2092 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2093 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2095 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2096 !strconcat(OpcodeStr, "pd"), f128mem,
2097 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2098 (bc_v2i64 (v2f64 VR128:$src2))))],
2099 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2100 (memopv2i64 addr:$src2)))], 0>,
2102 let Constraints = "$src1 = $dst" in {
2103 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2104 !strconcat(OpcodeStr, "ps"), f128mem,
2105 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2106 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2107 (memopv2i64 addr:$src2)))]>, TB;
2109 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2110 !strconcat(OpcodeStr, "pd"), f128mem,
2111 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2112 (bc_v2i64 (v2f64 VR128:$src2))))],
2113 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2114 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2118 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2120 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2122 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2123 !strconcat(OpcodeStr, "ps"), f256mem,
2124 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2125 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2126 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2128 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2129 !strconcat(OpcodeStr, "pd"), f256mem,
2130 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2131 (bc_v4i64 (v4f64 VR256:$src2))))],
2132 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2133 (memopv4i64 addr:$src2)))], 0>,
2137 // AVX 256-bit packed logical ops forms
2138 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2139 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2140 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2141 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2143 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2144 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2145 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2146 let isCommutable = 0 in
2147 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2149 //===----------------------------------------------------------------------===//
2150 // SSE 1 & 2 - Arithmetic Instructions
2151 //===----------------------------------------------------------------------===//
2153 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2156 /// In addition, we also have a special variant of the scalar form here to
2157 /// represent the associated intrinsic operation. This form is unlike the
2158 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2159 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2161 /// These three forms can each be reg+reg or reg+mem.
2164 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2166 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2168 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2169 OpNode, FR32, f32mem, Is2Addr>, XS;
2170 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2171 OpNode, FR64, f64mem, Is2Addr>, XD;
2174 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2176 let mayLoad = 0 in {
2177 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2178 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2179 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2180 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2184 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2186 let mayLoad = 0 in {
2187 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2188 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2189 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2190 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2194 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2196 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2197 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2198 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2199 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2202 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2204 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2205 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2206 SSEPackedSingle, Is2Addr>, TB;
2208 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2209 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2210 SSEPackedDouble, Is2Addr>, TB, OpSize;
2213 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2214 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2215 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2216 SSEPackedSingle, 0>, TB;
2218 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2219 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2220 SSEPackedDouble, 0>, TB, OpSize;
2223 // Binary Arithmetic instructions
2224 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2225 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
2226 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2227 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2228 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2229 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
2230 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2231 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2233 let isCommutable = 0 in {
2234 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2235 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
2236 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2237 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2238 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2239 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
2240 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2241 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2242 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2243 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
2244 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2245 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2246 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2247 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2248 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2249 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
2250 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2251 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2252 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2253 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2256 let Constraints = "$src1 = $dst" in {
2257 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2258 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2259 basic_sse12_fp_binop_s_int<0x58, "add">;
2260 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2261 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2262 basic_sse12_fp_binop_s_int<0x59, "mul">;
2264 let isCommutable = 0 in {
2265 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2266 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2267 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2268 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2269 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2270 basic_sse12_fp_binop_s_int<0x5E, "div">;
2271 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2272 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2273 basic_sse12_fp_binop_s_int<0x5F, "max">,
2274 basic_sse12_fp_binop_p_int<0x5F, "max">;
2275 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2276 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2277 basic_sse12_fp_binop_s_int<0x5D, "min">,
2278 basic_sse12_fp_binop_p_int<0x5D, "min">;
2283 /// In addition, we also have a special variant of the scalar form here to
2284 /// represent the associated intrinsic operation. This form is unlike the
2285 /// plain scalar form, in that it takes an entire vector (instead of a
2286 /// scalar) and leaves the top elements undefined.
2288 /// And, we have a special variant form for a full-vector intrinsic form.
2290 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2291 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2292 SDNode OpNode, Intrinsic F32Int> {
2293 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2294 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2295 [(set FR32:$dst, (OpNode FR32:$src))]>;
2296 // For scalar unary operations, fold a load into the operation
2297 // only in OptForSize mode. It eliminates an instruction, but it also
2298 // eliminates a whole-register clobber (the load), so it introduces a
2299 // partial register update condition.
2300 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2301 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2302 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2303 Requires<[HasSSE1, OptForSize]>;
2304 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2305 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2306 [(set VR128:$dst, (F32Int VR128:$src))]>;
2307 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2308 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2309 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2312 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2313 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2314 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2315 !strconcat(OpcodeStr,
2316 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2317 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2318 !strconcat(OpcodeStr,
2319 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2320 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2321 (ins ssmem:$src1, VR128:$src2),
2322 !strconcat(OpcodeStr,
2323 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2326 /// sse1_fp_unop_p - SSE1 unops in packed form.
2327 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2328 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2329 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2330 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2331 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2332 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2333 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2336 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2337 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2338 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2339 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2340 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2341 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2342 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2343 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2346 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2347 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2348 Intrinsic V4F32Int> {
2349 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2350 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2351 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2352 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2353 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2354 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2357 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2358 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2359 Intrinsic V4F32Int> {
2360 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2361 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2362 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2363 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2364 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2365 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2368 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2369 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2370 SDNode OpNode, Intrinsic F64Int> {
2371 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2372 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2373 [(set FR64:$dst, (OpNode FR64:$src))]>;
2374 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2375 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2376 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2377 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2378 Requires<[HasSSE2, OptForSize]>;
2379 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2380 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2381 [(set VR128:$dst, (F64Int VR128:$src))]>;
2382 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2383 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2384 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2387 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2388 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2389 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2390 !strconcat(OpcodeStr,
2391 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2392 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2393 !strconcat(OpcodeStr,
2394 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2395 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2396 (ins VR128:$src1, sdmem:$src2),
2397 !strconcat(OpcodeStr,
2398 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2401 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2402 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2404 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2405 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2406 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2407 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2408 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2409 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2412 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2413 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2414 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2415 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2416 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2417 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2418 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2419 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2422 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2423 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2424 Intrinsic V2F64Int> {
2425 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2426 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2427 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2428 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2429 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2430 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2433 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2434 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2435 Intrinsic V2F64Int> {
2436 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2437 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2438 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2439 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2440 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2441 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2444 let Predicates = [HasAVX] in {
2446 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2447 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
2449 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2450 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2451 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2452 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2453 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2454 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2455 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2456 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
2459 // Reciprocal approximations. Note that these typically require refinement
2460 // in order to obtain suitable precision.
2461 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
2462 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2463 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2464 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2465 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
2467 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
2468 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
2469 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
2470 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
2471 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
2474 def : Pat<(f32 (fsqrt FR32:$src)),
2475 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2476 def : Pat<(f32 (fsqrt (load addr:$src))),
2477 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2478 Requires<[HasAVX, OptForSize]>;
2479 def : Pat<(f64 (fsqrt FR64:$src)),
2480 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
2481 def : Pat<(f64 (fsqrt (load addr:$src))),
2482 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
2483 Requires<[HasAVX, OptForSize]>;
2485 def : Pat<(f32 (X86frsqrt FR32:$src)),
2486 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2487 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2488 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2489 Requires<[HasAVX, OptForSize]>;
2491 def : Pat<(f32 (X86frcp FR32:$src)),
2492 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2493 def : Pat<(f32 (X86frcp (load addr:$src))),
2494 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2495 Requires<[HasAVX, OptForSize]>;
2497 let Predicates = [HasAVX] in {
2498 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
2499 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2500 (VSQRTSSr (f32 (IMPLICIT_DEF)),
2501 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2503 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2504 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2506 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
2507 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
2508 (VSQRTSDr (f64 (IMPLICIT_DEF)),
2509 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
2511 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2512 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2514 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
2515 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2516 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
2517 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2519 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
2520 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2522 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
2523 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2524 (VRCPSSr (f32 (IMPLICIT_DEF)),
2525 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2527 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
2528 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2532 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2533 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
2534 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
2535 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2536 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
2537 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
2539 // Reciprocal approximations. Note that these typically require refinement
2540 // in order to obtain suitable precision.
2541 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2542 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
2543 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
2544 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2545 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
2546 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
2548 // There is no f64 version of the reciprocal approximation instructions.
2550 //===----------------------------------------------------------------------===//
2551 // SSE 1 & 2 - Non-temporal stores
2552 //===----------------------------------------------------------------------===//
2554 let AddedComplexity = 400 in { // Prefer non-temporal versions
2555 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2556 (ins f128mem:$dst, VR128:$src),
2557 "movntps\t{$src, $dst|$dst, $src}",
2558 [(alignednontemporalstore (v4f32 VR128:$src),
2560 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2561 (ins f128mem:$dst, VR128:$src),
2562 "movntpd\t{$src, $dst|$dst, $src}",
2563 [(alignednontemporalstore (v2f64 VR128:$src),
2565 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2566 (ins f128mem:$dst, VR128:$src),
2567 "movntdq\t{$src, $dst|$dst, $src}",
2568 [(alignednontemporalstore (v2f64 VR128:$src),
2571 let ExeDomain = SSEPackedInt in
2572 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2573 (ins f128mem:$dst, VR128:$src),
2574 "movntdq\t{$src, $dst|$dst, $src}",
2575 [(alignednontemporalstore (v4f32 VR128:$src),
2578 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2579 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
2581 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2582 (ins f256mem:$dst, VR256:$src),
2583 "movntps\t{$src, $dst|$dst, $src}",
2584 [(alignednontemporalstore (v8f32 VR256:$src),
2586 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2587 (ins f256mem:$dst, VR256:$src),
2588 "movntpd\t{$src, $dst|$dst, $src}",
2589 [(alignednontemporalstore (v4f64 VR256:$src),
2591 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2592 (ins f256mem:$dst, VR256:$src),
2593 "movntdq\t{$src, $dst|$dst, $src}",
2594 [(alignednontemporalstore (v4f64 VR256:$src),
2596 let ExeDomain = SSEPackedInt in
2597 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2598 (ins f256mem:$dst, VR256:$src),
2599 "movntdq\t{$src, $dst|$dst, $src}",
2600 [(alignednontemporalstore (v8f32 VR256:$src),
2604 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
2605 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
2606 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2607 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2608 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2609 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2611 let AddedComplexity = 400 in { // Prefer non-temporal versions
2612 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2613 "movntps\t{$src, $dst|$dst, $src}",
2614 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2615 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2616 "movntpd\t{$src, $dst|$dst, $src}",
2617 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2619 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2620 "movntdq\t{$src, $dst|$dst, $src}",
2621 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2623 let ExeDomain = SSEPackedInt in
2624 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2625 "movntdq\t{$src, $dst|$dst, $src}",
2626 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2628 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2629 (MOVNTDQmr addr:$dst, VR128:$src)>;
2631 // There is no AVX form for instructions below this point
2632 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2633 "movnti{l}\t{$src, $dst|$dst, $src}",
2634 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2635 TB, Requires<[HasSSE2]>;
2636 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2637 "movnti{q}\t{$src, $dst|$dst, $src}",
2638 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2639 TB, Requires<[HasSSE2]>;
2642 //===----------------------------------------------------------------------===//
2643 // SSE 1 & 2 - Prefetch and memory fence
2644 //===----------------------------------------------------------------------===//
2646 // Prefetch intrinsic.
2647 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2648 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2649 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2650 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2651 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2652 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2653 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2654 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2656 // Load, store, and memory fence
2657 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2658 TB, Requires<[HasSSE1]>;
2659 def : Pat<(X86SFence), (SFENCE)>;
2661 //===----------------------------------------------------------------------===//
2662 // SSE 1 & 2 - Load/Store XCSR register
2663 //===----------------------------------------------------------------------===//
2665 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2666 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2667 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2668 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2670 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2671 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2672 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2673 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2675 //===---------------------------------------------------------------------===//
2676 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2677 //===---------------------------------------------------------------------===//
2679 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2681 let neverHasSideEffects = 1 in {
2682 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2683 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2684 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2685 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2687 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2688 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2689 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2690 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2692 let canFoldAsLoad = 1, mayLoad = 1 in {
2693 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2694 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2695 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2696 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2697 let Predicates = [HasAVX] in {
2698 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2699 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2700 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2701 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2705 let mayStore = 1 in {
2706 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2707 (ins i128mem:$dst, VR128:$src),
2708 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2709 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2710 (ins i256mem:$dst, VR256:$src),
2711 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2712 let Predicates = [HasAVX] in {
2713 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2714 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2715 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2716 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2720 let neverHasSideEffects = 1 in
2721 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2722 "movdqa\t{$src, $dst|$dst, $src}", []>;
2724 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2725 "movdqu\t{$src, $dst|$dst, $src}",
2726 []>, XS, Requires<[HasSSE2]>;
2728 let canFoldAsLoad = 1, mayLoad = 1 in {
2729 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2730 "movdqa\t{$src, $dst|$dst, $src}",
2731 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2732 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2733 "movdqu\t{$src, $dst|$dst, $src}",
2734 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2735 XS, Requires<[HasSSE2]>;
2738 let mayStore = 1 in {
2739 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2740 "movdqa\t{$src, $dst|$dst, $src}",
2741 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2742 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2743 "movdqu\t{$src, $dst|$dst, $src}",
2744 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2745 XS, Requires<[HasSSE2]>;
2748 // Intrinsic forms of MOVDQU load and store
2749 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2750 "vmovdqu\t{$src, $dst|$dst, $src}",
2751 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2752 XS, VEX, Requires<[HasAVX]>;
2754 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2755 "movdqu\t{$src, $dst|$dst, $src}",
2756 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2757 XS, Requires<[HasSSE2]>;
2759 } // ExeDomain = SSEPackedInt
2761 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2762 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2763 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2765 //===---------------------------------------------------------------------===//
2766 // SSE2 - Packed Integer Arithmetic Instructions
2767 //===---------------------------------------------------------------------===//
2769 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2771 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2772 bit IsCommutable = 0, bit Is2Addr = 1> {
2773 let isCommutable = IsCommutable in
2774 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2775 (ins VR128:$src1, VR128:$src2),
2777 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2778 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2779 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2780 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2781 (ins VR128:$src1, i128mem:$src2),
2783 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2784 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2785 [(set VR128:$dst, (IntId VR128:$src1,
2786 (bitconvert (memopv2i64 addr:$src2))))]>;
2789 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2790 string OpcodeStr, Intrinsic IntId,
2791 Intrinsic IntId2, bit Is2Addr = 1> {
2792 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2793 (ins VR128:$src1, VR128:$src2),
2795 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2796 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2797 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2798 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2799 (ins VR128:$src1, i128mem:$src2),
2801 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2802 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2803 [(set VR128:$dst, (IntId VR128:$src1,
2804 (bitconvert (memopv2i64 addr:$src2))))]>;
2805 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2806 (ins VR128:$src1, i32i8imm:$src2),
2808 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2809 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2810 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2813 /// PDI_binop_rm - Simple SSE2 binary operator.
2814 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2815 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2816 let isCommutable = IsCommutable in
2817 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2818 (ins VR128:$src1, VR128:$src2),
2820 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2821 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2822 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2823 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2824 (ins VR128:$src1, i128mem:$src2),
2826 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2827 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2828 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2829 (bitconvert (memopv2i64 addr:$src2)))))]>;
2832 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2834 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2835 /// to collapse (bitconvert VT to VT) into its operand.
2837 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2838 bit IsCommutable = 0, bit Is2Addr = 1> {
2839 let isCommutable = IsCommutable in
2840 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2841 (ins VR128:$src1, VR128:$src2),
2843 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2844 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2845 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2846 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2847 (ins VR128:$src1, i128mem:$src2),
2849 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2850 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2851 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2854 } // ExeDomain = SSEPackedInt
2856 // 128-bit Integer Arithmetic
2858 let Predicates = [HasAVX] in {
2859 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2860 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2861 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2862 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2863 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2864 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2865 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2866 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2867 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2870 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2872 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2874 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2876 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2878 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2880 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2882 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2884 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2886 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2888 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2890 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2892 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2894 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2896 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2898 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2900 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2902 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2904 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2906 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2910 let Constraints = "$src1 = $dst" in {
2911 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2912 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2913 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2914 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2915 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2916 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2917 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2918 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2919 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2922 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2923 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2924 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2925 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2926 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2927 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2928 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2929 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2930 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2931 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2932 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2933 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2934 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2935 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2936 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2937 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2938 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2939 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2940 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2942 } // Constraints = "$src1 = $dst"
2944 //===---------------------------------------------------------------------===//
2945 // SSE2 - Packed Integer Logical Instructions
2946 //===---------------------------------------------------------------------===//
2948 let Predicates = [HasAVX] in {
2949 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2950 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2952 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2953 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2955 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2956 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2959 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2960 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2962 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2963 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2965 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2966 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2969 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2970 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2972 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2973 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2976 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2977 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2978 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2980 let ExeDomain = SSEPackedInt in {
2981 let neverHasSideEffects = 1 in {
2982 // 128-bit logical shifts.
2983 def VPSLLDQri : PDIi8<0x73, MRM7r,
2984 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2985 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2987 def VPSRLDQri : PDIi8<0x73, MRM3r,
2988 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2989 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2991 // PSRADQri doesn't exist in SSE[1-3].
2993 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2994 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2995 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2997 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
2999 def VPANDNrm : PDI<0xDF, MRMSrcMem,
3000 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3001 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3002 [(set VR128:$dst, (X86andnp VR128:$src1,
3003 (memopv2i64 addr:$src2)))]>, VEX_4V;
3007 let Constraints = "$src1 = $dst" in {
3008 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3009 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
3010 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3011 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
3012 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3013 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
3015 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3016 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
3017 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3018 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
3019 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3020 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
3022 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3023 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
3024 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3025 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
3027 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
3028 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
3029 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
3031 let ExeDomain = SSEPackedInt in {
3032 let neverHasSideEffects = 1 in {
3033 // 128-bit logical shifts.
3034 def PSLLDQri : PDIi8<0x73, MRM7r,
3035 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3036 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3037 def PSRLDQri : PDIi8<0x73, MRM3r,
3038 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3039 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3040 // PSRADQri doesn't exist in SSE[1-3].
3042 def PANDNrr : PDI<0xDF, MRMSrcReg,
3043 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3044 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3046 def PANDNrm : PDI<0xDF, MRMSrcMem,
3047 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3048 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3050 } // Constraints = "$src1 = $dst"
3052 let Predicates = [HasAVX] in {
3053 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3054 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3055 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3056 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3057 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3058 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
3059 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3060 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
3061 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3062 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3064 // Shift up / down and insert zero's.
3065 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3066 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3067 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3068 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3071 let Predicates = [HasSSE2] in {
3072 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3073 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3074 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3075 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3076 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3077 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
3078 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3079 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
3080 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3081 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3083 // Shift up / down and insert zero's.
3084 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3085 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3086 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3087 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3090 //===---------------------------------------------------------------------===//
3091 // SSE2 - Packed Integer Comparison Instructions
3092 //===---------------------------------------------------------------------===//
3094 let Predicates = [HasAVX] in {
3095 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
3097 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
3099 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
3101 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
3103 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
3105 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
3108 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3109 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3110 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3111 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3112 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3113 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3114 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3115 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3116 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3117 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3118 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3119 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3121 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3122 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3123 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3124 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3125 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3126 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3127 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3128 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3129 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3130 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3131 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3132 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3135 let Constraints = "$src1 = $dst" in {
3136 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
3137 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
3138 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
3139 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
3140 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
3141 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
3142 } // Constraints = "$src1 = $dst"
3144 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3145 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3146 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3147 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3148 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3149 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3150 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3151 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3152 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3153 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3154 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3155 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3157 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3158 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3159 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3160 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3161 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3162 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3163 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3164 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3165 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3166 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3167 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3168 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3170 //===---------------------------------------------------------------------===//
3171 // SSE2 - Packed Integer Pack Instructions
3172 //===---------------------------------------------------------------------===//
3174 let Predicates = [HasAVX] in {
3175 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3177 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3179 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3183 let Constraints = "$src1 = $dst" in {
3184 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
3185 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
3186 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
3187 } // Constraints = "$src1 = $dst"
3189 //===---------------------------------------------------------------------===//
3190 // SSE2 - Packed Integer Shuffle Instructions
3191 //===---------------------------------------------------------------------===//
3193 let ExeDomain = SSEPackedInt in {
3194 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3196 def ri : Ii8<0x70, MRMSrcReg,
3197 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3198 !strconcat(OpcodeStr,
3199 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3200 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
3202 def mi : Ii8<0x70, MRMSrcMem,
3203 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3204 !strconcat(OpcodeStr,
3205 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3206 [(set VR128:$dst, (vt (pshuf_frag:$src2
3207 (bc_frag (memopv2i64 addr:$src1)),
3210 } // ExeDomain = SSEPackedInt
3212 let Predicates = [HasAVX] in {
3213 let AddedComplexity = 5 in
3214 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
3217 // SSE2 with ImmT == Imm8 and XS prefix.
3218 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
3221 // SSE2 with ImmT == Imm8 and XD prefix.
3222 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
3225 let AddedComplexity = 5 in
3226 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3227 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3228 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
3229 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3230 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3232 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3234 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
3235 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3237 (VPSHUFDmi addr:$src1, imm:$imm)>;
3238 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3239 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
3240 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3241 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
3242 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3243 (VPSHUFHWri VR128:$src, imm:$imm)>;
3244 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3246 (VPSHUFHWmi addr:$src, imm:$imm)>;
3247 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3248 (VPSHUFLWri VR128:$src, imm:$imm)>;
3249 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3251 (VPSHUFLWmi addr:$src, imm:$imm)>;
3254 let Predicates = [HasSSE2] in {
3255 let AddedComplexity = 5 in
3256 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
3258 // SSE2 with ImmT == Imm8 and XS prefix.
3259 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
3261 // SSE2 with ImmT == Imm8 and XD prefix.
3262 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
3264 let AddedComplexity = 5 in
3265 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3266 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3267 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3268 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3269 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3271 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3273 (PSHUFDmi addr:$src1, imm:$imm)>;
3274 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3276 (PSHUFDmi addr:$src1, imm:$imm)>;
3277 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3278 (PSHUFDri VR128:$src1, imm:$imm)>;
3279 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3280 (PSHUFDri VR128:$src1, imm:$imm)>;
3281 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3282 (PSHUFHWri VR128:$src, imm:$imm)>;
3283 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3285 (PSHUFHWmi addr:$src, imm:$imm)>;
3286 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3287 (PSHUFLWri VR128:$src, imm:$imm)>;
3288 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3290 (PSHUFLWmi addr:$src, imm:$imm)>;
3293 //===---------------------------------------------------------------------===//
3294 // SSE2 - Packed Integer Unpack Instructions
3295 //===---------------------------------------------------------------------===//
3297 let ExeDomain = SSEPackedInt in {
3298 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3299 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3300 def rr : PDI<opc, MRMSrcReg,
3301 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3303 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3304 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3305 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3306 def rm : PDI<opc, MRMSrcMem,
3307 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3309 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3310 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3311 [(set VR128:$dst, (OpNode VR128:$src1,
3312 (bc_frag (memopv2i64
3316 let Predicates = [HasAVX] in {
3317 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
3318 bc_v16i8, 0>, VEX_4V;
3319 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
3320 bc_v8i16, 0>, VEX_4V;
3321 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
3322 bc_v4i32, 0>, VEX_4V;
3324 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3325 /// knew to collapse (bitconvert VT to VT) into its operand.
3326 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3327 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3328 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3329 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3330 VR128:$src2)))]>, VEX_4V;
3331 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3332 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3333 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3334 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3335 (memopv2i64 addr:$src2))))]>, VEX_4V;
3337 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
3338 bc_v16i8, 0>, VEX_4V;
3339 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
3340 bc_v8i16, 0>, VEX_4V;
3341 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
3342 bc_v4i32, 0>, VEX_4V;
3344 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3345 /// knew to collapse (bitconvert VT to VT) into its operand.
3346 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3347 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3348 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3349 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3350 VR128:$src2)))]>, VEX_4V;
3351 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3352 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3353 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3354 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3355 (memopv2i64 addr:$src2))))]>, VEX_4V;
3358 let Constraints = "$src1 = $dst" in {
3359 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
3360 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
3361 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
3363 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3364 /// knew to collapse (bitconvert VT to VT) into its operand.
3365 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3366 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3367 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3369 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
3370 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3371 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3372 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3374 (v2i64 (X86Punpcklqdq VR128:$src1,
3375 (memopv2i64 addr:$src2))))]>;
3377 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
3378 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
3379 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
3381 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3382 /// knew to collapse (bitconvert VT to VT) into its operand.
3383 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3384 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3385 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3387 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
3388 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3389 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3390 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3392 (v2i64 (X86Punpckhqdq VR128:$src1,
3393 (memopv2i64 addr:$src2))))]>;
3396 } // ExeDomain = SSEPackedInt
3398 //===---------------------------------------------------------------------===//
3399 // SSE2 - Packed Integer Extract and Insert
3400 //===---------------------------------------------------------------------===//
3402 let ExeDomain = SSEPackedInt in {
3403 multiclass sse2_pinsrw<bit Is2Addr = 1> {
3404 def rri : Ii8<0xC4, MRMSrcReg,
3405 (outs VR128:$dst), (ins VR128:$src1,
3406 GR32:$src2, i32i8imm:$src3),
3408 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3409 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3411 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
3412 def rmi : Ii8<0xC4, MRMSrcMem,
3413 (outs VR128:$dst), (ins VR128:$src1,
3414 i16mem:$src2, i32i8imm:$src3),
3416 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3417 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3419 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
3424 let Predicates = [HasAVX] in
3425 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
3426 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3427 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3428 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3429 imm:$src2))]>, TB, OpSize, VEX;
3430 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
3431 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3432 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3433 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3437 let Predicates = [HasAVX] in {
3438 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
3439 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
3440 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
3441 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
3442 []>, TB, OpSize, VEX_4V;
3445 let Constraints = "$src1 = $dst" in
3446 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
3448 } // ExeDomain = SSEPackedInt
3450 //===---------------------------------------------------------------------===//
3451 // SSE2 - Packed Mask Creation
3452 //===---------------------------------------------------------------------===//
3454 let ExeDomain = SSEPackedInt in {
3456 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
3457 "pmovmskb\t{$src, $dst|$dst, $src}",
3458 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
3459 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
3460 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
3461 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
3462 "pmovmskb\t{$src, $dst|$dst, $src}",
3463 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
3465 } // ExeDomain = SSEPackedInt
3467 //===---------------------------------------------------------------------===//
3468 // SSE2 - Conditional Store
3469 //===---------------------------------------------------------------------===//
3471 let ExeDomain = SSEPackedInt in {
3474 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
3475 (ins VR128:$src, VR128:$mask),
3476 "maskmovdqu\t{$mask, $src|$src, $mask}",
3477 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
3479 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
3480 (ins VR128:$src, VR128:$mask),
3481 "maskmovdqu\t{$mask, $src|$src, $mask}",
3482 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
3485 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
3486 "maskmovdqu\t{$mask, $src|$src, $mask}",
3487 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
3489 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
3490 "maskmovdqu\t{$mask, $src|$src, $mask}",
3491 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
3493 } // ExeDomain = SSEPackedInt
3495 //===---------------------------------------------------------------------===//
3496 // SSE2 - Move Doubleword
3497 //===---------------------------------------------------------------------===//
3499 //===---------------------------------------------------------------------===//
3500 // Move Int Doubleword to Packed Double Int
3502 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3503 "movd\t{$src, $dst|$dst, $src}",
3505 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
3506 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3507 "movd\t{$src, $dst|$dst, $src}",
3509 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
3511 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3512 "mov{d|q}\t{$src, $dst|$dst, $src}",
3514 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
3515 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
3516 "mov{d|q}\t{$src, $dst|$dst, $src}",
3517 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
3519 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3520 "movd\t{$src, $dst|$dst, $src}",
3522 (v4i32 (scalar_to_vector GR32:$src)))]>;
3523 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3524 "movd\t{$src, $dst|$dst, $src}",
3526 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
3527 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3528 "mov{d|q}\t{$src, $dst|$dst, $src}",
3530 (v2i64 (scalar_to_vector GR64:$src)))]>;
3531 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
3532 "mov{d|q}\t{$src, $dst|$dst, $src}",
3533 [(set FR64:$dst, (bitconvert GR64:$src))]>;
3535 //===---------------------------------------------------------------------===//
3536 // Move Int Doubleword to Single Scalar
3538 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3539 "movd\t{$src, $dst|$dst, $src}",
3540 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
3542 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3543 "movd\t{$src, $dst|$dst, $src}",
3544 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
3546 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3547 "movd\t{$src, $dst|$dst, $src}",
3548 [(set FR32:$dst, (bitconvert GR32:$src))]>;
3550 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3551 "movd\t{$src, $dst|$dst, $src}",
3552 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
3554 //===---------------------------------------------------------------------===//
3555 // Move Packed Doubleword Int to Packed Double Int
3557 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3558 "movd\t{$src, $dst|$dst, $src}",
3559 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3561 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
3562 (ins i32mem:$dst, VR128:$src),
3563 "movd\t{$src, $dst|$dst, $src}",
3564 [(store (i32 (vector_extract (v4i32 VR128:$src),
3565 (iPTR 0))), addr:$dst)]>, VEX;
3566 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3567 "movd\t{$src, $dst|$dst, $src}",
3568 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3570 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
3571 "movd\t{$src, $dst|$dst, $src}",
3572 [(store (i32 (vector_extract (v4i32 VR128:$src),
3573 (iPTR 0))), addr:$dst)]>;
3575 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3576 "mov{d|q}\t{$src, $dst|$dst, $src}",
3577 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
3579 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
3580 "movq\t{$src, $dst|$dst, $src}",
3581 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
3583 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
3584 "mov{d|q}\t{$src, $dst|$dst, $src}",
3585 [(set GR64:$dst, (bitconvert FR64:$src))]>;
3586 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
3587 "movq\t{$src, $dst|$dst, $src}",
3588 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
3590 //===---------------------------------------------------------------------===//
3591 // Move Scalar Single to Double Int
3593 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3594 "movd\t{$src, $dst|$dst, $src}",
3595 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
3596 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3597 "movd\t{$src, $dst|$dst, $src}",
3598 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
3599 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3600 "movd\t{$src, $dst|$dst, $src}",
3601 [(set GR32:$dst, (bitconvert FR32:$src))]>;
3602 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3603 "movd\t{$src, $dst|$dst, $src}",
3604 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3606 //===---------------------------------------------------------------------===//
3607 // Patterns and instructions to describe movd/movq to XMM register zero-extends
3609 let AddedComplexity = 15 in {
3610 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3611 "movd\t{$src, $dst|$dst, $src}",
3612 [(set VR128:$dst, (v4i32 (X86vzmovl
3613 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3615 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3616 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3617 [(set VR128:$dst, (v2i64 (X86vzmovl
3618 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3621 let AddedComplexity = 15 in {
3622 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3623 "movd\t{$src, $dst|$dst, $src}",
3624 [(set VR128:$dst, (v4i32 (X86vzmovl
3625 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3626 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3627 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3628 [(set VR128:$dst, (v2i64 (X86vzmovl
3629 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3632 let AddedComplexity = 20 in {
3633 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3634 "movd\t{$src, $dst|$dst, $src}",
3636 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3637 (loadi32 addr:$src))))))]>,
3639 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3640 "movd\t{$src, $dst|$dst, $src}",
3642 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3643 (loadi32 addr:$src))))))]>;
3645 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3646 (MOVZDI2PDIrm addr:$src)>;
3647 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3648 (MOVZDI2PDIrm addr:$src)>;
3649 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3650 (MOVZDI2PDIrm addr:$src)>;
3653 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3654 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3655 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3656 (v4i32 (scalar_to_vector GR32:$src)), (i32 0)))),
3657 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
3658 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3659 (v2i64 (scalar_to_vector GR64:$src)), (i32 0)))),
3660 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
3662 // These are the correct encodings of the instructions so that we know how to
3663 // read correct assembly, even though we continue to emit the wrong ones for
3664 // compatibility with Darwin's buggy assembler.
3665 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3666 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
3667 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3668 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
3669 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3670 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
3671 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3672 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
3673 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3674 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3675 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3676 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3678 //===---------------------------------------------------------------------===//
3679 // SSE2 - Move Quadword
3680 //===---------------------------------------------------------------------===//
3682 //===---------------------------------------------------------------------===//
3683 // Move Quadword Int to Packed Quadword Int
3685 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3686 "vmovq\t{$src, $dst|$dst, $src}",
3688 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3689 VEX, Requires<[HasAVX]>;
3690 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3691 "movq\t{$src, $dst|$dst, $src}",
3693 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3694 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3696 //===---------------------------------------------------------------------===//
3697 // Move Packed Quadword Int to Quadword Int
3699 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3700 "movq\t{$src, $dst|$dst, $src}",
3701 [(store (i64 (vector_extract (v2i64 VR128:$src),
3702 (iPTR 0))), addr:$dst)]>, VEX;
3703 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3704 "movq\t{$src, $dst|$dst, $src}",
3705 [(store (i64 (vector_extract (v2i64 VR128:$src),
3706 (iPTR 0))), addr:$dst)]>;
3708 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3709 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3711 //===---------------------------------------------------------------------===//
3712 // Store / copy lower 64-bits of a XMM register.
3714 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3715 "movq\t{$src, $dst|$dst, $src}",
3716 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3717 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3718 "movq\t{$src, $dst|$dst, $src}",
3719 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3721 let AddedComplexity = 20 in
3722 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3723 "vmovq\t{$src, $dst|$dst, $src}",
3725 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3726 (loadi64 addr:$src))))))]>,
3727 XS, VEX, Requires<[HasAVX]>;
3729 let AddedComplexity = 20 in {
3730 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3731 "movq\t{$src, $dst|$dst, $src}",
3733 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3734 (loadi64 addr:$src))))))]>,
3735 XS, Requires<[HasSSE2]>;
3737 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3738 (MOVZQI2PQIrm addr:$src)>;
3739 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3740 (MOVZQI2PQIrm addr:$src)>;
3741 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3744 //===---------------------------------------------------------------------===//
3745 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3746 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3748 let AddedComplexity = 15 in
3749 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3750 "vmovq\t{$src, $dst|$dst, $src}",
3751 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3752 XS, VEX, Requires<[HasAVX]>;
3753 let AddedComplexity = 15 in
3754 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3755 "movq\t{$src, $dst|$dst, $src}",
3756 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3757 XS, Requires<[HasSSE2]>;
3759 let AddedComplexity = 20 in
3760 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3761 "vmovq\t{$src, $dst|$dst, $src}",
3762 [(set VR128:$dst, (v2i64 (X86vzmovl
3763 (loadv2i64 addr:$src))))]>,
3764 XS, VEX, Requires<[HasAVX]>;
3765 let AddedComplexity = 20 in {
3766 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3767 "movq\t{$src, $dst|$dst, $src}",
3768 [(set VR128:$dst, (v2i64 (X86vzmovl
3769 (loadv2i64 addr:$src))))]>,
3770 XS, Requires<[HasSSE2]>;
3772 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3773 (MOVZPQILo2PQIrm addr:$src)>;
3776 // Instructions to match in the assembler
3777 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3778 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3779 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3780 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3781 // Recognize "movd" with GR64 destination, but encode as a "movq"
3782 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3783 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3785 // Instructions for the disassembler
3786 // xr = XMM register
3789 let Predicates = [HasAVX] in
3790 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3791 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3792 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3793 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3795 //===---------------------------------------------------------------------===//
3796 // SSE2 - Misc Instructions
3797 //===---------------------------------------------------------------------===//
3800 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3801 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3802 TB, Requires<[HasSSE2]>;
3804 // Load, store, and memory fence
3805 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3806 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3807 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3808 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3809 def : Pat<(X86LFence), (LFENCE)>;
3810 def : Pat<(X86MFence), (MFENCE)>;
3813 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3814 // was introduced with SSE2, it's backward compatible.
3815 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3817 // Alias instructions that map zero vector to pxor / xorp* for sse.
3818 // We set canFoldAsLoad because this can be converted to a constant-pool
3819 // load of an all-ones value if folding it would be beneficial.
3820 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
3821 // JIT implementation, it does not expand the instructions below like
3822 // X86MCInstLower does.
3823 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3824 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3825 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3826 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3827 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3828 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
3829 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3830 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
3832 //===---------------------------------------------------------------------===//
3833 // SSE3 - Conversion Instructions
3834 //===---------------------------------------------------------------------===//
3836 // Convert Packed Double FP to Packed DW Integers
3837 let Predicates = [HasAVX] in {
3838 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3839 // register, but the same isn't true when using memory operands instead.
3840 // Provide other assembly rr and rm forms to address this explicitly.
3841 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3842 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3843 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3844 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3847 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3848 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3849 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3850 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3853 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3854 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3855 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3856 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3859 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3860 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3861 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3862 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3864 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
3865 (VCVTPD2DQYrr VR256:$src)>;
3866 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
3867 (VCVTPD2DQYrm addr:$src)>;
3869 // Convert Packed DW Integers to Packed Double FP
3870 let Predicates = [HasAVX] in {
3871 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3872 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3873 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3874 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3875 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3876 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3877 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3878 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3881 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3882 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3883 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3884 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3886 // AVX 256-bit register conversion intrinsics
3887 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3888 (VCVTDQ2PDYrr VR128:$src)>;
3889 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3890 (VCVTDQ2PDYrm addr:$src)>;
3892 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3893 (VCVTPD2DQYrr VR256:$src)>;
3894 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3895 (VCVTPD2DQYrm addr:$src)>;
3897 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
3898 (VCVTDQ2PDYrr VR128:$src)>;
3899 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
3900 (VCVTDQ2PDYrm addr:$src)>;
3902 //===---------------------------------------------------------------------===//
3903 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
3904 //===---------------------------------------------------------------------===//
3905 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3906 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3907 X86MemOperand x86memop> {
3908 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3909 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3910 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
3911 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3912 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3913 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
3916 let Predicates = [HasAVX] in {
3917 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3918 v4f32, VR128, memopv4f32, f128mem>, VEX;
3919 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3920 v4f32, VR128, memopv4f32, f128mem>, VEX;
3921 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3922 v8f32, VR256, memopv8f32, f256mem>, VEX;
3923 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3924 v8f32, VR256, memopv8f32, f256mem>, VEX;
3926 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
3927 memopv4f32, f128mem>;
3928 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
3929 memopv4f32, f128mem>;
3931 let Predicates = [HasSSE3] in {
3932 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3933 (MOVSHDUPrr VR128:$src)>;
3934 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3935 (MOVSHDUPrm addr:$src)>;
3936 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3937 (MOVSLDUPrr VR128:$src)>;
3938 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3939 (MOVSLDUPrm addr:$src)>;
3942 let Predicates = [HasAVX] in {
3943 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3944 (VMOVSHDUPrr VR128:$src)>;
3945 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3946 (VMOVSHDUPrm addr:$src)>;
3947 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3948 (VMOVSLDUPrr VR128:$src)>;
3949 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3950 (VMOVSLDUPrm addr:$src)>;
3951 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
3952 (VMOVSHDUPYrr VR256:$src)>;
3953 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
3954 (VMOVSHDUPYrm addr:$src)>;
3955 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
3956 (VMOVSLDUPYrr VR256:$src)>;
3957 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
3958 (VMOVSLDUPYrm addr:$src)>;
3961 //===---------------------------------------------------------------------===//
3962 // SSE3 - Replicate Double FP - MOVDDUP
3963 //===---------------------------------------------------------------------===//
3965 multiclass sse3_replicate_dfp<string OpcodeStr> {
3966 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3967 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3968 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3969 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3970 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3972 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3976 // FIXME: Merge with above classe when there're patterns for the ymm version
3977 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3978 let Predicates = [HasAVX] in {
3979 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3980 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3982 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3983 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3988 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3989 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3990 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3992 let Predicates = [HasSSE3] in {
3993 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3995 (MOVDDUPrm addr:$src)>;
3996 let AddedComplexity = 5 in {
3997 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
3998 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3999 (MOVDDUPrm addr:$src)>;
4000 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4001 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4002 (MOVDDUPrm addr:$src)>;
4004 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4005 (MOVDDUPrm addr:$src)>;
4006 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4007 (MOVDDUPrm addr:$src)>;
4008 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4009 (MOVDDUPrm addr:$src)>;
4010 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4011 (MOVDDUPrm addr:$src)>;
4012 def : Pat<(X86Movddup (bc_v2f64
4013 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4014 (MOVDDUPrm addr:$src)>;
4017 let Predicates = [HasAVX] in {
4018 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4020 (VMOVDDUPrm addr:$src)>;
4021 let AddedComplexity = 5 in {
4022 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4023 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4024 (VMOVDDUPrm addr:$src)>;
4025 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4026 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4027 (VMOVDDUPrm addr:$src)>;
4029 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4030 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4031 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4032 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4033 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4034 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4035 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4036 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4037 def : Pat<(X86Movddup (bc_v2f64
4038 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4039 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4042 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4043 (VMOVDDUPYrm addr:$src)>;
4044 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4045 (VMOVDDUPYrm addr:$src)>;
4046 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4047 (VMOVDDUPYrm addr:$src)>;
4048 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4049 (VMOVDDUPYrm addr:$src)>;
4050 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4051 (VMOVDDUPYrr VR256:$src)>;
4052 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4053 (VMOVDDUPYrr VR256:$src)>;
4056 //===---------------------------------------------------------------------===//
4057 // SSE3 - Move Unaligned Integer
4058 //===---------------------------------------------------------------------===//
4060 let Predicates = [HasAVX] in {
4061 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4062 "vlddqu\t{$src, $dst|$dst, $src}",
4063 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4064 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4065 "vlddqu\t{$src, $dst|$dst, $src}",
4066 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4068 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4069 "lddqu\t{$src, $dst|$dst, $src}",
4070 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4072 //===---------------------------------------------------------------------===//
4073 // SSE3 - Arithmetic
4074 //===---------------------------------------------------------------------===//
4076 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4077 X86MemOperand x86memop, bit Is2Addr = 1> {
4078 def rr : I<0xD0, MRMSrcReg,
4079 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4081 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4082 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4083 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4084 def rm : I<0xD0, MRMSrcMem,
4085 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4087 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4088 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4089 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4092 let Predicates = [HasAVX],
4093 ExeDomain = SSEPackedDouble in {
4094 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4095 f128mem, 0>, TB, XD, VEX_4V;
4096 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4097 f128mem, 0>, TB, OpSize, VEX_4V;
4098 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4099 f256mem, 0>, TB, XD, VEX_4V;
4100 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4101 f256mem, 0>, TB, OpSize, VEX_4V;
4103 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
4104 ExeDomain = SSEPackedDouble in {
4105 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4107 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4108 f128mem>, TB, OpSize;
4111 //===---------------------------------------------------------------------===//
4112 // SSE3 Instructions
4113 //===---------------------------------------------------------------------===//
4116 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4117 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4118 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4120 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4121 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4122 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4124 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4126 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4127 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4128 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4130 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4131 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4132 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4134 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4135 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4136 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4138 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4140 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4141 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4142 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4145 let Predicates = [HasAVX] in {
4146 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4147 int_x86_sse3_hadd_ps, 0>, VEX_4V;
4148 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4149 int_x86_sse3_hadd_pd, 0>, VEX_4V;
4150 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4151 int_x86_sse3_hsub_ps, 0>, VEX_4V;
4152 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4153 int_x86_sse3_hsub_pd, 0>, VEX_4V;
4154 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4155 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
4156 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4157 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
4158 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4159 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
4160 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4161 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
4164 let Constraints = "$src1 = $dst" in {
4165 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
4166 int_x86_sse3_hadd_ps>;
4167 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
4168 int_x86_sse3_hadd_pd>;
4169 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
4170 int_x86_sse3_hsub_ps>;
4171 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
4172 int_x86_sse3_hsub_pd>;
4175 //===---------------------------------------------------------------------===//
4176 // SSSE3 - Packed Absolute Instructions
4177 //===---------------------------------------------------------------------===//
4180 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4181 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4182 PatFrag mem_frag128, Intrinsic IntId128> {
4183 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4185 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4186 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4189 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4191 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4194 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
4197 let Predicates = [HasAVX] in {
4198 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
4199 int_x86_ssse3_pabs_b_128>, VEX;
4200 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
4201 int_x86_ssse3_pabs_w_128>, VEX;
4202 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
4203 int_x86_ssse3_pabs_d_128>, VEX;
4206 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
4207 int_x86_ssse3_pabs_b_128>;
4208 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
4209 int_x86_ssse3_pabs_w_128>;
4210 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
4211 int_x86_ssse3_pabs_d_128>;
4213 //===---------------------------------------------------------------------===//
4214 // SSSE3 - Packed Binary Operator Instructions
4215 //===---------------------------------------------------------------------===//
4217 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4218 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4219 PatFrag mem_frag128, Intrinsic IntId128,
4221 let isCommutable = 1 in
4222 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4223 (ins VR128:$src1, VR128:$src2),
4225 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4226 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4227 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4229 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4230 (ins VR128:$src1, i128mem:$src2),
4232 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4233 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4235 (IntId128 VR128:$src1,
4236 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4239 let Predicates = [HasAVX] in {
4240 let isCommutable = 0 in {
4241 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
4242 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
4243 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
4244 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
4245 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
4246 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4247 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
4248 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
4249 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
4250 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
4251 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
4252 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4253 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
4254 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4255 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
4256 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
4257 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
4258 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
4259 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
4260 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
4261 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
4262 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
4264 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
4265 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4268 // None of these have i8 immediate fields.
4269 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
4270 let isCommutable = 0 in {
4271 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
4272 int_x86_ssse3_phadd_w_128>;
4273 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
4274 int_x86_ssse3_phadd_d_128>;
4275 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
4276 int_x86_ssse3_phadd_sw_128>;
4277 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
4278 int_x86_ssse3_phsub_w_128>;
4279 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
4280 int_x86_ssse3_phsub_d_128>;
4281 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
4282 int_x86_ssse3_phsub_sw_128>;
4283 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
4284 int_x86_ssse3_pmadd_ub_sw_128>;
4285 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
4286 int_x86_ssse3_pshuf_b_128>;
4287 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
4288 int_x86_ssse3_psign_b_128>;
4289 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
4290 int_x86_ssse3_psign_w_128>;
4291 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
4292 int_x86_ssse3_psign_d_128>;
4294 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
4295 int_x86_ssse3_pmul_hr_sw_128>;
4298 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4299 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
4300 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4301 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
4303 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4304 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
4305 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4306 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
4307 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4308 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
4310 //===---------------------------------------------------------------------===//
4311 // SSSE3 - Packed Align Instruction Patterns
4312 //===---------------------------------------------------------------------===//
4314 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
4315 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
4316 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4318 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4320 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4322 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
4323 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4325 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4327 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4331 let Predicates = [HasAVX] in
4332 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
4333 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
4334 defm PALIGN : ssse3_palign<"palignr">;
4336 let Predicates = [HasSSSE3] in {
4337 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4338 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4339 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4340 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4341 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4342 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4343 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4344 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4347 let Predicates = [HasAVX] in {
4348 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4349 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4350 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4351 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4352 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4353 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4354 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4355 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4358 //===---------------------------------------------------------------------===//
4359 // SSSE3 Misc Instructions
4360 //===---------------------------------------------------------------------===//
4362 // Thread synchronization
4363 let usesCustomInserter = 1 in {
4364 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
4365 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
4366 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
4367 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
4370 let Uses = [EAX, ECX, EDX] in
4371 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
4372 Requires<[HasSSE3]>;
4373 let Uses = [ECX, EAX] in
4374 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
4375 Requires<[HasSSE3]>;
4377 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
4378 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
4380 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
4381 Requires<[In32BitMode]>;
4382 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
4383 Requires<[In64BitMode]>;
4385 // extload f32 -> f64. This matches load+fextend because we have a hack in
4386 // the isel (PreprocessForFPConvert) that can introduce loads after dag
4388 // Since these loads aren't folded into the fextend, we have to match it
4390 let Predicates = [HasSSE2] in
4391 def : Pat<(fextend (loadf32 addr:$src)),
4392 (CVTSS2SDrm addr:$src)>;
4394 // Move scalar to XMM zero-extended
4395 // movd to XMM register zero-extends
4396 let AddedComplexity = 15 in {
4397 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
4398 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
4399 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
4400 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
4401 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
4402 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
4403 (MOVSSrr (v4f32 (V_SET0PS)),
4404 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
4405 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
4406 (MOVSSrr (v4i32 (V_SET0PI)),
4407 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
4410 // Splat v2f64 / v2i64
4411 let AddedComplexity = 10 in {
4412 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4413 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
4416 let AddedComplexity = 20 in {
4417 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
4418 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
4419 (MOVLPSrm VR128:$src1, addr:$src2)>;
4420 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
4421 (MOVLPDrm VR128:$src1, addr:$src2)>;
4422 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
4423 (MOVLPSrm VR128:$src1, addr:$src2)>;
4424 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
4425 (MOVLPDrm VR128:$src1, addr:$src2)>;
4428 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
4429 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4430 (MOVLPSmr addr:$src1, VR128:$src2)>;
4431 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4432 (MOVLPDmr addr:$src1, VR128:$src2)>;
4433 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
4435 (MOVLPSmr addr:$src1, VR128:$src2)>;
4436 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4437 (MOVLPDmr addr:$src1, VR128:$src2)>;
4439 let AddedComplexity = 15 in {
4440 // Setting the lowest element in the vector.
4441 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
4442 (MOVSSrr (v4i32 VR128:$src1),
4443 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
4444 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
4445 (MOVSDrr (v2i64 VR128:$src1),
4446 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
4448 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
4449 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
4450 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
4451 Requires<[HasSSE2]>;
4452 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
4453 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
4454 Requires<[HasSSE2]>;
4457 // Set lowest element and zero upper elements.
4458 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4459 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
4461 // Use movaps / movups for SSE integer load / store (one byte shorter).
4462 // The instructions selected below are then converted to MOVDQA/MOVDQU
4463 // during the SSE domain pass.
4464 let Predicates = [HasSSE1] in {
4465 def : Pat<(alignedloadv4i32 addr:$src),
4466 (MOVAPSrm addr:$src)>;
4467 def : Pat<(loadv4i32 addr:$src),
4468 (MOVUPSrm addr:$src)>;
4469 def : Pat<(alignedloadv2i64 addr:$src),
4470 (MOVAPSrm addr:$src)>;
4471 def : Pat<(loadv2i64 addr:$src),
4472 (MOVUPSrm addr:$src)>;
4474 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4475 (MOVAPSmr addr:$dst, VR128:$src)>;
4476 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4477 (MOVAPSmr addr:$dst, VR128:$src)>;
4478 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4479 (MOVAPSmr addr:$dst, VR128:$src)>;
4480 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4481 (MOVAPSmr addr:$dst, VR128:$src)>;
4482 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4483 (MOVUPSmr addr:$dst, VR128:$src)>;
4484 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4485 (MOVUPSmr addr:$dst, VR128:$src)>;
4486 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4487 (MOVUPSmr addr:$dst, VR128:$src)>;
4488 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4489 (MOVUPSmr addr:$dst, VR128:$src)>;
4492 // Use vmovaps/vmovups for AVX integer load/store.
4493 let Predicates = [HasAVX] in {
4494 // 128-bit load/store
4495 def : Pat<(alignedloadv4i32 addr:$src),
4496 (VMOVAPSrm addr:$src)>;
4497 def : Pat<(loadv4i32 addr:$src),
4498 (VMOVUPSrm addr:$src)>;
4499 def : Pat<(alignedloadv2i64 addr:$src),
4500 (VMOVAPSrm addr:$src)>;
4501 def : Pat<(loadv2i64 addr:$src),
4502 (VMOVUPSrm addr:$src)>;
4504 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4505 (VMOVAPSmr addr:$dst, VR128:$src)>;
4506 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4507 (VMOVAPSmr addr:$dst, VR128:$src)>;
4508 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4509 (VMOVAPSmr addr:$dst, VR128:$src)>;
4510 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4511 (VMOVAPSmr addr:$dst, VR128:$src)>;
4512 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4513 (VMOVUPSmr addr:$dst, VR128:$src)>;
4514 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4515 (VMOVUPSmr addr:$dst, VR128:$src)>;
4516 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4517 (VMOVUPSmr addr:$dst, VR128:$src)>;
4518 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4519 (VMOVUPSmr addr:$dst, VR128:$src)>;
4521 // 256-bit load/store
4522 def : Pat<(alignedloadv4i64 addr:$src),
4523 (VMOVAPSYrm addr:$src)>;
4524 def : Pat<(loadv4i64 addr:$src),
4525 (VMOVUPSYrm addr:$src)>;
4526 def : Pat<(alignedloadv8i32 addr:$src),
4527 (VMOVAPSYrm addr:$src)>;
4528 def : Pat<(loadv8i32 addr:$src),
4529 (VMOVUPSYrm addr:$src)>;
4530 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
4531 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4532 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
4533 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4534 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
4535 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4536 def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst),
4537 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4538 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
4539 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4540 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
4541 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4542 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
4543 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4544 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
4545 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4548 //===----------------------------------------------------------------------===//
4549 // SSE4.1 - Packed Move with Sign/Zero Extend
4550 //===----------------------------------------------------------------------===//
4552 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4553 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4554 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4555 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4557 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4558 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4560 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4564 let Predicates = [HasAVX] in {
4565 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4567 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4569 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4571 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4573 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4575 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4579 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4580 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4581 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4582 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4583 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4584 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4586 // Common patterns involving scalar load.
4587 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4588 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4589 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4590 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4592 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4593 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4594 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4595 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4597 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4598 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4599 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4600 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4602 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4603 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4604 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4605 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4607 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4608 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4609 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4610 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4612 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4613 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4614 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4615 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4618 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4619 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4620 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4621 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4623 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4624 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4626 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4630 let Predicates = [HasAVX] in {
4631 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4633 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4635 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4637 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4641 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4642 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4643 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4644 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4646 // Common patterns involving scalar load
4647 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4648 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4649 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4650 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4652 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4653 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4654 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4655 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4658 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4659 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4660 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4661 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4663 // Expecting a i16 load any extended to i32 value.
4664 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4665 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4666 [(set VR128:$dst, (IntId (bitconvert
4667 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4671 let Predicates = [HasAVX] in {
4672 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4674 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4677 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4678 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4680 // Common patterns involving scalar load
4681 def : Pat<(int_x86_sse41_pmovsxbq
4682 (bitconvert (v4i32 (X86vzmovl
4683 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4684 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4686 def : Pat<(int_x86_sse41_pmovzxbq
4687 (bitconvert (v4i32 (X86vzmovl
4688 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4689 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4691 //===----------------------------------------------------------------------===//
4692 // SSE4.1 - Extract Instructions
4693 //===----------------------------------------------------------------------===//
4695 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4696 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4697 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4698 (ins VR128:$src1, i32i8imm:$src2),
4699 !strconcat(OpcodeStr,
4700 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4701 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4703 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4704 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4705 !strconcat(OpcodeStr,
4706 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4709 // There's an AssertZext in the way of writing the store pattern
4710 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4713 let Predicates = [HasAVX] in {
4714 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4715 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4716 (ins VR128:$src1, i32i8imm:$src2),
4717 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4720 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4723 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4724 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4725 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4726 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4727 !strconcat(OpcodeStr,
4728 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4731 // There's an AssertZext in the way of writing the store pattern
4732 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4735 let Predicates = [HasAVX] in
4736 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4738 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4741 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4742 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4743 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4744 (ins VR128:$src1, i32i8imm:$src2),
4745 !strconcat(OpcodeStr,
4746 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4748 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4749 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4750 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4751 !strconcat(OpcodeStr,
4752 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4753 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4754 addr:$dst)]>, OpSize;
4757 let Predicates = [HasAVX] in
4758 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4760 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4762 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4763 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4764 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4765 (ins VR128:$src1, i32i8imm:$src2),
4766 !strconcat(OpcodeStr,
4767 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4769 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4770 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4771 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4772 !strconcat(OpcodeStr,
4773 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4774 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4775 addr:$dst)]>, OpSize, REX_W;
4778 let Predicates = [HasAVX] in
4779 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4781 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4783 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4785 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4786 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4787 (ins VR128:$src1, i32i8imm:$src2),
4788 !strconcat(OpcodeStr,
4789 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4791 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4793 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4794 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4795 !strconcat(OpcodeStr,
4796 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4797 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4798 addr:$dst)]>, OpSize;
4801 let Predicates = [HasAVX] in {
4802 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4803 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4804 (ins VR128:$src1, i32i8imm:$src2),
4805 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4808 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4810 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4811 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4814 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4815 Requires<[HasSSE41]>;
4817 //===----------------------------------------------------------------------===//
4818 // SSE4.1 - Insert Instructions
4819 //===----------------------------------------------------------------------===//
4821 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4822 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4823 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4825 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4827 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4829 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4830 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4831 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4833 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4835 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4837 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4838 imm:$src3))]>, OpSize;
4841 let Predicates = [HasAVX] in
4842 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4843 let Constraints = "$src1 = $dst" in
4844 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4846 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4847 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4848 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4850 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4852 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4854 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4856 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4857 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4859 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4861 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4863 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4864 imm:$src3)))]>, OpSize;
4867 let Predicates = [HasAVX] in
4868 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4869 let Constraints = "$src1 = $dst" in
4870 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4872 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4873 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4874 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4876 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4878 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4880 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4882 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4883 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4885 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4887 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4889 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4890 imm:$src3)))]>, OpSize;
4893 let Predicates = [HasAVX] in
4894 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4895 let Constraints = "$src1 = $dst" in
4896 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4898 // insertps has a few different modes, there's the first two here below which
4899 // are optimized inserts that won't zero arbitrary elements in the destination
4900 // vector. The next one matches the intrinsic and could zero arbitrary elements
4901 // in the target vector.
4902 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4903 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4904 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
4906 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4908 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4910 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4912 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4913 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
4915 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4917 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4919 (X86insrtps VR128:$src1,
4920 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4921 imm:$src3))]>, OpSize;
4924 let Constraints = "$src1 = $dst" in
4925 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4926 let Predicates = [HasAVX] in
4927 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4929 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4930 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4932 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4933 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4934 Requires<[HasSSE41]>;
4936 //===----------------------------------------------------------------------===//
4937 // SSE4.1 - Round Instructions
4938 //===----------------------------------------------------------------------===//
4940 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4941 X86MemOperand x86memop, RegisterClass RC,
4942 PatFrag mem_frag32, PatFrag mem_frag64,
4943 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4944 // Intrinsic operation, reg.
4945 // Vector intrinsic operation, reg
4946 def PSr : SS4AIi8<opcps, MRMSrcReg,
4947 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4948 !strconcat(OpcodeStr,
4949 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4950 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4953 // Vector intrinsic operation, mem
4954 def PSm : Ii8<opcps, MRMSrcMem,
4955 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4956 !strconcat(OpcodeStr,
4957 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4959 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4961 Requires<[HasSSE41]>;
4963 // Vector intrinsic operation, reg
4964 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4965 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4966 !strconcat(OpcodeStr,
4967 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4968 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4971 // Vector intrinsic operation, mem
4972 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4973 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4974 !strconcat(OpcodeStr,
4975 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4977 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4981 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4982 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4983 // Intrinsic operation, reg.
4984 // Vector intrinsic operation, reg
4985 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4986 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4987 !strconcat(OpcodeStr,
4988 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4991 // Vector intrinsic operation, mem
4992 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4993 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4994 !strconcat(OpcodeStr,
4995 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4996 []>, TA, OpSize, Requires<[HasSSE41]>;
4998 // Vector intrinsic operation, reg
4999 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
5000 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5001 !strconcat(OpcodeStr,
5002 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5005 // Vector intrinsic operation, mem
5006 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
5007 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5008 !strconcat(OpcodeStr,
5009 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5013 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5016 Intrinsic F64Int, bit Is2Addr = 1> {
5017 // Intrinsic operation, reg.
5018 def SSr : SS4AIi8<opcss, MRMSrcReg,
5019 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5021 !strconcat(OpcodeStr,
5022 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5023 !strconcat(OpcodeStr,
5024 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5025 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5028 // Intrinsic operation, mem.
5029 def SSm : SS4AIi8<opcss, MRMSrcMem,
5030 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5032 !strconcat(OpcodeStr,
5033 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5034 !strconcat(OpcodeStr,
5035 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5037 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5040 // Intrinsic operation, reg.
5041 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5042 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5044 !strconcat(OpcodeStr,
5045 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5046 !strconcat(OpcodeStr,
5047 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5048 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5051 // Intrinsic operation, mem.
5052 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5053 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5055 !strconcat(OpcodeStr,
5056 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5057 !strconcat(OpcodeStr,
5058 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5060 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5064 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
5066 // Intrinsic operation, reg.
5067 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
5068 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5069 !strconcat(OpcodeStr,
5070 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5073 // Intrinsic operation, mem.
5074 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
5075 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5076 !strconcat(OpcodeStr,
5077 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5080 // Intrinsic operation, reg.
5081 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
5082 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5083 !strconcat(OpcodeStr,
5084 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5087 // Intrinsic operation, mem.
5088 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
5089 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5090 !strconcat(OpcodeStr,
5091 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5095 // FP round - roundss, roundps, roundsd, roundpd
5096 let Predicates = [HasAVX] in {
5098 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5099 memopv4f32, memopv2f64,
5100 int_x86_sse41_round_ps,
5101 int_x86_sse41_round_pd>, VEX;
5102 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5103 memopv8f32, memopv4f64,
5104 int_x86_avx_round_ps_256,
5105 int_x86_avx_round_pd_256>, VEX;
5106 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5107 int_x86_sse41_round_ss,
5108 int_x86_sse41_round_sd, 0>, VEX_4V;
5110 // Instructions for the assembler
5111 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
5113 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
5115 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
5118 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5119 memopv4f32, memopv2f64,
5120 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5121 let Constraints = "$src1 = $dst" in
5122 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5123 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5125 //===----------------------------------------------------------------------===//
5126 // SSE4.1 - Packed Bit Test
5127 //===----------------------------------------------------------------------===//
5129 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5130 // the intel intrinsic that corresponds to this.
5131 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5132 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5133 "vptest\t{$src2, $src1|$src1, $src2}",
5134 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5136 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5137 "vptest\t{$src2, $src1|$src1, $src2}",
5138 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5141 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5142 "vptest\t{$src2, $src1|$src1, $src2}",
5143 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5145 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5146 "vptest\t{$src2, $src1|$src1, $src2}",
5147 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5151 let Defs = [EFLAGS] in {
5152 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5153 "ptest \t{$src2, $src1|$src1, $src2}",
5154 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5156 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5157 "ptest \t{$src2, $src1|$src1, $src2}",
5158 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5162 // The bit test instructions below are AVX only
5163 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5164 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5165 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5166 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5167 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5168 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5169 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5170 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5174 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5175 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5176 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5177 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5178 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5181 //===----------------------------------------------------------------------===//
5182 // SSE4.1 - Misc Instructions
5183 //===----------------------------------------------------------------------===//
5185 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5186 "popcnt{w}\t{$src, $dst|$dst, $src}",
5187 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
5188 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5189 "popcnt{w}\t{$src, $dst|$dst, $src}",
5190 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
5192 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5193 "popcnt{l}\t{$src, $dst|$dst, $src}",
5194 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
5195 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5196 "popcnt{l}\t{$src, $dst|$dst, $src}",
5197 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
5199 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5200 "popcnt{q}\t{$src, $dst|$dst, $src}",
5201 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
5202 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5203 "popcnt{q}\t{$src, $dst|$dst, $src}",
5204 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
5208 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5209 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5210 Intrinsic IntId128> {
5211 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5213 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5214 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5215 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5217 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5220 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
5223 let Predicates = [HasAVX] in
5224 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5225 int_x86_sse41_phminposuw>, VEX;
5226 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5227 int_x86_sse41_phminposuw>;
5229 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5230 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5231 Intrinsic IntId128, bit Is2Addr = 1> {
5232 let isCommutable = 1 in
5233 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5234 (ins VR128:$src1, VR128:$src2),
5236 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5237 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5238 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5239 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5240 (ins VR128:$src1, i128mem:$src2),
5242 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5243 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5245 (IntId128 VR128:$src1,
5246 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5249 let Predicates = [HasAVX] in {
5250 let isCommutable = 0 in
5251 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
5253 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
5255 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
5257 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
5259 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
5261 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
5263 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
5265 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
5267 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
5269 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
5271 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
5274 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5275 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
5276 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5277 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
5280 let Constraints = "$src1 = $dst" in {
5281 let isCommutable = 0 in
5282 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
5283 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
5284 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
5285 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
5286 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
5287 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
5288 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
5289 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
5290 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
5291 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
5292 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
5295 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5296 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
5297 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5298 (PCMPEQQrm VR128:$src1, addr:$src2)>;
5300 /// SS48I_binop_rm - Simple SSE41 binary operator.
5301 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5302 ValueType OpVT, bit Is2Addr = 1> {
5303 let isCommutable = 1 in
5304 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5305 (ins VR128:$src1, VR128:$src2),
5307 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5308 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5309 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
5311 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5312 (ins VR128:$src1, i128mem:$src2),
5314 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5315 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5316 [(set VR128:$dst, (OpNode VR128:$src1,
5317 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
5321 let Predicates = [HasAVX] in
5322 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
5323 let Constraints = "$src1 = $dst" in
5324 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
5326 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
5327 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
5328 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
5329 X86MemOperand x86memop, bit Is2Addr = 1> {
5330 let isCommutable = 1 in
5331 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5332 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
5334 !strconcat(OpcodeStr,
5335 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5336 !strconcat(OpcodeStr,
5337 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5338 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
5340 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
5341 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
5343 !strconcat(OpcodeStr,
5344 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5345 !strconcat(OpcodeStr,
5346 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5349 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
5353 let Predicates = [HasAVX] in {
5354 let isCommutable = 0 in {
5355 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
5356 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5357 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
5358 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5359 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
5360 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5361 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
5362 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5363 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
5364 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5365 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
5366 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5368 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
5369 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5370 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
5371 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5372 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
5373 VR256, memopv32i8, i256mem, 0>, VEX_4V;
5376 let Constraints = "$src1 = $dst" in {
5377 let isCommutable = 0 in {
5378 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
5379 VR128, memopv16i8, i128mem>;
5380 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
5381 VR128, memopv16i8, i128mem>;
5382 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
5383 VR128, memopv16i8, i128mem>;
5384 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
5385 VR128, memopv16i8, i128mem>;
5387 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
5388 VR128, memopv16i8, i128mem>;
5389 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
5390 VR128, memopv16i8, i128mem>;
5393 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
5394 let Predicates = [HasAVX] in {
5395 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
5396 RegisterClass RC, X86MemOperand x86memop,
5397 PatFrag mem_frag, Intrinsic IntId> {
5398 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
5399 (ins RC:$src1, RC:$src2, RC:$src3),
5400 !strconcat(OpcodeStr,
5401 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5402 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
5403 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5405 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
5406 (ins RC:$src1, x86memop:$src2, RC:$src3),
5407 !strconcat(OpcodeStr,
5408 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5410 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
5412 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5416 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
5417 memopv16i8, int_x86_sse41_blendvpd>;
5418 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
5419 memopv16i8, int_x86_sse41_blendvps>;
5420 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
5421 memopv16i8, int_x86_sse41_pblendvb>;
5422 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
5423 memopv32i8, int_x86_avx_blendv_pd_256>;
5424 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
5425 memopv32i8, int_x86_avx_blendv_ps_256>;
5427 /// SS41I_ternary_int - SSE 4.1 ternary operator
5428 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
5429 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5430 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5431 (ins VR128:$src1, VR128:$src2),
5432 !strconcat(OpcodeStr,
5433 "\t{$src2, $dst|$dst, $src2}"),
5434 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
5437 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5438 (ins VR128:$src1, i128mem:$src2),
5439 !strconcat(OpcodeStr,
5440 "\t{$src2, $dst|$dst, $src2}"),
5443 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
5447 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
5448 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
5449 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
5451 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
5452 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
5454 let Predicates = [HasAVX] in
5455 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5456 "vmovntdqa\t{$src, $dst|$dst, $src}",
5457 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5459 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5460 "movntdqa\t{$src, $dst|$dst, $src}",
5461 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5464 //===----------------------------------------------------------------------===//
5465 // SSE4.2 - Compare Instructions
5466 //===----------------------------------------------------------------------===//
5468 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
5469 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
5470 Intrinsic IntId128, bit Is2Addr = 1> {
5471 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
5472 (ins VR128:$src1, VR128:$src2),
5474 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5475 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5476 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5478 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
5479 (ins VR128:$src1, i128mem:$src2),
5481 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5482 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5484 (IntId128 VR128:$src1,
5485 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5488 let Predicates = [HasAVX] in {
5489 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
5492 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5493 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
5494 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5495 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
5498 let Constraints = "$src1 = $dst" in
5499 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
5501 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5502 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
5503 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5504 (PCMPGTQrm VR128:$src1, addr:$src2)>;
5506 //===----------------------------------------------------------------------===//
5507 // SSE4.2 - String/text Processing Instructions
5508 //===----------------------------------------------------------------------===//
5510 // Packed Compare Implicit Length Strings, Return Mask
5511 multiclass pseudo_pcmpistrm<string asm> {
5512 def REG : PseudoI<(outs VR128:$dst),
5513 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5514 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
5516 def MEM : PseudoI<(outs VR128:$dst),
5517 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5518 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
5519 VR128:$src1, (load addr:$src2), imm:$src3))]>;
5522 let Defs = [EFLAGS], usesCustomInserter = 1 in {
5523 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
5524 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
5527 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
5528 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5529 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5530 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5531 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5532 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5533 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5536 let Defs = [XMM0, EFLAGS] in {
5537 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5538 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5539 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5540 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5541 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5542 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5545 // Packed Compare Explicit Length Strings, Return Mask
5546 multiclass pseudo_pcmpestrm<string asm> {
5547 def REG : PseudoI<(outs VR128:$dst),
5548 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5549 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5550 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
5551 def MEM : PseudoI<(outs VR128:$dst),
5552 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5553 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5554 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
5557 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
5558 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
5559 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
5562 let Predicates = [HasAVX],
5563 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5564 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5565 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5566 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5567 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5568 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5569 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5572 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5573 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5574 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5575 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5576 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5577 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5578 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5581 // Packed Compare Implicit Length Strings, Return Index
5582 let Defs = [ECX, EFLAGS] in {
5583 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5584 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5585 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5586 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5587 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5588 (implicit EFLAGS)]>, OpSize;
5589 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5590 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5591 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5592 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5593 (implicit EFLAGS)]>, OpSize;
5597 let Predicates = [HasAVX] in {
5598 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5600 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5602 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5604 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5606 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5608 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5612 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5613 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5614 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5615 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5616 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5617 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5619 // Packed Compare Explicit Length Strings, Return Index
5620 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5621 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5622 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5623 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5624 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5625 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5626 (implicit EFLAGS)]>, OpSize;
5627 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5628 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5629 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5631 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5632 (implicit EFLAGS)]>, OpSize;
5636 let Predicates = [HasAVX] in {
5637 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5639 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5641 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5643 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5645 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5647 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5651 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5652 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5653 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5654 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5655 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5656 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5658 //===----------------------------------------------------------------------===//
5659 // SSE4.2 - CRC Instructions
5660 //===----------------------------------------------------------------------===//
5662 // No CRC instructions have AVX equivalents
5664 // crc intrinsic instruction
5665 // This set of instructions are only rm, the only difference is the size
5667 let Constraints = "$src1 = $dst" in {
5668 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5669 (ins GR32:$src1, i8mem:$src2),
5670 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5672 (int_x86_sse42_crc32_32_8 GR32:$src1,
5673 (load addr:$src2)))]>;
5674 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5675 (ins GR32:$src1, GR8:$src2),
5676 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5678 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5679 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5680 (ins GR32:$src1, i16mem:$src2),
5681 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5683 (int_x86_sse42_crc32_32_16 GR32:$src1,
5684 (load addr:$src2)))]>,
5686 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5687 (ins GR32:$src1, GR16:$src2),
5688 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5690 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5692 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5693 (ins GR32:$src1, i32mem:$src2),
5694 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5696 (int_x86_sse42_crc32_32_32 GR32:$src1,
5697 (load addr:$src2)))]>;
5698 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5699 (ins GR32:$src1, GR32:$src2),
5700 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5702 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5703 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5704 (ins GR64:$src1, i8mem:$src2),
5705 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5707 (int_x86_sse42_crc32_64_8 GR64:$src1,
5708 (load addr:$src2)))]>,
5710 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5711 (ins GR64:$src1, GR8:$src2),
5712 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5714 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5716 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5717 (ins GR64:$src1, i64mem:$src2),
5718 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5720 (int_x86_sse42_crc32_64_64 GR64:$src1,
5721 (load addr:$src2)))]>,
5723 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5724 (ins GR64:$src1, GR64:$src2),
5725 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5727 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5731 //===----------------------------------------------------------------------===//
5732 // AES-NI Instructions
5733 //===----------------------------------------------------------------------===//
5735 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5736 Intrinsic IntId128, bit Is2Addr = 1> {
5737 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5738 (ins VR128:$src1, VR128:$src2),
5740 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5741 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5742 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5744 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5745 (ins VR128:$src1, i128mem:$src2),
5747 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5748 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5750 (IntId128 VR128:$src1,
5751 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5754 // Perform One Round of an AES Encryption/Decryption Flow
5755 let Predicates = [HasAVX, HasAES] in {
5756 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5757 int_x86_aesni_aesenc, 0>, VEX_4V;
5758 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5759 int_x86_aesni_aesenclast, 0>, VEX_4V;
5760 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5761 int_x86_aesni_aesdec, 0>, VEX_4V;
5762 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5763 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5766 let Constraints = "$src1 = $dst" in {
5767 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5768 int_x86_aesni_aesenc>;
5769 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5770 int_x86_aesni_aesenclast>;
5771 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5772 int_x86_aesni_aesdec>;
5773 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5774 int_x86_aesni_aesdeclast>;
5777 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5778 (AESENCrr VR128:$src1, VR128:$src2)>;
5779 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5780 (AESENCrm VR128:$src1, addr:$src2)>;
5781 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5782 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5783 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5784 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5785 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5786 (AESDECrr VR128:$src1, VR128:$src2)>;
5787 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5788 (AESDECrm VR128:$src1, addr:$src2)>;
5789 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5790 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5791 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5792 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5794 // Perform the AES InvMixColumn Transformation
5795 let Predicates = [HasAVX, HasAES] in {
5796 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5798 "vaesimc\t{$src1, $dst|$dst, $src1}",
5800 (int_x86_aesni_aesimc VR128:$src1))]>,
5802 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5803 (ins i128mem:$src1),
5804 "vaesimc\t{$src1, $dst|$dst, $src1}",
5806 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5809 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5811 "aesimc\t{$src1, $dst|$dst, $src1}",
5813 (int_x86_aesni_aesimc VR128:$src1))]>,
5815 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5816 (ins i128mem:$src1),
5817 "aesimc\t{$src1, $dst|$dst, $src1}",
5819 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5822 // AES Round Key Generation Assist
5823 let Predicates = [HasAVX, HasAES] in {
5824 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5825 (ins VR128:$src1, i8imm:$src2),
5826 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5828 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5830 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5831 (ins i128mem:$src1, i8imm:$src2),
5832 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5834 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5838 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5839 (ins VR128:$src1, i8imm:$src2),
5840 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5842 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5844 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5845 (ins i128mem:$src1, i8imm:$src2),
5846 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5848 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5852 //===----------------------------------------------------------------------===//
5853 // CLMUL Instructions
5854 //===----------------------------------------------------------------------===//
5856 // Carry-less Multiplication instructions
5857 let Constraints = "$src1 = $dst" in {
5858 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5859 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5860 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5863 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5864 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5865 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5869 // AVX carry-less Multiplication instructions
5870 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5871 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5872 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5875 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5876 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5877 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5881 multiclass pclmul_alias<string asm, int immop> {
5882 def : InstAlias<!strconcat("pclmul", asm,
5883 "dq {$src, $dst|$dst, $src}"),
5884 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
5886 def : InstAlias<!strconcat("pclmul", asm,
5887 "dq {$src, $dst|$dst, $src}"),
5888 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
5890 def : InstAlias<!strconcat("vpclmul", asm,
5891 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5892 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
5894 def : InstAlias<!strconcat("vpclmul", asm,
5895 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5896 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
5898 defm : pclmul_alias<"hqhq", 0x11>;
5899 defm : pclmul_alias<"hqlq", 0x01>;
5900 defm : pclmul_alias<"lqhq", 0x10>;
5901 defm : pclmul_alias<"lqlq", 0x00>;
5903 //===----------------------------------------------------------------------===//
5905 //===----------------------------------------------------------------------===//
5907 //===----------------------------------------------------------------------===//
5908 // VBROADCAST - Load from memory and broadcast to all elements of the
5909 // destination operand
5911 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5912 X86MemOperand x86memop, Intrinsic Int> :
5913 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5914 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5915 [(set RC:$dst, (Int addr:$src))]>, VEX;
5917 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5918 int_x86_avx_vbroadcastss>;
5919 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5920 int_x86_avx_vbroadcastss_256>;
5921 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5922 int_x86_avx_vbroadcast_sd_256>;
5923 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5924 int_x86_avx_vbroadcastf128_pd_256>;
5926 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5927 (VBROADCASTF128 addr:$src)>;
5929 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
5930 (VBROADCASTSSY addr:$src)>;
5931 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
5932 (VBROADCASTSD addr:$src)>;
5933 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
5934 (VBROADCASTSSY addr:$src)>;
5935 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
5936 (VBROADCASTSD addr:$src)>;
5938 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
5939 (VBROADCASTSS addr:$src)>;
5940 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
5941 (VBROADCASTSS addr:$src)>;
5943 //===----------------------------------------------------------------------===//
5944 // VINSERTF128 - Insert packed floating-point values
5946 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5947 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5948 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5950 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5951 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5952 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5955 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5956 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5957 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5958 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5959 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5960 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5962 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5964 (VINSERTF128rr VR256:$src1, VR128:$src2,
5965 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5966 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5968 (VINSERTF128rr VR256:$src1, VR128:$src2,
5969 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5970 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5972 (VINSERTF128rr VR256:$src1, VR128:$src2,
5973 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5974 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5976 (VINSERTF128rr VR256:$src1, VR128:$src2,
5977 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5978 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
5980 (VINSERTF128rr VR256:$src1, VR128:$src2,
5981 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5982 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
5984 (VINSERTF128rr VR256:$src1, VR128:$src2,
5985 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5987 //===----------------------------------------------------------------------===//
5988 // VEXTRACTF128 - Extract packed floating-point values
5990 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5991 (ins VR256:$src1, i8imm:$src2),
5992 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5994 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5995 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5996 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5999 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6000 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6001 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6002 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6003 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6004 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6006 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6007 (v4f32 (VEXTRACTF128rr
6008 (v8f32 VR256:$src1),
6009 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6010 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6011 (v2f64 (VEXTRACTF128rr
6012 (v4f64 VR256:$src1),
6013 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6014 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6015 (v4i32 (VEXTRACTF128rr
6016 (v8i32 VR256:$src1),
6017 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6018 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6019 (v2i64 (VEXTRACTF128rr
6020 (v4i64 VR256:$src1),
6021 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6022 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6023 (v8i16 (VEXTRACTF128rr
6024 (v16i16 VR256:$src1),
6025 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6026 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6027 (v16i8 (VEXTRACTF128rr
6028 (v32i8 VR256:$src1),
6029 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6031 //===----------------------------------------------------------------------===//
6032 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6034 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6035 Intrinsic IntLd, Intrinsic IntLd256,
6036 Intrinsic IntSt, Intrinsic IntSt256,
6037 PatFrag pf128, PatFrag pf256> {
6038 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6039 (ins VR128:$src1, f128mem:$src2),
6040 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6041 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6043 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6044 (ins VR256:$src1, f256mem:$src2),
6045 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6046 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6048 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6049 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6050 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6051 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6052 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6053 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6054 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6055 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6058 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6059 int_x86_avx_maskload_ps,
6060 int_x86_avx_maskload_ps_256,
6061 int_x86_avx_maskstore_ps,
6062 int_x86_avx_maskstore_ps_256,
6063 memopv4f32, memopv8f32>;
6064 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6065 int_x86_avx_maskload_pd,
6066 int_x86_avx_maskload_pd_256,
6067 int_x86_avx_maskstore_pd,
6068 int_x86_avx_maskstore_pd_256,
6069 memopv2f64, memopv4f64>;
6071 //===----------------------------------------------------------------------===//
6072 // VPERMIL - Permute Single and Double Floating-Point Values
6074 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6075 RegisterClass RC, X86MemOperand x86memop_f,
6076 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
6077 Intrinsic IntVar, Intrinsic IntImm> {
6078 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6079 (ins RC:$src1, RC:$src2),
6080 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6081 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6082 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6083 (ins RC:$src1, x86memop_i:$src2),
6084 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6085 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
6087 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6088 (ins RC:$src1, i8imm:$src2),
6089 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6090 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
6091 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6092 (ins x86memop_f:$src1, i8imm:$src2),
6093 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6094 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
6097 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6098 memopv4f32, memopv4i32,
6099 int_x86_avx_vpermilvar_ps,
6100 int_x86_avx_vpermil_ps>;
6101 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6102 memopv8f32, memopv8i32,
6103 int_x86_avx_vpermilvar_ps_256,
6104 int_x86_avx_vpermil_ps_256>;
6105 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6106 memopv2f64, memopv2i64,
6107 int_x86_avx_vpermilvar_pd,
6108 int_x86_avx_vpermil_pd>;
6109 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6110 memopv4f64, memopv4i64,
6111 int_x86_avx_vpermilvar_pd_256,
6112 int_x86_avx_vpermil_pd_256>;
6114 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6115 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6116 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6117 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6118 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6119 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6120 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6121 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6123 //===----------------------------------------------------------------------===//
6124 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6126 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6127 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6128 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6130 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6131 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6132 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6135 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
6136 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6137 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
6138 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6139 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
6140 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6142 def : Pat<(int_x86_avx_vperm2f128_ps_256
6143 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
6144 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6145 def : Pat<(int_x86_avx_vperm2f128_pd_256
6146 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
6147 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6148 def : Pat<(int_x86_avx_vperm2f128_si_256
6149 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
6150 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6152 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6153 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6154 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6155 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6156 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6157 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6158 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6159 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6160 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6161 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6162 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6163 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6165 //===----------------------------------------------------------------------===//
6166 // VZERO - Zero YMM registers
6168 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
6169 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
6170 // Zero All YMM registers
6171 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6172 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
6174 // Zero Upper bits of YMM registers
6175 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
6176 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
6179 //===----------------------------------------------------------------------===//
6180 // SSE Shuffle pattern fragments
6181 //===----------------------------------------------------------------------===//
6183 // This is part of a "work in progress" refactoring. The idea is that all
6184 // vector shuffles are going to be translated into target specific nodes and
6185 // directly matched by the patterns below (which can be changed along the way)
6186 // The AVX version of some but not all of them are described here, and more
6187 // should come in a near future.
6189 // Shuffle with MOVLHPD
6190 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
6191 (scalar_to_vector (loadf64 addr:$src2)))),
6192 (MOVHPDrm VR128:$src1, addr:$src2)>;
6194 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
6195 // is during lowering, where it's not possible to recognize the load fold cause
6196 // it has two uses through a bitcast. One use disappears at isel time and the
6197 // fold opportunity reappears.
6198 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
6199 (scalar_to_vector (loadf64 addr:$src2)))),
6200 (MOVHPDrm VR128:$src1, addr:$src2)>;
6202 // Shuffle with MOVSS
6203 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
6204 (MOVSSrr VR128:$src1, FR32:$src2)>;
6205 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
6206 (MOVSSrr (v4i32 VR128:$src1),
6207 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
6208 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
6209 (MOVSSrr (v4f32 VR128:$src1),
6210 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
6212 // Shuffle with MOVSD
6213 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
6214 (MOVSDrr VR128:$src1, FR64:$src2)>;
6215 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
6216 (MOVSDrr (v2i64 VR128:$src1),
6217 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
6218 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
6219 (MOVSDrr (v2f64 VR128:$src1),
6220 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
6221 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
6222 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
6223 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
6224 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
6226 // Shuffle with MOVLPS
6227 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
6228 (MOVLPSrm VR128:$src1, addr:$src2)>;
6229 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
6230 (MOVLPSrm VR128:$src1, addr:$src2)>;
6231 def : Pat<(X86Movlps VR128:$src1,
6232 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
6233 (MOVLPSrm VR128:$src1, addr:$src2)>;
6234 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
6235 // is during lowering, where it's not possible to recognize the load fold cause
6236 // it has two uses through a bitcast. One use disappears at isel time and the
6237 // fold opportunity reappears.
6238 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
6239 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
6241 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
6242 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
6244 // Shuffle with MOVLPD
6245 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6246 (MOVLPDrm VR128:$src1, addr:$src2)>;
6247 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6248 (MOVLPDrm VR128:$src1, addr:$src2)>;
6249 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
6250 (scalar_to_vector (loadf64 addr:$src2)))),
6251 (MOVLPDrm VR128:$src1, addr:$src2)>;
6253 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
6254 def : Pat<(store (f64 (vector_extract
6255 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6256 (MOVHPSmr addr:$dst, VR128:$src)>;
6257 def : Pat<(store (f64 (vector_extract
6258 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6259 (MOVHPDmr addr:$dst, VR128:$src)>;
6261 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
6262 (MOVLPSmr addr:$src1, VR128:$src2)>;
6263 def : Pat<(store (v4i32 (X86Movlps
6264 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
6265 (MOVLPSmr addr:$src1, VR128:$src2)>;
6267 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6268 (MOVLPDmr addr:$src1, VR128:$src2)>;
6269 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6270 (MOVLPDmr addr:$src1, VR128:$src2)>;