1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
272 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
273 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
274 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
275 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
276 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
277 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
278 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
279 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
280 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
281 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
282 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
283 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
286 // Implicitly promote a 32-bit scalar to a vector.
287 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
288 (COPY_TO_REGCLASS FR32:$src, VR128)>;
289 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
290 (COPY_TO_REGCLASS FR32:$src, VR128)>;
291 // Implicitly promote a 64-bit scalar to a vector.
292 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
293 (COPY_TO_REGCLASS FR64:$src, VR128)>;
294 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
295 (COPY_TO_REGCLASS FR64:$src, VR128)>;
297 // Bitcasts between 128-bit vector types. Return the original type since
298 // no instruction is needed for the conversion
299 let Predicates = [HasSSE2] in {
300 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
304 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
309 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
314 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
319 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
324 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
328 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
329 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
332 // Bitcasts between 256-bit vector types. Return the original type since
333 // no instruction is needed for the conversion
334 let Predicates = [HasAVX] in {
335 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
339 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
344 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
349 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
354 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
359 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
363 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
364 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
367 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
368 // This is expanded by ExpandPostRAPseudos.
369 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
371 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
372 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
373 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
374 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
377 //===----------------------------------------------------------------------===//
378 // AVX & SSE - Zero/One Vectors
379 //===----------------------------------------------------------------------===//
381 // Alias instruction that maps zero vector to pxor / xorp* for sse.
382 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
383 // swizzled by ExecutionDepsFix to pxor.
384 // We set canFoldAsLoad because this can be converted to a constant-pool
385 // load of an all-zeros value if folding it would be beneficial.
386 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
388 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
389 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
392 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
394 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
395 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
396 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
399 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
400 // and doesn't need it because on sandy bridge the register is set to zero
401 // at the rename stage without using any execution unit, so SET0PSY
402 // and SET0PDY can be used for vector int instructions without penalty
403 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
404 isPseudo = 1, Predicates = [HasAVX] in {
405 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
406 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
409 let Predicates = [HasAVX] in
410 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
412 let Predicates = [HasAVX2] in {
413 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
414 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
415 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
416 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
419 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
420 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
421 let Predicates = [HasAVX1Only] in {
422 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
423 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
424 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
426 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 // We set canFoldAsLoad because this can be converted to a constant-pool
440 // load of an all-ones value if folding it would be beneficial.
441 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
443 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
444 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
445 let Predicates = [HasAVX2] in
446 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
447 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
451 //===----------------------------------------------------------------------===//
452 // SSE 1 & 2 - Move FP Scalar Instructions
454 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
455 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
456 // is used instead. Register-to-register movss/movsd is not modeled as an
457 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
458 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
459 //===----------------------------------------------------------------------===//
461 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
462 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
463 [(set VR128:$dst, (vt (OpNode VR128:$src1,
464 (scalar_to_vector RC:$src2))))],
467 // Loading from memory automatically zeroing upper bits.
468 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
469 PatFrag mem_pat, string OpcodeStr> :
470 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
471 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
472 [(set RC:$dst, (mem_pat addr:$src))],
476 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
477 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
479 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
480 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
483 // For the disassembler
484 let isCodeGenOnly = 1 in {
485 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
486 (ins VR128:$src1, FR32:$src2),
487 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
490 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
491 (ins VR128:$src1, FR64:$src2),
492 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
497 let canFoldAsLoad = 1, isReMaterializable = 1 in {
498 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
500 let AddedComplexity = 20 in
501 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
505 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
506 "movss\t{$src, $dst|$dst, $src}",
507 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
509 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
510 "movsd\t{$src, $dst|$dst, $src}",
511 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
515 let Constraints = "$src1 = $dst" in {
516 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
517 "movss\t{$src2, $dst|$dst, $src2}">, XS;
518 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
519 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
521 // For the disassembler
522 let isCodeGenOnly = 1 in {
523 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
524 (ins VR128:$src1, FR32:$src2),
525 "movss\t{$src2, $dst|$dst, $src2}", [],
526 IIC_SSE_MOV_S_RR>, XS;
527 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
528 (ins VR128:$src1, FR64:$src2),
529 "movsd\t{$src2, $dst|$dst, $src2}", [],
530 IIC_SSE_MOV_S_RR>, XD;
534 let canFoldAsLoad = 1, isReMaterializable = 1 in {
535 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
537 let AddedComplexity = 20 in
538 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
541 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
542 "movss\t{$src, $dst|$dst, $src}",
543 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
544 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
545 "movsd\t{$src, $dst|$dst, $src}",
546 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
549 let Predicates = [HasAVX] in {
550 let AddedComplexity = 15 in {
551 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
552 // MOVS{S,D} to the lower bits.
553 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
554 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
555 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
556 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
557 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
558 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
559 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
560 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
562 // Move low f32 and clear high bits.
563 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
564 (SUBREG_TO_REG (i32 0),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
567 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
568 (SUBREG_TO_REG (i32 0),
569 (VMOVSSrr (v4i32 (V_SET0)),
570 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
573 let AddedComplexity = 20 in {
574 // MOVSSrm zeros the high parts of the register; represent this
575 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
576 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
577 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
578 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
579 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
580 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
581 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
583 // MOVSDrm zeros the high parts of the register; represent this
584 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
585 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
586 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
587 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
588 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
589 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
590 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
591 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
592 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
593 def : Pat<(v2f64 (X86vzload addr:$src)),
594 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
596 // Represent the same patterns above but in the form they appear for
598 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
599 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
600 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
601 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
602 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
603 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
604 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
605 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
606 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
608 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
609 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
610 (SUBREG_TO_REG (i32 0),
611 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
613 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
614 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
615 (SUBREG_TO_REG (i64 0),
616 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
618 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
619 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
620 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
622 // Move low f64 and clear high bits.
623 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
624 (SUBREG_TO_REG (i32 0),
625 (VMOVSDrr (v2f64 (V_SET0)),
626 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
628 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
629 (SUBREG_TO_REG (i32 0),
630 (VMOVSDrr (v2i64 (V_SET0)),
631 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
633 // Extract and store.
634 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
636 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
637 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
639 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
641 // Shuffle with VMOVSS
642 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
643 (VMOVSSrr (v4i32 VR128:$src1),
644 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
645 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
646 (VMOVSSrr (v4f32 VR128:$src1),
647 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
650 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
651 (SUBREG_TO_REG (i32 0),
652 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
653 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
655 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
656 (SUBREG_TO_REG (i32 0),
657 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
658 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
661 // Shuffle with VMOVSD
662 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
663 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
664 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
665 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
666 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
667 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
668 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
669 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
673 (SUBREG_TO_REG (i32 0),
674 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
675 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
677 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
678 (SUBREG_TO_REG (i32 0),
679 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
680 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
684 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
685 // is during lowering, where it's not possible to recognize the fold cause
686 // it has two uses through a bitcast. One use disappears at isel time and the
687 // fold opportunity reappears.
688 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
689 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
690 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
691 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
692 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
693 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
694 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
695 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
698 let Predicates = [UseSSE1] in {
699 let AddedComplexity = 15 in {
700 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
701 // MOVSS to the lower bits.
702 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
703 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
704 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
705 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
706 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
707 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
710 let AddedComplexity = 20 in {
711 // MOVSSrm already zeros the high parts of the register.
712 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
713 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
714 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
715 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
716 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
717 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
720 // Extract and store.
721 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
723 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
725 // Shuffle with MOVSS
726 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
727 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
728 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
729 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
732 let Predicates = [UseSSE2] in {
733 let AddedComplexity = 15 in {
734 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
735 // MOVSD to the lower bits.
736 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
737 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
740 let AddedComplexity = 20 in {
741 // MOVSDrm already zeros the high parts of the register.
742 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
743 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
744 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
745 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
746 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
747 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
748 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
749 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
750 def : Pat<(v2f64 (X86vzload addr:$src)),
751 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
754 // Extract and store.
755 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
757 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
759 // Shuffle with MOVSD
760 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
761 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
762 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
763 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
764 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
765 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
766 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
767 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
769 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
770 // is during lowering, where it's not possible to recognize the fold cause
771 // it has two uses through a bitcast. One use disappears at isel time and the
772 // fold opportunity reappears.
773 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
774 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
775 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
776 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
777 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
778 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
779 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
780 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
783 //===----------------------------------------------------------------------===//
784 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
785 //===----------------------------------------------------------------------===//
787 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
788 X86MemOperand x86memop, PatFrag ld_frag,
789 string asm, Domain d,
791 bit IsReMaterializable = 1> {
792 let neverHasSideEffects = 1 in
793 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
794 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
795 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
796 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
797 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
798 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
801 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
802 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
804 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
805 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
807 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
808 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
810 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
811 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
814 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
815 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
817 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
818 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
819 TB, OpSize, VEX, VEX_L;
820 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
821 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
823 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
824 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
825 TB, OpSize, VEX, VEX_L;
826 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
827 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
829 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
830 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
832 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
833 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
835 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
836 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
839 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
840 "movaps\t{$src, $dst|$dst, $src}",
841 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
842 IIC_SSE_MOVA_P_MR>, VEX;
843 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
844 "movapd\t{$src, $dst|$dst, $src}",
845 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
846 IIC_SSE_MOVA_P_MR>, VEX;
847 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
848 "movups\t{$src, $dst|$dst, $src}",
849 [(store (v4f32 VR128:$src), addr:$dst)],
850 IIC_SSE_MOVU_P_MR>, VEX;
851 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
852 "movupd\t{$src, $dst|$dst, $src}",
853 [(store (v2f64 VR128:$src), addr:$dst)],
854 IIC_SSE_MOVU_P_MR>, VEX;
855 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
856 "movaps\t{$src, $dst|$dst, $src}",
857 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
858 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
859 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
860 "movapd\t{$src, $dst|$dst, $src}",
861 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
862 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
863 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
864 "movups\t{$src, $dst|$dst, $src}",
865 [(store (v8f32 VR256:$src), addr:$dst)],
866 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
867 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
868 "movupd\t{$src, $dst|$dst, $src}",
869 [(store (v4f64 VR256:$src), addr:$dst)],
870 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
873 let isCodeGenOnly = 1 in {
874 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
876 "movaps\t{$src, $dst|$dst, $src}", [],
877 IIC_SSE_MOVA_P_RR>, VEX;
878 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
880 "movapd\t{$src, $dst|$dst, $src}", [],
881 IIC_SSE_MOVA_P_RR>, VEX;
882 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
884 "movups\t{$src, $dst|$dst, $src}", [],
885 IIC_SSE_MOVU_P_RR>, VEX;
886 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
888 "movupd\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVU_P_RR>, VEX;
890 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
892 "movaps\t{$src, $dst|$dst, $src}", [],
893 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
894 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
896 "movapd\t{$src, $dst|$dst, $src}", [],
897 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
898 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
900 "movups\t{$src, $dst|$dst, $src}", [],
901 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
902 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
904 "movupd\t{$src, $dst|$dst, $src}", [],
905 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
908 let Predicates = [HasAVX] in {
909 def : Pat<(v8i32 (X86vzmovl
910 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
911 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
912 def : Pat<(v4i64 (X86vzmovl
913 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
914 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
915 def : Pat<(v8f32 (X86vzmovl
916 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
917 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
918 def : Pat<(v4f64 (X86vzmovl
919 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
920 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
924 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
925 (VMOVUPSYmr addr:$dst, VR256:$src)>;
926 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
927 (VMOVUPDYmr addr:$dst, VR256:$src)>;
929 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
930 "movaps\t{$src, $dst|$dst, $src}",
931 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
933 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
934 "movapd\t{$src, $dst|$dst, $src}",
935 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
937 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
938 "movups\t{$src, $dst|$dst, $src}",
939 [(store (v4f32 VR128:$src), addr:$dst)],
941 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
942 "movupd\t{$src, $dst|$dst, $src}",
943 [(store (v2f64 VR128:$src), addr:$dst)],
947 let isCodeGenOnly = 1 in {
948 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
949 "movaps\t{$src, $dst|$dst, $src}", [],
951 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
952 "movapd\t{$src, $dst|$dst, $src}", [],
954 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
955 "movups\t{$src, $dst|$dst, $src}", [],
957 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
958 "movupd\t{$src, $dst|$dst, $src}", [],
962 let Predicates = [HasAVX] in {
963 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
964 (VMOVUPSmr addr:$dst, VR128:$src)>;
965 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
966 (VMOVUPDmr addr:$dst, VR128:$src)>;
969 let Predicates = [UseSSE1] in
970 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
971 (MOVUPSmr addr:$dst, VR128:$src)>;
972 let Predicates = [UseSSE2] in
973 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
974 (MOVUPDmr addr:$dst, VR128:$src)>;
976 // Use vmovaps/vmovups for AVX integer load/store.
977 let Predicates = [HasAVX] in {
978 // 128-bit load/store
979 def : Pat<(alignedloadv2i64 addr:$src),
980 (VMOVAPSrm addr:$src)>;
981 def : Pat<(loadv2i64 addr:$src),
982 (VMOVUPSrm addr:$src)>;
984 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
985 (VMOVAPSmr addr:$dst, VR128:$src)>;
986 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
987 (VMOVAPSmr addr:$dst, VR128:$src)>;
988 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
989 (VMOVAPSmr addr:$dst, VR128:$src)>;
990 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
991 (VMOVAPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
993 (VMOVUPSmr addr:$dst, VR128:$src)>;
994 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
995 (VMOVUPSmr addr:$dst, VR128:$src)>;
996 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
999 (VMOVUPSmr addr:$dst, VR128:$src)>;
1001 // 256-bit load/store
1002 def : Pat<(alignedloadv4i64 addr:$src),
1003 (VMOVAPSYrm addr:$src)>;
1004 def : Pat<(loadv4i64 addr:$src),
1005 (VMOVUPSYrm addr:$src)>;
1006 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1007 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1008 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1009 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1010 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1011 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1012 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1013 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1014 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1015 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1016 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1017 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1018 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1019 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1020 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1021 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1023 // Special patterns for storing subvector extracts of lower 128-bits
1024 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1025 def : Pat<(alignedstore (v2f64 (extract_subvector
1026 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1027 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1028 def : Pat<(alignedstore (v4f32 (extract_subvector
1029 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1030 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1031 def : Pat<(alignedstore (v2i64 (extract_subvector
1032 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1033 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1034 def : Pat<(alignedstore (v4i32 (extract_subvector
1035 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1036 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1037 def : Pat<(alignedstore (v8i16 (extract_subvector
1038 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1039 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1040 def : Pat<(alignedstore (v16i8 (extract_subvector
1041 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1042 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1044 def : Pat<(store (v2f64 (extract_subvector
1045 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1046 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1047 def : Pat<(store (v4f32 (extract_subvector
1048 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1049 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1050 def : Pat<(store (v2i64 (extract_subvector
1051 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1052 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1053 def : Pat<(store (v4i32 (extract_subvector
1054 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1055 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1056 def : Pat<(store (v8i16 (extract_subvector
1057 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1058 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1059 def : Pat<(store (v16i8 (extract_subvector
1060 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1061 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 // Use movaps / movups for SSE integer load / store (one byte shorter).
1065 // The instructions selected below are then converted to MOVDQA/MOVDQU
1066 // during the SSE domain pass.
1067 let Predicates = [UseSSE1] in {
1068 def : Pat<(alignedloadv2i64 addr:$src),
1069 (MOVAPSrm addr:$src)>;
1070 def : Pat<(loadv2i64 addr:$src),
1071 (MOVUPSrm addr:$src)>;
1073 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1074 (MOVAPSmr addr:$dst, VR128:$src)>;
1075 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1076 (MOVAPSmr addr:$dst, VR128:$src)>;
1077 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1078 (MOVAPSmr addr:$dst, VR128:$src)>;
1079 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1080 (MOVAPSmr addr:$dst, VR128:$src)>;
1081 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1082 (MOVUPSmr addr:$dst, VR128:$src)>;
1083 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1084 (MOVUPSmr addr:$dst, VR128:$src)>;
1085 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1086 (MOVUPSmr addr:$dst, VR128:$src)>;
1087 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1088 (MOVUPSmr addr:$dst, VR128:$src)>;
1091 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1092 // bits are disregarded. FIXME: Set encoding to pseudo!
1093 let neverHasSideEffects = 1 in {
1094 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1095 "movaps\t{$src, $dst|$dst, $src}", [],
1096 IIC_SSE_MOVA_P_RR>, VEX;
1097 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1098 "movapd\t{$src, $dst|$dst, $src}", [],
1099 IIC_SSE_MOVA_P_RR>, VEX;
1100 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1101 "movaps\t{$src, $dst|$dst, $src}", [],
1103 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1104 "movapd\t{$src, $dst|$dst, $src}", [],
1108 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1109 // bits are disregarded. FIXME: Set encoding to pseudo!
1110 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1111 let isCodeGenOnly = 1 in {
1112 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1113 "movaps\t{$src, $dst|$dst, $src}",
1114 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1115 IIC_SSE_MOVA_P_RM>, VEX;
1116 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1117 "movapd\t{$src, $dst|$dst, $src}",
1118 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1119 IIC_SSE_MOVA_P_RM>, VEX;
1121 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1122 "movaps\t{$src, $dst|$dst, $src}",
1123 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1125 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1126 "movapd\t{$src, $dst|$dst, $src}",
1127 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1131 //===----------------------------------------------------------------------===//
1132 // SSE 1 & 2 - Move Low packed FP Instructions
1133 //===----------------------------------------------------------------------===//
1135 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1136 SDNode psnode, SDNode pdnode, string base_opc,
1137 string asm_opr, InstrItinClass itin> {
1138 def PSrm : PI<opc, MRMSrcMem,
1139 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1140 !strconcat(base_opc, "s", asm_opr),
1143 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1144 itin, SSEPackedSingle>, TB;
1146 def PDrm : PI<opc, MRMSrcMem,
1147 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1148 !strconcat(base_opc, "d", asm_opr),
1149 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1150 (scalar_to_vector (loadf64 addr:$src2)))))],
1151 itin, SSEPackedDouble>, TB, OpSize;
1154 let AddedComplexity = 20 in {
1155 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1156 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1157 IIC_SSE_MOV_LH>, VEX_4V;
1159 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1160 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1161 "\t{$src2, $dst|$dst, $src2}",
1165 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1166 "movlps\t{$src, $dst|$dst, $src}",
1167 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1168 (iPTR 0))), addr:$dst)],
1169 IIC_SSE_MOV_LH>, VEX;
1170 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1171 "movlpd\t{$src, $dst|$dst, $src}",
1172 [(store (f64 (vector_extract (v2f64 VR128:$src),
1173 (iPTR 0))), addr:$dst)],
1174 IIC_SSE_MOV_LH>, VEX;
1175 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1176 "movlps\t{$src, $dst|$dst, $src}",
1177 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1178 (iPTR 0))), addr:$dst)],
1180 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1181 "movlpd\t{$src, $dst|$dst, $src}",
1182 [(store (f64 (vector_extract (v2f64 VR128:$src),
1183 (iPTR 0))), addr:$dst)],
1186 let Predicates = [HasAVX] in {
1187 // Shuffle with VMOVLPS
1188 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1189 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1190 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1191 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1193 // Shuffle with VMOVLPD
1194 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1195 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1196 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1197 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1200 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1202 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1203 def : Pat<(store (v4i32 (X86Movlps
1204 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1205 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1206 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1208 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1209 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1211 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1214 let Predicates = [UseSSE1] in {
1215 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1216 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1217 (iPTR 0))), addr:$src1),
1218 (MOVLPSmr addr:$src1, VR128:$src2)>;
1220 // Shuffle with MOVLPS
1221 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1222 (MOVLPSrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1224 (MOVLPSrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(X86Movlps VR128:$src1,
1226 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1227 (MOVLPSrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (MOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1236 (MOVLPSmr addr:$src1, VR128:$src2)>;
1239 let Predicates = [UseSSE2] in {
1240 // Shuffle with MOVLPD
1241 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1242 (MOVLPDrm VR128:$src1, addr:$src2)>;
1243 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1244 (MOVLPDrm VR128:$src1, addr:$src2)>;
1247 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1249 (MOVLPDmr addr:$src1, VR128:$src2)>;
1250 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1252 (MOVLPDmr addr:$src1, VR128:$src2)>;
1255 //===----------------------------------------------------------------------===//
1256 // SSE 1 & 2 - Move Hi packed FP Instructions
1257 //===----------------------------------------------------------------------===//
1259 let AddedComplexity = 20 in {
1260 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1261 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1262 IIC_SSE_MOV_LH>, VEX_4V;
1264 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1265 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1266 "\t{$src2, $dst|$dst, $src2}",
1270 // v2f64 extract element 1 is always custom lowered to unpack high to low
1271 // and extract element 0 so the non-store version isn't too horrible.
1272 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1273 "movhps\t{$src, $dst|$dst, $src}",
1274 [(store (f64 (vector_extract
1275 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1276 (bc_v2f64 (v4f32 VR128:$src))),
1277 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1278 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1279 "movhpd\t{$src, $dst|$dst, $src}",
1280 [(store (f64 (vector_extract
1281 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1282 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1283 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1284 "movhps\t{$src, $dst|$dst, $src}",
1285 [(store (f64 (vector_extract
1286 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1287 (bc_v2f64 (v4f32 VR128:$src))),
1288 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1289 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1290 "movhpd\t{$src, $dst|$dst, $src}",
1291 [(store (f64 (vector_extract
1292 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1293 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1295 let Predicates = [HasAVX] in {
1297 def : Pat<(X86Movlhps VR128:$src1,
1298 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1299 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1300 def : Pat<(X86Movlhps VR128:$src1,
1301 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1302 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1304 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1305 // is during lowering, where it's not possible to recognize the load fold
1306 // cause it has two uses through a bitcast. One use disappears at isel time
1307 // and the fold opportunity reappears.
1308 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1309 (scalar_to_vector (loadf64 addr:$src2)))),
1310 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1313 let Predicates = [UseSSE1] in {
1315 def : Pat<(X86Movlhps VR128:$src1,
1316 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1317 (MOVHPSrm VR128:$src1, addr:$src2)>;
1318 def : Pat<(X86Movlhps VR128:$src1,
1319 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1320 (MOVHPSrm VR128:$src1, addr:$src2)>;
1323 let Predicates = [UseSSE2] in {
1324 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1325 // is during lowering, where it's not possible to recognize the load fold
1326 // cause it has two uses through a bitcast. One use disappears at isel time
1327 // and the fold opportunity reappears.
1328 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1329 (scalar_to_vector (loadf64 addr:$src2)))),
1330 (MOVHPDrm VR128:$src1, addr:$src2)>;
1333 //===----------------------------------------------------------------------===//
1334 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1335 //===----------------------------------------------------------------------===//
1337 let AddedComplexity = 20 in {
1338 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1339 (ins VR128:$src1, VR128:$src2),
1340 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1342 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1345 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1346 (ins VR128:$src1, VR128:$src2),
1347 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1349 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1353 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1354 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1355 (ins VR128:$src1, VR128:$src2),
1356 "movlhps\t{$src2, $dst|$dst, $src2}",
1358 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1360 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1361 (ins VR128:$src1, VR128:$src2),
1362 "movhlps\t{$src2, $dst|$dst, $src2}",
1364 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1368 let Predicates = [HasAVX] in {
1370 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1371 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1372 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1373 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1376 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1377 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1380 let Predicates = [UseSSE1] in {
1382 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1383 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1384 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1385 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1388 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1389 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1392 //===----------------------------------------------------------------------===//
1393 // SSE 1 & 2 - Conversion Instructions
1394 //===----------------------------------------------------------------------===//
1396 def SSE_CVT_PD : OpndItins<
1397 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1400 def SSE_CVT_PS : OpndItins<
1401 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1404 def SSE_CVT_Scalar : OpndItins<
1405 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1408 def SSE_CVT_SS2SI_32 : OpndItins<
1409 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1412 def SSE_CVT_SS2SI_64 : OpndItins<
1413 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1416 def SSE_CVT_SD2SI : OpndItins<
1417 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1420 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1421 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1422 string asm, OpndItins itins> {
1423 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1424 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1426 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1427 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1431 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1432 X86MemOperand x86memop, string asm, Domain d,
1434 let neverHasSideEffects = 1 in {
1435 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1438 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1443 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1444 X86MemOperand x86memop, string asm> {
1445 let neverHasSideEffects = 1 in {
1446 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1447 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1449 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1450 (ins DstRC:$src1, x86memop:$src),
1451 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1452 } // neverHasSideEffects = 1
1455 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1456 "cvttss2si\t{$src, $dst|$dst, $src}",
1459 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1460 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1462 XS, VEX, VEX_W, VEX_LIG;
1463 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1464 "cvttsd2si\t{$src, $dst|$dst, $src}",
1467 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1468 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1470 XD, VEX, VEX_W, VEX_LIG;
1472 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1473 // register, but the same isn't true when only using memory operands,
1474 // provide other assembly "l" and "q" forms to address this explicitly
1475 // where appropriate to do so.
1476 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1477 XS, VEX_4V, VEX_LIG;
1478 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1479 XS, VEX_4V, VEX_W, VEX_LIG;
1480 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1481 XD, VEX_4V, VEX_LIG;
1482 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1483 XD, VEX_4V, VEX_W, VEX_LIG;
1485 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1486 (VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
1487 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1488 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1490 let Predicates = [HasAVX] in {
1491 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1492 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1493 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1494 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1495 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1496 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1497 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1498 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1500 def : Pat<(f32 (sint_to_fp GR32:$src)),
1501 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1502 def : Pat<(f32 (sint_to_fp GR64:$src)),
1503 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1504 def : Pat<(f64 (sint_to_fp GR32:$src)),
1505 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1506 def : Pat<(f64 (sint_to_fp GR64:$src)),
1507 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1510 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1511 "cvttss2si\t{$src, $dst|$dst, $src}",
1512 SSE_CVT_SS2SI_32>, XS;
1513 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1514 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1515 SSE_CVT_SS2SI_64>, XS, REX_W;
1516 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1517 "cvttsd2si\t{$src, $dst|$dst, $src}",
1519 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1520 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1521 SSE_CVT_SD2SI>, XD, REX_W;
1522 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1523 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1524 SSE_CVT_Scalar>, XS;
1525 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1526 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1527 SSE_CVT_Scalar>, XS, REX_W;
1528 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1529 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1530 SSE_CVT_Scalar>, XD;
1531 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1532 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1533 SSE_CVT_Scalar>, XD, REX_W;
1535 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1536 // and/or XMM operand(s).
1538 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1539 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1540 string asm, OpndItins itins> {
1541 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1542 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1543 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1544 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1545 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1546 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>;
1549 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1550 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1551 PatFrag ld_frag, string asm, OpndItins itins,
1553 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1555 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1556 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1557 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1559 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1560 (ins DstRC:$src1, x86memop:$src2),
1562 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1563 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1564 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1568 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1569 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si{l}",
1570 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1571 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1572 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si{q}",
1573 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1575 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1576 sdmem, sse_load_f64, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1577 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1578 sdmem, sse_load_f64, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1581 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1582 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1583 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1584 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1585 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1586 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1588 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1589 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1590 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1591 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1592 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1593 SSE_CVT_Scalar, 0>, XD,
1596 let Constraints = "$src1 = $dst" in {
1597 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1598 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1599 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1600 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1601 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1602 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1603 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1604 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1605 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1606 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1607 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1608 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1613 // Aliases for intrinsics
1614 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1615 ssmem, sse_load_f32, "cvttss2si",
1616 SSE_CVT_SS2SI_32>, XS, VEX;
1617 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1618 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1619 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1621 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1622 sdmem, sse_load_f64, "cvttsd2si",
1623 SSE_CVT_SD2SI>, XD, VEX;
1624 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1625 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1626 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1628 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1629 ssmem, sse_load_f32, "cvttss2si",
1630 SSE_CVT_SS2SI_32>, XS;
1631 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1632 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1633 "cvttss2si{q}", SSE_CVT_SS2SI_64>, XS, REX_W;
1634 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1635 sdmem, sse_load_f64, "cvttsd2si",
1637 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1638 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1639 "cvttsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1641 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1642 ssmem, sse_load_f32, "cvtss2si{l}",
1643 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1644 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1645 ssmem, sse_load_f32, "cvtss2si{q}",
1646 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1648 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1649 ssmem, sse_load_f32, "cvtss2si{l}",
1650 SSE_CVT_SS2SI_32>, XS;
1651 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1652 ssmem, sse_load_f32, "cvtss2si{q}",
1653 SSE_CVT_SS2SI_64>, XS, REX_W;
1655 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1656 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1657 SSEPackedSingle, SSE_CVT_PS>,
1658 TB, VEX, Requires<[HasAVX]>;
1659 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1660 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1661 SSEPackedSingle, SSE_CVT_PS>,
1662 TB, VEX, VEX_L, Requires<[HasAVX]>;
1664 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1665 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1666 SSEPackedSingle, SSE_CVT_PS>,
1667 TB, Requires<[UseSSE2]>;
1671 // Convert scalar double to scalar single
1672 let neverHasSideEffects = 1 in {
1673 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1674 (ins FR64:$src1, FR64:$src2),
1675 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1676 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1678 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1679 (ins FR64:$src1, f64mem:$src2),
1680 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1681 [], IIC_SSE_CVT_Scalar_RM>,
1682 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1685 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1688 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1689 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1690 [(set FR32:$dst, (fround FR64:$src))],
1691 IIC_SSE_CVT_Scalar_RR>;
1692 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1693 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1694 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1695 IIC_SSE_CVT_Scalar_RM>,
1697 Requires<[UseSSE2, OptForSize]>;
1699 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1700 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1701 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1703 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1704 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
1705 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1706 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1707 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1708 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1709 VR128:$src1, sse_load_f64:$src2))],
1710 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
1712 let Constraints = "$src1 = $dst" in {
1713 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1714 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1715 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1717 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1718 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>;
1719 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1720 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1721 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1722 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1723 VR128:$src1, sse_load_f64:$src2))],
1724 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>;
1727 // Convert scalar single to scalar double
1728 // SSE2 instructions with XS prefix
1729 let neverHasSideEffects = 1 in {
1730 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1731 (ins FR32:$src1, FR32:$src2),
1732 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1733 [], IIC_SSE_CVT_Scalar_RR>,
1734 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1736 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1737 (ins FR32:$src1, f32mem:$src2),
1738 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1739 [], IIC_SSE_CVT_Scalar_RM>,
1740 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1743 def : Pat<(f64 (fextend FR32:$src)),
1744 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1745 def : Pat<(fextend (loadf32 addr:$src)),
1746 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1748 def : Pat<(extloadf32 addr:$src),
1749 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1750 Requires<[HasAVX, OptForSize]>;
1751 def : Pat<(extloadf32 addr:$src),
1752 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1753 Requires<[HasAVX, OptForSpeed]>;
1755 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1756 "cvtss2sd\t{$src, $dst|$dst, $src}",
1757 [(set FR64:$dst, (fextend FR32:$src))],
1758 IIC_SSE_CVT_Scalar_RR>, XS,
1759 Requires<[UseSSE2]>;
1760 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1761 "cvtss2sd\t{$src, $dst|$dst, $src}",
1762 [(set FR64:$dst, (extloadf32 addr:$src))],
1763 IIC_SSE_CVT_Scalar_RM>, XS,
1764 Requires<[UseSSE2, OptForSize]>;
1766 // extload f32 -> f64. This matches load+fextend because we have a hack in
1767 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1769 // Since these loads aren't folded into the fextend, we have to match it
1771 def : Pat<(fextend (loadf32 addr:$src)),
1772 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1773 def : Pat<(extloadf32 addr:$src),
1774 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1776 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1777 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1778 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1780 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1781 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
1782 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1783 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1784 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1786 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1787 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
1788 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1789 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1790 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1791 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1793 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1794 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>;
1795 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1796 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1797 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1799 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1800 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>;
1803 // Convert packed single/double fp to doubleword
1804 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvtps2dq\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1807 IIC_SSE_CVT_PS_RR>, VEX;
1808 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1809 "cvtps2dq\t{$src, $dst|$dst, $src}",
1811 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1812 IIC_SSE_CVT_PS_RM>, VEX;
1813 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1814 "cvtps2dq\t{$src, $dst|$dst, $src}",
1816 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1817 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1818 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1819 "cvtps2dq\t{$src, $dst|$dst, $src}",
1821 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1822 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1823 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1824 "cvtps2dq\t{$src, $dst|$dst, $src}",
1825 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1827 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1828 "cvtps2dq\t{$src, $dst|$dst, $src}",
1830 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1834 // Convert Packed Double FP to Packed DW Integers
1835 let Predicates = [HasAVX] in {
1836 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1837 // register, but the same isn't true when using memory operands instead.
1838 // Provide other assembly rr and rm forms to address this explicitly.
1839 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1840 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1841 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1845 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1846 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1847 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1848 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1850 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
1853 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1854 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1856 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L;
1857 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1858 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1860 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1862 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1863 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1866 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1867 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1869 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1871 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1872 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1873 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1876 // Convert with truncation packed single/double fp to doubleword
1877 // SSE2 packed instructions with XS prefix
1878 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1879 "cvttps2dq\t{$src, $dst|$dst, $src}",
1881 (int_x86_sse2_cvttps2dq VR128:$src))],
1882 IIC_SSE_CVT_PS_RR>, VEX;
1883 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1884 "cvttps2dq\t{$src, $dst|$dst, $src}",
1885 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1886 (memopv4f32 addr:$src)))],
1887 IIC_SSE_CVT_PS_RM>, VEX;
1888 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1889 "cvttps2dq\t{$src, $dst|$dst, $src}",
1891 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1892 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1893 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1894 "cvttps2dq\t{$src, $dst|$dst, $src}",
1895 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1896 (memopv8f32 addr:$src)))],
1897 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1899 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 "cvttps2dq\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1903 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1904 "cvttps2dq\t{$src, $dst|$dst, $src}",
1906 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1909 let Predicates = [HasAVX] in {
1910 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1911 (VCVTDQ2PSrr VR128:$src)>;
1912 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1913 (VCVTDQ2PSrm addr:$src)>;
1915 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1916 (VCVTDQ2PSrr VR128:$src)>;
1917 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1918 (VCVTDQ2PSrm addr:$src)>;
1920 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1921 (VCVTTPS2DQrr VR128:$src)>;
1922 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1923 (VCVTTPS2DQrm addr:$src)>;
1925 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1926 (VCVTDQ2PSYrr VR256:$src)>;
1927 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1928 (VCVTDQ2PSYrm addr:$src)>;
1930 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1931 (VCVTTPS2DQYrr VR256:$src)>;
1932 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1933 (VCVTTPS2DQYrm addr:$src)>;
1936 let Predicates = [UseSSE2] in {
1937 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1938 (CVTDQ2PSrr VR128:$src)>;
1939 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1940 (CVTDQ2PSrm addr:$src)>;
1942 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1943 (CVTDQ2PSrr VR128:$src)>;
1944 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1945 (CVTDQ2PSrm addr:$src)>;
1947 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1948 (CVTTPS2DQrr VR128:$src)>;
1949 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1950 (CVTTPS2DQrm addr:$src)>;
1953 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1954 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1956 (int_x86_sse2_cvttpd2dq VR128:$src))],
1957 IIC_SSE_CVT_PD_RR>, VEX;
1959 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1960 // register, but the same isn't true when using memory operands instead.
1961 // Provide other assembly rr and rm forms to address this explicitly.
1964 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
1965 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
1966 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1967 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
1968 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1969 (memopv2f64 addr:$src)))],
1970 IIC_SSE_CVT_PD_RM>, VEX;
1973 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1974 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1976 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
1977 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
1978 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1979 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1981 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
1982 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1983 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
1984 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
1986 let Predicates = [HasAVX] in {
1987 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
1988 (VCVTTPD2DQYrr VR256:$src)>;
1989 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
1990 (VCVTTPD2DQYrm addr:$src)>;
1991 } // Predicates = [HasAVX]
1993 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1994 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1995 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1997 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1998 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1999 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2000 (memopv2f64 addr:$src)))],
2003 // Convert packed single to packed double
2004 let Predicates = [HasAVX] in {
2005 // SSE2 instructions without OpSize prefix
2006 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2007 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2008 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2009 IIC_SSE_CVT_PD_RR>, TB, VEX;
2010 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2011 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2012 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2013 IIC_SSE_CVT_PD_RM>, TB, VEX;
2014 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2015 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2017 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2018 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L;
2019 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2020 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2022 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2023 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L;
2026 let Predicates = [UseSSE2] in {
2027 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2028 "cvtps2pd\t{$src, $dst|$dst, $src}",
2029 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2030 IIC_SSE_CVT_PD_RR>, TB;
2031 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2032 "cvtps2pd\t{$src, $dst|$dst, $src}",
2033 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2034 IIC_SSE_CVT_PD_RM>, TB;
2037 // Convert Packed DW Integers to Packed Double FP
2038 let Predicates = [HasAVX] in {
2039 let neverHasSideEffects = 1, mayLoad = 1 in
2040 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2041 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2043 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
2047 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2048 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2050 (int_x86_avx_cvtdq2_pd_256
2051 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L;
2052 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2053 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2055 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L;
2058 let neverHasSideEffects = 1, mayLoad = 1 in
2059 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2060 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2062 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2063 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2064 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2067 // AVX 256-bit register conversion intrinsics
2068 let Predicates = [HasAVX] in {
2069 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2070 (VCVTDQ2PDYrr VR128:$src)>;
2071 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2072 (VCVTDQ2PDYrm addr:$src)>;
2073 } // Predicates = [HasAVX]
2075 // Convert packed double to packed single
2076 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2077 // register, but the same isn't true when using memory operands instead.
2078 // Provide other assembly rr and rm forms to address this explicitly.
2079 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2080 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2081 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2082 IIC_SSE_CVT_PD_RR>, VEX;
2085 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2086 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2087 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2088 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2090 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2091 IIC_SSE_CVT_PD_RM>, VEX;
2094 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2095 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2097 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2098 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
2099 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2100 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2102 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2103 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2104 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2105 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2107 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2108 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2109 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2111 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2112 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2114 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2118 // AVX 256-bit register conversion intrinsics
2119 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2120 // whenever possible to avoid declaring two versions of each one.
2121 let Predicates = [HasAVX] in {
2122 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2123 (VCVTDQ2PSYrr VR256:$src)>;
2124 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2125 (VCVTDQ2PSYrm addr:$src)>;
2127 // Match fround and fextend for 128/256-bit conversions
2128 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2129 (VCVTPD2PSrr VR128:$src)>;
2130 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2131 (VCVTPD2PSXrm addr:$src)>;
2132 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2133 (VCVTPD2PSYrr VR256:$src)>;
2134 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2135 (VCVTPD2PSYrm addr:$src)>;
2137 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2138 (VCVTPS2PDrr VR128:$src)>;
2139 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2140 (VCVTPS2PDYrr VR128:$src)>;
2141 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2142 (VCVTPS2PDYrm addr:$src)>;
2145 let Predicates = [UseSSE2] in {
2146 // Match fround and fextend for 128 conversions
2147 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2148 (CVTPD2PSrr VR128:$src)>;
2149 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2150 (CVTPD2PSrm addr:$src)>;
2152 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2153 (CVTPS2PDrr VR128:$src)>;
2156 //===----------------------------------------------------------------------===//
2157 // SSE 1 & 2 - Compare Instructions
2158 //===----------------------------------------------------------------------===//
2160 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2161 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2162 Operand CC, SDNode OpNode, ValueType VT,
2163 PatFrag ld_frag, string asm, string asm_alt,
2165 def rr : SIi8<0xC2, MRMSrcReg,
2166 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2167 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2169 def rm : SIi8<0xC2, MRMSrcMem,
2170 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2171 [(set RC:$dst, (OpNode (VT RC:$src1),
2172 (ld_frag addr:$src2), imm:$cc))],
2175 // Accept explicit immediate argument form instead of comparison code.
2176 let neverHasSideEffects = 1 in {
2177 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2178 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2179 IIC_SSE_ALU_F32S_RR>;
2181 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2182 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2183 IIC_SSE_ALU_F32S_RM>;
2187 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2188 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2189 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2191 XS, VEX_4V, VEX_LIG;
2192 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2193 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2194 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2195 SSE_ALU_F32S>, // same latency as 32 bit compare
2196 XD, VEX_4V, VEX_LIG;
2198 let Constraints = "$src1 = $dst" in {
2199 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2200 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2201 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2203 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2204 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2205 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2206 SSE_ALU_F32S>, // same latency as 32 bit compare
2210 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2211 Intrinsic Int, string asm, OpndItins itins> {
2212 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2213 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2214 [(set VR128:$dst, (Int VR128:$src1,
2215 VR128:$src, imm:$cc))],
2217 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2218 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2219 [(set VR128:$dst, (Int VR128:$src1,
2220 (load addr:$src), imm:$cc))],
2224 // Aliases to match intrinsics which expect XMM operand(s).
2225 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2226 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2229 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2230 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2231 SSE_ALU_F32S>, // same latency as f32
2233 let Constraints = "$src1 = $dst" in {
2234 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2235 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2237 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2238 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2239 SSE_ALU_F32S>, // same latency as f32
2244 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2245 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2246 ValueType vt, X86MemOperand x86memop,
2247 PatFrag ld_frag, string OpcodeStr, Domain d> {
2248 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2249 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2250 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2251 IIC_SSE_COMIS_RR, d>;
2252 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2253 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2254 [(set EFLAGS, (OpNode (vt RC:$src1),
2255 (ld_frag addr:$src2)))],
2256 IIC_SSE_COMIS_RM, d>;
2259 let Defs = [EFLAGS] in {
2260 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2261 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2262 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2263 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2265 let Pattern = []<dag> in {
2266 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2267 "comiss", SSEPackedSingle>, TB, VEX,
2269 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2270 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2274 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2275 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2276 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2277 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2279 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2280 load, "comiss", SSEPackedSingle>, TB, VEX;
2281 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2282 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2283 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2284 "ucomiss", SSEPackedSingle>, TB;
2285 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2286 "ucomisd", SSEPackedDouble>, TB, OpSize;
2288 let Pattern = []<dag> in {
2289 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2290 "comiss", SSEPackedSingle>, TB;
2291 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2292 "comisd", SSEPackedDouble>, TB, OpSize;
2295 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2296 load, "ucomiss", SSEPackedSingle>, TB;
2297 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2298 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2300 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2301 "comiss", SSEPackedSingle>, TB;
2302 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2303 "comisd", SSEPackedDouble>, TB, OpSize;
2304 } // Defs = [EFLAGS]
2306 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2307 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2308 Operand CC, Intrinsic Int, string asm,
2309 string asm_alt, Domain d> {
2310 def rri : PIi8<0xC2, MRMSrcReg,
2311 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2312 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2313 IIC_SSE_CMPP_RR, d>;
2314 def rmi : PIi8<0xC2, MRMSrcMem,
2315 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2316 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2317 IIC_SSE_CMPP_RM, d>;
2319 // Accept explicit immediate argument form instead of comparison code.
2320 let neverHasSideEffects = 1 in {
2321 def rri_alt : PIi8<0xC2, MRMSrcReg,
2322 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2323 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2324 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2325 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2326 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2330 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2331 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2332 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2333 SSEPackedSingle>, TB, VEX_4V;
2334 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2335 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2336 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2337 SSEPackedDouble>, TB, OpSize, VEX_4V;
2338 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2339 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2340 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2341 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2342 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2343 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2344 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2345 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2346 let Constraints = "$src1 = $dst" in {
2347 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2348 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2349 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2350 SSEPackedSingle>, TB;
2351 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2352 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2353 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2354 SSEPackedDouble>, TB, OpSize;
2357 let Predicates = [HasAVX] in {
2358 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2359 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2360 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2361 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2362 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2363 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2364 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2365 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2367 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2368 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2369 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2370 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2371 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2372 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2373 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2374 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2377 let Predicates = [UseSSE1] in {
2378 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2379 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2380 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2381 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2384 let Predicates = [UseSSE2] in {
2385 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2386 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2387 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2388 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2391 //===----------------------------------------------------------------------===//
2392 // SSE 1 & 2 - Shuffle Instructions
2393 //===----------------------------------------------------------------------===//
2395 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2396 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2397 ValueType vt, string asm, PatFrag mem_frag,
2398 Domain d, bit IsConvertibleToThreeAddress = 0> {
2399 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2400 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2401 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2402 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2403 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2404 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2405 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2406 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2407 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2410 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2411 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2412 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2413 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2414 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2415 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2416 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2417 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2418 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2419 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2420 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2421 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2423 let Constraints = "$src1 = $dst" in {
2424 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2425 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2426 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2428 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2429 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2430 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2434 let Predicates = [HasAVX] in {
2435 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2436 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2437 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2438 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2439 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2441 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2442 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2443 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2444 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2445 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2448 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2449 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2450 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2451 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2452 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2454 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2455 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2456 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2457 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2458 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2461 let Predicates = [UseSSE1] in {
2462 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2463 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2464 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2465 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2466 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2469 let Predicates = [UseSSE2] in {
2470 // Generic SHUFPD patterns
2471 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2472 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2473 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2474 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2475 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2478 //===----------------------------------------------------------------------===//
2479 // SSE 1 & 2 - Unpack Instructions
2480 //===----------------------------------------------------------------------===//
2482 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2483 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2484 PatFrag mem_frag, RegisterClass RC,
2485 X86MemOperand x86memop, string asm,
2487 def rr : PI<opc, MRMSrcReg,
2488 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2490 (vt (OpNode RC:$src1, RC:$src2)))],
2492 def rm : PI<opc, MRMSrcMem,
2493 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2495 (vt (OpNode RC:$src1,
2496 (mem_frag addr:$src2))))],
2500 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2501 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2502 SSEPackedSingle>, TB, VEX_4V;
2503 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2504 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2505 SSEPackedDouble>, TB, OpSize, VEX_4V;
2506 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2507 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2508 SSEPackedSingle>, TB, VEX_4V;
2509 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2510 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2511 SSEPackedDouble>, TB, OpSize, VEX_4V;
2513 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2514 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2515 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2516 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2517 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2518 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2519 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2520 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2521 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2522 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2523 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2524 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2526 let Constraints = "$src1 = $dst" in {
2527 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2528 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2529 SSEPackedSingle>, TB;
2530 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2531 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2532 SSEPackedDouble>, TB, OpSize;
2533 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2534 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2535 SSEPackedSingle>, TB;
2536 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2537 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2538 SSEPackedDouble>, TB, OpSize;
2539 } // Constraints = "$src1 = $dst"
2541 let Predicates = [HasAVX1Only] in {
2542 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2543 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2544 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2545 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2546 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2547 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2548 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2549 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2551 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2552 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2553 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2554 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2555 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2556 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2557 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2558 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2561 let Predicates = [HasAVX] in {
2562 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2563 // problem is during lowering, where it's not possible to recognize the load
2564 // fold cause it has two uses through a bitcast. One use disappears at isel
2565 // time and the fold opportunity reappears.
2566 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2567 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2570 let Predicates = [UseSSE2] in {
2571 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2572 // problem is during lowering, where it's not possible to recognize the load
2573 // fold cause it has two uses through a bitcast. One use disappears at isel
2574 // time and the fold opportunity reappears.
2575 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2576 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2579 //===----------------------------------------------------------------------===//
2580 // SSE 1 & 2 - Extract Floating-Point Sign mask
2581 //===----------------------------------------------------------------------===//
2583 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2584 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2586 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2587 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2588 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2589 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2590 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2591 IIC_SSE_MOVMSK, d>, REX_W;
2594 let Predicates = [HasAVX] in {
2595 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2596 "movmskps", SSEPackedSingle>, TB, VEX;
2597 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2598 "movmskpd", SSEPackedDouble>, TB,
2600 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2601 "movmskps", SSEPackedSingle>, TB,
2603 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2604 "movmskpd", SSEPackedDouble>, TB,
2607 def : Pat<(i32 (X86fgetsign FR32:$src)),
2608 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2609 def : Pat<(i64 (X86fgetsign FR32:$src)),
2610 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2611 def : Pat<(i32 (X86fgetsign FR64:$src)),
2612 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2613 def : Pat<(i64 (X86fgetsign FR64:$src)),
2614 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2617 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2618 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2619 SSEPackedSingle>, TB, VEX;
2620 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2621 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2622 SSEPackedDouble>, TB,
2624 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2625 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2626 SSEPackedSingle>, TB, VEX, VEX_L;
2627 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2628 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2629 SSEPackedDouble>, TB,
2633 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2634 SSEPackedSingle>, TB;
2635 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2636 SSEPackedDouble>, TB, OpSize;
2638 def : Pat<(i32 (X86fgetsign FR32:$src)),
2639 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2640 Requires<[UseSSE1]>;
2641 def : Pat<(i64 (X86fgetsign FR32:$src)),
2642 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2643 Requires<[UseSSE1]>;
2644 def : Pat<(i32 (X86fgetsign FR64:$src)),
2645 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2646 Requires<[UseSSE2]>;
2647 def : Pat<(i64 (X86fgetsign FR64:$src)),
2648 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2649 Requires<[UseSSE2]>;
2651 //===---------------------------------------------------------------------===//
2652 // SSE2 - Packed Integer Logical Instructions
2653 //===---------------------------------------------------------------------===//
2655 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2657 /// PDI_binop_rm - Simple SSE2 binary operator.
2658 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2659 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2660 X86MemOperand x86memop,
2662 bit IsCommutable = 0,
2664 let isCommutable = IsCommutable in
2665 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2666 (ins RC:$src1, RC:$src2),
2668 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2669 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2670 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2671 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2672 (ins RC:$src1, x86memop:$src2),
2674 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2675 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2676 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2677 (bitconvert (memop_frag addr:$src2)))))],
2680 } // ExeDomain = SSEPackedInt
2682 // These are ordered here for pattern ordering requirements with the fp versions
2684 let Predicates = [HasAVX] in {
2685 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2686 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2687 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2688 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2689 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2690 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2691 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2692 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2695 let Constraints = "$src1 = $dst" in {
2696 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2697 i128mem, SSE_BIT_ITINS_P, 1>;
2698 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2699 i128mem, SSE_BIT_ITINS_P, 1>;
2700 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2701 i128mem, SSE_BIT_ITINS_P, 1>;
2702 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2703 i128mem, SSE_BIT_ITINS_P, 0>;
2704 } // Constraints = "$src1 = $dst"
2706 let Predicates = [HasAVX2] in {
2707 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2708 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
2709 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2710 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
2711 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2712 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
2713 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2714 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V, VEX_L;
2717 //===----------------------------------------------------------------------===//
2718 // SSE 1 & 2 - Logical Instructions
2719 //===----------------------------------------------------------------------===//
2721 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2723 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2724 SDNode OpNode, OpndItins itins> {
2725 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2726 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2729 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2730 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2733 let Constraints = "$src1 = $dst" in {
2734 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2735 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2738 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2739 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2744 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2745 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2747 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2749 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2752 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2753 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2756 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2758 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2760 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2761 // are all promoted to v2i64, and the patterns are covered by the int
2762 // version. This is needed in SSE only, because v2i64 isn't supported on
2763 // SSE1, but only on SSE2.
2764 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2765 !strconcat(OpcodeStr, "ps"), f128mem, [],
2766 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2767 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2769 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2770 !strconcat(OpcodeStr, "pd"), f128mem,
2771 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2772 (bc_v2i64 (v2f64 VR128:$src2))))],
2773 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2774 (memopv2i64 addr:$src2)))], 0>,
2776 let Constraints = "$src1 = $dst" in {
2777 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2778 !strconcat(OpcodeStr, "ps"), f128mem,
2779 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2780 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2781 (memopv2i64 addr:$src2)))]>, TB;
2783 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2784 !strconcat(OpcodeStr, "pd"), f128mem,
2785 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2786 (bc_v2i64 (v2f64 VR128:$src2))))],
2787 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2788 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2792 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2794 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2796 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2797 !strconcat(OpcodeStr, "ps"), f256mem,
2798 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2799 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2800 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2802 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2803 !strconcat(OpcodeStr, "pd"), f256mem,
2804 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2805 (bc_v4i64 (v4f64 VR256:$src2))))],
2806 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2807 (memopv4i64 addr:$src2)))], 0>,
2808 TB, OpSize, VEX_4V, VEX_L;
2811 // AVX 256-bit packed logical ops forms
2812 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2813 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2814 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2815 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2817 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2818 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2819 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2820 let isCommutable = 0 in
2821 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2823 //===----------------------------------------------------------------------===//
2824 // SSE 1 & 2 - Arithmetic Instructions
2825 //===----------------------------------------------------------------------===//
2827 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2830 /// In addition, we also have a special variant of the scalar form here to
2831 /// represent the associated intrinsic operation. This form is unlike the
2832 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2833 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2835 /// These three forms can each be reg+reg or reg+mem.
2838 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2840 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2843 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2844 OpNode, FR32, f32mem,
2845 itins.s, Is2Addr>, XS;
2846 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2847 OpNode, FR64, f64mem,
2848 itins.d, Is2Addr>, XD;
2851 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2854 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2855 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2857 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2858 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2862 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2865 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2866 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2868 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2869 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2873 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2876 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2877 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2878 itins.s, Is2Addr>, XS;
2879 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2880 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2881 itins.d, Is2Addr>, XD;
2884 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2887 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2888 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2889 SSEPackedSingle, itins.s, Is2Addr>,
2892 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2893 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2894 SSEPackedDouble, itins.d, Is2Addr>,
2898 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2900 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2901 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2902 SSEPackedSingle, itins.s, 0>, TB, VEX_L;
2904 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2905 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2906 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_L;
2909 // Binary Arithmetic instructions
2910 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2911 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2913 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2914 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2916 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2917 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2919 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2920 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2923 let isCommutable = 0 in {
2924 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2925 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2927 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2928 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2930 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2931 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2933 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2934 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2936 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2937 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2939 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2940 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2941 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2942 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2944 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2945 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2947 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2948 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2949 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2950 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2954 let Constraints = "$src1 = $dst" in {
2955 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2956 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2957 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2958 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2959 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2960 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2962 let isCommutable = 0 in {
2963 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2964 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2965 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2966 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2967 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2968 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2969 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2970 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2971 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2972 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2973 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2974 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2975 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2976 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2980 let isCodeGenOnly = 1 in {
2981 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
2983 defm VMAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P, 0>,
2984 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>, VEX_4V;
2985 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
2987 defm VMINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P, 0>,
2988 basic_sse12_fp_binop_p_y<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>, VEX_4V;
2989 let Constraints = "$src1 = $dst" in {
2990 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>,
2991 basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2992 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>,
2993 basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2998 /// In addition, we also have a special variant of the scalar form here to
2999 /// represent the associated intrinsic operation. This form is unlike the
3000 /// plain scalar form, in that it takes an entire vector (instead of a
3001 /// scalar) and leaves the top elements undefined.
3003 /// And, we have a special variant form for a full-vector intrinsic form.
3005 def SSE_SQRTP : OpndItins<
3006 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
3009 def SSE_SQRTS : OpndItins<
3010 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
3013 def SSE_RCPP : OpndItins<
3014 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3017 def SSE_RCPS : OpndItins<
3018 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3021 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3022 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3023 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3024 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3025 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3026 [(set FR32:$dst, (OpNode FR32:$src))]>;
3027 // For scalar unary operations, fold a load into the operation
3028 // only in OptForSize mode. It eliminates an instruction, but it also
3029 // eliminates a whole-register clobber (the load), so it introduces a
3030 // partial register update condition.
3031 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3032 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3033 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3034 Requires<[UseSSE1, OptForSize]>;
3035 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3036 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3037 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3038 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3039 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3040 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3043 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3044 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3045 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3046 !strconcat(OpcodeStr,
3047 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3048 let mayLoad = 1 in {
3049 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3050 !strconcat(OpcodeStr,
3051 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3052 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3053 (ins VR128:$src1, ssmem:$src2),
3054 !strconcat(OpcodeStr,
3055 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3059 /// sse1_fp_unop_p - SSE1 unops in packed form.
3060 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3062 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3063 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3064 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3065 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3066 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3067 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3070 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3071 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3073 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3074 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3075 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3077 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3078 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3079 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3083 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3084 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3085 Intrinsic V4F32Int, OpndItins itins> {
3086 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3087 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3088 [(set VR128:$dst, (V4F32Int VR128:$src))],
3090 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3091 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3092 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3096 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3097 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3098 Intrinsic V4F32Int, OpndItins itins> {
3099 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3100 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3101 [(set VR256:$dst, (V4F32Int VR256:$src))],
3103 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3104 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3105 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3109 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3110 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3111 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3112 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3113 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3114 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3115 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3116 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3117 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3118 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3119 Requires<[UseSSE2, OptForSize]>;
3120 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3121 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3122 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3123 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3124 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3125 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3128 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3129 let hasSideEffects = 0 in
3130 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3131 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3132 !strconcat(OpcodeStr,
3133 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3134 let mayLoad = 1 in {
3135 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3136 !strconcat(OpcodeStr,
3137 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3138 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3139 (ins VR128:$src1, sdmem:$src2),
3140 !strconcat(OpcodeStr,
3141 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3145 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3146 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3147 SDNode OpNode, OpndItins itins> {
3148 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3149 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3150 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3151 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3152 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3153 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3156 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3157 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3159 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3160 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3161 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3163 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3164 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3165 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3169 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3170 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3171 Intrinsic V2F64Int, OpndItins itins> {
3172 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3173 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3174 [(set VR128:$dst, (V2F64Int VR128:$src))],
3176 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3177 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3178 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3182 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3183 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3184 Intrinsic V2F64Int, OpndItins itins> {
3185 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3186 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3187 [(set VR256:$dst, (V2F64Int VR256:$src))],
3189 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3190 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3191 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3195 let Predicates = [HasAVX] in {
3197 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3198 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3200 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3201 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3202 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3203 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3204 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3206 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3208 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3210 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3214 // Reciprocal approximations. Note that these typically require refinement
3215 // in order to obtain suitable precision.
3216 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3217 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3218 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3219 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3221 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3224 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3225 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3226 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3227 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3229 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3233 def : Pat<(f32 (fsqrt FR32:$src)),
3234 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3235 def : Pat<(f32 (fsqrt (load addr:$src))),
3236 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3237 Requires<[HasAVX, OptForSize]>;
3238 def : Pat<(f64 (fsqrt FR64:$src)),
3239 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3240 def : Pat<(f64 (fsqrt (load addr:$src))),
3241 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3242 Requires<[HasAVX, OptForSize]>;
3244 def : Pat<(f32 (X86frsqrt FR32:$src)),
3245 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3246 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3247 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3248 Requires<[HasAVX, OptForSize]>;
3250 def : Pat<(f32 (X86frcp FR32:$src)),
3251 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3252 def : Pat<(f32 (X86frcp (load addr:$src))),
3253 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3254 Requires<[HasAVX, OptForSize]>;
3256 let Predicates = [HasAVX] in {
3257 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3258 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3259 (COPY_TO_REGCLASS VR128:$src, FR32)),
3261 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3262 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3264 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3265 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3266 (COPY_TO_REGCLASS VR128:$src, FR64)),
3268 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3269 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3271 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3272 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3273 (COPY_TO_REGCLASS VR128:$src, FR32)),
3275 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3276 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3278 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3279 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3280 (COPY_TO_REGCLASS VR128:$src, FR32)),
3282 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3283 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3287 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3289 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3290 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3291 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3293 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3294 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3296 // Reciprocal approximations. Note that these typically require refinement
3297 // in order to obtain suitable precision.
3298 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3300 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3301 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3303 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3305 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3306 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3308 // There is no f64 version of the reciprocal approximation instructions.
3310 //===----------------------------------------------------------------------===//
3311 // SSE 1 & 2 - Non-temporal stores
3312 //===----------------------------------------------------------------------===//
3314 let AddedComplexity = 400 in { // Prefer non-temporal versions
3315 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3316 (ins f128mem:$dst, VR128:$src),
3317 "movntps\t{$src, $dst|$dst, $src}",
3318 [(alignednontemporalstore (v4f32 VR128:$src),
3320 IIC_SSE_MOVNT>, VEX;
3321 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3322 (ins f128mem:$dst, VR128:$src),
3323 "movntpd\t{$src, $dst|$dst, $src}",
3324 [(alignednontemporalstore (v2f64 VR128:$src),
3326 IIC_SSE_MOVNT>, VEX;
3328 let ExeDomain = SSEPackedInt in
3329 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3330 (ins f128mem:$dst, VR128:$src),
3331 "movntdq\t{$src, $dst|$dst, $src}",
3332 [(alignednontemporalstore (v2i64 VR128:$src),
3334 IIC_SSE_MOVNT>, VEX;
3336 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3337 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3339 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3340 (ins f256mem:$dst, VR256:$src),
3341 "movntps\t{$src, $dst|$dst, $src}",
3342 [(alignednontemporalstore (v8f32 VR256:$src),
3344 IIC_SSE_MOVNT>, VEX, VEX_L;
3345 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3346 (ins f256mem:$dst, VR256:$src),
3347 "movntpd\t{$src, $dst|$dst, $src}",
3348 [(alignednontemporalstore (v4f64 VR256:$src),
3350 IIC_SSE_MOVNT>, VEX, VEX_L;
3351 let ExeDomain = SSEPackedInt in
3352 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3353 (ins f256mem:$dst, VR256:$src),
3354 "movntdq\t{$src, $dst|$dst, $src}",
3355 [(alignednontemporalstore (v4i64 VR256:$src),
3357 IIC_SSE_MOVNT>, VEX, VEX_L;
3360 let AddedComplexity = 400 in { // Prefer non-temporal versions
3361 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3362 "movntps\t{$src, $dst|$dst, $src}",
3363 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3365 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3366 "movntpd\t{$src, $dst|$dst, $src}",
3367 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3370 let ExeDomain = SSEPackedInt in
3371 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3372 "movntdq\t{$src, $dst|$dst, $src}",
3373 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3376 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3377 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3379 // There is no AVX form for instructions below this point
3380 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3381 "movnti{l}\t{$src, $dst|$dst, $src}",
3382 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3384 TB, Requires<[HasSSE2]>;
3385 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3386 "movnti{q}\t{$src, $dst|$dst, $src}",
3387 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3389 TB, Requires<[HasSSE2]>;
3392 //===----------------------------------------------------------------------===//
3393 // SSE 1 & 2 - Prefetch and memory fence
3394 //===----------------------------------------------------------------------===//
3396 // Prefetch intrinsic.
3397 let Predicates = [HasSSE1] in {
3398 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3399 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3400 IIC_SSE_PREFETCH>, TB;
3401 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3402 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3403 IIC_SSE_PREFETCH>, TB;
3404 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3405 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3406 IIC_SSE_PREFETCH>, TB;
3407 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3408 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3409 IIC_SSE_PREFETCH>, TB;
3413 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3414 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3415 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3417 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3418 // was introduced with SSE2, it's backward compatible.
3419 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3421 // Load, store, and memory fence
3422 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3423 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3424 TB, Requires<[HasSSE1]>;
3425 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3426 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3427 TB, Requires<[HasSSE2]>;
3428 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3429 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3430 TB, Requires<[HasSSE2]>;
3432 def : Pat<(X86SFence), (SFENCE)>;
3433 def : Pat<(X86LFence), (LFENCE)>;
3434 def : Pat<(X86MFence), (MFENCE)>;
3436 //===----------------------------------------------------------------------===//
3437 // SSE 1 & 2 - Load/Store XCSR register
3438 //===----------------------------------------------------------------------===//
3440 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3441 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3442 IIC_SSE_LDMXCSR>, VEX;
3443 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3444 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3445 IIC_SSE_STMXCSR>, VEX;
3447 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3448 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3450 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3451 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3454 //===---------------------------------------------------------------------===//
3455 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3456 //===---------------------------------------------------------------------===//
3458 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3460 let neverHasSideEffects = 1 in {
3461 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3462 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3464 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3465 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3468 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3469 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3471 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3472 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3476 let isCodeGenOnly = 1 in {
3477 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3478 "movdqa\t{$src, $dst|$dst, $src}", [],
3481 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3482 "movdqa\t{$src, $dst|$dst, $src}", [],
3483 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3484 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3485 "movdqu\t{$src, $dst|$dst, $src}", [],
3488 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3489 "movdqu\t{$src, $dst|$dst, $src}", [],
3490 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3493 let canFoldAsLoad = 1, mayLoad = 1 in {
3494 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3495 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3497 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3498 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3500 let Predicates = [HasAVX] in {
3501 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3502 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3504 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3505 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3510 let mayStore = 1 in {
3511 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3512 (ins i128mem:$dst, VR128:$src),
3513 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3515 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3516 (ins i256mem:$dst, VR256:$src),
3517 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3519 let Predicates = [HasAVX] in {
3520 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3521 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3523 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3524 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3529 let neverHasSideEffects = 1 in
3530 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3531 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3533 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3534 "movdqu\t{$src, $dst|$dst, $src}",
3535 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3538 let isCodeGenOnly = 1 in {
3539 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3540 "movdqa\t{$src, $dst|$dst, $src}", [],
3543 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3544 "movdqu\t{$src, $dst|$dst, $src}",
3545 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3548 let canFoldAsLoad = 1, mayLoad = 1 in {
3549 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3550 "movdqa\t{$src, $dst|$dst, $src}",
3551 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3553 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3554 "movdqu\t{$src, $dst|$dst, $src}",
3555 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3557 XS, Requires<[UseSSE2]>;
3560 let mayStore = 1 in {
3561 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3562 "movdqa\t{$src, $dst|$dst, $src}",
3563 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3565 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3566 "movdqu\t{$src, $dst|$dst, $src}",
3567 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3569 XS, Requires<[UseSSE2]>;
3572 // Intrinsic forms of MOVDQU load and store
3573 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3574 "vmovdqu\t{$src, $dst|$dst, $src}",
3575 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3577 XS, VEX, Requires<[HasAVX]>;
3579 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3580 "movdqu\t{$src, $dst|$dst, $src}",
3581 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3583 XS, Requires<[UseSSE2]>;
3585 } // ExeDomain = SSEPackedInt
3587 let Predicates = [HasAVX] in {
3588 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3589 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3592 //===---------------------------------------------------------------------===//
3593 // SSE2 - Packed Integer Arithmetic Instructions
3594 //===---------------------------------------------------------------------===//
3596 def SSE_PMADD : OpndItins<
3597 IIC_SSE_PMADD, IIC_SSE_PMADD
3600 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3602 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3603 RegisterClass RC, PatFrag memop_frag,
3604 X86MemOperand x86memop,
3606 bit IsCommutable = 0,
3608 let isCommutable = IsCommutable in
3609 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3610 (ins RC:$src1, RC:$src2),
3612 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3613 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3614 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3615 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3616 (ins RC:$src1, x86memop:$src2),
3618 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3619 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3620 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3624 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3625 string OpcodeStr, SDNode OpNode,
3626 SDNode OpNode2, RegisterClass RC,
3627 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3628 ShiftOpndItins itins,
3630 // src2 is always 128-bit
3631 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3632 (ins RC:$src1, VR128:$src2),
3634 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3635 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3636 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3638 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3639 (ins RC:$src1, i128mem:$src2),
3641 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3642 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3643 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3644 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3645 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3646 (ins RC:$src1, i32i8imm:$src2),
3648 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3649 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3650 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3653 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3654 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3655 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3656 PatFrag memop_frag, X86MemOperand x86memop,
3658 bit IsCommutable = 0, bit Is2Addr = 1> {
3659 let isCommutable = IsCommutable in
3660 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3661 (ins RC:$src1, RC:$src2),
3663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3664 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3665 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3666 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3667 (ins RC:$src1, x86memop:$src2),
3669 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3670 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3671 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3672 (bitconvert (memop_frag addr:$src2)))))]>;
3674 } // ExeDomain = SSEPackedInt
3676 // 128-bit Integer Arithmetic
3678 let Predicates = [HasAVX] in {
3679 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3680 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3682 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3683 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3684 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3685 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3686 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3687 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3688 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3689 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3690 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3691 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3692 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3693 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3694 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3695 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3696 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3697 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3698 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3699 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3703 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3704 VR128, memopv2i64, i128mem,
3705 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3706 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3707 VR128, memopv2i64, i128mem,
3708 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3709 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3710 VR128, memopv2i64, i128mem,
3711 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3712 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3713 VR128, memopv2i64, i128mem,
3714 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3715 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3716 VR128, memopv2i64, i128mem,
3717 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3718 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3719 VR128, memopv2i64, i128mem,
3720 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3721 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3722 VR128, memopv2i64, i128mem,
3723 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3724 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3725 VR128, memopv2i64, i128mem,
3726 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3727 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3728 VR128, memopv2i64, i128mem,
3729 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3730 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3731 VR128, memopv2i64, i128mem,
3732 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3733 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3734 VR128, memopv2i64, i128mem,
3735 SSE_PMADD, 1, 0>, VEX_4V;
3736 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3737 VR128, memopv2i64, i128mem,
3738 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3739 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3740 VR128, memopv2i64, i128mem,
3741 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3742 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3743 VR128, memopv2i64, i128mem,
3744 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3745 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3746 VR128, memopv2i64, i128mem,
3747 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3748 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3749 VR128, memopv2i64, i128mem,
3750 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3751 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3752 VR128, memopv2i64, i128mem,
3753 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3754 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3755 VR128, memopv2i64, i128mem,
3756 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3759 let Predicates = [HasAVX2] in {
3760 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3761 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3762 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3763 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3764 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3765 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3766 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3767 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3768 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3769 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3770 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3771 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3772 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3773 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3774 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3775 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3776 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3777 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3778 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3779 VR256, memopv4i64, i256mem,
3780 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3783 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3784 VR256, memopv4i64, i256mem,
3785 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3786 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3787 VR256, memopv4i64, i256mem,
3788 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3789 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3790 VR256, memopv4i64, i256mem,
3791 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3792 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3793 VR256, memopv4i64, i256mem,
3794 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3795 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3796 VR256, memopv4i64, i256mem,
3797 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3798 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3799 VR256, memopv4i64, i256mem,
3800 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3801 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3802 VR256, memopv4i64, i256mem,
3803 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3804 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3805 VR256, memopv4i64, i256mem,
3806 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3807 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3808 VR256, memopv4i64, i256mem,
3809 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3810 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3811 VR256, memopv4i64, i256mem,
3812 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3813 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3814 VR256, memopv4i64, i256mem,
3815 SSE_PMADD, 1, 0>, VEX_4V, VEX_L;
3816 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3817 VR256, memopv4i64, i256mem,
3818 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3819 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3820 VR256, memopv4i64, i256mem,
3821 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3822 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3823 VR256, memopv4i64, i256mem,
3824 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3825 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3826 VR256, memopv4i64, i256mem,
3827 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3828 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3829 VR256, memopv4i64, i256mem,
3830 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3831 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3832 VR256, memopv4i64, i256mem,
3833 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3834 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3835 VR256, memopv4i64, i256mem,
3836 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3839 let Constraints = "$src1 = $dst" in {
3840 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3841 i128mem, SSE_INTALU_ITINS_P, 1>;
3842 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3843 i128mem, SSE_INTALU_ITINS_P, 1>;
3844 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3845 i128mem, SSE_INTALU_ITINS_P, 1>;
3846 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3847 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3848 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3849 i128mem, SSE_INTMUL_ITINS_P, 1>;
3850 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3851 i128mem, SSE_INTALU_ITINS_P>;
3852 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3853 i128mem, SSE_INTALU_ITINS_P>;
3854 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3855 i128mem, SSE_INTALU_ITINS_P>;
3856 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3857 i128mem, SSE_INTALUQ_ITINS_P>;
3858 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3859 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3862 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3863 VR128, memopv2i64, i128mem,
3864 SSE_INTALU_ITINS_P>;
3865 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3866 VR128, memopv2i64, i128mem,
3867 SSE_INTALU_ITINS_P>;
3868 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3869 VR128, memopv2i64, i128mem,
3870 SSE_INTALU_ITINS_P>;
3871 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3872 VR128, memopv2i64, i128mem,
3873 SSE_INTALU_ITINS_P>;
3874 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3875 VR128, memopv2i64, i128mem,
3876 SSE_INTALU_ITINS_P, 1>;
3877 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3878 VR128, memopv2i64, i128mem,
3879 SSE_INTALU_ITINS_P, 1>;
3880 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3881 VR128, memopv2i64, i128mem,
3882 SSE_INTALU_ITINS_P, 1>;
3883 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3884 VR128, memopv2i64, i128mem,
3885 SSE_INTALU_ITINS_P, 1>;
3886 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3887 VR128, memopv2i64, i128mem,
3888 SSE_INTMUL_ITINS_P, 1>;
3889 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3890 VR128, memopv2i64, i128mem,
3891 SSE_INTMUL_ITINS_P, 1>;
3892 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3893 VR128, memopv2i64, i128mem,
3895 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3896 VR128, memopv2i64, i128mem,
3897 SSE_INTALU_ITINS_P, 1>;
3898 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3899 VR128, memopv2i64, i128mem,
3900 SSE_INTALU_ITINS_P, 1>;
3901 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3902 VR128, memopv2i64, i128mem,
3903 SSE_INTALU_ITINS_P, 1>;
3904 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3905 VR128, memopv2i64, i128mem,
3906 SSE_INTALU_ITINS_P, 1>;
3907 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3908 VR128, memopv2i64, i128mem,
3909 SSE_INTALU_ITINS_P, 1>;
3910 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3911 VR128, memopv2i64, i128mem,
3912 SSE_INTALU_ITINS_P, 1>;
3913 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3914 VR128, memopv2i64, i128mem,
3915 SSE_INTALU_ITINS_P, 1>;
3917 } // Constraints = "$src1 = $dst"
3919 //===---------------------------------------------------------------------===//
3920 // SSE2 - Packed Integer Logical Instructions
3921 //===---------------------------------------------------------------------===//
3923 let Predicates = [HasAVX] in {
3924 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3925 VR128, v8i16, v8i16, bc_v8i16,
3926 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3927 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3928 VR128, v4i32, v4i32, bc_v4i32,
3929 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3930 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3931 VR128, v2i64, v2i64, bc_v2i64,
3932 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3934 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3935 VR128, v8i16, v8i16, bc_v8i16,
3936 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3937 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3938 VR128, v4i32, v4i32, bc_v4i32,
3939 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3940 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3941 VR128, v2i64, v2i64, bc_v2i64,
3942 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3944 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3945 VR128, v8i16, v8i16, bc_v8i16,
3946 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3947 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3948 VR128, v4i32, v4i32, bc_v4i32,
3949 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3951 let ExeDomain = SSEPackedInt in {
3952 // 128-bit logical shifts.
3953 def VPSLLDQri : PDIi8<0x73, MRM7r,
3954 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3955 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3957 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3959 def VPSRLDQri : PDIi8<0x73, MRM3r,
3960 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3961 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3963 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3965 // PSRADQri doesn't exist in SSE[1-3].
3967 } // Predicates = [HasAVX]
3969 let Predicates = [HasAVX2] in {
3970 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3971 VR256, v16i16, v8i16, bc_v8i16,
3972 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3973 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3974 VR256, v8i32, v4i32, bc_v4i32,
3975 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3976 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3977 VR256, v4i64, v2i64, bc_v2i64,
3978 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3980 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3981 VR256, v16i16, v8i16, bc_v8i16,
3982 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3983 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3984 VR256, v8i32, v4i32, bc_v4i32,
3985 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3986 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3987 VR256, v4i64, v2i64, bc_v2i64,
3988 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3990 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3991 VR256, v16i16, v8i16, bc_v8i16,
3992 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3993 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3994 VR256, v8i32, v4i32, bc_v4i32,
3995 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3997 let ExeDomain = SSEPackedInt in {
3998 // 256-bit logical shifts.
3999 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4000 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4001 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4003 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4005 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4006 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4007 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4009 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4011 // PSRADQYri doesn't exist in SSE[1-3].
4013 } // Predicates = [HasAVX2]
4015 let Constraints = "$src1 = $dst" in {
4016 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4017 VR128, v8i16, v8i16, bc_v8i16,
4018 SSE_INTSHIFT_ITINS_P>;
4019 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4020 VR128, v4i32, v4i32, bc_v4i32,
4021 SSE_INTSHIFT_ITINS_P>;
4022 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4023 VR128, v2i64, v2i64, bc_v2i64,
4024 SSE_INTSHIFT_ITINS_P>;
4026 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4027 VR128, v8i16, v8i16, bc_v8i16,
4028 SSE_INTSHIFT_ITINS_P>;
4029 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4030 VR128, v4i32, v4i32, bc_v4i32,
4031 SSE_INTSHIFT_ITINS_P>;
4032 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4033 VR128, v2i64, v2i64, bc_v2i64,
4034 SSE_INTSHIFT_ITINS_P>;
4036 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4037 VR128, v8i16, v8i16, bc_v8i16,
4038 SSE_INTSHIFT_ITINS_P>;
4039 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4040 VR128, v4i32, v4i32, bc_v4i32,
4041 SSE_INTSHIFT_ITINS_P>;
4043 let ExeDomain = SSEPackedInt in {
4044 // 128-bit logical shifts.
4045 def PSLLDQri : PDIi8<0x73, MRM7r,
4046 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4047 "pslldq\t{$src2, $dst|$dst, $src2}",
4049 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4050 def PSRLDQri : PDIi8<0x73, MRM3r,
4051 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4052 "psrldq\t{$src2, $dst|$dst, $src2}",
4054 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4055 // PSRADQri doesn't exist in SSE[1-3].
4057 } // Constraints = "$src1 = $dst"
4059 let Predicates = [HasAVX] in {
4060 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4061 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4062 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4063 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4064 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4065 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4067 // Shift up / down and insert zero's.
4068 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4069 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4070 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4071 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4074 let Predicates = [HasAVX2] in {
4075 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4076 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4077 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4078 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4081 let Predicates = [UseSSE2] in {
4082 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4083 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4084 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4085 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4086 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4087 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4089 // Shift up / down and insert zero's.
4090 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4091 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4092 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4093 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4096 //===---------------------------------------------------------------------===//
4097 // SSE2 - Packed Integer Comparison Instructions
4098 //===---------------------------------------------------------------------===//
4100 let Predicates = [HasAVX] in {
4101 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4102 VR128, memopv2i64, i128mem,
4103 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4104 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4105 VR128, memopv2i64, i128mem,
4106 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4107 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4108 VR128, memopv2i64, i128mem,
4109 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4110 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4111 VR128, memopv2i64, i128mem,
4112 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4113 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4114 VR128, memopv2i64, i128mem,
4115 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4116 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4117 VR128, memopv2i64, i128mem,
4118 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4121 let Predicates = [HasAVX2] in {
4122 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4123 VR256, memopv4i64, i256mem,
4124 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4125 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4126 VR256, memopv4i64, i256mem,
4127 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4128 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4129 VR256, memopv4i64, i256mem,
4130 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4131 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4132 VR256, memopv4i64, i256mem,
4133 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4134 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4135 VR256, memopv4i64, i256mem,
4136 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4137 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4138 VR256, memopv4i64, i256mem,
4139 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4142 let Constraints = "$src1 = $dst" in {
4143 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4144 VR128, memopv2i64, i128mem,
4145 SSE_INTALU_ITINS_P, 1>;
4146 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4147 VR128, memopv2i64, i128mem,
4148 SSE_INTALU_ITINS_P, 1>;
4149 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4150 VR128, memopv2i64, i128mem,
4151 SSE_INTALU_ITINS_P, 1>;
4152 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4153 VR128, memopv2i64, i128mem,
4154 SSE_INTALU_ITINS_P>;
4155 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4156 VR128, memopv2i64, i128mem,
4157 SSE_INTALU_ITINS_P>;
4158 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4159 VR128, memopv2i64, i128mem,
4160 SSE_INTALU_ITINS_P>;
4161 } // Constraints = "$src1 = $dst"
4163 //===---------------------------------------------------------------------===//
4164 // SSE2 - Packed Integer Pack Instructions
4165 //===---------------------------------------------------------------------===//
4167 let Predicates = [HasAVX] in {
4168 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4169 VR128, memopv2i64, i128mem,
4170 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4171 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4172 VR128, memopv2i64, i128mem,
4173 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4174 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4175 VR128, memopv2i64, i128mem,
4176 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4179 let Predicates = [HasAVX2] in {
4180 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4181 VR256, memopv4i64, i256mem,
4182 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4183 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4184 VR256, memopv4i64, i256mem,
4185 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4186 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4187 VR256, memopv4i64, i256mem,
4188 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4191 let Constraints = "$src1 = $dst" in {
4192 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4193 VR128, memopv2i64, i128mem,
4194 SSE_INTALU_ITINS_P>;
4195 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4196 VR128, memopv2i64, i128mem,
4197 SSE_INTALU_ITINS_P>;
4198 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4199 VR128, memopv2i64, i128mem,
4200 SSE_INTALU_ITINS_P>;
4201 } // Constraints = "$src1 = $dst"
4203 //===---------------------------------------------------------------------===//
4204 // SSE2 - Packed Integer Shuffle Instructions
4205 //===---------------------------------------------------------------------===//
4207 let ExeDomain = SSEPackedInt in {
4208 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4209 def ri : Ii8<0x70, MRMSrcReg,
4210 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4211 !strconcat(OpcodeStr,
4212 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4213 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4215 def mi : Ii8<0x70, MRMSrcMem,
4216 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4217 !strconcat(OpcodeStr,
4218 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4220 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4225 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4226 def Yri : Ii8<0x70, MRMSrcReg,
4227 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4228 !strconcat(OpcodeStr,
4229 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4230 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4231 def Ymi : Ii8<0x70, MRMSrcMem,
4232 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4233 !strconcat(OpcodeStr,
4234 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4236 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4237 (i8 imm:$src2))))]>;
4239 } // ExeDomain = SSEPackedInt
4241 let Predicates = [HasAVX] in {
4242 let AddedComplexity = 5 in
4243 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4245 // SSE2 with ImmT == Imm8 and XS prefix.
4246 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4248 // SSE2 with ImmT == Imm8 and XD prefix.
4249 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4251 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4252 (VPSHUFDmi addr:$src1, imm:$imm)>;
4253 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4254 (VPSHUFDri VR128:$src1, imm:$imm)>;
4257 let Predicates = [HasAVX2] in {
4258 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>,
4259 TB, OpSize, VEX,VEX_L;
4260 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>,
4262 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>,
4266 let Predicates = [UseSSE2] in {
4267 let AddedComplexity = 5 in
4268 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4270 // SSE2 with ImmT == Imm8 and XS prefix.
4271 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4273 // SSE2 with ImmT == Imm8 and XD prefix.
4274 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4276 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4277 (PSHUFDmi addr:$src1, imm:$imm)>;
4278 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4279 (PSHUFDri VR128:$src1, imm:$imm)>;
4282 //===---------------------------------------------------------------------===//
4283 // SSE2 - Packed Integer Unpack Instructions
4284 //===---------------------------------------------------------------------===//
4286 let ExeDomain = SSEPackedInt in {
4287 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4288 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4289 def rr : PDI<opc, MRMSrcReg,
4290 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4292 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4293 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4294 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4296 def rm : PDI<opc, MRMSrcMem,
4297 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4299 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4300 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4301 [(set VR128:$dst, (OpNode VR128:$src1,
4302 (bc_frag (memopv2i64
4307 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4308 SDNode OpNode, PatFrag bc_frag> {
4309 def Yrr : PDI<opc, MRMSrcReg,
4310 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4311 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4312 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4313 def Yrm : PDI<opc, MRMSrcMem,
4314 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4315 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4316 [(set VR256:$dst, (OpNode VR256:$src1,
4317 (bc_frag (memopv4i64 addr:$src2))))]>;
4320 let Predicates = [HasAVX] in {
4321 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4322 bc_v16i8, 0>, VEX_4V;
4323 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4324 bc_v8i16, 0>, VEX_4V;
4325 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4326 bc_v4i32, 0>, VEX_4V;
4327 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4328 bc_v2i64, 0>, VEX_4V;
4330 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4331 bc_v16i8, 0>, VEX_4V;
4332 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4333 bc_v8i16, 0>, VEX_4V;
4334 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4335 bc_v4i32, 0>, VEX_4V;
4336 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4337 bc_v2i64, 0>, VEX_4V;
4340 let Predicates = [HasAVX2] in {
4341 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4342 bc_v32i8>, VEX_4V, VEX_L;
4343 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4344 bc_v16i16>, VEX_4V, VEX_L;
4345 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4346 bc_v8i32>, VEX_4V, VEX_L;
4347 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4348 bc_v4i64>, VEX_4V, VEX_L;
4350 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4351 bc_v32i8>, VEX_4V, VEX_L;
4352 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4353 bc_v16i16>, VEX_4V, VEX_L;
4354 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4355 bc_v8i32>, VEX_4V, VEX_L;
4356 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4357 bc_v4i64>, VEX_4V, VEX_L;
4360 let Constraints = "$src1 = $dst" in {
4361 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4363 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4365 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4367 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4370 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4372 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4374 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4376 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4379 } // ExeDomain = SSEPackedInt
4381 //===---------------------------------------------------------------------===//
4382 // SSE2 - Packed Integer Extract and Insert
4383 //===---------------------------------------------------------------------===//
4385 let ExeDomain = SSEPackedInt in {
4386 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4387 def rri : Ii8<0xC4, MRMSrcReg,
4388 (outs VR128:$dst), (ins VR128:$src1,
4389 GR32:$src2, i32i8imm:$src3),
4391 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4392 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4394 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4395 def rmi : Ii8<0xC4, MRMSrcMem,
4396 (outs VR128:$dst), (ins VR128:$src1,
4397 i16mem:$src2, i32i8imm:$src3),
4399 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4400 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4402 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4403 imm:$src3))], IIC_SSE_PINSRW>;
4407 let Predicates = [HasAVX] in
4408 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4409 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4410 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4411 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4412 imm:$src2))]>, TB, OpSize, VEX;
4413 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4414 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4415 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4416 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4417 imm:$src2))], IIC_SSE_PEXTRW>;
4420 let Predicates = [HasAVX] in {
4421 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4422 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4423 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4424 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4425 []>, TB, OpSize, VEX_4V;
4428 let Constraints = "$src1 = $dst" in
4429 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4431 } // ExeDomain = SSEPackedInt
4433 //===---------------------------------------------------------------------===//
4434 // SSE2 - Packed Mask Creation
4435 //===---------------------------------------------------------------------===//
4437 let ExeDomain = SSEPackedInt in {
4439 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4440 "pmovmskb\t{$src, $dst|$dst, $src}",
4441 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4442 IIC_SSE_MOVMSK>, VEX;
4443 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4444 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4446 let Predicates = [HasAVX2] in {
4447 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4448 "pmovmskb\t{$src, $dst|$dst, $src}",
4449 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4450 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4451 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4454 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4455 "pmovmskb\t{$src, $dst|$dst, $src}",
4456 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4459 } // ExeDomain = SSEPackedInt
4461 //===---------------------------------------------------------------------===//
4462 // SSE2 - Conditional Store
4463 //===---------------------------------------------------------------------===//
4465 let ExeDomain = SSEPackedInt in {
4468 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4469 (ins VR128:$src, VR128:$mask),
4470 "maskmovdqu\t{$mask, $src|$src, $mask}",
4471 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4472 IIC_SSE_MASKMOV>, VEX;
4474 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4475 (ins VR128:$src, VR128:$mask),
4476 "maskmovdqu\t{$mask, $src|$src, $mask}",
4477 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4478 IIC_SSE_MASKMOV>, VEX;
4481 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4482 "maskmovdqu\t{$mask, $src|$src, $mask}",
4483 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4486 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4487 "maskmovdqu\t{$mask, $src|$src, $mask}",
4488 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4491 } // ExeDomain = SSEPackedInt
4493 //===---------------------------------------------------------------------===//
4494 // SSE2 - Move Doubleword
4495 //===---------------------------------------------------------------------===//
4497 //===---------------------------------------------------------------------===//
4498 // Move Int Doubleword to Packed Double Int
4500 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4501 "movd\t{$src, $dst|$dst, $src}",
4503 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4505 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4506 "movd\t{$src, $dst|$dst, $src}",
4508 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4511 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4512 "mov{d|q}\t{$src, $dst|$dst, $src}",
4514 (v2i64 (scalar_to_vector GR64:$src)))],
4515 IIC_SSE_MOVDQ>, VEX;
4516 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4517 "mov{d|q}\t{$src, $dst|$dst, $src}",
4518 [(set FR64:$dst, (bitconvert GR64:$src))],
4519 IIC_SSE_MOVDQ>, VEX;
4521 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4522 "movd\t{$src, $dst|$dst, $src}",
4524 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4525 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4526 "movd\t{$src, $dst|$dst, $src}",
4528 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4530 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4531 "mov{d|q}\t{$src, $dst|$dst, $src}",
4533 (v2i64 (scalar_to_vector GR64:$src)))],
4535 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4536 "mov{d|q}\t{$src, $dst|$dst, $src}",
4537 [(set FR64:$dst, (bitconvert GR64:$src))],
4540 //===---------------------------------------------------------------------===//
4541 // Move Int Doubleword to Single Scalar
4543 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4544 "movd\t{$src, $dst|$dst, $src}",
4545 [(set FR32:$dst, (bitconvert GR32:$src))],
4546 IIC_SSE_MOVDQ>, VEX;
4548 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4549 "movd\t{$src, $dst|$dst, $src}",
4550 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4553 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4554 "movd\t{$src, $dst|$dst, $src}",
4555 [(set FR32:$dst, (bitconvert GR32:$src))],
4558 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4559 "movd\t{$src, $dst|$dst, $src}",
4560 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4563 //===---------------------------------------------------------------------===//
4564 // Move Packed Doubleword Int to Packed Double Int
4566 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4567 "movd\t{$src, $dst|$dst, $src}",
4568 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4569 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4570 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4571 (ins i32mem:$dst, VR128:$src),
4572 "movd\t{$src, $dst|$dst, $src}",
4573 [(store (i32 (vector_extract (v4i32 VR128:$src),
4574 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4576 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4577 "movd\t{$src, $dst|$dst, $src}",
4578 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4579 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4580 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4581 "movd\t{$src, $dst|$dst, $src}",
4582 [(store (i32 (vector_extract (v4i32 VR128:$src),
4583 (iPTR 0))), addr:$dst)],
4586 //===---------------------------------------------------------------------===//
4587 // Move Packed Doubleword Int first element to Doubleword Int
4589 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4590 "vmov{d|q}\t{$src, $dst|$dst, $src}",
4591 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4594 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4596 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4597 "mov{d|q}\t{$src, $dst|$dst, $src}",
4598 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4602 //===---------------------------------------------------------------------===//
4603 // Bitcast FR64 <-> GR64
4605 let Predicates = [HasAVX] in
4606 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4607 "vmovq\t{$src, $dst|$dst, $src}",
4608 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4610 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4611 "mov{d|q}\t{$src, $dst|$dst, $src}",
4612 [(set GR64:$dst, (bitconvert FR64:$src))],
4613 IIC_SSE_MOVDQ>, VEX;
4614 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4615 "movq\t{$src, $dst|$dst, $src}",
4616 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4617 IIC_SSE_MOVDQ>, VEX;
4619 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4620 "movq\t{$src, $dst|$dst, $src}",
4621 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4623 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4624 "mov{d|q}\t{$src, $dst|$dst, $src}",
4625 [(set GR64:$dst, (bitconvert FR64:$src))],
4627 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4628 "movq\t{$src, $dst|$dst, $src}",
4629 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4632 //===---------------------------------------------------------------------===//
4633 // Move Scalar Single to Double Int
4635 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4636 "movd\t{$src, $dst|$dst, $src}",
4637 [(set GR32:$dst, (bitconvert FR32:$src))],
4638 IIC_SSE_MOVD_ToGP>, VEX;
4639 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4640 "movd\t{$src, $dst|$dst, $src}",
4641 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4642 IIC_SSE_MOVDQ>, VEX;
4643 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4644 "movd\t{$src, $dst|$dst, $src}",
4645 [(set GR32:$dst, (bitconvert FR32:$src))],
4647 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4648 "movd\t{$src, $dst|$dst, $src}",
4649 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4652 //===---------------------------------------------------------------------===//
4653 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4655 let AddedComplexity = 15 in {
4656 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4657 "movd\t{$src, $dst|$dst, $src}",
4658 [(set VR128:$dst, (v4i32 (X86vzmovl
4659 (v4i32 (scalar_to_vector GR32:$src)))))],
4660 IIC_SSE_MOVDQ>, VEX;
4661 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4662 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4663 [(set VR128:$dst, (v2i64 (X86vzmovl
4664 (v2i64 (scalar_to_vector GR64:$src)))))],
4668 let AddedComplexity = 15 in {
4669 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4670 "movd\t{$src, $dst|$dst, $src}",
4671 [(set VR128:$dst, (v4i32 (X86vzmovl
4672 (v4i32 (scalar_to_vector GR32:$src)))))],
4674 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4675 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4676 [(set VR128:$dst, (v2i64 (X86vzmovl
4677 (v2i64 (scalar_to_vector GR64:$src)))))],
4681 let AddedComplexity = 20 in {
4682 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4683 "movd\t{$src, $dst|$dst, $src}",
4685 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4686 (loadi32 addr:$src))))))],
4687 IIC_SSE_MOVDQ>, VEX;
4688 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4689 "movd\t{$src, $dst|$dst, $src}",
4691 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4692 (loadi32 addr:$src))))))],
4696 let Predicates = [HasAVX] in {
4697 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4698 let AddedComplexity = 20 in {
4699 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4700 (VMOVZDI2PDIrm addr:$src)>;
4701 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4702 (VMOVZDI2PDIrm addr:$src)>;
4704 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4705 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4706 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4707 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4708 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4709 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4710 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4713 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4714 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4715 (MOVZDI2PDIrm addr:$src)>;
4716 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4717 (MOVZDI2PDIrm addr:$src)>;
4720 // These are the correct encodings of the instructions so that we know how to
4721 // read correct assembly, even though we continue to emit the wrong ones for
4722 // compatibility with Darwin's buggy assembler.
4723 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4724 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4725 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4726 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4727 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4728 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4729 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4730 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4731 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4732 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4733 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4734 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4736 //===---------------------------------------------------------------------===//
4737 // SSE2 - Move Quadword
4738 //===---------------------------------------------------------------------===//
4740 //===---------------------------------------------------------------------===//
4741 // Move Quadword Int to Packed Quadword Int
4743 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4744 "vmovq\t{$src, $dst|$dst, $src}",
4746 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4747 VEX, Requires<[HasAVX]>;
4748 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4749 "movq\t{$src, $dst|$dst, $src}",
4751 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4753 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4755 //===---------------------------------------------------------------------===//
4756 // Move Packed Quadword Int to Quadword Int
4758 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4759 "movq\t{$src, $dst|$dst, $src}",
4760 [(store (i64 (vector_extract (v2i64 VR128:$src),
4761 (iPTR 0))), addr:$dst)],
4762 IIC_SSE_MOVDQ>, VEX;
4763 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4764 "movq\t{$src, $dst|$dst, $src}",
4765 [(store (i64 (vector_extract (v2i64 VR128:$src),
4766 (iPTR 0))), addr:$dst)],
4769 //===---------------------------------------------------------------------===//
4770 // Store / copy lower 64-bits of a XMM register.
4772 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4773 "movq\t{$src, $dst|$dst, $src}",
4774 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4775 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4776 "movq\t{$src, $dst|$dst, $src}",
4777 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4780 let AddedComplexity = 20 in
4781 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4782 "vmovq\t{$src, $dst|$dst, $src}",
4784 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4785 (loadi64 addr:$src))))))],
4787 XS, VEX, Requires<[HasAVX]>;
4789 let AddedComplexity = 20 in
4790 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4791 "movq\t{$src, $dst|$dst, $src}",
4793 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4794 (loadi64 addr:$src))))))],
4796 XS, Requires<[UseSSE2]>;
4798 let Predicates = [HasAVX], AddedComplexity = 20 in {
4799 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4800 (VMOVZQI2PQIrm addr:$src)>;
4801 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4802 (VMOVZQI2PQIrm addr:$src)>;
4803 def : Pat<(v2i64 (X86vzload addr:$src)),
4804 (VMOVZQI2PQIrm addr:$src)>;
4807 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4808 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4809 (MOVZQI2PQIrm addr:$src)>;
4810 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4811 (MOVZQI2PQIrm addr:$src)>;
4812 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4815 let Predicates = [HasAVX] in {
4816 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4817 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4818 def : Pat<(v4i64 (X86vzload addr:$src)),
4819 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4822 //===---------------------------------------------------------------------===//
4823 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4824 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4826 let AddedComplexity = 15 in
4827 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4828 "vmovq\t{$src, $dst|$dst, $src}",
4829 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4831 XS, VEX, Requires<[HasAVX]>;
4832 let AddedComplexity = 15 in
4833 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4834 "movq\t{$src, $dst|$dst, $src}",
4835 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4837 XS, Requires<[UseSSE2]>;
4839 let AddedComplexity = 20 in
4840 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4841 "vmovq\t{$src, $dst|$dst, $src}",
4842 [(set VR128:$dst, (v2i64 (X86vzmovl
4843 (loadv2i64 addr:$src))))],
4845 XS, VEX, Requires<[HasAVX]>;
4846 let AddedComplexity = 20 in {
4847 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4848 "movq\t{$src, $dst|$dst, $src}",
4849 [(set VR128:$dst, (v2i64 (X86vzmovl
4850 (loadv2i64 addr:$src))))],
4852 XS, Requires<[UseSSE2]>;
4855 let AddedComplexity = 20 in {
4856 let Predicates = [HasAVX] in {
4857 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4858 (VMOVZPQILo2PQIrm addr:$src)>;
4859 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4860 (VMOVZPQILo2PQIrr VR128:$src)>;
4862 let Predicates = [UseSSE2] in {
4863 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4864 (MOVZPQILo2PQIrm addr:$src)>;
4865 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4866 (MOVZPQILo2PQIrr VR128:$src)>;
4870 // Instructions to match in the assembler
4871 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4872 "movq\t{$src, $dst|$dst, $src}", [],
4873 IIC_SSE_MOVDQ>, VEX, VEX_W;
4874 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4875 "movq\t{$src, $dst|$dst, $src}", [],
4876 IIC_SSE_MOVDQ>, VEX, VEX_W;
4877 // Recognize "movd" with GR64 destination, but encode as a "movq"
4878 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4879 "movd\t{$src, $dst|$dst, $src}", [],
4880 IIC_SSE_MOVDQ>, VEX, VEX_W;
4882 // Instructions for the disassembler
4883 // xr = XMM register
4886 let Predicates = [HasAVX] in
4887 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4888 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4889 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4890 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4892 //===---------------------------------------------------------------------===//
4893 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4894 //===---------------------------------------------------------------------===//
4895 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4896 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4897 X86MemOperand x86memop> {
4898 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4899 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4900 [(set RC:$dst, (vt (OpNode RC:$src)))],
4902 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4903 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4904 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4908 let Predicates = [HasAVX] in {
4909 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4910 v4f32, VR128, memopv4f32, f128mem>, VEX;
4911 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4912 v4f32, VR128, memopv4f32, f128mem>, VEX;
4913 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4914 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4915 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4916 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4918 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4919 memopv4f32, f128mem>;
4920 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4921 memopv4f32, f128mem>;
4923 let Predicates = [HasAVX] in {
4924 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4925 (VMOVSHDUPrr VR128:$src)>;
4926 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4927 (VMOVSHDUPrm addr:$src)>;
4928 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4929 (VMOVSLDUPrr VR128:$src)>;
4930 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4931 (VMOVSLDUPrm addr:$src)>;
4932 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4933 (VMOVSHDUPYrr VR256:$src)>;
4934 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4935 (VMOVSHDUPYrm addr:$src)>;
4936 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4937 (VMOVSLDUPYrr VR256:$src)>;
4938 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4939 (VMOVSLDUPYrm addr:$src)>;
4942 let Predicates = [UseSSE3] in {
4943 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4944 (MOVSHDUPrr VR128:$src)>;
4945 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4946 (MOVSHDUPrm addr:$src)>;
4947 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4948 (MOVSLDUPrr VR128:$src)>;
4949 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4950 (MOVSLDUPrm addr:$src)>;
4953 //===---------------------------------------------------------------------===//
4954 // SSE3 - Replicate Double FP - MOVDDUP
4955 //===---------------------------------------------------------------------===//
4957 multiclass sse3_replicate_dfp<string OpcodeStr> {
4958 let neverHasSideEffects = 1 in
4959 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4960 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4961 [], IIC_SSE_MOV_LH>;
4962 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4963 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4966 (scalar_to_vector (loadf64 addr:$src)))))],
4970 // FIXME: Merge with above classe when there're patterns for the ymm version
4971 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4972 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4973 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4974 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4975 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4976 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4979 (scalar_to_vector (loadf64 addr:$src)))))]>;
4982 let Predicates = [HasAVX] in {
4983 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4984 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4987 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4989 let Predicates = [HasAVX] in {
4990 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4991 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4992 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4993 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4994 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4995 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4996 def : Pat<(X86Movddup (bc_v2f64
4997 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4998 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5001 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
5002 (VMOVDDUPYrm addr:$src)>;
5003 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
5004 (VMOVDDUPYrm addr:$src)>;
5005 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5006 (VMOVDDUPYrm addr:$src)>;
5007 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5008 (VMOVDDUPYrr VR256:$src)>;
5011 let Predicates = [UseSSE3] in {
5012 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5013 (MOVDDUPrm addr:$src)>;
5014 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5015 (MOVDDUPrm addr:$src)>;
5016 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5017 (MOVDDUPrm addr:$src)>;
5018 def : Pat<(X86Movddup (bc_v2f64
5019 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5020 (MOVDDUPrm addr:$src)>;
5023 //===---------------------------------------------------------------------===//
5024 // SSE3 - Move Unaligned Integer
5025 //===---------------------------------------------------------------------===//
5027 let Predicates = [HasAVX] in {
5028 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5029 "vlddqu\t{$src, $dst|$dst, $src}",
5030 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5031 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5032 "vlddqu\t{$src, $dst|$dst, $src}",
5033 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5036 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5037 "lddqu\t{$src, $dst|$dst, $src}",
5038 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5041 //===---------------------------------------------------------------------===//
5042 // SSE3 - Arithmetic
5043 //===---------------------------------------------------------------------===//
5045 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5046 X86MemOperand x86memop, OpndItins itins,
5048 def rr : I<0xD0, MRMSrcReg,
5049 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5051 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5052 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5053 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5054 def rm : I<0xD0, MRMSrcMem,
5055 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5057 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5058 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5059 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5062 let Predicates = [HasAVX] in {
5063 let ExeDomain = SSEPackedSingle in {
5064 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5065 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5066 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5067 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
5069 let ExeDomain = SSEPackedDouble in {
5070 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5071 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5072 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5073 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
5076 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5077 let ExeDomain = SSEPackedSingle in
5078 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5079 f128mem, SSE_ALU_F32P>, TB, XD;
5080 let ExeDomain = SSEPackedDouble in
5081 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5082 f128mem, SSE_ALU_F64P>, TB, OpSize;
5085 //===---------------------------------------------------------------------===//
5086 // SSE3 Instructions
5087 //===---------------------------------------------------------------------===//
5090 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5091 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5092 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5094 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5095 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5096 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5098 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5101 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5102 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5103 IIC_SSE_HADDSUB_RM>;
5105 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5106 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5107 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5109 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5110 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5111 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5113 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5115 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5116 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5117 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5118 IIC_SSE_HADDSUB_RM>;
5121 let Predicates = [HasAVX] in {
5122 let ExeDomain = SSEPackedSingle in {
5123 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5124 X86fhadd, 0>, VEX_4V;
5125 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5126 X86fhsub, 0>, VEX_4V;
5127 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5128 X86fhadd, 0>, VEX_4V, VEX_L;
5129 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5130 X86fhsub, 0>, VEX_4V, VEX_L;
5132 let ExeDomain = SSEPackedDouble in {
5133 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5134 X86fhadd, 0>, VEX_4V;
5135 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5136 X86fhsub, 0>, VEX_4V;
5137 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5138 X86fhadd, 0>, VEX_4V, VEX_L;
5139 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5140 X86fhsub, 0>, VEX_4V, VEX_L;
5144 let Constraints = "$src1 = $dst" in {
5145 let ExeDomain = SSEPackedSingle in {
5146 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5147 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5149 let ExeDomain = SSEPackedDouble in {
5150 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5151 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5155 //===---------------------------------------------------------------------===//
5156 // SSSE3 - Packed Absolute Instructions
5157 //===---------------------------------------------------------------------===//
5160 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5161 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5162 Intrinsic IntId128> {
5163 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5165 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5166 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5169 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5171 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5174 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5178 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5179 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5180 Intrinsic IntId256> {
5181 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5183 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5184 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5187 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5189 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5192 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5195 let Predicates = [HasAVX] in {
5196 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5197 int_x86_ssse3_pabs_b_128>, VEX;
5198 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5199 int_x86_ssse3_pabs_w_128>, VEX;
5200 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5201 int_x86_ssse3_pabs_d_128>, VEX;
5204 let Predicates = [HasAVX2] in {
5205 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5206 int_x86_avx2_pabs_b>, VEX, VEX_L;
5207 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5208 int_x86_avx2_pabs_w>, VEX, VEX_L;
5209 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5210 int_x86_avx2_pabs_d>, VEX, VEX_L;
5213 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5214 int_x86_ssse3_pabs_b_128>;
5215 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5216 int_x86_ssse3_pabs_w_128>;
5217 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5218 int_x86_ssse3_pabs_d_128>;
5220 //===---------------------------------------------------------------------===//
5221 // SSSE3 - Packed Binary Operator Instructions
5222 //===---------------------------------------------------------------------===//
5224 def SSE_PHADDSUBD : OpndItins<
5225 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5227 def SSE_PHADDSUBSW : OpndItins<
5228 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5230 def SSE_PHADDSUBW : OpndItins<
5231 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5233 def SSE_PSHUFB : OpndItins<
5234 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5236 def SSE_PSIGN : OpndItins<
5237 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5239 def SSE_PMULHRSW : OpndItins<
5240 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5243 /// SS3I_binop_rm - Simple SSSE3 bin op
5244 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5245 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5246 X86MemOperand x86memop, OpndItins itins,
5248 let isCommutable = 1 in
5249 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5250 (ins RC:$src1, RC:$src2),
5252 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5253 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5254 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5256 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5257 (ins RC:$src1, x86memop:$src2),
5259 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5260 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5262 (OpVT (OpNode RC:$src1,
5263 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5266 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5267 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5268 Intrinsic IntId128, OpndItins itins,
5270 let isCommutable = 1 in
5271 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5272 (ins VR128:$src1, VR128:$src2),
5274 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5275 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5276 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5278 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5279 (ins VR128:$src1, i128mem:$src2),
5281 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5282 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5284 (IntId128 VR128:$src1,
5285 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5288 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5289 Intrinsic IntId256> {
5290 let isCommutable = 1 in
5291 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5292 (ins VR256:$src1, VR256:$src2),
5293 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5294 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5296 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5297 (ins VR256:$src1, i256mem:$src2),
5298 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5300 (IntId256 VR256:$src1,
5301 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5304 let ImmT = NoImm, Predicates = [HasAVX] in {
5305 let isCommutable = 0 in {
5306 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5307 memopv2i64, i128mem,
5308 SSE_PHADDSUBW, 0>, VEX_4V;
5309 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5310 memopv2i64, i128mem,
5311 SSE_PHADDSUBD, 0>, VEX_4V;
5312 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5313 memopv2i64, i128mem,
5314 SSE_PHADDSUBW, 0>, VEX_4V;
5315 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5316 memopv2i64, i128mem,
5317 SSE_PHADDSUBD, 0>, VEX_4V;
5318 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5319 memopv2i64, i128mem,
5320 SSE_PSIGN, 0>, VEX_4V;
5321 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5322 memopv2i64, i128mem,
5323 SSE_PSIGN, 0>, VEX_4V;
5324 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5325 memopv2i64, i128mem,
5326 SSE_PSIGN, 0>, VEX_4V;
5327 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5328 memopv2i64, i128mem,
5329 SSE_PSHUFB, 0>, VEX_4V;
5330 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5331 int_x86_ssse3_phadd_sw_128,
5332 SSE_PHADDSUBSW, 0>, VEX_4V;
5333 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5334 int_x86_ssse3_phsub_sw_128,
5335 SSE_PHADDSUBSW, 0>, VEX_4V;
5336 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5337 int_x86_ssse3_pmadd_ub_sw_128,
5338 SSE_PMADD, 0>, VEX_4V;
5340 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5341 int_x86_ssse3_pmul_hr_sw_128,
5342 SSE_PMULHRSW, 0>, VEX_4V;
5345 let ImmT = NoImm, Predicates = [HasAVX2] in {
5346 let isCommutable = 0 in {
5347 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5348 memopv4i64, i256mem,
5349 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5350 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5351 memopv4i64, i256mem,
5352 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5353 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5354 memopv4i64, i256mem,
5355 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5356 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5357 memopv4i64, i256mem,
5358 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5359 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5360 memopv4i64, i256mem,
5361 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5362 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5363 memopv4i64, i256mem,
5364 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5365 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5366 memopv4i64, i256mem,
5367 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5368 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5369 memopv4i64, i256mem,
5370 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5371 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5372 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5373 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5374 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5375 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5376 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5378 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5379 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5382 // None of these have i8 immediate fields.
5383 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5384 let isCommutable = 0 in {
5385 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5386 memopv2i64, i128mem, SSE_PHADDSUBW>;
5387 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5388 memopv2i64, i128mem, SSE_PHADDSUBD>;
5389 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5390 memopv2i64, i128mem, SSE_PHADDSUBW>;
5391 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5392 memopv2i64, i128mem, SSE_PHADDSUBD>;
5393 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5394 memopv2i64, i128mem, SSE_PSIGN>;
5395 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5396 memopv2i64, i128mem, SSE_PSIGN>;
5397 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5398 memopv2i64, i128mem, SSE_PSIGN>;
5399 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5400 memopv2i64, i128mem, SSE_PSHUFB>;
5401 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5402 int_x86_ssse3_phadd_sw_128,
5404 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5405 int_x86_ssse3_phsub_sw_128,
5407 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5408 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5410 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5411 int_x86_ssse3_pmul_hr_sw_128,
5415 //===---------------------------------------------------------------------===//
5416 // SSSE3 - Packed Align Instruction Patterns
5417 //===---------------------------------------------------------------------===//
5419 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5420 let neverHasSideEffects = 1 in {
5421 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5422 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5424 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5426 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5427 [], IIC_SSE_PALIGNR>, OpSize;
5429 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5430 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5432 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5434 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5435 [], IIC_SSE_PALIGNR>, OpSize;
5439 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5440 let neverHasSideEffects = 1 in {
5441 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5442 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5444 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5447 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5448 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5450 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5455 let Predicates = [HasAVX] in
5456 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5457 let Predicates = [HasAVX2] in
5458 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V, VEX_L;
5459 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5460 defm PALIGN : ssse3_palign<"palignr">;
5462 let Predicates = [HasAVX2] in {
5463 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5464 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5465 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5466 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5467 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5468 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5469 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5470 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5473 let Predicates = [HasAVX] in {
5474 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5475 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5476 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5477 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5478 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5479 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5480 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5481 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5484 let Predicates = [UseSSSE3] in {
5485 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5486 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5487 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5488 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5489 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5490 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5491 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5492 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5495 //===---------------------------------------------------------------------===//
5496 // SSSE3 - Thread synchronization
5497 //===---------------------------------------------------------------------===//
5499 let usesCustomInserter = 1 in {
5500 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5501 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5502 Requires<[HasSSE3]>;
5505 let Uses = [EAX, ECX, EDX] in
5506 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5507 TB, Requires<[HasSSE3]>;
5508 let Uses = [ECX, EAX] in
5509 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5510 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5511 TB, Requires<[HasSSE3]>;
5513 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5514 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5516 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5517 Requires<[In32BitMode]>;
5518 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5519 Requires<[In64BitMode]>;
5521 //===----------------------------------------------------------------------===//
5522 // SSE4.1 - Packed Move with Sign/Zero Extend
5523 //===----------------------------------------------------------------------===//
5525 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5526 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5527 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5528 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5530 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5531 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5533 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5537 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5539 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5540 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5541 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5543 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5544 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5545 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5548 let Predicates = [HasAVX] in {
5549 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5551 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5553 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5555 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5557 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5559 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5563 let Predicates = [HasAVX2] in {
5564 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5565 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5566 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5567 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5568 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5569 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5570 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5571 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5572 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5573 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5574 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5575 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5578 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5579 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5580 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5581 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5582 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5583 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5585 let Predicates = [HasAVX] in {
5586 // Common patterns involving scalar load.
5587 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5588 (VPMOVSXBWrm addr:$src)>;
5589 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5590 (VPMOVSXBWrm addr:$src)>;
5591 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5592 (VPMOVSXBWrm addr:$src)>;
5594 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5595 (VPMOVSXWDrm addr:$src)>;
5596 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5597 (VPMOVSXWDrm addr:$src)>;
5598 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5599 (VPMOVSXWDrm addr:$src)>;
5601 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5602 (VPMOVSXDQrm addr:$src)>;
5603 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5604 (VPMOVSXDQrm addr:$src)>;
5605 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5606 (VPMOVSXDQrm addr:$src)>;
5608 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5609 (VPMOVZXBWrm addr:$src)>;
5610 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5611 (VPMOVZXBWrm addr:$src)>;
5612 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5613 (VPMOVZXBWrm addr:$src)>;
5615 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5616 (VPMOVZXWDrm addr:$src)>;
5617 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5618 (VPMOVZXWDrm addr:$src)>;
5619 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5620 (VPMOVZXWDrm addr:$src)>;
5622 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5623 (VPMOVZXDQrm addr:$src)>;
5624 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5625 (VPMOVZXDQrm addr:$src)>;
5626 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5627 (VPMOVZXDQrm addr:$src)>;
5630 let Predicates = [UseSSE41] in {
5631 // Common patterns involving scalar load.
5632 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5633 (PMOVSXBWrm addr:$src)>;
5634 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5635 (PMOVSXBWrm addr:$src)>;
5636 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5637 (PMOVSXBWrm addr:$src)>;
5639 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5640 (PMOVSXWDrm addr:$src)>;
5641 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5642 (PMOVSXWDrm addr:$src)>;
5643 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5644 (PMOVSXWDrm addr:$src)>;
5646 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5647 (PMOVSXDQrm addr:$src)>;
5648 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5649 (PMOVSXDQrm addr:$src)>;
5650 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5651 (PMOVSXDQrm addr:$src)>;
5653 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5654 (PMOVZXBWrm addr:$src)>;
5655 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5656 (PMOVZXBWrm addr:$src)>;
5657 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5658 (PMOVZXBWrm addr:$src)>;
5660 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5661 (PMOVZXWDrm addr:$src)>;
5662 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5663 (PMOVZXWDrm addr:$src)>;
5664 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5665 (PMOVZXWDrm addr:$src)>;
5667 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5668 (PMOVZXDQrm addr:$src)>;
5669 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5670 (PMOVZXDQrm addr:$src)>;
5671 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5672 (PMOVZXDQrm addr:$src)>;
5675 let Predicates = [HasAVX2] in {
5676 let AddedComplexity = 15 in {
5677 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5678 (VPMOVZXDQYrr VR128:$src)>;
5679 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5680 (VPMOVZXWDYrr VR128:$src)>;
5683 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5684 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5687 let Predicates = [HasAVX] in {
5688 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5689 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5692 let Predicates = [UseSSE41] in {
5693 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5694 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5698 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5699 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5700 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5701 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5703 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5704 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5706 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5710 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5712 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5713 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5714 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5716 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5717 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5719 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5723 let Predicates = [HasAVX] in {
5724 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5726 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5728 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5730 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5734 let Predicates = [HasAVX2] in {
5735 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5736 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5737 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5738 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5739 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5740 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5741 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5742 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5745 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5746 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5747 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5748 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5750 let Predicates = [HasAVX] in {
5751 // Common patterns involving scalar load
5752 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5753 (VPMOVSXBDrm addr:$src)>;
5754 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5755 (VPMOVSXWQrm addr:$src)>;
5757 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5758 (VPMOVZXBDrm addr:$src)>;
5759 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5760 (VPMOVZXWQrm addr:$src)>;
5763 let Predicates = [UseSSE41] in {
5764 // Common patterns involving scalar load
5765 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5766 (PMOVSXBDrm addr:$src)>;
5767 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5768 (PMOVSXWQrm addr:$src)>;
5770 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5771 (PMOVZXBDrm addr:$src)>;
5772 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5773 (PMOVZXWQrm addr:$src)>;
5776 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5777 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5778 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5779 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5781 // Expecting a i16 load any extended to i32 value.
5782 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5783 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5784 [(set VR128:$dst, (IntId (bitconvert
5785 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5789 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5791 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5792 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5793 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5795 // Expecting a i16 load any extended to i32 value.
5796 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5797 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5798 [(set VR256:$dst, (IntId (bitconvert
5799 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5803 let Predicates = [HasAVX] in {
5804 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5806 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5809 let Predicates = [HasAVX2] in {
5810 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5811 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5812 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5813 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5815 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5816 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5818 let Predicates = [HasAVX] in {
5819 // Common patterns involving scalar load
5820 def : Pat<(int_x86_sse41_pmovsxbq
5821 (bitconvert (v4i32 (X86vzmovl
5822 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5823 (VPMOVSXBQrm addr:$src)>;
5825 def : Pat<(int_x86_sse41_pmovzxbq
5826 (bitconvert (v4i32 (X86vzmovl
5827 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5828 (VPMOVZXBQrm addr:$src)>;
5831 let Predicates = [UseSSE41] in {
5832 // Common patterns involving scalar load
5833 def : Pat<(int_x86_sse41_pmovsxbq
5834 (bitconvert (v4i32 (X86vzmovl
5835 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5836 (PMOVSXBQrm addr:$src)>;
5838 def : Pat<(int_x86_sse41_pmovzxbq
5839 (bitconvert (v4i32 (X86vzmovl
5840 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5841 (PMOVZXBQrm addr:$src)>;
5844 let Predicates = [HasAVX2] in {
5845 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5846 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5847 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5849 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5850 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5852 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5855 let Predicates = [HasAVX] in {
5856 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5857 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5858 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5860 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5861 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5863 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5865 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5866 (VPMOVZXBWrm addr:$src)>;
5867 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5868 (VPMOVZXBWrm addr:$src)>;
5869 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5870 (VPMOVZXBDrm addr:$src)>;
5871 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5872 (VPMOVZXBQrm addr:$src)>;
5874 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5875 (VPMOVZXWDrm addr:$src)>;
5876 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5877 (VPMOVZXWDrm addr:$src)>;
5878 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5879 (VPMOVZXWQrm addr:$src)>;
5881 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5882 (VPMOVZXDQrm addr:$src)>;
5883 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5884 (VPMOVZXDQrm addr:$src)>;
5885 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5886 (VPMOVZXDQrm addr:$src)>;
5889 let Predicates = [UseSSE41] in {
5890 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
5891 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
5892 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
5894 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
5895 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
5897 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
5899 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5900 (PMOVZXBWrm addr:$src)>;
5901 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5902 (PMOVZXBWrm addr:$src)>;
5903 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5904 (PMOVZXBDrm addr:$src)>;
5905 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5906 (PMOVZXBQrm addr:$src)>;
5908 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5909 (PMOVZXWDrm addr:$src)>;
5910 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5911 (PMOVZXWDrm addr:$src)>;
5912 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5913 (PMOVZXWQrm addr:$src)>;
5915 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5916 (PMOVZXDQrm addr:$src)>;
5917 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5918 (PMOVZXDQrm addr:$src)>;
5919 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5920 (PMOVZXDQrm addr:$src)>;
5923 //===----------------------------------------------------------------------===//
5924 // SSE4.1 - Extract Instructions
5925 //===----------------------------------------------------------------------===//
5927 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5928 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5929 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5930 (ins VR128:$src1, i32i8imm:$src2),
5931 !strconcat(OpcodeStr,
5932 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5933 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5935 let neverHasSideEffects = 1, mayStore = 1 in
5936 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5937 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5938 !strconcat(OpcodeStr,
5939 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5942 // There's an AssertZext in the way of writing the store pattern
5943 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5946 let Predicates = [HasAVX] in {
5947 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5948 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5949 (ins VR128:$src1, i32i8imm:$src2),
5950 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5953 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5956 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5957 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5958 let neverHasSideEffects = 1, mayStore = 1 in
5959 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5960 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5961 !strconcat(OpcodeStr,
5962 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5965 // There's an AssertZext in the way of writing the store pattern
5966 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5969 let Predicates = [HasAVX] in
5970 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5972 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5975 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5976 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5977 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5978 (ins VR128:$src1, i32i8imm:$src2),
5979 !strconcat(OpcodeStr,
5980 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5982 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5983 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5984 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5985 !strconcat(OpcodeStr,
5986 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5987 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5988 addr:$dst)]>, OpSize;
5991 let Predicates = [HasAVX] in
5992 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5994 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5996 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5997 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5998 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5999 (ins VR128:$src1, i32i8imm:$src2),
6000 !strconcat(OpcodeStr,
6001 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6003 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6004 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6005 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6006 !strconcat(OpcodeStr,
6007 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6008 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6009 addr:$dst)]>, OpSize, REX_W;
6012 let Predicates = [HasAVX] in
6013 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6015 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6017 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6019 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
6020 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6021 (ins VR128:$src1, i32i8imm:$src2),
6022 !strconcat(OpcodeStr,
6023 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6025 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
6027 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6028 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6029 !strconcat(OpcodeStr,
6030 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6031 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6032 addr:$dst)]>, OpSize;
6035 let ExeDomain = SSEPackedSingle in {
6036 let Predicates = [HasAVX] in {
6037 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6038 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6039 (ins VR128:$src1, i32i8imm:$src2),
6040 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
6043 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
6046 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6047 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6050 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6052 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6055 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6056 Requires<[UseSSE41]>;
6058 //===----------------------------------------------------------------------===//
6059 // SSE4.1 - Insert Instructions
6060 //===----------------------------------------------------------------------===//
6062 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6063 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6064 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6066 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6068 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6070 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6071 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6072 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6074 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6076 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6078 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6079 imm:$src3))]>, OpSize;
6082 let Predicates = [HasAVX] in
6083 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6084 let Constraints = "$src1 = $dst" in
6085 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6087 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6088 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6089 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6091 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6093 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6095 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6097 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6098 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6100 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6102 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6104 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6105 imm:$src3)))]>, OpSize;
6108 let Predicates = [HasAVX] in
6109 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6110 let Constraints = "$src1 = $dst" in
6111 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6113 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6114 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6115 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6119 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6121 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6123 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6124 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6126 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6128 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6130 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6131 imm:$src3)))]>, OpSize;
6134 let Predicates = [HasAVX] in
6135 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6136 let Constraints = "$src1 = $dst" in
6137 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6139 // insertps has a few different modes, there's the first two here below which
6140 // are optimized inserts that won't zero arbitrary elements in the destination
6141 // vector. The next one matches the intrinsic and could zero arbitrary elements
6142 // in the target vector.
6143 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6144 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6145 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6147 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6149 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6151 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6153 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6154 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6156 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6158 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6160 (X86insrtps VR128:$src1,
6161 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6162 imm:$src3))]>, OpSize;
6165 let ExeDomain = SSEPackedSingle in {
6166 let Predicates = [HasAVX] in
6167 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6168 let Constraints = "$src1 = $dst" in
6169 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6172 //===----------------------------------------------------------------------===//
6173 // SSE4.1 - Round Instructions
6174 //===----------------------------------------------------------------------===//
6176 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6177 X86MemOperand x86memop, RegisterClass RC,
6178 PatFrag mem_frag32, PatFrag mem_frag64,
6179 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6180 let ExeDomain = SSEPackedSingle in {
6181 // Intrinsic operation, reg.
6182 // Vector intrinsic operation, reg
6183 def PSr : SS4AIi8<opcps, MRMSrcReg,
6184 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6185 !strconcat(OpcodeStr,
6186 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6187 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6190 // Vector intrinsic operation, mem
6191 def PSm : SS4AIi8<opcps, MRMSrcMem,
6192 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6193 !strconcat(OpcodeStr,
6194 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6196 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6198 } // ExeDomain = SSEPackedSingle
6200 let ExeDomain = SSEPackedDouble in {
6201 // Vector intrinsic operation, reg
6202 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6203 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6204 !strconcat(OpcodeStr,
6205 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6206 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6209 // Vector intrinsic operation, mem
6210 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6211 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6212 !strconcat(OpcodeStr,
6213 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6215 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6217 } // ExeDomain = SSEPackedDouble
6220 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6223 Intrinsic F64Int, bit Is2Addr = 1> {
6224 let ExeDomain = GenericDomain in {
6226 def SSr : SS4AIi8<opcss, MRMSrcReg,
6227 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6229 !strconcat(OpcodeStr,
6230 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6231 !strconcat(OpcodeStr,
6232 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6235 // Intrinsic operation, reg.
6236 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6237 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6239 !strconcat(OpcodeStr,
6240 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6241 !strconcat(OpcodeStr,
6242 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6243 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6246 // Intrinsic operation, mem.
6247 def SSm : SS4AIi8<opcss, MRMSrcMem,
6248 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6250 !strconcat(OpcodeStr,
6251 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6252 !strconcat(OpcodeStr,
6253 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6255 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6259 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6260 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6262 !strconcat(OpcodeStr,
6263 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6264 !strconcat(OpcodeStr,
6265 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6268 // Intrinsic operation, reg.
6269 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6270 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6272 !strconcat(OpcodeStr,
6273 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6274 !strconcat(OpcodeStr,
6275 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6276 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6279 // Intrinsic operation, mem.
6280 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6281 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6283 !strconcat(OpcodeStr,
6284 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6285 !strconcat(OpcodeStr,
6286 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6288 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6290 } // ExeDomain = GenericDomain
6293 // FP round - roundss, roundps, roundsd, roundpd
6294 let Predicates = [HasAVX] in {
6296 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6297 memopv4f32, memopv2f64,
6298 int_x86_sse41_round_ps,
6299 int_x86_sse41_round_pd>, VEX;
6300 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6301 memopv8f32, memopv4f64,
6302 int_x86_avx_round_ps_256,
6303 int_x86_avx_round_pd_256>, VEX, VEX_L;
6304 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6305 int_x86_sse41_round_ss,
6306 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6308 def : Pat<(ffloor FR32:$src),
6309 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6310 def : Pat<(f64 (ffloor FR64:$src)),
6311 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6312 def : Pat<(f32 (fnearbyint FR32:$src)),
6313 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6314 def : Pat<(f64 (fnearbyint FR64:$src)),
6315 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6316 def : Pat<(f32 (fceil FR32:$src)),
6317 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6318 def : Pat<(f64 (fceil FR64:$src)),
6319 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6320 def : Pat<(f32 (frint FR32:$src)),
6321 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6322 def : Pat<(f64 (frint FR64:$src)),
6323 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6324 def : Pat<(f32 (ftrunc FR32:$src)),
6325 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6326 def : Pat<(f64 (ftrunc FR64:$src)),
6327 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6329 def : Pat<(v4f32 (ffloor VR128:$src)),
6330 (VROUNDPSr VR128:$src, (i32 0x1))>;
6331 def : Pat<(v2f64 (ffloor VR128:$src)),
6332 (VROUNDPDr VR128:$src, (i32 0x1))>;
6333 def : Pat<(v8f32 (ffloor VR256:$src)),
6334 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6335 def : Pat<(v4f64 (ffloor VR256:$src)),
6336 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6339 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6340 memopv4f32, memopv2f64,
6341 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6342 let Constraints = "$src1 = $dst" in
6343 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6344 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6346 let Predicates = [UseSSE41] in {
6347 def : Pat<(ffloor FR32:$src),
6348 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6349 def : Pat<(f64 (ffloor FR64:$src)),
6350 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6351 def : Pat<(f32 (fnearbyint FR32:$src)),
6352 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6353 def : Pat<(f64 (fnearbyint FR64:$src)),
6354 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6355 def : Pat<(f32 (fceil FR32:$src)),
6356 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6357 def : Pat<(f64 (fceil FR64:$src)),
6358 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6359 def : Pat<(f32 (frint FR32:$src)),
6360 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6361 def : Pat<(f64 (frint FR64:$src)),
6362 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6363 def : Pat<(f32 (ftrunc FR32:$src)),
6364 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6365 def : Pat<(f64 (ftrunc FR64:$src)),
6366 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6368 def : Pat<(v4f32 (ffloor VR128:$src)),
6369 (ROUNDPSr VR128:$src, (i32 0x1))>;
6370 def : Pat<(v2f64 (ffloor VR128:$src)),
6371 (ROUNDPDr VR128:$src, (i32 0x1))>;
6374 //===----------------------------------------------------------------------===//
6375 // SSE4.1 - Packed Bit Test
6376 //===----------------------------------------------------------------------===//
6378 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6379 // the intel intrinsic that corresponds to this.
6380 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6381 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6382 "vptest\t{$src2, $src1|$src1, $src2}",
6383 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6385 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6386 "vptest\t{$src2, $src1|$src1, $src2}",
6387 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6390 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6391 "vptest\t{$src2, $src1|$src1, $src2}",
6392 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6394 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6395 "vptest\t{$src2, $src1|$src1, $src2}",
6396 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6400 let Defs = [EFLAGS] in {
6401 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6402 "ptest\t{$src2, $src1|$src1, $src2}",
6403 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6405 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6406 "ptest\t{$src2, $src1|$src1, $src2}",
6407 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6411 // The bit test instructions below are AVX only
6412 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6413 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6414 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6415 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6416 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6417 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6418 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6419 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6423 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6424 let ExeDomain = SSEPackedSingle in {
6425 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6426 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6429 let ExeDomain = SSEPackedDouble in {
6430 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6431 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6436 //===----------------------------------------------------------------------===//
6437 // SSE4.1 - Misc Instructions
6438 //===----------------------------------------------------------------------===//
6440 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6441 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6442 "popcnt{w}\t{$src, $dst|$dst, $src}",
6443 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6445 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6446 "popcnt{w}\t{$src, $dst|$dst, $src}",
6447 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6448 (implicit EFLAGS)]>, OpSize, XS;
6450 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6451 "popcnt{l}\t{$src, $dst|$dst, $src}",
6452 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6454 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6455 "popcnt{l}\t{$src, $dst|$dst, $src}",
6456 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6457 (implicit EFLAGS)]>, XS;
6459 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6460 "popcnt{q}\t{$src, $dst|$dst, $src}",
6461 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6463 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6464 "popcnt{q}\t{$src, $dst|$dst, $src}",
6465 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6466 (implicit EFLAGS)]>, XS;
6471 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6472 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6473 Intrinsic IntId128> {
6474 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6476 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6477 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6478 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6483 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6486 let Predicates = [HasAVX] in
6487 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6488 int_x86_sse41_phminposuw>, VEX;
6489 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6490 int_x86_sse41_phminposuw>;
6492 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6493 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6494 Intrinsic IntId128, bit Is2Addr = 1> {
6495 let isCommutable = 1 in
6496 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6497 (ins VR128:$src1, VR128:$src2),
6499 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6500 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6501 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6502 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6503 (ins VR128:$src1, i128mem:$src2),
6505 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6506 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6508 (IntId128 VR128:$src1,
6509 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6512 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6513 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6514 Intrinsic IntId256> {
6515 let isCommutable = 1 in
6516 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6517 (ins VR256:$src1, VR256:$src2),
6518 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6519 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6520 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6521 (ins VR256:$src1, i256mem:$src2),
6522 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6524 (IntId256 VR256:$src1,
6525 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6528 let Predicates = [HasAVX] in {
6529 let isCommutable = 0 in
6530 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6532 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6534 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6536 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6538 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6540 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6542 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6544 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6546 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6548 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6552 let Predicates = [HasAVX2] in {
6553 let isCommutable = 0 in
6554 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6555 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6556 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6557 int_x86_avx2_pmins_b>, VEX_4V, VEX_L;
6558 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6559 int_x86_avx2_pmins_d>, VEX_4V, VEX_L;
6560 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6561 int_x86_avx2_pminu_d>, VEX_4V, VEX_L;
6562 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6563 int_x86_avx2_pminu_w>, VEX_4V, VEX_L;
6564 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6565 int_x86_avx2_pmaxs_b>, VEX_4V, VEX_L;
6566 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6567 int_x86_avx2_pmaxs_d>, VEX_4V, VEX_L;
6568 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6569 int_x86_avx2_pmaxu_d>, VEX_4V, VEX_L;
6570 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6571 int_x86_avx2_pmaxu_w>, VEX_4V, VEX_L;
6572 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6573 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6576 let Constraints = "$src1 = $dst" in {
6577 let isCommutable = 0 in
6578 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6579 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6580 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6581 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6582 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6583 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6584 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6585 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6586 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6587 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6590 /// SS48I_binop_rm - Simple SSE41 binary operator.
6591 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6592 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6593 X86MemOperand x86memop, bit Is2Addr = 1> {
6594 let isCommutable = 1 in
6595 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6596 (ins RC:$src1, RC:$src2),
6598 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6599 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6600 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6601 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6602 (ins RC:$src1, x86memop:$src2),
6604 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6605 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6607 (OpVT (OpNode RC:$src1,
6608 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6611 let Predicates = [HasAVX] in {
6612 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6613 memopv2i64, i128mem, 0>, VEX_4V;
6614 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6615 memopv2i64, i128mem, 0>, VEX_4V;
6617 let Predicates = [HasAVX2] in {
6618 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6619 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6620 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6621 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6624 let Constraints = "$src1 = $dst" in {
6625 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6626 memopv2i64, i128mem>;
6627 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6628 memopv2i64, i128mem>;
6631 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6632 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6633 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6634 X86MemOperand x86memop, bit Is2Addr = 1> {
6635 let isCommutable = 1 in
6636 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6637 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6639 !strconcat(OpcodeStr,
6640 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6641 !strconcat(OpcodeStr,
6642 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6643 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6645 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6646 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6648 !strconcat(OpcodeStr,
6649 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6650 !strconcat(OpcodeStr,
6651 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6654 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6658 let Predicates = [HasAVX] in {
6659 let isCommutable = 0 in {
6660 let ExeDomain = SSEPackedSingle in {
6661 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6662 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6663 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6664 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6665 f256mem, 0>, VEX_4V, VEX_L;
6667 let ExeDomain = SSEPackedDouble in {
6668 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6669 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6670 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6671 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6672 f256mem, 0>, VEX_4V, VEX_L;
6674 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6675 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6676 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6677 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6679 let ExeDomain = SSEPackedSingle in
6680 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6681 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6682 let ExeDomain = SSEPackedDouble in
6683 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6684 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6685 let ExeDomain = SSEPackedSingle in
6686 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6687 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6690 let Predicates = [HasAVX2] in {
6691 let isCommutable = 0 in {
6692 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6693 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6694 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6695 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6699 let Constraints = "$src1 = $dst" in {
6700 let isCommutable = 0 in {
6701 let ExeDomain = SSEPackedSingle in
6702 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6703 VR128, memopv4f32, f128mem>;
6704 let ExeDomain = SSEPackedDouble in
6705 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6706 VR128, memopv2f64, f128mem>;
6707 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6708 VR128, memopv2i64, i128mem>;
6709 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6710 VR128, memopv2i64, i128mem>;
6712 let ExeDomain = SSEPackedSingle in
6713 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6714 VR128, memopv4f32, f128mem>;
6715 let ExeDomain = SSEPackedDouble in
6716 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6717 VR128, memopv2f64, f128mem>;
6720 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6721 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6722 RegisterClass RC, X86MemOperand x86memop,
6723 PatFrag mem_frag, Intrinsic IntId> {
6724 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6725 (ins RC:$src1, RC:$src2, RC:$src3),
6726 !strconcat(OpcodeStr,
6727 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6728 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6729 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6731 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6732 (ins RC:$src1, x86memop:$src2, RC:$src3),
6733 !strconcat(OpcodeStr,
6734 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6736 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6738 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6741 let Predicates = [HasAVX] in {
6742 let ExeDomain = SSEPackedDouble in {
6743 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6744 memopv2f64, int_x86_sse41_blendvpd>;
6745 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6746 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6747 } // ExeDomain = SSEPackedDouble
6748 let ExeDomain = SSEPackedSingle in {
6749 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6750 memopv4f32, int_x86_sse41_blendvps>;
6751 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6752 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6753 } // ExeDomain = SSEPackedSingle
6754 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6755 memopv2i64, int_x86_sse41_pblendvb>;
6758 let Predicates = [HasAVX2] in {
6759 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6760 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6763 let Predicates = [HasAVX] in {
6764 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6765 (v16i8 VR128:$src2))),
6766 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6767 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6768 (v4i32 VR128:$src2))),
6769 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6770 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6771 (v4f32 VR128:$src2))),
6772 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6773 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6774 (v2i64 VR128:$src2))),
6775 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6776 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6777 (v2f64 VR128:$src2))),
6778 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6779 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6780 (v8i32 VR256:$src2))),
6781 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6782 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6783 (v8f32 VR256:$src2))),
6784 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6785 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6786 (v4i64 VR256:$src2))),
6787 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6788 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6789 (v4f64 VR256:$src2))),
6790 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6792 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6794 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6795 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6797 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6799 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6801 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6802 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6804 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6805 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6807 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6810 let Predicates = [HasAVX2] in {
6811 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6812 (v32i8 VR256:$src2))),
6813 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6814 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6816 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6819 /// SS41I_ternary_int - SSE 4.1 ternary operator
6820 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6821 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6822 X86MemOperand x86memop, Intrinsic IntId> {
6823 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6824 (ins VR128:$src1, VR128:$src2),
6825 !strconcat(OpcodeStr,
6826 "\t{$src2, $dst|$dst, $src2}"),
6827 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6830 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6831 (ins VR128:$src1, x86memop:$src2),
6832 !strconcat(OpcodeStr,
6833 "\t{$src2, $dst|$dst, $src2}"),
6836 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6840 let ExeDomain = SSEPackedDouble in
6841 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
6842 int_x86_sse41_blendvpd>;
6843 let ExeDomain = SSEPackedSingle in
6844 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
6845 int_x86_sse41_blendvps>;
6846 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
6847 int_x86_sse41_pblendvb>;
6849 // Aliases with the implicit xmm0 argument
6850 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6851 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
6852 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6853 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
6854 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6855 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
6856 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6857 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
6858 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6859 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
6860 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6861 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
6863 let Predicates = [UseSSE41] in {
6864 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6865 (v16i8 VR128:$src2))),
6866 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6867 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6868 (v4i32 VR128:$src2))),
6869 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6870 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6871 (v4f32 VR128:$src2))),
6872 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6873 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6874 (v2i64 VR128:$src2))),
6875 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6876 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6877 (v2f64 VR128:$src2))),
6878 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6880 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6882 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6883 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6885 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6886 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6888 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6892 let Predicates = [HasAVX] in
6893 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6894 "vmovntdqa\t{$src, $dst|$dst, $src}",
6895 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6897 let Predicates = [HasAVX2] in
6898 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6899 "vmovntdqa\t{$src, $dst|$dst, $src}",
6900 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6902 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6903 "movntdqa\t{$src, $dst|$dst, $src}",
6904 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6907 //===----------------------------------------------------------------------===//
6908 // SSE4.2 - Compare Instructions
6909 //===----------------------------------------------------------------------===//
6911 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6912 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6913 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6914 X86MemOperand x86memop, bit Is2Addr = 1> {
6915 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6916 (ins RC:$src1, RC:$src2),
6918 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6919 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6920 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6922 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6923 (ins RC:$src1, x86memop:$src2),
6925 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6926 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6928 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6931 let Predicates = [HasAVX] in
6932 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6933 memopv2i64, i128mem, 0>, VEX_4V;
6935 let Predicates = [HasAVX2] in
6936 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6937 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6939 let Constraints = "$src1 = $dst" in
6940 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6941 memopv2i64, i128mem>;
6943 //===----------------------------------------------------------------------===//
6944 // SSE4.2 - String/text Processing Instructions
6945 //===----------------------------------------------------------------------===//
6947 // Packed Compare Implicit Length Strings, Return Mask
6948 multiclass pseudo_pcmpistrm<string asm> {
6949 def REG : PseudoI<(outs VR128:$dst),
6950 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6951 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6953 def MEM : PseudoI<(outs VR128:$dst),
6954 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6955 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6956 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6959 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6960 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6961 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
6964 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6965 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6966 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6967 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6969 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6970 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6971 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6974 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6975 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6976 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6977 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6979 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6980 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6981 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6984 // Packed Compare Explicit Length Strings, Return Mask
6985 multiclass pseudo_pcmpestrm<string asm> {
6986 def REG : PseudoI<(outs VR128:$dst),
6987 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6988 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6989 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6990 def MEM : PseudoI<(outs VR128:$dst),
6991 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6992 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6993 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6996 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6997 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6998 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7001 let Predicates = [HasAVX],
7002 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7003 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
7004 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7005 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
7007 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
7008 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7009 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
7012 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7013 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
7014 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7015 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
7017 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
7018 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7019 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
7022 // Packed Compare Implicit Length Strings, Return Index
7023 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7024 multiclass SS42AI_pcmpistri<string asm> {
7025 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7026 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7027 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7030 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7031 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7032 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7037 let Predicates = [HasAVX] in
7038 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7039 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7041 // Packed Compare Explicit Length Strings, Return Index
7042 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7043 multiclass SS42AI_pcmpestri<string asm> {
7044 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7045 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7046 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7049 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7050 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7051 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7056 let Predicates = [HasAVX] in
7057 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7058 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7060 //===----------------------------------------------------------------------===//
7061 // SSE4.2 - CRC Instructions
7062 //===----------------------------------------------------------------------===//
7064 // No CRC instructions have AVX equivalents
7066 // crc intrinsic instruction
7067 // This set of instructions are only rm, the only difference is the size
7069 let Constraints = "$src1 = $dst" in {
7070 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7071 (ins GR32:$src1, i8mem:$src2),
7072 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7074 (int_x86_sse42_crc32_32_8 GR32:$src1,
7075 (load addr:$src2)))]>;
7076 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7077 (ins GR32:$src1, GR8:$src2),
7078 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7080 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7081 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7082 (ins GR32:$src1, i16mem:$src2),
7083 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7085 (int_x86_sse42_crc32_32_16 GR32:$src1,
7086 (load addr:$src2)))]>,
7088 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7089 (ins GR32:$src1, GR16:$src2),
7090 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7092 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7094 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7095 (ins GR32:$src1, i32mem:$src2),
7096 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7098 (int_x86_sse42_crc32_32_32 GR32:$src1,
7099 (load addr:$src2)))]>;
7100 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7101 (ins GR32:$src1, GR32:$src2),
7102 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7104 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7105 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7106 (ins GR64:$src1, i8mem:$src2),
7107 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7109 (int_x86_sse42_crc32_64_8 GR64:$src1,
7110 (load addr:$src2)))]>,
7112 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7113 (ins GR64:$src1, GR8:$src2),
7114 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7116 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7118 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7119 (ins GR64:$src1, i64mem:$src2),
7120 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7122 (int_x86_sse42_crc32_64_64 GR64:$src1,
7123 (load addr:$src2)))]>,
7125 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7126 (ins GR64:$src1, GR64:$src2),
7127 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7129 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7133 //===----------------------------------------------------------------------===//
7134 // AES-NI Instructions
7135 //===----------------------------------------------------------------------===//
7137 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7138 Intrinsic IntId128, bit Is2Addr = 1> {
7139 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7140 (ins VR128:$src1, VR128:$src2),
7142 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7143 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7144 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7146 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7147 (ins VR128:$src1, i128mem:$src2),
7149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7152 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7155 // Perform One Round of an AES Encryption/Decryption Flow
7156 let Predicates = [HasAVX, HasAES] in {
7157 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7158 int_x86_aesni_aesenc, 0>, VEX_4V;
7159 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7160 int_x86_aesni_aesenclast, 0>, VEX_4V;
7161 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7162 int_x86_aesni_aesdec, 0>, VEX_4V;
7163 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7164 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7167 let Constraints = "$src1 = $dst" in {
7168 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7169 int_x86_aesni_aesenc>;
7170 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7171 int_x86_aesni_aesenclast>;
7172 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7173 int_x86_aesni_aesdec>;
7174 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7175 int_x86_aesni_aesdeclast>;
7178 // Perform the AES InvMixColumn Transformation
7179 let Predicates = [HasAVX, HasAES] in {
7180 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7182 "vaesimc\t{$src1, $dst|$dst, $src1}",
7184 (int_x86_aesni_aesimc VR128:$src1))]>,
7186 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7187 (ins i128mem:$src1),
7188 "vaesimc\t{$src1, $dst|$dst, $src1}",
7189 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7192 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7194 "aesimc\t{$src1, $dst|$dst, $src1}",
7196 (int_x86_aesni_aesimc VR128:$src1))]>,
7198 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7199 (ins i128mem:$src1),
7200 "aesimc\t{$src1, $dst|$dst, $src1}",
7201 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7204 // AES Round Key Generation Assist
7205 let Predicates = [HasAVX, HasAES] in {
7206 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7207 (ins VR128:$src1, i8imm:$src2),
7208 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7210 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7212 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7213 (ins i128mem:$src1, i8imm:$src2),
7214 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7216 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7219 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7220 (ins VR128:$src1, i8imm:$src2),
7221 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7223 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7225 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7226 (ins i128mem:$src1, i8imm:$src2),
7227 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7229 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7232 //===----------------------------------------------------------------------===//
7233 // PCLMUL Instructions
7234 //===----------------------------------------------------------------------===//
7236 // AVX carry-less Multiplication instructions
7237 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7238 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7239 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7241 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7243 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7244 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7245 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7246 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7247 (memopv2i64 addr:$src2), imm:$src3))]>;
7249 // Carry-less Multiplication instructions
7250 let Constraints = "$src1 = $dst" in {
7251 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7252 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7253 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7255 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7257 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7258 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7259 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7260 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7261 (memopv2i64 addr:$src2), imm:$src3))]>;
7262 } // Constraints = "$src1 = $dst"
7265 multiclass pclmul_alias<string asm, int immop> {
7266 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7267 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7269 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7270 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7272 def : InstAlias<!strconcat("vpclmul", asm,
7273 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7274 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7276 def : InstAlias<!strconcat("vpclmul", asm,
7277 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7278 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7280 defm : pclmul_alias<"hqhq", 0x11>;
7281 defm : pclmul_alias<"hqlq", 0x01>;
7282 defm : pclmul_alias<"lqhq", 0x10>;
7283 defm : pclmul_alias<"lqlq", 0x00>;
7285 //===----------------------------------------------------------------------===//
7286 // SSE4A Instructions
7287 //===----------------------------------------------------------------------===//
7289 let Predicates = [HasSSE4A] in {
7291 let Constraints = "$src = $dst" in {
7292 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7293 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7294 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7295 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7296 imm:$idx))]>, TB, OpSize;
7297 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7298 (ins VR128:$src, VR128:$mask),
7299 "extrq\t{$mask, $src|$src, $mask}",
7300 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7301 VR128:$mask))]>, TB, OpSize;
7303 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7304 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7305 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7306 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7307 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7308 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7309 (ins VR128:$src, VR128:$mask),
7310 "insertq\t{$mask, $src|$src, $mask}",
7311 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7312 VR128:$mask))]>, XD;
7315 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7316 "movntss\t{$src, $dst|$dst, $src}",
7317 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7319 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7320 "movntsd\t{$src, $dst|$dst, $src}",
7321 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7324 //===----------------------------------------------------------------------===//
7326 //===----------------------------------------------------------------------===//
7328 //===----------------------------------------------------------------------===//
7329 // VBROADCAST - Load from memory and broadcast to all elements of the
7330 // destination operand
7332 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7333 X86MemOperand x86memop, Intrinsic Int> :
7334 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7335 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7336 [(set RC:$dst, (Int addr:$src))]>, VEX;
7338 // AVX2 adds register forms
7339 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7341 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7342 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7343 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7345 let ExeDomain = SSEPackedSingle in {
7346 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7347 int_x86_avx_vbroadcast_ss>;
7348 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7349 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7351 let ExeDomain = SSEPackedDouble in
7352 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7353 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7354 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7355 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7357 let ExeDomain = SSEPackedSingle in {
7358 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7359 int_x86_avx2_vbroadcast_ss_ps>;
7360 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7361 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7363 let ExeDomain = SSEPackedDouble in
7364 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7365 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7367 let Predicates = [HasAVX2] in
7368 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7369 int_x86_avx2_vbroadcasti128>, VEX_L;
7371 let Predicates = [HasAVX] in
7372 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7373 (VBROADCASTF128 addr:$src)>;
7376 //===----------------------------------------------------------------------===//
7377 // VINSERTF128 - Insert packed floating-point values
7379 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7380 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7381 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7382 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7385 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7386 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7387 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7391 let Predicates = [HasAVX] in {
7392 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7394 (VINSERTF128rr VR256:$src1, VR128:$src2,
7395 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7396 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7398 (VINSERTF128rr VR256:$src1, VR128:$src2,
7399 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7401 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7403 (VINSERTF128rm VR256:$src1, addr:$src2,
7404 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7405 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7407 (VINSERTF128rm VR256:$src1, addr:$src2,
7408 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7411 let Predicates = [HasAVX1Only] in {
7412 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7414 (VINSERTF128rr VR256:$src1, VR128:$src2,
7415 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7416 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7418 (VINSERTF128rr VR256:$src1, VR128:$src2,
7419 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7420 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7422 (VINSERTF128rr VR256:$src1, VR128:$src2,
7423 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7424 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7426 (VINSERTF128rr VR256:$src1, VR128:$src2,
7427 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7429 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7431 (VINSERTF128rm VR256:$src1, addr:$src2,
7432 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7433 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7434 (bc_v4i32 (memopv2i64 addr:$src2)),
7436 (VINSERTF128rm VR256:$src1, addr:$src2,
7437 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7438 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7439 (bc_v16i8 (memopv2i64 addr:$src2)),
7441 (VINSERTF128rm VR256:$src1, addr:$src2,
7442 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7443 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7444 (bc_v8i16 (memopv2i64 addr:$src2)),
7446 (VINSERTF128rm VR256:$src1, addr:$src2,
7447 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7450 //===----------------------------------------------------------------------===//
7451 // VEXTRACTF128 - Extract packed floating-point values
7453 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7454 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7455 (ins VR256:$src1, i8imm:$src2),
7456 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7459 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7460 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7461 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7466 let Predicates = [HasAVX] in {
7467 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7468 (v4f32 (VEXTRACTF128rr
7469 (v8f32 VR256:$src1),
7470 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7471 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7472 (v2f64 (VEXTRACTF128rr
7473 (v4f64 VR256:$src1),
7474 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7476 def : Pat<(alignedstore (v4f32 (vextractf128_extract:$ext (v8f32 VR256:$src1),
7477 (iPTR imm))), addr:$dst),
7478 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7479 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7480 def : Pat<(alignedstore (v2f64 (vextractf128_extract:$ext (v4f64 VR256:$src1),
7481 (iPTR imm))), addr:$dst),
7482 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7483 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7486 let Predicates = [HasAVX1Only] in {
7487 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7488 (v2i64 (VEXTRACTF128rr
7489 (v4i64 VR256:$src1),
7490 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7491 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7492 (v4i32 (VEXTRACTF128rr
7493 (v8i32 VR256:$src1),
7494 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7495 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7496 (v8i16 (VEXTRACTF128rr
7497 (v16i16 VR256:$src1),
7498 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7499 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7500 (v16i8 (VEXTRACTF128rr
7501 (v32i8 VR256:$src1),
7502 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7504 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7505 (iPTR imm))), addr:$dst),
7506 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7507 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7508 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7509 (iPTR imm))), addr:$dst),
7510 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7511 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7512 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7513 (iPTR imm))), addr:$dst),
7514 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7515 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7516 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7517 (iPTR imm))), addr:$dst),
7518 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7519 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7522 //===----------------------------------------------------------------------===//
7523 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7525 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7526 Intrinsic IntLd, Intrinsic IntLd256,
7527 Intrinsic IntSt, Intrinsic IntSt256> {
7528 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7529 (ins VR128:$src1, f128mem:$src2),
7530 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7531 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7533 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7534 (ins VR256:$src1, f256mem:$src2),
7535 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7536 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7538 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7539 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7540 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7541 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7542 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7543 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7544 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7545 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7548 let ExeDomain = SSEPackedSingle in
7549 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7550 int_x86_avx_maskload_ps,
7551 int_x86_avx_maskload_ps_256,
7552 int_x86_avx_maskstore_ps,
7553 int_x86_avx_maskstore_ps_256>;
7554 let ExeDomain = SSEPackedDouble in
7555 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7556 int_x86_avx_maskload_pd,
7557 int_x86_avx_maskload_pd_256,
7558 int_x86_avx_maskstore_pd,
7559 int_x86_avx_maskstore_pd_256>;
7561 //===----------------------------------------------------------------------===//
7562 // VPERMIL - Permute Single and Double Floating-Point Values
7564 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7565 RegisterClass RC, X86MemOperand x86memop_f,
7566 X86MemOperand x86memop_i, PatFrag i_frag,
7567 Intrinsic IntVar, ValueType vt> {
7568 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7569 (ins RC:$src1, RC:$src2),
7570 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7571 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7572 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7573 (ins RC:$src1, x86memop_i:$src2),
7574 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7575 [(set RC:$dst, (IntVar RC:$src1,
7576 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7578 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7579 (ins RC:$src1, i8imm:$src2),
7580 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7581 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7582 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7583 (ins x86memop_f:$src1, i8imm:$src2),
7584 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7586 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7589 let ExeDomain = SSEPackedSingle in {
7590 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7591 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7592 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7593 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7595 let ExeDomain = SSEPackedDouble in {
7596 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7597 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7598 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7599 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7602 let Predicates = [HasAVX] in {
7603 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7604 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7605 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7606 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7607 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7609 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7610 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7611 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7613 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7614 (VPERMILPDri VR128:$src1, imm:$imm)>;
7615 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7616 (VPERMILPDmi addr:$src1, imm:$imm)>;
7619 //===----------------------------------------------------------------------===//
7620 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7622 let ExeDomain = SSEPackedSingle in {
7623 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7624 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7625 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7626 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7627 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7628 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7629 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7630 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7631 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7632 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7635 let Predicates = [HasAVX] in {
7636 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7637 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7638 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7639 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7640 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7643 let Predicates = [HasAVX1Only] in {
7644 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7645 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7646 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7647 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7648 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7649 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7650 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7651 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7653 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7654 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7655 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7656 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7657 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7658 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7659 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7660 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7661 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7662 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7663 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7664 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7667 //===----------------------------------------------------------------------===//
7668 // VZERO - Zero YMM registers
7670 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7671 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7672 // Zero All YMM registers
7673 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7674 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7676 // Zero Upper bits of YMM registers
7677 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7678 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7681 //===----------------------------------------------------------------------===//
7682 // Half precision conversion instructions
7683 //===----------------------------------------------------------------------===//
7684 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7685 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7686 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7687 [(set RC:$dst, (Int VR128:$src))]>,
7689 let neverHasSideEffects = 1, mayLoad = 1 in
7690 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7691 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7694 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7695 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7696 (ins RC:$src1, i32i8imm:$src2),
7697 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7698 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7700 let neverHasSideEffects = 1, mayStore = 1 in
7701 def mr : Ii8<0x1D, MRMDestMem, (outs),
7702 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7703 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7707 let Predicates = [HasAVX, HasF16C] in {
7708 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7709 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7710 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7711 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7714 //===----------------------------------------------------------------------===//
7715 // AVX2 Instructions
7716 //===----------------------------------------------------------------------===//
7718 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7719 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7720 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7721 X86MemOperand x86memop> {
7722 let isCommutable = 1 in
7723 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7724 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7725 !strconcat(OpcodeStr,
7726 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7727 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7729 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7730 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7731 !strconcat(OpcodeStr,
7732 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7735 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7739 let isCommutable = 0 in {
7740 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7741 VR128, memopv2i64, i128mem>;
7742 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7743 VR256, memopv4i64, i256mem>, VEX_L;
7746 //===----------------------------------------------------------------------===//
7747 // VPBROADCAST - Load from memory and broadcast to all elements of the
7748 // destination operand
7750 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7751 X86MemOperand x86memop, PatFrag ld_frag,
7752 Intrinsic Int128, Intrinsic Int256> {
7753 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7754 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7755 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7756 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7757 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7759 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7760 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7761 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7762 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
7763 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7764 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7766 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
7770 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7771 int_x86_avx2_pbroadcastb_128,
7772 int_x86_avx2_pbroadcastb_256>;
7773 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7774 int_x86_avx2_pbroadcastw_128,
7775 int_x86_avx2_pbroadcastw_256>;
7776 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7777 int_x86_avx2_pbroadcastd_128,
7778 int_x86_avx2_pbroadcastd_256>;
7779 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7780 int_x86_avx2_pbroadcastq_128,
7781 int_x86_avx2_pbroadcastq_256>;
7783 let Predicates = [HasAVX2] in {
7784 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7785 (VPBROADCASTBrm addr:$src)>;
7786 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7787 (VPBROADCASTBYrm addr:$src)>;
7788 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7789 (VPBROADCASTWrm addr:$src)>;
7790 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7791 (VPBROADCASTWYrm addr:$src)>;
7792 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7793 (VPBROADCASTDrm addr:$src)>;
7794 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7795 (VPBROADCASTDYrm addr:$src)>;
7796 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7797 (VPBROADCASTQrm addr:$src)>;
7798 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7799 (VPBROADCASTQYrm addr:$src)>;
7801 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
7802 (VPBROADCASTBrr VR128:$src)>;
7803 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
7804 (VPBROADCASTBYrr VR128:$src)>;
7805 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
7806 (VPBROADCASTWrr VR128:$src)>;
7807 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
7808 (VPBROADCASTWYrr VR128:$src)>;
7809 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
7810 (VPBROADCASTDrr VR128:$src)>;
7811 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
7812 (VPBROADCASTDYrr VR128:$src)>;
7813 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
7814 (VPBROADCASTQrr VR128:$src)>;
7815 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
7816 (VPBROADCASTQYrr VR128:$src)>;
7817 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
7818 (VBROADCASTSSrr VR128:$src)>;
7819 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
7820 (VBROADCASTSSYrr VR128:$src)>;
7821 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
7822 (VPBROADCASTQrr VR128:$src)>;
7823 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
7824 (VBROADCASTSDYrr VR128:$src)>;
7826 // Provide fallback in case the load node that is used in the patterns above
7827 // is used by additional users, which prevents the pattern selection.
7828 let AddedComplexity = 20 in {
7829 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7830 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7831 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7832 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7833 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7834 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
7836 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7837 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7838 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7839 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7840 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7841 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
7845 // AVX1 broadcast patterns
7846 let Predicates = [HasAVX1Only] in {
7847 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7848 (VBROADCASTSSYrm addr:$src)>;
7849 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7850 (VBROADCASTSDYrm addr:$src)>;
7851 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7852 (VBROADCASTSSrm addr:$src)>;
7855 let Predicates = [HasAVX] in {
7856 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7857 (VBROADCASTSSYrm addr:$src)>;
7858 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7859 (VBROADCASTSDYrm addr:$src)>;
7860 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7861 (VBROADCASTSSrm addr:$src)>;
7863 // Provide fallback in case the load node that is used in the patterns above
7864 // is used by additional users, which prevents the pattern selection.
7865 let AddedComplexity = 20 in {
7866 // 128bit broadcasts:
7867 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7868 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
7869 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7870 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7871 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
7872 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
7873 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7874 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7875 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
7876 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
7878 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7879 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
7880 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7881 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7882 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
7883 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
7884 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7885 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7886 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
7887 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
7891 //===----------------------------------------------------------------------===//
7892 // VPERM - Permute instructions
7895 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7897 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7898 (ins VR256:$src1, VR256:$src2),
7899 !strconcat(OpcodeStr,
7900 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7902 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
7904 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7905 (ins VR256:$src1, i256mem:$src2),
7906 !strconcat(OpcodeStr,
7907 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7909 (OpVT (X86VPermv VR256:$src1,
7910 (bitconvert (mem_frag addr:$src2)))))]>,
7914 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7915 let ExeDomain = SSEPackedSingle in
7916 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7918 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7920 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7921 (ins VR256:$src1, i8imm:$src2),
7922 !strconcat(OpcodeStr,
7923 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7925 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
7927 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7928 (ins i256mem:$src1, i8imm:$src2),
7929 !strconcat(OpcodeStr,
7930 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7932 (OpVT (X86VPermi (mem_frag addr:$src1),
7933 (i8 imm:$src2))))]>, VEX, VEX_L;
7936 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7937 let ExeDomain = SSEPackedDouble in
7938 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7940 //===----------------------------------------------------------------------===//
7941 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7943 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7944 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7945 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7946 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7947 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7948 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7949 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7950 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7951 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7952 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7954 let Predicates = [HasAVX2] in {
7955 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7956 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7957 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7958 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7959 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7960 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7962 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7964 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7965 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7966 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7967 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7968 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7970 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7974 //===----------------------------------------------------------------------===//
7975 // VINSERTI128 - Insert packed integer values
7977 let neverHasSideEffects = 1 in {
7978 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7979 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7980 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7983 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7984 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7985 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7989 let Predicates = [HasAVX2] in {
7990 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7992 (VINSERTI128rr VR256:$src1, VR128:$src2,
7993 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7994 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7996 (VINSERTI128rr VR256:$src1, VR128:$src2,
7997 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7998 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8000 (VINSERTI128rr VR256:$src1, VR128:$src2,
8001 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8002 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8004 (VINSERTI128rr VR256:$src1, VR128:$src2,
8005 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8007 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
8009 (VINSERTI128rm VR256:$src1, addr:$src2,
8010 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8011 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
8012 (bc_v4i32 (memopv2i64 addr:$src2)),
8014 (VINSERTI128rm VR256:$src1, addr:$src2,
8015 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8016 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
8017 (bc_v16i8 (memopv2i64 addr:$src2)),
8019 (VINSERTI128rm VR256:$src1, addr:$src2,
8020 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8021 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
8022 (bc_v8i16 (memopv2i64 addr:$src2)),
8024 (VINSERTI128rm VR256:$src1, addr:$src2,
8025 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8028 //===----------------------------------------------------------------------===//
8029 // VEXTRACTI128 - Extract packed integer values
8031 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8032 (ins VR256:$src1, i8imm:$src2),
8033 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8035 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8037 let neverHasSideEffects = 1, mayStore = 1 in
8038 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8039 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8040 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8043 let Predicates = [HasAVX2] in {
8044 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8045 (v2i64 (VEXTRACTI128rr
8046 (v4i64 VR256:$src1),
8047 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8048 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8049 (v4i32 (VEXTRACTI128rr
8050 (v8i32 VR256:$src1),
8051 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8052 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8053 (v8i16 (VEXTRACTI128rr
8054 (v16i16 VR256:$src1),
8055 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8056 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8057 (v16i8 (VEXTRACTI128rr
8058 (v32i8 VR256:$src1),
8059 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8061 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
8062 (iPTR imm))), addr:$dst),
8063 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8064 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8065 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
8066 (iPTR imm))), addr:$dst),
8067 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8068 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8069 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
8070 (iPTR imm))), addr:$dst),
8071 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8072 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8073 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
8074 (iPTR imm))), addr:$dst),
8075 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8076 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8079 //===----------------------------------------------------------------------===//
8080 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8082 multiclass avx2_pmovmask<string OpcodeStr,
8083 Intrinsic IntLd128, Intrinsic IntLd256,
8084 Intrinsic IntSt128, Intrinsic IntSt256> {
8085 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8086 (ins VR128:$src1, i128mem:$src2),
8087 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8088 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8089 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8090 (ins VR256:$src1, i256mem:$src2),
8091 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8092 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8094 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8095 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8096 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8097 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8098 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8099 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8100 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8101 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8104 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8105 int_x86_avx2_maskload_d,
8106 int_x86_avx2_maskload_d_256,
8107 int_x86_avx2_maskstore_d,
8108 int_x86_avx2_maskstore_d_256>;
8109 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8110 int_x86_avx2_maskload_q,
8111 int_x86_avx2_maskload_q_256,
8112 int_x86_avx2_maskstore_q,
8113 int_x86_avx2_maskstore_q_256>, VEX_W;
8116 //===----------------------------------------------------------------------===//
8117 // Variable Bit Shifts
8119 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8120 ValueType vt128, ValueType vt256> {
8121 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8122 (ins VR128:$src1, VR128:$src2),
8123 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8125 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8127 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8128 (ins VR128:$src1, i128mem:$src2),
8129 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8131 (vt128 (OpNode VR128:$src1,
8132 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8134 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8135 (ins VR256:$src1, VR256:$src2),
8136 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8138 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8140 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8141 (ins VR256:$src1, i256mem:$src2),
8142 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8144 (vt256 (OpNode VR256:$src1,
8145 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8149 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8150 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8151 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8152 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8153 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8155 //===----------------------------------------------------------------------===//
8156 // VGATHER - GATHER Operations
8157 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8158 X86MemOperand memop128, X86MemOperand memop256> {
8159 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8160 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8161 !strconcat(OpcodeStr,
8162 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8164 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8165 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8166 !strconcat(OpcodeStr,
8167 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8168 []>, VEX_4VOp3, VEX_L;
8171 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
8172 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8173 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8174 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8175 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8176 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8177 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8178 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8179 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;