1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, [SDNPHasChain]>;
22 def X86loadu : SDNode<"X86ISD::LOAD_UA", SDTLoad, [SDNPHasChain]>;
23 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
24 [SDNPCommutative, SDNPAssociative]>;
25 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
26 [SDNPCommutative, SDNPAssociative]>;
27 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
28 [SDNPHasChain, SDNPOutFlag]>;
29 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
30 [SDNPHasChain, SDNPOutFlag]>;
31 def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
32 def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
33 def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
35 //===----------------------------------------------------------------------===//
36 // SSE Complex Patterns
37 //===----------------------------------------------------------------------===//
39 // These are 'extloads' from a scalar to the low element of a vector, zeroing
40 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
42 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
44 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
47 def ssmem : Operand<v4f32> {
48 let PrintMethod = "printf32mem";
49 let NumMIOperands = 4;
50 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
52 def sdmem : Operand<v2f64> {
53 let PrintMethod = "printf64mem";
54 let NumMIOperands = 4;
55 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
58 //===----------------------------------------------------------------------===//
59 // SSE pattern fragments
60 //===----------------------------------------------------------------------===//
62 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
63 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
65 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
66 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
67 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
69 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
70 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
71 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
72 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
73 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
74 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
76 def fp32imm0 : PatLeaf<(f32 fpimm), [{
77 return N->isExactlyValue(+0.0);
80 def PSxLDQ_imm : SDNodeXForm<imm, [{
81 // Transformation function: imm >> 3
82 return getI32Imm(N->getValue() >> 3);
85 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
87 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
88 return getI8Imm(X86::getShuffleSHUFImmediate(N));
91 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
93 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
94 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
97 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
99 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
100 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
103 def SSE_splat_mask : PatLeaf<(build_vector), [{
104 return X86::isSplatMask(N);
105 }], SHUFFLE_get_shuf_imm>;
107 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
108 return X86::isSplatLoMask(N);
111 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
112 return X86::isMOVHLPSMask(N);
115 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
116 return X86::isMOVHPMask(N);
119 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
120 return X86::isMOVLPMask(N);
123 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
124 return X86::isMOVLMask(N);
127 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
128 return X86::isMOVSHDUPMask(N);
131 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
132 return X86::isMOVSLDUPMask(N);
135 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isUNPCKLMask(N);
139 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isUNPCKHMask(N);
143 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isUNPCKL_v_undef_Mask(N);
147 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
148 return X86::isPSHUFDMask(N);
149 }], SHUFFLE_get_shuf_imm>;
151 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
152 return X86::isPSHUFHWMask(N);
153 }], SHUFFLE_get_pshufhw_imm>;
155 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
156 return X86::isPSHUFLWMask(N);
157 }], SHUFFLE_get_pshuflw_imm>;
159 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
160 return X86::isPSHUFDMask(N);
161 }], SHUFFLE_get_shuf_imm>;
163 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
164 return X86::isSHUFPMask(N);
165 }], SHUFFLE_get_shuf_imm>;
167 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
168 return X86::isSHUFPMask(N);
169 }], SHUFFLE_get_shuf_imm>;
171 //===----------------------------------------------------------------------===//
172 // SSE scalar FP Instructions
173 //===----------------------------------------------------------------------===//
175 // Instruction templates
176 // SSI - SSE1 instructions with XS prefix.
177 // SDI - SSE2 instructions with XD prefix.
178 // PSI - SSE1 instructions with TB prefix.
179 // PDI - SSE2 instructions with TB and OpSize prefixes.
180 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
181 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
182 // S3I - SSE3 instructions with TB and OpSize prefixes.
183 // S3SI - SSE3 instructions with XS prefix.
184 // S3DI - SSE3 instructions with XD prefix.
185 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
186 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
187 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
188 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
189 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
190 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
191 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
192 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
193 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
194 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
195 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
196 : Ii8<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
198 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
199 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
200 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
201 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
202 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
203 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
205 //===----------------------------------------------------------------------===//
206 // Helpers for defining instructions that directly correspond to intrinsics.
208 multiclass SS_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
209 def r : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
210 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
211 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
212 def m : SSI<o, MRMSrcMem, (ops VR128:$dst, ssmem:$src),
213 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
214 [(set VR128:$dst, (v4f32 (IntId sse_load_f32:$src)))]>;
217 multiclass SD_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
218 def r : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
219 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
220 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
221 def m : SDI<o, MRMSrcMem, (ops VR128:$dst, sdmem:$src),
222 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
223 [(set VR128:$dst, (v2f64 (IntId sse_load_f64:$src)))]>;
226 class PS_Intr<bits<8> o, string OpcodeStr, Intrinsic IntId>
227 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
228 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
229 [(set VR128:$dst, (IntId VR128:$src))]>;
230 class PS_Intm<bits<8> o, string OpcodeStr, Intrinsic IntId>
231 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
232 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
233 [(set VR128:$dst, (IntId (load addr:$src)))]>;
234 class PD_Intr<bits<8> o, string OpcodeStr, Intrinsic IntId>
235 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
236 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
237 [(set VR128:$dst, (IntId VR128:$src))]>;
238 class PD_Intm<bits<8> o, string OpcodeStr, Intrinsic IntId>
239 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
240 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
241 [(set VR128:$dst, (IntId (load addr:$src)))]>;
243 class PS_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
244 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
245 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
246 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
247 class PS_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
248 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
249 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
250 [(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))]>;
251 class PD_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
252 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
253 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
254 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
255 class PD_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
256 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
257 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
258 [(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))]>;
260 // Some 'special' instructions
261 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
262 "#IMPLICIT_DEF $dst",
263 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
264 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
265 "#IMPLICIT_DEF $dst",
266 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
268 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
269 // scheduler into a branch sequence.
270 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
271 def CMOV_FR32 : I<0, Pseudo,
272 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
273 "#CMOV_FR32 PSEUDO!",
274 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
275 def CMOV_FR64 : I<0, Pseudo,
276 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
277 "#CMOV_FR64 PSEUDO!",
278 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
279 def CMOV_V4F32 : I<0, Pseudo,
280 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
281 "#CMOV_V4F32 PSEUDO!",
283 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
284 def CMOV_V2F64 : I<0, Pseudo,
285 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
286 "#CMOV_V2F64 PSEUDO!",
288 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
289 def CMOV_V2I64 : I<0, Pseudo,
290 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
291 "#CMOV_V2I64 PSEUDO!",
293 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
297 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
298 "movss {$src, $dst|$dst, $src}", []>;
299 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
300 "movss {$src, $dst|$dst, $src}",
301 [(set FR32:$dst, (loadf32 addr:$src))]>;
302 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
303 "movsd {$src, $dst|$dst, $src}", []>;
304 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
305 "movsd {$src, $dst|$dst, $src}",
306 [(set FR64:$dst, (loadf64 addr:$src))]>;
308 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
309 "movss {$src, $dst|$dst, $src}",
310 [(store FR32:$src, addr:$dst)]>;
311 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
312 "movsd {$src, $dst|$dst, $src}",
313 [(store FR64:$src, addr:$dst)]>;
315 /// scalar_sse12_fp_binop_rm - Scalar SSE binops come in four basic forms:
316 /// 1. f32 vs f64 - These come in SSE1/SSE2 forms for float/doubles.
317 /// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
319 /// In addition, scalar SSE ops have an intrinsic form. This form is unlike the
320 /// normal form, in that they take an entire vector (instead of a scalar) and
321 /// leave the top elements undefined. This adds another two variants of the
322 /// above permutations, giving us 8 forms for 'instruction'.
324 let isTwoAddress = 1 in {
325 multiclass scalar_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
326 SDNode OpNode, Intrinsic F32Int,
327 Intrinsic F64Int, bit Commutable = 0> {
328 // Scalar operation, reg+reg.
329 def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
330 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2"),
331 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
332 let isCommutable = Commutable;
334 def SDrr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
335 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2"),
336 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
337 let isCommutable = Commutable;
339 // Scalar operation, reg+mem.
340 def SSrm : SSI<opc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
341 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2"),
342 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
343 def SDrm : SDI<opc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
344 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2"),
345 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
347 // Vector intrinsic operation, reg+reg.
348 def SSrr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
349 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2"),
350 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
351 let isCommutable = Commutable;
353 def SDrr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
354 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2"),
355 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
356 let isCommutable = Commutable;
358 // Vector intrinsic operation, reg+mem.
359 def SSrm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2),
360 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2"),
361 [(set VR128:$dst, (F32Int VR128:$src1,
362 sse_load_f32:$src2))]>;
363 def SDrm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2),
364 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2"),
365 [(set VR128:$dst, (F64Int VR128:$src1,
366 sse_load_f64:$src2))]>;
370 // Arithmetic instructions
372 defm ADD : scalar_sse12_fp_binop_rm<0x58, "add", fadd,
373 int_x86_sse_add_ss, int_x86_sse2_add_sd, 1>;
374 defm MUL : scalar_sse12_fp_binop_rm<0x59, "mul", fmul,
375 int_x86_sse_mul_ss, int_x86_sse2_mul_sd, 1>;
376 defm SUB : scalar_sse12_fp_binop_rm<0x5C, "sub", fsub,
377 int_x86_sse_sub_ss, int_x86_sse2_sub_sd>;
378 defm DIV : scalar_sse12_fp_binop_rm<0x5E, "div", fdiv,
379 int_x86_sse_div_ss, int_x86_sse2_div_sd>;
382 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
383 "sqrtss {$src, $dst|$dst, $src}",
384 [(set FR32:$dst, (fsqrt FR32:$src))]>;
385 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
386 "sqrtss {$src, $dst|$dst, $src}",
387 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
388 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
389 "sqrtsd {$src, $dst|$dst, $src}",
390 [(set FR64:$dst, (fsqrt FR64:$src))]>;
391 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
392 "sqrtsd {$src, $dst|$dst, $src}",
393 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
395 class SS_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
396 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
397 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
398 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
399 class SS_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
400 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2),
401 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
402 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, sse_load_f32:$src2)))]>;
403 class SD_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
404 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
405 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
406 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
407 class SD_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
408 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2),
409 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
410 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, sse_load_f64:$src2)))]>;
413 // Aliases to match intrinsics which expect XMM operand(s).
415 defm SQRTSS_Int : SS_IntUnary<0x51, "sqrtss" , int_x86_sse_sqrt_ss>;
416 defm SQRTSD_Int : SD_IntUnary<0x51, "sqrtsd" , int_x86_sse2_sqrt_sd>;
417 defm RSQRTSS_Int : SS_IntUnary<0x52, "rsqrtss", int_x86_sse_rsqrt_ss>;
418 defm RCPSS_Int : SS_IntUnary<0x53, "rcpss" , int_x86_sse_rcp_ss>;
420 let isTwoAddress = 1 in {
421 let isCommutable = 1 in {
422 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss", int_x86_sse_max_ss>;
423 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd", int_x86_sse2_max_sd>;
424 def Int_MINSSrr : SS_Intrr<0x5D, "minss", int_x86_sse_min_ss>;
425 def Int_MINSDrr : SD_Intrr<0x5D, "minsd", int_x86_sse2_min_sd>;
427 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss", int_x86_sse_max_ss>;
428 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd", int_x86_sse2_max_sd>;
429 def Int_MINSSrm : SS_Intrm<0x5D, "minss", int_x86_sse_min_ss>;
430 def Int_MINSDrm : SD_Intrm<0x5D, "minsd", int_x86_sse2_min_sd>;
433 // Conversion instructions
434 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src),
435 "cvttss2si {$src, $dst|$dst, $src}",
436 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
437 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
438 "cvttss2si {$src, $dst|$dst, $src}",
439 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
440 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src),
441 "cvttsd2si {$src, $dst|$dst, $src}",
442 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
443 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src),
444 "cvttsd2si {$src, $dst|$dst, $src}",
445 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
446 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
447 "cvtsd2ss {$src, $dst|$dst, $src}",
448 [(set FR32:$dst, (fround FR64:$src))]>;
449 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
450 "cvtsd2ss {$src, $dst|$dst, $src}",
451 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
452 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src),
453 "cvtsi2ss {$src, $dst|$dst, $src}",
454 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
455 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
456 "cvtsi2ss {$src, $dst|$dst, $src}",
457 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
458 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src),
459 "cvtsi2sd {$src, $dst|$dst, $src}",
460 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
461 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
462 "cvtsi2sd {$src, $dst|$dst, $src}",
463 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
465 // SSE2 instructions with XS prefix
466 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
467 "cvtss2sd {$src, $dst|$dst, $src}",
468 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
470 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
471 "cvtss2sd {$src, $dst|$dst, $src}",
472 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
475 // Match intrinsics which expect XMM operand(s).
476 def Int_CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
477 "cvtss2si {$src, $dst|$dst, $src}",
478 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
479 def Int_CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
480 "cvtss2si {$src, $dst|$dst, $src}",
481 [(set GR32:$dst, (int_x86_sse_cvtss2si
482 (load addr:$src)))]>;
483 def Int_CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
484 "cvtsd2si {$src, $dst|$dst, $src}",
485 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
486 def Int_CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
487 "cvtsd2si {$src, $dst|$dst, $src}",
488 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
489 (load addr:$src)))]>;
491 // Aliases for intrinsics
492 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
493 "cvttss2si {$src, $dst|$dst, $src}",
494 [(set GR32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
495 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
496 "cvttss2si {$src, $dst|$dst, $src}",
497 [(set GR32:$dst, (int_x86_sse_cvttss2si(load addr:$src)))]>;
498 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
499 "cvttsd2si {$src, $dst|$dst, $src}",
500 [(set GR32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
501 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
502 "cvttsd2si {$src, $dst|$dst, $src}",
503 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
504 (load addr:$src)))]>;
506 let isTwoAddress = 1 in {
507 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
508 (ops VR128:$dst, VR128:$src1, GR32:$src2),
509 "cvtsi2ss {$src2, $dst|$dst, $src2}",
510 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
512 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
513 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
514 "cvtsi2ss {$src2, $dst|$dst, $src2}",
515 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
516 (loadi32 addr:$src2)))]>;
519 // Comparison instructions
520 let isTwoAddress = 1 in {
521 def CMPSSrr : SSI<0xC2, MRMSrcReg,
522 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
523 "cmp${cc}ss {$src, $dst|$dst, $src}",
525 def CMPSSrm : SSI<0xC2, MRMSrcMem,
526 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
527 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
528 def CMPSDrr : SDI<0xC2, MRMSrcReg,
529 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
530 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
531 def CMPSDrm : SDI<0xC2, MRMSrcMem,
532 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
533 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
536 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
537 "ucomiss {$src2, $src1|$src1, $src2}",
538 [(X86cmp FR32:$src1, FR32:$src2)]>;
539 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
540 "ucomiss {$src2, $src1|$src1, $src2}",
541 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
542 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
543 "ucomisd {$src2, $src1|$src1, $src2}",
544 [(X86cmp FR64:$src1, FR64:$src2)]>;
545 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
546 "ucomisd {$src2, $src1|$src1, $src2}",
547 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
549 // Aliases to match intrinsics which expect XMM operand(s).
550 let isTwoAddress = 1 in {
551 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
552 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
553 "cmp${cc}ss {$src, $dst|$dst, $src}",
554 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
555 VR128:$src, imm:$cc))]>;
556 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
557 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
558 "cmp${cc}ss {$src, $dst|$dst, $src}",
559 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
560 (load addr:$src), imm:$cc))]>;
561 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
562 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
563 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
564 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
565 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
566 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
569 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
570 "ucomiss {$src2, $src1|$src1, $src2}",
571 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
572 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
573 "ucomiss {$src2, $src1|$src1, $src2}",
574 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>;
575 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
576 "ucomisd {$src2, $src1|$src1, $src2}",
577 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
578 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
579 "ucomisd {$src2, $src1|$src1, $src2}",
580 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>;
582 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
583 "comiss {$src2, $src1|$src1, $src2}",
584 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
585 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
586 "comiss {$src2, $src1|$src1, $src2}",
587 [(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>;
588 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
589 "comisd {$src2, $src1|$src1, $src2}",
590 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
591 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
592 "comisd {$src2, $src1|$src1, $src2}",
593 [(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
595 // Aliases of packed instructions for scalar use. These all have names that
598 // Alias instructions that map fld0 to pxor for sse.
599 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
600 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
601 Requires<[HasSSE1]>, TB, OpSize;
602 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
603 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
604 Requires<[HasSSE2]>, TB, OpSize;
606 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
607 // Upper bits are disregarded.
608 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
609 "movaps {$src, $dst|$dst, $src}", []>;
610 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
611 "movapd {$src, $dst|$dst, $src}", []>;
613 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
614 // Upper bits are disregarded.
615 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
616 "movaps {$src, $dst|$dst, $src}",
617 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
618 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
619 "movapd {$src, $dst|$dst, $src}",
620 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
622 // Alias bitwise logical operations using SSE logical ops on packed FP values.
623 let isTwoAddress = 1 in {
624 let isCommutable = 1 in {
625 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
626 "andps {$src2, $dst|$dst, $src2}",
627 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
628 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
629 "andpd {$src2, $dst|$dst, $src2}",
630 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
631 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
632 "orps {$src2, $dst|$dst, $src2}", []>;
633 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
634 "orpd {$src2, $dst|$dst, $src2}", []>;
635 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
636 "xorps {$src2, $dst|$dst, $src2}",
637 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
638 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
639 "xorpd {$src2, $dst|$dst, $src2}",
640 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
642 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
643 "andps {$src2, $dst|$dst, $src2}",
644 [(set FR32:$dst, (X86fand FR32:$src1,
645 (X86loadpf32 addr:$src2)))]>;
646 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
647 "andpd {$src2, $dst|$dst, $src2}",
648 [(set FR64:$dst, (X86fand FR64:$src1,
649 (X86loadpf64 addr:$src2)))]>;
650 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
651 "orps {$src2, $dst|$dst, $src2}", []>;
652 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
653 "orpd {$src2, $dst|$dst, $src2}", []>;
654 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
655 "xorps {$src2, $dst|$dst, $src2}",
656 [(set FR32:$dst, (X86fxor FR32:$src1,
657 (X86loadpf32 addr:$src2)))]>;
658 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
659 "xorpd {$src2, $dst|$dst, $src2}",
660 [(set FR64:$dst, (X86fxor FR64:$src1,
661 (X86loadpf64 addr:$src2)))]>;
663 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
664 "andnps {$src2, $dst|$dst, $src2}", []>;
665 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
666 "andnps {$src2, $dst|$dst, $src2}", []>;
667 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
668 "andnpd {$src2, $dst|$dst, $src2}", []>;
669 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
670 "andnpd {$src2, $dst|$dst, $src2}", []>;
673 //===----------------------------------------------------------------------===//
674 // SSE packed FP Instructions
675 //===----------------------------------------------------------------------===//
677 // Some 'special' instructions
678 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
679 "#IMPLICIT_DEF $dst",
680 [(set VR128:$dst, (v4f32 (undef)))]>,
684 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
685 "movaps {$src, $dst|$dst, $src}", []>;
686 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
687 "movaps {$src, $dst|$dst, $src}",
688 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
689 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
690 "movapd {$src, $dst|$dst, $src}", []>;
691 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
692 "movapd {$src, $dst|$dst, $src}",
693 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
695 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
696 "movaps {$src, $dst|$dst, $src}",
697 [(store (v4f32 VR128:$src), addr:$dst)]>;
698 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
699 "movapd {$src, $dst|$dst, $src}",
700 [(store (v2f64 VR128:$src), addr:$dst)]>;
702 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
703 "movups {$src, $dst|$dst, $src}", []>;
704 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
705 "movups {$src, $dst|$dst, $src}",
706 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
707 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
708 "movups {$src, $dst|$dst, $src}",
709 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
710 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
711 "movupd {$src, $dst|$dst, $src}", []>;
712 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
713 "movupd {$src, $dst|$dst, $src}",
714 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
715 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
716 "movupd {$src, $dst|$dst, $src}",
717 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
719 let isTwoAddress = 1 in {
720 let AddedComplexity = 20 in {
721 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
722 "movlps {$src2, $dst|$dst, $src2}",
724 (v4f32 (vector_shuffle VR128:$src1,
725 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
726 MOVLP_shuffle_mask)))]>;
727 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
728 "movlpd {$src2, $dst|$dst, $src2}",
730 (v2f64 (vector_shuffle VR128:$src1,
731 (scalar_to_vector (loadf64 addr:$src2)),
732 MOVLP_shuffle_mask)))]>;
733 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
734 "movhps {$src2, $dst|$dst, $src2}",
736 (v4f32 (vector_shuffle VR128:$src1,
737 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
738 MOVHP_shuffle_mask)))]>;
739 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
740 "movhpd {$src2, $dst|$dst, $src2}",
742 (v2f64 (vector_shuffle VR128:$src1,
743 (scalar_to_vector (loadf64 addr:$src2)),
744 MOVHP_shuffle_mask)))]>;
748 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
749 "movlps {$src, $dst|$dst, $src}",
750 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
751 (iPTR 0))), addr:$dst)]>;
752 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
753 "movlpd {$src, $dst|$dst, $src}",
754 [(store (f64 (vector_extract (v2f64 VR128:$src),
755 (iPTR 0))), addr:$dst)]>;
757 // v2f64 extract element 1 is always custom lowered to unpack high to low
758 // and extract element 0 so the non-store version isn't too horrible.
759 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
760 "movhps {$src, $dst|$dst, $src}",
761 [(store (f64 (vector_extract
762 (v2f64 (vector_shuffle
763 (bc_v2f64 (v4f32 VR128:$src)), (undef),
764 UNPCKH_shuffle_mask)), (iPTR 0))),
766 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
767 "movhpd {$src, $dst|$dst, $src}",
768 [(store (f64 (vector_extract
769 (v2f64 (vector_shuffle VR128:$src, (undef),
770 UNPCKH_shuffle_mask)), (iPTR 0))),
773 let isTwoAddress = 1 in {
774 let AddedComplexity = 15 in {
775 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
776 "movlhps {$src2, $dst|$dst, $src2}",
778 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
779 MOVHP_shuffle_mask)))]>;
781 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
782 "movhlps {$src2, $dst|$dst, $src2}",
784 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
785 MOVHLPS_shuffle_mask)))]>;
789 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
790 "movshdup {$src, $dst|$dst, $src}",
791 [(set VR128:$dst, (v4f32 (vector_shuffle
793 MOVSHDUP_shuffle_mask)))]>;
794 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
795 "movshdup {$src, $dst|$dst, $src}",
796 [(set VR128:$dst, (v4f32 (vector_shuffle
797 (loadv4f32 addr:$src), (undef),
798 MOVSHDUP_shuffle_mask)))]>;
800 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
801 "movsldup {$src, $dst|$dst, $src}",
802 [(set VR128:$dst, (v4f32 (vector_shuffle
804 MOVSLDUP_shuffle_mask)))]>;
805 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
806 "movsldup {$src, $dst|$dst, $src}",
807 [(set VR128:$dst, (v4f32 (vector_shuffle
808 (loadv4f32 addr:$src), (undef),
809 MOVSLDUP_shuffle_mask)))]>;
811 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
812 "movddup {$src, $dst|$dst, $src}",
813 [(set VR128:$dst, (v2f64 (vector_shuffle
815 SSE_splat_lo_mask)))]>;
816 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
817 "movddup {$src, $dst|$dst, $src}",
818 [(set VR128:$dst, (v2f64 (vector_shuffle
819 (scalar_to_vector (loadf64 addr:$src)),
821 SSE_splat_lo_mask)))]>;
823 // SSE2 instructions without OpSize prefix
824 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
825 "cvtdq2ps {$src, $dst|$dst, $src}",
826 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
827 TB, Requires<[HasSSE2]>;
828 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
829 "cvtdq2ps {$src, $dst|$dst, $src}",
830 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
831 (bitconvert (loadv2i64 addr:$src))))]>,
832 TB, Requires<[HasSSE2]>;
834 // SSE2 instructions with XS prefix
835 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
836 "cvtdq2pd {$src, $dst|$dst, $src}",
837 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
838 XS, Requires<[HasSSE2]>;
839 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
840 "cvtdq2pd {$src, $dst|$dst, $src}",
841 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
842 (bitconvert (loadv2i64 addr:$src))))]>,
843 XS, Requires<[HasSSE2]>;
845 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
846 "cvtps2dq {$src, $dst|$dst, $src}",
847 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
848 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
849 "cvtps2dq {$src, $dst|$dst, $src}",
850 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
851 (load addr:$src)))]>;
852 // SSE2 packed instructions with XS prefix
853 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
854 "cvttps2dq {$src, $dst|$dst, $src}",
855 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
856 XS, Requires<[HasSSE2]>;
857 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
858 "cvttps2dq {$src, $dst|$dst, $src}",
859 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
860 (load addr:$src)))]>,
861 XS, Requires<[HasSSE2]>;
863 // SSE2 packed instructions with XD prefix
864 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
865 "cvtpd2dq {$src, $dst|$dst, $src}",
866 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
867 XD, Requires<[HasSSE2]>;
868 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
869 "cvtpd2dq {$src, $dst|$dst, $src}",
870 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
871 (load addr:$src)))]>,
872 XD, Requires<[HasSSE2]>;
873 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
874 "cvttpd2dq {$src, $dst|$dst, $src}",
875 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
876 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
877 "cvttpd2dq {$src, $dst|$dst, $src}",
878 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
879 (load addr:$src)))]>;
881 // SSE2 instructions without OpSize prefix
882 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
883 "cvtps2pd {$src, $dst|$dst, $src}",
884 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
885 TB, Requires<[HasSSE2]>;
886 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
887 "cvtps2pd {$src, $dst|$dst, $src}",
888 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
889 (load addr:$src)))]>,
890 TB, Requires<[HasSSE2]>;
892 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
893 "cvtpd2ps {$src, $dst|$dst, $src}",
894 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
895 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
896 "cvtpd2ps {$src, $dst|$dst, $src}",
897 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
898 (load addr:$src)))]>;
900 // Match intrinsics which expect XMM operand(s).
901 // Aliases for intrinsics
902 let isTwoAddress = 1 in {
903 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
904 (ops VR128:$dst, VR128:$src1, GR32:$src2),
905 "cvtsi2sd {$src2, $dst|$dst, $src2}",
906 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
908 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
909 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
910 "cvtsi2sd {$src2, $dst|$dst, $src2}",
911 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
912 (loadi32 addr:$src2)))]>;
913 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
914 (ops VR128:$dst, VR128:$src1, VR128:$src2),
915 "cvtsd2ss {$src2, $dst|$dst, $src2}",
916 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
918 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
919 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
920 "cvtsd2ss {$src2, $dst|$dst, $src2}",
921 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
922 (load addr:$src2)))]>;
923 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
924 (ops VR128:$dst, VR128:$src1, VR128:$src2),
925 "cvtss2sd {$src2, $dst|$dst, $src2}",
926 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
929 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
930 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
931 "cvtss2sd {$src2, $dst|$dst, $src2}",
932 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
933 (load addr:$src2)))]>, XS,
937 /// packed_sse12_fp_binop_rm - Packed SSE binops come in four basic forms:
938 /// 1. v4f32 vs v2f64 - These come in SSE1/SSE2 forms for float/doubles.
939 /// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
941 let isTwoAddress = 1 in {
942 multiclass packed_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
943 SDNode OpNode, bit Commutable = 0> {
944 // Packed operation, reg+reg.
945 def PSrr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
946 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2"),
947 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
948 let isCommutable = Commutable;
950 def PDrr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
951 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2"),
952 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
953 let isCommutable = Commutable;
955 // Packed operation, reg+mem.
956 def PSrm : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
957 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2"),
958 [(set VR128:$dst, (OpNode VR128:$src1, (loadv4f32 addr:$src2)))]>;
959 def PDrm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
960 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2"),
961 [(set VR128:$dst, (OpNode VR128:$src1, (loadv2f64 addr:$src2)))]>;
965 defm ADD : packed_sse12_fp_binop_rm<0x58, "add", fadd, 1>;
966 defm MUL : packed_sse12_fp_binop_rm<0x59, "mul", fmul, 1>;
967 defm DIV : packed_sse12_fp_binop_rm<0x5E, "div", fdiv>;
968 defm SUB : packed_sse12_fp_binop_rm<0x5C, "sub", fsub>;
971 let isTwoAddress = 1 in {
972 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
973 (ops VR128:$dst, VR128:$src1, VR128:$src2),
974 "addsubps {$src2, $dst|$dst, $src2}",
975 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
977 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
978 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
979 "addsubps {$src2, $dst|$dst, $src2}",
980 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
981 (load addr:$src2)))]>;
982 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
983 (ops VR128:$dst, VR128:$src1, VR128:$src2),
984 "addsubpd {$src2, $dst|$dst, $src2}",
985 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
987 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
988 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
989 "addsubpd {$src2, $dst|$dst, $src2}",
990 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
991 (load addr:$src2)))]>;
994 def SQRTPSr : PS_Intr<0x51, "sqrtps", int_x86_sse_sqrt_ps>;
995 def SQRTPSm : PS_Intm<0x51, "sqrtps", int_x86_sse_sqrt_ps>;
996 def SQRTPDr : PD_Intr<0x51, "sqrtpd", int_x86_sse2_sqrt_pd>;
997 def SQRTPDm : PD_Intm<0x51, "sqrtpd", int_x86_sse2_sqrt_pd>;
999 def RSQRTPSr : PS_Intr<0x52, "rsqrtps", int_x86_sse_rsqrt_ps>;
1000 def RSQRTPSm : PS_Intm<0x52, "rsqrtps", int_x86_sse_rsqrt_ps>;
1001 def RCPPSr : PS_Intr<0x53, "rcpps", int_x86_sse_rcp_ps>;
1002 def RCPPSm : PS_Intm<0x53, "rcpps", int_x86_sse_rcp_ps>;
1004 let isTwoAddress = 1 in {
1005 let isCommutable = 1 in {
1006 def MAXPSrr : PS_Intrr<0x5F, "maxps", int_x86_sse_max_ps>;
1007 def MAXPDrr : PD_Intrr<0x5F, "maxpd", int_x86_sse2_max_pd>;
1008 def MINPSrr : PS_Intrr<0x5D, "minps", int_x86_sse_min_ps>;
1009 def MINPDrr : PD_Intrr<0x5D, "minpd", int_x86_sse2_min_pd>;
1011 def MAXPSrm : PS_Intrm<0x5F, "maxps", int_x86_sse_max_ps>;
1012 def MAXPDrm : PD_Intrm<0x5F, "maxpd", int_x86_sse2_max_pd>;
1013 def MINPSrm : PS_Intrm<0x5D, "minps", int_x86_sse_min_ps>;
1014 def MINPDrm : PD_Intrm<0x5D, "minpd", int_x86_sse2_min_pd>;
1018 let isTwoAddress = 1 in {
1019 let isCommutable = 1 in {
1020 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1021 "andps {$src2, $dst|$dst, $src2}",
1022 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1023 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1024 "andpd {$src2, $dst|$dst, $src2}",
1026 (and (bc_v2i64 (v2f64 VR128:$src1)),
1027 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1028 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1029 "orps {$src2, $dst|$dst, $src2}",
1030 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1031 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1032 "orpd {$src2, $dst|$dst, $src2}",
1034 (or (bc_v2i64 (v2f64 VR128:$src1)),
1035 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1036 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1037 "xorps {$src2, $dst|$dst, $src2}",
1038 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1039 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1040 "xorpd {$src2, $dst|$dst, $src2}",
1042 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1043 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1045 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1046 "andps {$src2, $dst|$dst, $src2}",
1047 [(set VR128:$dst, (and VR128:$src1,
1048 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1049 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1050 "andpd {$src2, $dst|$dst, $src2}",
1052 (and (bc_v2i64 (v2f64 VR128:$src1)),
1053 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1054 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1055 "orps {$src2, $dst|$dst, $src2}",
1056 [(set VR128:$dst, (or VR128:$src1,
1057 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1058 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1059 "orpd {$src2, $dst|$dst, $src2}",
1061 (or (bc_v2i64 (v2f64 VR128:$src1)),
1062 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1063 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1064 "xorps {$src2, $dst|$dst, $src2}",
1065 [(set VR128:$dst, (xor VR128:$src1,
1066 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1067 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1068 "xorpd {$src2, $dst|$dst, $src2}",
1070 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1071 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1072 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1073 "andnps {$src2, $dst|$dst, $src2}",
1074 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1075 (bc_v2i64 (v4i32 immAllOnesV))),
1077 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1078 "andnps {$src2, $dst|$dst, $src2}",
1079 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1080 (bc_v2i64 (v4i32 immAllOnesV))),
1081 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1082 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1083 "andnpd {$src2, $dst|$dst, $src2}",
1085 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1086 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1087 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1088 "andnpd {$src2, $dst|$dst, $src2}",
1090 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1091 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1094 let isTwoAddress = 1 in {
1095 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1096 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1097 "cmp${cc}ps {$src, $dst|$dst, $src}",
1098 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1099 VR128:$src, imm:$cc))]>;
1100 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1101 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1102 "cmp${cc}ps {$src, $dst|$dst, $src}",
1103 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1104 (load addr:$src), imm:$cc))]>;
1105 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1106 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1107 "cmp${cc}pd {$src, $dst|$dst, $src}",
1108 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1109 VR128:$src, imm:$cc))]>;
1110 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1111 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1112 "cmp${cc}pd {$src, $dst|$dst, $src}",
1113 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1114 (load addr:$src), imm:$cc))]>;
1117 // Shuffle and unpack instructions
1118 let isTwoAddress = 1 in {
1119 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1120 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1121 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1122 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1123 [(set VR128:$dst, (v4f32 (vector_shuffle
1124 VR128:$src1, VR128:$src2,
1125 SHUFP_shuffle_mask:$src3)))]>;
1126 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1127 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1128 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1129 [(set VR128:$dst, (v4f32 (vector_shuffle
1130 VR128:$src1, (load addr:$src2),
1131 SHUFP_shuffle_mask:$src3)))]>;
1132 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1133 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1134 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1135 [(set VR128:$dst, (v2f64 (vector_shuffle
1136 VR128:$src1, VR128:$src2,
1137 SHUFP_shuffle_mask:$src3)))]>;
1138 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1139 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1140 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1141 [(set VR128:$dst, (v2f64 (vector_shuffle
1142 VR128:$src1, (load addr:$src2),
1143 SHUFP_shuffle_mask:$src3)))]>;
1145 let AddedComplexity = 10 in {
1146 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1147 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1148 "unpckhps {$src2, $dst|$dst, $src2}",
1149 [(set VR128:$dst, (v4f32 (vector_shuffle
1150 VR128:$src1, VR128:$src2,
1151 UNPCKH_shuffle_mask)))]>;
1152 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1153 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1154 "unpckhps {$src2, $dst|$dst, $src2}",
1155 [(set VR128:$dst, (v4f32 (vector_shuffle
1156 VR128:$src1, (load addr:$src2),
1157 UNPCKH_shuffle_mask)))]>;
1158 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1159 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1160 "unpckhpd {$src2, $dst|$dst, $src2}",
1161 [(set VR128:$dst, (v2f64 (vector_shuffle
1162 VR128:$src1, VR128:$src2,
1163 UNPCKH_shuffle_mask)))]>;
1164 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1165 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1166 "unpckhpd {$src2, $dst|$dst, $src2}",
1167 [(set VR128:$dst, (v2f64 (vector_shuffle
1168 VR128:$src1, (load addr:$src2),
1169 UNPCKH_shuffle_mask)))]>;
1171 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1172 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1173 "unpcklps {$src2, $dst|$dst, $src2}",
1174 [(set VR128:$dst, (v4f32 (vector_shuffle
1175 VR128:$src1, VR128:$src2,
1176 UNPCKL_shuffle_mask)))]>;
1177 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1178 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1179 "unpcklps {$src2, $dst|$dst, $src2}",
1180 [(set VR128:$dst, (v4f32 (vector_shuffle
1181 VR128:$src1, (load addr:$src2),
1182 UNPCKL_shuffle_mask)))]>;
1183 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1184 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1185 "unpcklpd {$src2, $dst|$dst, $src2}",
1186 [(set VR128:$dst, (v2f64 (vector_shuffle
1187 VR128:$src1, VR128:$src2,
1188 UNPCKL_shuffle_mask)))]>;
1189 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1190 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1191 "unpcklpd {$src2, $dst|$dst, $src2}",
1192 [(set VR128:$dst, (v2f64 (vector_shuffle
1193 VR128:$src1, (load addr:$src2),
1194 UNPCKL_shuffle_mask)))]>;
1195 } // AddedComplexity
1200 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
1201 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1202 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1203 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
1204 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
1205 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1206 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1207 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
1208 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
1209 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1210 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1211 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
1212 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
1213 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1214 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1215 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
1217 let isTwoAddress = 1 in {
1218 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
1219 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
1220 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
1221 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
1222 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
1223 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
1224 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
1225 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
1228 //===----------------------------------------------------------------------===//
1229 // SSE integer instructions
1230 //===----------------------------------------------------------------------===//
1232 // Move Instructions
1233 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1234 "movdqa {$src, $dst|$dst, $src}", []>;
1235 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1236 "movdqa {$src, $dst|$dst, $src}",
1237 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1238 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1239 "movdqa {$src, $dst|$dst, $src}",
1240 [(store (v2i64 VR128:$src), addr:$dst)]>;
1241 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1242 "movdqu {$src, $dst|$dst, $src}",
1243 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1244 XS, Requires<[HasSSE2]>;
1245 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1246 "movdqu {$src, $dst|$dst, $src}",
1247 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1248 XS, Requires<[HasSSE2]>;
1249 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1250 "lddqu {$src, $dst|$dst, $src}",
1251 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
1254 let isTwoAddress = 1 in {
1255 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1256 bit Commutable = 0> {
1257 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1258 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1259 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1260 let isCommutable = Commutable;
1262 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1263 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1264 [(set VR128:$dst, (IntId VR128:$src1,
1265 (bitconvert (loadv2i64 addr:$src2))))]>;
1269 let isTwoAddress = 1 in {
1270 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1271 string OpcodeStr, Intrinsic IntId> {
1272 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1273 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1274 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1275 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1276 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1277 [(set VR128:$dst, (IntId VR128:$src1,
1278 (bitconvert (loadv2i64 addr:$src2))))]>;
1279 def ri : PDIi8<opc2, ImmForm, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1280 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1281 [(set VR128:$dst, (IntId VR128:$src1,
1282 (scalar_to_vector (i32 imm:$src2))))]>;
1287 let isTwoAddress = 1 in {
1288 /// PDI_binop_rm - Simple SSE2 binary operator.
1289 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1290 ValueType OpVT, bit Commutable = 0> {
1291 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1292 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1293 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1294 let isCommutable = Commutable;
1296 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1297 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1298 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1299 (bitconvert (loadv2i64 addr:$src2)))))]>;
1302 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1304 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1305 /// to collapse (bitconvert VT to VT) into its operand.
1307 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1308 bit Commutable = 0> {
1309 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1310 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1311 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1312 let isCommutable = Commutable;
1314 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1315 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1316 [(set VR128:$dst, (OpNode VR128:$src1,(loadv2i64 addr:$src2)))]>;
1321 // 128-bit Integer Arithmetic
1323 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1324 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1325 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1326 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1328 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1329 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1330 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1331 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1333 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1334 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1335 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1336 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1338 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1339 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1340 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1341 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1343 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1345 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1346 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1347 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1349 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1351 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1352 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1355 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1356 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1357 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1358 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1359 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1362 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1363 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1364 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1366 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1367 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1368 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1370 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1371 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1372 // PSRAQ doesn't exist in SSE[1-3].
1375 // 128-bit logical shifts.
1376 let isTwoAddress = 1 in {
1377 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1378 "pslldq {$src2, $dst|$dst, $src2}", []>;
1379 def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1380 "psrldq {$src2, $dst|$dst, $src2}", []>;
1381 // PSRADQri doesn't exist in SSE[1-3].
1384 let Predicates = [HasSSE2] in {
1385 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1386 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1387 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1388 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1392 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1393 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1394 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1396 let isTwoAddress = 1 in {
1397 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1398 "pandn {$src2, $dst|$dst, $src2}",
1399 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1402 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1403 "pandn {$src2, $dst|$dst, $src2}",
1404 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1405 (load addr:$src2))))]>;
1408 // SSE2 Integer comparison
1409 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1410 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1411 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1412 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1413 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1414 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1416 // Pack instructions
1417 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1418 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1419 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1421 // Shuffle and unpack instructions
1422 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1423 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1424 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1425 [(set VR128:$dst, (v4i32 (vector_shuffle
1426 VR128:$src1, (undef),
1427 PSHUFD_shuffle_mask:$src2)))]>;
1428 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1429 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1430 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1431 [(set VR128:$dst, (v4i32 (vector_shuffle
1432 (bc_v4i32(loadv2i64 addr:$src1)),
1434 PSHUFD_shuffle_mask:$src2)))]>;
1436 // SSE2 with ImmT == Imm8 and XS prefix.
1437 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1438 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1439 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1440 [(set VR128:$dst, (v8i16 (vector_shuffle
1441 VR128:$src1, (undef),
1442 PSHUFHW_shuffle_mask:$src2)))]>,
1443 XS, Requires<[HasSSE2]>;
1444 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1445 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1446 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1447 [(set VR128:$dst, (v8i16 (vector_shuffle
1448 (bc_v8i16 (loadv2i64 addr:$src1)),
1450 PSHUFHW_shuffle_mask:$src2)))]>,
1451 XS, Requires<[HasSSE2]>;
1453 // SSE2 with ImmT == Imm8 and XD prefix.
1454 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1455 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1456 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1457 [(set VR128:$dst, (v8i16 (vector_shuffle
1458 VR128:$src1, (undef),
1459 PSHUFLW_shuffle_mask:$src2)))]>,
1460 XD, Requires<[HasSSE2]>;
1461 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1462 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1463 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1464 [(set VR128:$dst, (v8i16 (vector_shuffle
1465 (bc_v8i16 (loadv2i64 addr:$src1)),
1467 PSHUFLW_shuffle_mask:$src2)))]>,
1468 XD, Requires<[HasSSE2]>;
1470 let isTwoAddress = 1 in {
1471 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1472 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1473 "punpcklbw {$src2, $dst|$dst, $src2}",
1475 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1476 UNPCKL_shuffle_mask)))]>;
1477 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1478 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1479 "punpcklbw {$src2, $dst|$dst, $src2}",
1481 (v16i8 (vector_shuffle VR128:$src1,
1482 (bc_v16i8 (loadv2i64 addr:$src2)),
1483 UNPCKL_shuffle_mask)))]>;
1484 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1485 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1486 "punpcklwd {$src2, $dst|$dst, $src2}",
1488 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1489 UNPCKL_shuffle_mask)))]>;
1490 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1491 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1492 "punpcklwd {$src2, $dst|$dst, $src2}",
1494 (v8i16 (vector_shuffle VR128:$src1,
1495 (bc_v8i16 (loadv2i64 addr:$src2)),
1496 UNPCKL_shuffle_mask)))]>;
1497 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1498 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1499 "punpckldq {$src2, $dst|$dst, $src2}",
1501 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1502 UNPCKL_shuffle_mask)))]>;
1503 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1504 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1505 "punpckldq {$src2, $dst|$dst, $src2}",
1507 (v4i32 (vector_shuffle VR128:$src1,
1508 (bc_v4i32 (loadv2i64 addr:$src2)),
1509 UNPCKL_shuffle_mask)))]>;
1510 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1511 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1512 "punpcklqdq {$src2, $dst|$dst, $src2}",
1514 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1515 UNPCKL_shuffle_mask)))]>;
1516 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1517 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1518 "punpcklqdq {$src2, $dst|$dst, $src2}",
1520 (v2i64 (vector_shuffle VR128:$src1,
1521 (loadv2i64 addr:$src2),
1522 UNPCKL_shuffle_mask)))]>;
1524 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1525 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1526 "punpckhbw {$src2, $dst|$dst, $src2}",
1528 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1529 UNPCKH_shuffle_mask)))]>;
1530 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1531 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1532 "punpckhbw {$src2, $dst|$dst, $src2}",
1534 (v16i8 (vector_shuffle VR128:$src1,
1535 (bc_v16i8 (loadv2i64 addr:$src2)),
1536 UNPCKH_shuffle_mask)))]>;
1537 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1538 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1539 "punpckhwd {$src2, $dst|$dst, $src2}",
1541 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1542 UNPCKH_shuffle_mask)))]>;
1543 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1544 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1545 "punpckhwd {$src2, $dst|$dst, $src2}",
1547 (v8i16 (vector_shuffle VR128:$src1,
1548 (bc_v8i16 (loadv2i64 addr:$src2)),
1549 UNPCKH_shuffle_mask)))]>;
1550 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1551 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1552 "punpckhdq {$src2, $dst|$dst, $src2}",
1554 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1555 UNPCKH_shuffle_mask)))]>;
1556 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1557 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1558 "punpckhdq {$src2, $dst|$dst, $src2}",
1560 (v4i32 (vector_shuffle VR128:$src1,
1561 (bc_v4i32 (loadv2i64 addr:$src2)),
1562 UNPCKH_shuffle_mask)))]>;
1563 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1564 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1565 "punpckhqdq {$src2, $dst|$dst, $src2}",
1567 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1568 UNPCKH_shuffle_mask)))]>;
1569 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1570 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1571 "punpckhqdq {$src2, $dst|$dst, $src2}",
1573 (v2i64 (vector_shuffle VR128:$src1,
1574 (loadv2i64 addr:$src2),
1575 UNPCKH_shuffle_mask)))]>;
1579 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
1580 (ops GR32:$dst, VR128:$src1, i32i8imm:$src2),
1581 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1582 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
1583 (iPTR imm:$src2)))]>;
1584 let isTwoAddress = 1 in {
1585 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
1586 (ops VR128:$dst, VR128:$src1, GR32:$src2, i32i8imm:$src3),
1587 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1588 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1589 GR32:$src2, (iPTR imm:$src3))))]>;
1590 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
1591 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
1592 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1594 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1595 (i32 (anyext (loadi16 addr:$src2))),
1596 (iPTR imm:$src3))))]>;
1599 //===----------------------------------------------------------------------===//
1600 // Miscellaneous Instructions
1601 //===----------------------------------------------------------------------===//
1604 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1605 "movmskps {$src, $dst|$dst, $src}",
1606 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1607 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1608 "movmskpd {$src, $dst|$dst, $src}",
1609 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1611 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1612 "pmovmskb {$src, $dst|$dst, $src}",
1613 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1615 // Conditional store
1616 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (ops VR128:$src, VR128:$mask),
1617 "maskmovdqu {$mask, $src|$src, $mask}",
1618 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1621 // Prefetching loads.
1622 // TODO: no intrinsics for these?
1623 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), "prefetcht0 $src", []>;
1624 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), "prefetcht1 $src", []>;
1625 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), "prefetcht2 $src", []>;
1626 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src), "prefetchtnta $src", []>;
1628 // Non-temporal stores
1629 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1630 "movntps {$src, $dst|$dst, $src}",
1631 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1632 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1633 "movntpd {$src, $dst|$dst, $src}",
1634 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1635 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1636 "movntdq {$src, $dst|$dst, $src}",
1637 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1638 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1639 "movnti {$src, $dst|$dst, $src}",
1640 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
1641 TB, Requires<[HasSSE2]>;
1644 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
1645 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
1646 TB, Requires<[HasSSE2]>;
1648 // Load, store, and memory fence
1649 def SFENCE : PSI<0xAE, MRM7m, (ops), "sfence", [(int_x86_sse_sfence)]>;
1650 def LFENCE : I<0xAE, MRM5m, (ops),
1651 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
1652 def MFENCE : I<0xAE, MRM6m, (ops),
1653 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
1656 def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src),
1657 "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1658 def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst),
1659 "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1661 // Thread synchronization
1662 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
1663 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
1664 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
1665 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
1667 //===----------------------------------------------------------------------===//
1668 // Alias Instructions
1669 //===----------------------------------------------------------------------===//
1671 // Alias instructions that map zero vector to pxor / xorp* for sse.
1672 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1673 def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
1675 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1677 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
1678 "pcmpeqd $dst, $dst",
1679 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
1681 // FR32 / FR64 to 128-bit vector conversion.
1682 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
1683 "movss {$src, $dst|$dst, $src}",
1685 (v4f32 (scalar_to_vector FR32:$src)))]>;
1686 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1687 "movss {$src, $dst|$dst, $src}",
1689 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1690 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
1691 "movsd {$src, $dst|$dst, $src}",
1693 (v2f64 (scalar_to_vector FR64:$src)))]>;
1694 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1695 "movsd {$src, $dst|$dst, $src}",
1697 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
1699 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1700 "movd {$src, $dst|$dst, $src}",
1702 (v4i32 (scalar_to_vector GR32:$src)))]>;
1703 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1704 "movd {$src, $dst|$dst, $src}",
1706 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
1707 // SSE2 instructions with XS prefix
1708 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
1709 "movq {$src, $dst|$dst, $src}",
1711 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
1712 Requires<[HasSSE2]>;
1713 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1714 "movq {$src, $dst|$dst, $src}",
1716 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
1717 Requires<[HasSSE2]>;
1718 // FIXME: may not be able to eliminate this movss with coalescing the src and
1719 // dest register classes are different. We really want to write this pattern
1721 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1722 // (f32 FR32:$src)>;
1723 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
1724 "movss {$src, $dst|$dst, $src}",
1725 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1727 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
1728 "movss {$src, $dst|$dst, $src}",
1729 [(store (f32 (vector_extract (v4f32 VR128:$src),
1730 (iPTR 0))), addr:$dst)]>;
1731 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
1732 "movsd {$src, $dst|$dst, $src}",
1733 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
1735 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1736 "movsd {$src, $dst|$dst, $src}",
1737 [(store (f64 (vector_extract (v2f64 VR128:$src),
1738 (iPTR 0))), addr:$dst)]>;
1739 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src),
1740 "movd {$src, $dst|$dst, $src}",
1741 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
1743 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
1744 "movd {$src, $dst|$dst, $src}",
1745 [(store (i32 (vector_extract (v4i32 VR128:$src),
1746 (iPTR 0))), addr:$dst)]>;
1748 // Move to lower bits of a VR128, leaving upper bits alone.
1749 // Three operand (but two address) aliases.
1750 let isTwoAddress = 1 in {
1751 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
1752 "movss {$src2, $dst|$dst, $src2}", []>;
1753 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
1754 "movsd {$src2, $dst|$dst, $src2}", []>;
1756 let AddedComplexity = 15 in {
1757 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1758 "movss {$src2, $dst|$dst, $src2}",
1760 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1761 MOVL_shuffle_mask)))]>;
1762 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1763 "movsd {$src2, $dst|$dst, $src2}",
1765 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
1766 MOVL_shuffle_mask)))]>;
1770 // Store / copy lower 64-bits of a XMM register.
1771 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1772 "movq {$src, $dst|$dst, $src}",
1773 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
1775 // Move to lower bits of a VR128 and zeroing upper bits.
1776 // Loading from memory automatically zeroing upper bits.
1777 let AddedComplexity = 20 in {
1778 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1779 "movss {$src, $dst|$dst, $src}",
1780 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
1781 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
1782 MOVL_shuffle_mask)))]>;
1783 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1784 "movsd {$src, $dst|$dst, $src}",
1785 [(set VR128:$dst, (v2f64 (vector_shuffle immAllZerosV,
1786 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
1787 MOVL_shuffle_mask)))]>;
1789 let AddedComplexity = 15 in
1790 // movd / movq to XMM register zero-extends
1791 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1792 "movd {$src, $dst|$dst, $src}",
1793 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
1794 (v4i32 (scalar_to_vector GR32:$src)),
1795 MOVL_shuffle_mask)))]>;
1796 let AddedComplexity = 20 in
1797 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1798 "movd {$src, $dst|$dst, $src}",
1799 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
1800 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
1801 MOVL_shuffle_mask)))]>;
1802 // Moving from XMM to XMM but still clear upper 64 bits.
1803 let AddedComplexity = 15 in
1804 def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1805 "movq {$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
1807 XS, Requires<[HasSSE2]>;
1808 let AddedComplexity = 20 in
1809 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1810 "movq {$src, $dst|$dst, $src}",
1811 [(set VR128:$dst, (int_x86_sse2_movl_dq
1812 (bitconvert (loadv2i64 addr:$src))))]>,
1813 XS, Requires<[HasSSE2]>;
1815 //===----------------------------------------------------------------------===//
1816 // Non-Instruction Patterns
1817 //===----------------------------------------------------------------------===//
1819 // 128-bit vector undef's.
1820 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1821 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1822 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1823 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1824 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1826 // 128-bit vector all zero's.
1827 def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1828 def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1829 def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1830 def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1831 def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1833 // 128-bit vector all one's.
1834 def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1835 def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1836 def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1837 def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1838 def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
1840 // Store 128-bit integer vector values.
1841 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1842 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1843 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1844 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1845 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1846 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1848 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
1850 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
1851 Requires<[HasSSE2]>;
1852 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
1853 Requires<[HasSSE2]>;
1856 let Predicates = [HasSSE2] in {
1857 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
1858 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
1859 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
1860 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
1861 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
1862 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
1863 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
1864 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
1865 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
1866 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
1867 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
1868 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
1869 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
1870 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
1871 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
1872 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
1873 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
1874 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
1875 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
1876 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
1877 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
1878 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
1879 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
1880 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
1881 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
1882 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
1883 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
1884 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
1885 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
1886 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
1889 // Move scalar to XMM zero-extended
1890 // movd to XMM register zero-extends
1891 let AddedComplexity = 15 in {
1892 def : Pat<(v8i16 (vector_shuffle immAllZerosV,
1893 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
1894 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
1895 def : Pat<(v16i8 (vector_shuffle immAllZerosV,
1896 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
1897 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
1898 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
1899 def : Pat<(v2f64 (vector_shuffle immAllZerosV,
1900 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
1901 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
1902 def : Pat<(v4f32 (vector_shuffle immAllZerosV,
1903 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
1904 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
1907 // Splat v2f64 / v2i64
1908 let AddedComplexity = 10 in {
1909 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
1910 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1911 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
1912 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1913 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
1914 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1915 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
1916 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1920 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
1921 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
1922 Requires<[HasSSE1]>;
1924 // Special unary SHUFPSrri case.
1925 // FIXME: when we want non two-address code, then we should use PSHUFD?
1926 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
1927 SHUFP_unary_shuffle_mask:$sm),
1928 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
1929 Requires<[HasSSE1]>;
1930 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
1931 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
1932 SHUFP_unary_shuffle_mask:$sm),
1933 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
1934 Requires<[HasSSE2]>;
1935 // Special binary v4i32 shuffle cases with SHUFPS.
1936 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
1937 PSHUFD_binary_shuffle_mask:$sm),
1938 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
1939 Requires<[HasSSE2]>;
1940 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
1941 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
1942 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
1943 Requires<[HasSSE2]>;
1945 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
1946 let AddedComplexity = 10 in {
1947 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
1948 UNPCKL_v_undef_shuffle_mask)),
1949 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1950 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
1951 UNPCKL_v_undef_shuffle_mask)),
1952 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1953 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
1954 UNPCKL_v_undef_shuffle_mask)),
1955 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1956 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1957 UNPCKL_v_undef_shuffle_mask)),
1958 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
1961 let AddedComplexity = 15 in
1962 // vector_shuffle v1, <undef> <1, 1, 3, 3>
1963 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1964 MOVSHDUP_shuffle_mask)),
1965 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
1966 let AddedComplexity = 20 in
1967 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
1968 MOVSHDUP_shuffle_mask)),
1969 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
1971 // vector_shuffle v1, <undef> <0, 0, 2, 2>
1972 let AddedComplexity = 15 in
1973 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1974 MOVSLDUP_shuffle_mask)),
1975 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
1976 let AddedComplexity = 20 in
1977 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
1978 MOVSLDUP_shuffle_mask)),
1979 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
1981 let AddedComplexity = 15 in {
1982 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1983 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1984 MOVHP_shuffle_mask)),
1985 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1987 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1988 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1989 MOVHLPS_shuffle_mask)),
1990 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1992 // vector_shuffle v1, undef <2, 3, ?, ?> using MOVHLPS
1993 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
1994 UNPCKH_shuffle_mask)),
1995 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1996 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
1997 UNPCKH_shuffle_mask)),
1998 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2001 let AddedComplexity = 20 in {
2002 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2003 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2004 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2005 MOVLP_shuffle_mask)),
2006 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2007 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2008 MOVLP_shuffle_mask)),
2009 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2010 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2011 MOVHP_shuffle_mask)),
2012 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2013 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2014 MOVHP_shuffle_mask)),
2015 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2017 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2018 MOVLP_shuffle_mask)),
2019 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2020 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2021 MOVLP_shuffle_mask)),
2022 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2023 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2024 MOVHP_shuffle_mask)),
2025 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2026 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2027 MOVLP_shuffle_mask)),
2028 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2031 let AddedComplexity = 15 in {
2032 // Setting the lowest element in the vector.
2033 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2034 MOVL_shuffle_mask)),
2035 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2036 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2037 MOVL_shuffle_mask)),
2038 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2040 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2041 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2042 MOVLP_shuffle_mask)),
2043 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2044 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2045 MOVLP_shuffle_mask)),
2046 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2049 // Set lowest element and zero upper elements.
2050 let AddedComplexity = 20 in
2051 def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2052 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2053 MOVL_shuffle_mask)),
2054 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2056 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2057 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2058 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2059 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2060 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2061 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2062 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2063 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2064 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2065 Requires<[HasSSE2]>;
2066 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2067 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2068 Requires<[HasSSE2]>;
2069 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2070 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2071 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2072 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2073 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2074 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2075 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2076 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2077 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2078 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2079 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2080 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2081 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2082 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2083 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2084 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2086 // Some special case pandn patterns.
2087 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2089 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2090 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2092 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2093 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2095 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2097 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2098 (load addr:$src2))),
2099 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2100 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2101 (load addr:$src2))),
2102 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2103 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2104 (load addr:$src2))),
2105 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2108 def : Pat<(v4f32 (X86loadu addr:$src)), (MOVUPSrm addr:$src)>,
2109 Requires<[HasSSE1]>;