1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
22 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
23 [SDNPCommutative, SDNPAssociative]>;
24 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
25 [SDNPCommutative, SDNPAssociative]>;
26 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
28 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
30 def X86s2vec : SDNode<"X86ISD::S2VEC",
31 SDTypeProfile<1, 1, []>, []>;
32 def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
33 SDTypeProfile<1, 1, []>, []>;
34 def X86pextrw : SDNode<"X86ISD::PEXTRW",
35 SDTypeProfile<1, 2, []>, []>;
36 def X86pinsrw : SDNode<"X86ISD::PINSRW",
37 SDTypeProfile<1, 3, []>, []>;
39 //===----------------------------------------------------------------------===//
40 // SSE pattern fragments
41 //===----------------------------------------------------------------------===//
43 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
44 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
46 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
47 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
48 def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
49 def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
50 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
51 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
53 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
54 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
55 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
56 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
57 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
58 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
60 def fp32imm0 : PatLeaf<(f32 fpimm), [{
61 return N->isExactlyValue(+0.0);
64 def PSxLDQ_imm : SDNodeXForm<imm, [{
65 // Transformation function: imm >> 3
66 return getI32Imm(N->getValue() >> 3);
69 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
71 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
72 return getI8Imm(X86::getShuffleSHUFImmediate(N));
75 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
77 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
78 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
81 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
83 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
84 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
87 def SSE_splat_mask : PatLeaf<(build_vector), [{
88 return X86::isSplatMask(N);
89 }], SHUFFLE_get_shuf_imm>;
91 def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
92 return X86::isMOVLHPSMask(N);
95 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
96 return X86::isMOVHLPSMask(N);
99 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
100 return X86::isMOVHPMask(N);
103 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
104 return X86::isMOVLPMask(N);
107 def MOVS_shuffle_mask : PatLeaf<(build_vector), [{
108 return X86::isMOVSMask(N);
111 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
112 return X86::isUNPCKLMask(N);
115 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
116 return X86::isUNPCKHMask(N);
119 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
120 return X86::isUNPCKL_v_undef_Mask(N);
123 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
124 return X86::isPSHUFDMask(N);
125 }], SHUFFLE_get_shuf_imm>;
127 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
128 return X86::isPSHUFHWMask(N);
129 }], SHUFFLE_get_pshufhw_imm>;
131 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
132 return X86::isPSHUFLWMask(N);
133 }], SHUFFLE_get_pshuflw_imm>;
135 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isPSHUFDMask(N);
137 }], SHUFFLE_get_shuf_imm>;
139 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isSHUFPMask(N);
141 }], SHUFFLE_get_shuf_imm>;
143 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isSHUFPMask(N);
145 }], SHUFFLE_get_shuf_imm>;
147 //===----------------------------------------------------------------------===//
148 // SSE scalar FP Instructions
149 //===----------------------------------------------------------------------===//
151 // Instruction templates
152 // SSI - SSE1 instructions with XS prefix.
153 // SDI - SSE2 instructions with XD prefix.
154 // PSI - SSE1 instructions with TB prefix.
155 // PDI - SSE2 instructions with TB and OpSize prefixes.
156 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
157 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
158 // S3SI - SSE3 instructions with XD prefix.
159 // S3DI - SSE3 instructions with TB and OpSize prefixes.
160 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
161 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
162 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
163 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
164 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
165 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
166 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
167 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
168 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
169 : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasSSE1]> {
170 let Pattern = pattern;
172 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
173 : X86Inst<o, F, Imm8, ops, asm>, TB, OpSize, Requires<[HasSSE2]> {
174 let Pattern = pattern;
176 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
177 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
178 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
179 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
181 //===----------------------------------------------------------------------===//
182 // Helpers for defining instructions that directly correspond to intrinsics.
183 class SS_Intr<bits<8> o, string asm, Intrinsic IntId>
184 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
185 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
186 class SS_Intm<bits<8> o, string asm, Intrinsic IntId>
187 : SSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
188 [(set VR128:$dst, (v4f32 (IntId (load addr:$src))))]>;
189 class SD_Intr<bits<8> o, string asm, Intrinsic IntId>
190 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
191 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
192 class SD_Intm<bits<8> o, string asm, Intrinsic IntId>
193 : SDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
194 [(set VR128:$dst, (v2f64 (IntId (load addr:$src))))]>;
196 class SS_Intrr<bits<8> o, string asm, Intrinsic IntId>
197 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
198 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
199 class SS_Intrm<bits<8> o, string asm, Intrinsic IntId>
200 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
201 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
202 class SD_Intrr<bits<8> o, string asm, Intrinsic IntId>
203 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
204 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
205 class SD_Intrm<bits<8> o, string asm, Intrinsic IntId>
206 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
207 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
209 class PS_Intr<bits<8> o, string asm, Intrinsic IntId>
210 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
211 [(set VR128:$dst, (IntId VR128:$src))]>;
212 class PS_Intm<bits<8> o, string asm, Intrinsic IntId>
213 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
214 [(set VR128:$dst, (IntId (loadv4f32 addr:$src)))]>;
215 class PD_Intr<bits<8> o, string asm, Intrinsic IntId>
216 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
217 [(set VR128:$dst, (IntId VR128:$src))]>;
218 class PD_Intm<bits<8> o, string asm, Intrinsic IntId>
219 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
220 [(set VR128:$dst, (IntId (loadv2f64 addr:$src)))]>;
222 class PS_Intrr<bits<8> o, string asm, Intrinsic IntId>
223 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
224 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
225 class PS_Intrm<bits<8> o, string asm, Intrinsic IntId>
226 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
227 [(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))]>;
228 class PD_Intrr<bits<8> o, string asm, Intrinsic IntId>
229 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
230 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
231 class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
232 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
233 [(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
235 class S3S_Intrr<bits<8> o, string asm, Intrinsic IntId>
236 : S3SI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
237 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
238 class S3S_Intrm<bits<8> o, string asm, Intrinsic IntId>
239 : S3SI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
240 [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
241 (loadv4f32 addr:$src2))))]>;
242 class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
243 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
244 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
245 class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
246 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
247 [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
248 (loadv2f64 addr:$src2))))]>;
250 // Some 'special' instructions
251 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
252 "#IMPLICIT_DEF $dst",
253 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
254 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
255 "#IMPLICIT_DEF $dst",
256 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
258 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
259 // scheduler into a branch sequence.
260 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
261 def CMOV_FR32 : I<0, Pseudo,
262 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
263 "#CMOV_FR32 PSEUDO!",
264 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
265 def CMOV_FR64 : I<0, Pseudo,
266 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
267 "#CMOV_FR64 PSEUDO!",
268 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
269 def CMOV_V4F32 : I<0, Pseudo,
270 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
271 "#CMOV_V4F32 PSEUDO!",
273 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
274 def CMOV_V2F64 : I<0, Pseudo,
275 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
276 "#CMOV_V2F64 PSEUDO!",
278 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
279 def CMOV_V2I64 : I<0, Pseudo,
280 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
281 "#CMOV_V2I64 PSEUDO!",
283 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
287 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
288 "movss {$src, $dst|$dst, $src}", []>;
289 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
290 "movss {$src, $dst|$dst, $src}",
291 [(set FR32:$dst, (loadf32 addr:$src))]>;
292 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
293 "movsd {$src, $dst|$dst, $src}", []>;
294 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
295 "movsd {$src, $dst|$dst, $src}",
296 [(set FR64:$dst, (loadf64 addr:$src))]>;
298 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
299 "movss {$src, $dst|$dst, $src}",
300 [(store FR32:$src, addr:$dst)]>;
301 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
302 "movsd {$src, $dst|$dst, $src}",
303 [(store FR64:$src, addr:$dst)]>;
305 // Arithmetic instructions
306 let isTwoAddress = 1 in {
307 let isCommutable = 1 in {
308 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
309 "addss {$src2, $dst|$dst, $src2}",
310 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
311 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
312 "addsd {$src2, $dst|$dst, $src2}",
313 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
314 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
315 "mulss {$src2, $dst|$dst, $src2}",
316 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
317 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
318 "mulsd {$src2, $dst|$dst, $src2}",
319 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
322 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
323 "addss {$src2, $dst|$dst, $src2}",
324 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
325 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
326 "addsd {$src2, $dst|$dst, $src2}",
327 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
328 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
329 "mulss {$src2, $dst|$dst, $src2}",
330 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
331 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
332 "mulsd {$src2, $dst|$dst, $src2}",
333 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
335 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
336 "divss {$src2, $dst|$dst, $src2}",
337 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
338 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
339 "divss {$src2, $dst|$dst, $src2}",
340 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
341 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
342 "divsd {$src2, $dst|$dst, $src2}",
343 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
344 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
345 "divsd {$src2, $dst|$dst, $src2}",
346 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
348 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
349 "subss {$src2, $dst|$dst, $src2}",
350 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
351 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
352 "subss {$src2, $dst|$dst, $src2}",
353 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
354 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
355 "subsd {$src2, $dst|$dst, $src2}",
356 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
357 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
358 "subsd {$src2, $dst|$dst, $src2}",
359 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
362 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
363 "sqrtss {$src, $dst|$dst, $src}",
364 [(set FR32:$dst, (fsqrt FR32:$src))]>;
365 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
366 "sqrtss {$src, $dst|$dst, $src}",
367 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
368 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
369 "sqrtsd {$src, $dst|$dst, $src}",
370 [(set FR64:$dst, (fsqrt FR64:$src))]>;
371 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
372 "sqrtsd {$src, $dst|$dst, $src}",
373 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
375 def RSQRTSSr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
376 "rsqrtss {$src, $dst|$dst, $src}", []>;
377 def RSQRTSSm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
378 "rsqrtss {$src, $dst|$dst, $src}", []>;
379 def RCPSSr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
380 "rcpss {$src, $dst|$dst, $src}", []>;
381 def RCPSSm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
382 "rcpss {$src, $dst|$dst, $src}", []>;
384 let isTwoAddress = 1 in {
385 def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
386 "maxss {$src2, $dst|$dst, $src2}", []>;
387 def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
388 "maxss {$src2, $dst|$dst, $src2}", []>;
389 def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
390 "maxsd {$src2, $dst|$dst, $src2}", []>;
391 def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
392 "maxsd {$src2, $dst|$dst, $src2}", []>;
393 def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
394 "minss {$src2, $dst|$dst, $src2}", []>;
395 def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
396 "minss {$src2, $dst|$dst, $src2}", []>;
397 def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
398 "minsd {$src2, $dst|$dst, $src2}", []>;
399 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
400 "minsd {$src2, $dst|$dst, $src2}", []>;
403 // Aliases to match intrinsics which expect XMM operand(s).
404 let isTwoAddress = 1 in {
405 let isCommutable = 1 in {
406 def Int_ADDSSrr : SS_Intrr<0x58, "addss {$src2, $dst|$dst, $src2}",
408 def Int_ADDSDrr : SD_Intrr<0x58, "addsd {$src2, $dst|$dst, $src2}",
409 int_x86_sse2_add_sd>;
410 def Int_MULSSrr : SS_Intrr<0x59, "mulss {$src2, $dst|$dst, $src2}",
412 def Int_MULSDrr : SD_Intrr<0x59, "mulsd {$src2, $dst|$dst, $src2}",
413 int_x86_sse2_mul_sd>;
416 def Int_ADDSSrm : SS_Intrm<0x58, "addss {$src2, $dst|$dst, $src2}",
418 def Int_ADDSDrm : SD_Intrm<0x58, "addsd {$src2, $dst|$dst, $src2}",
419 int_x86_sse2_add_sd>;
420 def Int_MULSSrm : SS_Intrm<0x59, "mulss {$src2, $dst|$dst, $src2}",
422 def Int_MULSDrm : SD_Intrm<0x59, "mulsd {$src2, $dst|$dst, $src2}",
423 int_x86_sse2_mul_sd>;
425 def Int_DIVSSrr : SS_Intrr<0x5E, "divss {$src2, $dst|$dst, $src2}",
427 def Int_DIVSSrm : SS_Intrm<0x5E, "divss {$src2, $dst|$dst, $src2}",
429 def Int_DIVSDrr : SD_Intrr<0x5E, "divsd {$src2, $dst|$dst, $src2}",
430 int_x86_sse2_div_sd>;
431 def Int_DIVSDrm : SD_Intrm<0x5E, "divsd {$src2, $dst|$dst, $src2}",
432 int_x86_sse2_div_sd>;
434 def Int_SUBSSrr : SS_Intrr<0x5C, "subss {$src2, $dst|$dst, $src2}",
436 def Int_SUBSSrm : SS_Intrm<0x5C, "subss {$src2, $dst|$dst, $src2}",
438 def Int_SUBSDrr : SD_Intrr<0x5C, "subsd {$src2, $dst|$dst, $src2}",
439 int_x86_sse2_sub_sd>;
440 def Int_SUBSDrm : SD_Intrm<0x5C, "subsd {$src2, $dst|$dst, $src2}",
441 int_x86_sse2_sub_sd>;
444 def Int_SQRTSSr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}",
445 int_x86_sse_sqrt_ss>;
446 def Int_SQRTSSm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}",
447 int_x86_sse_sqrt_ss>;
448 def Int_SQRTSDr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}",
449 int_x86_sse2_sqrt_sd>;
450 def Int_SQRTSDm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}",
451 int_x86_sse2_sqrt_sd>;
453 def Int_RSQRTSSr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}",
454 int_x86_sse_rsqrt_ss>;
455 def Int_RSQRTSSm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}",
456 int_x86_sse_rsqrt_ss>;
457 def Int_RCPSSr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}",
459 def Int_RCPSSm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}",
462 let isTwoAddress = 1 in {
463 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}",
465 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}",
467 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
468 int_x86_sse2_max_sd>;
469 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
470 int_x86_sse2_max_sd>;
471 def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}",
473 def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}",
475 def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}",
476 int_x86_sse2_min_sd>;
477 def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}",
478 int_x86_sse2_min_sd>;
481 // Conversion instructions
482 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
483 "cvttss2si {$src, $dst|$dst, $src}",
484 [(set R32:$dst, (fp_to_sint FR32:$src))]>;
485 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
486 "cvttss2si {$src, $dst|$dst, $src}",
487 [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
488 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
489 "cvttsd2si {$src, $dst|$dst, $src}",
490 [(set R32:$dst, (fp_to_sint FR64:$src))]>;
491 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
492 "cvttsd2si {$src, $dst|$dst, $src}",
493 [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
494 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
495 "cvtsd2ss {$src, $dst|$dst, $src}",
496 [(set FR32:$dst, (fround FR64:$src))]>;
497 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
498 "cvtsd2ss {$src, $dst|$dst, $src}",
499 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
500 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
501 "cvtsi2ss {$src, $dst|$dst, $src}",
502 [(set FR32:$dst, (sint_to_fp R32:$src))]>;
503 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
504 "cvtsi2ss {$src, $dst|$dst, $src}",
505 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
506 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
507 "cvtsi2sd {$src, $dst|$dst, $src}",
508 [(set FR64:$dst, (sint_to_fp R32:$src))]>;
509 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
510 "cvtsi2sd {$src, $dst|$dst, $src}",
511 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
513 // SSE2 instructions with XS prefix
514 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
515 "cvtss2sd {$src, $dst|$dst, $src}",
516 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
518 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
519 "cvtss2sd {$src, $dst|$dst, $src}",
520 [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
523 // Match intrinsics which expect XMM operand(s).
524 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
525 "cvtss2si {$src, $dst|$dst, $src}",
526 [(set R32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
527 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
528 "cvtss2si {$src, $dst|$dst, $src}",
529 [(set R32:$dst, (int_x86_sse_cvtss2si
530 (loadv4f32 addr:$src)))]>;
532 // Aliases for intrinsics
533 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
534 "cvttss2si {$src, $dst|$dst, $src}",
535 [(set R32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
536 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
537 "cvttss2si {$src, $dst|$dst, $src}",
538 [(set R32:$dst, (int_x86_sse_cvttss2si
539 (loadv4f32 addr:$src)))]>;
540 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
541 "cvttsd2si {$src, $dst|$dst, $src}",
542 [(set R32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
543 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
544 "cvttsd2si {$src, $dst|$dst, $src}",
545 [(set R32:$dst, (int_x86_sse2_cvttsd2si
546 (loadv2f64 addr:$src)))]>;
548 let isTwoAddress = 1 in {
549 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
550 (ops VR128:$dst, VR128:$src1, R32:$src2),
551 "cvtsi2ss {$src2, $dst|$dst, $src2}",
552 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
554 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
555 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
556 "cvtsi2ss {$src2, $dst|$dst, $src2}",
557 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
558 (loadi32 addr:$src2)))]>;
561 // Comparison instructions
562 let isTwoAddress = 1 in {
563 def CMPSSrr : SSI<0xC2, MRMSrcReg,
564 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
565 "cmp${cc}ss {$src, $dst|$dst, $src}",
567 def CMPSSrm : SSI<0xC2, MRMSrcMem,
568 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
569 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
570 def CMPSDrr : SDI<0xC2, MRMSrcReg,
571 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
572 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
573 def CMPSDrm : SDI<0xC2, MRMSrcMem,
574 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
575 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
578 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
579 "ucomiss {$src2, $src1|$src1, $src2}",
580 [(X86cmp FR32:$src1, FR32:$src2)]>;
581 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
582 "ucomiss {$src2, $src1|$src1, $src2}",
583 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
584 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
585 "ucomisd {$src2, $src1|$src1, $src2}",
586 [(X86cmp FR64:$src1, FR64:$src2)]>;
587 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
588 "ucomisd {$src2, $src1|$src1, $src2}",
589 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
591 // Aliases to match intrinsics which expect XMM operand(s).
592 let isTwoAddress = 1 in {
593 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
594 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
595 "cmp${cc}ss {$src, $dst|$dst, $src}",
596 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
597 VR128:$src, imm:$cc))]>;
598 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
599 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
600 "cmp${cc}ss {$src, $dst|$dst, $src}",
601 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
602 (load addr:$src), imm:$cc))]>;
603 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
604 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
605 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
606 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
607 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
608 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
611 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
612 "ucomiss {$src2, $src1|$src1, $src2}",
613 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
614 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
615 "ucomiss {$src2, $src1|$src1, $src2}",
616 [(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
617 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
618 "ucomisd {$src2, $src1|$src1, $src2}",
619 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
620 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
621 "ucomisd {$src2, $src1|$src1, $src2}",
622 [(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
624 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
625 "comiss {$src2, $src1|$src1, $src2}",
626 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
627 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
628 "comiss {$src2, $src1|$src1, $src2}",
629 [(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
630 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
631 "comisd {$src2, $src1|$src1, $src2}",
632 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
633 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
634 "comisd {$src2, $src1|$src1, $src2}",
635 [(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
637 // Aliases of packed instructions for scalar use. These all have names that
640 // Alias instructions that map fld0 to pxor for sse.
641 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
642 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
643 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
644 Requires<[HasSSE1]>, TB, OpSize;
645 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
646 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
647 Requires<[HasSSE2]>, TB, OpSize;
649 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
650 // Upper bits are disregarded.
651 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
652 "movaps {$src, $dst|$dst, $src}", []>;
653 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
654 "movapd {$src, $dst|$dst, $src}", []>;
656 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
657 // Upper bits are disregarded.
658 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
659 "movaps {$src, $dst|$dst, $src}",
660 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
661 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
662 "movapd {$src, $dst|$dst, $src}",
663 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
665 // Alias bitwise logical operations using SSE logical ops on packed FP values.
666 let isTwoAddress = 1 in {
667 let isCommutable = 1 in {
668 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
669 "andps {$src2, $dst|$dst, $src2}",
670 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
671 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
672 "andpd {$src2, $dst|$dst, $src2}",
673 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
674 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
675 "orps {$src2, $dst|$dst, $src2}", []>;
676 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
677 "orpd {$src2, $dst|$dst, $src2}", []>;
678 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
679 "xorps {$src2, $dst|$dst, $src2}",
680 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
681 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
682 "xorpd {$src2, $dst|$dst, $src2}",
683 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
685 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
686 "andps {$src2, $dst|$dst, $src2}",
687 [(set FR32:$dst, (X86fand FR32:$src1,
688 (X86loadpf32 addr:$src2)))]>;
689 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
690 "andpd {$src2, $dst|$dst, $src2}",
691 [(set FR64:$dst, (X86fand FR64:$src1,
692 (X86loadpf64 addr:$src2)))]>;
693 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
694 "orps {$src2, $dst|$dst, $src2}", []>;
695 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
696 "orpd {$src2, $dst|$dst, $src2}", []>;
697 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
698 "xorps {$src2, $dst|$dst, $src2}",
699 [(set FR32:$dst, (X86fxor FR32:$src1,
700 (X86loadpf32 addr:$src2)))]>;
701 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
702 "xorpd {$src2, $dst|$dst, $src2}",
703 [(set FR64:$dst, (X86fxor FR64:$src1,
704 (X86loadpf64 addr:$src2)))]>;
706 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
707 "andnps {$src2, $dst|$dst, $src2}", []>;
708 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
709 "andnps {$src2, $dst|$dst, $src2}", []>;
710 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
711 "andnpd {$src2, $dst|$dst, $src2}", []>;
712 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
713 "andnpd {$src2, $dst|$dst, $src2}", []>;
716 //===----------------------------------------------------------------------===//
717 // SSE packed FP Instructions
718 //===----------------------------------------------------------------------===//
720 // Some 'special' instructions
721 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
722 "#IMPLICIT_DEF $dst",
723 [(set VR128:$dst, (v4f32 (undef)))]>,
727 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
728 "movaps {$src, $dst|$dst, $src}", []>;
729 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
730 "movaps {$src, $dst|$dst, $src}",
731 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
732 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
733 "movapd {$src, $dst|$dst, $src}", []>;
734 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
735 "movapd {$src, $dst|$dst, $src}",
736 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
738 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
739 "movaps {$src, $dst|$dst, $src}",
740 [(store (v4f32 VR128:$src), addr:$dst)]>;
741 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
742 "movapd {$src, $dst|$dst, $src}",
743 [(store (v2f64 VR128:$src), addr:$dst)]>;
745 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
746 "movups {$src, $dst|$dst, $src}", []>;
747 def MOVUPSrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
748 "movups {$src, $dst|$dst, $src}",
749 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
750 def MOVUPSmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
751 "movups {$src, $dst|$dst, $src}",
752 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
753 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
754 "movupd {$src, $dst|$dst, $src}", []>;
755 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
756 "movupd {$src, $dst|$dst, $src}",
757 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
758 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
759 "movupd {$src, $dst|$dst, $src}",
760 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
761 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
762 "movdqu {$src, $dst|$dst, $src}",
763 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
764 XS, Requires<[HasSSE2]>;
765 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
766 "movdqu {$src, $dst|$dst, $src}",
767 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
768 XS, Requires<[HasSSE2]>;
770 let isTwoAddress = 1 in {
771 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
772 "movlps {$src2, $dst|$dst, $src2}",
774 (v4f32 (vector_shuffle VR128:$src1,
775 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
776 MOVLP_shuffle_mask)))]>;
777 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
778 "movlpd {$src2, $dst|$dst, $src2}",
780 (v2f64 (vector_shuffle VR128:$src1,
781 (scalar_to_vector (loadf64 addr:$src2)),
782 MOVLP_shuffle_mask)))]>;
783 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
784 "movhps {$src2, $dst|$dst, $src2}",
786 (v4f32 (vector_shuffle VR128:$src1,
787 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
788 MOVHP_shuffle_mask)))]>;
789 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
790 "movhpd {$src2, $dst|$dst, $src2}",
792 (v2f64 (vector_shuffle VR128:$src1,
793 (scalar_to_vector (loadf64 addr:$src2)),
794 MOVHP_shuffle_mask)))]>;
797 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
798 "movlps {$src, $dst|$dst, $src}",
799 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
800 (i32 0))), addr:$dst)]>;
801 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
802 "movlpd {$src, $dst|$dst, $src}",
803 [(store (f64 (vector_extract (v2f64 VR128:$src),
804 (i32 0))), addr:$dst)]>;
806 // v2f64 extract element 1 is always custom lowered to unpack high to low
807 // and extract element 0 so the non-store version isn't too horrible.
808 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
809 "movhps {$src, $dst|$dst, $src}",
810 [(store (f64 (vector_extract
811 (v2f64 (vector_shuffle
812 (bc_v2f64 (v4f32 VR128:$src)), (undef),
813 UNPCKH_shuffle_mask)), (i32 0))),
815 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
816 "movhpd {$src, $dst|$dst, $src}",
817 [(store (f64 (vector_extract
818 (v2f64 (vector_shuffle VR128:$src, (undef),
819 UNPCKH_shuffle_mask)), (i32 0))),
822 let isTwoAddress = 1 in {
823 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
824 "movlhps {$src2, $dst|$dst, $src2}",
826 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
827 MOVLHPS_shuffle_mask)))]>;
829 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
830 "movhlps {$src2, $dst|$dst, $src2}",
832 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
833 MOVHLPS_shuffle_mask)))]>;
836 // SSE2 instructions without OpSize prefix
837 def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
838 "cvtdq2ps {$src, $dst|$dst, $src}",
839 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
840 TB, Requires<[HasSSE2]>;
841 def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
842 "cvtdq2ps {$src, $dst|$dst, $src}",
843 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
844 (bc_v4i32 (loadv2i64 addr:$src))))]>,
845 TB, Requires<[HasSSE2]>;
847 // SSE2 instructions with XS prefix
848 def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
849 "cvtdq2pd {$src, $dst|$dst, $src}",
850 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
851 XS, Requires<[HasSSE2]>;
852 def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
853 "cvtdq2pd {$src, $dst|$dst, $src}",
854 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
855 (bc_v4i32 (loadv2i64 addr:$src))))]>,
856 XS, Requires<[HasSSE2]>;
858 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
859 "cvtps2dq {$src, $dst|$dst, $src}",
860 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
861 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
862 "cvtps2dq {$src, $dst|$dst, $src}",
863 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
864 (loadv4f32 addr:$src)))]>;
865 // SSE2 packed instructions with XS prefix
866 def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
867 "cvttps2dq {$src, $dst|$dst, $src}",
868 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
869 XS, Requires<[HasSSE2]>;
870 def CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
871 "cvttps2dq {$src, $dst|$dst, $src}",
872 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
873 (loadv4f32 addr:$src)))]>,
874 XS, Requires<[HasSSE2]>;
876 // SSE2 packed instructions with XD prefix
877 def CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
878 "cvtpd2dq {$src, $dst|$dst, $src}",
879 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
880 XD, Requires<[HasSSE2]>;
881 def CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
882 "cvtpd2dq {$src, $dst|$dst, $src}",
883 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
884 (loadv2f64 addr:$src)))]>,
885 XD, Requires<[HasSSE2]>;
886 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
887 "cvttpd2dq {$src, $dst|$dst, $src}",
888 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
889 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
890 "cvttpd2dq {$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
892 (loadv2f64 addr:$src)))]>;
894 // SSE2 instructions without OpSize prefix
895 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
896 "cvtps2pd {$src, $dst|$dst, $src}",
897 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
898 TB, Requires<[HasSSE2]>;
899 def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
900 "cvtps2pd {$src, $dst|$dst, $src}",
901 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
902 (loadv4f32 addr:$src)))]>,
903 TB, Requires<[HasSSE2]>;
905 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
906 "cvtpd2ps {$src, $dst|$dst, $src}",
907 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
908 def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
909 "cvtpd2ps {$src, $dst|$dst, $src}",
910 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
911 (loadv2f64 addr:$src)))]>;
914 def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
915 "cvtsd2si {$src, $dst|$dst, $src}",
916 [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
917 def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
918 "cvtsd2si {$src, $dst|$dst, $src}",
919 [(set R32:$dst, (int_x86_sse2_cvtsd2si
920 (loadv2f64 addr:$src)))]>;
922 // Match intrinsics which expect XMM operand(s).
923 // Aliases for intrinsics
924 let isTwoAddress = 1 in {
925 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
926 (ops VR128:$dst, VR128:$src1, R32:$src2),
927 "cvtsi2sd {$src2, $dst|$dst, $src2}",
928 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
930 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
931 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
932 "cvtsi2sd {$src2, $dst|$dst, $src2}",
933 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
934 (loadi32 addr:$src2)))]>;
935 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
936 (ops VR128:$dst, VR128:$src1, VR128:$src2),
937 "cvtsd2ss {$src2, $dst|$dst, $src2}",
938 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
940 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
941 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
942 "cvtsd2ss {$src2, $dst|$dst, $src2}",
943 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
944 (loadv2f64 addr:$src2)))]>;
945 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
946 (ops VR128:$dst, VR128:$src1, VR128:$src2),
947 "cvtss2sd {$src2, $dst|$dst, $src2}",
948 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
951 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
952 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
953 "cvtss2sd {$src2, $dst|$dst, $src2}",
954 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
955 (loadv4f32 addr:$src2)))]>, XS,
960 let isTwoAddress = 1 in {
961 let isCommutable = 1 in {
962 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
963 "addps {$src2, $dst|$dst, $src2}",
964 [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
965 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
966 "addpd {$src2, $dst|$dst, $src2}",
967 [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
968 def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
969 "mulps {$src2, $dst|$dst, $src2}",
970 [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
971 def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
972 "mulpd {$src2, $dst|$dst, $src2}",
973 [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
976 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
977 "addps {$src2, $dst|$dst, $src2}",
978 [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
979 (load addr:$src2))))]>;
980 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
981 "addpd {$src2, $dst|$dst, $src2}",
982 [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
983 (load addr:$src2))))]>;
984 def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
985 "mulps {$src2, $dst|$dst, $src2}",
986 [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
987 (load addr:$src2))))]>;
988 def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
989 "mulpd {$src2, $dst|$dst, $src2}",
990 [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
991 (load addr:$src2))))]>;
993 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
994 "divps {$src2, $dst|$dst, $src2}",
995 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
996 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
997 "divps {$src2, $dst|$dst, $src2}",
998 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
999 (load addr:$src2))))]>;
1000 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1001 "divpd {$src2, $dst|$dst, $src2}",
1002 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
1003 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1004 "divpd {$src2, $dst|$dst, $src2}",
1005 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
1006 (load addr:$src2))))]>;
1008 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1009 "subps {$src2, $dst|$dst, $src2}",
1010 [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
1011 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1012 "subps {$src2, $dst|$dst, $src2}",
1013 [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
1014 (load addr:$src2))))]>;
1015 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1016 "subpd {$src2, $dst|$dst, $src2}",
1017 [(set VR128:$dst, (v2f64 (fsub VR128:$src1, VR128:$src2)))]>;
1018 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1019 "subpd {$src2, $dst|$dst, $src2}",
1020 [(set VR128:$dst, (v2f64 (fsub VR128:$src1,
1021 (load addr:$src2))))]>;
1024 def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
1025 int_x86_sse_sqrt_ps>;
1026 def SQRTPSm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}",
1027 int_x86_sse_sqrt_ps>;
1028 def SQRTPDr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1029 int_x86_sse2_sqrt_pd>;
1030 def SQRTPDm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1031 int_x86_sse2_sqrt_pd>;
1033 def RSQRTPSr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1034 int_x86_sse_rsqrt_ps>;
1035 def RSQRTPSm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1036 int_x86_sse_rsqrt_ps>;
1037 def RCPPSr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}",
1038 int_x86_sse_rcp_ps>;
1039 def RCPPSm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}",
1040 int_x86_sse_rcp_ps>;
1042 let isTwoAddress = 1 in {
1043 def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1044 int_x86_sse_max_ps>;
1045 def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1046 int_x86_sse_max_ps>;
1047 def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1048 int_x86_sse2_max_pd>;
1049 def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1050 int_x86_sse2_max_pd>;
1051 def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}",
1052 int_x86_sse_min_ps>;
1053 def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}",
1054 int_x86_sse_min_ps>;
1055 def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1056 int_x86_sse2_min_pd>;
1057 def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1058 int_x86_sse2_min_pd>;
1062 let isTwoAddress = 1 in {
1063 let isCommutable = 1 in {
1064 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1065 "andps {$src2, $dst|$dst, $src2}",
1066 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1067 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1068 "andpd {$src2, $dst|$dst, $src2}",
1070 (and (bc_v2i64 (v2f64 VR128:$src1)),
1071 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1072 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1073 "orps {$src2, $dst|$dst, $src2}",
1074 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1075 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1076 "orpd {$src2, $dst|$dst, $src2}",
1078 (or (bc_v2i64 (v2f64 VR128:$src1)),
1079 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1080 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1081 "xorps {$src2, $dst|$dst, $src2}",
1082 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1083 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1084 "xorpd {$src2, $dst|$dst, $src2}",
1086 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1087 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1089 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1090 "andps {$src2, $dst|$dst, $src2}",
1091 [(set VR128:$dst, (and VR128:$src1,
1092 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1093 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1094 "andpd {$src2, $dst|$dst, $src2}",
1096 (and (bc_v2i64 (v2f64 VR128:$src1)),
1097 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1098 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1099 "orps {$src2, $dst|$dst, $src2}",
1100 [(set VR128:$dst, (or VR128:$src1,
1101 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1102 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1103 "orpd {$src2, $dst|$dst, $src2}",
1105 (or (bc_v2i64 (v2f64 VR128:$src1)),
1106 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1107 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1108 "xorps {$src2, $dst|$dst, $src2}",
1109 [(set VR128:$dst, (xor VR128:$src1,
1110 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1111 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1112 "xorpd {$src2, $dst|$dst, $src2}",
1114 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1115 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1116 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1117 "andnps {$src2, $dst|$dst, $src2}",
1118 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1119 (bc_v2i64 (v4i32 immAllOnesV))),
1121 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1122 "andnps {$src2, $dst|$dst, $src2}",
1123 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1124 (bc_v2i64 (v4i32 immAllOnesV))),
1125 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1126 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1127 "andnpd {$src2, $dst|$dst, $src2}",
1129 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1130 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1131 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1132 "andnpd {$src2, $dst|$dst, $src2}",
1134 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1135 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1138 let isTwoAddress = 1 in {
1139 def CMPPSrr : PSIi8<0xC2, MRMSrcReg,
1140 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1141 "cmp${cc}ps {$src, $dst|$dst, $src}",
1142 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1143 VR128:$src, imm:$cc))]>;
1144 def CMPPSrm : PSIi8<0xC2, MRMSrcMem,
1145 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1146 "cmp${cc}ps {$src, $dst|$dst, $src}",
1147 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1148 (load addr:$src), imm:$cc))]>;
1149 def CMPPDrr : PDIi8<0xC2, MRMSrcReg,
1150 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1151 "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
1152 def CMPPDrm : PDIi8<0xC2, MRMSrcMem,
1153 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1154 "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
1157 // Shuffle and unpack instructions
1158 let isTwoAddress = 1 in {
1159 def SHUFPSrr : PSIi8<0xC6, MRMSrcReg,
1160 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1161 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1162 [(set VR128:$dst, (v4f32 (vector_shuffle
1163 VR128:$src1, VR128:$src2,
1164 SHUFP_shuffle_mask:$src3)))]>;
1165 def SHUFPSrm : PSIi8<0xC6, MRMSrcMem,
1166 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1167 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1168 [(set VR128:$dst, (v4f32 (vector_shuffle
1169 VR128:$src1, (load addr:$src2),
1170 SHUFP_shuffle_mask:$src3)))]>;
1171 def SHUFPDrr : PDIi8<0xC6, MRMSrcReg,
1172 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1173 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1174 [(set VR128:$dst, (v2f64 (vector_shuffle
1175 VR128:$src1, VR128:$src2,
1176 SHUFP_shuffle_mask:$src3)))]>;
1177 def SHUFPDrm : PDIi8<0xC6, MRMSrcMem,
1178 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1179 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1180 [(set VR128:$dst, (v2f64 (vector_shuffle
1181 VR128:$src1, (load addr:$src2),
1182 SHUFP_shuffle_mask:$src3)))]>;
1184 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1185 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1186 "unpckhps {$src2, $dst|$dst, $src2}",
1187 [(set VR128:$dst, (v4f32 (vector_shuffle
1188 VR128:$src1, VR128:$src2,
1189 UNPCKH_shuffle_mask)))]>;
1190 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1191 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1192 "unpckhps {$src2, $dst|$dst, $src2}",
1193 [(set VR128:$dst, (v4f32 (vector_shuffle
1194 VR128:$src1, (load addr:$src2),
1195 UNPCKH_shuffle_mask)))]>;
1196 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1197 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1198 "unpckhpd {$src2, $dst|$dst, $src2}",
1199 [(set VR128:$dst, (v2f64 (vector_shuffle
1200 VR128:$src1, VR128:$src2,
1201 UNPCKH_shuffle_mask)))]>;
1202 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1203 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1204 "unpckhpd {$src2, $dst|$dst, $src2}",
1205 [(set VR128:$dst, (v2f64 (vector_shuffle
1206 VR128:$src1, (load addr:$src2),
1207 UNPCKH_shuffle_mask)))]>;
1209 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1210 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1211 "unpcklps {$src2, $dst|$dst, $src2}",
1212 [(set VR128:$dst, (v4f32 (vector_shuffle
1213 VR128:$src1, VR128:$src2,
1214 UNPCKL_shuffle_mask)))]>;
1215 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1216 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1217 "unpcklps {$src2, $dst|$dst, $src2}",
1218 [(set VR128:$dst, (v4f32 (vector_shuffle
1219 VR128:$src1, (load addr:$src2),
1220 UNPCKL_shuffle_mask)))]>;
1221 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1222 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1223 "unpcklpd {$src2, $dst|$dst, $src2}",
1224 [(set VR128:$dst, (v2f64 (vector_shuffle
1225 VR128:$src1, VR128:$src2,
1226 UNPCKL_shuffle_mask)))]>;
1227 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1228 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1229 "unpcklpd {$src2, $dst|$dst, $src2}",
1230 [(set VR128:$dst, (v2f64 (vector_shuffle
1231 VR128:$src1, (load addr:$src2),
1232 UNPCKL_shuffle_mask)))]>;
1236 let isTwoAddress = 1 in {
1237 def HADDPSrr : S3S_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1238 int_x86_sse3_hadd_ps>;
1239 def HADDPSrm : S3S_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1240 int_x86_sse3_hadd_ps>;
1241 def HADDPDrr : S3D_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1242 int_x86_sse3_hadd_pd>;
1243 def HADDPDrm : S3D_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1244 int_x86_sse3_hadd_pd>;
1245 def HSUBPSrr : S3S_Intrr<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
1246 int_x86_sse3_hsub_ps>;
1247 def HSUBPSrm : S3S_Intrm<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
1248 int_x86_sse3_hsub_ps>;
1249 def HSUBPDrr : S3D_Intrr<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
1250 int_x86_sse3_hsub_pd>;
1251 def HSUBPDrm : S3D_Intrm<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
1252 int_x86_sse3_hsub_pd>;
1255 //===----------------------------------------------------------------------===//
1256 // SSE integer instructions
1257 //===----------------------------------------------------------------------===//
1259 // Move Instructions
1260 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1261 "movdqa {$src, $dst|$dst, $src}", []>;
1262 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1263 "movdqa {$src, $dst|$dst, $src}",
1264 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1265 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1266 "movdqa {$src, $dst|$dst, $src}",
1267 [(store (v2i64 VR128:$src), addr:$dst)]>;
1269 // 128-bit Integer Arithmetic
1270 let isTwoAddress = 1 in {
1271 let isCommutable = 1 in {
1272 def PADDBrr : PDI<0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1273 "paddb {$src2, $dst|$dst, $src2}",
1274 [(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))]>;
1275 def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1276 "paddw {$src2, $dst|$dst, $src2}",
1277 [(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))]>;
1278 def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1279 "paddd {$src2, $dst|$dst, $src2}",
1280 [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
1282 def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1283 "paddq {$src2, $dst|$dst, $src2}",
1284 [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
1286 def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1287 "paddb {$src2, $dst|$dst, $src2}",
1288 [(set VR128:$dst, (v16i8 (add VR128:$src1,
1289 (load addr:$src2))))]>;
1290 def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1291 "paddw {$src2, $dst|$dst, $src2}",
1292 [(set VR128:$dst, (v8i16 (add VR128:$src1,
1293 (load addr:$src2))))]>;
1294 def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1295 "paddd {$src2, $dst|$dst, $src2}",
1296 [(set VR128:$dst, (v4i32 (add VR128:$src1,
1297 (load addr:$src2))))]>;
1298 def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1299 "paddd {$src2, $dst|$dst, $src2}",
1300 [(set VR128:$dst, (v2i64 (add VR128:$src1,
1301 (load addr:$src2))))]>;
1303 let isCommutable = 1 in {
1304 def PADDSBrr : PDI<0xEC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1305 "paddsb {$src2, $dst|$dst, $src2}",
1306 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1308 def PADDSWrr : PDI<0xED, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1309 "paddsw {$src2, $dst|$dst, $src2}",
1310 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1312 def PADDUSBrr : PDI<0xDC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1313 "paddusb {$src2, $dst|$dst, $src2}",
1314 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1316 def PADDUSWrr : PDI<0xDD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1317 "paddusw {$src2, $dst|$dst, $src2}",
1318 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1321 def PADDSBrm : PDI<0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1322 "paddsb {$src2, $dst|$dst, $src2}",
1323 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1324 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1325 def PADDSWrm : PDI<0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1326 "paddsw {$src2, $dst|$dst, $src2}",
1327 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1328 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1329 def PADDUSBrm : PDI<0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1330 "paddusb {$src2, $dst|$dst, $src2}",
1331 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1332 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1333 def PADDUSWrm : PDI<0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1334 "paddusw {$src2, $dst|$dst, $src2}",
1335 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1336 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1339 def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1340 "psubb {$src2, $dst|$dst, $src2}",
1341 [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
1342 def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1343 "psubw {$src2, $dst|$dst, $src2}",
1344 [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))]>;
1345 def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1346 "psubd {$src2, $dst|$dst, $src2}",
1347 [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
1348 def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1349 "psubq {$src2, $dst|$dst, $src2}",
1350 [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
1352 def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1353 "psubb {$src2, $dst|$dst, $src2}",
1354 [(set VR128:$dst, (v16i8 (sub VR128:$src1,
1355 (load addr:$src2))))]>;
1356 def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1357 "psubw {$src2, $dst|$dst, $src2}",
1358 [(set VR128:$dst, (v8i16 (sub VR128:$src1,
1359 (load addr:$src2))))]>;
1360 def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1361 "psubd {$src2, $dst|$dst, $src2}",
1362 [(set VR128:$dst, (v4i32 (sub VR128:$src1,
1363 (load addr:$src2))))]>;
1364 def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1365 "psubd {$src2, $dst|$dst, $src2}",
1366 [(set VR128:$dst, (v2i64 (sub VR128:$src1,
1367 (load addr:$src2))))]>;
1369 def PSUBSBrr : PDI<0xE8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1370 "psubsb {$src2, $dst|$dst, $src2}",
1371 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1373 def PSUBSWrr : PDI<0xE9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1374 "psubsw {$src2, $dst|$dst, $src2}",
1375 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1377 def PSUBUSBrr : PDI<0xD8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1378 "psubusb {$src2, $dst|$dst, $src2}",
1379 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1381 def PSUBUSWrr : PDI<0xD9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1382 "psubusw {$src2, $dst|$dst, $src2}",
1383 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1386 def PSUBSBrm : PDI<0xE8, MRMSrcMem,
1387 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1388 "psubsb {$src2, $dst|$dst, $src2}",
1389 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1390 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1391 def PSUBSWrm : PDI<0xE9, MRMSrcMem,
1392 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1393 "psubsw {$src2, $dst|$dst, $src2}",
1394 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1395 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1396 def PSUBUSBrm : PDI<0xD8, MRMSrcMem,
1397 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1398 "psubusb {$src2, $dst|$dst, $src2}",
1399 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1400 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1401 def PSUBUSWrm : PDI<0xD9, MRMSrcMem,
1402 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1403 "psubusw {$src2, $dst|$dst, $src2}",
1404 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1405 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1407 let isCommutable = 1 in {
1408 def PMULHUWrr : PDI<0xE4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1409 "pmulhuw {$src2, $dst|$dst, $src2}",
1410 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1412 def PMULHWrr : PDI<0xE5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1413 "pmulhw {$src2, $dst|$dst, $src2}",
1414 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1416 def PMULLWrr : PDI<0xD5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1417 "pmullw {$src2, $dst|$dst, $src2}",
1418 [(set VR128:$dst, (v8i16 (mul VR128:$src1, VR128:$src2)))]>;
1419 def PMULUDQrr : PDI<0xF4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1420 "pmuludq {$src2, $dst|$dst, $src2}",
1421 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1424 def PMULHUWrm : PDI<0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1425 "pmulhuw {$src2, $dst|$dst, $src2}",
1426 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1427 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1428 def PMULHWrm : PDI<0xE5, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1429 "pmulhw {$src2, $dst|$dst, $src2}",
1430 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1431 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1432 def PMULLWrm : PDI<0xD5, MRMSrcMem,
1433 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1434 "pmullw {$src2, $dst|$dst, $src2}",
1435 [(set VR128:$dst, (v8i16 (mul VR128:$src1,
1436 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1437 def PMULUDQrm : PDI<0xF4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1438 "pmuludq {$src2, $dst|$dst, $src2}",
1439 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1440 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1442 let isCommutable = 1 in {
1443 def PMADDWDrr : PDI<0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1444 "pmaddwd {$src2, $dst|$dst, $src2}",
1445 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1448 def PMADDWDrm : PDI<0xF5, MRMSrcMem,
1449 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1450 "pmaddwd {$src2, $dst|$dst, $src2}",
1451 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1452 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1454 let isCommutable = 1 in {
1455 def PAVGBrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1456 "pavgb {$src2, $dst|$dst, $src2}",
1457 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1459 def PAVGWrr : PDI<0xE3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1460 "pavgw {$src2, $dst|$dst, $src2}",
1461 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1464 def PAVGBrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1465 "pavgb {$src2, $dst|$dst, $src2}",
1466 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1467 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1468 def PAVGWrm : PDI<0xE3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1469 "pavgw {$src2, $dst|$dst, $src2}",
1470 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1471 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1473 let isCommutable = 1 in {
1474 def PMAXUBrr : PDI<0xDE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1475 "pmaxub {$src2, $dst|$dst, $src2}",
1476 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1478 def PMAXSWrr : PDI<0xEE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1479 "pmaxsw {$src2, $dst|$dst, $src2}",
1480 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1483 def PMAXUBrm : PDI<0xDE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1484 "pmaxub {$src2, $dst|$dst, $src2}",
1485 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1486 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1487 def PMAXSWrm : PDI<0xEE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1488 "pmaxsw {$src2, $dst|$dst, $src2}",
1489 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1490 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1492 let isCommutable = 1 in {
1493 def PMINUBrr : PDI<0xDA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1494 "pminub {$src2, $dst|$dst, $src2}",
1495 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1497 def PMINSWrr : PDI<0xEA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1498 "pminsw {$src2, $dst|$dst, $src2}",
1499 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1502 def PMINUBrm : PDI<0xDA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1503 "pminub {$src2, $dst|$dst, $src2}",
1504 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1505 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1506 def PMINSWrm : PDI<0xEA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1507 "pminsw {$src2, $dst|$dst, $src2}",
1508 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1509 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1512 let isCommutable = 1 in {
1513 def PSADBWrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1514 "psadbw {$src2, $dst|$dst, $src2}",
1515 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1518 def PSADBWrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1519 "psadbw {$src2, $dst|$dst, $src2}",
1520 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1521 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1524 let isTwoAddress = 1 in {
1525 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1526 "pslldq {$src2, $dst|$dst, $src2}", []>;
1527 def PSRLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1528 "psrldq {$src2, $dst|$dst, $src2}", []>;
1532 let isTwoAddress = 1 in {
1533 let isCommutable = 1 in {
1534 def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1535 "pand {$src2, $dst|$dst, $src2}",
1536 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1538 def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1539 "pand {$src2, $dst|$dst, $src2}",
1540 [(set VR128:$dst, (v2i64 (and VR128:$src1,
1541 (load addr:$src2))))]>;
1542 def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1543 "por {$src2, $dst|$dst, $src2}",
1544 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1546 def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1547 "por {$src2, $dst|$dst, $src2}",
1548 [(set VR128:$dst, (v2i64 (or VR128:$src1,
1549 (load addr:$src2))))]>;
1550 def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1551 "pxor {$src2, $dst|$dst, $src2}",
1552 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1554 def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1555 "pxor {$src2, $dst|$dst, $src2}",
1556 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
1557 (load addr:$src2))))]>;
1560 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1561 "pandn {$src2, $dst|$dst, $src2}",
1562 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1565 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1566 "pandn {$src2, $dst|$dst, $src2}",
1567 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1568 (load addr:$src2))))]>;
1571 // Pack instructions
1572 let isTwoAddress = 1 in {
1573 def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1575 "packsswb {$src2, $dst|$dst, $src2}",
1576 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1579 def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1581 "packsswb {$src2, $dst|$dst, $src2}",
1582 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1584 (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
1585 def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1587 "packssdw {$src2, $dst|$dst, $src2}",
1588 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1591 def PACKSSDWrm : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1593 "packssdw {$src2, $dst|$dst, $src2}",
1594 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1596 (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
1597 def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1599 "packuswb {$src2, $dst|$dst, $src2}",
1600 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1603 def PACKUSWBrm : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1605 "packuswb {$src2, $dst|$dst, $src2}",
1606 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1608 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1611 // Shuffle and unpack instructions
1612 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1613 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1614 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1615 [(set VR128:$dst, (v4i32 (vector_shuffle
1616 VR128:$src1, (undef),
1617 PSHUFD_shuffle_mask:$src2)))]>;
1618 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1619 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1620 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1621 [(set VR128:$dst, (v4i32 (vector_shuffle
1622 (bc_v4i32 (loadv2i64 addr:$src1)),
1624 PSHUFD_shuffle_mask:$src2)))]>;
1626 // SSE2 with ImmT == Imm8 and XS prefix.
1627 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1628 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1629 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1630 [(set VR128:$dst, (v8i16 (vector_shuffle
1631 VR128:$src1, (undef),
1632 PSHUFHW_shuffle_mask:$src2)))]>,
1633 XS, Requires<[HasSSE2]>;
1634 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1635 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1636 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1637 [(set VR128:$dst, (v8i16 (vector_shuffle
1638 (bc_v8i16 (loadv2i64 addr:$src1)),
1640 PSHUFHW_shuffle_mask:$src2)))]>,
1641 XS, Requires<[HasSSE2]>;
1643 // SSE2 with ImmT == Imm8 and XD prefix.
1644 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1645 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1646 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1647 [(set VR128:$dst, (v8i16 (vector_shuffle
1648 VR128:$src1, (undef),
1649 PSHUFLW_shuffle_mask:$src2)))]>,
1650 XD, Requires<[HasSSE2]>;
1651 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1652 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1653 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1654 [(set VR128:$dst, (v8i16 (vector_shuffle
1655 (bc_v8i16 (loadv2i64 addr:$src1)),
1657 PSHUFLW_shuffle_mask:$src2)))]>,
1658 XD, Requires<[HasSSE2]>;
1660 let isTwoAddress = 1 in {
1661 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1662 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1663 "punpcklbw {$src2, $dst|$dst, $src2}",
1665 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1666 UNPCKL_shuffle_mask)))]>;
1667 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1668 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1669 "punpcklbw {$src2, $dst|$dst, $src2}",
1671 (v16i8 (vector_shuffle VR128:$src1,
1672 (bc_v16i8 (loadv2i64 addr:$src2)),
1673 UNPCKL_shuffle_mask)))]>;
1674 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1675 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1676 "punpcklwd {$src2, $dst|$dst, $src2}",
1678 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1679 UNPCKL_shuffle_mask)))]>;
1680 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1681 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1682 "punpcklwd {$src2, $dst|$dst, $src2}",
1684 (v8i16 (vector_shuffle VR128:$src1,
1685 (bc_v8i16 (loadv2i64 addr:$src2)),
1686 UNPCKL_shuffle_mask)))]>;
1687 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1688 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1689 "punpckldq {$src2, $dst|$dst, $src2}",
1691 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1692 UNPCKL_shuffle_mask)))]>;
1693 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1694 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1695 "punpckldq {$src2, $dst|$dst, $src2}",
1697 (v4i32 (vector_shuffle VR128:$src1,
1698 (bc_v4i32 (loadv2i64 addr:$src2)),
1699 UNPCKL_shuffle_mask)))]>;
1700 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1701 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1702 "punpcklqdq {$src2, $dst|$dst, $src2}",
1704 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1705 UNPCKL_shuffle_mask)))]>;
1706 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1707 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1708 "punpcklqdq {$src2, $dst|$dst, $src2}",
1710 (v2i64 (vector_shuffle VR128:$src1,
1711 (loadv2i64 addr:$src2),
1712 UNPCKL_shuffle_mask)))]>;
1714 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1715 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1716 "punpckhbw {$src2, $dst|$dst, $src2}",
1718 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1719 UNPCKH_shuffle_mask)))]>;
1720 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1721 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1722 "punpckhbw {$src2, $dst|$dst, $src2}",
1724 (v16i8 (vector_shuffle VR128:$src1,
1725 (bc_v16i8 (loadv2i64 addr:$src2)),
1726 UNPCKH_shuffle_mask)))]>;
1727 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1728 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1729 "punpckhwd {$src2, $dst|$dst, $src2}",
1731 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1732 UNPCKH_shuffle_mask)))]>;
1733 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1734 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1735 "punpckhwd {$src2, $dst|$dst, $src2}",
1737 (v8i16 (vector_shuffle VR128:$src1,
1738 (bc_v8i16 (loadv2i64 addr:$src2)),
1739 UNPCKH_shuffle_mask)))]>;
1740 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1741 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1742 "punpckhdq {$src2, $dst|$dst, $src2}",
1744 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1745 UNPCKH_shuffle_mask)))]>;
1746 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1747 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1748 "punpckhdq {$src2, $dst|$dst, $src2}",
1750 (v4i32 (vector_shuffle VR128:$src1,
1751 (bc_v4i32 (loadv2i64 addr:$src2)),
1752 UNPCKH_shuffle_mask)))]>;
1753 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1754 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1755 "punpckhdq {$src2, $dst|$dst, $src2}",
1757 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1758 UNPCKH_shuffle_mask)))]>;
1759 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1760 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1761 "punpckhqdq {$src2, $dst|$dst, $src2}",
1763 (v2i64 (vector_shuffle VR128:$src1,
1764 (loadv2i64 addr:$src2),
1765 UNPCKH_shuffle_mask)))]>;
1769 def PEXTRWr : PDIi8<0xC5, MRMSrcReg,
1770 (ops R32:$dst, VR128:$src1, i32i8imm:$src2),
1771 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1772 [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1),
1773 (i32 imm:$src2)))]>;
1774 def PEXTRWm : PDIi8<0xC5, MRMSrcMem,
1775 (ops R32:$dst, i128mem:$src1, i32i8imm:$src2),
1776 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1777 [(set R32:$dst, (X86pextrw
1778 (bc_v8i16 (loadv2i64 addr:$src1)),
1779 (i32 imm:$src2)))]>;
1781 let isTwoAddress = 1 in {
1782 def PINSRWr : PDIi8<0xC4, MRMSrcReg,
1783 (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
1784 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1785 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1786 R32:$src2, (i32 imm:$src3))))]>;
1787 def PINSRWm : PDIi8<0xC4, MRMSrcMem,
1788 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
1789 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1791 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1792 (i32 (anyext (loadi16 addr:$src2))),
1793 (i32 imm:$src3))))]>;
1796 //===----------------------------------------------------------------------===//
1797 // Miscellaneous Instructions
1798 //===----------------------------------------------------------------------===//
1801 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
1802 "movmskps {$src, $dst|$dst, $src}",
1803 [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1804 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
1805 "movmskpd {$src, $dst|$dst, $src}",
1806 [(set R32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1808 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
1809 "pmovmskb {$src, $dst|$dst, $src}",
1810 [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1812 // Conditional store
1813 def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
1814 "maskmovdqu {$mask, $src|$src, $mask}",
1815 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1818 // Prefetching loads
1819 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
1820 "prefetcht0 $src", []>;
1821 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
1822 "prefetcht1 $src", []>;
1823 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
1824 "prefetcht2 $src", []>;
1825 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
1826 "prefetchtnta $src", []>;
1828 // Non-temporal stores
1829 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1830 "movntps {$src, $dst|$dst, $src}",
1831 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1832 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1833 "movntpd {$src, $dst|$dst, $src}",
1834 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1835 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1836 "movntdq {$src, $dst|$dst, $src}",
1837 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1838 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
1839 "movnti {$src, $dst|$dst, $src}",
1840 [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>,
1841 TB, Requires<[HasSSE2]>;
1844 def SFENCE : I<0xAE, MRM7m, (ops),
1845 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
1848 def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),
1850 [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
1851 def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
1853 [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
1855 //===----------------------------------------------------------------------===//
1856 // Alias Instructions
1857 //===----------------------------------------------------------------------===//
1859 // Alias instructions that map zero vector to pxor / xorp* for sse.
1860 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1861 def V_SET0_PI : PDI<0xEF, MRMInitReg, (ops VR128:$dst),
1863 [(set VR128:$dst, (v2i64 immAllZerosV))]>;
1864 def V_SET0_PS : PSI<0x57, MRMInitReg, (ops VR128:$dst),
1866 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1867 def V_SET0_PD : PDI<0x57, MRMInitReg, (ops VR128:$dst),
1869 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1871 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
1872 "pcmpeqd $dst, $dst",
1873 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
1875 // FR32 / FR64 to 128-bit vector conversion.
1876 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
1877 "movss {$src, $dst|$dst, $src}",
1879 (v4f32 (scalar_to_vector FR32:$src)))]>;
1880 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1881 "movss {$src, $dst|$dst, $src}",
1883 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1884 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
1885 "movsd {$src, $dst|$dst, $src}",
1887 (v2f64 (scalar_to_vector FR64:$src)))]>;
1888 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1889 "movsd {$src, $dst|$dst, $src}",
1891 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
1893 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
1894 "movd {$src, $dst|$dst, $src}",
1896 (v4i32 (scalar_to_vector R32:$src)))]>;
1897 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1898 "movd {$src, $dst|$dst, $src}",
1900 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
1901 // SSE2 instructions with XS prefix
1902 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
1903 "movq {$src, $dst|$dst, $src}",
1905 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
1906 Requires<[HasSSE2]>;
1907 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1908 "movq {$src, $dst|$dst, $src}",
1910 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
1911 Requires<[HasSSE2]>;
1912 // FIXME: may not be able to eliminate this movss with coalescing the src and
1913 // dest register classes are different. We really want to write this pattern
1915 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (i32 0))),
1916 // (f32 FR32:$src)>;
1917 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
1918 "movss {$src, $dst|$dst, $src}",
1919 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1921 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
1922 "movss {$src, $dst|$dst, $src}",
1923 [(store (f32 (vector_extract (v4f32 VR128:$src),
1924 (i32 0))), addr:$dst)]>;
1925 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
1926 "movsd {$src, $dst|$dst, $src}",
1927 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
1929 def MOVPDI2DIrr : PDI<0x6E, MRMSrcReg, (ops R32:$dst, VR128:$src),
1930 "movd {$src, $dst|$dst, $src}",
1931 [(set R32:$dst, (vector_extract (v4i32 VR128:$src),
1933 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
1934 "movd {$src, $dst|$dst, $src}",
1935 [(store (i32 (vector_extract (v4i32 VR128:$src),
1936 (i32 0))), addr:$dst)]>;
1938 // Move to lower bits of a VR128, leaving upper bits alone.
1939 // Three operand (but two address) aliases.
1940 let isTwoAddress = 1 in {
1941 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
1942 "movss {$src2, $dst|$dst, $src2}", []>;
1943 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
1944 "movsd {$src2, $dst|$dst, $src2}", []>;
1945 def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2),
1946 "movd {$src2, $dst|$dst, $src2}", []>;
1948 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1949 "movss {$src2, $dst|$dst, $src2}",
1951 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1952 MOVS_shuffle_mask)))]>;
1953 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1954 "movsd {$src2, $dst|$dst, $src2}",
1956 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
1957 MOVS_shuffle_mask)))]>;
1960 // Store / copy lower 64-bits of a XMM register.
1961 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1962 "movq {$src, $dst|$dst, $src}",
1963 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
1965 // FIXME: Temporary workaround since 2-wide shuffle is broken.
1966 def MOVLQ128rr : PDI<0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1967 "movq {$src, $dst|$dst, $src}",
1968 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>;
1970 // Move to lower bits of a VR128 and zeroing upper bits.
1971 // Loading from memory automatically zeroing upper bits.
1972 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1973 "movss {$src, $dst|$dst, $src}",
1975 (v4f32 (X86zexts2vec (loadf32 addr:$src))))]>;
1976 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1977 "movsd {$src, $dst|$dst, $src}",
1979 (v2f64 (X86zexts2vec (loadf64 addr:$src))))]>;
1980 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1981 "movd {$src, $dst|$dst, $src}",
1983 (v4i32 (X86zexts2vec (loadi32 addr:$src))))]>;
1984 def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1985 "movq {$src, $dst|$dst, $src}",
1987 (bc_v2i64 (v2f64 (X86zexts2vec
1988 (loadf64 addr:$src)))))]>;
1990 //===----------------------------------------------------------------------===//
1991 // Non-Instruction Patterns
1992 //===----------------------------------------------------------------------===//
1994 // 128-bit vector undef's.
1995 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1996 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1997 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1998 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1999 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2001 // 128-bit vector all zero's.
2002 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0_PI))>, Requires<[HasSSE2]>;
2003 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0_PI))>, Requires<[HasSSE2]>;
2004 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0_PI))>, Requires<[HasSSE2]>;
2006 // 128-bit vector all one's.
2007 def : Pat<(v16i8 immAllOnesV), (v16i8 (V_SETALLONES))>, Requires<[HasSSE2]>;
2008 def : Pat<(v8i16 immAllOnesV), (v8i16 (V_SETALLONES))>, Requires<[HasSSE2]>;
2009 def : Pat<(v4i32 immAllOnesV), (v4i32 (V_SETALLONES))>, Requires<[HasSSE2]>;
2010 def : Pat<(v2i64 immAllOnesV), (v2i64 (V_SETALLONES))>, Requires<[HasSSE2]>;
2011 def : Pat<(v4f32 immAllOnesV), (v4f32 (V_SETALLONES))>, Requires<[HasSSE1]>;
2013 // Store 128-bit integer vector values.
2014 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2015 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2016 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2017 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2018 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2019 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2021 // Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
2023 def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
2024 Requires<[HasSSE2]>;
2025 def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
2026 Requires<[HasSSE2]>;
2029 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
2030 Requires<[HasSSE2]>;
2031 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>,
2032 Requires<[HasSSE2]>;
2033 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>,
2034 Requires<[HasSSE2]>;
2035 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>,
2036 Requires<[HasSSE2]>;
2037 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>,
2038 Requires<[HasSSE2]>;
2039 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2040 Requires<[HasSSE2]>;
2041 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2042 Requires<[HasSSE2]>;
2043 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2044 Requires<[HasSSE2]>;
2045 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>,
2046 Requires<[HasSSE2]>;
2047 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
2048 Requires<[HasSSE2]>;
2049 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2050 Requires<[HasSSE2]>;
2051 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
2052 Requires<[HasSSE2]>;
2053 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2054 Requires<[HasSSE2]>;
2055 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>,
2056 Requires<[HasSSE2]>;
2057 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>,
2058 Requires<[HasSSE2]>;
2059 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2060 Requires<[HasSSE2]>;
2061 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
2062 Requires<[HasSSE2]>;
2063 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2064 Requires<[HasSSE2]>;
2065 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>,
2066 Requires<[HasSSE2]>;
2067 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>,
2068 Requires<[HasSSE2]>;
2069 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>,
2070 Requires<[HasSSE2]>;
2071 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
2072 Requires<[HasSSE2]>;
2073 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>,
2074 Requires<[HasSSE2]>;
2075 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>,
2076 Requires<[HasSSE2]>;
2077 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>,
2078 Requires<[HasSSE2]>;
2079 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>,
2080 Requires<[HasSSE2]>;
2081 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>,
2082 Requires<[HasSSE2]>;
2083 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>,
2084 Requires<[HasSSE2]>;
2085 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>,
2086 Requires<[HasSSE2]>;
2087 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>,
2088 Requires<[HasSSE2]>;
2090 // Zeroing a VR128 then do a MOVS* to the lower bits.
2091 def : Pat<(v2f64 (X86zexts2vec FR64:$src)),
2092 (MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>;
2093 def : Pat<(v4f32 (X86zexts2vec FR32:$src)),
2094 (MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>;
2095 def : Pat<(v4i32 (X86zexts2vec R32:$src)),
2096 (MOVLDI2PDIrr (V_SET0_PI), R32:$src)>, Requires<[HasSSE2]>;
2097 def : Pat<(v8i16 (X86zexts2vec R16:$src)),
2098 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr16 R16:$src))>, Requires<[HasSSE2]>;
2099 def : Pat<(v16i8 (X86zexts2vec R8:$src)),
2100 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
2102 // Splat v2f64 / v2i64
2103 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_mask:$sm),
2104 (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
2105 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_mask:$sm),
2106 (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
2109 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2110 (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
2111 Requires<[HasSSE1]>;
2113 // Special unary SHUFPSrr case.
2114 // FIXME: when we want non two-address code, then we should use PSHUFD?
2115 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2116 SHUFP_unary_shuffle_mask:$sm),
2117 (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm))>,
2118 Requires<[HasSSE1]>;
2119 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2120 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
2121 SHUFP_unary_shuffle_mask:$sm),
2122 (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm))>,
2123 Requires<[HasSSE2]>;
2124 // Special binary v4i32 shuffle cases with SHUFPS.
2125 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2126 PSHUFD_binary_shuffle_mask:$sm),
2127 (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
2128 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
2129 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2130 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2131 (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
2132 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
2134 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2135 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2136 UNPCKL_v_undef_shuffle_mask)),
2137 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2138 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2139 UNPCKL_v_undef_shuffle_mask)),
2140 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2141 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2142 UNPCKL_v_undef_shuffle_mask)),
2143 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2144 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2145 UNPCKL_v_undef_shuffle_mask)),
2146 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2148 // 128-bit logical shifts
2149 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2150 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2151 Requires<[HasSSE2]>;
2152 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2153 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2154 Requires<[HasSSE2]>;
2156 // Some special case pandn patterns.
2157 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2159 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2160 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2162 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2163 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2165 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2167 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2168 (load addr:$src2))),
2169 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2170 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2171 (load addr:$src2))),
2172 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2173 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2174 (load addr:$src2))),
2175 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;