1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 def SSE_BIT_ITINS_P : OpndItins<
124 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
127 let Sched = WriteVecALU in {
128 def SSE_INTALU_ITINS_P : OpndItins<
129 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
132 def SSE_INTALUQ_ITINS_P : OpndItins<
133 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
137 let Sched = WriteVecIMul in
138 def SSE_INTMUL_ITINS_P : OpndItins<
139 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
142 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
143 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
146 def SSE_MOVA_ITINS : OpndItins<
147 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
150 def SSE_MOVU_ITINS : OpndItins<
151 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
154 def SSE_DPPD_ITINS : OpndItins<
155 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
158 def SSE_DPPS_ITINS : OpndItins<
159 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
162 def DEFAULT_ITINS : OpndItins<
163 IIC_ALU_NONMEM, IIC_ALU_MEM
166 def SSE_EXTRACT_ITINS : OpndItins<
167 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
170 def SSE_INSERT_ITINS : OpndItins<
171 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
174 def SSE_MPSADBW_ITINS : OpndItins<
175 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
178 def SSE_PMULLD_ITINS : OpndItins<
179 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
182 //===----------------------------------------------------------------------===//
183 // SSE 1 & 2 Instructions Classes
184 //===----------------------------------------------------------------------===//
186 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
187 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
188 RegisterClass RC, X86MemOperand x86memop,
191 let isCommutable = 1 in {
192 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
194 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
196 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
197 Sched<[itins.Sched]>;
199 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
201 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
203 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
204 Sched<[itins.Sched.Folded, ReadAfterLd]>;
207 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
208 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
209 string asm, string SSEVer, string FPSizeStr,
210 Operand memopr, ComplexPattern mem_cpat,
213 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
215 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
216 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
217 [(set RC:$dst, (!cast<Intrinsic>(
218 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
219 RC:$src1, RC:$src2))], itins.rr>,
220 Sched<[itins.Sched]>;
221 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
223 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
224 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
225 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
226 SSEVer, "_", OpcodeStr, FPSizeStr))
227 RC:$src1, mem_cpat:$src2))], itins.rm>,
228 Sched<[itins.Sched.Folded, ReadAfterLd]>;
231 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
232 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
233 RegisterClass RC, ValueType vt,
234 X86MemOperand x86memop, PatFrag mem_frag,
235 Domain d, OpndItins itins, bit Is2Addr = 1> {
236 let isCommutable = 1 in
237 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
241 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
242 Sched<[itins.Sched]>;
244 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
246 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
247 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
248 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
250 Sched<[itins.Sched.Folded, ReadAfterLd]>;
253 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
254 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
255 string OpcodeStr, X86MemOperand x86memop,
256 list<dag> pat_rr, list<dag> pat_rm,
258 let isCommutable = 1, hasSideEffects = 0 in
259 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
261 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
262 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
263 pat_rr, NoItinerary, d>,
264 Sched<[WriteVecLogic]>;
265 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
267 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
269 pat_rm, NoItinerary, d>,
270 Sched<[WriteVecLogicLd, ReadAfterLd]>;
273 //===----------------------------------------------------------------------===//
274 // Non-instruction patterns
275 //===----------------------------------------------------------------------===//
277 // A vector extract of the first f32/f64 position is a subregister copy
278 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
279 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
280 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
281 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
283 // A 128-bit subvector extract from the first 256-bit vector position
284 // is a subregister copy that needs no instruction.
285 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
286 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
287 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
288 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
290 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
291 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
292 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
293 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
295 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
296 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
297 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
298 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
300 // A 128-bit subvector insert to the first 256-bit vector position
301 // is a subregister copy that needs no instruction.
302 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
303 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
304 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
305 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
306 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
307 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
308 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
309 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
310 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
311 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
312 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
313 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
314 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
317 // Implicitly promote a 32-bit scalar to a vector.
318 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
319 (COPY_TO_REGCLASS FR32:$src, VR128)>;
320 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
321 (COPY_TO_REGCLASS FR32:$src, VR128)>;
322 // Implicitly promote a 64-bit scalar to a vector.
323 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
324 (COPY_TO_REGCLASS FR64:$src, VR128)>;
325 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
326 (COPY_TO_REGCLASS FR64:$src, VR128)>;
328 // Bitcasts between 128-bit vector types. Return the original type since
329 // no instruction is needed for the conversion
330 let Predicates = [HasSSE2] in {
331 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
332 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
333 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
334 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
335 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
336 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
337 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
338 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
339 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
340 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
341 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
342 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
343 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
344 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
345 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
346 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
347 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
348 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
349 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
350 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
351 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
352 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
353 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
354 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
355 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
356 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
357 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
358 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
359 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
360 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
363 // Bitcasts between 256-bit vector types. Return the original type since
364 // no instruction is needed for the conversion
365 let Predicates = [HasAVX] in {
366 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
367 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
368 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
369 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
370 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
371 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
372 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
373 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
374 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
375 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
376 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
377 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
378 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
379 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
380 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
381 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
382 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
383 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
384 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
385 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
386 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
387 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
388 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
389 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
390 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
391 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
392 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
393 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
394 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
395 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
398 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
399 // This is expanded by ExpandPostRAPseudos.
400 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
401 isPseudo = 1, SchedRW = [WriteZero] in {
402 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
403 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
404 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
405 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
408 //===----------------------------------------------------------------------===//
409 // AVX & SSE - Zero/One Vectors
410 //===----------------------------------------------------------------------===//
412 // Alias instruction that maps zero vector to pxor / xorp* for sse.
413 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
414 // swizzled by ExecutionDepsFix to pxor.
415 // We set canFoldAsLoad because this can be converted to a constant-pool
416 // load of an all-zeros value if folding it would be beneficial.
417 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
418 isPseudo = 1, SchedRW = [WriteZero] in {
419 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
420 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
423 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
424 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
425 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
426 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
427 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
430 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
431 // and doesn't need it because on sandy bridge the register is set to zero
432 // at the rename stage without using any execution unit, so SET0PSY
433 // and SET0PDY can be used for vector int instructions without penalty
434 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
435 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
436 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
437 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
440 let Predicates = [HasAVX] in
441 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
443 let Predicates = [HasAVX2] in {
444 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
445 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
446 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
447 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
450 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
451 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
452 let Predicates = [HasAVX1Only] in {
453 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
454 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
455 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
457 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
458 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
459 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
461 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
462 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
463 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
465 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
466 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
467 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-ones value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
476 let Predicates = [HasAVX2] in
477 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
478 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
482 //===----------------------------------------------------------------------===//
483 // SSE 1 & 2 - Move FP Scalar Instructions
485 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
486 // register copies because it's a partial register update; Register-to-register
487 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
488 // that the insert be implementable in terms of a copy, and just mentioned, we
489 // don't use movss/movsd for copies.
490 //===----------------------------------------------------------------------===//
492 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
493 X86MemOperand x86memop, string base_opc,
495 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
496 (ins VR128:$src1, RC:$src2),
497 !strconcat(base_opc, asm_opr),
498 [(set VR128:$dst, (vt (OpNode VR128:$src1,
499 (scalar_to_vector RC:$src2))))],
500 IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
502 // For the disassembler
503 let isCodeGenOnly = 1, hasSideEffects = 0 in
504 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
505 (ins VR128:$src1, RC:$src2),
506 !strconcat(base_opc, asm_opr),
507 [], IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
510 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
511 X86MemOperand x86memop, string OpcodeStr> {
513 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
514 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
517 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
519 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
520 VEX, VEX_LIG, Sched<[WriteStore]>;
522 let Constraints = "$src1 = $dst" in {
523 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
524 "\t{$src2, $dst|$dst, $src2}">;
527 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
528 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
529 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
533 // Loading from memory automatically zeroing upper bits.
534 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
535 PatFrag mem_pat, string OpcodeStr> {
536 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
538 [(set RC:$dst, (mem_pat addr:$src))],
539 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
540 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
541 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
542 [(set RC:$dst, (mem_pat addr:$src))],
543 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
546 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
547 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
549 let canFoldAsLoad = 1, isReMaterializable = 1 in {
550 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
552 let AddedComplexity = 20 in
553 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
557 let Predicates = [UseAVX] in {
558 let AddedComplexity = 15 in {
559 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
560 // MOVS{S,D} to the lower bits.
561 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
562 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
563 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
564 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
565 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
566 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
567 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
568 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
570 // Move low f32 and clear high bits.
571 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
572 (SUBREG_TO_REG (i32 0),
573 (VMOVSSrr (v4f32 (V_SET0)),
574 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
575 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
576 (SUBREG_TO_REG (i32 0),
577 (VMOVSSrr (v4i32 (V_SET0)),
578 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
581 let AddedComplexity = 20 in {
582 // MOVSSrm zeros the high parts of the register; represent this
583 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
584 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
585 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
586 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
587 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
588 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
589 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
591 // MOVSDrm zeros the high parts of the register; represent this
592 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
593 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
594 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
595 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
596 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
597 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
598 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
599 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
600 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
601 def : Pat<(v2f64 (X86vzload addr:$src)),
602 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
604 // Represent the same patterns above but in the form they appear for
606 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
607 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
608 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
609 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
610 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
612 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
613 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
616 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
617 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
618 (SUBREG_TO_REG (i32 0),
619 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
621 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
622 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
623 (SUBREG_TO_REG (i64 0),
624 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
626 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
627 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
628 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
630 // Move low f64 and clear high bits.
631 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
632 (SUBREG_TO_REG (i32 0),
633 (VMOVSDrr (v2f64 (V_SET0)),
634 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
636 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
637 (SUBREG_TO_REG (i32 0),
638 (VMOVSDrr (v2i64 (V_SET0)),
639 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
641 // Extract and store.
642 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
644 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
645 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
647 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
649 // Shuffle with VMOVSS
650 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
651 (VMOVSSrr (v4i32 VR128:$src1),
652 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
653 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
654 (VMOVSSrr (v4f32 VR128:$src1),
655 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
658 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
659 (SUBREG_TO_REG (i32 0),
660 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
661 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
663 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
666 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
669 // Shuffle with VMOVSD
670 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
671 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
674 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
675 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
676 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
680 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
681 (SUBREG_TO_REG (i32 0),
682 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
683 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
685 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
686 (SUBREG_TO_REG (i32 0),
687 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
688 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
692 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
693 // is during lowering, where it's not possible to recognize the fold cause
694 // it has two uses through a bitcast. One use disappears at isel time and the
695 // fold opportunity reappears.
696 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
697 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
698 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
699 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
700 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
701 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
702 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
703 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
706 let Predicates = [UseSSE1] in {
707 let AddedComplexity = 15 in {
708 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
709 // MOVSS to the lower bits.
710 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
711 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
712 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
713 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
714 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
715 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
718 let AddedComplexity = 20 in {
719 // MOVSSrm already zeros the high parts of the register.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
721 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
722 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
723 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
724 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
728 // Extract and store.
729 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
731 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
733 // Shuffle with MOVSS
734 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
735 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
736 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
737 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
740 let Predicates = [UseSSE2] in {
741 let AddedComplexity = 15 in {
742 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
743 // MOVSD to the lower bits.
744 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
745 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
748 let AddedComplexity = 20 in {
749 // MOVSDrm already zeros the high parts of the register.
750 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
751 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
752 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
753 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
754 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
755 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
756 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
757 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
758 def : Pat<(v2f64 (X86vzload addr:$src)),
759 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 // Extract and store.
763 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
765 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
767 // Shuffle with MOVSD
768 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
769 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
770 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
771 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
772 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
773 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
774 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
775 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
777 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
778 // is during lowering, where it's not possible to recognize the fold cause
779 // it has two uses through a bitcast. One use disappears at isel time and the
780 // fold opportunity reappears.
781 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
782 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
783 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
784 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
785 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
786 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
788 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
791 //===----------------------------------------------------------------------===//
792 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
793 //===----------------------------------------------------------------------===//
795 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
796 X86MemOperand x86memop, PatFrag ld_frag,
797 string asm, Domain d,
799 bit IsReMaterializable = 1> {
800 let neverHasSideEffects = 1 in
801 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
802 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
804 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
805 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
806 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
807 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
811 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
812 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
814 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
815 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
817 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
818 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
820 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
821 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
824 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
829 TB, OpSize, VEX, VEX_L;
830 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 TB, OpSize, VEX, VEX_L;
836 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
837 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
839 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
840 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
842 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
843 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
845 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
846 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let SchedRW = [WriteStore] in {
850 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
851 "movaps\t{$src, $dst|$dst, $src}",
852 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
853 IIC_SSE_MOVA_P_MR>, VEX;
854 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
855 "movapd\t{$src, $dst|$dst, $src}",
856 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
857 IIC_SSE_MOVA_P_MR>, VEX;
858 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
859 "movups\t{$src, $dst|$dst, $src}",
860 [(store (v4f32 VR128:$src), addr:$dst)],
861 IIC_SSE_MOVU_P_MR>, VEX;
862 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
863 "movupd\t{$src, $dst|$dst, $src}",
864 [(store (v2f64 VR128:$src), addr:$dst)],
865 IIC_SSE_MOVU_P_MR>, VEX;
866 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
870 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
874 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v8f32 VR256:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
878 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v4f64 VR256:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
885 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
886 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
888 "movaps\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVA_P_RR>, VEX;
890 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
892 "movapd\t{$src, $dst|$dst, $src}", [],
893 IIC_SSE_MOVA_P_RR>, VEX;
894 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
896 "movups\t{$src, $dst|$dst, $src}", [],
897 IIC_SSE_MOVU_P_RR>, VEX;
898 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
900 "movupd\t{$src, $dst|$dst, $src}", [],
901 IIC_SSE_MOVU_P_RR>, VEX;
902 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
904 "movaps\t{$src, $dst|$dst, $src}", [],
905 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
906 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
908 "movapd\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
910 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
912 "movups\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
914 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
916 "movupd\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
920 let Predicates = [HasAVX] in {
921 def : Pat<(v8i32 (X86vzmovl
922 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
923 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
924 def : Pat<(v4i64 (X86vzmovl
925 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
926 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
927 def : Pat<(v8f32 (X86vzmovl
928 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
929 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
930 def : Pat<(v4f64 (X86vzmovl
931 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
932 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
936 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
937 (VMOVUPSYmr addr:$dst, VR256:$src)>;
938 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
939 (VMOVUPDYmr addr:$dst, VR256:$src)>;
941 let SchedRW = [WriteStore] in {
942 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
943 "movaps\t{$src, $dst|$dst, $src}",
944 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
946 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
947 "movapd\t{$src, $dst|$dst, $src}",
948 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
950 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
951 "movups\t{$src, $dst|$dst, $src}",
952 [(store (v4f32 VR128:$src), addr:$dst)],
954 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
955 "movupd\t{$src, $dst|$dst, $src}",
956 [(store (v2f64 VR128:$src), addr:$dst)],
961 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
962 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
963 "movaps\t{$src, $dst|$dst, $src}", [],
965 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
966 "movapd\t{$src, $dst|$dst, $src}", [],
968 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}", [],
971 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
972 "movupd\t{$src, $dst|$dst, $src}", [],
976 let Predicates = [HasAVX] in {
977 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
978 (VMOVUPSmr addr:$dst, VR128:$src)>;
979 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
980 (VMOVUPDmr addr:$dst, VR128:$src)>;
983 let Predicates = [UseSSE1] in
984 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
985 (MOVUPSmr addr:$dst, VR128:$src)>;
986 let Predicates = [UseSSE2] in
987 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
988 (MOVUPDmr addr:$dst, VR128:$src)>;
990 // Use vmovaps/vmovups for AVX integer load/store.
991 let Predicates = [HasAVX] in {
992 // 128-bit load/store
993 def : Pat<(alignedloadv2i64 addr:$src),
994 (VMOVAPSrm addr:$src)>;
995 def : Pat<(loadv2i64 addr:$src),
996 (VMOVUPSrm addr:$src)>;
998 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
999 (VMOVAPSmr addr:$dst, VR128:$src)>;
1000 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1001 (VMOVAPSmr addr:$dst, VR128:$src)>;
1002 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1003 (VMOVAPSmr addr:$dst, VR128:$src)>;
1004 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1005 (VMOVAPSmr addr:$dst, VR128:$src)>;
1006 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1007 (VMOVUPSmr addr:$dst, VR128:$src)>;
1008 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1009 (VMOVUPSmr addr:$dst, VR128:$src)>;
1010 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1011 (VMOVUPSmr addr:$dst, VR128:$src)>;
1012 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1013 (VMOVUPSmr addr:$dst, VR128:$src)>;
1015 // 256-bit load/store
1016 def : Pat<(alignedloadv4i64 addr:$src),
1017 (VMOVAPSYrm addr:$src)>;
1018 def : Pat<(loadv4i64 addr:$src),
1019 (VMOVUPSYrm addr:$src)>;
1020 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1021 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1022 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1023 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1024 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1025 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1026 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1027 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1028 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1029 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1030 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1031 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1032 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1033 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1034 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1035 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1037 // Special patterns for storing subvector extracts of lower 128-bits
1038 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1039 def : Pat<(alignedstore (v2f64 (extract_subvector
1040 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1041 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1042 def : Pat<(alignedstore (v4f32 (extract_subvector
1043 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1044 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1045 def : Pat<(alignedstore (v2i64 (extract_subvector
1046 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1047 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1048 def : Pat<(alignedstore (v4i32 (extract_subvector
1049 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1050 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1051 def : Pat<(alignedstore (v8i16 (extract_subvector
1052 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1053 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1054 def : Pat<(alignedstore (v16i8 (extract_subvector
1055 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1056 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1058 def : Pat<(store (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(store (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(store (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(store (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(store (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(store (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1078 // Use movaps / movups for SSE integer load / store (one byte shorter).
1079 // The instructions selected below are then converted to MOVDQA/MOVDQU
1080 // during the SSE domain pass.
1081 let Predicates = [UseSSE1] in {
1082 def : Pat<(alignedloadv2i64 addr:$src),
1083 (MOVAPSrm addr:$src)>;
1084 def : Pat<(loadv2i64 addr:$src),
1085 (MOVUPSrm addr:$src)>;
1087 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1088 (MOVAPSmr addr:$dst, VR128:$src)>;
1089 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1090 (MOVAPSmr addr:$dst, VR128:$src)>;
1091 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1092 (MOVAPSmr addr:$dst, VR128:$src)>;
1093 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1094 (MOVAPSmr addr:$dst, VR128:$src)>;
1095 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1096 (MOVUPSmr addr:$dst, VR128:$src)>;
1097 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1098 (MOVUPSmr addr:$dst, VR128:$src)>;
1099 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1100 (MOVUPSmr addr:$dst, VR128:$src)>;
1101 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1102 (MOVUPSmr addr:$dst, VR128:$src)>;
1105 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1106 // bits are disregarded. FIXME: Set encoding to pseudo!
1107 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1108 let isCodeGenOnly = 1 in {
1109 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1110 "movaps\t{$src, $dst|$dst, $src}",
1111 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 IIC_SSE_MOVA_P_RM>, VEX;
1113 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1114 "movapd\t{$src, $dst|$dst, $src}",
1115 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1116 IIC_SSE_MOVA_P_RM>, VEX;
1117 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1118 "movaps\t{$src, $dst|$dst, $src}",
1119 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1121 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1122 "movapd\t{$src, $dst|$dst, $src}",
1123 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1128 //===----------------------------------------------------------------------===//
1129 // SSE 1 & 2 - Move Low packed FP Instructions
1130 //===----------------------------------------------------------------------===//
1132 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1133 string base_opc, string asm_opr,
1134 InstrItinClass itin> {
1135 def PSrm : PI<opc, MRMSrcMem,
1136 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1137 !strconcat(base_opc, "s", asm_opr),
1139 (psnode VR128:$src1,
1140 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1141 itin, SSEPackedSingle>, TB,
1142 Sched<[WriteShuffleLd, ReadAfterLd]>;
1144 def PDrm : PI<opc, MRMSrcMem,
1145 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1146 !strconcat(base_opc, "d", asm_opr),
1147 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1148 (scalar_to_vector (loadf64 addr:$src2)))))],
1149 itin, SSEPackedDouble>, TB, OpSize,
1150 Sched<[WriteShuffleLd, ReadAfterLd]>;
1154 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1155 string base_opc, InstrItinClass itin> {
1156 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1157 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1160 let Constraints = "$src1 = $dst" in
1161 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1162 "\t{$src2, $dst|$dst, $src2}",
1166 let AddedComplexity = 20 in {
1167 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1171 let SchedRW = [WriteStore] in {
1172 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1173 "movlps\t{$src, $dst|$dst, $src}",
1174 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1175 (iPTR 0))), addr:$dst)],
1176 IIC_SSE_MOV_LH>, VEX;
1177 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1178 "movlpd\t{$src, $dst|$dst, $src}",
1179 [(store (f64 (vector_extract (v2f64 VR128:$src),
1180 (iPTR 0))), addr:$dst)],
1181 IIC_SSE_MOV_LH>, VEX;
1182 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1183 "movlps\t{$src, $dst|$dst, $src}",
1184 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1185 (iPTR 0))), addr:$dst)],
1187 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1188 "movlpd\t{$src, $dst|$dst, $src}",
1189 [(store (f64 (vector_extract (v2f64 VR128:$src),
1190 (iPTR 0))), addr:$dst)],
1194 let Predicates = [HasAVX] in {
1195 // Shuffle with VMOVLPS
1196 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1197 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1198 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1199 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1201 // Shuffle with VMOVLPD
1202 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1203 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1204 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1205 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1208 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1210 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1211 def : Pat<(store (v4i32 (X86Movlps
1212 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1213 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1214 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1216 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1217 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1219 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1222 let Predicates = [UseSSE1] in {
1223 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1224 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1225 (iPTR 0))), addr:$src1),
1226 (MOVLPSmr addr:$src1, VR128:$src2)>;
1228 // Shuffle with MOVLPS
1229 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1230 (MOVLPSrm VR128:$src1, addr:$src2)>;
1231 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1232 (MOVLPSrm VR128:$src1, addr:$src2)>;
1233 def : Pat<(X86Movlps VR128:$src1,
1234 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1235 (MOVLPSrm VR128:$src1, addr:$src2)>;
1238 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1240 (MOVLPSmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v4i32 (X86Movlps
1242 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1244 (MOVLPSmr addr:$src1, VR128:$src2)>;
1247 let Predicates = [UseSSE2] in {
1248 // Shuffle with MOVLPD
1249 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1250 (MOVLPDrm VR128:$src1, addr:$src2)>;
1251 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1252 (MOVLPDrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1257 (MOVLPDmr addr:$src1, VR128:$src2)>;
1258 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1260 (MOVLPDmr addr:$src1, VR128:$src2)>;
1263 //===----------------------------------------------------------------------===//
1264 // SSE 1 & 2 - Move Hi packed FP Instructions
1265 //===----------------------------------------------------------------------===//
1267 let AddedComplexity = 20 in {
1268 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1272 let SchedRW = [WriteStore] in {
1273 // v2f64 extract element 1 is always custom lowered to unpack high to low
1274 // and extract element 0 so the non-store version isn't too horrible.
1275 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1276 "movhps\t{$src, $dst|$dst, $src}",
1277 [(store (f64 (vector_extract
1278 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1279 (bc_v2f64 (v4f32 VR128:$src))),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1281 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1282 "movhpd\t{$src, $dst|$dst, $src}",
1283 [(store (f64 (vector_extract
1284 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1285 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1286 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1287 "movhps\t{$src, $dst|$dst, $src}",
1288 [(store (f64 (vector_extract
1289 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1290 (bc_v2f64 (v4f32 VR128:$src))),
1291 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1292 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1293 "movhpd\t{$src, $dst|$dst, $src}",
1294 [(store (f64 (vector_extract
1295 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1296 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1299 let Predicates = [HasAVX] in {
1301 def : Pat<(X86Movlhps VR128:$src1,
1302 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1303 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1304 def : Pat<(X86Movlhps VR128:$src1,
1305 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1306 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1308 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1309 // is during lowering, where it's not possible to recognize the load fold
1310 // cause it has two uses through a bitcast. One use disappears at isel time
1311 // and the fold opportunity reappears.
1312 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1313 (scalar_to_vector (loadf64 addr:$src2)))),
1314 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1317 let Predicates = [UseSSE1] in {
1319 def : Pat<(X86Movlhps VR128:$src1,
1320 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1321 (MOVHPSrm VR128:$src1, addr:$src2)>;
1322 def : Pat<(X86Movlhps VR128:$src1,
1323 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1324 (MOVHPSrm VR128:$src1, addr:$src2)>;
1327 let Predicates = [UseSSE2] in {
1328 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1329 // is during lowering, where it's not possible to recognize the load fold
1330 // cause it has two uses through a bitcast. One use disappears at isel time
1331 // and the fold opportunity reappears.
1332 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1333 (scalar_to_vector (loadf64 addr:$src2)))),
1334 (MOVHPDrm VR128:$src1, addr:$src2)>;
1337 //===----------------------------------------------------------------------===//
1338 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1339 //===----------------------------------------------------------------------===//
1341 let AddedComplexity = 20, Predicates = [UseAVX] in {
1342 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1343 (ins VR128:$src1, VR128:$src2),
1344 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1346 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1348 VEX_4V, Sched<[WriteShuffle]>;
1349 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1350 (ins VR128:$src1, VR128:$src2),
1351 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1353 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 VEX_4V, Sched<[WriteShuffle]>;
1357 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1358 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1359 (ins VR128:$src1, VR128:$src2),
1360 "movlhps\t{$src2, $dst|$dst, $src2}",
1362 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1363 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1364 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1365 (ins VR128:$src1, VR128:$src2),
1366 "movhlps\t{$src2, $dst|$dst, $src2}",
1368 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1369 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1372 let Predicates = [UseAVX] in {
1374 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1375 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1376 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1377 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1380 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1381 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1384 let Predicates = [UseSSE1] in {
1386 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1387 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1388 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1389 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1392 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1393 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1396 //===----------------------------------------------------------------------===//
1397 // SSE 1 & 2 - Conversion Instructions
1398 //===----------------------------------------------------------------------===//
1400 def SSE_CVT_PD : OpndItins<
1401 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1404 let Sched = WriteCvtI2F in
1405 def SSE_CVT_PS : OpndItins<
1406 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1409 let Sched = WriteCvtI2F in
1410 def SSE_CVT_Scalar : OpndItins<
1411 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1414 let Sched = WriteCvtF2I in
1415 def SSE_CVT_SS2SI_32 : OpndItins<
1416 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1419 let Sched = WriteCvtF2I in
1420 def SSE_CVT_SS2SI_64 : OpndItins<
1421 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1424 let Sched = WriteCvtF2I in
1425 def SSE_CVT_SD2SI : OpndItins<
1426 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1429 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1431 string asm, OpndItins itins> {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1433 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1434 itins.rr>, Sched<[itins.Sched]>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1436 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1437 itins.rm>, Sched<[itins.Sched.Folded]>;
1440 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1441 X86MemOperand x86memop, string asm, Domain d,
1443 let neverHasSideEffects = 1 in {
1444 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1445 [], itins.rr, d>, Sched<[itins.Sched]>;
1447 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1448 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1452 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1453 X86MemOperand x86memop, string asm> {
1454 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1455 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1456 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1457 Sched<[WriteCvtI2F]>;
1459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1460 (ins DstRC:$src1, x86memop:$src),
1461 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1462 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1463 } // neverHasSideEffects = 1
1466 let Predicates = [UseAVX] in {
1467 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1468 "cvttss2si\t{$src, $dst|$dst, $src}",
1471 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1472 "cvttss2si\t{$src, $dst|$dst, $src}",
1474 XS, VEX, VEX_W, VEX_LIG;
1475 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1476 "cvttsd2si\t{$src, $dst|$dst, $src}",
1479 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1480 "cvttsd2si\t{$src, $dst|$dst, $src}",
1482 XD, VEX, VEX_W, VEX_LIG;
1484 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1485 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1486 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1487 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1488 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1489 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1490 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1491 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1492 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1493 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1494 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1495 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1496 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1497 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1498 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1499 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1501 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1502 // register, but the same isn't true when only using memory operands,
1503 // provide other assembly "l" and "q" forms to address this explicitly
1504 // where appropriate to do so.
1505 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1506 XS, VEX_4V, VEX_LIG;
1507 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1508 XS, VEX_4V, VEX_W, VEX_LIG;
1509 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1510 XD, VEX_4V, VEX_LIG;
1511 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1512 XD, VEX_4V, VEX_W, VEX_LIG;
1514 let Predicates = [UseAVX] in {
1515 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1516 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1517 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1518 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1520 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1521 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1522 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1523 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1524 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1525 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1526 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1527 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1529 def : Pat<(f32 (sint_to_fp GR32:$src)),
1530 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1531 def : Pat<(f32 (sint_to_fp GR64:$src)),
1532 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1533 def : Pat<(f64 (sint_to_fp GR32:$src)),
1534 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1535 def : Pat<(f64 (sint_to_fp GR64:$src)),
1536 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1539 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1540 "cvttss2si\t{$src, $dst|$dst, $src}",
1541 SSE_CVT_SS2SI_32>, XS;
1542 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1543 "cvttss2si\t{$src, $dst|$dst, $src}",
1544 SSE_CVT_SS2SI_64>, XS, REX_W;
1545 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1546 "cvttsd2si\t{$src, $dst|$dst, $src}",
1548 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1549 "cvttsd2si\t{$src, $dst|$dst, $src}",
1550 SSE_CVT_SD2SI>, XD, REX_W;
1551 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1552 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1553 SSE_CVT_Scalar>, XS;
1554 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1555 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1556 SSE_CVT_Scalar>, XS, REX_W;
1557 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1558 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1559 SSE_CVT_Scalar>, XD;
1560 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1561 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1562 SSE_CVT_Scalar>, XD, REX_W;
1564 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1565 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1566 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1567 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1568 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1569 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1570 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1571 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1572 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1573 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1574 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1575 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1576 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1577 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1578 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1579 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1581 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1582 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1583 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1584 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1586 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1587 // and/or XMM operand(s).
1589 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1590 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1591 string asm, OpndItins itins> {
1592 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1593 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1594 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1595 Sched<[itins.Sched]>;
1596 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1597 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1598 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1599 Sched<[itins.Sched.Folded]>;
1602 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1603 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1604 PatFrag ld_frag, string asm, OpndItins itins,
1606 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1608 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1609 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1610 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1611 itins.rr>, Sched<[itins.Sched]>;
1612 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1613 (ins DstRC:$src1, x86memop:$src2),
1615 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1616 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1617 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1618 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1621 let Predicates = [UseAVX] in {
1622 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1623 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1624 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1625 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1626 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1627 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1629 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1630 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1631 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1632 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1635 let Predicates = [UseAVX] in {
1636 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1637 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1638 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1639 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1640 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1641 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1643 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1644 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1645 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1646 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1647 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1648 SSE_CVT_Scalar, 0>, XD,
1651 let Constraints = "$src1 = $dst" in {
1652 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1653 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1654 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1655 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1656 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1657 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1658 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1659 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1660 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1661 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1662 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1663 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1668 // Aliases for intrinsics
1669 let Predicates = [UseAVX] in {
1670 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1671 ssmem, sse_load_f32, "cvttss2si",
1672 SSE_CVT_SS2SI_32>, XS, VEX;
1673 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1674 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1675 "cvttss2si", SSE_CVT_SS2SI_64>,
1677 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1678 sdmem, sse_load_f64, "cvttsd2si",
1679 SSE_CVT_SD2SI>, XD, VEX;
1680 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1681 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1682 "cvttsd2si", SSE_CVT_SD2SI>,
1685 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1686 ssmem, sse_load_f32, "cvttss2si",
1687 SSE_CVT_SS2SI_32>, XS;
1688 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1689 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1690 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1691 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1692 sdmem, sse_load_f64, "cvttsd2si",
1694 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1695 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1696 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1698 let Predicates = [UseAVX] in {
1699 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1700 ssmem, sse_load_f32, "cvtss2si",
1701 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1702 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1703 ssmem, sse_load_f32, "cvtss2si",
1704 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1706 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1707 ssmem, sse_load_f32, "cvtss2si",
1708 SSE_CVT_SS2SI_32>, XS;
1709 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1710 ssmem, sse_load_f32, "cvtss2si",
1711 SSE_CVT_SS2SI_64>, XS, REX_W;
1713 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1714 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1715 SSEPackedSingle, SSE_CVT_PS>,
1716 TB, VEX, Requires<[HasAVX]>;
1717 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1718 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1719 SSEPackedSingle, SSE_CVT_PS>,
1720 TB, VEX, VEX_L, Requires<[HasAVX]>;
1722 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1723 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1724 SSEPackedSingle, SSE_CVT_PS>,
1725 TB, Requires<[UseSSE2]>;
1727 let Predicates = [UseAVX] in {
1728 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1729 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1730 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1731 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1732 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1733 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1734 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1735 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1736 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1737 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1738 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1739 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1740 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1741 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1742 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1743 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1746 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1747 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1748 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1749 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1750 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1751 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1752 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1753 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1754 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1755 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1756 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1757 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1758 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1759 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1760 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1761 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1765 // Convert scalar double to scalar single
1766 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1767 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1768 (ins FR64:$src1, FR64:$src2),
1769 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1770 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1771 Sched<[WriteCvtF2F]>;
1773 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1774 (ins FR64:$src1, f64mem:$src2),
1775 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1776 [], IIC_SSE_CVT_Scalar_RM>,
1777 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1778 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1781 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1784 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1785 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1786 [(set FR32:$dst, (fround FR64:$src))],
1787 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1788 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1789 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1790 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1791 IIC_SSE_CVT_Scalar_RM>,
1793 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1795 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1796 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1797 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1799 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1800 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1801 Sched<[WriteCvtF2F]>;
1802 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1803 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1804 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1805 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1806 VR128:$src1, sse_load_f64:$src2))],
1807 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1808 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1810 let Constraints = "$src1 = $dst" in {
1811 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1812 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1813 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1815 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1816 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1817 Sched<[WriteCvtF2F]>;
1818 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1819 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1820 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1821 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1822 VR128:$src1, sse_load_f64:$src2))],
1823 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1824 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1827 // Convert scalar single to scalar double
1828 // SSE2 instructions with XS prefix
1829 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1830 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1831 (ins FR32:$src1, FR32:$src2),
1832 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1833 [], IIC_SSE_CVT_Scalar_RR>,
1834 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1835 Sched<[WriteCvtF2F]>;
1837 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1838 (ins FR32:$src1, f32mem:$src2),
1839 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1840 [], IIC_SSE_CVT_Scalar_RM>,
1841 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1842 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1845 def : Pat<(f64 (fextend FR32:$src)),
1846 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1847 def : Pat<(fextend (loadf32 addr:$src)),
1848 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1850 def : Pat<(extloadf32 addr:$src),
1851 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1852 Requires<[UseAVX, OptForSize]>;
1853 def : Pat<(extloadf32 addr:$src),
1854 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1855 Requires<[UseAVX, OptForSpeed]>;
1857 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1858 "cvtss2sd\t{$src, $dst|$dst, $src}",
1859 [(set FR64:$dst, (fextend FR32:$src))],
1860 IIC_SSE_CVT_Scalar_RR>, XS,
1861 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1862 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1863 "cvtss2sd\t{$src, $dst|$dst, $src}",
1864 [(set FR64:$dst, (extloadf32 addr:$src))],
1865 IIC_SSE_CVT_Scalar_RM>, XS,
1866 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1868 // extload f32 -> f64. This matches load+fextend because we have a hack in
1869 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1871 // Since these loads aren't folded into the fextend, we have to match it
1873 def : Pat<(fextend (loadf32 addr:$src)),
1874 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1875 def : Pat<(extloadf32 addr:$src),
1876 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1878 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1879 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1880 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1882 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1883 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1884 Sched<[WriteCvtF2F]>;
1885 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1886 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1889 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1890 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1891 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1892 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1893 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1894 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1895 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1897 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1898 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1899 Sched<[WriteCvtF2F]>;
1900 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1901 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1902 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1904 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1905 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1906 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1909 // Convert packed single/double fp to doubleword
1910 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvtps2dq\t{$src, $dst|$dst, $src}",
1912 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1913 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1914 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1915 "cvtps2dq\t{$src, $dst|$dst, $src}",
1917 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1918 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1919 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1920 "cvtps2dq\t{$src, $dst|$dst, $src}",
1922 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1923 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1924 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1925 "cvtps2dq\t{$src, $dst|$dst, $src}",
1927 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1928 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1929 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1930 "cvtps2dq\t{$src, $dst|$dst, $src}",
1931 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1932 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1933 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1934 "cvtps2dq\t{$src, $dst|$dst, $src}",
1936 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1937 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1940 // Convert Packed Double FP to Packed DW Integers
1941 let Predicates = [HasAVX] in {
1942 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1943 // register, but the same isn't true when using memory operands instead.
1944 // Provide other assembly rr and rm forms to address this explicitly.
1945 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1946 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1947 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1948 VEX, Sched<[WriteCvtF2I]>;
1951 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1952 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1953 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1954 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1956 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
1957 Sched<[WriteCvtF2ILd]>;
1960 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1961 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1963 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
1964 Sched<[WriteCvtF2I]>;
1965 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1966 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1968 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
1969 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1970 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1971 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1974 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1975 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1977 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1978 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
1979 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1980 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1981 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1982 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
1984 // Convert with truncation packed single/double fp to doubleword
1985 // SSE2 packed instructions with XS prefix
1986 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvttps2dq\t{$src, $dst|$dst, $src}",
1989 (int_x86_sse2_cvttps2dq VR128:$src))],
1990 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1991 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1992 "cvttps2dq\t{$src, $dst|$dst, $src}",
1993 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1994 (loadv4f32 addr:$src)))],
1995 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1996 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1997 "cvttps2dq\t{$src, $dst|$dst, $src}",
1999 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2000 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2001 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2002 "cvttps2dq\t{$src, $dst|$dst, $src}",
2003 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2004 (loadv8f32 addr:$src)))],
2005 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2006 Sched<[WriteCvtF2ILd]>;
2008 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2009 "cvttps2dq\t{$src, $dst|$dst, $src}",
2010 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2011 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2012 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2013 "cvttps2dq\t{$src, $dst|$dst, $src}",
2015 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2016 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2018 let Predicates = [HasAVX] in {
2019 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2020 (VCVTDQ2PSrr VR128:$src)>;
2021 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2022 (VCVTDQ2PSrm addr:$src)>;
2024 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2025 (VCVTDQ2PSrr VR128:$src)>;
2026 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2027 (VCVTDQ2PSrm addr:$src)>;
2029 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2030 (VCVTTPS2DQrr VR128:$src)>;
2031 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2032 (VCVTTPS2DQrm addr:$src)>;
2034 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2035 (VCVTDQ2PSYrr VR256:$src)>;
2036 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2037 (VCVTDQ2PSYrm addr:$src)>;
2039 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2040 (VCVTTPS2DQYrr VR256:$src)>;
2041 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2042 (VCVTTPS2DQYrm addr:$src)>;
2045 let Predicates = [UseSSE2] in {
2046 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2047 (CVTDQ2PSrr VR128:$src)>;
2048 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2049 (CVTDQ2PSrm addr:$src)>;
2051 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2052 (CVTDQ2PSrr VR128:$src)>;
2053 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2054 (CVTDQ2PSrm addr:$src)>;
2056 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2057 (CVTTPS2DQrr VR128:$src)>;
2058 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2059 (CVTTPS2DQrm addr:$src)>;
2062 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2063 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2065 (int_x86_sse2_cvttpd2dq VR128:$src))],
2066 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2068 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2069 // register, but the same isn't true when using memory operands instead.
2070 // Provide other assembly rr and rm forms to address this explicitly.
2073 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2074 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
2075 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2076 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2077 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2078 (loadv2f64 addr:$src)))],
2079 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2082 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2083 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2085 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2086 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2087 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2088 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2090 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2091 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2092 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2093 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2095 let Predicates = [HasAVX] in {
2096 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2097 (VCVTTPD2DQYrr VR256:$src)>;
2098 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2099 (VCVTTPD2DQYrm addr:$src)>;
2100 } // Predicates = [HasAVX]
2102 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2103 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2104 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2105 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2106 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2107 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2108 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2109 (memopv2f64 addr:$src)))],
2111 Sched<[WriteCvtF2ILd]>;
2113 // Convert packed single to packed double
2114 let Predicates = [HasAVX] in {
2115 // SSE2 instructions without OpSize prefix
2116 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2117 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2118 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2119 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2120 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2121 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2122 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2123 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2124 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2125 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2127 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2128 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2129 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2130 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2132 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2133 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2136 let Predicates = [UseSSE2] in {
2137 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2138 "cvtps2pd\t{$src, $dst|$dst, $src}",
2139 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2140 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2141 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2142 "cvtps2pd\t{$src, $dst|$dst, $src}",
2143 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2144 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2147 // Convert Packed DW Integers to Packed Double FP
2148 let Predicates = [HasAVX] in {
2149 let neverHasSideEffects = 1, mayLoad = 1 in
2150 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2151 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2152 []>, VEX, Sched<[WriteCvtI2FLd]>;
2153 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2154 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2156 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2157 Sched<[WriteCvtI2F]>;
2158 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2159 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2161 (int_x86_avx_cvtdq2_pd_256
2162 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2163 Sched<[WriteCvtI2FLd]>;
2164 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2165 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2167 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2168 Sched<[WriteCvtI2F]>;
2171 let neverHasSideEffects = 1, mayLoad = 1 in
2172 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2173 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2174 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2175 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2180 // AVX 256-bit register conversion intrinsics
2181 let Predicates = [HasAVX] in {
2182 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2183 (VCVTDQ2PDYrr VR128:$src)>;
2184 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2185 (VCVTDQ2PDYrm addr:$src)>;
2186 } // Predicates = [HasAVX]
2188 // Convert packed double to packed single
2189 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2190 // register, but the same isn't true when using memory operands instead.
2191 // Provide other assembly rr and rm forms to address this explicitly.
2192 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2193 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2194 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2195 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2198 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2199 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2200 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2201 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2203 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2204 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2207 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2208 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2210 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2211 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2212 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2213 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2215 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2216 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2217 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2218 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2220 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2221 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2222 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2223 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2224 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2225 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2227 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2228 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2231 // AVX 256-bit register conversion intrinsics
2232 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2233 // whenever possible to avoid declaring two versions of each one.
2234 let Predicates = [HasAVX] in {
2235 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2236 (VCVTDQ2PSYrr VR256:$src)>;
2237 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2238 (VCVTDQ2PSYrm addr:$src)>;
2240 // Match fround and fextend for 128/256-bit conversions
2241 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2242 (VCVTPD2PSrr VR128:$src)>;
2243 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2244 (VCVTPD2PSXrm addr:$src)>;
2245 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2246 (VCVTPD2PSYrr VR256:$src)>;
2247 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2248 (VCVTPD2PSYrm addr:$src)>;
2250 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2251 (VCVTPS2PDrr VR128:$src)>;
2252 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2253 (VCVTPS2PDYrr VR128:$src)>;
2254 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2255 (VCVTPS2PDYrm addr:$src)>;
2258 let Predicates = [UseSSE2] in {
2259 // Match fround and fextend for 128 conversions
2260 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2261 (CVTPD2PSrr VR128:$src)>;
2262 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2263 (CVTPD2PSrm addr:$src)>;
2265 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2266 (CVTPS2PDrr VR128:$src)>;
2269 //===----------------------------------------------------------------------===//
2270 // SSE 1 & 2 - Compare Instructions
2271 //===----------------------------------------------------------------------===//
2273 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2274 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2275 Operand CC, SDNode OpNode, ValueType VT,
2276 PatFrag ld_frag, string asm, string asm_alt,
2278 def rr : SIi8<0xC2, MRMSrcReg,
2279 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2280 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2281 itins.rr>, Sched<[itins.Sched]>;
2282 def rm : SIi8<0xC2, MRMSrcMem,
2283 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2284 [(set RC:$dst, (OpNode (VT RC:$src1),
2285 (ld_frag addr:$src2), imm:$cc))],
2287 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2289 // Accept explicit immediate argument form instead of comparison code.
2290 let neverHasSideEffects = 1 in {
2291 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2292 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2293 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2295 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2296 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2297 IIC_SSE_ALU_F32S_RM>,
2298 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2302 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2303 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2304 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2306 XS, VEX_4V, VEX_LIG;
2307 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2308 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2309 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2310 SSE_ALU_F32S>, // same latency as 32 bit compare
2311 XD, VEX_4V, VEX_LIG;
2313 let Constraints = "$src1 = $dst" in {
2314 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2315 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2316 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2318 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2319 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2320 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2325 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2326 Intrinsic Int, string asm, OpndItins itins> {
2327 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2328 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2329 [(set VR128:$dst, (Int VR128:$src1,
2330 VR128:$src, imm:$cc))],
2332 Sched<[itins.Sched]>;
2333 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2334 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2335 [(set VR128:$dst, (Int VR128:$src1,
2336 (load addr:$src), imm:$cc))],
2338 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2341 // Aliases to match intrinsics which expect XMM operand(s).
2342 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2343 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2346 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2347 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2348 SSE_ALU_F32S>, // same latency as f32
2350 let Constraints = "$src1 = $dst" in {
2351 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2352 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2354 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2355 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2361 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2362 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2363 ValueType vt, X86MemOperand x86memop,
2364 PatFrag ld_frag, string OpcodeStr> {
2365 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2366 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2367 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2370 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2371 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2372 [(set EFLAGS, (OpNode (vt RC:$src1),
2373 (ld_frag addr:$src2)))],
2375 Sched<[WriteFAddLd, ReadAfterLd]>;
2378 let Defs = [EFLAGS] in {
2379 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2380 "ucomiss">, TB, VEX, VEX_LIG;
2381 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2382 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2383 let Pattern = []<dag> in {
2384 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2385 "comiss">, TB, VEX, VEX_LIG;
2386 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2387 "comisd">, TB, OpSize, VEX, VEX_LIG;
2390 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2391 load, "ucomiss">, TB, VEX;
2392 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2393 load, "ucomisd">, TB, OpSize, VEX;
2395 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2396 load, "comiss">, TB, VEX;
2397 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2398 load, "comisd">, TB, OpSize, VEX;
2399 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2401 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2402 "ucomisd">, TB, OpSize;
2404 let Pattern = []<dag> in {
2405 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2407 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2408 "comisd">, TB, OpSize;
2411 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2412 load, "ucomiss">, TB;
2413 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2414 load, "ucomisd">, TB, OpSize;
2416 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2418 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2419 "comisd">, TB, OpSize;
2420 } // Defs = [EFLAGS]
2422 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2423 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2424 Operand CC, Intrinsic Int, string asm,
2425 string asm_alt, Domain d,
2426 OpndItins itins = SSE_ALU_F32P> {
2427 def rri : PIi8<0xC2, MRMSrcReg,
2428 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2429 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2432 def rmi : PIi8<0xC2, MRMSrcMem,
2433 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2434 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2436 Sched<[WriteFAddLd, ReadAfterLd]>;
2438 // Accept explicit immediate argument form instead of comparison code.
2439 let neverHasSideEffects = 1 in {
2440 def rri_alt : PIi8<0xC2, MRMSrcReg,
2441 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2442 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2443 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2444 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2445 asm_alt, [], itins.rm, d>,
2446 Sched<[WriteFAddLd, ReadAfterLd]>;
2450 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2451 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2452 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2453 SSEPackedSingle>, TB, VEX_4V;
2454 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2455 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2456 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2457 SSEPackedDouble>, TB, OpSize, VEX_4V;
2458 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2459 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2460 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2461 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2462 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2463 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2464 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2465 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2466 let Constraints = "$src1 = $dst" in {
2467 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2468 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2469 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2470 SSEPackedSingle, SSE_ALU_F32P>, TB;
2471 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2472 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2473 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2474 SSEPackedDouble, SSE_ALU_F64P>, TB, OpSize;
2477 let Predicates = [HasAVX] in {
2478 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2479 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2480 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2481 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2482 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2483 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2484 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2485 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2487 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2488 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2489 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2490 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2491 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2492 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2493 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2494 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2497 let Predicates = [UseSSE1] in {
2498 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2499 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2500 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2501 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2504 let Predicates = [UseSSE2] in {
2505 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2506 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2507 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2508 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2511 //===----------------------------------------------------------------------===//
2512 // SSE 1 & 2 - Shuffle Instructions
2513 //===----------------------------------------------------------------------===//
2515 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2516 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2517 ValueType vt, string asm, PatFrag mem_frag,
2518 Domain d, bit IsConvertibleToThreeAddress = 0> {
2519 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2520 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2521 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2522 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2523 Sched<[WriteShuffleLd, ReadAfterLd]>;
2524 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2525 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2526 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2527 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2528 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2529 Sched<[WriteShuffle]>;
2532 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2533 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2534 loadv4f32, SSEPackedSingle>, TB, VEX_4V;
2535 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2536 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2537 loadv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2538 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2539 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2540 loadv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2541 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2542 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2543 loadv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2545 let Constraints = "$src1 = $dst" in {
2546 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2547 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2548 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2550 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2551 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2552 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2556 let Predicates = [HasAVX] in {
2557 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2558 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2559 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2560 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2561 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2563 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2564 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2565 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2566 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2567 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2570 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2571 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2572 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2573 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2574 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2576 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2577 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2578 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2579 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2580 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2583 let Predicates = [UseSSE1] in {
2584 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2585 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2586 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2587 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2588 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2591 let Predicates = [UseSSE2] in {
2592 // Generic SHUFPD patterns
2593 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2594 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2595 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2596 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2597 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2600 //===----------------------------------------------------------------------===//
2601 // SSE 1 & 2 - Unpack Instructions
2602 //===----------------------------------------------------------------------===//
2604 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2605 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2606 PatFrag mem_frag, RegisterClass RC,
2607 X86MemOperand x86memop, string asm,
2609 def rr : PI<opc, MRMSrcReg,
2610 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2612 (vt (OpNode RC:$src1, RC:$src2)))],
2613 IIC_SSE_UNPCK, d>, Sched<[WriteShuffle]>;
2614 def rm : PI<opc, MRMSrcMem,
2615 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2617 (vt (OpNode RC:$src1,
2618 (mem_frag addr:$src2))))],
2620 Sched<[WriteShuffleLd, ReadAfterLd]>;
2623 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2624 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2625 SSEPackedSingle>, TB, VEX_4V;
2626 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2627 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2628 SSEPackedDouble>, TB, OpSize, VEX_4V;
2629 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2630 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2631 SSEPackedSingle>, TB, VEX_4V;
2632 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2633 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2634 SSEPackedDouble>, TB, OpSize, VEX_4V;
2636 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2637 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2638 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2639 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2640 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2641 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2642 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2643 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2644 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2645 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2646 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2647 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2649 let Constraints = "$src1 = $dst" in {
2650 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2651 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2652 SSEPackedSingle>, TB;
2653 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2654 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2655 SSEPackedDouble>, TB, OpSize;
2656 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2657 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2658 SSEPackedSingle>, TB;
2659 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2660 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2661 SSEPackedDouble>, TB, OpSize;
2662 } // Constraints = "$src1 = $dst"
2664 let Predicates = [HasAVX1Only] in {
2665 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2666 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2667 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2668 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2669 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2670 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2671 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2672 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2674 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2675 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2676 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2677 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2678 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2679 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2680 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2681 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2684 let Predicates = [HasAVX] in {
2685 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2686 // problem is during lowering, where it's not possible to recognize the load
2687 // fold cause it has two uses through a bitcast. One use disappears at isel
2688 // time and the fold opportunity reappears.
2689 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2690 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2693 let Predicates = [UseSSE2] in {
2694 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2695 // problem is during lowering, where it's not possible to recognize the load
2696 // fold cause it has two uses through a bitcast. One use disappears at isel
2697 // time and the fold opportunity reappears.
2698 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2699 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2702 //===----------------------------------------------------------------------===//
2703 // SSE 1 & 2 - Extract Floating-Point Sign mask
2704 //===----------------------------------------------------------------------===//
2706 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2707 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2709 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2710 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2711 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2712 Sched<[WriteVecLogic]>;
2715 let Predicates = [HasAVX] in {
2716 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2717 "movmskps", SSEPackedSingle>, TB, VEX;
2718 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2719 "movmskpd", SSEPackedDouble>, TB,
2721 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2722 "movmskps", SSEPackedSingle>, TB,
2724 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2725 "movmskpd", SSEPackedDouble>, TB,
2728 def : Pat<(i32 (X86fgetsign FR32:$src)),
2729 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2730 def : Pat<(i64 (X86fgetsign FR32:$src)),
2731 (SUBREG_TO_REG (i64 0),
2732 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2733 def : Pat<(i32 (X86fgetsign FR64:$src)),
2734 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2735 def : Pat<(i64 (X86fgetsign FR64:$src)),
2736 (SUBREG_TO_REG (i64 0),
2737 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2740 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2741 SSEPackedSingle>, TB;
2742 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2743 SSEPackedDouble>, TB, OpSize;
2745 def : Pat<(i32 (X86fgetsign FR32:$src)),
2746 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2747 Requires<[UseSSE1]>;
2748 def : Pat<(i64 (X86fgetsign FR32:$src)),
2749 (SUBREG_TO_REG (i64 0),
2750 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2751 Requires<[UseSSE1]>;
2752 def : Pat<(i32 (X86fgetsign FR64:$src)),
2753 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2754 Requires<[UseSSE2]>;
2755 def : Pat<(i64 (X86fgetsign FR64:$src)),
2756 (SUBREG_TO_REG (i64 0),
2757 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2758 Requires<[UseSSE2]>;
2760 //===---------------------------------------------------------------------===//
2761 // SSE2 - Packed Integer Logical Instructions
2762 //===---------------------------------------------------------------------===//
2764 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2766 /// PDI_binop_rm - Simple SSE2 binary operator.
2767 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2768 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2769 X86MemOperand x86memop, OpndItins itins,
2770 bit IsCommutable, bit Is2Addr> {
2771 let isCommutable = IsCommutable in
2772 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2773 (ins RC:$src1, RC:$src2),
2775 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2776 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2777 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2778 Sched<[itins.Sched]>;
2779 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2780 (ins RC:$src1, x86memop:$src2),
2782 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2783 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2784 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2785 (bitconvert (memop_frag addr:$src2)))))],
2787 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2789 } // ExeDomain = SSEPackedInt
2791 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2792 ValueType OpVT128, ValueType OpVT256,
2793 OpndItins itins, bit IsCommutable = 0> {
2794 let Predicates = [HasAVX] in
2795 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2796 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2798 let Constraints = "$src1 = $dst" in
2799 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2800 memopv2i64, i128mem, itins, IsCommutable, 1>;
2802 let Predicates = [HasAVX2] in
2803 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2804 OpVT256, VR256, loadv4i64, i256mem, itins,
2805 IsCommutable, 0>, VEX_4V, VEX_L;
2808 // These are ordered here for pattern ordering requirements with the fp versions
2810 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2811 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2812 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2813 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2814 SSE_BIT_ITINS_P, 0>;
2816 //===----------------------------------------------------------------------===//
2817 // SSE 1 & 2 - Logical Instructions
2818 //===----------------------------------------------------------------------===//
2820 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2822 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2823 SDNode OpNode, OpndItins itins> {
2824 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2825 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2828 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2829 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2832 let Constraints = "$src1 = $dst" in {
2833 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2834 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2837 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2838 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2843 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2844 let isCodeGenOnly = 1 in {
2845 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2847 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2849 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2852 let isCommutable = 0 in
2853 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2857 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2859 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2861 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2862 !strconcat(OpcodeStr, "ps"), f256mem,
2863 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2864 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2865 (loadv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2867 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2868 !strconcat(OpcodeStr, "pd"), f256mem,
2869 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2870 (bc_v4i64 (v4f64 VR256:$src2))))],
2871 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2872 (loadv4i64 addr:$src2)))], 0>,
2873 TB, OpSize, VEX_4V, VEX_L;
2875 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2876 // are all promoted to v2i64, and the patterns are covered by the int
2877 // version. This is needed in SSE only, because v2i64 isn't supported on
2878 // SSE1, but only on SSE2.
2879 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2880 !strconcat(OpcodeStr, "ps"), f128mem, [],
2881 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2882 (loadv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2884 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2885 !strconcat(OpcodeStr, "pd"), f128mem,
2886 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2887 (bc_v2i64 (v2f64 VR128:$src2))))],
2888 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2889 (loadv2i64 addr:$src2)))], 0>,
2892 let Constraints = "$src1 = $dst" in {
2893 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2894 !strconcat(OpcodeStr, "ps"), f128mem,
2895 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2896 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2897 (memopv2i64 addr:$src2)))]>, TB;
2899 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2900 !strconcat(OpcodeStr, "pd"), f128mem,
2901 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2902 (bc_v2i64 (v2f64 VR128:$src2))))],
2903 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2904 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2908 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2909 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2910 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2911 let isCommutable = 0 in
2912 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2914 //===----------------------------------------------------------------------===//
2915 // SSE 1 & 2 - Arithmetic Instructions
2916 //===----------------------------------------------------------------------===//
2918 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2921 /// In addition, we also have a special variant of the scalar form here to
2922 /// represent the associated intrinsic operation. This form is unlike the
2923 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2924 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2926 /// These three forms can each be reg+reg or reg+mem.
2929 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2931 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2932 SDNode OpNode, SizeItins itins> {
2933 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2934 VR128, v4f32, f128mem, loadv4f32,
2935 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2936 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2937 VR128, v2f64, f128mem, loadv2f64,
2938 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2940 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2941 OpNode, VR256, v8f32, f256mem, loadv8f32,
2942 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2943 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2944 OpNode, VR256, v4f64, f256mem, loadv4f64,
2945 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2947 let Constraints = "$src1 = $dst" in {
2948 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2949 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2951 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2952 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2953 itins.d>, TB, OpSize;
2957 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2959 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2960 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
2961 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2962 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
2964 let Constraints = "$src1 = $dst" in {
2965 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2966 OpNode, FR32, f32mem, itins.s>, XS;
2967 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2968 OpNode, FR64, f64mem, itins.d>, XD;
2972 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2974 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2975 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2976 itins.s, 0>, XS, VEX_4V, VEX_LIG;
2977 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2978 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2979 itins.d, 0>, XD, VEX_4V, VEX_LIG;
2981 let Constraints = "$src1 = $dst" in {
2982 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2983 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2985 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2986 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2991 // Binary Arithmetic instructions
2992 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2993 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2994 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2995 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2996 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2997 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2998 let isCommutable = 0 in {
2999 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3000 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3001 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3002 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3003 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3004 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3005 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3006 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3007 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3008 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3009 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3010 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3013 let isCodeGenOnly = 1 in {
3014 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3015 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3016 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3017 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3021 /// In addition, we also have a special variant of the scalar form here to
3022 /// represent the associated intrinsic operation. This form is unlike the
3023 /// plain scalar form, in that it takes an entire vector (instead of a
3024 /// scalar) and leaves the top elements undefined.
3026 /// And, we have a special variant form for a full-vector intrinsic form.
3028 let Sched = WriteFSqrt in {
3029 def SSE_SQRTPS : OpndItins<
3030 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3033 def SSE_SQRTSS : OpndItins<
3034 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3037 def SSE_SQRTPD : OpndItins<
3038 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3041 def SSE_SQRTSD : OpndItins<
3042 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3046 let Sched = WriteFRcp in {
3047 def SSE_RCPP : OpndItins<
3048 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3051 def SSE_RCPS : OpndItins<
3052 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3056 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3057 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3058 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3059 let Predicates = [HasAVX], hasSideEffects = 0 in {
3060 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3061 (ins FR32:$src1, FR32:$src2),
3062 !strconcat("v", OpcodeStr,
3063 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3064 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3065 let mayLoad = 1 in {
3066 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3067 (ins FR32:$src1,f32mem:$src2),
3068 !strconcat("v", OpcodeStr,
3069 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3070 []>, VEX_4V, VEX_LIG,
3071 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3072 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3073 (ins VR128:$src1, ssmem:$src2),
3074 !strconcat("v", OpcodeStr,
3075 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3076 []>, VEX_4V, VEX_LIG,
3077 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3081 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3082 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3083 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3084 // For scalar unary operations, fold a load into the operation
3085 // only in OptForSize mode. It eliminates an instruction, but it also
3086 // eliminates a whole-register clobber (the load), so it introduces a
3087 // partial register update condition.
3088 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3089 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3090 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3091 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3092 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3093 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3094 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3095 Sched<[itins.Sched]>;
3096 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3097 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3098 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3099 Sched<[itins.Sched.Folded]>;
3102 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3103 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3105 let Predicates = [HasAVX], hasSideEffects = 0 in {
3106 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3107 (ins FR32:$src1, FR32:$src2),
3108 !strconcat("v", OpcodeStr,
3109 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3110 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3111 let mayLoad = 1 in {
3112 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3113 (ins FR32:$src1,f32mem:$src2),
3114 !strconcat("v", OpcodeStr,
3115 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3116 []>, VEX_4V, VEX_LIG,
3117 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3118 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3119 (ins VR128:$src1, ssmem:$src2),
3120 !strconcat("v", OpcodeStr,
3121 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3122 []>, VEX_4V, VEX_LIG,
3123 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3127 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3128 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3129 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3130 // For scalar unary operations, fold a load into the operation
3131 // only in OptForSize mode. It eliminates an instruction, but it also
3132 // eliminates a whole-register clobber (the load), so it introduces a
3133 // partial register update condition.
3134 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3135 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3136 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3137 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3138 let Constraints = "$src1 = $dst" in {
3139 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3140 (ins VR128:$src1, VR128:$src2),
3141 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3142 [], itins.rr>, Sched<[itins.Sched]>;
3143 let mayLoad = 1, hasSideEffects = 0 in
3144 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3145 (ins VR128:$src1, ssmem:$src2),
3146 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3147 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3151 /// sse1_fp_unop_p - SSE1 unops in packed form.
3152 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3154 let Predicates = [HasAVX] in {
3155 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3156 !strconcat("v", OpcodeStr,
3157 "ps\t{$src, $dst|$dst, $src}"),
3158 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3159 itins.rr>, VEX, Sched<[itins.Sched]>;
3160 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3161 !strconcat("v", OpcodeStr,
3162 "ps\t{$src, $dst|$dst, $src}"),
3163 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3164 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3165 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3166 !strconcat("v", OpcodeStr,
3167 "ps\t{$src, $dst|$dst, $src}"),
3168 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3169 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3170 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3171 !strconcat("v", OpcodeStr,
3172 "ps\t{$src, $dst|$dst, $src}"),
3173 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3174 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3177 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3178 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3179 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3180 Sched<[itins.Sched]>;
3181 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3182 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3183 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3184 Sched<[itins.Sched.Folded]>;
3187 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3188 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3189 Intrinsic V4F32Int, Intrinsic V8F32Int,
3191 let Predicates = [HasAVX] in {
3192 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3193 !strconcat("v", OpcodeStr,
3194 "ps\t{$src, $dst|$dst, $src}"),
3195 [(set VR128:$dst, (V4F32Int VR128:$src))],
3196 itins.rr>, VEX, Sched<[itins.Sched]>;
3197 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3198 !strconcat("v", OpcodeStr,
3199 "ps\t{$src, $dst|$dst, $src}"),
3200 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3201 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3202 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3203 !strconcat("v", OpcodeStr,
3204 "ps\t{$src, $dst|$dst, $src}"),
3205 [(set VR256:$dst, (V8F32Int VR256:$src))],
3206 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3207 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3209 !strconcat("v", OpcodeStr,
3210 "ps\t{$src, $dst|$dst, $src}"),
3211 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3212 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3215 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3216 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3217 [(set VR128:$dst, (V4F32Int VR128:$src))],
3218 itins.rr>, Sched<[itins.Sched]>;
3219 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3220 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3221 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3222 itins.rm>, Sched<[itins.Sched.Folded]>;
3225 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3226 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3227 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3228 let Predicates = [HasAVX], hasSideEffects = 0 in {
3229 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3230 (ins FR64:$src1, FR64:$src2),
3231 !strconcat("v", OpcodeStr,
3232 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3233 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3234 let mayLoad = 1 in {
3235 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3236 (ins FR64:$src1,f64mem:$src2),
3237 !strconcat("v", OpcodeStr,
3238 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3239 []>, VEX_4V, VEX_LIG,
3240 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3241 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3242 (ins VR128:$src1, sdmem:$src2),
3243 !strconcat("v", OpcodeStr,
3244 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3245 []>, VEX_4V, VEX_LIG,
3246 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3250 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3251 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3252 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3253 Sched<[itins.Sched]>;
3254 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3255 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3256 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3257 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3258 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3259 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3260 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3261 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3262 Sched<[itins.Sched]>;
3263 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3264 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3265 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3266 Sched<[itins.Sched.Folded]>;
3269 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3270 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3271 SDNode OpNode, OpndItins itins> {
3272 let Predicates = [HasAVX] in {
3273 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3274 !strconcat("v", OpcodeStr,
3275 "pd\t{$src, $dst|$dst, $src}"),
3276 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3277 itins.rr>, VEX, Sched<[itins.Sched]>;
3278 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3279 !strconcat("v", OpcodeStr,
3280 "pd\t{$src, $dst|$dst, $src}"),
3281 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3282 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3283 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3284 !strconcat("v", OpcodeStr,
3285 "pd\t{$src, $dst|$dst, $src}"),
3286 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3287 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3288 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3289 !strconcat("v", OpcodeStr,
3290 "pd\t{$src, $dst|$dst, $src}"),
3291 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3292 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3295 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3296 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3297 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3298 Sched<[itins.Sched]>;
3299 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3300 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3301 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3302 Sched<[itins.Sched.Folded]>;
3306 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3308 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3309 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3311 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3313 // Reciprocal approximations. Note that these typically require refinement
3314 // in order to obtain suitable precision.
3315 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3316 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3317 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3318 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3319 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3320 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3321 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3322 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3324 let Predicates = [UseAVX] in {
3325 def : Pat<(f32 (fsqrt FR32:$src)),
3326 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3327 def : Pat<(f32 (fsqrt (load addr:$src))),
3328 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3329 Requires<[HasAVX, OptForSize]>;
3330 def : Pat<(f64 (fsqrt FR64:$src)),
3331 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3332 def : Pat<(f64 (fsqrt (load addr:$src))),
3333 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3334 Requires<[HasAVX, OptForSize]>;
3336 def : Pat<(f32 (X86frsqrt FR32:$src)),
3337 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3338 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3339 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3340 Requires<[HasAVX, OptForSize]>;
3342 def : Pat<(f32 (X86frcp FR32:$src)),
3343 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3344 def : Pat<(f32 (X86frcp (load addr:$src))),
3345 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3346 Requires<[HasAVX, OptForSize]>;
3348 let Predicates = [UseAVX] in {
3349 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3350 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3351 (COPY_TO_REGCLASS VR128:$src, FR32)),
3353 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3354 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3356 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3357 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3358 (COPY_TO_REGCLASS VR128:$src, FR64)),
3360 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3361 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3364 let Predicates = [HasAVX] in {
3365 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3366 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3367 (COPY_TO_REGCLASS VR128:$src, FR32)),
3369 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3370 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3372 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3373 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3374 (COPY_TO_REGCLASS VR128:$src, FR32)),
3376 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3377 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3380 // Reciprocal approximations. Note that these typically require refinement
3381 // in order to obtain suitable precision.
3382 let Predicates = [UseSSE1] in {
3383 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3384 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3385 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3386 (RCPSSr_Int VR128:$src, VR128:$src)>;
3389 // There is no f64 version of the reciprocal approximation instructions.
3391 //===----------------------------------------------------------------------===//
3392 // SSE 1 & 2 - Non-temporal stores
3393 //===----------------------------------------------------------------------===//
3395 let AddedComplexity = 400 in { // Prefer non-temporal versions
3396 let SchedRW = [WriteStore] in {
3397 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3398 (ins f128mem:$dst, VR128:$src),
3399 "movntps\t{$src, $dst|$dst, $src}",
3400 [(alignednontemporalstore (v4f32 VR128:$src),
3402 IIC_SSE_MOVNT>, VEX;
3403 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3404 (ins f128mem:$dst, VR128:$src),
3405 "movntpd\t{$src, $dst|$dst, $src}",
3406 [(alignednontemporalstore (v2f64 VR128:$src),
3408 IIC_SSE_MOVNT>, VEX;
3410 let ExeDomain = SSEPackedInt in
3411 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3412 (ins f128mem:$dst, VR128:$src),
3413 "movntdq\t{$src, $dst|$dst, $src}",
3414 [(alignednontemporalstore (v2i64 VR128:$src),
3416 IIC_SSE_MOVNT>, VEX;
3418 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3419 (ins f256mem:$dst, VR256:$src),
3420 "movntps\t{$src, $dst|$dst, $src}",
3421 [(alignednontemporalstore (v8f32 VR256:$src),
3423 IIC_SSE_MOVNT>, VEX, VEX_L;
3424 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3425 (ins f256mem:$dst, VR256:$src),
3426 "movntpd\t{$src, $dst|$dst, $src}",
3427 [(alignednontemporalstore (v4f64 VR256:$src),
3429 IIC_SSE_MOVNT>, VEX, VEX_L;
3430 let ExeDomain = SSEPackedInt in
3431 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3432 (ins f256mem:$dst, VR256:$src),
3433 "movntdq\t{$src, $dst|$dst, $src}",
3434 [(alignednontemporalstore (v4i64 VR256:$src),
3436 IIC_SSE_MOVNT>, VEX, VEX_L;
3438 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3439 "movntps\t{$src, $dst|$dst, $src}",
3440 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3442 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3443 "movntpd\t{$src, $dst|$dst, $src}",
3444 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3447 let ExeDomain = SSEPackedInt in
3448 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3449 "movntdq\t{$src, $dst|$dst, $src}",
3450 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3453 // There is no AVX form for instructions below this point
3454 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3455 "movnti{l}\t{$src, $dst|$dst, $src}",
3456 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3458 TB, Requires<[HasSSE2]>;
3459 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3460 "movnti{q}\t{$src, $dst|$dst, $src}",
3461 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3463 TB, Requires<[HasSSE2]>;
3464 } // SchedRW = [WriteStore]
3466 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3467 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3469 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3470 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3471 } // AddedComplexity
3473 //===----------------------------------------------------------------------===//
3474 // SSE 1 & 2 - Prefetch and memory fence
3475 //===----------------------------------------------------------------------===//
3477 // Prefetch intrinsic.
3478 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3479 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3480 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3481 IIC_SSE_PREFETCH>, TB;
3482 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3483 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3484 IIC_SSE_PREFETCH>, TB;
3485 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3486 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3487 IIC_SSE_PREFETCH>, TB;
3488 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3489 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3490 IIC_SSE_PREFETCH>, TB;
3493 // FIXME: How should these memory instructions be modeled?
3494 let SchedRW = [WriteLoad] in {
3496 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3497 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3498 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3500 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3501 // was introduced with SSE2, it's backward compatible.
3502 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3503 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3504 REP, Requires<[HasSSE2]>;
3506 // Load, store, and memory fence
3507 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3508 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3509 TB, Requires<[HasSSE1]>;
3510 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3511 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3512 TB, Requires<[HasSSE2]>;
3513 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3514 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3515 TB, Requires<[HasSSE2]>;
3518 def : Pat<(X86SFence), (SFENCE)>;
3519 def : Pat<(X86LFence), (LFENCE)>;
3520 def : Pat<(X86MFence), (MFENCE)>;
3522 //===----------------------------------------------------------------------===//
3523 // SSE 1 & 2 - Load/Store XCSR register
3524 //===----------------------------------------------------------------------===//
3526 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3527 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3528 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3529 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3530 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3531 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3533 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3534 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3535 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3536 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3537 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3538 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3540 //===---------------------------------------------------------------------===//
3541 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3542 //===---------------------------------------------------------------------===//
3544 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3546 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3547 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3548 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3550 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3551 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3553 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3554 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3556 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3557 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3562 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
3563 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3564 "movdqa\t{$src, $dst|$dst, $src}", [],
3567 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3568 "movdqa\t{$src, $dst|$dst, $src}", [],
3569 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3570 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3571 "movdqu\t{$src, $dst|$dst, $src}", [],
3574 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3575 "movdqu\t{$src, $dst|$dst, $src}", [],
3576 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3579 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3580 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3581 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3582 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3584 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3585 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3587 let Predicates = [HasAVX] in {
3588 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3589 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3591 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3592 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3597 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3598 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3599 (ins i128mem:$dst, VR128:$src),
3600 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3602 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3603 (ins i256mem:$dst, VR256:$src),
3604 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3606 let Predicates = [HasAVX] in {
3607 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3608 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3610 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3611 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3616 let SchedRW = [WriteMove] in {
3617 let neverHasSideEffects = 1 in
3618 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3619 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3621 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3622 "movdqu\t{$src, $dst|$dst, $src}",
3623 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3626 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3627 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3628 "movdqa\t{$src, $dst|$dst, $src}", [],
3631 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3632 "movdqu\t{$src, $dst|$dst, $src}",
3633 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3637 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3638 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3639 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3640 "movdqa\t{$src, $dst|$dst, $src}",
3641 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3643 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3644 "movdqu\t{$src, $dst|$dst, $src}",
3645 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3647 XS, Requires<[UseSSE2]>;
3650 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3651 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3652 "movdqa\t{$src, $dst|$dst, $src}",
3653 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3655 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3656 "movdqu\t{$src, $dst|$dst, $src}",
3657 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3659 XS, Requires<[UseSSE2]>;
3662 } // ExeDomain = SSEPackedInt
3664 let Predicates = [HasAVX] in {
3665 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3666 (VMOVDQUmr addr:$dst, VR128:$src)>;
3667 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3668 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3670 let Predicates = [UseSSE2] in
3671 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3672 (MOVDQUmr addr:$dst, VR128:$src)>;
3674 //===---------------------------------------------------------------------===//
3675 // SSE2 - Packed Integer Arithmetic Instructions
3676 //===---------------------------------------------------------------------===//
3678 let Sched = WriteVecIMul in
3679 def SSE_PMADD : OpndItins<
3680 IIC_SSE_PMADD, IIC_SSE_PMADD
3683 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3685 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3686 RegisterClass RC, PatFrag memop_frag,
3687 X86MemOperand x86memop,
3689 bit IsCommutable = 0,
3691 let isCommutable = IsCommutable in
3692 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3693 (ins RC:$src1, RC:$src2),
3695 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3696 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3697 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3698 Sched<[itins.Sched]>;
3699 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3700 (ins RC:$src1, x86memop:$src2),
3702 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3703 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3704 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3705 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3708 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3709 Intrinsic IntId256, OpndItins itins,
3710 bit IsCommutable = 0> {
3711 let Predicates = [HasAVX] in
3712 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3713 VR128, loadv2i64, i128mem, itins,
3714 IsCommutable, 0>, VEX_4V;
3716 let Constraints = "$src1 = $dst" in
3717 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3718 i128mem, itins, IsCommutable, 1>;
3720 let Predicates = [HasAVX2] in
3721 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3722 VR256, loadv4i64, i256mem, itins,
3723 IsCommutable, 0>, VEX_4V, VEX_L;
3726 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3727 string OpcodeStr, SDNode OpNode,
3728 SDNode OpNode2, RegisterClass RC,
3729 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3730 ShiftOpndItins itins,
3732 // src2 is always 128-bit
3733 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3734 (ins RC:$src1, VR128:$src2),
3736 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3737 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3738 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3739 itins.rr>, Sched<[WriteVecShift]>;
3740 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3741 (ins RC:$src1, i128mem:$src2),
3743 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3744 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3745 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3746 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
3747 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3748 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3749 (ins RC:$src1, i8imm:$src2),
3751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3752 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3753 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3754 Sched<[WriteVecShift]>;
3757 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3758 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3759 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3760 PatFrag memop_frag, X86MemOperand x86memop,
3762 bit IsCommutable = 0, bit Is2Addr = 1> {
3763 let isCommutable = IsCommutable in
3764 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3765 (ins RC:$src1, RC:$src2),
3767 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3768 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3769 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3770 Sched<[itins.Sched]>;
3771 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3772 (ins RC:$src1, x86memop:$src2),
3774 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3775 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3776 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3777 (bitconvert (memop_frag addr:$src2)))))]>,
3778 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3780 } // ExeDomain = SSEPackedInt
3782 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3783 SSE_INTALU_ITINS_P, 1>;
3784 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3785 SSE_INTALU_ITINS_P, 1>;
3786 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3787 SSE_INTALU_ITINS_P, 1>;
3788 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3789 SSE_INTALUQ_ITINS_P, 1>;
3790 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3791 SSE_INTMUL_ITINS_P, 1>;
3792 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3793 SSE_INTALU_ITINS_P, 0>;
3794 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3795 SSE_INTALU_ITINS_P, 0>;
3796 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3797 SSE_INTALU_ITINS_P, 0>;
3798 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3799 SSE_INTALUQ_ITINS_P, 0>;
3800 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3801 SSE_INTALU_ITINS_P, 0>;
3802 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3803 SSE_INTALU_ITINS_P, 0>;
3804 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3805 SSE_INTALU_ITINS_P, 1>;
3806 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3807 SSE_INTALU_ITINS_P, 1>;
3808 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3809 SSE_INTALU_ITINS_P, 1>;
3810 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3811 SSE_INTALU_ITINS_P, 1>;
3814 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
3815 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
3816 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3817 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
3818 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3819 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
3820 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3821 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
3822 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3823 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
3824 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3825 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
3826 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3827 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
3828 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3829 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
3830 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3831 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
3832 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3833 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
3834 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3835 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
3836 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3837 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
3839 let Predicates = [HasAVX] in
3840 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3841 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3843 let Predicates = [HasAVX2] in
3844 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3845 VR256, loadv4i64, i256mem,
3846 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3847 let Constraints = "$src1 = $dst" in
3848 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3849 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3851 //===---------------------------------------------------------------------===//
3852 // SSE2 - Packed Integer Logical Instructions
3853 //===---------------------------------------------------------------------===//
3855 let Predicates = [HasAVX] in {
3856 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3857 VR128, v8i16, v8i16, bc_v8i16,
3858 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3859 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3860 VR128, v4i32, v4i32, bc_v4i32,
3861 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3862 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3863 VR128, v2i64, v2i64, bc_v2i64,
3864 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3866 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3867 VR128, v8i16, v8i16, bc_v8i16,
3868 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3869 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3870 VR128, v4i32, v4i32, bc_v4i32,
3871 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3872 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3873 VR128, v2i64, v2i64, bc_v2i64,
3874 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3876 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3877 VR128, v8i16, v8i16, bc_v8i16,
3878 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3879 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3880 VR128, v4i32, v4i32, bc_v4i32,
3881 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3883 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3884 // 128-bit logical shifts.
3885 def VPSLLDQri : PDIi8<0x73, MRM7r,
3886 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3887 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3889 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3891 def VPSRLDQri : PDIi8<0x73, MRM3r,
3892 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3893 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3895 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3897 // PSRADQri doesn't exist in SSE[1-3].
3899 } // Predicates = [HasAVX]
3901 let Predicates = [HasAVX2] in {
3902 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3903 VR256, v16i16, v8i16, bc_v8i16,
3904 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3905 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3906 VR256, v8i32, v4i32, bc_v4i32,
3907 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3908 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3909 VR256, v4i64, v2i64, bc_v2i64,
3910 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3912 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3913 VR256, v16i16, v8i16, bc_v8i16,
3914 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3915 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3916 VR256, v8i32, v4i32, bc_v4i32,
3917 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3918 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3919 VR256, v4i64, v2i64, bc_v2i64,
3920 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3922 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3923 VR256, v16i16, v8i16, bc_v8i16,
3924 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3925 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3926 VR256, v8i32, v4i32, bc_v4i32,
3927 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3929 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3930 // 256-bit logical shifts.
3931 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3932 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3933 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3935 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3937 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3938 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3939 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3941 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3943 // PSRADQYri doesn't exist in SSE[1-3].
3945 } // Predicates = [HasAVX2]
3947 let Constraints = "$src1 = $dst" in {
3948 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3949 VR128, v8i16, v8i16, bc_v8i16,
3950 SSE_INTSHIFT_ITINS_P>;
3951 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3952 VR128, v4i32, v4i32, bc_v4i32,
3953 SSE_INTSHIFT_ITINS_P>;
3954 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3955 VR128, v2i64, v2i64, bc_v2i64,
3956 SSE_INTSHIFT_ITINS_P>;
3958 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3959 VR128, v8i16, v8i16, bc_v8i16,
3960 SSE_INTSHIFT_ITINS_P>;
3961 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3962 VR128, v4i32, v4i32, bc_v4i32,
3963 SSE_INTSHIFT_ITINS_P>;
3964 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3965 VR128, v2i64, v2i64, bc_v2i64,
3966 SSE_INTSHIFT_ITINS_P>;
3968 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3969 VR128, v8i16, v8i16, bc_v8i16,
3970 SSE_INTSHIFT_ITINS_P>;
3971 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3972 VR128, v4i32, v4i32, bc_v4i32,
3973 SSE_INTSHIFT_ITINS_P>;
3975 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3976 // 128-bit logical shifts.
3977 def PSLLDQri : PDIi8<0x73, MRM7r,
3978 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3979 "pslldq\t{$src2, $dst|$dst, $src2}",
3981 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
3982 IIC_SSE_INTSHDQ_P_RI>;
3983 def PSRLDQri : PDIi8<0x73, MRM3r,
3984 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3985 "psrldq\t{$src2, $dst|$dst, $src2}",
3987 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
3988 IIC_SSE_INTSHDQ_P_RI>;
3989 // PSRADQri doesn't exist in SSE[1-3].
3991 } // Constraints = "$src1 = $dst"
3993 let Predicates = [HasAVX] in {
3994 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3995 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3996 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3997 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3998 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3999 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4001 // Shift up / down and insert zero's.
4002 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4003 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4004 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4005 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4008 let Predicates = [HasAVX2] in {
4009 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4010 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4011 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4012 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4015 let Predicates = [UseSSE2] in {
4016 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4017 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4018 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4019 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4020 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4021 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4023 // Shift up / down and insert zero's.
4024 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4025 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4026 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4027 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4030 //===---------------------------------------------------------------------===//
4031 // SSE2 - Packed Integer Comparison Instructions
4032 //===---------------------------------------------------------------------===//
4034 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4035 SSE_INTALU_ITINS_P, 1>;
4036 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4037 SSE_INTALU_ITINS_P, 1>;
4038 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4039 SSE_INTALU_ITINS_P, 1>;
4040 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4041 SSE_INTALU_ITINS_P, 0>;
4042 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4043 SSE_INTALU_ITINS_P, 0>;
4044 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4045 SSE_INTALU_ITINS_P, 0>;
4047 //===---------------------------------------------------------------------===//
4048 // SSE2 - Packed Integer Pack Instructions
4049 //===---------------------------------------------------------------------===//
4051 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4052 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
4053 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4054 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
4055 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4056 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
4058 //===---------------------------------------------------------------------===//
4059 // SSE2 - Packed Integer Shuffle Instructions
4060 //===---------------------------------------------------------------------===//
4062 let ExeDomain = SSEPackedInt in {
4063 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4065 let Predicates = [HasAVX] in {
4066 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4067 (ins VR128:$src1, i8imm:$src2),
4068 !strconcat("v", OpcodeStr,
4069 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4071 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4072 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4073 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4074 (ins i128mem:$src1, i8imm:$src2),
4075 !strconcat("v", OpcodeStr,
4076 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4078 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4079 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4080 Sched<[WriteShuffleLd]>;
4083 let Predicates = [HasAVX2] in {
4084 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4085 (ins VR256:$src1, i8imm:$src2),
4086 !strconcat("v", OpcodeStr,
4087 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4089 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4090 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4091 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4092 (ins i256mem:$src1, i8imm:$src2),
4093 !strconcat("v", OpcodeStr,
4094 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4096 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4097 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4098 Sched<[WriteShuffleLd]>;
4101 let Predicates = [UseSSE2] in {
4102 def ri : Ii8<0x70, MRMSrcReg,
4103 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4104 !strconcat(OpcodeStr,
4105 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4107 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4108 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4109 def mi : Ii8<0x70, MRMSrcMem,
4110 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4111 !strconcat(OpcodeStr,
4112 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4114 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4115 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4116 Sched<[WriteShuffleLd]>;
4119 } // ExeDomain = SSEPackedInt
4121 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4122 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4123 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4125 let Predicates = [HasAVX] in {
4126 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4127 (VPSHUFDmi addr:$src1, imm:$imm)>;
4128 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4129 (VPSHUFDri VR128:$src1, imm:$imm)>;
4132 let Predicates = [UseSSE2] in {
4133 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4134 (PSHUFDmi addr:$src1, imm:$imm)>;
4135 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4136 (PSHUFDri VR128:$src1, imm:$imm)>;
4139 //===---------------------------------------------------------------------===//
4140 // SSE2 - Packed Integer Unpack Instructions
4141 //===---------------------------------------------------------------------===//
4143 let ExeDomain = SSEPackedInt in {
4144 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4145 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4146 def rr : PDI<opc, MRMSrcReg,
4147 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4149 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4150 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4151 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4152 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4153 def rm : PDI<opc, MRMSrcMem,
4154 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4156 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4157 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4158 [(set VR128:$dst, (OpNode VR128:$src1,
4159 (bc_frag (memopv2i64
4162 Sched<[WriteShuffleLd, ReadAfterLd]>;
4165 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4166 SDNode OpNode, PatFrag bc_frag> {
4167 def Yrr : PDI<opc, MRMSrcReg,
4168 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4169 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4170 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4171 Sched<[WriteShuffle]>;
4172 def Yrm : PDI<opc, MRMSrcMem,
4173 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4174 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4175 [(set VR256:$dst, (OpNode VR256:$src1,
4176 (bc_frag (memopv4i64 addr:$src2))))]>,
4177 Sched<[WriteShuffleLd, ReadAfterLd]>;
4180 let Predicates = [HasAVX] in {
4181 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4182 bc_v16i8, 0>, VEX_4V;
4183 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4184 bc_v8i16, 0>, VEX_4V;
4185 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4186 bc_v4i32, 0>, VEX_4V;
4187 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4188 bc_v2i64, 0>, VEX_4V;
4190 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4191 bc_v16i8, 0>, VEX_4V;
4192 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4193 bc_v8i16, 0>, VEX_4V;
4194 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4195 bc_v4i32, 0>, VEX_4V;
4196 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4197 bc_v2i64, 0>, VEX_4V;
4200 let Predicates = [HasAVX2] in {
4201 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4202 bc_v32i8>, VEX_4V, VEX_L;
4203 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4204 bc_v16i16>, VEX_4V, VEX_L;
4205 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4206 bc_v8i32>, VEX_4V, VEX_L;
4207 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4208 bc_v4i64>, VEX_4V, VEX_L;
4210 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4211 bc_v32i8>, VEX_4V, VEX_L;
4212 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4213 bc_v16i16>, VEX_4V, VEX_L;
4214 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4215 bc_v8i32>, VEX_4V, VEX_L;
4216 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4217 bc_v4i64>, VEX_4V, VEX_L;
4220 let Constraints = "$src1 = $dst" in {
4221 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4223 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4225 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4227 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4230 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4232 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4234 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4236 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4239 } // ExeDomain = SSEPackedInt
4241 //===---------------------------------------------------------------------===//
4242 // SSE2 - Packed Integer Extract and Insert
4243 //===---------------------------------------------------------------------===//
4245 let ExeDomain = SSEPackedInt in {
4246 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4247 def rri : Ii8<0xC4, MRMSrcReg,
4248 (outs VR128:$dst), (ins VR128:$src1,
4249 GR32orGR64:$src2, i32i8imm:$src3),
4251 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4252 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4254 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4255 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4256 def rmi : Ii8<0xC4, MRMSrcMem,
4257 (outs VR128:$dst), (ins VR128:$src1,
4258 i16mem:$src2, i32i8imm:$src3),
4260 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4261 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4263 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4264 imm:$src3))], IIC_SSE_PINSRW>,
4265 Sched<[WriteShuffleLd, ReadAfterLd]>;
4269 let Predicates = [HasAVX] in
4270 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4271 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4272 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4273 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4274 imm:$src2))]>, TB, OpSize, VEX,
4275 Sched<[WriteShuffle]>;
4276 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4277 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4278 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4279 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4280 imm:$src2))], IIC_SSE_PEXTRW>,
4281 Sched<[WriteShuffleLd, ReadAfterLd]>;
4284 let Predicates = [HasAVX] in
4285 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4287 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4288 defm PINSRW : sse2_pinsrw, TB, OpSize;
4290 } // ExeDomain = SSEPackedInt
4292 //===---------------------------------------------------------------------===//
4293 // SSE2 - Packed Mask Creation
4294 //===---------------------------------------------------------------------===//
4296 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4298 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4300 "pmovmskb\t{$src, $dst|$dst, $src}",
4301 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4302 IIC_SSE_MOVMSK>, VEX;
4304 let Predicates = [HasAVX2] in {
4305 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4307 "pmovmskb\t{$src, $dst|$dst, $src}",
4308 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4312 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4313 "pmovmskb\t{$src, $dst|$dst, $src}",
4314 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4317 } // ExeDomain = SSEPackedInt
4319 //===---------------------------------------------------------------------===//
4320 // SSE2 - Conditional Store
4321 //===---------------------------------------------------------------------===//
4323 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4325 let Uses = [EDI], Predicates = [HasAVX,In32BitMode] in
4326 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4327 (ins VR128:$src, VR128:$mask),
4328 "maskmovdqu\t{$mask, $src|$src, $mask}",
4329 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4330 IIC_SSE_MASKMOV>, VEX;
4331 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4332 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4333 (ins VR128:$src, VR128:$mask),
4334 "maskmovdqu\t{$mask, $src|$src, $mask}",
4335 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4336 IIC_SSE_MASKMOV>, VEX;
4338 let Uses = [EDI], Predicates = [UseSSE2,In32BitMode] in
4339 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4340 "maskmovdqu\t{$mask, $src|$src, $mask}",
4341 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4343 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4344 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4345 "maskmovdqu\t{$mask, $src|$src, $mask}",
4346 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4349 } // ExeDomain = SSEPackedInt
4351 //===---------------------------------------------------------------------===//
4352 // SSE2 - Move Doubleword
4353 //===---------------------------------------------------------------------===//
4355 //===---------------------------------------------------------------------===//
4356 // Move Int Doubleword to Packed Double Int
4358 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4359 "movd\t{$src, $dst|$dst, $src}",
4361 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4362 VEX, Sched<[WriteMove]>;
4363 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4364 "movd\t{$src, $dst|$dst, $src}",
4366 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4368 VEX, Sched<[WriteLoad]>;
4369 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4370 "movq\t{$src, $dst|$dst, $src}",
4372 (v2i64 (scalar_to_vector GR64:$src)))],
4373 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4374 let isCodeGenOnly = 1 in
4375 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4376 "movq\t{$src, $dst|$dst, $src}",
4377 [(set FR64:$dst, (bitconvert GR64:$src))],
4378 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4380 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4381 "movd\t{$src, $dst|$dst, $src}",
4383 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4385 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4386 "movd\t{$src, $dst|$dst, $src}",
4388 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4389 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4390 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4391 "mov{d|q}\t{$src, $dst|$dst, $src}",
4393 (v2i64 (scalar_to_vector GR64:$src)))],
4394 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4395 let isCodeGenOnly = 1 in
4396 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4397 "mov{d|q}\t{$src, $dst|$dst, $src}",
4398 [(set FR64:$dst, (bitconvert GR64:$src))],
4399 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4401 //===---------------------------------------------------------------------===//
4402 // Move Int Doubleword to Single Scalar
4404 let isCodeGenOnly = 1 in {
4405 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4406 "movd\t{$src, $dst|$dst, $src}",
4407 [(set FR32:$dst, (bitconvert GR32:$src))],
4408 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4410 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4411 "movd\t{$src, $dst|$dst, $src}",
4412 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4414 VEX, Sched<[WriteLoad]>;
4415 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4416 "movd\t{$src, $dst|$dst, $src}",
4417 [(set FR32:$dst, (bitconvert GR32:$src))],
4418 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4420 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4421 "movd\t{$src, $dst|$dst, $src}",
4422 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4423 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4426 //===---------------------------------------------------------------------===//
4427 // Move Packed Doubleword Int to Packed Double Int
4429 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4430 "movd\t{$src, $dst|$dst, $src}",
4431 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4432 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4434 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4435 (ins i32mem:$dst, VR128:$src),
4436 "movd\t{$src, $dst|$dst, $src}",
4437 [(store (i32 (vector_extract (v4i32 VR128:$src),
4438 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4439 VEX, Sched<[WriteLoad]>;
4440 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4441 "movd\t{$src, $dst|$dst, $src}",
4442 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4443 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4445 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4446 "movd\t{$src, $dst|$dst, $src}",
4447 [(store (i32 (vector_extract (v4i32 VR128:$src),
4448 (iPTR 0))), addr:$dst)],
4449 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4451 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4452 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4454 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4455 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4457 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4458 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4460 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4461 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4463 //===---------------------------------------------------------------------===//
4464 // Move Packed Doubleword Int first element to Doubleword Int
4466 let SchedRW = [WriteMove] in {
4467 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4468 "movq\t{$src, $dst|$dst, $src}",
4469 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4474 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4475 "mov{d|q}\t{$src, $dst|$dst, $src}",
4476 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4481 //===---------------------------------------------------------------------===//
4482 // Bitcast FR64 <-> GR64
4484 let isCodeGenOnly = 1 in {
4485 let Predicates = [UseAVX] in
4486 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4487 "movq\t{$src, $dst|$dst, $src}",
4488 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4489 VEX, Sched<[WriteLoad]>;
4490 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4491 "movq\t{$src, $dst|$dst, $src}",
4492 [(set GR64:$dst, (bitconvert FR64:$src))],
4493 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4494 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4495 "movq\t{$src, $dst|$dst, $src}",
4496 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4497 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4499 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4500 "movq\t{$src, $dst|$dst, $src}",
4501 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4502 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4503 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4504 "mov{d|q}\t{$src, $dst|$dst, $src}",
4505 [(set GR64:$dst, (bitconvert FR64:$src))],
4506 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4507 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4508 "movq\t{$src, $dst|$dst, $src}",
4509 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4510 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4513 //===---------------------------------------------------------------------===//
4514 // Move Scalar Single to Double Int
4516 let isCodeGenOnly = 1 in {
4517 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4518 "movd\t{$src, $dst|$dst, $src}",
4519 [(set GR32:$dst, (bitconvert FR32:$src))],
4520 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4521 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4522 "movd\t{$src, $dst|$dst, $src}",
4523 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4524 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4525 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4526 "movd\t{$src, $dst|$dst, $src}",
4527 [(set GR32:$dst, (bitconvert FR32:$src))],
4528 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4529 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4530 "movd\t{$src, $dst|$dst, $src}",
4531 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4532 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4535 //===---------------------------------------------------------------------===//
4536 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4538 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4539 let AddedComplexity = 15 in {
4540 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4541 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4542 [(set VR128:$dst, (v2i64 (X86vzmovl
4543 (v2i64 (scalar_to_vector GR64:$src)))))],
4546 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4547 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4548 [(set VR128:$dst, (v2i64 (X86vzmovl
4549 (v2i64 (scalar_to_vector GR64:$src)))))],
4552 } // isCodeGenOnly, SchedRW
4554 let Predicates = [UseAVX] in {
4555 let AddedComplexity = 15 in
4556 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4557 (VMOVDI2PDIrr GR32:$src)>;
4559 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4560 let AddedComplexity = 20 in {
4561 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4562 (VMOVDI2PDIrm addr:$src)>;
4563 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4564 (VMOVDI2PDIrm addr:$src)>;
4565 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4566 (VMOVDI2PDIrm addr:$src)>;
4568 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4569 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4570 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4571 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4572 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4573 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4574 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4577 let Predicates = [UseSSE2] in {
4578 let AddedComplexity = 15 in
4579 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4580 (MOVDI2PDIrr GR32:$src)>;
4582 let AddedComplexity = 20 in {
4583 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4584 (MOVDI2PDIrm addr:$src)>;
4585 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4586 (MOVDI2PDIrm addr:$src)>;
4587 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4588 (MOVDI2PDIrm addr:$src)>;
4592 // These are the correct encodings of the instructions so that we know how to
4593 // read correct assembly, even though we continue to emit the wrong ones for
4594 // compatibility with Darwin's buggy assembler.
4595 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4596 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4597 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4598 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4599 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4600 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4601 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4602 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4603 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4605 //===---------------------------------------------------------------------===//
4606 // SSE2 - Move Quadword
4607 //===---------------------------------------------------------------------===//
4609 //===---------------------------------------------------------------------===//
4610 // Move Quadword Int to Packed Quadword Int
4613 let SchedRW = [WriteLoad] in {
4614 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4615 "vmovq\t{$src, $dst|$dst, $src}",
4617 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4618 VEX, Requires<[UseAVX]>;
4619 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4620 "movq\t{$src, $dst|$dst, $src}",
4622 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4624 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4627 //===---------------------------------------------------------------------===//
4628 // Move Packed Quadword Int to Quadword Int
4630 let SchedRW = [WriteStore] in {
4631 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4632 "movq\t{$src, $dst|$dst, $src}",
4633 [(store (i64 (vector_extract (v2i64 VR128:$src),
4634 (iPTR 0))), addr:$dst)],
4635 IIC_SSE_MOVDQ>, VEX;
4636 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4637 "movq\t{$src, $dst|$dst, $src}",
4638 [(store (i64 (vector_extract (v2i64 VR128:$src),
4639 (iPTR 0))), addr:$dst)],
4643 //===---------------------------------------------------------------------===//
4644 // Store / copy lower 64-bits of a XMM register.
4646 def VMOVLQ128mr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4647 "movq\t{$src, $dst|$dst, $src}",
4648 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX,
4649 Sched<[WriteStore]>;
4650 def MOVLQ128mr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4651 "movq\t{$src, $dst|$dst, $src}",
4652 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4653 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4655 let isCodeGenOnly = 1, AddedComplexity = 20 in {
4656 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4657 "vmovq\t{$src, $dst|$dst, $src}",
4659 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4660 (loadi64 addr:$src))))))],
4662 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
4664 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4665 "movq\t{$src, $dst|$dst, $src}",
4667 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4668 (loadi64 addr:$src))))))],
4670 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4673 let Predicates = [UseAVX], AddedComplexity = 20 in {
4674 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4675 (VMOVZQI2PQIrm addr:$src)>;
4676 def : Pat<(v2i64 (X86vzload addr:$src)),
4677 (VMOVZQI2PQIrm addr:$src)>;
4680 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4681 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4682 (MOVZQI2PQIrm addr:$src)>;
4683 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4686 let Predicates = [HasAVX] in {
4687 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4688 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4689 def : Pat<(v4i64 (X86vzload addr:$src)),
4690 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4693 //===---------------------------------------------------------------------===//
4694 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4695 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4697 let SchedRW = [WriteVecLogic] in {
4698 let AddedComplexity = 15 in
4699 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4700 "vmovq\t{$src, $dst|$dst, $src}",
4701 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4703 XS, VEX, Requires<[UseAVX]>;
4704 let AddedComplexity = 15 in
4705 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4706 "movq\t{$src, $dst|$dst, $src}",
4707 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4709 XS, Requires<[UseSSE2]>;
4712 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
4713 let AddedComplexity = 20 in
4714 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4715 "vmovq\t{$src, $dst|$dst, $src}",
4716 [(set VR128:$dst, (v2i64 (X86vzmovl
4717 (loadv2i64 addr:$src))))],
4719 XS, VEX, Requires<[UseAVX]>;
4720 let AddedComplexity = 20 in {
4721 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4722 "movq\t{$src, $dst|$dst, $src}",
4723 [(set VR128:$dst, (v2i64 (X86vzmovl
4724 (loadv2i64 addr:$src))))],
4726 XS, Requires<[UseSSE2]>;
4728 } // isCodeGenOnly, SchedRW
4730 let AddedComplexity = 20 in {
4731 let Predicates = [UseAVX] in {
4732 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4733 (VMOVZPQILo2PQIrr VR128:$src)>;
4735 let Predicates = [UseSSE2] in {
4736 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4737 (MOVZPQILo2PQIrr VR128:$src)>;
4741 //===---------------------------------------------------------------------===//
4742 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4743 //===---------------------------------------------------------------------===//
4744 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4745 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4746 X86MemOperand x86memop> {
4747 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4748 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4749 [(set RC:$dst, (vt (OpNode RC:$src)))],
4750 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4751 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4752 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4753 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4754 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4757 let Predicates = [HasAVX] in {
4758 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4759 v4f32, VR128, loadv4f32, f128mem>, VEX;
4760 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4761 v4f32, VR128, loadv4f32, f128mem>, VEX;
4762 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4763 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
4764 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4765 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
4767 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4768 memopv4f32, f128mem>;
4769 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4770 memopv4f32, f128mem>;
4772 let Predicates = [HasAVX] in {
4773 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4774 (VMOVSHDUPrr VR128:$src)>;
4775 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
4776 (VMOVSHDUPrm addr:$src)>;
4777 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4778 (VMOVSLDUPrr VR128:$src)>;
4779 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
4780 (VMOVSLDUPrm addr:$src)>;
4781 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4782 (VMOVSHDUPYrr VR256:$src)>;
4783 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
4784 (VMOVSHDUPYrm addr:$src)>;
4785 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4786 (VMOVSLDUPYrr VR256:$src)>;
4787 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
4788 (VMOVSLDUPYrm addr:$src)>;
4791 let Predicates = [UseSSE3] in {
4792 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4793 (MOVSHDUPrr VR128:$src)>;
4794 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4795 (MOVSHDUPrm addr:$src)>;
4796 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4797 (MOVSLDUPrr VR128:$src)>;
4798 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4799 (MOVSLDUPrm addr:$src)>;
4802 //===---------------------------------------------------------------------===//
4803 // SSE3 - Replicate Double FP - MOVDDUP
4804 //===---------------------------------------------------------------------===//
4806 multiclass sse3_replicate_dfp<string OpcodeStr> {
4807 let neverHasSideEffects = 1 in
4808 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4809 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4810 [], IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4811 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4812 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4815 (scalar_to_vector (loadf64 addr:$src)))))],
4816 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4819 // FIXME: Merge with above classe when there're patterns for the ymm version
4820 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4821 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4822 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4823 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
4824 Sched<[WriteShuffle]>;
4825 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4826 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4829 (scalar_to_vector (loadf64 addr:$src)))))]>,
4830 Sched<[WriteShuffleLd]>;
4833 let Predicates = [HasAVX] in {
4834 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4835 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4838 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4840 let Predicates = [HasAVX] in {
4841 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
4842 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4843 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
4844 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4845 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
4846 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4847 def : Pat<(X86Movddup (bc_v2f64
4848 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4849 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4852 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
4853 (VMOVDDUPYrm addr:$src)>;
4854 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
4855 (VMOVDDUPYrm addr:$src)>;
4856 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4857 (VMOVDDUPYrm addr:$src)>;
4858 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4859 (VMOVDDUPYrr VR256:$src)>;
4862 let Predicates = [UseSSE3] in {
4863 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4864 (MOVDDUPrm addr:$src)>;
4865 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4866 (MOVDDUPrm addr:$src)>;
4867 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4868 (MOVDDUPrm addr:$src)>;
4869 def : Pat<(X86Movddup (bc_v2f64
4870 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4871 (MOVDDUPrm addr:$src)>;
4874 //===---------------------------------------------------------------------===//
4875 // SSE3 - Move Unaligned Integer
4876 //===---------------------------------------------------------------------===//
4878 let SchedRW = [WriteLoad] in {
4879 let Predicates = [HasAVX] in {
4880 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4881 "vlddqu\t{$src, $dst|$dst, $src}",
4882 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4883 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4884 "vlddqu\t{$src, $dst|$dst, $src}",
4885 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
4888 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4889 "lddqu\t{$src, $dst|$dst, $src}",
4890 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4894 //===---------------------------------------------------------------------===//
4895 // SSE3 - Arithmetic
4896 //===---------------------------------------------------------------------===//
4898 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4899 X86MemOperand x86memop, OpndItins itins,
4901 def rr : I<0xD0, MRMSrcReg,
4902 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4904 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4905 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4906 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
4907 Sched<[itins.Sched]>;
4908 def rm : I<0xD0, MRMSrcMem,
4909 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4911 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4912 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4913 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
4914 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4917 let Predicates = [HasAVX] in {
4918 let ExeDomain = SSEPackedSingle in {
4919 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4920 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
4921 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4922 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
4924 let ExeDomain = SSEPackedDouble in {
4925 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4926 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
4927 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4928 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
4931 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
4932 let ExeDomain = SSEPackedSingle in
4933 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4934 f128mem, SSE_ALU_F32P>, TB, XD;
4935 let ExeDomain = SSEPackedDouble in
4936 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4937 f128mem, SSE_ALU_F64P>, TB, OpSize;
4940 //===---------------------------------------------------------------------===//
4941 // SSE3 Instructions
4942 //===---------------------------------------------------------------------===//
4945 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4946 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4947 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4949 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4950 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4951 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
4954 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4956 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4957 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4958 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4959 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
4961 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4962 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4963 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4965 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4966 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4967 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
4970 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4972 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4973 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4974 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4975 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
4978 let Predicates = [HasAVX] in {
4979 let ExeDomain = SSEPackedSingle in {
4980 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4981 X86fhadd, 0>, VEX_4V;
4982 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4983 X86fhsub, 0>, VEX_4V;
4984 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4985 X86fhadd, 0>, VEX_4V, VEX_L;
4986 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4987 X86fhsub, 0>, VEX_4V, VEX_L;
4989 let ExeDomain = SSEPackedDouble in {
4990 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4991 X86fhadd, 0>, VEX_4V;
4992 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4993 X86fhsub, 0>, VEX_4V;
4994 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4995 X86fhadd, 0>, VEX_4V, VEX_L;
4996 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4997 X86fhsub, 0>, VEX_4V, VEX_L;
5001 let Constraints = "$src1 = $dst" in {
5002 let ExeDomain = SSEPackedSingle in {
5003 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5004 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5006 let ExeDomain = SSEPackedDouble in {
5007 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5008 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5012 //===---------------------------------------------------------------------===//
5013 // SSSE3 - Packed Absolute Instructions
5014 //===---------------------------------------------------------------------===//
5017 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5018 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5019 Intrinsic IntId128> {
5020 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5022 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5023 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5024 OpSize, Sched<[WriteVecALU]>;
5026 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5028 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5031 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5032 OpSize, Sched<[WriteVecALULd]>;
5035 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5036 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5037 Intrinsic IntId256> {
5038 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5040 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5041 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5042 OpSize, Sched<[WriteVecALU]>;
5044 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5046 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5049 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5050 Sched<[WriteVecALULd]>;
5053 // Helper fragments to match sext vXi1 to vXiY.
5054 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5056 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5057 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5058 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5060 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5061 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5063 let Predicates = [HasAVX] in {
5064 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5065 int_x86_ssse3_pabs_b_128>, VEX;
5066 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5067 int_x86_ssse3_pabs_w_128>, VEX;
5068 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5069 int_x86_ssse3_pabs_d_128>, VEX;
5072 (bc_v2i64 (v16i1sextv16i8)),
5073 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5074 (VPABSBrr128 VR128:$src)>;
5076 (bc_v2i64 (v8i1sextv8i16)),
5077 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5078 (VPABSWrr128 VR128:$src)>;
5080 (bc_v2i64 (v4i1sextv4i32)),
5081 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5082 (VPABSDrr128 VR128:$src)>;
5085 let Predicates = [HasAVX2] in {
5086 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5087 int_x86_avx2_pabs_b>, VEX, VEX_L;
5088 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5089 int_x86_avx2_pabs_w>, VEX, VEX_L;
5090 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5091 int_x86_avx2_pabs_d>, VEX, VEX_L;
5094 (bc_v4i64 (v32i1sextv32i8)),
5095 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5096 (VPABSBrr256 VR256:$src)>;
5098 (bc_v4i64 (v16i1sextv16i16)),
5099 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5100 (VPABSWrr256 VR256:$src)>;
5102 (bc_v4i64 (v8i1sextv8i32)),
5103 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5104 (VPABSDrr256 VR256:$src)>;
5107 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5108 int_x86_ssse3_pabs_b_128>;
5109 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5110 int_x86_ssse3_pabs_w_128>;
5111 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5112 int_x86_ssse3_pabs_d_128>;
5114 let Predicates = [HasSSSE3] in {
5116 (bc_v2i64 (v16i1sextv16i8)),
5117 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5118 (PABSBrr128 VR128:$src)>;
5120 (bc_v2i64 (v8i1sextv8i16)),
5121 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5122 (PABSWrr128 VR128:$src)>;
5124 (bc_v2i64 (v4i1sextv4i32)),
5125 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5126 (PABSDrr128 VR128:$src)>;
5129 //===---------------------------------------------------------------------===//
5130 // SSSE3 - Packed Binary Operator Instructions
5131 //===---------------------------------------------------------------------===//
5133 let Sched = WriteVecALU in {
5134 def SSE_PHADDSUBD : OpndItins<
5135 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5137 def SSE_PHADDSUBSW : OpndItins<
5138 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5140 def SSE_PHADDSUBW : OpndItins<
5141 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5144 let Sched = WriteShuffle in
5145 def SSE_PSHUFB : OpndItins<
5146 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5148 let Sched = WriteVecALU in
5149 def SSE_PSIGN : OpndItins<
5150 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5152 let Sched = WriteVecIMul in
5153 def SSE_PMULHRSW : OpndItins<
5154 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5157 /// SS3I_binop_rm - Simple SSSE3 bin op
5158 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5159 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5160 X86MemOperand x86memop, OpndItins itins,
5162 let isCommutable = 1 in
5163 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5164 (ins RC:$src1, RC:$src2),
5166 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5167 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5168 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5169 OpSize, Sched<[itins.Sched]>;
5170 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5171 (ins RC:$src1, x86memop:$src2),
5173 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5174 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5176 (OpVT (OpNode RC:$src1,
5177 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5178 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5181 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5182 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5183 Intrinsic IntId128, OpndItins itins,
5185 let isCommutable = 1 in
5186 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5187 (ins VR128:$src1, VR128:$src2),
5189 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5190 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5191 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5192 OpSize, Sched<[itins.Sched]>;
5193 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5194 (ins VR128:$src1, i128mem:$src2),
5196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5199 (IntId128 VR128:$src1,
5200 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5201 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5204 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5205 Intrinsic IntId256> {
5206 let isCommutable = 1 in
5207 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5208 (ins VR256:$src1, VR256:$src2),
5209 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5210 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5212 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5213 (ins VR256:$src1, i256mem:$src2),
5214 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5216 (IntId256 VR256:$src1,
5217 (bitconvert (loadv4i64 addr:$src2))))]>, OpSize;
5220 let ImmT = NoImm, Predicates = [HasAVX] in {
5221 let isCommutable = 0 in {
5222 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5224 SSE_PHADDSUBW, 0>, VEX_4V;
5225 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5227 SSE_PHADDSUBD, 0>, VEX_4V;
5228 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5230 SSE_PHADDSUBW, 0>, VEX_4V;
5231 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5233 SSE_PHADDSUBD, 0>, VEX_4V;
5234 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5236 SSE_PSIGN, 0>, VEX_4V;
5237 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5239 SSE_PSIGN, 0>, VEX_4V;
5240 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5242 SSE_PSIGN, 0>, VEX_4V;
5243 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5245 SSE_PSHUFB, 0>, VEX_4V;
5246 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5247 int_x86_ssse3_phadd_sw_128,
5248 SSE_PHADDSUBSW, 0>, VEX_4V;
5249 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5250 int_x86_ssse3_phsub_sw_128,
5251 SSE_PHADDSUBSW, 0>, VEX_4V;
5252 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5253 int_x86_ssse3_pmadd_ub_sw_128,
5254 SSE_PMADD, 0>, VEX_4V;
5256 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5257 int_x86_ssse3_pmul_hr_sw_128,
5258 SSE_PMULHRSW, 0>, VEX_4V;
5261 let ImmT = NoImm, Predicates = [HasAVX2] in {
5262 let isCommutable = 0 in {
5263 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5265 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5266 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5268 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5269 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5271 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5272 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5274 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5275 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5277 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5278 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5280 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5281 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5283 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5284 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5286 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5287 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5288 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5289 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5290 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5291 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5292 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5294 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5295 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5298 // None of these have i8 immediate fields.
5299 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5300 let isCommutable = 0 in {
5301 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5302 memopv2i64, i128mem, SSE_PHADDSUBW>;
5303 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5304 memopv2i64, i128mem, SSE_PHADDSUBD>;
5305 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5306 memopv2i64, i128mem, SSE_PHADDSUBW>;
5307 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5308 memopv2i64, i128mem, SSE_PHADDSUBD>;
5309 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5310 memopv2i64, i128mem, SSE_PSIGN>;
5311 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5312 memopv2i64, i128mem, SSE_PSIGN>;
5313 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5314 memopv2i64, i128mem, SSE_PSIGN>;
5315 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5316 memopv2i64, i128mem, SSE_PSHUFB>;
5317 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5318 int_x86_ssse3_phadd_sw_128,
5320 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5321 int_x86_ssse3_phsub_sw_128,
5323 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5324 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5326 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5327 int_x86_ssse3_pmul_hr_sw_128,
5331 //===---------------------------------------------------------------------===//
5332 // SSSE3 - Packed Align Instruction Patterns
5333 //===---------------------------------------------------------------------===//
5335 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5336 let neverHasSideEffects = 1 in {
5337 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5338 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5340 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5342 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5343 [], IIC_SSE_PALIGNRR>, OpSize, Sched<[WriteShuffle]>;
5345 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5346 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5348 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5350 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5351 [], IIC_SSE_PALIGNRM>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5355 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5356 let neverHasSideEffects = 1 in {
5357 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5358 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5360 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5361 []>, OpSize, Sched<[WriteShuffle]>;
5363 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5364 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5366 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5367 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5371 let Predicates = [HasAVX] in
5372 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5373 let Predicates = [HasAVX2] in
5374 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5375 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5376 defm PALIGN : ssse3_palignr<"palignr">;
5378 let Predicates = [HasAVX2] in {
5379 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5380 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5381 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5382 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5383 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5384 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5385 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5386 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5389 let Predicates = [HasAVX] in {
5390 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5391 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5392 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5393 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5394 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5395 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5396 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5397 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5400 let Predicates = [UseSSSE3] in {
5401 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5402 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5403 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5404 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5405 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5406 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5407 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5408 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5411 //===---------------------------------------------------------------------===//
5412 // SSSE3 - Thread synchronization
5413 //===---------------------------------------------------------------------===//
5415 let SchedRW = [WriteSystem] in {
5416 let usesCustomInserter = 1 in {
5417 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5418 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5419 Requires<[HasSSE3]>;
5422 let Uses = [EAX, ECX, EDX] in
5423 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5424 TB, Requires<[HasSSE3]>;
5425 let Uses = [ECX, EAX] in
5426 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5427 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5428 TB, Requires<[HasSSE3]>;
5431 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[In32BitMode]>;
5432 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5434 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5435 Requires<[In32BitMode]>;
5436 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5437 Requires<[In64BitMode]>;
5439 //===----------------------------------------------------------------------===//
5440 // SSE4.1 - Packed Move with Sign/Zero Extend
5441 //===----------------------------------------------------------------------===//
5443 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5444 OpndItins itins = DEFAULT_ITINS> {
5445 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5446 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5447 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5449 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5450 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5452 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5456 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5458 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5459 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5460 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5462 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5463 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5464 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5468 let Predicates = [HasAVX] in {
5469 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5470 int_x86_sse41_pmovsxbw>, VEX;
5471 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5472 int_x86_sse41_pmovsxwd>, VEX;
5473 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5474 int_x86_sse41_pmovsxdq>, VEX;
5475 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5476 int_x86_sse41_pmovzxbw>, VEX;
5477 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5478 int_x86_sse41_pmovzxwd>, VEX;
5479 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5480 int_x86_sse41_pmovzxdq>, VEX;
5483 let Predicates = [HasAVX2] in {
5484 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5485 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5486 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5487 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5488 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5489 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5490 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5491 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5492 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5493 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5494 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5495 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5498 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw, SSE_INTALU_ITINS_P>;
5499 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd, SSE_INTALU_ITINS_P>;
5500 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq, SSE_INTALU_ITINS_P>;
5501 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw, SSE_INTALU_ITINS_P>;
5502 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd, SSE_INTALU_ITINS_P>;
5503 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq, SSE_INTALU_ITINS_P>;
5505 let Predicates = [HasAVX] in {
5506 // Common patterns involving scalar load.
5507 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5508 (VPMOVSXBWrm addr:$src)>;
5509 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5510 (VPMOVSXBWrm addr:$src)>;
5511 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5512 (VPMOVSXBWrm addr:$src)>;
5514 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5515 (VPMOVSXWDrm addr:$src)>;
5516 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5517 (VPMOVSXWDrm addr:$src)>;
5518 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5519 (VPMOVSXWDrm addr:$src)>;
5521 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5522 (VPMOVSXDQrm addr:$src)>;
5523 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5524 (VPMOVSXDQrm addr:$src)>;
5525 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5526 (VPMOVSXDQrm addr:$src)>;
5528 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5529 (VPMOVZXBWrm addr:$src)>;
5530 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5531 (VPMOVZXBWrm addr:$src)>;
5532 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5533 (VPMOVZXBWrm addr:$src)>;
5535 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5536 (VPMOVZXWDrm addr:$src)>;
5537 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5538 (VPMOVZXWDrm addr:$src)>;
5539 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5540 (VPMOVZXWDrm addr:$src)>;
5542 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5543 (VPMOVZXDQrm addr:$src)>;
5544 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5545 (VPMOVZXDQrm addr:$src)>;
5546 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5547 (VPMOVZXDQrm addr:$src)>;
5550 let Predicates = [UseSSE41] in {
5551 // Common patterns involving scalar load.
5552 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5553 (PMOVSXBWrm addr:$src)>;
5554 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5555 (PMOVSXBWrm addr:$src)>;
5556 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5557 (PMOVSXBWrm addr:$src)>;
5559 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5560 (PMOVSXWDrm addr:$src)>;
5561 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5562 (PMOVSXWDrm addr:$src)>;
5563 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5564 (PMOVSXWDrm addr:$src)>;
5566 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5567 (PMOVSXDQrm addr:$src)>;
5568 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5569 (PMOVSXDQrm addr:$src)>;
5570 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5571 (PMOVSXDQrm addr:$src)>;
5573 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5574 (PMOVZXBWrm addr:$src)>;
5575 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5576 (PMOVZXBWrm addr:$src)>;
5577 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5578 (PMOVZXBWrm addr:$src)>;
5580 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5581 (PMOVZXWDrm addr:$src)>;
5582 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5583 (PMOVZXWDrm addr:$src)>;
5584 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5585 (PMOVZXWDrm addr:$src)>;
5587 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5588 (PMOVZXDQrm addr:$src)>;
5589 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5590 (PMOVZXDQrm addr:$src)>;
5591 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5592 (PMOVZXDQrm addr:$src)>;
5595 let Predicates = [HasAVX2] in {
5596 let AddedComplexity = 15 in {
5597 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5598 (VPMOVZXDQYrr VR128:$src)>;
5599 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5600 (VPMOVZXWDYrr VR128:$src)>;
5601 def : Pat<(v16i16 (X86vzmovly (v16i8 VR128:$src))),
5602 (VPMOVZXBWYrr VR128:$src)>;
5605 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5606 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5607 def : Pat<(v16i16 (X86vsmovl (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5610 let Predicates = [HasAVX] in {
5611 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5612 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5613 def : Pat<(v8i16 (X86vsmovl (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5616 let Predicates = [UseSSE41] in {
5617 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5618 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5619 def : Pat<(v8i16 (X86vsmovl (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5623 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5624 OpndItins itins = DEFAULT_ITINS> {
5625 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5626 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5627 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5629 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5630 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5632 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
5637 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5639 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5640 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5641 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5643 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5644 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5646 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5650 let Predicates = [HasAVX] in {
5651 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5653 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5655 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5657 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5661 let Predicates = [HasAVX2] in {
5662 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5663 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5664 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5665 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5666 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5667 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5668 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5669 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5672 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
5673 SSE_INTALU_ITINS_P>;
5674 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
5675 SSE_INTALU_ITINS_P>;
5676 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
5677 SSE_INTALU_ITINS_P>;
5678 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
5679 SSE_INTALU_ITINS_P>;
5681 let Predicates = [HasAVX] in {
5682 // Common patterns involving scalar load
5683 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5684 (VPMOVSXBDrm addr:$src)>;
5685 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5686 (VPMOVSXWQrm addr:$src)>;
5688 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5689 (VPMOVZXBDrm addr:$src)>;
5690 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5691 (VPMOVZXWQrm addr:$src)>;
5694 let Predicates = [UseSSE41] in {
5695 // Common patterns involving scalar load
5696 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5697 (PMOVSXBDrm addr:$src)>;
5698 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5699 (PMOVSXWQrm addr:$src)>;
5701 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5702 (PMOVZXBDrm addr:$src)>;
5703 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5704 (PMOVZXWQrm addr:$src)>;
5707 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5708 OpndItins itins = DEFAULT_ITINS> {
5709 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5710 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5711 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5713 // Expecting a i16 load any extended to i32 value.
5714 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5715 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5716 [(set VR128:$dst, (IntId (bitconvert
5717 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5721 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5723 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5724 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5725 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5727 // Expecting a i16 load any extended to i32 value.
5728 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5729 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5730 [(set VR256:$dst, (IntId (bitconvert
5731 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5735 let Predicates = [HasAVX] in {
5736 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5738 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5741 let Predicates = [HasAVX2] in {
5742 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5743 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5744 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5745 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5747 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
5748 SSE_INTALU_ITINS_P>;
5749 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
5750 SSE_INTALU_ITINS_P>;
5752 let Predicates = [HasAVX2] in {
5753 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5754 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5755 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
5757 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5758 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
5760 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5762 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
5763 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5764 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
5765 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5766 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
5767 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5769 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
5770 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5771 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
5772 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5774 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
5775 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5777 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5778 (VPMOVSXWDYrm addr:$src)>;
5779 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5780 (VPMOVSXDQYrm addr:$src)>;
5782 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5783 (scalar_to_vector (loadi64 addr:$src))))))),
5784 (VPMOVSXBDYrm addr:$src)>;
5785 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5786 (scalar_to_vector (loadf64 addr:$src))))))),
5787 (VPMOVSXBDYrm addr:$src)>;
5789 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5790 (scalar_to_vector (loadi64 addr:$src))))))),
5791 (VPMOVSXWQYrm addr:$src)>;
5792 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5793 (scalar_to_vector (loadf64 addr:$src))))))),
5794 (VPMOVSXWQYrm addr:$src)>;
5796 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5797 (scalar_to_vector (loadi32 addr:$src))))))),
5798 (VPMOVSXBQYrm addr:$src)>;
5801 let Predicates = [HasAVX] in {
5802 // Common patterns involving scalar load
5803 def : Pat<(int_x86_sse41_pmovsxbq
5804 (bitconvert (v4i32 (X86vzmovl
5805 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5806 (VPMOVSXBQrm addr:$src)>;
5808 def : Pat<(int_x86_sse41_pmovzxbq
5809 (bitconvert (v4i32 (X86vzmovl
5810 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5811 (VPMOVZXBQrm addr:$src)>;
5814 let Predicates = [UseSSE41] in {
5815 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5816 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
5817 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
5819 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5820 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
5822 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5824 // Common patterns involving scalar load
5825 def : Pat<(int_x86_sse41_pmovsxbq
5826 (bitconvert (v4i32 (X86vzmovl
5827 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5828 (PMOVSXBQrm addr:$src)>;
5830 def : Pat<(int_x86_sse41_pmovzxbq
5831 (bitconvert (v4i32 (X86vzmovl
5832 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5833 (PMOVZXBQrm addr:$src)>;
5835 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5836 (scalar_to_vector (loadi64 addr:$src))))))),
5837 (PMOVSXWDrm addr:$src)>;
5838 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5839 (scalar_to_vector (loadf64 addr:$src))))))),
5840 (PMOVSXWDrm addr:$src)>;
5841 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5842 (scalar_to_vector (loadi32 addr:$src))))))),
5843 (PMOVSXBDrm addr:$src)>;
5844 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5845 (scalar_to_vector (loadi32 addr:$src))))))),
5846 (PMOVSXWQrm addr:$src)>;
5847 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5848 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5849 (PMOVSXBQrm addr:$src)>;
5850 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5851 (scalar_to_vector (loadi64 addr:$src))))))),
5852 (PMOVSXDQrm addr:$src)>;
5853 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5854 (scalar_to_vector (loadf64 addr:$src))))))),
5855 (PMOVSXDQrm addr:$src)>;
5856 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5857 (scalar_to_vector (loadi64 addr:$src))))))),
5858 (PMOVSXBWrm addr:$src)>;
5859 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5860 (scalar_to_vector (loadf64 addr:$src))))))),
5861 (PMOVSXBWrm addr:$src)>;
5864 let Predicates = [HasAVX2] in {
5865 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5866 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5867 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5869 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5870 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5872 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5874 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5875 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5876 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5877 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5878 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5879 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5881 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5882 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5883 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5884 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5886 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5887 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5890 let Predicates = [HasAVX] in {
5891 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5892 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5893 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5895 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5896 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5898 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5900 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5901 (VPMOVZXBWrm addr:$src)>;
5902 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5903 (VPMOVZXBWrm addr:$src)>;
5904 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5905 (VPMOVZXBDrm addr:$src)>;
5906 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5907 (VPMOVZXBQrm addr:$src)>;
5909 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5910 (VPMOVZXWDrm addr:$src)>;
5911 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5912 (VPMOVZXWDrm addr:$src)>;
5913 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5914 (VPMOVZXWQrm addr:$src)>;
5916 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5917 (VPMOVZXDQrm addr:$src)>;
5918 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5919 (VPMOVZXDQrm addr:$src)>;
5920 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5921 (VPMOVZXDQrm addr:$src)>;
5923 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5924 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
5925 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
5927 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5928 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
5930 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5932 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5933 (scalar_to_vector (loadi64 addr:$src))))))),
5934 (VPMOVSXWDrm addr:$src)>;
5935 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5936 (scalar_to_vector (loadi64 addr:$src))))))),
5937 (VPMOVSXDQrm addr:$src)>;
5938 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5939 (scalar_to_vector (loadf64 addr:$src))))))),
5940 (VPMOVSXWDrm addr:$src)>;
5941 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5942 (scalar_to_vector (loadf64 addr:$src))))))),
5943 (VPMOVSXDQrm addr:$src)>;
5944 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5945 (scalar_to_vector (loadi64 addr:$src))))))),
5946 (VPMOVSXBWrm addr:$src)>;
5947 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5948 (scalar_to_vector (loadf64 addr:$src))))))),
5949 (VPMOVSXBWrm addr:$src)>;
5951 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5952 (scalar_to_vector (loadi32 addr:$src))))))),
5953 (VPMOVSXBDrm addr:$src)>;
5954 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5955 (scalar_to_vector (loadi32 addr:$src))))))),
5956 (VPMOVSXWQrm addr:$src)>;
5957 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5958 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5959 (VPMOVSXBQrm addr:$src)>;
5962 let Predicates = [UseSSE41] in {
5963 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
5964 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
5965 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
5967 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
5968 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
5970 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
5972 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5973 (PMOVZXBWrm addr:$src)>;
5974 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5975 (PMOVZXBWrm addr:$src)>;
5976 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5977 (PMOVZXBDrm addr:$src)>;
5978 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5979 (PMOVZXBQrm addr:$src)>;
5981 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5982 (PMOVZXWDrm addr:$src)>;
5983 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5984 (PMOVZXWDrm addr:$src)>;
5985 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5986 (PMOVZXWQrm addr:$src)>;
5988 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5989 (PMOVZXDQrm addr:$src)>;
5990 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5991 (PMOVZXDQrm addr:$src)>;
5992 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5993 (PMOVZXDQrm addr:$src)>;
5996 //===----------------------------------------------------------------------===//
5997 // SSE4.1 - Extract Instructions
5998 //===----------------------------------------------------------------------===//
6000 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6001 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6002 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6003 (ins VR128:$src1, i32i8imm:$src2),
6004 !strconcat(OpcodeStr,
6005 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6006 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6009 let neverHasSideEffects = 1, mayStore = 1 in
6010 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6011 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6012 !strconcat(OpcodeStr,
6013 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6016 // There's an AssertZext in the way of writing the store pattern
6017 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6020 let Predicates = [HasAVX] in
6021 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6023 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6026 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6027 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6028 let isCodeGenOnly = 1, hasSideEffects = 0 in
6029 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6030 (ins VR128:$src1, i32i8imm:$src2),
6031 !strconcat(OpcodeStr,
6032 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6035 let neverHasSideEffects = 1, mayStore = 1 in
6036 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6037 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6038 !strconcat(OpcodeStr,
6039 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6042 // There's an AssertZext in the way of writing the store pattern
6043 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6046 let Predicates = [HasAVX] in
6047 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6049 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6052 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6053 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6054 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6055 (ins VR128:$src1, i32i8imm:$src2),
6056 !strconcat(OpcodeStr,
6057 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6059 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6060 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6061 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6062 !strconcat(OpcodeStr,
6063 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6064 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6065 addr:$dst)]>, OpSize;
6068 let Predicates = [HasAVX] in
6069 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6071 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6073 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6074 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6075 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6076 (ins VR128:$src1, i32i8imm:$src2),
6077 !strconcat(OpcodeStr,
6078 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6080 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6081 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6082 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6083 !strconcat(OpcodeStr,
6084 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6085 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6086 addr:$dst)]>, OpSize, REX_W;
6089 let Predicates = [HasAVX] in
6090 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6092 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6094 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6096 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6097 OpndItins itins = DEFAULT_ITINS> {
6098 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6099 (ins VR128:$src1, i32i8imm:$src2),
6100 !strconcat(OpcodeStr,
6101 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6102 [(set GR32orGR64:$dst,
6103 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6106 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6107 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6108 !strconcat(OpcodeStr,
6109 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6110 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6111 addr:$dst)], itins.rm>, OpSize;
6114 let ExeDomain = SSEPackedSingle in {
6115 let Predicates = [UseAVX] in
6116 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6117 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6120 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6121 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6124 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6126 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6129 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6130 Requires<[UseSSE41]>;
6132 //===----------------------------------------------------------------------===//
6133 // SSE4.1 - Insert Instructions
6134 //===----------------------------------------------------------------------===//
6136 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6137 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6138 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6140 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6142 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6144 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>, OpSize;
6145 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6146 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6148 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6150 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6152 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6153 imm:$src3))]>, OpSize;
6156 let Predicates = [HasAVX] in
6157 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6158 let Constraints = "$src1 = $dst" in
6159 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6161 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6162 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6163 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6165 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6167 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6169 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6171 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6172 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6174 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6176 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6178 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6179 imm:$src3)))]>, OpSize;
6182 let Predicates = [HasAVX] in
6183 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6184 let Constraints = "$src1 = $dst" in
6185 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6187 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6188 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6189 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6191 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6193 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6195 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6197 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6198 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6200 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6202 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6204 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6205 imm:$src3)))]>, OpSize;
6208 let Predicates = [HasAVX] in
6209 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6210 let Constraints = "$src1 = $dst" in
6211 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6213 // insertps has a few different modes, there's the first two here below which
6214 // are optimized inserts that won't zero arbitrary elements in the destination
6215 // vector. The next one matches the intrinsic and could zero arbitrary elements
6216 // in the target vector.
6217 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6218 OpndItins itins = DEFAULT_ITINS> {
6219 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6220 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6222 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6224 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6226 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6228 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6229 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6231 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6233 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6235 (X86insrtps VR128:$src1,
6236 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6237 imm:$src3))], itins.rm>, OpSize;
6240 let ExeDomain = SSEPackedSingle in {
6241 let Predicates = [UseAVX] in
6242 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6243 let Constraints = "$src1 = $dst" in
6244 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6247 //===----------------------------------------------------------------------===//
6248 // SSE4.1 - Round Instructions
6249 //===----------------------------------------------------------------------===//
6251 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6252 X86MemOperand x86memop, RegisterClass RC,
6253 PatFrag mem_frag32, PatFrag mem_frag64,
6254 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6255 let ExeDomain = SSEPackedSingle in {
6256 // Intrinsic operation, reg.
6257 // Vector intrinsic operation, reg
6258 def PSr : SS4AIi8<opcps, MRMSrcReg,
6259 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6260 !strconcat(OpcodeStr,
6261 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6262 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6263 IIC_SSE_ROUNDPS_REG>,
6266 // Vector intrinsic operation, mem
6267 def PSm : SS4AIi8<opcps, MRMSrcMem,
6268 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6269 !strconcat(OpcodeStr,
6270 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6272 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6273 IIC_SSE_ROUNDPS_MEM>,
6275 } // ExeDomain = SSEPackedSingle
6277 let ExeDomain = SSEPackedDouble in {
6278 // Vector intrinsic operation, reg
6279 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6280 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6281 !strconcat(OpcodeStr,
6282 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6283 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6284 IIC_SSE_ROUNDPS_REG>,
6287 // Vector intrinsic operation, mem
6288 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6289 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6290 !strconcat(OpcodeStr,
6291 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6293 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6294 IIC_SSE_ROUNDPS_REG>,
6296 } // ExeDomain = SSEPackedDouble
6299 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6302 Intrinsic F64Int, bit Is2Addr = 1> {
6303 let ExeDomain = GenericDomain in {
6305 let hasSideEffects = 0 in
6306 def SSr : SS4AIi8<opcss, MRMSrcReg,
6307 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6309 !strconcat(OpcodeStr,
6310 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6311 !strconcat(OpcodeStr,
6312 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6315 // Intrinsic operation, reg.
6316 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6317 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6319 !strconcat(OpcodeStr,
6320 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6321 !strconcat(OpcodeStr,
6322 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6323 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6326 // Intrinsic operation, mem.
6327 def SSm : SS4AIi8<opcss, MRMSrcMem,
6328 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6330 !strconcat(OpcodeStr,
6331 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6332 !strconcat(OpcodeStr,
6333 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6335 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6339 let hasSideEffects = 0 in
6340 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6341 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6343 !strconcat(OpcodeStr,
6344 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6345 !strconcat(OpcodeStr,
6346 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6349 // Intrinsic operation, reg.
6350 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6351 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6353 !strconcat(OpcodeStr,
6354 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6355 !strconcat(OpcodeStr,
6356 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6357 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6360 // Intrinsic operation, mem.
6361 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6362 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6364 !strconcat(OpcodeStr,
6365 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6366 !strconcat(OpcodeStr,
6367 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6369 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6371 } // ExeDomain = GenericDomain
6374 // FP round - roundss, roundps, roundsd, roundpd
6375 let Predicates = [HasAVX] in {
6377 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6378 loadv4f32, loadv2f64,
6379 int_x86_sse41_round_ps,
6380 int_x86_sse41_round_pd>, VEX;
6381 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6382 loadv8f32, loadv4f64,
6383 int_x86_avx_round_ps_256,
6384 int_x86_avx_round_pd_256>, VEX, VEX_L;
6385 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6386 int_x86_sse41_round_ss,
6387 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6389 def : Pat<(ffloor FR32:$src),
6390 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6391 def : Pat<(f64 (ffloor FR64:$src)),
6392 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6393 def : Pat<(f32 (fnearbyint FR32:$src)),
6394 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6395 def : Pat<(f64 (fnearbyint FR64:$src)),
6396 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6397 def : Pat<(f32 (fceil FR32:$src)),
6398 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6399 def : Pat<(f64 (fceil FR64:$src)),
6400 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6401 def : Pat<(f32 (frint FR32:$src)),
6402 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6403 def : Pat<(f64 (frint FR64:$src)),
6404 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6405 def : Pat<(f32 (ftrunc FR32:$src)),
6406 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6407 def : Pat<(f64 (ftrunc FR64:$src)),
6408 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6410 def : Pat<(v4f32 (ffloor VR128:$src)),
6411 (VROUNDPSr VR128:$src, (i32 0x1))>;
6412 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6413 (VROUNDPSr VR128:$src, (i32 0xC))>;
6414 def : Pat<(v4f32 (fceil VR128:$src)),
6415 (VROUNDPSr VR128:$src, (i32 0x2))>;
6416 def : Pat<(v4f32 (frint VR128:$src)),
6417 (VROUNDPSr VR128:$src, (i32 0x4))>;
6418 def : Pat<(v4f32 (ftrunc VR128:$src)),
6419 (VROUNDPSr VR128:$src, (i32 0x3))>;
6421 def : Pat<(v2f64 (ffloor VR128:$src)),
6422 (VROUNDPDr VR128:$src, (i32 0x1))>;
6423 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6424 (VROUNDPDr VR128:$src, (i32 0xC))>;
6425 def : Pat<(v2f64 (fceil VR128:$src)),
6426 (VROUNDPDr VR128:$src, (i32 0x2))>;
6427 def : Pat<(v2f64 (frint VR128:$src)),
6428 (VROUNDPDr VR128:$src, (i32 0x4))>;
6429 def : Pat<(v2f64 (ftrunc VR128:$src)),
6430 (VROUNDPDr VR128:$src, (i32 0x3))>;
6432 def : Pat<(v8f32 (ffloor VR256:$src)),
6433 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6434 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6435 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6436 def : Pat<(v8f32 (fceil VR256:$src)),
6437 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6438 def : Pat<(v8f32 (frint VR256:$src)),
6439 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6440 def : Pat<(v8f32 (ftrunc VR256:$src)),
6441 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6443 def : Pat<(v4f64 (ffloor VR256:$src)),
6444 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6445 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6446 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6447 def : Pat<(v4f64 (fceil VR256:$src)),
6448 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6449 def : Pat<(v4f64 (frint VR256:$src)),
6450 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6451 def : Pat<(v4f64 (ftrunc VR256:$src)),
6452 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6455 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6456 memopv4f32, memopv2f64,
6457 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6458 let Constraints = "$src1 = $dst" in
6459 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6460 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6462 let Predicates = [UseSSE41] in {
6463 def : Pat<(ffloor FR32:$src),
6464 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6465 def : Pat<(f64 (ffloor FR64:$src)),
6466 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6467 def : Pat<(f32 (fnearbyint FR32:$src)),
6468 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6469 def : Pat<(f64 (fnearbyint FR64:$src)),
6470 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6471 def : Pat<(f32 (fceil FR32:$src)),
6472 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6473 def : Pat<(f64 (fceil FR64:$src)),
6474 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6475 def : Pat<(f32 (frint FR32:$src)),
6476 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6477 def : Pat<(f64 (frint FR64:$src)),
6478 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6479 def : Pat<(f32 (ftrunc FR32:$src)),
6480 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6481 def : Pat<(f64 (ftrunc FR64:$src)),
6482 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6484 def : Pat<(v4f32 (ffloor VR128:$src)),
6485 (ROUNDPSr VR128:$src, (i32 0x1))>;
6486 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6487 (ROUNDPSr VR128:$src, (i32 0xC))>;
6488 def : Pat<(v4f32 (fceil VR128:$src)),
6489 (ROUNDPSr VR128:$src, (i32 0x2))>;
6490 def : Pat<(v4f32 (frint VR128:$src)),
6491 (ROUNDPSr VR128:$src, (i32 0x4))>;
6492 def : Pat<(v4f32 (ftrunc VR128:$src)),
6493 (ROUNDPSr VR128:$src, (i32 0x3))>;
6495 def : Pat<(v2f64 (ffloor VR128:$src)),
6496 (ROUNDPDr VR128:$src, (i32 0x1))>;
6497 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6498 (ROUNDPDr VR128:$src, (i32 0xC))>;
6499 def : Pat<(v2f64 (fceil VR128:$src)),
6500 (ROUNDPDr VR128:$src, (i32 0x2))>;
6501 def : Pat<(v2f64 (frint VR128:$src)),
6502 (ROUNDPDr VR128:$src, (i32 0x4))>;
6503 def : Pat<(v2f64 (ftrunc VR128:$src)),
6504 (ROUNDPDr VR128:$src, (i32 0x3))>;
6507 //===----------------------------------------------------------------------===//
6508 // SSE4.1 - Packed Bit Test
6509 //===----------------------------------------------------------------------===//
6511 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6512 // the intel intrinsic that corresponds to this.
6513 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6514 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6515 "vptest\t{$src2, $src1|$src1, $src2}",
6516 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6518 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6519 "vptest\t{$src2, $src1|$src1, $src2}",
6520 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6523 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6524 "vptest\t{$src2, $src1|$src1, $src2}",
6525 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6527 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6528 "vptest\t{$src2, $src1|$src1, $src2}",
6529 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6533 let Defs = [EFLAGS] in {
6534 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6535 "ptest\t{$src2, $src1|$src1, $src2}",
6536 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6538 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6539 "ptest\t{$src2, $src1|$src1, $src2}",
6540 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6544 // The bit test instructions below are AVX only
6545 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6546 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6547 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6548 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6549 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6550 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6551 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6552 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6556 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6557 let ExeDomain = SSEPackedSingle in {
6558 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6559 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6562 let ExeDomain = SSEPackedDouble in {
6563 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6564 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6569 //===----------------------------------------------------------------------===//
6570 // SSE4.1 - Misc Instructions
6571 //===----------------------------------------------------------------------===//
6573 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6574 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6575 "popcnt{w}\t{$src, $dst|$dst, $src}",
6576 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6579 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6580 "popcnt{w}\t{$src, $dst|$dst, $src}",
6581 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6582 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize, XS;
6584 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6585 "popcnt{l}\t{$src, $dst|$dst, $src}",
6586 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6589 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6590 "popcnt{l}\t{$src, $dst|$dst, $src}",
6591 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6592 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6594 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6595 "popcnt{q}\t{$src, $dst|$dst, $src}",
6596 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6599 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6600 "popcnt{q}\t{$src, $dst|$dst, $src}",
6601 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6602 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6607 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6608 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6609 Intrinsic IntId128> {
6610 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6612 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6613 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6614 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6619 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6622 let Predicates = [HasAVX] in
6623 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6624 int_x86_sse41_phminposuw>, VEX;
6625 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6626 int_x86_sse41_phminposuw>;
6628 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6629 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6630 Intrinsic IntId128, bit Is2Addr = 1,
6631 OpndItins itins = DEFAULT_ITINS> {
6632 let isCommutable = 1 in
6633 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6634 (ins VR128:$src1, VR128:$src2),
6636 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6637 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6638 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
6640 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6641 (ins VR128:$src1, i128mem:$src2),
6643 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6644 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6646 (IntId128 VR128:$src1,
6647 (bitconvert (memopv2i64 addr:$src2))))],
6651 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6652 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6653 Intrinsic IntId256> {
6654 let isCommutable = 1 in
6655 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6656 (ins VR256:$src1, VR256:$src2),
6657 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6658 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6659 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6660 (ins VR256:$src1, i256mem:$src2),
6661 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6663 (IntId256 VR256:$src1,
6664 (bitconvert (loadv4i64 addr:$src2))))]>, OpSize;
6668 /// SS48I_binop_rm - Simple SSE41 binary operator.
6669 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6670 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6671 X86MemOperand x86memop, bit Is2Addr = 1,
6672 OpndItins itins = DEFAULT_ITINS> {
6673 let isCommutable = 1 in
6674 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6675 (ins RC:$src1, RC:$src2),
6677 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6678 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6679 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6680 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6681 (ins RC:$src1, x86memop:$src2),
6683 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6684 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6686 (OpVT (OpNode RC:$src1,
6687 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6690 let Predicates = [HasAVX] in {
6691 let isCommutable = 0 in
6692 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6694 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6695 loadv2i64, i128mem, 0>, VEX_4V;
6696 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6697 loadv2i64, i128mem, 0>, VEX_4V;
6698 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6699 loadv2i64, i128mem, 0>, VEX_4V;
6700 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6701 loadv2i64, i128mem, 0>, VEX_4V;
6702 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6703 loadv2i64, i128mem, 0>, VEX_4V;
6704 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6705 loadv2i64, i128mem, 0>, VEX_4V;
6706 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6707 loadv2i64, i128mem, 0>, VEX_4V;
6708 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6709 loadv2i64, i128mem, 0>, VEX_4V;
6710 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6714 let Predicates = [HasAVX2] in {
6715 let isCommutable = 0 in
6716 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6717 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6718 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6719 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6720 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6721 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6722 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6723 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6724 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6725 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6726 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6727 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6728 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6729 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6730 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6731 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6732 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6733 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6734 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6735 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6738 let Constraints = "$src1 = $dst" in {
6739 let isCommutable = 0 in
6740 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6741 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6742 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6743 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6744 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6745 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6746 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6747 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6748 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6749 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6750 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6751 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6752 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6753 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6754 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6755 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6756 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6757 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq,
6758 1, SSE_INTMUL_ITINS_P>;
6761 let Predicates = [HasAVX] in {
6762 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6763 memopv2i64, i128mem, 0>, VEX_4V;
6764 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6765 memopv2i64, i128mem, 0>, VEX_4V;
6767 let Predicates = [HasAVX2] in {
6768 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6769 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6770 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6771 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6774 let Constraints = "$src1 = $dst" in {
6775 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6776 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6777 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6778 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6781 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6782 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6783 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6784 X86MemOperand x86memop, bit Is2Addr = 1,
6785 OpndItins itins = DEFAULT_ITINS> {
6786 let isCommutable = 1 in
6787 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6788 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6790 !strconcat(OpcodeStr,
6791 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6792 !strconcat(OpcodeStr,
6793 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6794 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6796 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6797 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6799 !strconcat(OpcodeStr,
6800 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6801 !strconcat(OpcodeStr,
6802 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6805 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6809 let Predicates = [HasAVX] in {
6810 let isCommutable = 0 in {
6811 let ExeDomain = SSEPackedSingle in {
6812 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6813 VR128, loadv4f32, f128mem, 0>, VEX_4V;
6814 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6815 int_x86_avx_blend_ps_256, VR256, loadv8f32,
6816 f256mem, 0>, VEX_4V, VEX_L;
6818 let ExeDomain = SSEPackedDouble in {
6819 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6820 VR128, loadv2f64, f128mem, 0>, VEX_4V;
6821 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6822 int_x86_avx_blend_pd_256,VR256, loadv4f64,
6823 f256mem, 0>, VEX_4V, VEX_L;
6825 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6826 VR128, loadv2i64, i128mem, 0>, VEX_4V;
6827 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6828 VR128, loadv2i64, i128mem, 0>, VEX_4V;
6830 let ExeDomain = SSEPackedSingle in
6831 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6832 VR128, loadv4f32, f128mem, 0>, VEX_4V;
6833 let ExeDomain = SSEPackedDouble in
6834 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6835 VR128, loadv2f64, f128mem, 0>, VEX_4V;
6836 let ExeDomain = SSEPackedSingle in
6837 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6838 VR256, loadv8f32, i256mem, 0>, VEX_4V, VEX_L;
6841 let Predicates = [HasAVX2] in {
6842 let isCommutable = 0 in {
6843 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6844 VR256, loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6845 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6846 VR256, loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6850 let Constraints = "$src1 = $dst" in {
6851 let isCommutable = 0 in {
6852 let ExeDomain = SSEPackedSingle in
6853 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6854 VR128, memopv4f32, f128mem,
6855 1, SSE_INTALU_ITINS_P>;
6856 let ExeDomain = SSEPackedDouble in
6857 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6858 VR128, memopv2f64, f128mem,
6859 1, SSE_INTALU_ITINS_P>;
6860 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6861 VR128, memopv2i64, i128mem,
6862 1, SSE_INTALU_ITINS_P>;
6863 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6864 VR128, memopv2i64, i128mem,
6865 1, SSE_INTMUL_ITINS_P>;
6867 let ExeDomain = SSEPackedSingle in
6868 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6869 VR128, memopv4f32, f128mem, 1,
6871 let ExeDomain = SSEPackedDouble in
6872 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6873 VR128, memopv2f64, f128mem, 1,
6877 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6878 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6879 RegisterClass RC, X86MemOperand x86memop,
6880 PatFrag mem_frag, Intrinsic IntId> {
6881 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6882 (ins RC:$src1, RC:$src2, RC:$src3),
6883 !strconcat(OpcodeStr,
6884 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6885 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6886 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6888 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6889 (ins RC:$src1, x86memop:$src2, RC:$src3),
6890 !strconcat(OpcodeStr,
6891 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6893 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6895 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6898 let Predicates = [HasAVX] in {
6899 let ExeDomain = SSEPackedDouble in {
6900 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6901 loadv2f64, int_x86_sse41_blendvpd>;
6902 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6903 loadv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6904 } // ExeDomain = SSEPackedDouble
6905 let ExeDomain = SSEPackedSingle in {
6906 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6907 loadv4f32, int_x86_sse41_blendvps>;
6908 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6909 loadv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6910 } // ExeDomain = SSEPackedSingle
6911 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6912 loadv2i64, int_x86_sse41_pblendvb>;
6915 let Predicates = [HasAVX2] in {
6916 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6917 loadv4i64, int_x86_avx2_pblendvb>, VEX_L;
6920 let Predicates = [HasAVX] in {
6921 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6922 (v16i8 VR128:$src2))),
6923 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6924 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6925 (v4i32 VR128:$src2))),
6926 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6927 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6928 (v4f32 VR128:$src2))),
6929 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6930 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6931 (v2i64 VR128:$src2))),
6932 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6933 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6934 (v2f64 VR128:$src2))),
6935 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6936 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6937 (v8i32 VR256:$src2))),
6938 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6939 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6940 (v8f32 VR256:$src2))),
6941 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6942 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6943 (v4i64 VR256:$src2))),
6944 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6945 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6946 (v4f64 VR256:$src2))),
6947 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6949 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6951 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6952 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6954 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6956 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6958 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6959 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6961 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6962 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6964 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6967 let Predicates = [HasAVX2] in {
6968 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6969 (v32i8 VR256:$src2))),
6970 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6971 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6973 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6976 /// SS41I_ternary_int - SSE 4.1 ternary operator
6977 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6978 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6979 X86MemOperand x86memop, Intrinsic IntId,
6980 OpndItins itins = DEFAULT_ITINS> {
6981 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6982 (ins VR128:$src1, VR128:$src2),
6983 !strconcat(OpcodeStr,
6984 "\t{$src2, $dst|$dst, $src2}"),
6985 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
6988 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6989 (ins VR128:$src1, x86memop:$src2),
6990 !strconcat(OpcodeStr,
6991 "\t{$src2, $dst|$dst, $src2}"),
6994 (bitconvert (mem_frag addr:$src2)), XMM0))],
6999 let ExeDomain = SSEPackedDouble in
7000 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7001 int_x86_sse41_blendvpd>;
7002 let ExeDomain = SSEPackedSingle in
7003 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7004 int_x86_sse41_blendvps>;
7005 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7006 int_x86_sse41_pblendvb>;
7008 // Aliases with the implicit xmm0 argument
7009 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7010 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7011 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7012 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7013 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7014 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7015 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7016 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7017 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7018 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7019 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7020 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7022 let Predicates = [UseSSE41] in {
7023 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7024 (v16i8 VR128:$src2))),
7025 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7026 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7027 (v4i32 VR128:$src2))),
7028 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7029 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7030 (v4f32 VR128:$src2))),
7031 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7032 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7033 (v2i64 VR128:$src2))),
7034 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7035 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7036 (v2f64 VR128:$src2))),
7037 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7039 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7041 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7042 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7044 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7045 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7047 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7051 let Predicates = [HasAVX] in
7052 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7053 "vmovntdqa\t{$src, $dst|$dst, $src}",
7054 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7056 let Predicates = [HasAVX2] in
7057 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7058 "vmovntdqa\t{$src, $dst|$dst, $src}",
7059 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7061 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7062 "movntdqa\t{$src, $dst|$dst, $src}",
7063 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7066 //===----------------------------------------------------------------------===//
7067 // SSE4.2 - Compare Instructions
7068 //===----------------------------------------------------------------------===//
7070 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7071 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7072 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7073 X86MemOperand x86memop, bit Is2Addr = 1> {
7074 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7075 (ins RC:$src1, RC:$src2),
7077 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7078 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7079 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7081 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7082 (ins RC:$src1, x86memop:$src2),
7084 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7085 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7087 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7090 let Predicates = [HasAVX] in
7091 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7092 loadv2i64, i128mem, 0>, VEX_4V;
7094 let Predicates = [HasAVX2] in
7095 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7096 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7098 let Constraints = "$src1 = $dst" in
7099 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7100 memopv2i64, i128mem>;
7102 //===----------------------------------------------------------------------===//
7103 // SSE4.2 - String/text Processing Instructions
7104 //===----------------------------------------------------------------------===//
7106 // Packed Compare Implicit Length Strings, Return Mask
7107 multiclass pseudo_pcmpistrm<string asm> {
7108 def REG : PseudoI<(outs VR128:$dst),
7109 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7110 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7112 def MEM : PseudoI<(outs VR128:$dst),
7113 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7114 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7115 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7118 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7119 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7120 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7123 multiclass pcmpistrm_SS42AI<string asm> {
7124 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7125 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7126 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7129 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7130 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7131 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7135 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7136 let Predicates = [HasAVX] in
7137 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7138 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7141 // Packed Compare Explicit Length Strings, Return Mask
7142 multiclass pseudo_pcmpestrm<string asm> {
7143 def REG : PseudoI<(outs VR128:$dst),
7144 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7145 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7146 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7147 def MEM : PseudoI<(outs VR128:$dst),
7148 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7149 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7150 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7153 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7154 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7155 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7158 multiclass SS42AI_pcmpestrm<string asm> {
7159 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7160 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7161 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7164 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7165 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7166 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7170 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7171 let Predicates = [HasAVX] in
7172 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7173 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7176 // Packed Compare Implicit Length Strings, Return Index
7177 multiclass pseudo_pcmpistri<string asm> {
7178 def REG : PseudoI<(outs GR32:$dst),
7179 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7180 [(set GR32:$dst, EFLAGS,
7181 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7182 def MEM : PseudoI<(outs GR32:$dst),
7183 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7184 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7185 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7188 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7189 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7190 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7193 multiclass SS42AI_pcmpistri<string asm> {
7194 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7195 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7196 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7199 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7200 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7201 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7205 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7206 let Predicates = [HasAVX] in
7207 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7208 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7211 // Packed Compare Explicit Length Strings, Return Index
7212 multiclass pseudo_pcmpestri<string asm> {
7213 def REG : PseudoI<(outs GR32:$dst),
7214 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7215 [(set GR32:$dst, EFLAGS,
7216 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7217 def MEM : PseudoI<(outs GR32:$dst),
7218 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7219 [(set GR32:$dst, EFLAGS,
7220 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7224 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7225 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7226 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7229 multiclass SS42AI_pcmpestri<string asm> {
7230 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7231 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7232 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7235 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7236 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7237 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7241 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7242 let Predicates = [HasAVX] in
7243 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7244 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7247 //===----------------------------------------------------------------------===//
7248 // SSE4.2 - CRC Instructions
7249 //===----------------------------------------------------------------------===//
7251 // No CRC instructions have AVX equivalents
7253 // crc intrinsic instruction
7254 // This set of instructions are only rm, the only difference is the size
7256 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7257 RegisterClass RCIn, SDPatternOperator Int> :
7258 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7259 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7260 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>;
7262 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7263 X86MemOperand x86memop, SDPatternOperator Int> :
7264 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7265 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7266 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7269 let Constraints = "$src1 = $dst" in {
7270 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7271 int_x86_sse42_crc32_32_8>;
7272 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7273 int_x86_sse42_crc32_32_8>;
7274 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7275 int_x86_sse42_crc32_32_16>, OpSize;
7276 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7277 int_x86_sse42_crc32_32_16>, OpSize;
7278 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7279 int_x86_sse42_crc32_32_32>;
7280 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7281 int_x86_sse42_crc32_32_32>;
7282 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7283 int_x86_sse42_crc32_64_64>, REX_W;
7284 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7285 int_x86_sse42_crc32_64_64>, REX_W;
7286 let hasSideEffects = 0 in {
7288 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7290 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7295 //===----------------------------------------------------------------------===//
7296 // SHA-NI Instructions
7297 //===----------------------------------------------------------------------===//
7299 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7301 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7302 (ins VR128:$src1, VR128:$src2),
7303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7305 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7306 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7308 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7309 (ins VR128:$src1, i128mem:$src2),
7310 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7312 (set VR128:$dst, (IntId VR128:$src1,
7313 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7314 (set VR128:$dst, (IntId VR128:$src1,
7315 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7318 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7319 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7320 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7321 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7323 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7324 (i8 imm:$src3)))]>, TA;
7325 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7326 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7327 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7329 (int_x86_sha1rnds4 VR128:$src1,
7330 (bc_v4i32 (memopv2i64 addr:$src2)),
7331 (i8 imm:$src3)))]>, TA;
7333 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7334 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7335 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7338 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7340 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7341 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7344 // Aliases with explicit %xmm0
7345 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7346 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7347 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7348 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7350 //===----------------------------------------------------------------------===//
7351 // AES-NI Instructions
7352 //===----------------------------------------------------------------------===//
7354 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7355 Intrinsic IntId128, bit Is2Addr = 1> {
7356 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7357 (ins VR128:$src1, VR128:$src2),
7359 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7361 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7363 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7364 (ins VR128:$src1, i128mem:$src2),
7366 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7367 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7369 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7372 // Perform One Round of an AES Encryption/Decryption Flow
7373 let Predicates = [HasAVX, HasAES] in {
7374 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7375 int_x86_aesni_aesenc, 0>, VEX_4V;
7376 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7377 int_x86_aesni_aesenclast, 0>, VEX_4V;
7378 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7379 int_x86_aesni_aesdec, 0>, VEX_4V;
7380 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7381 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7384 let Constraints = "$src1 = $dst" in {
7385 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7386 int_x86_aesni_aesenc>;
7387 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7388 int_x86_aesni_aesenclast>;
7389 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7390 int_x86_aesni_aesdec>;
7391 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7392 int_x86_aesni_aesdeclast>;
7395 // Perform the AES InvMixColumn Transformation
7396 let Predicates = [HasAVX, HasAES] in {
7397 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7399 "vaesimc\t{$src1, $dst|$dst, $src1}",
7401 (int_x86_aesni_aesimc VR128:$src1))]>,
7403 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7404 (ins i128mem:$src1),
7405 "vaesimc\t{$src1, $dst|$dst, $src1}",
7406 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7409 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7411 "aesimc\t{$src1, $dst|$dst, $src1}",
7413 (int_x86_aesni_aesimc VR128:$src1))]>,
7415 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7416 (ins i128mem:$src1),
7417 "aesimc\t{$src1, $dst|$dst, $src1}",
7418 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7421 // AES Round Key Generation Assist
7422 let Predicates = [HasAVX, HasAES] in {
7423 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7424 (ins VR128:$src1, i8imm:$src2),
7425 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7427 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7429 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7430 (ins i128mem:$src1, i8imm:$src2),
7431 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7433 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7436 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7437 (ins VR128:$src1, i8imm:$src2),
7438 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7440 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7442 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7443 (ins i128mem:$src1, i8imm:$src2),
7444 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7446 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7449 //===----------------------------------------------------------------------===//
7450 // PCLMUL Instructions
7451 //===----------------------------------------------------------------------===//
7453 // AVX carry-less Multiplication instructions
7454 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7455 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7456 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7458 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7460 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7461 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7462 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7463 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7464 (loadv2i64 addr:$src2), imm:$src3))]>;
7466 // Carry-less Multiplication instructions
7467 let Constraints = "$src1 = $dst" in {
7468 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7469 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7470 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7472 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7473 IIC_SSE_PCLMULQDQ_RR>;
7475 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7476 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7477 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7478 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7479 (memopv2i64 addr:$src2), imm:$src3))],
7480 IIC_SSE_PCLMULQDQ_RM>;
7481 } // Constraints = "$src1 = $dst"
7484 multiclass pclmul_alias<string asm, int immop> {
7485 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7486 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7488 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7489 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7491 def : InstAlias<!strconcat("vpclmul", asm,
7492 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7493 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7495 def : InstAlias<!strconcat("vpclmul", asm,
7496 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7497 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7499 defm : pclmul_alias<"hqhq", 0x11>;
7500 defm : pclmul_alias<"hqlq", 0x01>;
7501 defm : pclmul_alias<"lqhq", 0x10>;
7502 defm : pclmul_alias<"lqlq", 0x00>;
7504 //===----------------------------------------------------------------------===//
7505 // SSE4A Instructions
7506 //===----------------------------------------------------------------------===//
7508 let Predicates = [HasSSE4A] in {
7510 let Constraints = "$src = $dst" in {
7511 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7512 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7513 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7514 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7515 imm:$idx))]>, TB, OpSize;
7516 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7517 (ins VR128:$src, VR128:$mask),
7518 "extrq\t{$mask, $src|$src, $mask}",
7519 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7520 VR128:$mask))]>, TB, OpSize;
7522 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7523 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7524 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7525 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7526 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7527 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7528 (ins VR128:$src, VR128:$mask),
7529 "insertq\t{$mask, $src|$src, $mask}",
7530 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7531 VR128:$mask))]>, XD;
7534 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7535 "movntss\t{$src, $dst|$dst, $src}",
7536 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7538 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7539 "movntsd\t{$src, $dst|$dst, $src}",
7540 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7543 //===----------------------------------------------------------------------===//
7545 //===----------------------------------------------------------------------===//
7547 //===----------------------------------------------------------------------===//
7548 // VBROADCAST - Load from memory and broadcast to all elements of the
7549 // destination operand
7551 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7552 X86MemOperand x86memop, Intrinsic Int> :
7553 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7554 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7555 [(set RC:$dst, (Int addr:$src))]>, VEX;
7557 // AVX2 adds register forms
7558 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7560 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7561 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7562 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7564 let ExeDomain = SSEPackedSingle in {
7565 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7566 int_x86_avx_vbroadcast_ss>;
7567 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7568 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7570 let ExeDomain = SSEPackedDouble in
7571 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7572 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7573 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7574 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7576 let ExeDomain = SSEPackedSingle in {
7577 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7578 int_x86_avx2_vbroadcast_ss_ps>;
7579 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7580 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7582 let ExeDomain = SSEPackedDouble in
7583 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7584 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7586 let Predicates = [HasAVX2] in
7587 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7588 int_x86_avx2_vbroadcasti128>, VEX_L;
7590 let Predicates = [HasAVX] in
7591 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7592 (VBROADCASTF128 addr:$src)>;
7595 //===----------------------------------------------------------------------===//
7596 // VINSERTF128 - Insert packed floating-point values
7598 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7599 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7600 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7601 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7604 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7605 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7606 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7610 let Predicates = [HasAVX] in {
7611 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7613 (VINSERTF128rr VR256:$src1, VR128:$src2,
7614 (INSERT_get_vinsert128_imm VR256:$ins))>;
7615 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7617 (VINSERTF128rr VR256:$src1, VR128:$src2,
7618 (INSERT_get_vinsert128_imm VR256:$ins))>;
7620 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7622 (VINSERTF128rm VR256:$src1, addr:$src2,
7623 (INSERT_get_vinsert128_imm VR256:$ins))>;
7624 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7626 (VINSERTF128rm VR256:$src1, addr:$src2,
7627 (INSERT_get_vinsert128_imm VR256:$ins))>;
7630 let Predicates = [HasAVX1Only] in {
7631 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7633 (VINSERTF128rr VR256:$src1, VR128:$src2,
7634 (INSERT_get_vinsert128_imm VR256:$ins))>;
7635 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7637 (VINSERTF128rr VR256:$src1, VR128:$src2,
7638 (INSERT_get_vinsert128_imm VR256:$ins))>;
7639 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7641 (VINSERTF128rr VR256:$src1, VR128:$src2,
7642 (INSERT_get_vinsert128_imm VR256:$ins))>;
7643 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7645 (VINSERTF128rr VR256:$src1, VR128:$src2,
7646 (INSERT_get_vinsert128_imm VR256:$ins))>;
7648 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7650 (VINSERTF128rm VR256:$src1, addr:$src2,
7651 (INSERT_get_vinsert128_imm VR256:$ins))>;
7652 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7653 (bc_v4i32 (loadv2i64 addr:$src2)),
7655 (VINSERTF128rm VR256:$src1, addr:$src2,
7656 (INSERT_get_vinsert128_imm VR256:$ins))>;
7657 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7658 (bc_v16i8 (loadv2i64 addr:$src2)),
7660 (VINSERTF128rm VR256:$src1, addr:$src2,
7661 (INSERT_get_vinsert128_imm VR256:$ins))>;
7662 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7663 (bc_v8i16 (loadv2i64 addr:$src2)),
7665 (VINSERTF128rm VR256:$src1, addr:$src2,
7666 (INSERT_get_vinsert128_imm VR256:$ins))>;
7669 //===----------------------------------------------------------------------===//
7670 // VEXTRACTF128 - Extract packed floating-point values
7672 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7673 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7674 (ins VR256:$src1, i8imm:$src2),
7675 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7678 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7679 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7680 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7685 let Predicates = [HasAVX] in {
7686 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7687 (v4f32 (VEXTRACTF128rr
7688 (v8f32 VR256:$src1),
7689 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7690 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7691 (v2f64 (VEXTRACTF128rr
7692 (v4f64 VR256:$src1),
7693 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7695 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7696 (iPTR imm))), addr:$dst),
7697 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7698 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7699 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7700 (iPTR imm))), addr:$dst),
7701 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7702 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7705 let Predicates = [HasAVX1Only] in {
7706 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7707 (v2i64 (VEXTRACTF128rr
7708 (v4i64 VR256:$src1),
7709 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7710 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7711 (v4i32 (VEXTRACTF128rr
7712 (v8i32 VR256:$src1),
7713 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7714 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7715 (v8i16 (VEXTRACTF128rr
7716 (v16i16 VR256:$src1),
7717 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7718 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7719 (v16i8 (VEXTRACTF128rr
7720 (v32i8 VR256:$src1),
7721 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7723 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7724 (iPTR imm))), addr:$dst),
7725 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7726 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7727 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7728 (iPTR imm))), addr:$dst),
7729 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7730 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7731 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7732 (iPTR imm))), addr:$dst),
7733 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7734 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7735 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7736 (iPTR imm))), addr:$dst),
7737 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7738 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7741 //===----------------------------------------------------------------------===//
7742 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7744 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7745 Intrinsic IntLd, Intrinsic IntLd256,
7746 Intrinsic IntSt, Intrinsic IntSt256> {
7747 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7748 (ins VR128:$src1, f128mem:$src2),
7749 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7750 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7752 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7753 (ins VR256:$src1, f256mem:$src2),
7754 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7755 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7757 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7758 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7759 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7760 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7761 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7762 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7763 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7764 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7767 let ExeDomain = SSEPackedSingle in
7768 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7769 int_x86_avx_maskload_ps,
7770 int_x86_avx_maskload_ps_256,
7771 int_x86_avx_maskstore_ps,
7772 int_x86_avx_maskstore_ps_256>;
7773 let ExeDomain = SSEPackedDouble in
7774 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7775 int_x86_avx_maskload_pd,
7776 int_x86_avx_maskload_pd_256,
7777 int_x86_avx_maskstore_pd,
7778 int_x86_avx_maskstore_pd_256>;
7780 //===----------------------------------------------------------------------===//
7781 // VPERMIL - Permute Single and Double Floating-Point Values
7783 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7784 RegisterClass RC, X86MemOperand x86memop_f,
7785 X86MemOperand x86memop_i, PatFrag i_frag,
7786 Intrinsic IntVar, ValueType vt> {
7787 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7788 (ins RC:$src1, RC:$src2),
7789 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7790 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7791 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7792 (ins RC:$src1, x86memop_i:$src2),
7793 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7794 [(set RC:$dst, (IntVar RC:$src1,
7795 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7797 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7798 (ins RC:$src1, i8imm:$src2),
7799 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7800 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7801 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7802 (ins x86memop_f:$src1, i8imm:$src2),
7803 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7805 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7808 let ExeDomain = SSEPackedSingle in {
7809 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7810 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7811 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7812 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7814 let ExeDomain = SSEPackedDouble in {
7815 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7816 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7817 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7818 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7821 let Predicates = [HasAVX] in {
7822 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7823 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7824 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7825 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7826 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (loadv4i64 addr:$src1)),
7828 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7829 def : Pat<(v4i64 (X86VPermilp (loadv4i64 addr:$src1), (i8 imm:$imm))),
7830 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7832 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7833 (VPERMILPDri VR128:$src1, imm:$imm)>;
7834 def : Pat<(v2i64 (X86VPermilp (loadv2i64 addr:$src1), (i8 imm:$imm))),
7835 (VPERMILPDmi addr:$src1, imm:$imm)>;
7838 //===----------------------------------------------------------------------===//
7839 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7841 let ExeDomain = SSEPackedSingle in {
7842 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7843 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7844 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7845 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7846 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7847 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7848 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7849 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7850 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
7851 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7854 let Predicates = [HasAVX] in {
7855 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7856 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7857 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7858 (loadv4f64 addr:$src2), (i8 imm:$imm))),
7859 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7862 let Predicates = [HasAVX1Only] in {
7863 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7864 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7865 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7866 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7867 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7868 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7869 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7870 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7872 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7873 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
7874 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7875 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7876 (loadv4i64 addr:$src2), (i8 imm:$imm))),
7877 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7878 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7879 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
7880 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7881 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7882 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
7883 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7886 //===----------------------------------------------------------------------===//
7887 // VZERO - Zero YMM registers
7889 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7890 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7891 // Zero All YMM registers
7892 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7893 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7895 // Zero Upper bits of YMM registers
7896 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7897 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7900 //===----------------------------------------------------------------------===//
7901 // Half precision conversion instructions
7902 //===----------------------------------------------------------------------===//
7903 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7904 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7905 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7906 [(set RC:$dst, (Int VR128:$src))]>,
7908 let neverHasSideEffects = 1, mayLoad = 1 in
7909 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7910 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7913 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7914 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7915 (ins RC:$src1, i32i8imm:$src2),
7916 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7917 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7919 let neverHasSideEffects = 1, mayStore = 1 in
7920 def mr : Ii8<0x1D, MRMDestMem, (outs),
7921 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7922 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7926 let Predicates = [HasF16C] in {
7927 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7928 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7929 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7930 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7933 //===----------------------------------------------------------------------===//
7934 // AVX2 Instructions
7935 //===----------------------------------------------------------------------===//
7937 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7938 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7939 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7940 X86MemOperand x86memop> {
7941 let isCommutable = 1 in
7942 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7943 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7944 !strconcat(OpcodeStr,
7945 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7946 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7948 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7949 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7950 !strconcat(OpcodeStr,
7951 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7954 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7958 let isCommutable = 0 in {
7959 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7960 VR128, loadv2i64, i128mem>;
7961 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7962 VR256, loadv4i64, i256mem>, VEX_L;
7965 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
7967 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7968 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
7970 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7972 //===----------------------------------------------------------------------===//
7973 // VPBROADCAST - Load from memory and broadcast to all elements of the
7974 // destination operand
7976 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7977 X86MemOperand x86memop, PatFrag ld_frag,
7978 Intrinsic Int128, Intrinsic Int256> {
7979 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7980 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7981 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7982 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7983 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7985 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7986 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7987 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7988 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
7989 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7990 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7992 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
7996 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7997 int_x86_avx2_pbroadcastb_128,
7998 int_x86_avx2_pbroadcastb_256>;
7999 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8000 int_x86_avx2_pbroadcastw_128,
8001 int_x86_avx2_pbroadcastw_256>;
8002 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8003 int_x86_avx2_pbroadcastd_128,
8004 int_x86_avx2_pbroadcastd_256>;
8005 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8006 int_x86_avx2_pbroadcastq_128,
8007 int_x86_avx2_pbroadcastq_256>;
8009 let Predicates = [HasAVX2] in {
8010 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8011 (VPBROADCASTBrm addr:$src)>;
8012 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8013 (VPBROADCASTBYrm addr:$src)>;
8014 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8015 (VPBROADCASTWrm addr:$src)>;
8016 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8017 (VPBROADCASTWYrm addr:$src)>;
8018 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8019 (VPBROADCASTDrm addr:$src)>;
8020 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8021 (VPBROADCASTDYrm addr:$src)>;
8022 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8023 (VPBROADCASTQrm addr:$src)>;
8024 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8025 (VPBROADCASTQYrm addr:$src)>;
8027 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8028 (VPBROADCASTBrr VR128:$src)>;
8029 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8030 (VPBROADCASTBYrr VR128:$src)>;
8031 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8032 (VPBROADCASTWrr VR128:$src)>;
8033 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8034 (VPBROADCASTWYrr VR128:$src)>;
8035 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8036 (VPBROADCASTDrr VR128:$src)>;
8037 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8038 (VPBROADCASTDYrr VR128:$src)>;
8039 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8040 (VPBROADCASTQrr VR128:$src)>;
8041 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8042 (VPBROADCASTQYrr VR128:$src)>;
8043 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8044 (VBROADCASTSSrr VR128:$src)>;
8045 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8046 (VBROADCASTSSYrr VR128:$src)>;
8047 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8048 (VPBROADCASTQrr VR128:$src)>;
8049 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8050 (VBROADCASTSDYrr VR128:$src)>;
8052 // Provide fallback in case the load node that is used in the patterns above
8053 // is used by additional users, which prevents the pattern selection.
8054 let AddedComplexity = 20 in {
8055 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8056 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8057 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8058 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8059 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8060 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8062 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8063 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8064 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8065 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8066 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8067 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8071 // AVX1 broadcast patterns
8072 let Predicates = [HasAVX1Only] in {
8073 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8074 (VBROADCASTSSYrm addr:$src)>;
8075 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8076 (VBROADCASTSDYrm addr:$src)>;
8077 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8078 (VBROADCASTSSrm addr:$src)>;
8081 let Predicates = [HasAVX] in {
8082 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8083 (VBROADCASTSSYrm addr:$src)>;
8084 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8085 (VBROADCASTSDYrm addr:$src)>;
8086 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8087 (VBROADCASTSSrm addr:$src)>;
8089 // Provide fallback in case the load node that is used in the patterns above
8090 // is used by additional users, which prevents the pattern selection.
8091 let AddedComplexity = 20 in {
8092 // 128bit broadcasts:
8093 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8094 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8095 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8096 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8097 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8098 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8099 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8100 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8101 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8102 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8104 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8105 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8106 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8107 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8108 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8109 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8110 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8111 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8112 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8113 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8117 //===----------------------------------------------------------------------===//
8118 // VPERM - Permute instructions
8121 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8123 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8124 (ins VR256:$src1, VR256:$src2),
8125 !strconcat(OpcodeStr,
8126 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8128 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8130 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8131 (ins VR256:$src1, i256mem:$src2),
8132 !strconcat(OpcodeStr,
8133 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8135 (OpVT (X86VPermv VR256:$src1,
8136 (bitconvert (mem_frag addr:$src2)))))]>,
8140 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32>;
8141 let ExeDomain = SSEPackedSingle in
8142 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32>;
8144 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8146 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8147 (ins VR256:$src1, i8imm:$src2),
8148 !strconcat(OpcodeStr,
8149 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8151 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8153 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8154 (ins i256mem:$src1, i8imm:$src2),
8155 !strconcat(OpcodeStr,
8156 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8158 (OpVT (X86VPermi (mem_frag addr:$src1),
8159 (i8 imm:$src2))))]>, VEX, VEX_L;
8162 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64>, VEX_W;
8163 let ExeDomain = SSEPackedDouble in
8164 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64>, VEX_W;
8166 //===----------------------------------------------------------------------===//
8167 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8169 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8170 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8171 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8172 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8173 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8174 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8175 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8176 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8177 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8178 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8180 let Predicates = [HasAVX2] in {
8181 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8182 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8183 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8184 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8185 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8186 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8188 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8190 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8191 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8192 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8193 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8194 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8196 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8200 //===----------------------------------------------------------------------===//
8201 // VINSERTI128 - Insert packed integer values
8203 let neverHasSideEffects = 1 in {
8204 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8205 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8206 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8209 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8210 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8211 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8215 let Predicates = [HasAVX2] in {
8216 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8218 (VINSERTI128rr VR256:$src1, VR128:$src2,
8219 (INSERT_get_vinsert128_imm VR256:$ins))>;
8220 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8222 (VINSERTI128rr VR256:$src1, VR128:$src2,
8223 (INSERT_get_vinsert128_imm VR256:$ins))>;
8224 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8226 (VINSERTI128rr VR256:$src1, VR128:$src2,
8227 (INSERT_get_vinsert128_imm VR256:$ins))>;
8228 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8230 (VINSERTI128rr VR256:$src1, VR128:$src2,
8231 (INSERT_get_vinsert128_imm VR256:$ins))>;
8233 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8235 (VINSERTI128rm VR256:$src1, addr:$src2,
8236 (INSERT_get_vinsert128_imm VR256:$ins))>;
8237 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8238 (bc_v4i32 (loadv2i64 addr:$src2)),
8240 (VINSERTI128rm VR256:$src1, addr:$src2,
8241 (INSERT_get_vinsert128_imm VR256:$ins))>;
8242 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8243 (bc_v16i8 (loadv2i64 addr:$src2)),
8245 (VINSERTI128rm VR256:$src1, addr:$src2,
8246 (INSERT_get_vinsert128_imm VR256:$ins))>;
8247 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8248 (bc_v8i16 (loadv2i64 addr:$src2)),
8250 (VINSERTI128rm VR256:$src1, addr:$src2,
8251 (INSERT_get_vinsert128_imm VR256:$ins))>;
8254 //===----------------------------------------------------------------------===//
8255 // VEXTRACTI128 - Extract packed integer values
8257 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8258 (ins VR256:$src1, i8imm:$src2),
8259 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8261 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8263 let neverHasSideEffects = 1, mayStore = 1 in
8264 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8265 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8266 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8269 let Predicates = [HasAVX2] in {
8270 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8271 (v2i64 (VEXTRACTI128rr
8272 (v4i64 VR256:$src1),
8273 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8274 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8275 (v4i32 (VEXTRACTI128rr
8276 (v8i32 VR256:$src1),
8277 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8278 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8279 (v8i16 (VEXTRACTI128rr
8280 (v16i16 VR256:$src1),
8281 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8282 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8283 (v16i8 (VEXTRACTI128rr
8284 (v32i8 VR256:$src1),
8285 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8287 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8288 (iPTR imm))), addr:$dst),
8289 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8290 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8291 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8292 (iPTR imm))), addr:$dst),
8293 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8294 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8295 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8296 (iPTR imm))), addr:$dst),
8297 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8298 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8299 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8300 (iPTR imm))), addr:$dst),
8301 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8302 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8305 //===----------------------------------------------------------------------===//
8306 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8308 multiclass avx2_pmovmask<string OpcodeStr,
8309 Intrinsic IntLd128, Intrinsic IntLd256,
8310 Intrinsic IntSt128, Intrinsic IntSt256> {
8311 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8312 (ins VR128:$src1, i128mem:$src2),
8313 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8314 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8315 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8316 (ins VR256:$src1, i256mem:$src2),
8317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8318 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8320 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8321 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8322 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8323 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8324 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8325 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8326 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8327 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8330 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8331 int_x86_avx2_maskload_d,
8332 int_x86_avx2_maskload_d_256,
8333 int_x86_avx2_maskstore_d,
8334 int_x86_avx2_maskstore_d_256>;
8335 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8336 int_x86_avx2_maskload_q,
8337 int_x86_avx2_maskload_q_256,
8338 int_x86_avx2_maskstore_q,
8339 int_x86_avx2_maskstore_q_256>, VEX_W;
8342 //===----------------------------------------------------------------------===//
8343 // Variable Bit Shifts
8345 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8346 ValueType vt128, ValueType vt256> {
8347 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8348 (ins VR128:$src1, VR128:$src2),
8349 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8351 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8353 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8354 (ins VR128:$src1, i128mem:$src2),
8355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8357 (vt128 (OpNode VR128:$src1,
8358 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8360 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8361 (ins VR256:$src1, VR256:$src2),
8362 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8364 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8366 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8367 (ins VR256:$src1, i256mem:$src2),
8368 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8370 (vt256 (OpNode VR256:$src1,
8371 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8375 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8376 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8377 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8378 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8379 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8381 //===----------------------------------------------------------------------===//
8382 // VGATHER - GATHER Operations
8383 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8384 X86MemOperand memop128, X86MemOperand memop256> {
8385 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8386 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8387 !strconcat(OpcodeStr,
8388 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8390 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8391 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8392 !strconcat(OpcodeStr,
8393 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8394 []>, VEX_4VOp3, VEX_L;
8397 let mayLoad = 1, Constraints
8398 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8400 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8401 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8402 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8403 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8404 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8405 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8406 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8407 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;