1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 // Implicitly promote a 32-bit scalar to a vector.
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
287 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
288 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
289 // Implicitly promote a 64-bit scalar to a vector.
290 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
291 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
292 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
293 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
295 // Bitcasts between 128-bit vector types. Return the original type since
296 // no instruction is needed for the conversion
297 let Predicates = [HasSSE2] in {
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 // Bitcasts between 256-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasAVX] in {
333 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
334 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 // Alias instructions that map fld0 to pxor for sse.
366 // This is expanded by ExpandPostRAPseudos.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
369 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
370 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
371 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
372 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 //===----------------------------------------------------------------------===//
376 // AVX & SSE - Zero/One Vectors
377 //===----------------------------------------------------------------------===//
379 // Alias instruction that maps zero vector to pxor / xorp* for sse.
380 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
381 // swizzled by ExecutionDepsFix to pxor.
382 // We set canFoldAsLoad because this can be converted to a constant-pool
383 // load of an all-zeros value if folding it would be beneficial.
384 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
385 isPseudo = 1, neverHasSideEffects = 1 in {
386 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
389 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
390 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
391 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
392 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
394 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397 // The same as done above but for AVX. The 256-bit ISA does not support PI,
398 // and doesn't need it because on sandy bridge the register is set to zero
399 // at the rename stage without using any execution unit, so SET0PSY
400 // and SET0PDY can be used for vector int instructions without penalty
401 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
402 // JIT implementatioan, it does not expand the instructions below like
403 // X86MCInstLower does.
404 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
405 isCodeGenOnly = 1 in {
406 let Predicates = [HasAVX] in {
407 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
408 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
409 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
410 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
412 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
413 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
417 let Predicates = [HasAVX2], AddedComplexity = 5 in {
418 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
419 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
420 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
421 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
424 // AVX has no support for 256-bit integer instructions, but since the 128-bit
425 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
426 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
438 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
440 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
445 // JIT implementation, it does not expand the instructions below like
446 // X86MCInstLower does.
447 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
448 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
449 let Predicates = [HasAVX] in
450 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
451 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
452 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
453 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
454 let Predicates = [HasAVX2] in
455 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
456 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
460 //===----------------------------------------------------------------------===//
461 // SSE 1 & 2 - Move FP Scalar Instructions
463 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
464 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
465 // is used instead. Register-to-register movss/movsd is not modeled as an
466 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
467 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
468 //===----------------------------------------------------------------------===//
470 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
471 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
472 [(set VR128:$dst, (vt (OpNode VR128:$src1,
473 (scalar_to_vector RC:$src2))))],
476 // Loading from memory automatically zeroing upper bits.
477 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
478 PatFrag mem_pat, string OpcodeStr> :
479 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
481 [(set RC:$dst, (mem_pat addr:$src))],
485 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
486 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
488 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
489 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
492 // For the disassembler
493 let isCodeGenOnly = 1 in {
494 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
495 (ins VR128:$src1, FR32:$src2),
496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
499 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
500 (ins VR128:$src1, FR64:$src2),
501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
506 let canFoldAsLoad = 1, isReMaterializable = 1 in {
507 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
509 let AddedComplexity = 20 in
510 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
514 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
515 "movss\t{$src, $dst|$dst, $src}",
516 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
518 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
519 "movsd\t{$src, $dst|$dst, $src}",
520 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
524 let Constraints = "$src1 = $dst" in {
525 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
526 "movss\t{$src2, $dst|$dst, $src2}">, XS;
527 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
528 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
530 // For the disassembler
531 let isCodeGenOnly = 1 in {
532 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
533 (ins VR128:$src1, FR32:$src2),
534 "movss\t{$src2, $dst|$dst, $src2}", [],
535 IIC_SSE_MOV_S_RR>, XS;
536 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
537 (ins VR128:$src1, FR64:$src2),
538 "movsd\t{$src2, $dst|$dst, $src2}", [],
539 IIC_SSE_MOV_S_RR>, XD;
543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
544 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
546 let AddedComplexity = 20 in
547 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
550 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
551 "movss\t{$src, $dst|$dst, $src}",
552 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
553 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
554 "movsd\t{$src, $dst|$dst, $src}",
555 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
558 let Predicates = [HasAVX] in {
559 let AddedComplexity = 15 in {
560 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
561 // MOVS{S,D} to the lower bits.
562 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
563 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
564 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
567 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
568 (VMOVSSrr (v4i32 (V_SET0)),
569 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
570 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
571 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
573 // Move low f32 and clear high bits.
574 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
575 (SUBREG_TO_REG (i32 0),
576 (VMOVSSrr (v4f32 (V_SET0)),
577 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
578 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
579 (SUBREG_TO_REG (i32 0),
580 (VMOVSSrr (v4i32 (V_SET0)),
581 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
584 let AddedComplexity = 20 in {
585 // MOVSSrm zeros the high parts of the register; represent this
586 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
587 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
588 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
589 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
590 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
591 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
592 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
594 // MOVSDrm zeros the high parts of the register; represent this
595 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
596 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
597 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
598 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
599 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
600 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
601 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
602 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
603 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
604 def : Pat<(v2f64 (X86vzload addr:$src)),
605 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
607 // Represent the same patterns above but in the form they appear for
609 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
610 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
612 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
613 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
615 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
616 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
617 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
619 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
620 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
621 (SUBREG_TO_REG (i32 0),
622 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
624 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
625 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
626 (SUBREG_TO_REG (i64 0),
627 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
629 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
630 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
631 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
633 // Move low f64 and clear high bits.
634 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
635 (SUBREG_TO_REG (i32 0),
636 (VMOVSDrr (v2f64 (V_SET0)),
637 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
639 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
640 (SUBREG_TO_REG (i32 0),
641 (VMOVSDrr (v2i64 (V_SET0)),
642 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
644 // Extract and store.
645 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
648 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
649 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
652 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
654 // Shuffle with VMOVSS
655 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
656 (VMOVSSrr (v4i32 VR128:$src1),
657 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
658 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
659 (VMOVSSrr (v4f32 VR128:$src1),
660 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
663 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
666 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
667 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
668 (SUBREG_TO_REG (i32 0),
669 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
670 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
672 // Shuffle with VMOVSD
673 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
674 (VMOVSDrr (v2i64 VR128:$src1),
675 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
676 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr (v2f64 VR128:$src1),
678 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
679 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
680 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
682 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
683 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
687 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
688 (SUBREG_TO_REG (i32 0),
689 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
690 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
691 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
694 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
697 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
698 // is during lowering, where it's not possible to recognize the fold cause
699 // it has two uses through a bitcast. One use disappears at isel time and the
700 // fold opportunity reappears.
701 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
702 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
704 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
705 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
707 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
708 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
710 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
715 let Predicates = [HasSSE1] in {
716 let AddedComplexity = 15 in {
717 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
718 // MOVSS to the lower bits.
719 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
720 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
721 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
722 (MOVSSrr (v4f32 (V_SET0)),
723 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)),
726 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
729 let AddedComplexity = 20 in {
730 // MOVSSrm zeros the high parts of the register; represent this
731 // with SUBREG_TO_REG.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
744 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
746 // Shuffle with MOVSS
747 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
748 (MOVSSrr (v4i32 VR128:$src1),
749 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
750 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
751 (MOVSSrr (v4f32 VR128:$src1),
752 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
755 let Predicates = [HasSSE2] in {
756 let AddedComplexity = 15 in {
757 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
758 // MOVSD to the lower bits.
759 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
760 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
763 let AddedComplexity = 20 in {
764 // MOVSDrm zeros the high parts of the register; represent this
765 // with SUBREG_TO_REG.
766 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
767 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
768 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
769 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
770 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
771 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
772 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
773 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
774 def : Pat<(v2f64 (X86vzload addr:$src)),
775 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
778 // Extract and store.
779 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
782 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
784 // Shuffle with MOVSD
785 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
786 (MOVSDrr (v2i64 VR128:$src1),
787 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
788 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
789 (MOVSDrr (v2f64 VR128:$src1),
790 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
791 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
793 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
796 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
797 // is during lowering, where it's not possible to recognize the fold cause
798 // it has two uses through a bitcast. One use disappears at isel time and the
799 // fold opportunity reappears.
800 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
801 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
802 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
803 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
804 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
805 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
806 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
807 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
810 //===----------------------------------------------------------------------===//
811 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
812 //===----------------------------------------------------------------------===//
814 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
815 X86MemOperand x86memop, PatFrag ld_frag,
816 string asm, Domain d,
818 bit IsReMaterializable = 1> {
819 let neverHasSideEffects = 1 in
820 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
821 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
822 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
823 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
824 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
825 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
828 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
829 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
831 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
832 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
834 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
835 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
837 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
838 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
841 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
842 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
844 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
845 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
847 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
848 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
850 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
851 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
853 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
854 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
856 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
857 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
859 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
860 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
862 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
863 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX;
870 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX;
874 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v4f32 VR128:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX;
878 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v2f64 VR128:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX;
882 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
883 "movaps\t{$src, $dst|$dst, $src}",
884 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
885 IIC_SSE_MOVA_P_MR>, VEX;
886 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
887 "movapd\t{$src, $dst|$dst, $src}",
888 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
889 IIC_SSE_MOVA_P_MR>, VEX;
890 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
891 "movups\t{$src, $dst|$dst, $src}",
892 [(store (v8f32 VR256:$src), addr:$dst)],
893 IIC_SSE_MOVU_P_MR>, VEX;
894 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
895 "movupd\t{$src, $dst|$dst, $src}",
896 [(store (v4f64 VR256:$src), addr:$dst)],
897 IIC_SSE_MOVU_P_MR>, VEX;
900 let isCodeGenOnly = 1 in {
901 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
903 "movaps\t{$src, $dst|$dst, $src}", [],
904 IIC_SSE_MOVA_P_RR>, VEX;
905 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
907 "movapd\t{$src, $dst|$dst, $src}", [],
908 IIC_SSE_MOVA_P_RR>, VEX;
909 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
911 "movups\t{$src, $dst|$dst, $src}", [],
912 IIC_SSE_MOVU_P_RR>, VEX;
913 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
915 "movupd\t{$src, $dst|$dst, $src}", [],
916 IIC_SSE_MOVU_P_RR>, VEX;
917 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
919 "movaps\t{$src, $dst|$dst, $src}", [],
920 IIC_SSE_MOVA_P_RR>, VEX;
921 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
923 "movapd\t{$src, $dst|$dst, $src}", [],
924 IIC_SSE_MOVA_P_RR>, VEX;
925 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
927 "movups\t{$src, $dst|$dst, $src}", [],
928 IIC_SSE_MOVU_P_RR>, VEX;
929 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
931 "movupd\t{$src, $dst|$dst, $src}", [],
932 IIC_SSE_MOVU_P_RR>, VEX;
935 let Predicates = [HasAVX] in {
936 def : Pat<(v8i32 (X86vzmovl
937 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
938 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
939 def : Pat<(v4i64 (X86vzmovl
940 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v8f32 (X86vzmovl
943 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v4f64 (X86vzmovl
946 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
951 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
952 (VMOVUPSYmr addr:$dst, VR256:$src)>;
953 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
954 (VMOVUPDYmr addr:$dst, VR256:$src)>;
956 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
957 "movaps\t{$src, $dst|$dst, $src}",
958 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
960 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movapd\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
964 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movups\t{$src, $dst|$dst, $src}",
966 [(store (v4f32 VR128:$src), addr:$dst)],
968 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movupd\t{$src, $dst|$dst, $src}",
970 [(store (v2f64 VR128:$src), addr:$dst)],
974 let isCodeGenOnly = 1 in {
975 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
976 "movaps\t{$src, $dst|$dst, $src}", [],
978 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
979 "movapd\t{$src, $dst|$dst, $src}", [],
981 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movups\t{$src, $dst|$dst, $src}", [],
984 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movupd\t{$src, $dst|$dst, $src}", [],
989 let Predicates = [HasAVX] in {
990 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
991 (VMOVUPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
993 (VMOVUPDmr addr:$dst, VR128:$src)>;
996 let Predicates = [HasSSE1] in
997 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
998 (MOVUPSmr addr:$dst, VR128:$src)>;
999 let Predicates = [HasSSE2] in
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (MOVUPDmr addr:$dst, VR128:$src)>;
1003 // Use vmovaps/vmovups for AVX integer load/store.
1004 let Predicates = [HasAVX] in {
1005 // 128-bit load/store
1006 def : Pat<(alignedloadv2i64 addr:$src),
1007 (VMOVAPSrm addr:$src)>;
1008 def : Pat<(loadv2i64 addr:$src),
1009 (VMOVUPSrm addr:$src)>;
1011 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1012 (VMOVAPSmr addr:$dst, VR128:$src)>;
1013 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1014 (VMOVAPSmr addr:$dst, VR128:$src)>;
1015 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1016 (VMOVAPSmr addr:$dst, VR128:$src)>;
1017 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1020 (VMOVUPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1022 (VMOVUPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1024 (VMOVUPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1028 // 256-bit load/store
1029 def : Pat<(alignedloadv4i64 addr:$src),
1030 (VMOVAPSYrm addr:$src)>;
1031 def : Pat<(loadv4i64 addr:$src),
1032 (VMOVUPSYrm addr:$src)>;
1033 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1034 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1035 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1036 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1037 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1038 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1039 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1042 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1044 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1046 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 // Use movaps / movups for SSE integer load / store (one byte shorter).
1052 // The instructions selected below are then converted to MOVDQA/MOVDQU
1053 // during the SSE domain pass.
1054 let Predicates = [HasSSE1] in {
1055 def : Pat<(alignedloadv2i64 addr:$src),
1056 (MOVAPSrm addr:$src)>;
1057 def : Pat<(loadv2i64 addr:$src),
1058 (MOVUPSrm addr:$src)>;
1060 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1061 (MOVAPSmr addr:$dst, VR128:$src)>;
1062 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1063 (MOVAPSmr addr:$dst, VR128:$src)>;
1064 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1065 (MOVAPSmr addr:$dst, VR128:$src)>;
1066 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1067 (MOVAPSmr addr:$dst, VR128:$src)>;
1068 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1069 (MOVUPSmr addr:$dst, VR128:$src)>;
1070 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1071 (MOVUPSmr addr:$dst, VR128:$src)>;
1072 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1073 (MOVUPSmr addr:$dst, VR128:$src)>;
1074 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1075 (MOVUPSmr addr:$dst, VR128:$src)>;
1078 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1079 // bits are disregarded. FIXME: Set encoding to pseudo!
1080 let neverHasSideEffects = 1 in {
1081 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1082 "movaps\t{$src, $dst|$dst, $src}", [],
1083 IIC_SSE_MOVA_P_RR>, VEX;
1084 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1085 "movapd\t{$src, $dst|$dst, $src}", [],
1086 IIC_SSE_MOVA_P_RR>, VEX;
1087 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1088 "movaps\t{$src, $dst|$dst, $src}", [],
1090 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1091 "movapd\t{$src, $dst|$dst, $src}", [],
1095 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1096 // bits are disregarded. FIXME: Set encoding to pseudo!
1097 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1098 let isCodeGenOnly = 1 in {
1099 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1100 "movaps\t{$src, $dst|$dst, $src}",
1101 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1102 IIC_SSE_MOVA_P_RM>, VEX;
1103 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1104 "movapd\t{$src, $dst|$dst, $src}",
1105 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1106 IIC_SSE_MOVA_P_RM>, VEX;
1108 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1109 "movaps\t{$src, $dst|$dst, $src}",
1110 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1113 "movapd\t{$src, $dst|$dst, $src}",
1114 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1118 //===----------------------------------------------------------------------===//
1119 // SSE 1 & 2 - Move Low packed FP Instructions
1120 //===----------------------------------------------------------------------===//
1122 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1123 SDNode psnode, SDNode pdnode, string base_opc,
1124 string asm_opr, InstrItinClass itin> {
1125 def PSrm : PI<opc, MRMSrcMem,
1126 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1127 !strconcat(base_opc, "s", asm_opr),
1130 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1131 itin, SSEPackedSingle>, TB;
1133 def PDrm : PI<opc, MRMSrcMem,
1134 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1135 !strconcat(base_opc, "d", asm_opr),
1136 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1137 (scalar_to_vector (loadf64 addr:$src2)))))],
1138 itin, SSEPackedDouble>, TB, OpSize;
1141 let AddedComplexity = 20 in {
1142 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1144 IIC_SSE_MOV_LH>, VEX_4V;
1146 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1147 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1148 "\t{$src2, $dst|$dst, $src2}",
1152 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1153 "movlps\t{$src, $dst|$dst, $src}",
1154 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1155 (iPTR 0))), addr:$dst)],
1156 IIC_SSE_MOV_LH>, VEX;
1157 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1158 "movlpd\t{$src, $dst|$dst, $src}",
1159 [(store (f64 (vector_extract (v2f64 VR128:$src),
1160 (iPTR 0))), addr:$dst)],
1161 IIC_SSE_MOV_LH>, VEX;
1162 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1163 "movlps\t{$src, $dst|$dst, $src}",
1164 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1165 (iPTR 0))), addr:$dst)],
1167 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1168 "movlpd\t{$src, $dst|$dst, $src}",
1169 [(store (f64 (vector_extract (v2f64 VR128:$src),
1170 (iPTR 0))), addr:$dst)],
1173 let Predicates = [HasAVX] in {
1174 // Shuffle with VMOVLPS
1175 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1176 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1177 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1178 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1180 // Shuffle with VMOVLPD
1181 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1182 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1183 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1184 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1187 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1189 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1190 def : Pat<(store (v4i32 (X86Movlps
1191 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1192 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1193 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1195 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1196 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1198 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1201 let Predicates = [HasSSE1] in {
1202 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1203 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1204 (iPTR 0))), addr:$src1),
1205 (MOVLPSmr addr:$src1, VR128:$src2)>;
1207 // Shuffle with MOVLPS
1208 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1209 (MOVLPSrm VR128:$src1, addr:$src2)>;
1210 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1211 (MOVLPSrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(X86Movlps VR128:$src1,
1213 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1214 (MOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1219 (MOVLPSmr addr:$src1, VR128:$src2)>;
1220 def : Pat<(store (v4i32 (X86Movlps
1221 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1223 (MOVLPSmr addr:$src1, VR128:$src2)>;
1226 let Predicates = [HasSSE2] in {
1227 // Shuffle with MOVLPD
1228 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1229 (MOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1231 (MOVLPDrm VR128:$src1, addr:$src2)>;
1234 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1236 (MOVLPDmr addr:$src1, VR128:$src2)>;
1237 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1239 (MOVLPDmr addr:$src1, VR128:$src2)>;
1242 //===----------------------------------------------------------------------===//
1243 // SSE 1 & 2 - Move Hi packed FP Instructions
1244 //===----------------------------------------------------------------------===//
1246 let AddedComplexity = 20 in {
1247 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1249 IIC_SSE_MOV_LH>, VEX_4V;
1251 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1252 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1253 "\t{$src2, $dst|$dst, $src2}",
1257 // v2f64 extract element 1 is always custom lowered to unpack high to low
1258 // and extract element 0 so the non-store version isn't too horrible.
1259 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1260 "movhps\t{$src, $dst|$dst, $src}",
1261 [(store (f64 (vector_extract
1262 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1263 (bc_v2f64 (v4f32 VR128:$src))),
1264 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1265 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1266 "movhpd\t{$src, $dst|$dst, $src}",
1267 [(store (f64 (vector_extract
1268 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1269 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1270 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1271 "movhps\t{$src, $dst|$dst, $src}",
1272 [(store (f64 (vector_extract
1273 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1274 (bc_v2f64 (v4f32 VR128:$src))),
1275 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1276 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1277 "movhpd\t{$src, $dst|$dst, $src}",
1278 [(store (f64 (vector_extract
1279 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1282 let Predicates = [HasAVX] in {
1284 def : Pat<(X86Movlhps VR128:$src1,
1285 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1286 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1287 def : Pat<(X86Movlhps VR128:$src1,
1288 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1289 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1291 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1292 // is during lowering, where it's not possible to recognize the load fold
1293 // cause it has two uses through a bitcast. One use disappears at isel time
1294 // and the fold opportunity reappears.
1295 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1296 (scalar_to_vector (loadf64 addr:$src2)))),
1297 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1300 let Predicates = [HasSSE1] in {
1302 def : Pat<(X86Movlhps VR128:$src1,
1303 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1304 (MOVHPSrm VR128:$src1, addr:$src2)>;
1305 def : Pat<(X86Movlhps VR128:$src1,
1306 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1307 (MOVHPSrm VR128:$src1, addr:$src2)>;
1310 let Predicates = [HasSSE2] in {
1311 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1312 // is during lowering, where it's not possible to recognize the load fold
1313 // cause it has two uses through a bitcast. One use disappears at isel time
1314 // and the fold opportunity reappears.
1315 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1316 (scalar_to_vector (loadf64 addr:$src2)))),
1317 (MOVHPDrm VR128:$src1, addr:$src2)>;
1320 //===----------------------------------------------------------------------===//
1321 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1322 //===----------------------------------------------------------------------===//
1324 let AddedComplexity = 20 in {
1325 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1326 (ins VR128:$src1, VR128:$src2),
1327 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1329 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1332 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1333 (ins VR128:$src1, VR128:$src2),
1334 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1336 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1340 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1341 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1342 (ins VR128:$src1, VR128:$src2),
1343 "movlhps\t{$src2, $dst|$dst, $src2}",
1345 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1347 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1348 (ins VR128:$src1, VR128:$src2),
1349 "movhlps\t{$src2, $dst|$dst, $src2}",
1351 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 let Predicates = [HasAVX] in {
1357 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1358 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1359 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1360 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1363 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1364 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1367 let Predicates = [HasSSE1] in {
1369 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1370 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1371 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1372 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1375 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1376 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1379 //===----------------------------------------------------------------------===//
1380 // SSE 1 & 2 - Conversion Instructions
1381 //===----------------------------------------------------------------------===//
1383 def SSE_CVT_PD : OpndItins<
1384 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1387 def SSE_CVT_PS : OpndItins<
1388 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1391 def SSE_CVT_Scalar : OpndItins<
1392 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1395 def SSE_CVT_SS2SI_32 : OpndItins<
1396 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1399 def SSE_CVT_SS2SI_64 : OpndItins<
1400 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1403 def SSE_CVT_SD2SI : OpndItins<
1404 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1407 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1408 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1409 string asm, OpndItins itins> {
1410 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1411 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1413 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1414 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1418 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1420 string asm, Domain d, OpndItins itins> {
1421 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1422 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1424 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1425 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1429 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 X86MemOperand x86memop, string asm> {
1431 let neverHasSideEffects = 1 in {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1433 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1436 (ins DstRC:$src1, x86memop:$src),
1437 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1438 } // neverHasSideEffects = 1
1441 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1442 "cvttss2si\t{$src, $dst|$dst, $src}",
1445 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1446 "cvttss2si\t{$src, $dst|$dst, $src}",
1448 XS, VEX, VEX_W, VEX_LIG;
1449 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1450 "cvttsd2si\t{$src, $dst|$dst, $src}",
1453 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1454 "cvttsd2si\t{$src, $dst|$dst, $src}",
1456 XD, VEX, VEX_W, VEX_LIG;
1458 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1459 // register, but the same isn't true when only using memory operands,
1460 // provide other assembly "l" and "q" forms to address this explicitly
1461 // where appropriate to do so.
1462 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1463 XS, VEX_4V, VEX_LIG;
1464 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1465 XS, VEX_4V, VEX_W, VEX_LIG;
1466 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1467 XD, VEX_4V, VEX_LIG;
1468 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1469 XD, VEX_4V, VEX_LIG;
1470 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1471 XD, VEX_4V, VEX_W, VEX_LIG;
1473 let Predicates = [HasAVX], AddedComplexity = 1 in {
1474 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1475 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1476 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1477 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1478 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1479 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1480 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1481 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1483 def : Pat<(f32 (sint_to_fp GR32:$src)),
1484 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1485 def : Pat<(f32 (sint_to_fp GR64:$src)),
1486 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1487 def : Pat<(f64 (sint_to_fp GR32:$src)),
1488 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1489 def : Pat<(f64 (sint_to_fp GR64:$src)),
1490 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1493 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1494 "cvttss2si\t{$src, $dst|$dst, $src}",
1495 SSE_CVT_SS2SI_32>, XS;
1496 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1497 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1498 SSE_CVT_SS2SI_64>, XS, REX_W;
1499 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1500 "cvttsd2si\t{$src, $dst|$dst, $src}",
1502 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1503 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1504 SSE_CVT_SD2SI>, XD, REX_W;
1505 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1506 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1507 SSE_CVT_Scalar>, XS;
1508 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1509 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1510 SSE_CVT_Scalar>, XS, REX_W;
1511 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1512 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1513 SSE_CVT_Scalar>, XD;
1514 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1515 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1516 SSE_CVT_Scalar>, XD, REX_W;
1518 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1519 // and/or XMM operand(s).
1521 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1522 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1523 string asm, OpndItins itins> {
1524 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1526 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1527 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1528 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1529 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm>;
1532 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1533 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1534 PatFrag ld_frag, string asm, OpndItins itins,
1536 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1538 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1539 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1540 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1542 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1543 (ins DstRC:$src1, x86memop:$src2),
1545 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1546 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1547 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1551 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1552 f128mem, load, "cvtsd2si", SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1553 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1554 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si",
1555 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1557 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1558 f128mem, load, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1559 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1560 f128mem, load, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1563 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1564 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1565 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1566 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1567 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss",
1568 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1570 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1571 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1572 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1573 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1574 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd",
1575 SSE_CVT_Scalar, 0>, XD,
1578 let Constraints = "$src1 = $dst" in {
1579 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1580 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1581 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1582 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1583 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1584 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1585 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1586 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1587 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1588 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1589 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1590 "cvtsi2sd", SSE_CVT_Scalar>, XD, REX_W;
1595 // Aliases for intrinsics
1596 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1597 f32mem, load, "cvttss2si",
1598 SSE_CVT_SS2SI_32>, XS, VEX;
1599 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1600 int_x86_sse_cvttss2si64, f32mem, load,
1601 "cvttss2si", SSE_CVT_SS2SI_64>,
1603 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1604 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1606 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1607 int_x86_sse2_cvttsd2si64, f128mem, load,
1608 "cvttsd2si", SSE_CVT_SD2SI>,
1610 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1611 f32mem, load, "cvttss2si",
1612 SSE_CVT_SS2SI_32>, XS;
1613 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1614 int_x86_sse_cvttss2si64, f32mem, load,
1615 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1617 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1618 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1620 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1621 int_x86_sse2_cvttsd2si64, f128mem, load,
1622 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1625 let Pattern = []<dag> in {
1626 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1627 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1628 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1629 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1630 "cvtss2si\t{$src, $dst|$dst, $src}",
1631 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1632 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1633 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1634 SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
1635 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1636 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1637 SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
1640 let Pattern = []<dag> in {
1641 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1642 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1643 SSE_CVT_SS2SI_32>, XS;
1644 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1645 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1646 SSE_CVT_SS2SI_64>, XS, REX_W;
1647 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1648 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1649 SSEPackedSingle, SSE_CVT_PS>,
1650 TB; /* PD SSE3 form is avaiable */
1653 let Predicates = [HasAVX] in {
1654 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1655 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1656 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1657 (VCVTSS2SIrm addr:$src)>;
1658 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1659 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1660 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1661 (VCVTSS2SI64rm addr:$src)>;
1664 let Predicates = [HasSSE1] in {
1665 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1666 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1667 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1668 (CVTSS2SIrm addr:$src)>;
1669 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1670 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1671 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1672 (CVTSS2SI64rm addr:$src)>;
1677 // Convert scalar double to scalar single
1678 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1679 (ins FR64:$src1, FR64:$src2),
1680 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1681 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1683 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1684 (ins FR64:$src1, f64mem:$src2),
1685 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1686 [], IIC_SSE_CVT_Scalar_RM>,
1687 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1689 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1692 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1693 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1694 [(set FR32:$dst, (fround FR64:$src))],
1695 IIC_SSE_CVT_Scalar_RR>;
1696 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1697 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1698 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1699 IIC_SSE_CVT_Scalar_RM>,
1701 Requires<[HasSSE2, OptForSize]>;
1703 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1704 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1707 let Constraints = "$src1 = $dst" in
1708 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1709 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1710 SSE_CVT_Scalar>, XS;
1712 // Convert scalar single to scalar double
1713 // SSE2 instructions with XS prefix
1714 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1715 (ins FR32:$src1, FR32:$src2),
1716 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1717 [], IIC_SSE_CVT_Scalar_RR>,
1718 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1720 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1721 (ins FR32:$src1, f32mem:$src2),
1722 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1723 [], IIC_SSE_CVT_Scalar_RM>,
1724 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1726 let Predicates = [HasAVX] in {
1727 def : Pat<(f64 (fextend FR32:$src)),
1728 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1729 def : Pat<(fextend (loadf32 addr:$src)),
1730 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1731 def : Pat<(extloadf32 addr:$src),
1732 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1735 def : Pat<(extloadf32 addr:$src),
1736 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1737 Requires<[HasAVX, OptForSpeed]>;
1739 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1740 "cvtss2sd\t{$src, $dst|$dst, $src}",
1741 [(set FR64:$dst, (fextend FR32:$src))],
1742 IIC_SSE_CVT_Scalar_RR>, XS,
1743 Requires<[HasSSE2]>;
1744 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1745 "cvtss2sd\t{$src, $dst|$dst, $src}",
1746 [(set FR64:$dst, (extloadf32 addr:$src))],
1747 IIC_SSE_CVT_Scalar_RM>, XS,
1748 Requires<[HasSSE2, OptForSize]>;
1750 // extload f32 -> f64. This matches load+fextend because we have a hack in
1751 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1753 // Since these loads aren't folded into the fextend, we have to match it
1755 def : Pat<(fextend (loadf32 addr:$src)),
1756 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1757 def : Pat<(extloadf32 addr:$src),
1758 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1760 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1761 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1762 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1763 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1765 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V,
1767 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1768 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1769 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1770 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1771 (load addr:$src2)))],
1772 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V,
1774 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1775 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1776 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1777 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1778 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1780 IIC_SSE_CVT_Scalar_RR>, XS,
1781 Requires<[HasSSE2]>;
1782 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1783 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1784 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1785 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1786 (load addr:$src2)))],
1787 IIC_SSE_CVT_Scalar_RM>, XS,
1788 Requires<[HasSSE2]>;
1791 // Convert doubleword to packed single/double fp
1792 // SSE2 instructions without OpSize prefix
1793 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1794 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1795 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
1797 TB, VEX, Requires<[HasAVX]>;
1798 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1799 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1800 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1801 (bitconvert (memopv2i64 addr:$src))))],
1803 TB, VEX, Requires<[HasAVX]>;
1804 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
1808 TB, Requires<[HasSSE2]>;
1809 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1810 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1811 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1812 (bitconvert (memopv2i64 addr:$src))))],
1814 TB, Requires<[HasSSE2]>;
1816 // SSE2 instructions with XS prefix
1817 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1818 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1819 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
1821 XS, VEX, Requires<[HasAVX]>;
1822 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1823 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1824 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1825 (bitconvert (memopv2i64 addr:$src))))],
1827 XS, VEX, Requires<[HasAVX]>;
1828 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1829 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1830 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
1832 XS, Requires<[HasSSE2]>;
1833 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1834 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1835 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1836 (bitconvert (memopv2i64 addr:$src))))],
1838 XS, Requires<[HasSSE2]>;
1841 // Convert packed single/double fp to doubleword
1842 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1843 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1844 IIC_SSE_CVT_PS_RR>, VEX;
1845 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1846 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1847 IIC_SSE_CVT_PS_RM>, VEX;
1848 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1849 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1850 IIC_SSE_CVT_PS_RR>, VEX;
1851 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1852 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1853 IIC_SSE_CVT_PS_RM>, VEX;
1854 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1855 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1857 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1858 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1861 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1862 "cvtps2dq\t{$src, $dst|$dst, $src}",
1863 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1866 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1868 "cvtps2dq\t{$src, $dst|$dst, $src}",
1869 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1870 (memop addr:$src)))],
1871 IIC_SSE_CVT_PS_RM>, VEX;
1872 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1873 "cvtps2dq\t{$src, $dst|$dst, $src}",
1874 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1876 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1877 "cvtps2dq\t{$src, $dst|$dst, $src}",
1878 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1879 (memop addr:$src)))],
1882 // SSE2 packed instructions with XD prefix
1883 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1884 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1885 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1887 XD, VEX, Requires<[HasAVX]>;
1888 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1889 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1890 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1891 (memop addr:$src)))],
1893 XD, VEX, Requires<[HasAVX]>;
1894 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1895 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1896 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1898 XD, Requires<[HasSSE2]>;
1899 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1900 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1902 (memop addr:$src)))],
1904 XD, Requires<[HasSSE2]>;
1907 // Convert with truncation packed single/double fp to doubleword
1908 // SSE2 packed instructions with XS prefix
1909 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1910 "cvttps2dq\t{$src, $dst|$dst, $src}",
1912 (int_x86_sse2_cvttps2dq VR128:$src))],
1913 IIC_SSE_CVT_PS_RR>, VEX;
1914 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1915 "cvttps2dq\t{$src, $dst|$dst, $src}",
1916 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1917 (memop addr:$src)))],
1918 IIC_SSE_CVT_PS_RM>, VEX;
1919 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1920 "cvttps2dq\t{$src, $dst|$dst, $src}",
1922 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1923 IIC_SSE_CVT_PS_RR>, VEX;
1924 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1925 "cvttps2dq\t{$src, $dst|$dst, $src}",
1926 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1927 (memopv8f32 addr:$src)))],
1928 IIC_SSE_CVT_PS_RM>, VEX;
1930 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1931 "cvttps2dq\t{$src, $dst|$dst, $src}",
1933 (int_x86_sse2_cvttps2dq VR128:$src))],
1935 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1936 "cvttps2dq\t{$src, $dst|$dst, $src}",
1938 (int_x86_sse2_cvttps2dq (memop addr:$src)))],
1941 let Predicates = [HasAVX] in {
1942 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1943 (Int_VCVTDQ2PSrr VR128:$src)>;
1944 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1945 (Int_VCVTDQ2PSrm addr:$src)>;
1947 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1948 (VCVTTPS2DQrr VR128:$src)>;
1949 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1950 (VCVTTPS2DQrm addr:$src)>;
1952 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1953 (VCVTDQ2PSYrr VR256:$src)>;
1954 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1955 (VCVTDQ2PSYrm addr:$src)>;
1957 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1958 (VCVTTPS2DQYrr VR256:$src)>;
1959 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1960 (VCVTTPS2DQYrm addr:$src)>;
1963 let Predicates = [HasSSE2] in {
1964 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1965 (Int_CVTDQ2PSrr VR128:$src)>;
1966 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1967 (Int_CVTDQ2PSrm addr:$src)>;
1969 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1970 (CVTTPS2DQrr VR128:$src)>;
1971 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1972 (CVTTPS2DQrm addr:$src)>;
1975 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1976 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1978 (int_x86_sse2_cvttpd2dq VR128:$src))],
1979 IIC_SSE_CVT_PD_RR>, VEX;
1980 let isCodeGenOnly = 1 in
1981 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1982 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1983 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1984 (memop addr:$src)))],
1985 IIC_SSE_CVT_PD_RM>, VEX;
1986 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1988 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1990 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1991 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1992 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1993 (memop addr:$src)))],
1996 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1997 // register, but the same isn't true when using memory operands instead.
1998 // Provide other assembly rr and rm forms to address this explicitly.
1999 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2000 "cvttpd2dq\t{$src, $dst|$dst, $src}", [],
2001 IIC_SSE_CVT_PD_RR>, VEX;
2004 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2005 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
2006 IIC_SSE_CVT_PD_RR>, VEX;
2007 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2008 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
2009 IIC_SSE_CVT_PD_RM>, VEX;
2012 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2013 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
2014 IIC_SSE_CVT_PD_RR>, VEX;
2015 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2016 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
2017 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2019 // Convert packed single to packed double
2020 let Predicates = [HasAVX] in {
2021 // SSE2 instructions without OpSize prefix
2022 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2023 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2024 IIC_SSE_CVT_PD_RR>, TB, VEX;
2025 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2026 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2027 IIC_SSE_CVT_PD_RM>, TB, VEX;
2028 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2029 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2030 IIC_SSE_CVT_PD_RR>, TB, VEX;
2031 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2032 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2033 IIC_SSE_CVT_PD_RM>, TB, VEX;
2035 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2036 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2037 IIC_SSE_CVT_PD_RR>, TB;
2038 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2039 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2040 IIC_SSE_CVT_PD_RM>, TB;
2042 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2043 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2044 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2046 TB, VEX, Requires<[HasAVX]>;
2047 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2048 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2049 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2050 (load addr:$src)))],
2052 TB, VEX, Requires<[HasAVX]>;
2053 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2054 "cvtps2pd\t{$src, $dst|$dst, $src}",
2055 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2057 TB, Requires<[HasSSE2]>;
2058 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2059 "cvtps2pd\t{$src, $dst|$dst, $src}",
2060 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2061 (load addr:$src)))],
2063 TB, Requires<[HasSSE2]>;
2065 // Convert packed double to packed single
2066 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2067 // register, but the same isn't true when using memory operands instead.
2068 // Provide other assembly rr and rm forms to address this explicitly.
2069 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2070 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2071 IIC_SSE_CVT_PD_RR>, VEX;
2072 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2073 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2074 IIC_SSE_CVT_PD_RR>, VEX;
2077 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2078 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2079 IIC_SSE_CVT_PD_RR>, VEX;
2080 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2081 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2082 IIC_SSE_CVT_PD_RM>, VEX;
2085 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2086 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2087 IIC_SSE_CVT_PD_RR>, VEX;
2088 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2089 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2090 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2091 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2092 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2094 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2095 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2099 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2100 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2101 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2103 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
2105 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2106 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2107 (memop addr:$src)))],
2109 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2110 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2111 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2113 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2114 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2115 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2116 (memop addr:$src)))],
2119 // AVX 256-bit register conversion intrinsics
2120 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2121 // whenever possible to avoid declaring two versions of each one.
2122 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2123 (VCVTDQ2PSYrr VR256:$src)>;
2124 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2125 (VCVTDQ2PSYrm addr:$src)>;
2127 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
2128 (VCVTPD2PSYrr VR256:$src)>;
2129 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
2130 (VCVTPD2PSYrm addr:$src)>;
2132 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
2133 (VCVTPS2DQYrr VR256:$src)>;
2134 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
2135 (VCVTPS2DQYrm addr:$src)>;
2137 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
2138 (VCVTPS2PDYrr VR128:$src)>;
2139 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
2140 (VCVTPS2PDYrm addr:$src)>;
2142 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
2143 (VCVTTPD2DQYrr VR256:$src)>;
2144 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
2145 (VCVTTPD2DQYrm addr:$src)>;
2147 // Match fround and fextend for 128/256-bit conversions
2148 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2149 (VCVTPD2PSYrr VR256:$src)>;
2150 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2151 (VCVTPD2PSYrm addr:$src)>;
2153 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2154 (VCVTPS2PDYrr VR128:$src)>;
2155 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2156 (VCVTPS2PDYrm addr:$src)>;
2158 //===----------------------------------------------------------------------===//
2159 // SSE 1 & 2 - Compare Instructions
2160 //===----------------------------------------------------------------------===//
2162 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2163 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2164 Operand CC, SDNode OpNode, ValueType VT,
2165 PatFrag ld_frag, string asm, string asm_alt,
2167 def rr : SIi8<0xC2, MRMSrcReg,
2168 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2169 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2171 def rm : SIi8<0xC2, MRMSrcMem,
2172 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2173 [(set RC:$dst, (OpNode (VT RC:$src1),
2174 (ld_frag addr:$src2), imm:$cc))],
2177 // Accept explicit immediate argument form instead of comparison code.
2178 let neverHasSideEffects = 1 in {
2179 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2180 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2181 IIC_SSE_ALU_F32S_RR>;
2183 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2184 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2185 IIC_SSE_ALU_F32S_RM>;
2189 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2190 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2191 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2193 XS, VEX_4V, VEX_LIG;
2194 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2195 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2196 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2197 SSE_ALU_F32S>, // same latency as 32 bit compare
2198 XD, VEX_4V, VEX_LIG;
2200 let Constraints = "$src1 = $dst" in {
2201 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2202 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2203 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2205 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2206 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2207 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2208 SSE_ALU_F32S>, // same latency as 32 bit compare
2212 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2213 Intrinsic Int, string asm, OpndItins itins> {
2214 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2215 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2216 [(set VR128:$dst, (Int VR128:$src1,
2217 VR128:$src, imm:$cc))],
2219 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2220 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2221 [(set VR128:$dst, (Int VR128:$src1,
2222 (load addr:$src), imm:$cc))],
2226 // Aliases to match intrinsics which expect XMM operand(s).
2227 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2228 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2231 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2232 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2233 SSE_ALU_F32S>, // same latency as f32
2235 let Constraints = "$src1 = $dst" in {
2236 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2237 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2239 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2240 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2241 SSE_ALU_F32S>, // same latency as f32
2246 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2247 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2248 ValueType vt, X86MemOperand x86memop,
2249 PatFrag ld_frag, string OpcodeStr, Domain d> {
2250 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2251 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2252 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2253 IIC_SSE_COMIS_RR, d>;
2254 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2255 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2256 [(set EFLAGS, (OpNode (vt RC:$src1),
2257 (ld_frag addr:$src2)))],
2258 IIC_SSE_COMIS_RM, d>;
2261 let Defs = [EFLAGS] in {
2262 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2263 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2264 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2265 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2267 let Pattern = []<dag> in {
2268 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2269 "comiss", SSEPackedSingle>, TB, VEX,
2271 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2272 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2276 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2277 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2278 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2279 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2281 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2282 load, "comiss", SSEPackedSingle>, TB, VEX;
2283 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2284 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2285 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2286 "ucomiss", SSEPackedSingle>, TB;
2287 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2288 "ucomisd", SSEPackedDouble>, TB, OpSize;
2290 let Pattern = []<dag> in {
2291 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2292 "comiss", SSEPackedSingle>, TB;
2293 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2294 "comisd", SSEPackedDouble>, TB, OpSize;
2297 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2298 load, "ucomiss", SSEPackedSingle>, TB;
2299 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2300 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2302 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2303 "comiss", SSEPackedSingle>, TB;
2304 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2305 "comisd", SSEPackedDouble>, TB, OpSize;
2306 } // Defs = [EFLAGS]
2308 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2309 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2310 Operand CC, Intrinsic Int, string asm,
2311 string asm_alt, Domain d> {
2312 def rri : PIi8<0xC2, MRMSrcReg,
2313 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2314 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2315 IIC_SSE_CMPP_RR, d>;
2316 def rmi : PIi8<0xC2, MRMSrcMem,
2317 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2318 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2319 IIC_SSE_CMPP_RM, d>;
2321 // Accept explicit immediate argument form instead of comparison code.
2322 let neverHasSideEffects = 1 in {
2323 def rri_alt : PIi8<0xC2, MRMSrcReg,
2324 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2325 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2326 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2327 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2328 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2332 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2333 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2334 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2335 SSEPackedSingle>, TB, VEX_4V;
2336 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2337 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2338 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2339 SSEPackedDouble>, TB, OpSize, VEX_4V;
2340 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2341 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2342 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2343 SSEPackedSingle>, TB, VEX_4V;
2344 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2345 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2346 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2347 SSEPackedDouble>, TB, OpSize, VEX_4V;
2348 let Constraints = "$src1 = $dst" in {
2349 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2350 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2351 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2352 SSEPackedSingle>, TB;
2353 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2354 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2355 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2356 SSEPackedDouble>, TB, OpSize;
2359 let Predicates = [HasAVX] in {
2360 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2361 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2362 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2363 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2364 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2365 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2366 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2367 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2369 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2370 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2371 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2372 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2373 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2374 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2375 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2376 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2379 let Predicates = [HasSSE1] in {
2380 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2381 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2382 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2383 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2386 let Predicates = [HasSSE2] in {
2387 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2388 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2389 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2390 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2393 //===----------------------------------------------------------------------===//
2394 // SSE 1 & 2 - Shuffle Instructions
2395 //===----------------------------------------------------------------------===//
2397 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2398 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2399 ValueType vt, string asm, PatFrag mem_frag,
2400 Domain d, bit IsConvertibleToThreeAddress = 0> {
2401 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2402 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2403 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2404 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2405 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2406 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2407 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2408 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2409 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2412 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2413 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2414 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2415 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2416 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2417 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2418 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2419 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2420 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2421 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2422 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2423 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2425 let Constraints = "$src1 = $dst" in {
2426 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2427 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2428 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2430 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2431 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2432 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2436 let Predicates = [HasAVX] in {
2437 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2438 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2439 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2440 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2441 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2443 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2444 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2445 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2446 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2447 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2450 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2451 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2452 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2453 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2454 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2456 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2457 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2458 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2459 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2460 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2463 let Predicates = [HasSSE1] in {
2464 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2465 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2466 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2467 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2468 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2471 let Predicates = [HasSSE2] in {
2472 // Generic SHUFPD patterns
2473 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2474 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2475 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2476 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2477 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2480 //===----------------------------------------------------------------------===//
2481 // SSE 1 & 2 - Unpack Instructions
2482 //===----------------------------------------------------------------------===//
2484 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2485 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2486 PatFrag mem_frag, RegisterClass RC,
2487 X86MemOperand x86memop, string asm,
2489 def rr : PI<opc, MRMSrcReg,
2490 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2492 (vt (OpNode RC:$src1, RC:$src2)))],
2494 def rm : PI<opc, MRMSrcMem,
2495 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2497 (vt (OpNode RC:$src1,
2498 (mem_frag addr:$src2))))],
2502 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2503 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2504 SSEPackedSingle>, TB, VEX_4V;
2505 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2506 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2507 SSEPackedDouble>, TB, OpSize, VEX_4V;
2508 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2509 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2510 SSEPackedSingle>, TB, VEX_4V;
2511 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2512 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2513 SSEPackedDouble>, TB, OpSize, VEX_4V;
2515 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2516 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2517 SSEPackedSingle>, TB, VEX_4V;
2518 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2519 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2520 SSEPackedDouble>, TB, OpSize, VEX_4V;
2521 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2522 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2523 SSEPackedSingle>, TB, VEX_4V;
2524 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2525 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2526 SSEPackedDouble>, TB, OpSize, VEX_4V;
2528 let Constraints = "$src1 = $dst" in {
2529 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2530 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2531 SSEPackedSingle>, TB;
2532 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2533 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2534 SSEPackedDouble>, TB, OpSize;
2535 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2536 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2537 SSEPackedSingle>, TB;
2538 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2539 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2540 SSEPackedDouble>, TB, OpSize;
2541 } // Constraints = "$src1 = $dst"
2543 let Predicates = [HasAVX], AddedComplexity = 1 in {
2544 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2545 // problem is during lowering, where it's not possible to recognize the load
2546 // fold cause it has two uses through a bitcast. One use disappears at isel
2547 // time and the fold opportunity reappears.
2548 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2549 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2552 let Predicates = [HasSSE2] in {
2553 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2554 // problem is during lowering, where it's not possible to recognize the load
2555 // fold cause it has two uses through a bitcast. One use disappears at isel
2556 // time and the fold opportunity reappears.
2557 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2558 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2561 //===----------------------------------------------------------------------===//
2562 // SSE 1 & 2 - Extract Floating-Point Sign mask
2563 //===----------------------------------------------------------------------===//
2565 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2566 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2568 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2569 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2570 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2571 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2572 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2573 IIC_SSE_MOVMSK, d>, REX_W;
2576 let Predicates = [HasAVX] in {
2577 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2578 "movmskps", SSEPackedSingle>, TB, VEX;
2579 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2580 "movmskpd", SSEPackedDouble>, TB,
2582 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2583 "movmskps", SSEPackedSingle>, TB, VEX;
2584 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2585 "movmskpd", SSEPackedDouble>, TB,
2588 def : Pat<(i32 (X86fgetsign FR32:$src)),
2589 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2591 def : Pat<(i64 (X86fgetsign FR32:$src)),
2592 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2594 def : Pat<(i32 (X86fgetsign FR64:$src)),
2595 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2597 def : Pat<(i64 (X86fgetsign FR64:$src)),
2598 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2602 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2603 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2604 SSEPackedSingle>, TB, VEX;
2605 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2606 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2607 SSEPackedDouble>, TB,
2609 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2610 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2611 SSEPackedSingle>, TB, VEX;
2612 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2613 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2614 SSEPackedDouble>, TB,
2618 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2619 SSEPackedSingle>, TB;
2620 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2621 SSEPackedDouble>, TB, OpSize;
2623 def : Pat<(i32 (X86fgetsign FR32:$src)),
2624 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2625 sub_ss))>, Requires<[HasSSE1]>;
2626 def : Pat<(i64 (X86fgetsign FR32:$src)),
2627 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2628 sub_ss))>, Requires<[HasSSE1]>;
2629 def : Pat<(i32 (X86fgetsign FR64:$src)),
2630 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2631 sub_sd))>, Requires<[HasSSE2]>;
2632 def : Pat<(i64 (X86fgetsign FR64:$src)),
2633 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2634 sub_sd))>, Requires<[HasSSE2]>;
2636 //===---------------------------------------------------------------------===//
2637 // SSE2 - Packed Integer Logical Instructions
2638 //===---------------------------------------------------------------------===//
2640 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2642 /// PDI_binop_rm - Simple SSE2 binary operator.
2643 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2644 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2645 X86MemOperand x86memop,
2647 bit IsCommutable = 0,
2649 let isCommutable = IsCommutable in
2650 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2651 (ins RC:$src1, RC:$src2),
2653 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2654 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2655 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2656 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2657 (ins RC:$src1, x86memop:$src2),
2659 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2660 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2661 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2662 (bitconvert (memop_frag addr:$src2)))))],
2665 } // ExeDomain = SSEPackedInt
2667 // These are ordered here for pattern ordering requirements with the fp versions
2669 let Predicates = [HasAVX] in {
2670 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2671 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2672 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2673 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2674 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2675 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2676 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2677 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2680 let Constraints = "$src1 = $dst" in {
2681 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2682 i128mem, SSE_BIT_ITINS_P, 1>;
2683 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2684 i128mem, SSE_BIT_ITINS_P, 1>;
2685 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2686 i128mem, SSE_BIT_ITINS_P, 1>;
2687 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2688 i128mem, SSE_BIT_ITINS_P, 0>;
2689 } // Constraints = "$src1 = $dst"
2691 let Predicates = [HasAVX2] in {
2692 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2693 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2694 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2695 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2696 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2697 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2698 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2699 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2702 //===----------------------------------------------------------------------===//
2703 // SSE 1 & 2 - Logical Instructions
2704 //===----------------------------------------------------------------------===//
2706 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2708 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2709 SDNode OpNode, OpndItins itins> {
2710 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2711 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2714 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2715 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2718 let Constraints = "$src1 = $dst" in {
2719 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2720 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2723 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2724 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2729 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2730 let mayLoad = 0 in {
2731 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2733 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2735 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2739 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2740 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2743 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2745 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2747 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2748 // are all promoted to v2i64, and the patterns are covered by the int
2749 // version. This is needed in SSE only, because v2i64 isn't supported on
2750 // SSE1, but only on SSE2.
2751 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2752 !strconcat(OpcodeStr, "ps"), f128mem, [],
2753 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2754 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2756 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2757 !strconcat(OpcodeStr, "pd"), f128mem,
2758 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2759 (bc_v2i64 (v2f64 VR128:$src2))))],
2760 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2761 (memopv2i64 addr:$src2)))], 0>,
2763 let Constraints = "$src1 = $dst" in {
2764 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2765 !strconcat(OpcodeStr, "ps"), f128mem,
2766 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2767 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2768 (memopv2i64 addr:$src2)))]>, TB;
2770 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2771 !strconcat(OpcodeStr, "pd"), f128mem,
2772 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2773 (bc_v2i64 (v2f64 VR128:$src2))))],
2774 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2775 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2779 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2781 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2783 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2784 !strconcat(OpcodeStr, "ps"), f256mem,
2785 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2786 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2787 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2789 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2790 !strconcat(OpcodeStr, "pd"), f256mem,
2791 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2792 (bc_v4i64 (v4f64 VR256:$src2))))],
2793 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2794 (memopv4i64 addr:$src2)))], 0>,
2798 // AVX 256-bit packed logical ops forms
2799 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2800 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2801 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2802 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2804 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2805 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2806 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2807 let isCommutable = 0 in
2808 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2810 //===----------------------------------------------------------------------===//
2811 // SSE 1 & 2 - Arithmetic Instructions
2812 //===----------------------------------------------------------------------===//
2814 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2817 /// In addition, we also have a special variant of the scalar form here to
2818 /// represent the associated intrinsic operation. This form is unlike the
2819 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2820 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2822 /// These three forms can each be reg+reg or reg+mem.
2825 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2827 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2830 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2831 OpNode, FR32, f32mem,
2832 itins.s, Is2Addr>, XS;
2833 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2834 OpNode, FR64, f64mem,
2835 itins.d, Is2Addr>, XD;
2838 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2841 let mayLoad = 0 in {
2842 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2843 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2845 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2846 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2851 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2854 let mayLoad = 0 in {
2855 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2856 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2858 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2859 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2864 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2867 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2868 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2869 itins.s, Is2Addr>, XS;
2870 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2871 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2872 itins.d, Is2Addr>, XD;
2875 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2878 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2879 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2880 SSEPackedSingle, itins.s, Is2Addr>,
2883 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2884 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2885 SSEPackedDouble, itins.d, Is2Addr>,
2889 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2891 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2892 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2893 SSEPackedSingle, itins.s, 0>, TB;
2895 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2896 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2897 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2900 // Binary Arithmetic instructions
2901 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2902 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2904 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2905 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2907 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2908 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2910 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2911 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2914 let isCommutable = 0 in {
2915 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2916 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2918 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2919 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>, VEX_4V;
2920 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2921 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2923 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2924 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2926 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2927 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2929 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2930 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2931 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2932 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2934 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2935 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2937 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2938 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2939 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2940 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2944 let Constraints = "$src1 = $dst" in {
2945 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2946 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2947 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2948 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2949 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2950 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2952 let isCommutable = 0 in {
2953 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2954 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2955 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2956 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2957 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2958 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2959 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2960 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2961 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2962 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2963 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2964 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2965 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2966 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2971 /// In addition, we also have a special variant of the scalar form here to
2972 /// represent the associated intrinsic operation. This form is unlike the
2973 /// plain scalar form, in that it takes an entire vector (instead of a
2974 /// scalar) and leaves the top elements undefined.
2976 /// And, we have a special variant form for a full-vector intrinsic form.
2978 def SSE_SQRTP : OpndItins<
2979 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2982 def SSE_SQRTS : OpndItins<
2983 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2986 def SSE_RCPP : OpndItins<
2987 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
2990 def SSE_RCPS : OpndItins<
2991 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
2994 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2995 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2996 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
2997 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2998 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2999 [(set FR32:$dst, (OpNode FR32:$src))]>;
3000 // For scalar unary operations, fold a load into the operation
3001 // only in OptForSize mode. It eliminates an instruction, but it also
3002 // eliminates a whole-register clobber (the load), so it introduces a
3003 // partial register update condition.
3004 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3005 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3006 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3007 Requires<[HasSSE1, OptForSize]>;
3008 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3009 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3010 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3011 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3012 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3013 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3016 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3017 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3018 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3019 !strconcat(OpcodeStr,
3020 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3022 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3023 !strconcat(OpcodeStr,
3024 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3025 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3026 (ins VR128:$src1, ssmem:$src2),
3027 !strconcat(OpcodeStr,
3028 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3031 /// sse1_fp_unop_p - SSE1 unops in packed form.
3032 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3034 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3035 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3036 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3037 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3038 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3039 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3042 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3043 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3045 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3046 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3047 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3049 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3050 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3051 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3055 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3056 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3057 Intrinsic V4F32Int, OpndItins itins> {
3058 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3059 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3060 [(set VR128:$dst, (V4F32Int VR128:$src))],
3062 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3063 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3064 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3068 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3069 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3070 Intrinsic V4F32Int, OpndItins itins> {
3071 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3072 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3073 [(set VR256:$dst, (V4F32Int VR256:$src))],
3075 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3076 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3077 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3081 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3082 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3083 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3084 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3085 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3086 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3087 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3088 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3089 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3090 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3091 Requires<[HasSSE2, OptForSize]>;
3092 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3093 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3094 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3095 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3096 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3097 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3100 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3101 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3102 let neverHasSideEffects = 1 in {
3103 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3104 !strconcat(OpcodeStr,
3105 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3107 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3108 !strconcat(OpcodeStr,
3109 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3111 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3112 (ins VR128:$src1, sdmem:$src2),
3113 !strconcat(OpcodeStr,
3114 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3117 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3118 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3119 SDNode OpNode, OpndItins itins> {
3120 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3121 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3122 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3123 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3124 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3125 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3128 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3129 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3131 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3132 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3133 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3135 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3136 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3137 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3141 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3142 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3143 Intrinsic V2F64Int, OpndItins itins> {
3144 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3145 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3146 [(set VR128:$dst, (V2F64Int VR128:$src))],
3148 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3149 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3150 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3154 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3155 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3156 Intrinsic V2F64Int, OpndItins itins> {
3157 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3158 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3159 [(set VR256:$dst, (V2F64Int VR256:$src))],
3161 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3162 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3163 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3167 let Predicates = [HasAVX] in {
3169 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3170 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3172 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3173 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3174 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3175 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3176 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3178 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3180 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3182 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3186 // Reciprocal approximations. Note that these typically require refinement
3187 // in order to obtain suitable precision.
3188 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3189 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3190 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3191 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3193 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3196 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3197 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3198 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3199 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3201 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3205 let AddedComplexity = 1 in {
3206 def : Pat<(f32 (fsqrt FR32:$src)),
3207 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3208 def : Pat<(f32 (fsqrt (load addr:$src))),
3209 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3210 Requires<[HasAVX, OptForSize]>;
3211 def : Pat<(f64 (fsqrt FR64:$src)),
3212 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3213 def : Pat<(f64 (fsqrt (load addr:$src))),
3214 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3215 Requires<[HasAVX, OptForSize]>;
3217 def : Pat<(f32 (X86frsqrt FR32:$src)),
3218 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3219 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3220 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3221 Requires<[HasAVX, OptForSize]>;
3223 def : Pat<(f32 (X86frcp FR32:$src)),
3224 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3225 def : Pat<(f32 (X86frcp (load addr:$src))),
3226 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3227 Requires<[HasAVX, OptForSize]>;
3230 let Predicates = [HasAVX], AddedComplexity = 1 in {
3231 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3232 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3233 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3234 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3236 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3237 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3239 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3240 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3241 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3242 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3244 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3245 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3247 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3248 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3249 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3250 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3252 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3253 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3255 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3256 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3257 (VRCPSSr (f32 (IMPLICIT_DEF)),
3258 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3260 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3261 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3265 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3267 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3268 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3269 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3271 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3272 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3274 // Reciprocal approximations. Note that these typically require refinement
3275 // in order to obtain suitable precision.
3276 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3278 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3279 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3281 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3283 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3284 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3286 // There is no f64 version of the reciprocal approximation instructions.
3288 //===----------------------------------------------------------------------===//
3289 // SSE 1 & 2 - Non-temporal stores
3290 //===----------------------------------------------------------------------===//
3292 let AddedComplexity = 400 in { // Prefer non-temporal versions
3293 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3294 (ins f128mem:$dst, VR128:$src),
3295 "movntps\t{$src, $dst|$dst, $src}",
3296 [(alignednontemporalstore (v4f32 VR128:$src),
3298 IIC_SSE_MOVNT>, VEX;
3299 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3300 (ins f128mem:$dst, VR128:$src),
3301 "movntpd\t{$src, $dst|$dst, $src}",
3302 [(alignednontemporalstore (v2f64 VR128:$src),
3304 IIC_SSE_MOVNT>, VEX;
3306 let ExeDomain = SSEPackedInt in
3307 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3308 (ins f128mem:$dst, VR128:$src),
3309 "movntdq\t{$src, $dst|$dst, $src}",
3310 [(alignednontemporalstore (v2i64 VR128:$src),
3312 IIC_SSE_MOVNT>, VEX;
3314 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3315 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3317 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3318 (ins f256mem:$dst, VR256:$src),
3319 "movntps\t{$src, $dst|$dst, $src}",
3320 [(alignednontemporalstore (v8f32 VR256:$src),
3322 IIC_SSE_MOVNT>, VEX;
3323 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3324 (ins f256mem:$dst, VR256:$src),
3325 "movntpd\t{$src, $dst|$dst, $src}",
3326 [(alignednontemporalstore (v4f64 VR256:$src),
3328 IIC_SSE_MOVNT>, VEX;
3329 let ExeDomain = SSEPackedInt in
3330 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3331 (ins f256mem:$dst, VR256:$src),
3332 "movntdq\t{$src, $dst|$dst, $src}",
3333 [(alignednontemporalstore (v4i64 VR256:$src),
3335 IIC_SSE_MOVNT>, VEX;
3338 let AddedComplexity = 400 in { // Prefer non-temporal versions
3339 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3340 "movntps\t{$src, $dst|$dst, $src}",
3341 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3343 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3344 "movntpd\t{$src, $dst|$dst, $src}",
3345 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3348 let ExeDomain = SSEPackedInt in
3349 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3350 "movntdq\t{$src, $dst|$dst, $src}",
3351 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3354 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3355 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3357 // There is no AVX form for instructions below this point
3358 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3359 "movnti{l}\t{$src, $dst|$dst, $src}",
3360 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3362 TB, Requires<[HasSSE2]>;
3363 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3364 "movnti{q}\t{$src, $dst|$dst, $src}",
3365 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3367 TB, Requires<[HasSSE2]>;
3370 //===----------------------------------------------------------------------===//
3371 // SSE 1 & 2 - Prefetch and memory fence
3372 //===----------------------------------------------------------------------===//
3374 // Prefetch intrinsic.
3375 let Predicates = [HasSSE1] in {
3376 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3377 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3378 IIC_SSE_PREFETCH>, TB;
3379 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3380 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3381 IIC_SSE_PREFETCH>, TB;
3382 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3383 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3384 IIC_SSE_PREFETCH>, TB;
3385 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3386 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3387 IIC_SSE_PREFETCH>, TB;
3391 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3392 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3393 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3395 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3396 // was introduced with SSE2, it's backward compatible.
3397 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3399 // Load, store, and memory fence
3400 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3401 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3402 TB, Requires<[HasSSE1]>;
3403 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3404 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3405 TB, Requires<[HasSSE2]>;
3406 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3407 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3408 TB, Requires<[HasSSE2]>;
3410 def : Pat<(X86SFence), (SFENCE)>;
3411 def : Pat<(X86LFence), (LFENCE)>;
3412 def : Pat<(X86MFence), (MFENCE)>;
3414 //===----------------------------------------------------------------------===//
3415 // SSE 1 & 2 - Load/Store XCSR register
3416 //===----------------------------------------------------------------------===//
3418 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3419 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3420 IIC_SSE_LDMXCSR>, VEX;
3421 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3422 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3423 IIC_SSE_STMXCSR>, VEX;
3425 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3426 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3428 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3429 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3432 //===---------------------------------------------------------------------===//
3433 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3434 //===---------------------------------------------------------------------===//
3436 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3438 let neverHasSideEffects = 1 in {
3439 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3440 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3442 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3443 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3446 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3447 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3449 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3450 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3454 let isCodeGenOnly = 1 in {
3455 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3456 "movdqa\t{$src, $dst|$dst, $src}", [],
3459 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3460 "movdqa\t{$src, $dst|$dst, $src}", [],
3463 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3464 "movdqu\t{$src, $dst|$dst, $src}", [],
3467 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3468 "movdqu\t{$src, $dst|$dst, $src}", [],
3473 let canFoldAsLoad = 1, mayLoad = 1 in {
3474 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3475 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3477 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3478 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3480 let Predicates = [HasAVX] in {
3481 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3482 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3484 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3485 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3490 let mayStore = 1 in {
3491 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3492 (ins i128mem:$dst, VR128:$src),
3493 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3495 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3496 (ins i256mem:$dst, VR256:$src),
3497 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3499 let Predicates = [HasAVX] in {
3500 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3501 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3503 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3504 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3509 let neverHasSideEffects = 1 in
3510 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3511 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3513 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3514 "movdqu\t{$src, $dst|$dst, $src}",
3515 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3518 let isCodeGenOnly = 1 in {
3519 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3520 "movdqa\t{$src, $dst|$dst, $src}", [],
3523 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3524 "movdqu\t{$src, $dst|$dst, $src}",
3525 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3528 let canFoldAsLoad = 1, mayLoad = 1 in {
3529 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3530 "movdqa\t{$src, $dst|$dst, $src}",
3531 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3533 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3534 "movdqu\t{$src, $dst|$dst, $src}",
3535 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3537 XS, Requires<[HasSSE2]>;
3540 let mayStore = 1 in {
3541 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3542 "movdqa\t{$src, $dst|$dst, $src}",
3543 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3545 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3546 "movdqu\t{$src, $dst|$dst, $src}",
3547 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3549 XS, Requires<[HasSSE2]>;
3552 // Intrinsic forms of MOVDQU load and store
3553 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3554 "vmovdqu\t{$src, $dst|$dst, $src}",
3555 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3557 XS, VEX, Requires<[HasAVX]>;
3559 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3560 "movdqu\t{$src, $dst|$dst, $src}",
3561 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3563 XS, Requires<[HasSSE2]>;
3565 } // ExeDomain = SSEPackedInt
3567 let Predicates = [HasAVX] in {
3568 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3569 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3572 //===---------------------------------------------------------------------===//
3573 // SSE2 - Packed Integer Arithmetic Instructions
3574 //===---------------------------------------------------------------------===//
3576 def SSE_PMADD : OpndItins<
3577 IIC_SSE_PMADD, IIC_SSE_PMADD
3580 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3582 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3583 RegisterClass RC, PatFrag memop_frag,
3584 X86MemOperand x86memop,
3586 bit IsCommutable = 0,
3588 let isCommutable = IsCommutable in
3589 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3590 (ins RC:$src1, RC:$src2),
3592 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3593 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3594 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3595 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3596 (ins RC:$src1, x86memop:$src2),
3598 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3599 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3600 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3604 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3605 string OpcodeStr, SDNode OpNode,
3606 SDNode OpNode2, RegisterClass RC,
3607 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3608 ShiftOpndItins itins,
3610 // src2 is always 128-bit
3611 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3612 (ins RC:$src1, VR128:$src2),
3614 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3615 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3616 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3618 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3619 (ins RC:$src1, i128mem:$src2),
3621 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3622 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3623 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3624 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3625 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3626 (ins RC:$src1, i32i8imm:$src2),
3628 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3629 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3630 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3633 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3634 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3635 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3636 PatFrag memop_frag, X86MemOperand x86memop,
3638 bit IsCommutable = 0, bit Is2Addr = 1> {
3639 let isCommutable = IsCommutable in
3640 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3641 (ins RC:$src1, RC:$src2),
3643 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3644 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3645 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3646 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3647 (ins RC:$src1, x86memop:$src2),
3649 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3650 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3651 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3652 (bitconvert (memop_frag addr:$src2)))))]>;
3654 } // ExeDomain = SSEPackedInt
3656 // 128-bit Integer Arithmetic
3658 let Predicates = [HasAVX] in {
3659 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3660 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3662 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3663 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3664 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3665 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3666 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3667 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3668 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3669 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3670 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3671 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3672 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3673 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3674 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3675 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3676 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3677 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3678 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3679 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3683 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3684 VR128, memopv2i64, i128mem,
3685 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3686 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3687 VR128, memopv2i64, i128mem,
3688 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3689 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3690 VR128, memopv2i64, i128mem,
3691 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3692 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3693 VR128, memopv2i64, i128mem,
3694 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3695 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3696 VR128, memopv2i64, i128mem,
3697 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3698 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3699 VR128, memopv2i64, i128mem,
3700 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3701 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3702 VR128, memopv2i64, i128mem,
3703 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3704 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3705 VR128, memopv2i64, i128mem,
3706 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3707 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3708 VR128, memopv2i64, i128mem,
3709 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3710 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3711 VR128, memopv2i64, i128mem,
3712 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3713 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3714 VR128, memopv2i64, i128mem,
3715 SSE_PMADD, 1, 0>, VEX_4V;
3716 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3717 VR128, memopv2i64, i128mem,
3718 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3719 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3720 VR128, memopv2i64, i128mem,
3721 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3722 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3723 VR128, memopv2i64, i128mem,
3724 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3725 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3726 VR128, memopv2i64, i128mem,
3727 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3728 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3729 VR128, memopv2i64, i128mem,
3730 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3731 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3732 VR128, memopv2i64, i128mem,
3733 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3734 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3735 VR128, memopv2i64, i128mem,
3736 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3739 let Predicates = [HasAVX2] in {
3740 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3741 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3742 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3743 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3744 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3745 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3746 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3747 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3748 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3749 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3750 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3751 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3752 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3753 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3754 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3755 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3756 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3757 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3758 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3759 VR256, memopv4i64, i256mem,
3760 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3763 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3764 VR256, memopv4i64, i256mem,
3765 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3766 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3767 VR256, memopv4i64, i256mem,
3768 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3769 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3770 VR256, memopv4i64, i256mem,
3771 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3772 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3773 VR256, memopv4i64, i256mem,
3774 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3775 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3776 VR256, memopv4i64, i256mem,
3777 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3778 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3779 VR256, memopv4i64, i256mem,
3780 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3781 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3782 VR256, memopv4i64, i256mem,
3783 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3784 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3785 VR256, memopv4i64, i256mem,
3786 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3787 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3788 VR256, memopv4i64, i256mem,
3789 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3790 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3791 VR256, memopv4i64, i256mem,
3792 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3793 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3794 VR256, memopv4i64, i256mem,
3795 SSE_PMADD, 1, 0>, VEX_4V;
3796 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3797 VR256, memopv4i64, i256mem,
3798 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3799 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3800 VR256, memopv4i64, i256mem,
3801 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3802 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3803 VR256, memopv4i64, i256mem,
3804 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3805 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3806 VR256, memopv4i64, i256mem,
3807 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3808 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3809 VR256, memopv4i64, i256mem,
3810 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3811 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3812 VR256, memopv4i64, i256mem,
3813 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3814 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3815 VR256, memopv4i64, i256mem,
3816 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3819 let Constraints = "$src1 = $dst" in {
3820 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3821 i128mem, SSE_INTALU_ITINS_P, 1>;
3822 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3823 i128mem, SSE_INTALU_ITINS_P, 1>;
3824 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3825 i128mem, SSE_INTALU_ITINS_P, 1>;
3826 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3827 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3828 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3829 i128mem, SSE_INTMUL_ITINS_P, 1>;
3830 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3831 i128mem, SSE_INTALU_ITINS_P>;
3832 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3833 i128mem, SSE_INTALU_ITINS_P>;
3834 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3835 i128mem, SSE_INTALU_ITINS_P>;
3836 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3837 i128mem, SSE_INTALUQ_ITINS_P>;
3838 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3839 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3842 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3843 VR128, memopv2i64, i128mem,
3844 SSE_INTALU_ITINS_P>;
3845 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3846 VR128, memopv2i64, i128mem,
3847 SSE_INTALU_ITINS_P>;
3848 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3849 VR128, memopv2i64, i128mem,
3850 SSE_INTALU_ITINS_P>;
3851 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3852 VR128, memopv2i64, i128mem,
3853 SSE_INTALU_ITINS_P>;
3854 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3855 VR128, memopv2i64, i128mem,
3856 SSE_INTALU_ITINS_P, 1>;
3857 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3858 VR128, memopv2i64, i128mem,
3859 SSE_INTALU_ITINS_P, 1>;
3860 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3861 VR128, memopv2i64, i128mem,
3862 SSE_INTALU_ITINS_P, 1>;
3863 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3864 VR128, memopv2i64, i128mem,
3865 SSE_INTALU_ITINS_P, 1>;
3866 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3867 VR128, memopv2i64, i128mem,
3868 SSE_INTMUL_ITINS_P, 1>;
3869 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3870 VR128, memopv2i64, i128mem,
3871 SSE_INTMUL_ITINS_P, 1>;
3872 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3873 VR128, memopv2i64, i128mem,
3875 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3876 VR128, memopv2i64, i128mem,
3877 SSE_INTALU_ITINS_P, 1>;
3878 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3879 VR128, memopv2i64, i128mem,
3880 SSE_INTALU_ITINS_P, 1>;
3881 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3882 VR128, memopv2i64, i128mem,
3883 SSE_INTALU_ITINS_P, 1>;
3884 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3885 VR128, memopv2i64, i128mem,
3886 SSE_INTALU_ITINS_P, 1>;
3887 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3888 VR128, memopv2i64, i128mem,
3889 SSE_INTALU_ITINS_P, 1>;
3890 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3891 VR128, memopv2i64, i128mem,
3892 SSE_INTALU_ITINS_P, 1>;
3893 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3894 VR128, memopv2i64, i128mem,
3895 SSE_INTALU_ITINS_P, 1>;
3897 } // Constraints = "$src1 = $dst"
3899 //===---------------------------------------------------------------------===//
3900 // SSE2 - Packed Integer Logical Instructions
3901 //===---------------------------------------------------------------------===//
3903 let Predicates = [HasAVX] in {
3904 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3905 VR128, v8i16, v8i16, bc_v8i16,
3906 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3907 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3908 VR128, v4i32, v4i32, bc_v4i32,
3909 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3910 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3911 VR128, v2i64, v2i64, bc_v2i64,
3912 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3914 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3915 VR128, v8i16, v8i16, bc_v8i16,
3916 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3917 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3918 VR128, v4i32, v4i32, bc_v4i32,
3919 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3920 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3921 VR128, v2i64, v2i64, bc_v2i64,
3922 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3924 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3925 VR128, v8i16, v8i16, bc_v8i16,
3926 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3927 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3928 VR128, v4i32, v4i32, bc_v4i32,
3929 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3931 let ExeDomain = SSEPackedInt in {
3932 // 128-bit logical shifts.
3933 def VPSLLDQri : PDIi8<0x73, MRM7r,
3934 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3935 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3937 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3939 def VPSRLDQri : PDIi8<0x73, MRM3r,
3940 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3941 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3943 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3945 // PSRADQri doesn't exist in SSE[1-3].
3947 } // Predicates = [HasAVX]
3949 let Predicates = [HasAVX2] in {
3950 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3951 VR256, v16i16, v8i16, bc_v8i16,
3952 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3953 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3954 VR256, v8i32, v4i32, bc_v4i32,
3955 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3956 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3957 VR256, v4i64, v2i64, bc_v2i64,
3958 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3960 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3961 VR256, v16i16, v8i16, bc_v8i16,
3962 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3963 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3964 VR256, v8i32, v4i32, bc_v4i32,
3965 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3966 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3967 VR256, v4i64, v2i64, bc_v2i64,
3968 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3970 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3971 VR256, v16i16, v8i16, bc_v8i16,
3972 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3973 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3974 VR256, v8i32, v4i32, bc_v4i32,
3975 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3977 let ExeDomain = SSEPackedInt in {
3978 // 256-bit logical shifts.
3979 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3980 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3981 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3983 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3985 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3986 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3987 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3989 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3991 // PSRADQYri doesn't exist in SSE[1-3].
3993 } // Predicates = [HasAVX2]
3995 let Constraints = "$src1 = $dst" in {
3996 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3997 VR128, v8i16, v8i16, bc_v8i16,
3998 SSE_INTSHIFT_ITINS_P>;
3999 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4000 VR128, v4i32, v4i32, bc_v4i32,
4001 SSE_INTSHIFT_ITINS_P>;
4002 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4003 VR128, v2i64, v2i64, bc_v2i64,
4004 SSE_INTSHIFT_ITINS_P>;
4006 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4007 VR128, v8i16, v8i16, bc_v8i16,
4008 SSE_INTSHIFT_ITINS_P>;
4009 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4010 VR128, v4i32, v4i32, bc_v4i32,
4011 SSE_INTSHIFT_ITINS_P>;
4012 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4013 VR128, v2i64, v2i64, bc_v2i64,
4014 SSE_INTSHIFT_ITINS_P>;
4016 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4017 VR128, v8i16, v8i16, bc_v8i16,
4018 SSE_INTSHIFT_ITINS_P>;
4019 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4020 VR128, v4i32, v4i32, bc_v4i32,
4021 SSE_INTSHIFT_ITINS_P>;
4023 let ExeDomain = SSEPackedInt in {
4024 // 128-bit logical shifts.
4025 def PSLLDQri : PDIi8<0x73, MRM7r,
4026 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4027 "pslldq\t{$src2, $dst|$dst, $src2}",
4029 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4030 def PSRLDQri : PDIi8<0x73, MRM3r,
4031 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4032 "psrldq\t{$src2, $dst|$dst, $src2}",
4034 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4035 // PSRADQri doesn't exist in SSE[1-3].
4037 } // Constraints = "$src1 = $dst"
4039 let Predicates = [HasAVX] in {
4040 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4041 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4042 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4043 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4044 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4045 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4047 // Shift up / down and insert zero's.
4048 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4049 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4050 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4051 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4054 let Predicates = [HasAVX2] in {
4055 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4056 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4057 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4058 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4061 let Predicates = [HasSSE2] in {
4062 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4063 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4064 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4065 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4066 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4067 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4069 // Shift up / down and insert zero's.
4070 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4071 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4072 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4073 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4076 //===---------------------------------------------------------------------===//
4077 // SSE2 - Packed Integer Comparison Instructions
4078 //===---------------------------------------------------------------------===//
4080 let Predicates = [HasAVX] in {
4081 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4082 VR128, memopv2i64, i128mem,
4083 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4084 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4085 VR128, memopv2i64, i128mem,
4086 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4087 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4088 VR128, memopv2i64, i128mem,
4089 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4090 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4091 VR128, memopv2i64, i128mem,
4092 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4093 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4094 VR128, memopv2i64, i128mem,
4095 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4096 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4097 VR128, memopv2i64, i128mem,
4098 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4101 let Predicates = [HasAVX2] in {
4102 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4103 VR256, memopv4i64, i256mem,
4104 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4105 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4106 VR256, memopv4i64, i256mem,
4107 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4108 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4109 VR256, memopv4i64, i256mem,
4110 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4111 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4112 VR256, memopv4i64, i256mem,
4113 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4114 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4115 VR256, memopv4i64, i256mem,
4116 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4117 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4118 VR256, memopv4i64, i256mem,
4119 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4122 let Constraints = "$src1 = $dst" in {
4123 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4124 VR128, memopv2i64, i128mem,
4125 SSE_INTALU_ITINS_P, 1>;
4126 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4127 VR128, memopv2i64, i128mem,
4128 SSE_INTALU_ITINS_P, 1>;
4129 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4130 VR128, memopv2i64, i128mem,
4131 SSE_INTALU_ITINS_P, 1>;
4132 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4133 VR128, memopv2i64, i128mem,
4134 SSE_INTALU_ITINS_P>;
4135 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4136 VR128, memopv2i64, i128mem,
4137 SSE_INTALU_ITINS_P>;
4138 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4139 VR128, memopv2i64, i128mem,
4140 SSE_INTALU_ITINS_P>;
4141 } // Constraints = "$src1 = $dst"
4143 //===---------------------------------------------------------------------===//
4144 // SSE2 - Packed Integer Pack Instructions
4145 //===---------------------------------------------------------------------===//
4147 let Predicates = [HasAVX] in {
4148 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4149 VR128, memopv2i64, i128mem,
4150 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4151 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4152 VR128, memopv2i64, i128mem,
4153 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4154 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4155 VR128, memopv2i64, i128mem,
4156 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4159 let Predicates = [HasAVX2] in {
4160 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4161 VR256, memopv4i64, i256mem,
4162 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4163 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4164 VR256, memopv4i64, i256mem,
4165 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4166 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4167 VR256, memopv4i64, i256mem,
4168 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4171 let Constraints = "$src1 = $dst" in {
4172 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4173 VR128, memopv2i64, i128mem,
4174 SSE_INTALU_ITINS_P>;
4175 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4176 VR128, memopv2i64, i128mem,
4177 SSE_INTALU_ITINS_P>;
4178 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4179 VR128, memopv2i64, i128mem,
4180 SSE_INTALU_ITINS_P>;
4181 } // Constraints = "$src1 = $dst"
4183 //===---------------------------------------------------------------------===//
4184 // SSE2 - Packed Integer Shuffle Instructions
4185 //===---------------------------------------------------------------------===//
4187 let ExeDomain = SSEPackedInt in {
4188 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4189 def ri : Ii8<0x70, MRMSrcReg,
4190 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4191 !strconcat(OpcodeStr,
4192 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4193 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4195 def mi : Ii8<0x70, MRMSrcMem,
4196 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4197 !strconcat(OpcodeStr,
4198 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4200 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4205 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4206 def Yri : Ii8<0x70, MRMSrcReg,
4207 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4208 !strconcat(OpcodeStr,
4209 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4210 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4211 def Ymi : Ii8<0x70, MRMSrcMem,
4212 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4213 !strconcat(OpcodeStr,
4214 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4216 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4217 (i8 imm:$src2))))]>;
4219 } // ExeDomain = SSEPackedInt
4221 let Predicates = [HasAVX] in {
4222 let AddedComplexity = 5 in
4223 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4225 // SSE2 with ImmT == Imm8 and XS prefix.
4226 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4228 // SSE2 with ImmT == Imm8 and XD prefix.
4229 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4231 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4232 (VPSHUFDmi addr:$src1, imm:$imm)>;
4233 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4234 (VPSHUFDri VR128:$src1, imm:$imm)>;
4237 let Predicates = [HasAVX2] in {
4238 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4239 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4240 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4243 let Predicates = [HasSSE2] in {
4244 let AddedComplexity = 5 in
4245 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4247 // SSE2 with ImmT == Imm8 and XS prefix.
4248 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4250 // SSE2 with ImmT == Imm8 and XD prefix.
4251 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4253 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4254 (PSHUFDmi addr:$src1, imm:$imm)>;
4255 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4256 (PSHUFDri VR128:$src1, imm:$imm)>;
4259 //===---------------------------------------------------------------------===//
4260 // SSE2 - Packed Integer Unpack Instructions
4261 //===---------------------------------------------------------------------===//
4263 let ExeDomain = SSEPackedInt in {
4264 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4265 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4266 def rr : PDI<opc, MRMSrcReg,
4267 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4269 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4270 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4271 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4273 def rm : PDI<opc, MRMSrcMem,
4274 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4276 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4277 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4278 [(set VR128:$dst, (OpNode VR128:$src1,
4279 (bc_frag (memopv2i64
4284 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4285 SDNode OpNode, PatFrag bc_frag> {
4286 def Yrr : PDI<opc, MRMSrcReg,
4287 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4288 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4289 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4290 def Yrm : PDI<opc, MRMSrcMem,
4291 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4292 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4293 [(set VR256:$dst, (OpNode VR256:$src1,
4294 (bc_frag (memopv4i64 addr:$src2))))]>;
4297 let Predicates = [HasAVX] in {
4298 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4299 bc_v16i8, 0>, VEX_4V;
4300 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4301 bc_v8i16, 0>, VEX_4V;
4302 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4303 bc_v4i32, 0>, VEX_4V;
4304 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4305 bc_v2i64, 0>, VEX_4V;
4307 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4308 bc_v16i8, 0>, VEX_4V;
4309 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4310 bc_v8i16, 0>, VEX_4V;
4311 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4312 bc_v4i32, 0>, VEX_4V;
4313 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4314 bc_v2i64, 0>, VEX_4V;
4317 let Predicates = [HasAVX2] in {
4318 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4320 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4322 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4324 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4327 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4329 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4331 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4333 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4337 let Constraints = "$src1 = $dst" in {
4338 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4340 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4342 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4344 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4347 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4349 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4351 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4353 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4356 } // ExeDomain = SSEPackedInt
4358 // Patterns for using AVX1 instructions with integer vectors
4359 // Here to give AVX2 priority
4360 let Predicates = [HasAVX] in {
4361 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4362 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4363 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4364 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4365 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4366 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4367 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4368 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4370 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4371 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4372 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4373 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4374 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4375 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4376 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4377 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4380 //===---------------------------------------------------------------------===//
4381 // SSE2 - Packed Integer Extract and Insert
4382 //===---------------------------------------------------------------------===//
4384 let ExeDomain = SSEPackedInt in {
4385 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4386 def rri : Ii8<0xC4, MRMSrcReg,
4387 (outs VR128:$dst), (ins VR128:$src1,
4388 GR32:$src2, i32i8imm:$src3),
4390 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4391 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4393 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4394 def rmi : Ii8<0xC4, MRMSrcMem,
4395 (outs VR128:$dst), (ins VR128:$src1,
4396 i16mem:$src2, i32i8imm:$src3),
4398 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4399 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4401 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4402 imm:$src3))], IIC_SSE_PINSRW>;
4406 let Predicates = [HasAVX] in
4407 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4408 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4409 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4410 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4411 imm:$src2))]>, TB, OpSize, VEX;
4412 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4413 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4414 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4415 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4416 imm:$src2))], IIC_SSE_PEXTRW>;
4419 let Predicates = [HasAVX] in {
4420 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4421 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4422 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4423 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4424 []>, TB, OpSize, VEX_4V;
4427 let Constraints = "$src1 = $dst" in
4428 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4430 } // ExeDomain = SSEPackedInt
4432 //===---------------------------------------------------------------------===//
4433 // SSE2 - Packed Mask Creation
4434 //===---------------------------------------------------------------------===//
4436 let ExeDomain = SSEPackedInt in {
4438 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4439 "pmovmskb\t{$src, $dst|$dst, $src}",
4440 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4441 IIC_SSE_MOVMSK>, VEX;
4442 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4443 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4445 let Predicates = [HasAVX2] in {
4446 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4447 "pmovmskb\t{$src, $dst|$dst, $src}",
4448 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4449 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4450 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4453 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4454 "pmovmskb\t{$src, $dst|$dst, $src}",
4455 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4458 } // ExeDomain = SSEPackedInt
4460 //===---------------------------------------------------------------------===//
4461 // SSE2 - Conditional Store
4462 //===---------------------------------------------------------------------===//
4464 let ExeDomain = SSEPackedInt in {
4467 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4468 (ins VR128:$src, VR128:$mask),
4469 "maskmovdqu\t{$mask, $src|$src, $mask}",
4470 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4471 IIC_SSE_MASKMOV>, VEX;
4473 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4474 (ins VR128:$src, VR128:$mask),
4475 "maskmovdqu\t{$mask, $src|$src, $mask}",
4476 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4477 IIC_SSE_MASKMOV>, VEX;
4480 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4481 "maskmovdqu\t{$mask, $src|$src, $mask}",
4482 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4485 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4486 "maskmovdqu\t{$mask, $src|$src, $mask}",
4487 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4490 } // ExeDomain = SSEPackedInt
4492 //===---------------------------------------------------------------------===//
4493 // SSE2 - Move Doubleword
4494 //===---------------------------------------------------------------------===//
4496 //===---------------------------------------------------------------------===//
4497 // Move Int Doubleword to Packed Double Int
4499 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4500 "movd\t{$src, $dst|$dst, $src}",
4502 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4504 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4505 "movd\t{$src, $dst|$dst, $src}",
4507 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4510 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4511 "mov{d|q}\t{$src, $dst|$dst, $src}",
4513 (v2i64 (scalar_to_vector GR64:$src)))],
4514 IIC_SSE_MOVDQ>, VEX;
4515 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4516 "mov{d|q}\t{$src, $dst|$dst, $src}",
4517 [(set FR64:$dst, (bitconvert GR64:$src))],
4518 IIC_SSE_MOVDQ>, VEX;
4520 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4521 "movd\t{$src, $dst|$dst, $src}",
4523 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4524 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4525 "movd\t{$src, $dst|$dst, $src}",
4527 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4529 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4530 "mov{d|q}\t{$src, $dst|$dst, $src}",
4532 (v2i64 (scalar_to_vector GR64:$src)))],
4534 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4535 "mov{d|q}\t{$src, $dst|$dst, $src}",
4536 [(set FR64:$dst, (bitconvert GR64:$src))],
4539 //===---------------------------------------------------------------------===//
4540 // Move Int Doubleword to Single Scalar
4542 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4543 "movd\t{$src, $dst|$dst, $src}",
4544 [(set FR32:$dst, (bitconvert GR32:$src))],
4545 IIC_SSE_MOVDQ>, VEX;
4547 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4548 "movd\t{$src, $dst|$dst, $src}",
4549 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4552 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4553 "movd\t{$src, $dst|$dst, $src}",
4554 [(set FR32:$dst, (bitconvert GR32:$src))],
4557 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4558 "movd\t{$src, $dst|$dst, $src}",
4559 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4562 //===---------------------------------------------------------------------===//
4563 // Move Packed Doubleword Int to Packed Double Int
4565 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4566 "movd\t{$src, $dst|$dst, $src}",
4567 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4568 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4569 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4570 (ins i32mem:$dst, VR128:$src),
4571 "movd\t{$src, $dst|$dst, $src}",
4572 [(store (i32 (vector_extract (v4i32 VR128:$src),
4573 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4575 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4576 "movd\t{$src, $dst|$dst, $src}",
4577 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4578 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4579 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4580 "movd\t{$src, $dst|$dst, $src}",
4581 [(store (i32 (vector_extract (v4i32 VR128:$src),
4582 (iPTR 0))), addr:$dst)],
4585 //===---------------------------------------------------------------------===//
4586 // Move Packed Doubleword Int first element to Doubleword Int
4588 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4589 "mov{d|q}\t{$src, $dst|$dst, $src}",
4590 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4593 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4595 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4596 "mov{d|q}\t{$src, $dst|$dst, $src}",
4597 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4601 //===---------------------------------------------------------------------===//
4602 // Bitcast FR64 <-> GR64
4604 let Predicates = [HasAVX] in
4605 def VMOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4606 "vmovq\t{$src, $dst|$dst, $src}",
4607 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4609 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4610 "mov{d|q}\t{$src, $dst|$dst, $src}",
4611 [(set GR64:$dst, (bitconvert FR64:$src))],
4612 IIC_SSE_MOVDQ>, VEX;
4613 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4614 "movq\t{$src, $dst|$dst, $src}",
4615 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4616 IIC_SSE_MOVDQ>, VEX;
4618 def MOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4619 "movq\t{$src, $dst|$dst, $src}",
4620 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4622 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4623 "mov{d|q}\t{$src, $dst|$dst, $src}",
4624 [(set GR64:$dst, (bitconvert FR64:$src))],
4626 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4627 "movq\t{$src, $dst|$dst, $src}",
4628 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4631 //===---------------------------------------------------------------------===//
4632 // Move Scalar Single to Double Int
4634 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4635 "movd\t{$src, $dst|$dst, $src}",
4636 [(set GR32:$dst, (bitconvert FR32:$src))],
4637 IIC_SSE_MOVD_ToGP>, VEX;
4638 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4639 "movd\t{$src, $dst|$dst, $src}",
4640 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4641 IIC_SSE_MOVDQ>, VEX;
4642 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4643 "movd\t{$src, $dst|$dst, $src}",
4644 [(set GR32:$dst, (bitconvert FR32:$src))],
4646 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4647 "movd\t{$src, $dst|$dst, $src}",
4648 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4651 //===---------------------------------------------------------------------===//
4652 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4654 let AddedComplexity = 15 in {
4655 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4656 "movd\t{$src, $dst|$dst, $src}",
4657 [(set VR128:$dst, (v4i32 (X86vzmovl
4658 (v4i32 (scalar_to_vector GR32:$src)))))],
4659 IIC_SSE_MOVDQ>, VEX;
4660 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4661 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4662 [(set VR128:$dst, (v2i64 (X86vzmovl
4663 (v2i64 (scalar_to_vector GR64:$src)))))],
4667 let AddedComplexity = 15 in {
4668 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4669 "movd\t{$src, $dst|$dst, $src}",
4670 [(set VR128:$dst, (v4i32 (X86vzmovl
4671 (v4i32 (scalar_to_vector GR32:$src)))))],
4673 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4674 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4675 [(set VR128:$dst, (v2i64 (X86vzmovl
4676 (v2i64 (scalar_to_vector GR64:$src)))))],
4680 let AddedComplexity = 20 in {
4681 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4682 "movd\t{$src, $dst|$dst, $src}",
4684 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4685 (loadi32 addr:$src))))))],
4686 IIC_SSE_MOVDQ>, VEX;
4687 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4688 "movd\t{$src, $dst|$dst, $src}",
4690 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4691 (loadi32 addr:$src))))))],
4695 let Predicates = [HasAVX] in {
4696 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4697 let AddedComplexity = 20 in {
4698 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4699 (VMOVZDI2PDIrm addr:$src)>;
4700 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4701 (VMOVZDI2PDIrm addr:$src)>;
4703 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4704 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4705 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4706 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4707 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4708 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4709 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4712 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4713 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4714 (MOVZDI2PDIrm addr:$src)>;
4715 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4716 (MOVZDI2PDIrm addr:$src)>;
4719 // These are the correct encodings of the instructions so that we know how to
4720 // read correct assembly, even though we continue to emit the wrong ones for
4721 // compatibility with Darwin's buggy assembler.
4722 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4723 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4724 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4725 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4726 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4727 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4728 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4729 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4730 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4731 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4732 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4733 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4735 //===---------------------------------------------------------------------===//
4736 // SSE2 - Move Quadword
4737 //===---------------------------------------------------------------------===//
4739 //===---------------------------------------------------------------------===//
4740 // Move Quadword Int to Packed Quadword Int
4742 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4743 "vmovq\t{$src, $dst|$dst, $src}",
4745 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4746 VEX, Requires<[HasAVX]>;
4747 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4748 "movq\t{$src, $dst|$dst, $src}",
4750 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4752 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4754 //===---------------------------------------------------------------------===//
4755 // Move Packed Quadword Int to Quadword Int
4757 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4758 "movq\t{$src, $dst|$dst, $src}",
4759 [(store (i64 (vector_extract (v2i64 VR128:$src),
4760 (iPTR 0))), addr:$dst)],
4761 IIC_SSE_MOVDQ>, VEX;
4762 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4763 "movq\t{$src, $dst|$dst, $src}",
4764 [(store (i64 (vector_extract (v2i64 VR128:$src),
4765 (iPTR 0))), addr:$dst)],
4768 //===---------------------------------------------------------------------===//
4769 // Store / copy lower 64-bits of a XMM register.
4771 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4772 "movq\t{$src, $dst|$dst, $src}",
4773 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4774 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4775 "movq\t{$src, $dst|$dst, $src}",
4776 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4779 let AddedComplexity = 20 in
4780 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4781 "vmovq\t{$src, $dst|$dst, $src}",
4783 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4784 (loadi64 addr:$src))))))],
4786 XS, VEX, Requires<[HasAVX]>;
4788 let AddedComplexity = 20 in
4789 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4790 "movq\t{$src, $dst|$dst, $src}",
4792 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4793 (loadi64 addr:$src))))))],
4795 XS, Requires<[HasSSE2]>;
4797 let Predicates = [HasAVX], AddedComplexity = 20 in {
4798 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4799 (VMOVZQI2PQIrm addr:$src)>;
4800 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4801 (VMOVZQI2PQIrm addr:$src)>;
4802 def : Pat<(v2i64 (X86vzload addr:$src)),
4803 (VMOVZQI2PQIrm addr:$src)>;
4806 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4807 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4808 (MOVZQI2PQIrm addr:$src)>;
4809 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4810 (MOVZQI2PQIrm addr:$src)>;
4811 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4814 let Predicates = [HasAVX] in {
4815 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4816 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4817 def : Pat<(v4i64 (X86vzload addr:$src)),
4818 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4821 //===---------------------------------------------------------------------===//
4822 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4823 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4825 let AddedComplexity = 15 in
4826 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4827 "vmovq\t{$src, $dst|$dst, $src}",
4828 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4830 XS, VEX, Requires<[HasAVX]>;
4831 let AddedComplexity = 15 in
4832 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4833 "movq\t{$src, $dst|$dst, $src}",
4834 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4836 XS, Requires<[HasSSE2]>;
4838 let AddedComplexity = 20 in
4839 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4840 "vmovq\t{$src, $dst|$dst, $src}",
4841 [(set VR128:$dst, (v2i64 (X86vzmovl
4842 (loadv2i64 addr:$src))))],
4844 XS, VEX, Requires<[HasAVX]>;
4845 let AddedComplexity = 20 in {
4846 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4847 "movq\t{$src, $dst|$dst, $src}",
4848 [(set VR128:$dst, (v2i64 (X86vzmovl
4849 (loadv2i64 addr:$src))))],
4851 XS, Requires<[HasSSE2]>;
4854 let AddedComplexity = 20 in {
4855 let Predicates = [HasAVX] in {
4856 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4857 (VMOVZPQILo2PQIrm addr:$src)>;
4858 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4859 (VMOVZPQILo2PQIrr VR128:$src)>;
4861 let Predicates = [HasSSE2] in {
4862 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4863 (MOVZPQILo2PQIrm addr:$src)>;
4864 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4865 (MOVZPQILo2PQIrr VR128:$src)>;
4869 // Instructions to match in the assembler
4870 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4871 "movq\t{$src, $dst|$dst, $src}", [],
4872 IIC_SSE_MOVDQ>, VEX, VEX_W;
4873 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4874 "movq\t{$src, $dst|$dst, $src}", [],
4875 IIC_SSE_MOVDQ>, VEX, VEX_W;
4876 // Recognize "movd" with GR64 destination, but encode as a "movq"
4877 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4878 "movd\t{$src, $dst|$dst, $src}", [],
4879 IIC_SSE_MOVDQ>, VEX, VEX_W;
4881 // Instructions for the disassembler
4882 // xr = XMM register
4885 let Predicates = [HasAVX] in
4886 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4887 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4888 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4889 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4891 //===---------------------------------------------------------------------===//
4892 // SSE3 - Conversion Instructions
4893 //===---------------------------------------------------------------------===//
4895 // Convert Packed Double FP to Packed DW Integers
4896 let Predicates = [HasAVX] in {
4897 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4898 // register, but the same isn't true when using memory operands instead.
4899 // Provide other assembly rr and rm forms to address this explicitly.
4900 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4901 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4902 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4903 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4906 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4907 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4908 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4909 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4912 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4913 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX;
4914 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4915 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4918 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4919 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
4921 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4922 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
4925 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4926 (VCVTTPD2DQYrr VR256:$src)>;
4927 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4928 (VCVTTPD2DQYrm addr:$src)>;
4930 // Convert Packed DW Integers to Packed Double FP
4931 let Predicates = [HasAVX] in {
4932 def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4933 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4934 def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4935 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4936 def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4937 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4938 def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4939 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4942 def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4943 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
4945 def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4946 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
4949 // AVX 256-bit register conversion intrinsics
4950 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4951 (VCVTDQ2PDYrr VR128:$src)>;
4952 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
4953 (VCVTDQ2PDYrm addr:$src)>;
4955 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4956 (VCVTPD2DQYrr VR256:$src)>;
4957 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4958 (VCVTPD2DQYrm addr:$src)>;
4960 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4961 (VCVTDQ2PDYrr VR128:$src)>;
4962 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
4963 (VCVTDQ2PDYrm addr:$src)>;
4965 //===---------------------------------------------------------------------===//
4966 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4967 //===---------------------------------------------------------------------===//
4968 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4969 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4970 X86MemOperand x86memop> {
4971 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4972 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4973 [(set RC:$dst, (vt (OpNode RC:$src)))],
4975 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4976 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4977 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4981 let Predicates = [HasAVX] in {
4982 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4983 v4f32, VR128, memopv4f32, f128mem>, VEX;
4984 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4985 v4f32, VR128, memopv4f32, f128mem>, VEX;
4986 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4987 v8f32, VR256, memopv8f32, f256mem>, VEX;
4988 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4989 v8f32, VR256, memopv8f32, f256mem>, VEX;
4991 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4992 memopv4f32, f128mem>;
4993 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4994 memopv4f32, f128mem>;
4996 let Predicates = [HasAVX] in {
4997 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4998 (VMOVSHDUPrr VR128:$src)>;
4999 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5000 (VMOVSHDUPrm addr:$src)>;
5001 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5002 (VMOVSLDUPrr VR128:$src)>;
5003 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5004 (VMOVSLDUPrm addr:$src)>;
5005 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5006 (VMOVSHDUPYrr VR256:$src)>;
5007 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
5008 (VMOVSHDUPYrm addr:$src)>;
5009 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5010 (VMOVSLDUPYrr VR256:$src)>;
5011 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
5012 (VMOVSLDUPYrm addr:$src)>;
5015 let Predicates = [HasSSE3] in {
5016 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5017 (MOVSHDUPrr VR128:$src)>;
5018 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5019 (MOVSHDUPrm addr:$src)>;
5020 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5021 (MOVSLDUPrr VR128:$src)>;
5022 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5023 (MOVSLDUPrm addr:$src)>;
5026 //===---------------------------------------------------------------------===//
5027 // SSE3 - Replicate Double FP - MOVDDUP
5028 //===---------------------------------------------------------------------===//
5030 multiclass sse3_replicate_dfp<string OpcodeStr> {
5031 let neverHasSideEffects = 1 in
5032 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5033 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5034 [], IIC_SSE_MOV_LH>;
5035 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5036 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5039 (scalar_to_vector (loadf64 addr:$src)))))],
5043 // FIXME: Merge with above classe when there're patterns for the ymm version
5044 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5045 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5046 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5047 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
5048 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5049 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5052 (scalar_to_vector (loadf64 addr:$src)))))]>;
5055 let Predicates = [HasAVX] in {
5056 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5057 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
5060 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5062 let Predicates = [HasAVX] in {
5063 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5064 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5065 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5066 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5067 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5068 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5069 def : Pat<(X86Movddup (bc_v2f64
5070 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5071 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5074 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
5075 (VMOVDDUPYrm addr:$src)>;
5076 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
5077 (VMOVDDUPYrm addr:$src)>;
5078 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5079 (VMOVDDUPYrm addr:$src)>;
5080 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5081 (VMOVDDUPYrr VR256:$src)>;
5084 let Predicates = [HasSSE3] in {
5085 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5086 (MOVDDUPrm addr:$src)>;
5087 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5088 (MOVDDUPrm addr:$src)>;
5089 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5090 (MOVDDUPrm addr:$src)>;
5091 def : Pat<(X86Movddup (bc_v2f64
5092 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5093 (MOVDDUPrm addr:$src)>;
5096 //===---------------------------------------------------------------------===//
5097 // SSE3 - Move Unaligned Integer
5098 //===---------------------------------------------------------------------===//
5100 let Predicates = [HasAVX] in {
5101 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5102 "vlddqu\t{$src, $dst|$dst, $src}",
5103 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5104 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5105 "vlddqu\t{$src, $dst|$dst, $src}",
5106 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5108 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5109 "lddqu\t{$src, $dst|$dst, $src}",
5110 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5113 //===---------------------------------------------------------------------===//
5114 // SSE3 - Arithmetic
5115 //===---------------------------------------------------------------------===//
5117 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5118 X86MemOperand x86memop, OpndItins itins,
5120 def rr : I<0xD0, MRMSrcReg,
5121 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5123 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5124 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5125 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5126 def rm : I<0xD0, MRMSrcMem,
5127 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5129 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5130 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5131 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5134 let Predicates = [HasAVX] in {
5135 let ExeDomain = SSEPackedSingle in {
5136 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5137 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5138 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5139 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5141 let ExeDomain = SSEPackedDouble in {
5142 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5143 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5144 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5145 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5148 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5149 let ExeDomain = SSEPackedSingle in
5150 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5151 f128mem, SSE_ALU_F32P>, TB, XD;
5152 let ExeDomain = SSEPackedDouble in
5153 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5154 f128mem, SSE_ALU_F64P>, TB, OpSize;
5157 //===---------------------------------------------------------------------===//
5158 // SSE3 Instructions
5159 //===---------------------------------------------------------------------===//
5162 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5163 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5164 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5166 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5167 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5168 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5170 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5172 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5173 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5174 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5175 IIC_SSE_HADDSUB_RM>;
5177 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5178 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5179 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5181 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5182 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5183 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5185 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5187 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5188 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5189 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5190 IIC_SSE_HADDSUB_RM>;
5193 let Predicates = [HasAVX] in {
5194 let ExeDomain = SSEPackedSingle in {
5195 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5196 X86fhadd, 0>, VEX_4V;
5197 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5198 X86fhsub, 0>, VEX_4V;
5199 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5200 X86fhadd, 0>, VEX_4V;
5201 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5202 X86fhsub, 0>, VEX_4V;
5204 let ExeDomain = SSEPackedDouble in {
5205 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5206 X86fhadd, 0>, VEX_4V;
5207 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5208 X86fhsub, 0>, VEX_4V;
5209 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5210 X86fhadd, 0>, VEX_4V;
5211 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5212 X86fhsub, 0>, VEX_4V;
5216 let Constraints = "$src1 = $dst" in {
5217 let ExeDomain = SSEPackedSingle in {
5218 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5219 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5221 let ExeDomain = SSEPackedDouble in {
5222 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5223 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5227 //===---------------------------------------------------------------------===//
5228 // SSSE3 - Packed Absolute Instructions
5229 //===---------------------------------------------------------------------===//
5232 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5233 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5234 Intrinsic IntId128> {
5235 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5237 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5238 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5241 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5243 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5246 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5250 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5251 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5252 Intrinsic IntId256> {
5253 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5255 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5256 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5259 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5261 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5264 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5267 let Predicates = [HasAVX] in {
5268 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5269 int_x86_ssse3_pabs_b_128>, VEX;
5270 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5271 int_x86_ssse3_pabs_w_128>, VEX;
5272 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5273 int_x86_ssse3_pabs_d_128>, VEX;
5276 let Predicates = [HasAVX2] in {
5277 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5278 int_x86_avx2_pabs_b>, VEX;
5279 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5280 int_x86_avx2_pabs_w>, VEX;
5281 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5282 int_x86_avx2_pabs_d>, VEX;
5285 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5286 int_x86_ssse3_pabs_b_128>;
5287 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5288 int_x86_ssse3_pabs_w_128>;
5289 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5290 int_x86_ssse3_pabs_d_128>;
5292 //===---------------------------------------------------------------------===//
5293 // SSSE3 - Packed Binary Operator Instructions
5294 //===---------------------------------------------------------------------===//
5296 def SSE_PHADDSUBD : OpndItins<
5297 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5299 def SSE_PHADDSUBSW : OpndItins<
5300 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5302 def SSE_PHADDSUBW : OpndItins<
5303 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5305 def SSE_PSHUFB : OpndItins<
5306 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5308 def SSE_PSIGN : OpndItins<
5309 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5311 def SSE_PMULHRSW : OpndItins<
5312 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5315 /// SS3I_binop_rm - Simple SSSE3 bin op
5316 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5317 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5318 X86MemOperand x86memop, OpndItins itins,
5320 let isCommutable = 1 in
5321 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5322 (ins RC:$src1, RC:$src2),
5324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5326 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5328 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5329 (ins RC:$src1, x86memop:$src2),
5331 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5332 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5334 (OpVT (OpNode RC:$src1,
5335 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5338 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5339 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5340 Intrinsic IntId128, OpndItins itins,
5342 let isCommutable = 1 in
5343 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5344 (ins VR128:$src1, VR128:$src2),
5346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5348 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5350 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5351 (ins VR128:$src1, i128mem:$src2),
5353 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5354 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5356 (IntId128 VR128:$src1,
5357 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5360 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5361 Intrinsic IntId256> {
5362 let isCommutable = 1 in
5363 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5364 (ins VR256:$src1, VR256:$src2),
5365 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5366 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5368 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5369 (ins VR256:$src1, i256mem:$src2),
5370 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5372 (IntId256 VR256:$src1,
5373 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5376 let ImmT = NoImm, Predicates = [HasAVX] in {
5377 let isCommutable = 0 in {
5378 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5379 memopv2i64, i128mem,
5380 SSE_PHADDSUBW, 0>, VEX_4V;
5381 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5382 memopv2i64, i128mem,
5383 SSE_PHADDSUBD, 0>, VEX_4V;
5384 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5385 memopv2i64, i128mem,
5386 SSE_PHADDSUBW, 0>, VEX_4V;
5387 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5388 memopv2i64, i128mem,
5389 SSE_PHADDSUBD, 0>, VEX_4V;
5390 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5391 memopv2i64, i128mem,
5392 SSE_PSIGN, 0>, VEX_4V;
5393 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5394 memopv2i64, i128mem,
5395 SSE_PSIGN, 0>, VEX_4V;
5396 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5397 memopv2i64, i128mem,
5398 SSE_PSIGN, 0>, VEX_4V;
5399 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5400 memopv2i64, i128mem,
5401 SSE_PSHUFB, 0>, VEX_4V;
5402 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5403 int_x86_ssse3_phadd_sw_128,
5404 SSE_PHADDSUBSW, 0>, VEX_4V;
5405 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5406 int_x86_ssse3_phsub_sw_128,
5407 SSE_PHADDSUBSW, 0>, VEX_4V;
5408 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5409 int_x86_ssse3_pmadd_ub_sw_128,
5410 SSE_PMADD, 0>, VEX_4V;
5412 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5413 int_x86_ssse3_pmul_hr_sw_128,
5414 SSE_PMULHRSW, 0>, VEX_4V;
5417 let ImmT = NoImm, Predicates = [HasAVX2] in {
5418 let isCommutable = 0 in {
5419 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5420 memopv4i64, i256mem,
5421 SSE_PHADDSUBW, 0>, VEX_4V;
5422 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5423 memopv4i64, i256mem,
5424 SSE_PHADDSUBW, 0>, VEX_4V;
5425 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5426 memopv4i64, i256mem,
5427 SSE_PHADDSUBW, 0>, VEX_4V;
5428 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5429 memopv4i64, i256mem,
5430 SSE_PHADDSUBW, 0>, VEX_4V;
5431 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5432 memopv4i64, i256mem,
5433 SSE_PHADDSUBW, 0>, VEX_4V;
5434 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5435 memopv4i64, i256mem,
5436 SSE_PHADDSUBW, 0>, VEX_4V;
5437 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5438 memopv4i64, i256mem,
5439 SSE_PHADDSUBW, 0>, VEX_4V;
5440 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5441 memopv4i64, i256mem,
5442 SSE_PHADDSUBW, 0>, VEX_4V;
5443 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5444 int_x86_avx2_phadd_sw>, VEX_4V;
5445 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5446 int_x86_avx2_phsub_sw>, VEX_4V;
5447 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5448 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5450 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5451 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5454 // None of these have i8 immediate fields.
5455 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5456 let isCommutable = 0 in {
5457 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5458 memopv2i64, i128mem, SSE_PHADDSUBW>;
5459 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5460 memopv2i64, i128mem, SSE_PHADDSUBD>;
5461 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5462 memopv2i64, i128mem, SSE_PHADDSUBW>;
5463 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5464 memopv2i64, i128mem, SSE_PHADDSUBD>;
5465 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5466 memopv2i64, i128mem, SSE_PSIGN>;
5467 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5468 memopv2i64, i128mem, SSE_PSIGN>;
5469 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5470 memopv2i64, i128mem, SSE_PSIGN>;
5471 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5472 memopv2i64, i128mem, SSE_PSHUFB>;
5473 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5474 int_x86_ssse3_phadd_sw_128,
5476 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5477 int_x86_ssse3_phsub_sw_128,
5479 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5480 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5482 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5483 int_x86_ssse3_pmul_hr_sw_128,
5487 //===---------------------------------------------------------------------===//
5488 // SSSE3 - Packed Align Instruction Patterns
5489 //===---------------------------------------------------------------------===//
5491 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5492 let neverHasSideEffects = 1 in {
5493 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5494 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5496 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5498 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5499 [], IIC_SSE_PALIGNR>, OpSize;
5501 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5502 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5504 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5506 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5507 [], IIC_SSE_PALIGNR>, OpSize;
5511 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5512 let neverHasSideEffects = 1 in {
5513 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5514 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5516 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5519 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5520 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5522 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5527 let Predicates = [HasAVX] in
5528 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5529 let Predicates = [HasAVX2] in
5530 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5531 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5532 defm PALIGN : ssse3_palign<"palignr">;
5534 let Predicates = [HasAVX2] in {
5535 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5536 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5537 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5538 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5539 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5540 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5541 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5542 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5545 let Predicates = [HasAVX] in {
5546 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5547 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5548 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5549 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5550 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5551 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5552 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5553 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5556 let Predicates = [HasSSSE3] in {
5557 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5558 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5559 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5560 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5561 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5562 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5563 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5564 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5567 //===---------------------------------------------------------------------===//
5568 // SSSE3 - Thread synchronization
5569 //===---------------------------------------------------------------------===//
5571 let usesCustomInserter = 1 in {
5572 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5573 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5574 Requires<[HasSSE3]>;
5575 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5576 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5577 Requires<[HasSSE3]>;
5580 let Uses = [EAX, ECX, EDX] in
5581 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5582 TB, Requires<[HasSSE3]>;
5583 let Uses = [ECX, EAX] in
5584 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", [], IIC_SSE_MWAIT>,
5585 TB, Requires<[HasSSE3]>;
5587 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5588 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5590 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5591 Requires<[In32BitMode]>;
5592 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5593 Requires<[In64BitMode]>;
5595 //===----------------------------------------------------------------------===//
5596 // SSE4.1 - Packed Move with Sign/Zero Extend
5597 //===----------------------------------------------------------------------===//
5599 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5600 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5601 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5602 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5604 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5605 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5607 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5611 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5613 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5614 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5615 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5617 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5618 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5619 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5622 let Predicates = [HasAVX] in {
5623 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5625 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5627 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5629 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5631 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5633 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5637 let Predicates = [HasAVX2] in {
5638 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5639 int_x86_avx2_pmovsxbw>, VEX;
5640 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5641 int_x86_avx2_pmovsxwd>, VEX;
5642 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5643 int_x86_avx2_pmovsxdq>, VEX;
5644 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5645 int_x86_avx2_pmovzxbw>, VEX;
5646 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5647 int_x86_avx2_pmovzxwd>, VEX;
5648 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5649 int_x86_avx2_pmovzxdq>, VEX;
5652 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5653 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5654 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5655 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5656 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5657 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5659 let Predicates = [HasAVX] in {
5660 // Common patterns involving scalar load.
5661 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5662 (VPMOVSXBWrm addr:$src)>;
5663 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5664 (VPMOVSXBWrm addr:$src)>;
5666 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5667 (VPMOVSXWDrm addr:$src)>;
5668 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5669 (VPMOVSXWDrm addr:$src)>;
5671 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5672 (VPMOVSXDQrm addr:$src)>;
5673 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5674 (VPMOVSXDQrm addr:$src)>;
5676 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5677 (VPMOVZXBWrm addr:$src)>;
5678 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5679 (VPMOVZXBWrm addr:$src)>;
5681 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5682 (VPMOVZXWDrm addr:$src)>;
5683 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5684 (VPMOVZXWDrm addr:$src)>;
5686 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5687 (VPMOVZXDQrm addr:$src)>;
5688 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5689 (VPMOVZXDQrm addr:$src)>;
5692 let Predicates = [HasSSE41] in {
5693 // Common patterns involving scalar load.
5694 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5695 (PMOVSXBWrm addr:$src)>;
5696 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5697 (PMOVSXBWrm addr:$src)>;
5699 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5700 (PMOVSXWDrm addr:$src)>;
5701 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5702 (PMOVSXWDrm addr:$src)>;
5704 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5705 (PMOVSXDQrm addr:$src)>;
5706 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5707 (PMOVSXDQrm addr:$src)>;
5709 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5710 (PMOVZXBWrm addr:$src)>;
5711 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5712 (PMOVZXBWrm addr:$src)>;
5714 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5715 (PMOVZXWDrm addr:$src)>;
5716 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5717 (PMOVZXWDrm addr:$src)>;
5719 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5720 (PMOVZXDQrm addr:$src)>;
5721 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5722 (PMOVZXDQrm addr:$src)>;
5725 let Predicates = [HasAVX2] in {
5726 let AddedComplexity = 15 in {
5727 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5728 (VPMOVZXDQYrr VR128:$src)>;
5729 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5730 (VPMOVZXWDYrr VR128:$src)>;
5733 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5734 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5737 let Predicates = [HasAVX] in {
5738 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5739 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5742 let Predicates = [HasSSE41] in {
5743 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5744 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5748 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5749 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5750 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5751 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5753 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5754 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5756 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5760 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5762 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5763 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5764 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5766 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5767 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5769 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5773 let Predicates = [HasAVX] in {
5774 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5776 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5778 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5780 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5784 let Predicates = [HasAVX2] in {
5785 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5786 int_x86_avx2_pmovsxbd>, VEX;
5787 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5788 int_x86_avx2_pmovsxwq>, VEX;
5789 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5790 int_x86_avx2_pmovzxbd>, VEX;
5791 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5792 int_x86_avx2_pmovzxwq>, VEX;
5795 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5796 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5797 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5798 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5800 let Predicates = [HasAVX] in {
5801 // Common patterns involving scalar load
5802 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5803 (VPMOVSXBDrm addr:$src)>;
5804 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5805 (VPMOVSXWQrm addr:$src)>;
5807 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5808 (VPMOVZXBDrm addr:$src)>;
5809 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5810 (VPMOVZXWQrm addr:$src)>;
5813 let Predicates = [HasSSE41] in {
5814 // Common patterns involving scalar load
5815 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5816 (PMOVSXBDrm addr:$src)>;
5817 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5818 (PMOVSXWQrm addr:$src)>;
5820 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5821 (PMOVZXBDrm addr:$src)>;
5822 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5823 (PMOVZXWQrm addr:$src)>;
5826 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5827 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5828 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5829 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5831 // Expecting a i16 load any extended to i32 value.
5832 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5833 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5834 [(set VR128:$dst, (IntId (bitconvert
5835 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5839 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5841 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5842 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5843 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5845 // Expecting a i16 load any extended to i32 value.
5846 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5848 [(set VR256:$dst, (IntId (bitconvert
5849 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5853 let Predicates = [HasAVX] in {
5854 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5856 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5859 let Predicates = [HasAVX2] in {
5860 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5861 int_x86_avx2_pmovsxbq>, VEX;
5862 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5863 int_x86_avx2_pmovzxbq>, VEX;
5865 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5866 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5868 let Predicates = [HasAVX] in {
5869 // Common patterns involving scalar load
5870 def : Pat<(int_x86_sse41_pmovsxbq
5871 (bitconvert (v4i32 (X86vzmovl
5872 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5873 (VPMOVSXBQrm addr:$src)>;
5875 def : Pat<(int_x86_sse41_pmovzxbq
5876 (bitconvert (v4i32 (X86vzmovl
5877 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5878 (VPMOVZXBQrm addr:$src)>;
5881 let Predicates = [HasSSE41] in {
5882 // Common patterns involving scalar load
5883 def : Pat<(int_x86_sse41_pmovsxbq
5884 (bitconvert (v4i32 (X86vzmovl
5885 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5886 (PMOVSXBQrm addr:$src)>;
5888 def : Pat<(int_x86_sse41_pmovzxbq
5889 (bitconvert (v4i32 (X86vzmovl
5890 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5891 (PMOVZXBQrm addr:$src)>;
5894 //===----------------------------------------------------------------------===//
5895 // SSE4.1 - Extract Instructions
5896 //===----------------------------------------------------------------------===//
5898 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5899 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5900 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5901 (ins VR128:$src1, i32i8imm:$src2),
5902 !strconcat(OpcodeStr,
5903 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5904 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5906 let neverHasSideEffects = 1, mayStore = 1 in
5907 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5908 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5909 !strconcat(OpcodeStr,
5910 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5913 // There's an AssertZext in the way of writing the store pattern
5914 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5917 let Predicates = [HasAVX] in {
5918 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5919 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5920 (ins VR128:$src1, i32i8imm:$src2),
5921 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5924 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5927 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5928 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5929 let neverHasSideEffects = 1, mayStore = 1 in
5930 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5931 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5932 !strconcat(OpcodeStr,
5933 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5936 // There's an AssertZext in the way of writing the store pattern
5937 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5940 let Predicates = [HasAVX] in
5941 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5943 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5946 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5947 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5948 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5949 (ins VR128:$src1, i32i8imm:$src2),
5950 !strconcat(OpcodeStr,
5951 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5953 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5954 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5955 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5956 !strconcat(OpcodeStr,
5957 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5958 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5959 addr:$dst)]>, OpSize;
5962 let Predicates = [HasAVX] in
5963 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5965 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5967 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5968 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5969 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5970 (ins VR128:$src1, i32i8imm:$src2),
5971 !strconcat(OpcodeStr,
5972 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5974 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5975 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5976 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5977 !strconcat(OpcodeStr,
5978 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5979 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5980 addr:$dst)]>, OpSize, REX_W;
5983 let Predicates = [HasAVX] in
5984 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5986 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5988 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5990 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5991 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5992 (ins VR128:$src1, i32i8imm:$src2),
5993 !strconcat(OpcodeStr,
5994 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5996 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5998 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5999 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6000 !strconcat(OpcodeStr,
6001 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6002 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6003 addr:$dst)]>, OpSize;
6006 let ExeDomain = SSEPackedSingle in {
6007 let Predicates = [HasAVX] in {
6008 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6009 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6010 (ins VR128:$src1, i32i8imm:$src2),
6011 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
6014 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
6017 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6018 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6021 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6023 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6026 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6027 Requires<[HasSSE41]>;
6029 //===----------------------------------------------------------------------===//
6030 // SSE4.1 - Insert Instructions
6031 //===----------------------------------------------------------------------===//
6033 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6034 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6035 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6037 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6039 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6041 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6042 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6043 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6045 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6047 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6049 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6050 imm:$src3))]>, OpSize;
6053 let Predicates = [HasAVX] in
6054 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6055 let Constraints = "$src1 = $dst" in
6056 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6058 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6059 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6060 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6062 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6064 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6066 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6068 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6069 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6071 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6073 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6075 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6076 imm:$src3)))]>, OpSize;
6079 let Predicates = [HasAVX] in
6080 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6081 let Constraints = "$src1 = $dst" in
6082 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6084 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6085 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6086 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6088 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6090 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6092 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6094 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6095 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6097 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6099 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6101 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6102 imm:$src3)))]>, OpSize;
6105 let Predicates = [HasAVX] in
6106 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6107 let Constraints = "$src1 = $dst" in
6108 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6110 // insertps has a few different modes, there's the first two here below which
6111 // are optimized inserts that won't zero arbitrary elements in the destination
6112 // vector. The next one matches the intrinsic and could zero arbitrary elements
6113 // in the target vector.
6114 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6115 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6116 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6118 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6120 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6122 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6124 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6125 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6127 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6129 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6131 (X86insrtps VR128:$src1,
6132 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6133 imm:$src3))]>, OpSize;
6136 let ExeDomain = SSEPackedSingle in {
6137 let Predicates = [HasAVX] in
6138 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6139 let Constraints = "$src1 = $dst" in
6140 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6143 //===----------------------------------------------------------------------===//
6144 // SSE4.1 - Round Instructions
6145 //===----------------------------------------------------------------------===//
6147 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6148 X86MemOperand x86memop, RegisterClass RC,
6149 PatFrag mem_frag32, PatFrag mem_frag64,
6150 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6151 let ExeDomain = SSEPackedSingle in {
6152 // Intrinsic operation, reg.
6153 // Vector intrinsic operation, reg
6154 def PSr : SS4AIi8<opcps, MRMSrcReg,
6155 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6156 !strconcat(OpcodeStr,
6157 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6158 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6161 // Vector intrinsic operation, mem
6162 def PSm : SS4AIi8<opcps, MRMSrcMem,
6163 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6164 !strconcat(OpcodeStr,
6165 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6167 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6169 } // ExeDomain = SSEPackedSingle
6171 let ExeDomain = SSEPackedDouble in {
6172 // Vector intrinsic operation, reg
6173 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6174 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6175 !strconcat(OpcodeStr,
6176 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6177 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6180 // Vector intrinsic operation, mem
6181 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6182 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6183 !strconcat(OpcodeStr,
6184 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6186 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6188 } // ExeDomain = SSEPackedDouble
6191 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6194 Intrinsic F64Int, bit Is2Addr = 1> {
6195 let ExeDomain = GenericDomain in {
6197 def SSr : SS4AIi8<opcss, MRMSrcReg,
6198 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6200 !strconcat(OpcodeStr,
6201 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6202 !strconcat(OpcodeStr,
6203 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6206 // Intrinsic operation, reg.
6207 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6208 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6210 !strconcat(OpcodeStr,
6211 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6212 !strconcat(OpcodeStr,
6213 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6214 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6217 // Intrinsic operation, mem.
6218 def SSm : SS4AIi8<opcss, MRMSrcMem,
6219 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6221 !strconcat(OpcodeStr,
6222 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6223 !strconcat(OpcodeStr,
6224 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6226 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6230 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6231 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6233 !strconcat(OpcodeStr,
6234 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6235 !strconcat(OpcodeStr,
6236 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6239 // Intrinsic operation, reg.
6240 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6241 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6243 !strconcat(OpcodeStr,
6244 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6245 !strconcat(OpcodeStr,
6246 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6247 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6250 // Intrinsic operation, mem.
6251 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6252 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6254 !strconcat(OpcodeStr,
6255 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6256 !strconcat(OpcodeStr,
6257 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6259 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6261 } // ExeDomain = GenericDomain
6264 // FP round - roundss, roundps, roundsd, roundpd
6265 let Predicates = [HasAVX] in {
6267 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6268 memopv4f32, memopv2f64,
6269 int_x86_sse41_round_ps,
6270 int_x86_sse41_round_pd>, VEX;
6271 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6272 memopv8f32, memopv4f64,
6273 int_x86_avx_round_ps_256,
6274 int_x86_avx_round_pd_256>, VEX;
6275 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6276 int_x86_sse41_round_ss,
6277 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6279 def : Pat<(ffloor FR32:$src),
6280 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6281 def : Pat<(f64 (ffloor FR64:$src)),
6282 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6283 def : Pat<(f32 (fnearbyint FR32:$src)),
6284 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6285 def : Pat<(f64 (fnearbyint FR64:$src)),
6286 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6287 def : Pat<(f32 (fceil FR32:$src)),
6288 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6289 def : Pat<(f64 (fceil FR64:$src)),
6290 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6291 def : Pat<(f32 (frint FR32:$src)),
6292 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6293 def : Pat<(f64 (frint FR64:$src)),
6294 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6295 def : Pat<(f32 (ftrunc FR32:$src)),
6296 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6297 def : Pat<(f64 (ftrunc FR64:$src)),
6298 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6301 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6302 memopv4f32, memopv2f64,
6303 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6304 let Constraints = "$src1 = $dst" in
6305 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6306 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6308 def : Pat<(ffloor FR32:$src),
6309 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6310 def : Pat<(f64 (ffloor FR64:$src)),
6311 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6312 def : Pat<(f32 (fnearbyint FR32:$src)),
6313 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6314 def : Pat<(f64 (fnearbyint FR64:$src)),
6315 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6316 def : Pat<(f32 (fceil FR32:$src)),
6317 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6318 def : Pat<(f64 (fceil FR64:$src)),
6319 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6320 def : Pat<(f32 (frint FR32:$src)),
6321 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6322 def : Pat<(f64 (frint FR64:$src)),
6323 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6324 def : Pat<(f32 (ftrunc FR32:$src)),
6325 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6326 def : Pat<(f64 (ftrunc FR64:$src)),
6327 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6329 //===----------------------------------------------------------------------===//
6330 // SSE4.1 - Packed Bit Test
6331 //===----------------------------------------------------------------------===//
6333 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6334 // the intel intrinsic that corresponds to this.
6335 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6336 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6337 "vptest\t{$src2, $src1|$src1, $src2}",
6338 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6340 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6341 "vptest\t{$src2, $src1|$src1, $src2}",
6342 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6345 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6346 "vptest\t{$src2, $src1|$src1, $src2}",
6347 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6349 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6350 "vptest\t{$src2, $src1|$src1, $src2}",
6351 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6355 let Defs = [EFLAGS] in {
6356 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6357 "ptest\t{$src2, $src1|$src1, $src2}",
6358 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6360 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6361 "ptest\t{$src2, $src1|$src1, $src2}",
6362 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6366 // The bit test instructions below are AVX only
6367 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6368 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6369 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6370 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6371 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6372 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6373 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6374 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6378 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6379 let ExeDomain = SSEPackedSingle in {
6380 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6381 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6383 let ExeDomain = SSEPackedDouble in {
6384 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6385 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6389 //===----------------------------------------------------------------------===//
6390 // SSE4.1 - Misc Instructions
6391 //===----------------------------------------------------------------------===//
6393 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6394 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6395 "popcnt{w}\t{$src, $dst|$dst, $src}",
6396 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6398 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6399 "popcnt{w}\t{$src, $dst|$dst, $src}",
6400 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6401 (implicit EFLAGS)]>, OpSize, XS;
6403 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6404 "popcnt{l}\t{$src, $dst|$dst, $src}",
6405 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6407 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6408 "popcnt{l}\t{$src, $dst|$dst, $src}",
6409 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6410 (implicit EFLAGS)]>, XS;
6412 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6413 "popcnt{q}\t{$src, $dst|$dst, $src}",
6414 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6416 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6417 "popcnt{q}\t{$src, $dst|$dst, $src}",
6418 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6419 (implicit EFLAGS)]>, XS;
6424 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6425 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6426 Intrinsic IntId128> {
6427 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6429 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6430 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6431 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6433 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6436 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6439 let Predicates = [HasAVX] in
6440 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6441 int_x86_sse41_phminposuw>, VEX;
6442 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6443 int_x86_sse41_phminposuw>;
6445 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6446 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6447 Intrinsic IntId128, bit Is2Addr = 1> {
6448 let isCommutable = 1 in
6449 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6450 (ins VR128:$src1, VR128:$src2),
6452 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6453 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6454 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6455 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6456 (ins VR128:$src1, i128mem:$src2),
6458 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6459 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6461 (IntId128 VR128:$src1,
6462 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6465 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6466 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6467 Intrinsic IntId256> {
6468 let isCommutable = 1 in
6469 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6470 (ins VR256:$src1, VR256:$src2),
6471 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6472 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6473 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6474 (ins VR256:$src1, i256mem:$src2),
6475 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6477 (IntId256 VR256:$src1,
6478 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6481 let Predicates = [HasAVX] in {
6482 let isCommutable = 0 in
6483 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6485 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6487 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6489 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6491 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6493 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6495 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6497 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6499 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6501 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6505 let Predicates = [HasAVX2] in {
6506 let isCommutable = 0 in
6507 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6508 int_x86_avx2_packusdw>, VEX_4V;
6509 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6510 int_x86_avx2_pmins_b>, VEX_4V;
6511 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6512 int_x86_avx2_pmins_d>, VEX_4V;
6513 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6514 int_x86_avx2_pminu_d>, VEX_4V;
6515 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6516 int_x86_avx2_pminu_w>, VEX_4V;
6517 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6518 int_x86_avx2_pmaxs_b>, VEX_4V;
6519 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6520 int_x86_avx2_pmaxs_d>, VEX_4V;
6521 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6522 int_x86_avx2_pmaxu_d>, VEX_4V;
6523 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6524 int_x86_avx2_pmaxu_w>, VEX_4V;
6525 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6526 int_x86_avx2_pmul_dq>, VEX_4V;
6529 let Constraints = "$src1 = $dst" in {
6530 let isCommutable = 0 in
6531 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6532 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6533 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6534 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6535 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6536 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6537 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6538 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6539 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6540 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6543 /// SS48I_binop_rm - Simple SSE41 binary operator.
6544 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6545 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6546 X86MemOperand x86memop, bit Is2Addr = 1> {
6547 let isCommutable = 1 in
6548 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6549 (ins RC:$src1, RC:$src2),
6551 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6552 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6553 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6554 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6555 (ins RC:$src1, x86memop:$src2),
6557 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6558 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6560 (OpVT (OpNode RC:$src1,
6561 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6564 let Predicates = [HasAVX] in {
6565 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6566 memopv2i64, i128mem, 0>, VEX_4V;
6567 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6568 memopv2i64, i128mem, 0>, VEX_4V;
6570 let Predicates = [HasAVX2] in {
6571 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6572 memopv4i64, i256mem, 0>, VEX_4V;
6573 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6574 memopv4i64, i256mem, 0>, VEX_4V;
6577 let Constraints = "$src1 = $dst" in {
6578 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6579 memopv2i64, i128mem>;
6580 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6581 memopv2i64, i128mem>;
6584 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6585 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6586 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6587 X86MemOperand x86memop, bit Is2Addr = 1> {
6588 let isCommutable = 1 in
6589 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6590 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6592 !strconcat(OpcodeStr,
6593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6594 !strconcat(OpcodeStr,
6595 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6596 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6598 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6599 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6601 !strconcat(OpcodeStr,
6602 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6603 !strconcat(OpcodeStr,
6604 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6607 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6611 let Predicates = [HasAVX] in {
6612 let isCommutable = 0 in {
6613 let ExeDomain = SSEPackedSingle in {
6614 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6615 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6616 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6617 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6619 let ExeDomain = SSEPackedDouble in {
6620 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6621 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6622 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6623 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6625 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6626 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6627 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6628 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6630 let ExeDomain = SSEPackedSingle in
6631 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6632 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6633 let ExeDomain = SSEPackedDouble in
6634 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6635 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6636 let ExeDomain = SSEPackedSingle in
6637 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6638 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6641 let Predicates = [HasAVX2] in {
6642 let isCommutable = 0 in {
6643 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6644 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6645 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6646 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6650 let Constraints = "$src1 = $dst" in {
6651 let isCommutable = 0 in {
6652 let ExeDomain = SSEPackedSingle in
6653 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6654 VR128, memopv4f32, i128mem>;
6655 let ExeDomain = SSEPackedDouble in
6656 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6657 VR128, memopv2f64, i128mem>;
6658 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6659 VR128, memopv2i64, i128mem>;
6660 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6661 VR128, memopv2i64, i128mem>;
6663 let ExeDomain = SSEPackedSingle in
6664 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6665 VR128, memopv4f32, i128mem>;
6666 let ExeDomain = SSEPackedDouble in
6667 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6668 VR128, memopv2f64, i128mem>;
6671 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6672 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6673 RegisterClass RC, X86MemOperand x86memop,
6674 PatFrag mem_frag, Intrinsic IntId> {
6675 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6676 (ins RC:$src1, RC:$src2, RC:$src3),
6677 !strconcat(OpcodeStr,
6678 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6679 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6680 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6682 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6683 (ins RC:$src1, x86memop:$src2, RC:$src3),
6684 !strconcat(OpcodeStr,
6685 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6687 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6689 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6692 let Predicates = [HasAVX] in {
6693 let ExeDomain = SSEPackedDouble in {
6694 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6695 memopv2f64, int_x86_sse41_blendvpd>;
6696 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6697 memopv4f64, int_x86_avx_blendv_pd_256>;
6698 } // ExeDomain = SSEPackedDouble
6699 let ExeDomain = SSEPackedSingle in {
6700 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6701 memopv4f32, int_x86_sse41_blendvps>;
6702 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6703 memopv8f32, int_x86_avx_blendv_ps_256>;
6704 } // ExeDomain = SSEPackedSingle
6705 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6706 memopv2i64, int_x86_sse41_pblendvb>;
6709 let Predicates = [HasAVX2] in {
6710 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6711 memopv4i64, int_x86_avx2_pblendvb>;
6714 let Predicates = [HasAVX] in {
6715 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6716 (v16i8 VR128:$src2))),
6717 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6718 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6719 (v4i32 VR128:$src2))),
6720 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6721 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6722 (v4f32 VR128:$src2))),
6723 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6724 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6725 (v2i64 VR128:$src2))),
6726 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6727 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6728 (v2f64 VR128:$src2))),
6729 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6730 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6731 (v8i32 VR256:$src2))),
6732 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6733 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6734 (v8f32 VR256:$src2))),
6735 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6736 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6737 (v4i64 VR256:$src2))),
6738 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6739 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6740 (v4f64 VR256:$src2))),
6741 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6743 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6745 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6746 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6748 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6750 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6752 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6753 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6755 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6756 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6758 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6761 let Predicates = [HasAVX2] in {
6762 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6763 (v32i8 VR256:$src2))),
6764 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6765 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6767 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6770 /// SS41I_ternary_int - SSE 4.1 ternary operator
6771 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6772 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6774 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6775 (ins VR128:$src1, VR128:$src2),
6776 !strconcat(OpcodeStr,
6777 "\t{$src2, $dst|$dst, $src2}"),
6778 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6781 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6782 (ins VR128:$src1, i128mem:$src2),
6783 !strconcat(OpcodeStr,
6784 "\t{$src2, $dst|$dst, $src2}"),
6787 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6791 let ExeDomain = SSEPackedDouble in
6792 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6793 int_x86_sse41_blendvpd>;
6794 let ExeDomain = SSEPackedSingle in
6795 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6796 int_x86_sse41_blendvps>;
6797 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6798 int_x86_sse41_pblendvb>;
6800 let Predicates = [HasSSE41] in {
6801 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6802 (v16i8 VR128:$src2))),
6803 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6804 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6805 (v4i32 VR128:$src2))),
6806 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6807 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6808 (v4f32 VR128:$src2))),
6809 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6810 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6811 (v2i64 VR128:$src2))),
6812 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6813 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6814 (v2f64 VR128:$src2))),
6815 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6817 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6819 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6820 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6822 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6823 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6825 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6829 let Predicates = [HasAVX] in
6830 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6831 "vmovntdqa\t{$src, $dst|$dst, $src}",
6832 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6834 let Predicates = [HasAVX2] in
6835 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6836 "vmovntdqa\t{$src, $dst|$dst, $src}",
6837 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6839 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6840 "movntdqa\t{$src, $dst|$dst, $src}",
6841 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6844 //===----------------------------------------------------------------------===//
6845 // SSE4.2 - Compare Instructions
6846 //===----------------------------------------------------------------------===//
6848 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6849 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6850 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6851 X86MemOperand x86memop, bit Is2Addr = 1> {
6852 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6853 (ins RC:$src1, RC:$src2),
6855 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6856 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6857 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6859 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6860 (ins RC:$src1, x86memop:$src2),
6862 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6863 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6865 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6868 let Predicates = [HasAVX] in
6869 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6870 memopv2i64, i128mem, 0>, VEX_4V;
6872 let Predicates = [HasAVX2] in
6873 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6874 memopv4i64, i256mem, 0>, VEX_4V;
6876 let Constraints = "$src1 = $dst" in
6877 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6878 memopv2i64, i128mem>;
6880 //===----------------------------------------------------------------------===//
6881 // SSE4.2 - String/text Processing Instructions
6882 //===----------------------------------------------------------------------===//
6884 // Packed Compare Implicit Length Strings, Return Mask
6885 multiclass pseudo_pcmpistrm<string asm> {
6886 def REG : PseudoI<(outs VR128:$dst),
6887 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6888 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6890 def MEM : PseudoI<(outs VR128:$dst),
6891 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6892 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6893 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6896 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6897 let AddedComplexity = 1 in
6898 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6899 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6902 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6903 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6904 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6905 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6907 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6908 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6909 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6912 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6913 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6914 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6915 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6917 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6918 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6919 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6922 // Packed Compare Explicit Length Strings, Return Mask
6923 multiclass pseudo_pcmpestrm<string asm> {
6924 def REG : PseudoI<(outs VR128:$dst),
6925 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6926 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6927 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6928 def MEM : PseudoI<(outs VR128:$dst),
6929 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6930 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6931 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6934 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6935 let AddedComplexity = 1 in
6936 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6937 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6940 let Predicates = [HasAVX],
6941 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6942 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6943 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6944 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6946 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6947 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6948 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6951 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6952 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6953 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6954 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6956 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6957 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6958 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6961 // Packed Compare Implicit Length Strings, Return Index
6962 let Defs = [ECX, EFLAGS] in {
6963 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6964 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6965 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6966 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6967 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6968 (implicit EFLAGS)]>, OpSize;
6969 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6970 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6971 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6972 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6973 (implicit EFLAGS)]>, OpSize;
6977 let Predicates = [HasAVX] in {
6978 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6980 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6982 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6984 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6986 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6988 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6992 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6993 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6994 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6995 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6996 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6997 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6999 // Packed Compare Explicit Length Strings, Return Index
7000 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
7001 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
7002 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7003 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7004 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7005 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
7006 (implicit EFLAGS)]>, OpSize;
7007 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7008 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7009 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7011 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
7012 (implicit EFLAGS)]>, OpSize;
7016 let Predicates = [HasAVX] in {
7017 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
7019 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
7021 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
7023 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
7025 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
7027 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
7031 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
7032 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
7033 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
7034 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
7035 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
7036 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
7038 //===----------------------------------------------------------------------===//
7039 // SSE4.2 - CRC Instructions
7040 //===----------------------------------------------------------------------===//
7042 // No CRC instructions have AVX equivalents
7044 // crc intrinsic instruction
7045 // This set of instructions are only rm, the only difference is the size
7047 let Constraints = "$src1 = $dst" in {
7048 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7049 (ins GR32:$src1, i8mem:$src2),
7050 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7052 (int_x86_sse42_crc32_32_8 GR32:$src1,
7053 (load addr:$src2)))]>;
7054 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7055 (ins GR32:$src1, GR8:$src2),
7056 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7058 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7059 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7060 (ins GR32:$src1, i16mem:$src2),
7061 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7063 (int_x86_sse42_crc32_32_16 GR32:$src1,
7064 (load addr:$src2)))]>,
7066 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7067 (ins GR32:$src1, GR16:$src2),
7068 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7070 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7072 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7073 (ins GR32:$src1, i32mem:$src2),
7074 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7076 (int_x86_sse42_crc32_32_32 GR32:$src1,
7077 (load addr:$src2)))]>;
7078 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7079 (ins GR32:$src1, GR32:$src2),
7080 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7082 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7083 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7084 (ins GR64:$src1, i8mem:$src2),
7085 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7087 (int_x86_sse42_crc32_64_8 GR64:$src1,
7088 (load addr:$src2)))]>,
7090 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7091 (ins GR64:$src1, GR8:$src2),
7092 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7094 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7096 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7097 (ins GR64:$src1, i64mem:$src2),
7098 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7100 (int_x86_sse42_crc32_64_64 GR64:$src1,
7101 (load addr:$src2)))]>,
7103 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7104 (ins GR64:$src1, GR64:$src2),
7105 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7107 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7111 //===----------------------------------------------------------------------===//
7112 // AES-NI Instructions
7113 //===----------------------------------------------------------------------===//
7115 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7116 Intrinsic IntId128, bit Is2Addr = 1> {
7117 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7118 (ins VR128:$src1, VR128:$src2),
7120 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7121 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7122 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7124 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7125 (ins VR128:$src1, i128mem:$src2),
7127 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7128 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7130 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7133 // Perform One Round of an AES Encryption/Decryption Flow
7134 let Predicates = [HasAVX, HasAES] in {
7135 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7136 int_x86_aesni_aesenc, 0>, VEX_4V;
7137 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7138 int_x86_aesni_aesenclast, 0>, VEX_4V;
7139 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7140 int_x86_aesni_aesdec, 0>, VEX_4V;
7141 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7142 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7145 let Constraints = "$src1 = $dst" in {
7146 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7147 int_x86_aesni_aesenc>;
7148 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7149 int_x86_aesni_aesenclast>;
7150 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7151 int_x86_aesni_aesdec>;
7152 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7153 int_x86_aesni_aesdeclast>;
7156 // Perform the AES InvMixColumn Transformation
7157 let Predicates = [HasAVX, HasAES] in {
7158 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7160 "vaesimc\t{$src1, $dst|$dst, $src1}",
7162 (int_x86_aesni_aesimc VR128:$src1))]>,
7164 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7165 (ins i128mem:$src1),
7166 "vaesimc\t{$src1, $dst|$dst, $src1}",
7167 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7170 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7172 "aesimc\t{$src1, $dst|$dst, $src1}",
7174 (int_x86_aesni_aesimc VR128:$src1))]>,
7176 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7177 (ins i128mem:$src1),
7178 "aesimc\t{$src1, $dst|$dst, $src1}",
7179 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7182 // AES Round Key Generation Assist
7183 let Predicates = [HasAVX, HasAES] in {
7184 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7185 (ins VR128:$src1, i8imm:$src2),
7186 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7188 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7190 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7191 (ins i128mem:$src1, i8imm:$src2),
7192 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7194 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7197 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7198 (ins VR128:$src1, i8imm:$src2),
7199 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7201 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7203 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7204 (ins i128mem:$src1, i8imm:$src2),
7205 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7207 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7210 //===----------------------------------------------------------------------===//
7211 // PCLMUL Instructions
7212 //===----------------------------------------------------------------------===//
7214 // AVX carry-less Multiplication instructions
7215 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7216 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7217 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7219 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7221 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7222 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7223 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7224 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7225 (memopv2i64 addr:$src2), imm:$src3))]>;
7227 // Carry-less Multiplication instructions
7228 let Constraints = "$src1 = $dst" in {
7229 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7230 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7231 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7233 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7235 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7236 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7237 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7238 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7239 (memopv2i64 addr:$src2), imm:$src3))]>;
7240 } // Constraints = "$src1 = $dst"
7243 multiclass pclmul_alias<string asm, int immop> {
7244 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7245 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7247 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7248 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7250 def : InstAlias<!strconcat("vpclmul", asm,
7251 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7252 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7254 def : InstAlias<!strconcat("vpclmul", asm,
7255 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7256 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7258 defm : pclmul_alias<"hqhq", 0x11>;
7259 defm : pclmul_alias<"hqlq", 0x01>;
7260 defm : pclmul_alias<"lqhq", 0x10>;
7261 defm : pclmul_alias<"lqlq", 0x00>;
7263 //===----------------------------------------------------------------------===//
7264 // SSE4A Instructions
7265 //===----------------------------------------------------------------------===//
7267 let Predicates = [HasSSE4A] in {
7269 let Constraints = "$src = $dst" in {
7270 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7271 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7272 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7273 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7274 imm:$idx))]>, TB, OpSize;
7275 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7276 (ins VR128:$src, VR128:$mask),
7277 "extrq\t{$mask, $src|$src, $mask}",
7278 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7279 VR128:$mask))]>, TB, OpSize;
7281 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7282 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7283 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7284 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7285 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7286 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7287 (ins VR128:$src, VR128:$mask),
7288 "insertq\t{$mask, $src|$src, $mask}",
7289 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7290 VR128:$mask))]>, XD;
7293 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7294 "movntss\t{$src, $dst|$dst, $src}",
7295 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7297 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7298 "movntsd\t{$src, $dst|$dst, $src}",
7299 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7302 //===----------------------------------------------------------------------===//
7304 //===----------------------------------------------------------------------===//
7306 //===----------------------------------------------------------------------===//
7307 // VBROADCAST - Load from memory and broadcast to all elements of the
7308 // destination operand
7310 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7311 X86MemOperand x86memop, Intrinsic Int> :
7312 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7313 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7314 [(set RC:$dst, (Int addr:$src))]>, VEX;
7316 // AVX2 adds register forms
7317 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7319 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7320 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7321 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7323 let ExeDomain = SSEPackedSingle in {
7324 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7325 int_x86_avx_vbroadcast_ss>;
7326 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7327 int_x86_avx_vbroadcast_ss_256>;
7329 let ExeDomain = SSEPackedDouble in
7330 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7331 int_x86_avx_vbroadcast_sd_256>;
7332 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7333 int_x86_avx_vbroadcastf128_pd_256>;
7335 let ExeDomain = SSEPackedSingle in {
7336 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7337 int_x86_avx2_vbroadcast_ss_ps>;
7338 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7339 int_x86_avx2_vbroadcast_ss_ps_256>;
7341 let ExeDomain = SSEPackedDouble in
7342 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7343 int_x86_avx2_vbroadcast_sd_pd_256>;
7345 let Predicates = [HasAVX2] in
7346 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7347 int_x86_avx2_vbroadcasti128>;
7349 let Predicates = [HasAVX] in
7350 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7351 (VBROADCASTF128 addr:$src)>;
7354 //===----------------------------------------------------------------------===//
7355 // VINSERTF128 - Insert packed floating-point values
7357 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7358 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7359 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7360 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7363 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7364 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7365 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7369 let Predicates = [HasAVX] in {
7370 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7372 (VINSERTF128rr VR256:$src1, VR128:$src2,
7373 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7374 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7376 (VINSERTF128rr VR256:$src1, VR128:$src2,
7377 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7378 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7380 (VINSERTF128rr VR256:$src1, VR128:$src2,
7381 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7382 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7384 (VINSERTF128rr VR256:$src1, VR128:$src2,
7385 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7386 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7388 (VINSERTF128rr VR256:$src1, VR128:$src2,
7389 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7390 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7392 (VINSERTF128rr VR256:$src1, VR128:$src2,
7393 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7395 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7397 (VINSERTF128rm VR256:$src1, addr:$src2,
7398 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7399 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7401 (VINSERTF128rm VR256:$src1, addr:$src2,
7402 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7403 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7405 (VINSERTF128rm VR256:$src1, addr:$src2,
7406 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7409 //===----------------------------------------------------------------------===//
7410 // VEXTRACTF128 - Extract packed floating-point values
7412 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7413 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7414 (ins VR256:$src1, i8imm:$src2),
7415 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7418 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7419 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7420 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7424 // Extract and store.
7425 let Predicates = [HasAVX] in {
7426 def : Pat<(alignedstore (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2), addr:$dst),
7427 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7428 def : Pat<(alignedstore (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2), addr:$dst),
7429 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7430 def : Pat<(alignedstore (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2), addr:$dst),
7431 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7433 def : Pat<(int_x86_sse_storeu_ps addr:$dst, (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2)),
7434 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7435 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2)),
7436 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7437 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, (bc_v16i8 (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2))),
7438 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7442 let Predicates = [HasAVX] in {
7443 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7444 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7445 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7446 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7447 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7448 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7450 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7451 (v4f32 (VEXTRACTF128rr
7452 (v8f32 VR256:$src1),
7453 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7454 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7455 (v2f64 (VEXTRACTF128rr
7456 (v4f64 VR256:$src1),
7457 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7458 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7459 (v2i64 (VEXTRACTF128rr
7460 (v4i64 VR256:$src1),
7461 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7462 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7463 (v4i32 (VEXTRACTF128rr
7464 (v8i32 VR256:$src1),
7465 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7466 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7467 (v8i16 (VEXTRACTF128rr
7468 (v16i16 VR256:$src1),
7469 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7470 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7471 (v16i8 (VEXTRACTF128rr
7472 (v32i8 VR256:$src1),
7473 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7476 //===----------------------------------------------------------------------===//
7477 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7479 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7480 Intrinsic IntLd, Intrinsic IntLd256,
7481 Intrinsic IntSt, Intrinsic IntSt256> {
7482 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7483 (ins VR128:$src1, f128mem:$src2),
7484 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7485 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7487 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7488 (ins VR256:$src1, f256mem:$src2),
7489 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7490 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7492 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7493 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7494 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7495 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7496 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7497 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7498 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7499 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7502 let ExeDomain = SSEPackedSingle in
7503 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7504 int_x86_avx_maskload_ps,
7505 int_x86_avx_maskload_ps_256,
7506 int_x86_avx_maskstore_ps,
7507 int_x86_avx_maskstore_ps_256>;
7508 let ExeDomain = SSEPackedDouble in
7509 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7510 int_x86_avx_maskload_pd,
7511 int_x86_avx_maskload_pd_256,
7512 int_x86_avx_maskstore_pd,
7513 int_x86_avx_maskstore_pd_256>;
7515 //===----------------------------------------------------------------------===//
7516 // VPERMIL - Permute Single and Double Floating-Point Values
7518 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7519 RegisterClass RC, X86MemOperand x86memop_f,
7520 X86MemOperand x86memop_i, PatFrag i_frag,
7521 Intrinsic IntVar, ValueType vt> {
7522 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7523 (ins RC:$src1, RC:$src2),
7524 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7525 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7526 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7527 (ins RC:$src1, x86memop_i:$src2),
7528 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7529 [(set RC:$dst, (IntVar RC:$src1,
7530 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7532 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7533 (ins RC:$src1, i8imm:$src2),
7534 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7535 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7536 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7537 (ins x86memop_f:$src1, i8imm:$src2),
7538 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7540 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7543 let ExeDomain = SSEPackedSingle in {
7544 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7545 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7546 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7547 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7549 let ExeDomain = SSEPackedDouble in {
7550 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7551 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7552 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7553 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7556 let Predicates = [HasAVX] in {
7557 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7558 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7559 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7560 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7561 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7563 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7564 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7565 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7567 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7568 (VPERMILPDri VR128:$src1, imm:$imm)>;
7569 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7570 (VPERMILPDmi addr:$src1, imm:$imm)>;
7573 //===----------------------------------------------------------------------===//
7574 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7576 let ExeDomain = SSEPackedSingle in {
7577 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7578 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7579 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7580 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7581 (i8 imm:$src3))))]>, VEX_4V;
7582 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7583 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7584 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7585 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7586 (i8 imm:$src3)))]>, VEX_4V;
7589 let Predicates = [HasAVX] in {
7590 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7591 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7592 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7593 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7594 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7595 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7596 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7597 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7598 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7599 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7601 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7602 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7603 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7604 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7605 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7606 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7607 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7608 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7609 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7610 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7611 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7612 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7613 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7614 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7615 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7616 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7617 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7618 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7621 //===----------------------------------------------------------------------===//
7622 // VZERO - Zero YMM registers
7624 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7625 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7626 // Zero All YMM registers
7627 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7628 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7630 // Zero Upper bits of YMM registers
7631 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7632 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7635 //===----------------------------------------------------------------------===//
7636 // Half precision conversion instructions
7637 //===----------------------------------------------------------------------===//
7638 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7639 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7640 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7641 [(set RC:$dst, (Int VR128:$src))]>,
7643 let neverHasSideEffects = 1, mayLoad = 1 in
7644 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7645 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7648 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7649 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7650 (ins RC:$src1, i32i8imm:$src2),
7651 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7652 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7654 let neverHasSideEffects = 1, mayStore = 1 in
7655 def mr : Ii8<0x1D, MRMDestMem, (outs),
7656 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7657 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7661 let Predicates = [HasAVX, HasF16C] in {
7662 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7663 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7664 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7665 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7668 //===----------------------------------------------------------------------===//
7669 // AVX2 Instructions
7670 //===----------------------------------------------------------------------===//
7672 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7673 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7674 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7675 X86MemOperand x86memop> {
7676 let isCommutable = 1 in
7677 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7678 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7679 !strconcat(OpcodeStr,
7680 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7681 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7683 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7684 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7685 !strconcat(OpcodeStr,
7686 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7689 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7693 let isCommutable = 0 in {
7694 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7695 VR128, memopv2i64, i128mem>;
7696 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7697 VR256, memopv4i64, i256mem>;
7700 //===----------------------------------------------------------------------===//
7701 // VPBROADCAST - Load from memory and broadcast to all elements of the
7702 // destination operand
7704 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7705 X86MemOperand x86memop, PatFrag ld_frag,
7706 Intrinsic Int128, Intrinsic Int256> {
7707 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7708 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7709 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7710 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7711 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7713 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7714 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7715 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7716 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7717 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7718 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7720 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7723 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7724 int_x86_avx2_pbroadcastb_128,
7725 int_x86_avx2_pbroadcastb_256>;
7726 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7727 int_x86_avx2_pbroadcastw_128,
7728 int_x86_avx2_pbroadcastw_256>;
7729 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7730 int_x86_avx2_pbroadcastd_128,
7731 int_x86_avx2_pbroadcastd_256>;
7732 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7733 int_x86_avx2_pbroadcastq_128,
7734 int_x86_avx2_pbroadcastq_256>;
7736 let Predicates = [HasAVX2] in {
7737 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7738 (VPBROADCASTBrm addr:$src)>;
7739 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7740 (VPBROADCASTBYrm addr:$src)>;
7741 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7742 (VPBROADCASTWrm addr:$src)>;
7743 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7744 (VPBROADCASTWYrm addr:$src)>;
7745 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7746 (VPBROADCASTDrm addr:$src)>;
7747 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7748 (VPBROADCASTDYrm addr:$src)>;
7749 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7750 (VPBROADCASTQrm addr:$src)>;
7751 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7752 (VPBROADCASTQYrm addr:$src)>;
7754 // Provide fallback in case the load node that is used in the patterns above
7755 // is used by additional users, which prevents the pattern selection.
7756 let AddedComplexity = 20 in {
7757 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7759 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7760 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7762 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7763 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7765 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd))>;
7767 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7769 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7770 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7772 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7773 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7775 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd))>;
7779 // AVX1 broadcast patterns
7780 let Predicates = [HasAVX] in {
7781 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7782 (VBROADCASTSSYrm addr:$src)>;
7783 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7784 (VBROADCASTSDrm addr:$src)>;
7785 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7786 (VBROADCASTSSYrm addr:$src)>;
7787 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7788 (VBROADCASTSDrm addr:$src)>;
7789 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7790 (VBROADCASTSSrm addr:$src)>;
7791 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7792 (VBROADCASTSSrm addr:$src)>;
7794 // Provide fallback in case the load node that is used in the patterns above
7795 // is used by additional users, which prevents the pattern selection.
7796 let AddedComplexity = 20 in {
7797 // 128bit broadcasts:
7798 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7800 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0)>;
7801 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7802 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7804 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0),
7807 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss),
7809 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7810 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7812 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd), 0),
7815 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd),
7818 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7820 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0)>;
7821 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7822 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7824 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0),
7827 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss),
7829 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7830 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7832 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd), 0),
7835 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd),
7840 //===----------------------------------------------------------------------===//
7841 // VPERM - Permute instructions
7844 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7846 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7847 (ins VR256:$src1, VR256:$src2),
7848 !strconcat(OpcodeStr,
7849 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7851 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7852 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7853 (ins VR256:$src1, i256mem:$src2),
7854 !strconcat(OpcodeStr,
7855 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7857 (OpVT (X86VPermv VR256:$src1,
7858 (bitconvert (mem_frag addr:$src2)))))]>,
7862 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7863 let ExeDomain = SSEPackedSingle in
7864 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7866 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7868 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7869 (ins VR256:$src1, i8imm:$src2),
7870 !strconcat(OpcodeStr,
7871 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7873 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7874 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7875 (ins i256mem:$src1, i8imm:$src2),
7876 !strconcat(OpcodeStr,
7877 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7879 (OpVT (X86VPermi (mem_frag addr:$src1),
7880 (i8 imm:$src2))))]>, VEX;
7883 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7884 let ExeDomain = SSEPackedDouble in
7885 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7887 //===----------------------------------------------------------------------===//
7888 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7890 let AddedComplexity = 1 in {
7891 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7892 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7893 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7894 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7895 (i8 imm:$src3))))]>, VEX_4V;
7896 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7897 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7898 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7899 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7900 (i8 imm:$src3)))]>, VEX_4V;
7903 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7904 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7905 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7906 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7907 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7908 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7909 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7911 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7913 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7914 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7915 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7916 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7917 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7919 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7923 //===----------------------------------------------------------------------===//
7924 // VINSERTI128 - Insert packed integer values
7926 let neverHasSideEffects = 1 in {
7927 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7928 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7929 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7932 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7933 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7934 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7938 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7939 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7941 (VINSERTI128rr VR256:$src1, VR128:$src2,
7942 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7943 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7945 (VINSERTI128rr VR256:$src1, VR128:$src2,
7946 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7947 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7949 (VINSERTI128rr VR256:$src1, VR128:$src2,
7950 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7951 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7953 (VINSERTI128rr VR256:$src1, VR128:$src2,
7954 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7957 //===----------------------------------------------------------------------===//
7958 // VEXTRACTI128 - Extract packed integer values
7960 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7961 (ins VR256:$src1, i8imm:$src2),
7962 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7964 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7966 let neverHasSideEffects = 1, mayStore = 1 in
7967 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7968 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7969 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7971 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7972 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7973 (v2i64 (VEXTRACTI128rr
7974 (v4i64 VR256:$src1),
7975 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7976 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7977 (v4i32 (VEXTRACTI128rr
7978 (v8i32 VR256:$src1),
7979 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7980 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7981 (v8i16 (VEXTRACTI128rr
7982 (v16i16 VR256:$src1),
7983 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7984 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7985 (v16i8 (VEXTRACTI128rr
7986 (v32i8 VR256:$src1),
7987 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7990 //===----------------------------------------------------------------------===//
7991 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7993 multiclass avx2_pmovmask<string OpcodeStr,
7994 Intrinsic IntLd128, Intrinsic IntLd256,
7995 Intrinsic IntSt128, Intrinsic IntSt256> {
7996 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7997 (ins VR128:$src1, i128mem:$src2),
7998 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7999 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8000 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8001 (ins VR256:$src1, i256mem:$src2),
8002 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8003 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
8004 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8005 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8006 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8007 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8008 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8009 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8010 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8011 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
8014 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8015 int_x86_avx2_maskload_d,
8016 int_x86_avx2_maskload_d_256,
8017 int_x86_avx2_maskstore_d,
8018 int_x86_avx2_maskstore_d_256>;
8019 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8020 int_x86_avx2_maskload_q,
8021 int_x86_avx2_maskload_q_256,
8022 int_x86_avx2_maskstore_q,
8023 int_x86_avx2_maskstore_q_256>, VEX_W;
8026 //===----------------------------------------------------------------------===//
8027 // Variable Bit Shifts
8029 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8030 ValueType vt128, ValueType vt256> {
8031 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8032 (ins VR128:$src1, VR128:$src2),
8033 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8035 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8037 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8038 (ins VR128:$src1, i128mem:$src2),
8039 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8041 (vt128 (OpNode VR128:$src1,
8042 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8044 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8045 (ins VR256:$src1, VR256:$src2),
8046 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8048 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8050 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8051 (ins VR256:$src1, i256mem:$src2),
8052 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8054 (vt256 (OpNode VR256:$src1,
8055 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8059 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8060 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8061 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8062 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8063 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;