1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 def SSE_BIT_ITINS_P : OpndItins<
124 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
127 let Sched = WriteVecALU in {
128 def SSE_INTALU_ITINS_P : OpndItins<
129 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
132 def SSE_INTALUQ_ITINS_P : OpndItins<
133 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
137 let Sched = WriteVecIMul in
138 def SSE_INTMUL_ITINS_P : OpndItins<
139 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
142 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
143 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
146 def SSE_MOVA_ITINS : OpndItins<
147 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
150 def SSE_MOVU_ITINS : OpndItins<
151 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
154 def SSE_DPPD_ITINS : OpndItins<
155 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
158 def SSE_DPPS_ITINS : OpndItins<
159 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
162 def DEFAULT_ITINS : OpndItins<
163 IIC_ALU_NONMEM, IIC_ALU_MEM
166 def SSE_EXTRACT_ITINS : OpndItins<
167 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
170 def SSE_INSERT_ITINS : OpndItins<
171 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
174 def SSE_MPSADBW_ITINS : OpndItins<
175 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
178 def SSE_PMULLD_ITINS : OpndItins<
179 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
182 //===----------------------------------------------------------------------===//
183 // SSE 1 & 2 Instructions Classes
184 //===----------------------------------------------------------------------===//
186 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
187 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
188 RegisterClass RC, X86MemOperand x86memop,
191 let isCommutable = 1 in {
192 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
194 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
196 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
197 Sched<[itins.Sched]>;
199 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
201 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
203 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
204 Sched<[itins.Sched.Folded, ReadAfterLd]>;
207 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
208 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
209 string asm, string SSEVer, string FPSizeStr,
210 Operand memopr, ComplexPattern mem_cpat,
213 let isCodeGenOnly = 1 in {
214 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
216 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 [(set RC:$dst, (!cast<Intrinsic>(
219 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
220 RC:$src1, RC:$src2))], itins.rr>,
221 Sched<[itins.Sched]>;
222 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
224 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
225 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
226 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
227 SSEVer, "_", OpcodeStr, FPSizeStr))
228 RC:$src1, mem_cpat:$src2))], itins.rm>,
229 Sched<[itins.Sched.Folded, ReadAfterLd]>;
233 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
234 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
235 RegisterClass RC, ValueType vt,
236 X86MemOperand x86memop, PatFrag mem_frag,
237 Domain d, OpndItins itins, bit Is2Addr = 1> {
238 let isCommutable = 1 in
239 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
241 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
242 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
243 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
244 Sched<[itins.Sched]>;
246 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
252 Sched<[itins.Sched.Folded, ReadAfterLd]>;
255 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
256 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
257 string OpcodeStr, X86MemOperand x86memop,
258 list<dag> pat_rr, list<dag> pat_rm,
260 let isCommutable = 1, hasSideEffects = 0 in
261 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
263 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
264 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
265 pat_rr, NoItinerary, d>,
266 Sched<[WriteVecLogic]>;
267 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
269 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 pat_rm, NoItinerary, d>,
272 Sched<[WriteVecLogicLd, ReadAfterLd]>;
275 //===----------------------------------------------------------------------===//
276 // Non-instruction patterns
277 //===----------------------------------------------------------------------===//
279 // A vector extract of the first f32/f64 position is a subregister copy
280 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
281 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
282 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
283 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
285 // A 128-bit subvector extract from the first 256-bit vector position
286 // is a subregister copy that needs no instruction.
287 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
288 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
289 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
290 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
292 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
293 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
294 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
295 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
297 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
298 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
299 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
300 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
302 // A 128-bit subvector insert to the first 256-bit vector position
303 // is a subregister copy that needs no instruction.
304 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
305 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
306 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
307 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
308 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
309 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
310 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
311 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
312 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
313 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
314 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
315 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
316 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
319 // Implicitly promote a 32-bit scalar to a vector.
320 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
321 (COPY_TO_REGCLASS FR32:$src, VR128)>;
322 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
323 (COPY_TO_REGCLASS FR32:$src, VR128)>;
324 // Implicitly promote a 64-bit scalar to a vector.
325 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
326 (COPY_TO_REGCLASS FR64:$src, VR128)>;
327 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
328 (COPY_TO_REGCLASS FR64:$src, VR128)>;
330 // Bitcasts between 128-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasSSE2] in {
333 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
334 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
335 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
336 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
337 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
338 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
339 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
340 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
341 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
342 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
343 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
344 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
345 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
346 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
347 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
348 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
349 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
350 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
351 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
352 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
353 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
354 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
355 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
356 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
357 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
358 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
359 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
360 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
361 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
362 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
365 // Bitcasts between 256-bit vector types. Return the original type since
366 // no instruction is needed for the conversion
367 let Predicates = [HasAVX] in {
368 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
369 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
370 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
371 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
372 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
373 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
374 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
375 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
376 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
377 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
378 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
379 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
380 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
381 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
382 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
383 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
384 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
385 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
386 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
387 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
388 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
389 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
390 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
391 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
392 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
393 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
394 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
395 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
396 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
397 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
400 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
401 // This is expanded by ExpandPostRAPseudos.
402 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
403 isPseudo = 1, SchedRW = [WriteZero] in {
404 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
405 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
406 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
407 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
410 //===----------------------------------------------------------------------===//
411 // AVX & SSE - Zero/One Vectors
412 //===----------------------------------------------------------------------===//
414 // Alias instruction that maps zero vector to pxor / xorp* for sse.
415 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
416 // swizzled by ExecutionDepsFix to pxor.
417 // We set canFoldAsLoad because this can be converted to a constant-pool
418 // load of an all-zeros value if folding it would be beneficial.
419 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
420 isPseudo = 1, SchedRW = [WriteZero] in {
421 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
422 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
425 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
426 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
427 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
428 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
429 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
432 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
433 // and doesn't need it because on sandy bridge the register is set to zero
434 // at the rename stage without using any execution unit, so SET0PSY
435 // and SET0PDY can be used for vector int instructions without penalty
436 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
437 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
438 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
439 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
442 let Predicates = [HasAVX] in
443 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
445 let Predicates = [HasAVX2] in {
446 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
447 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
448 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
449 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
452 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
453 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
454 let Predicates = [HasAVX1Only] in {
455 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
456 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
457 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
459 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
460 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
461 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
463 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
464 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
465 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
467 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
468 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
469 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-ones value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
478 let Predicates = [HasAVX2] in
479 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
480 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
484 //===----------------------------------------------------------------------===//
485 // SSE 1 & 2 - Move FP Scalar Instructions
487 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
488 // register copies because it's a partial register update; Register-to-register
489 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
490 // that the insert be implementable in terms of a copy, and just mentioned, we
491 // don't use movss/movsd for copies.
492 //===----------------------------------------------------------------------===//
494 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
495 X86MemOperand x86memop, string base_opc,
497 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
498 (ins VR128:$src1, RC:$src2),
499 !strconcat(base_opc, asm_opr),
500 [(set VR128:$dst, (vt (OpNode VR128:$src1,
501 (scalar_to_vector RC:$src2))))],
502 IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
504 // For the disassembler
505 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
506 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
507 (ins VR128:$src1, RC:$src2),
508 !strconcat(base_opc, asm_opr),
509 [], IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
512 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
513 X86MemOperand x86memop, string OpcodeStr> {
515 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
516 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
519 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
520 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
521 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
522 VEX, VEX_LIG, Sched<[WriteStore]>;
524 let Constraints = "$src1 = $dst" in {
525 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
526 "\t{$src2, $dst|$dst, $src2}">;
529 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
530 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
531 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
535 // Loading from memory automatically zeroing upper bits.
536 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
537 PatFrag mem_pat, string OpcodeStr> {
538 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
539 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
540 [(set RC:$dst, (mem_pat addr:$src))],
541 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
542 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
543 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
544 [(set RC:$dst, (mem_pat addr:$src))],
545 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
548 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
549 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
551 let canFoldAsLoad = 1, isReMaterializable = 1 in {
552 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
554 let AddedComplexity = 20 in
555 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
559 let Predicates = [UseAVX] in {
560 let AddedComplexity = 15 in {
561 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
562 // MOVS{S,D} to the lower bits.
563 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
564 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
565 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
566 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
567 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
568 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
569 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
570 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
572 // Move low f32 and clear high bits.
573 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
574 (SUBREG_TO_REG (i32 0),
575 (VMOVSSrr (v4f32 (V_SET0)),
576 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
577 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
578 (SUBREG_TO_REG (i32 0),
579 (VMOVSSrr (v4i32 (V_SET0)),
580 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
583 let AddedComplexity = 20 in {
584 // MOVSSrm zeros the high parts of the register; represent this
585 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
586 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
587 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
588 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
589 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
590 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
591 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
593 // MOVSDrm zeros the high parts of the register; represent this
594 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
595 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
596 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
597 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
598 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
599 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
600 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
601 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
602 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
603 def : Pat<(v2f64 (X86vzload addr:$src)),
604 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
606 // Represent the same patterns above but in the form they appear for
608 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
609 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
610 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
611 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
612 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
613 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
614 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
615 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
616 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
618 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
619 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
620 (SUBREG_TO_REG (i32 0),
621 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
623 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
624 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
625 (SUBREG_TO_REG (i64 0),
626 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
628 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
629 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
630 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
632 // Move low f64 and clear high bits.
633 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
634 (SUBREG_TO_REG (i32 0),
635 (VMOVSDrr (v2f64 (V_SET0)),
636 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
638 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
639 (SUBREG_TO_REG (i32 0),
640 (VMOVSDrr (v2i64 (V_SET0)),
641 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
643 // Extract and store.
644 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
646 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
647 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
649 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
651 // Shuffle with VMOVSS
652 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
653 (VMOVSSrr (v4i32 VR128:$src1),
654 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
655 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
656 (VMOVSSrr (v4f32 VR128:$src1),
657 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
660 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
661 (SUBREG_TO_REG (i32 0),
662 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
663 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
665 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
666 (SUBREG_TO_REG (i32 0),
667 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
668 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
671 // Shuffle with VMOVSD
672 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
674 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
675 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
676 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
678 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
679 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
682 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
683 (SUBREG_TO_REG (i32 0),
684 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
685 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
687 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
688 (SUBREG_TO_REG (i32 0),
689 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
690 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
694 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
695 // is during lowering, where it's not possible to recognize the fold cause
696 // it has two uses through a bitcast. One use disappears at isel time and the
697 // fold opportunity reappears.
698 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
699 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
700 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
701 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
702 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
703 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
704 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
705 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 let Predicates = [UseSSE1] in {
709 let AddedComplexity = 15 in {
710 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
711 // MOVSS to the lower bits.
712 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
713 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
714 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
715 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
716 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
717 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
720 let AddedComplexity = 20 in {
721 // MOVSSrm already zeros the high parts of the register.
722 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
723 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
724 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
726 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
727 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
730 // Extract and store.
731 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
733 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
735 // Shuffle with MOVSS
736 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
737 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
738 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
739 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
742 let Predicates = [UseSSE2] in {
743 let AddedComplexity = 15 in {
744 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
745 // MOVSD to the lower bits.
746 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
747 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
750 let AddedComplexity = 20 in {
751 // MOVSDrm already zeros the high parts of the register.
752 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
753 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
754 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
755 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
756 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
757 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
758 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
759 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
760 def : Pat<(v2f64 (X86vzload addr:$src)),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 // Extract and store.
765 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
767 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
769 // Shuffle with MOVSD
770 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
771 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
772 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
773 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
774 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
775 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
776 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
777 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
779 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
780 // is during lowering, where it's not possible to recognize the fold cause
781 // it has two uses through a bitcast. One use disappears at isel time and the
782 // fold opportunity reappears.
783 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
784 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
785 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
786 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
788 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
789 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
790 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 //===----------------------------------------------------------------------===//
794 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
795 //===----------------------------------------------------------------------===//
797 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
798 X86MemOperand x86memop, PatFrag ld_frag,
799 string asm, Domain d,
801 bit IsReMaterializable = 1> {
802 let neverHasSideEffects = 1 in
803 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
804 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
806 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
807 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
808 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
809 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
813 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
814 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
816 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
817 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
819 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
820 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
822 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
823 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
826 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
827 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
829 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
830 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
832 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
833 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
835 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
836 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
838 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
839 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
841 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
842 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
844 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
845 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
847 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
848 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
851 let SchedRW = [WriteStore] in {
852 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
853 "movaps\t{$src, $dst|$dst, $src}",
854 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
855 IIC_SSE_MOVA_P_MR>, VEX;
856 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
857 "movapd\t{$src, $dst|$dst, $src}",
858 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
859 IIC_SSE_MOVA_P_MR>, VEX;
860 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
861 "movups\t{$src, $dst|$dst, $src}",
862 [(store (v4f32 VR128:$src), addr:$dst)],
863 IIC_SSE_MOVU_P_MR>, VEX;
864 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
865 "movupd\t{$src, $dst|$dst, $src}",
866 [(store (v2f64 VR128:$src), addr:$dst)],
867 IIC_SSE_MOVU_P_MR>, VEX;
868 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
869 "movaps\t{$src, $dst|$dst, $src}",
870 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
871 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
872 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
873 "movapd\t{$src, $dst|$dst, $src}",
874 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
875 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
876 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
877 "movups\t{$src, $dst|$dst, $src}",
878 [(store (v8f32 VR256:$src), addr:$dst)],
879 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
880 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
881 "movupd\t{$src, $dst|$dst, $src}",
882 [(store (v4f64 VR256:$src), addr:$dst)],
883 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
887 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
888 SchedRW = [WriteMove] in {
889 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
891 "movaps\t{$src, $dst|$dst, $src}", [],
892 IIC_SSE_MOVA_P_RR>, VEX;
893 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
895 "movapd\t{$src, $dst|$dst, $src}", [],
896 IIC_SSE_MOVA_P_RR>, VEX;
897 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
899 "movups\t{$src, $dst|$dst, $src}", [],
900 IIC_SSE_MOVU_P_RR>, VEX;
901 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
903 "movupd\t{$src, $dst|$dst, $src}", [],
904 IIC_SSE_MOVU_P_RR>, VEX;
905 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
907 "movaps\t{$src, $dst|$dst, $src}", [],
908 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
909 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
911 "movapd\t{$src, $dst|$dst, $src}", [],
912 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
913 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
915 "movups\t{$src, $dst|$dst, $src}", [],
916 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
917 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
919 "movupd\t{$src, $dst|$dst, $src}", [],
920 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
923 let Predicates = [HasAVX] in {
924 def : Pat<(v8i32 (X86vzmovl
925 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
926 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
927 def : Pat<(v4i64 (X86vzmovl
928 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
929 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
930 def : Pat<(v8f32 (X86vzmovl
931 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
932 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
933 def : Pat<(v4f64 (X86vzmovl
934 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
935 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
939 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
940 (VMOVUPSYmr addr:$dst, VR256:$src)>;
941 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
942 (VMOVUPDYmr addr:$dst, VR256:$src)>;
944 let SchedRW = [WriteStore] in {
945 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
946 "movaps\t{$src, $dst|$dst, $src}",
947 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
949 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
950 "movapd\t{$src, $dst|$dst, $src}",
951 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
953 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
954 "movups\t{$src, $dst|$dst, $src}",
955 [(store (v4f32 VR128:$src), addr:$dst)],
957 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
958 "movupd\t{$src, $dst|$dst, $src}",
959 [(store (v2f64 VR128:$src), addr:$dst)],
964 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
965 SchedRW = [WriteMove] in {
966 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
967 "movaps\t{$src, $dst|$dst, $src}", [],
969 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
970 "movapd\t{$src, $dst|$dst, $src}", [],
972 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
973 "movups\t{$src, $dst|$dst, $src}", [],
975 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
976 "movupd\t{$src, $dst|$dst, $src}", [],
980 let Predicates = [HasAVX] in {
981 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
982 (VMOVUPSmr addr:$dst, VR128:$src)>;
983 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
984 (VMOVUPDmr addr:$dst, VR128:$src)>;
987 let Predicates = [UseSSE1] in
988 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
989 (MOVUPSmr addr:$dst, VR128:$src)>;
990 let Predicates = [UseSSE2] in
991 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
992 (MOVUPDmr addr:$dst, VR128:$src)>;
994 // Use vmovaps/vmovups for AVX integer load/store.
995 let Predicates = [HasAVX] in {
996 // 128-bit load/store
997 def : Pat<(alignedloadv2i64 addr:$src),
998 (VMOVAPSrm addr:$src)>;
999 def : Pat<(loadv2i64 addr:$src),
1000 (VMOVUPSrm addr:$src)>;
1002 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1003 (VMOVAPSmr addr:$dst, VR128:$src)>;
1004 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1005 (VMOVAPSmr addr:$dst, VR128:$src)>;
1006 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1007 (VMOVAPSmr addr:$dst, VR128:$src)>;
1008 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1009 (VMOVAPSmr addr:$dst, VR128:$src)>;
1010 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1011 (VMOVUPSmr addr:$dst, VR128:$src)>;
1012 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1013 (VMOVUPSmr addr:$dst, VR128:$src)>;
1014 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1015 (VMOVUPSmr addr:$dst, VR128:$src)>;
1016 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1017 (VMOVUPSmr addr:$dst, VR128:$src)>;
1019 // 256-bit load/store
1020 def : Pat<(alignedloadv4i64 addr:$src),
1021 (VMOVAPSYrm addr:$src)>;
1022 def : Pat<(loadv4i64 addr:$src),
1023 (VMOVUPSYrm addr:$src)>;
1024 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1025 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1026 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1027 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1028 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1029 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1030 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1031 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1032 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1033 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1034 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1035 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1036 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1037 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1038 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1039 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1041 // Special patterns for storing subvector extracts of lower 128-bits
1042 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1043 def : Pat<(alignedstore (v2f64 (extract_subvector
1044 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1045 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1046 def : Pat<(alignedstore (v4f32 (extract_subvector
1047 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1048 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1049 def : Pat<(alignedstore (v2i64 (extract_subvector
1050 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1051 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1052 def : Pat<(alignedstore (v4i32 (extract_subvector
1053 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1054 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1055 def : Pat<(alignedstore (v8i16 (extract_subvector
1056 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1057 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1058 def : Pat<(alignedstore (v16i8 (extract_subvector
1059 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1062 def : Pat<(store (v2f64 (extract_subvector
1063 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1064 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1065 def : Pat<(store (v4f32 (extract_subvector
1066 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1067 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1068 def : Pat<(store (v2i64 (extract_subvector
1069 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1070 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1071 def : Pat<(store (v4i32 (extract_subvector
1072 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1073 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1074 def : Pat<(store (v8i16 (extract_subvector
1075 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1076 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1077 def : Pat<(store (v16i8 (extract_subvector
1078 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1079 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1082 // Use movaps / movups for SSE integer load / store (one byte shorter).
1083 // The instructions selected below are then converted to MOVDQA/MOVDQU
1084 // during the SSE domain pass.
1085 let Predicates = [UseSSE1] in {
1086 def : Pat<(alignedloadv2i64 addr:$src),
1087 (MOVAPSrm addr:$src)>;
1088 def : Pat<(loadv2i64 addr:$src),
1089 (MOVUPSrm addr:$src)>;
1091 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1092 (MOVAPSmr addr:$dst, VR128:$src)>;
1093 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1094 (MOVAPSmr addr:$dst, VR128:$src)>;
1095 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1096 (MOVAPSmr addr:$dst, VR128:$src)>;
1097 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1098 (MOVAPSmr addr:$dst, VR128:$src)>;
1099 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1100 (MOVUPSmr addr:$dst, VR128:$src)>;
1101 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1102 (MOVUPSmr addr:$dst, VR128:$src)>;
1103 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1104 (MOVUPSmr addr:$dst, VR128:$src)>;
1105 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1106 (MOVUPSmr addr:$dst, VR128:$src)>;
1109 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1110 // bits are disregarded. FIXME: Set encoding to pseudo!
1111 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1112 let isCodeGenOnly = 1 in {
1113 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1114 "movaps\t{$src, $dst|$dst, $src}",
1115 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1116 IIC_SSE_MOVA_P_RM>, VEX;
1117 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1118 "movapd\t{$src, $dst|$dst, $src}",
1119 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1120 IIC_SSE_MOVA_P_RM>, VEX;
1121 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1122 "movaps\t{$src, $dst|$dst, $src}",
1123 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1125 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1126 "movapd\t{$src, $dst|$dst, $src}",
1127 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1132 //===----------------------------------------------------------------------===//
1133 // SSE 1 & 2 - Move Low packed FP Instructions
1134 //===----------------------------------------------------------------------===//
1136 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1137 string base_opc, string asm_opr,
1138 InstrItinClass itin> {
1139 def PSrm : PI<opc, MRMSrcMem,
1140 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1141 !strconcat(base_opc, "s", asm_opr),
1143 (psnode VR128:$src1,
1144 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1145 itin, SSEPackedSingle>, TB,
1146 Sched<[WriteShuffleLd, ReadAfterLd]>;
1148 def PDrm : PI<opc, MRMSrcMem,
1149 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1150 !strconcat(base_opc, "d", asm_opr),
1151 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1152 (scalar_to_vector (loadf64 addr:$src2)))))],
1153 itin, SSEPackedDouble>, PD,
1154 Sched<[WriteShuffleLd, ReadAfterLd]>;
1158 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1159 string base_opc, InstrItinClass itin> {
1160 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1161 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1164 let Constraints = "$src1 = $dst" in
1165 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1166 "\t{$src2, $dst|$dst, $src2}",
1170 let AddedComplexity = 20 in {
1171 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1175 let SchedRW = [WriteStore] in {
1176 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1177 "movlps\t{$src, $dst|$dst, $src}",
1178 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1179 (iPTR 0))), addr:$dst)],
1180 IIC_SSE_MOV_LH>, VEX;
1181 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1182 "movlpd\t{$src, $dst|$dst, $src}",
1183 [(store (f64 (vector_extract (v2f64 VR128:$src),
1184 (iPTR 0))), addr:$dst)],
1185 IIC_SSE_MOV_LH>, VEX;
1186 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1187 "movlps\t{$src, $dst|$dst, $src}",
1188 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1189 (iPTR 0))), addr:$dst)],
1191 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1192 "movlpd\t{$src, $dst|$dst, $src}",
1193 [(store (f64 (vector_extract (v2f64 VR128:$src),
1194 (iPTR 0))), addr:$dst)],
1198 let Predicates = [HasAVX] in {
1199 // Shuffle with VMOVLPS
1200 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1201 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1202 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1203 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1205 // Shuffle with VMOVLPD
1206 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1207 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1208 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1209 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1214 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1215 def : Pat<(store (v4i32 (X86Movlps
1216 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1217 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1218 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1220 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1221 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1223 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1226 let Predicates = [UseSSE1] in {
1227 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1228 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1229 (iPTR 0))), addr:$src1),
1230 (MOVLPSmr addr:$src1, VR128:$src2)>;
1232 // Shuffle with MOVLPS
1233 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1234 (MOVLPSrm VR128:$src1, addr:$src2)>;
1235 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1236 (MOVLPSrm VR128:$src1, addr:$src2)>;
1237 def : Pat<(X86Movlps VR128:$src1,
1238 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1239 (MOVLPSrm VR128:$src1, addr:$src2)>;
1242 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1244 (MOVLPSmr addr:$src1, VR128:$src2)>;
1245 def : Pat<(store (v4i32 (X86Movlps
1246 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1248 (MOVLPSmr addr:$src1, VR128:$src2)>;
1251 let Predicates = [UseSSE2] in {
1252 // Shuffle with MOVLPD
1253 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1254 (MOVLPDrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1256 (MOVLPDrm VR128:$src1, addr:$src2)>;
1259 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1261 (MOVLPDmr addr:$src1, VR128:$src2)>;
1262 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1264 (MOVLPDmr addr:$src1, VR128:$src2)>;
1267 //===----------------------------------------------------------------------===//
1268 // SSE 1 & 2 - Move Hi packed FP Instructions
1269 //===----------------------------------------------------------------------===//
1271 let AddedComplexity = 20 in {
1272 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1276 let SchedRW = [WriteStore] in {
1277 // v2f64 extract element 1 is always custom lowered to unpack high to low
1278 // and extract element 0 so the non-store version isn't too horrible.
1279 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1280 "movhps\t{$src, $dst|$dst, $src}",
1281 [(store (f64 (vector_extract
1282 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1283 (bc_v2f64 (v4f32 VR128:$src))),
1284 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1285 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1286 "movhpd\t{$src, $dst|$dst, $src}",
1287 [(store (f64 (vector_extract
1288 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1289 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1290 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1291 "movhps\t{$src, $dst|$dst, $src}",
1292 [(store (f64 (vector_extract
1293 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1294 (bc_v2f64 (v4f32 VR128:$src))),
1295 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1296 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1297 "movhpd\t{$src, $dst|$dst, $src}",
1298 [(store (f64 (vector_extract
1299 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1300 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1303 let Predicates = [HasAVX] in {
1305 def : Pat<(X86Movlhps VR128:$src1,
1306 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1307 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1308 def : Pat<(X86Movlhps VR128:$src1,
1309 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1310 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1312 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1313 // is during lowering, where it's not possible to recognize the load fold
1314 // cause it has two uses through a bitcast. One use disappears at isel time
1315 // and the fold opportunity reappears.
1316 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1317 (scalar_to_vector (loadf64 addr:$src2)))),
1318 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1321 let Predicates = [UseSSE1] in {
1323 def : Pat<(X86Movlhps VR128:$src1,
1324 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1325 (MOVHPSrm VR128:$src1, addr:$src2)>;
1326 def : Pat<(X86Movlhps VR128:$src1,
1327 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1328 (MOVHPSrm VR128:$src1, addr:$src2)>;
1331 let Predicates = [UseSSE2] in {
1332 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1333 // is during lowering, where it's not possible to recognize the load fold
1334 // cause it has two uses through a bitcast. One use disappears at isel time
1335 // and the fold opportunity reappears.
1336 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1337 (scalar_to_vector (loadf64 addr:$src2)))),
1338 (MOVHPDrm VR128:$src1, addr:$src2)>;
1341 //===----------------------------------------------------------------------===//
1342 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1343 //===----------------------------------------------------------------------===//
1345 let AddedComplexity = 20, Predicates = [UseAVX] in {
1346 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1347 (ins VR128:$src1, VR128:$src2),
1348 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1350 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1352 VEX_4V, Sched<[WriteShuffle]>;
1353 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1354 (ins VR128:$src1, VR128:$src2),
1355 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1357 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1359 VEX_4V, Sched<[WriteShuffle]>;
1361 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1362 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1363 (ins VR128:$src1, VR128:$src2),
1364 "movlhps\t{$src2, $dst|$dst, $src2}",
1366 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1367 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1368 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1369 (ins VR128:$src1, VR128:$src2),
1370 "movhlps\t{$src2, $dst|$dst, $src2}",
1372 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1373 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1376 let Predicates = [UseAVX] in {
1378 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1379 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1380 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1381 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1384 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1385 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1388 let Predicates = [UseSSE1] in {
1390 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1391 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1392 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1393 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1396 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1397 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1400 //===----------------------------------------------------------------------===//
1401 // SSE 1 & 2 - Conversion Instructions
1402 //===----------------------------------------------------------------------===//
1404 def SSE_CVT_PD : OpndItins<
1405 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1408 let Sched = WriteCvtI2F in
1409 def SSE_CVT_PS : OpndItins<
1410 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1413 let Sched = WriteCvtI2F in
1414 def SSE_CVT_Scalar : OpndItins<
1415 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1418 let Sched = WriteCvtF2I in
1419 def SSE_CVT_SS2SI_32 : OpndItins<
1420 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1423 let Sched = WriteCvtF2I in
1424 def SSE_CVT_SS2SI_64 : OpndItins<
1425 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1428 let Sched = WriteCvtF2I in
1429 def SSE_CVT_SD2SI : OpndItins<
1430 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1433 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1434 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1435 string asm, OpndItins itins> {
1436 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1437 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1438 itins.rr>, Sched<[itins.Sched]>;
1439 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1440 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1441 itins.rm>, Sched<[itins.Sched.Folded]>;
1444 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1445 X86MemOperand x86memop, string asm, Domain d,
1447 let neverHasSideEffects = 1 in {
1448 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1449 [], itins.rr, d>, Sched<[itins.Sched]>;
1451 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1452 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1456 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1457 X86MemOperand x86memop, string asm> {
1458 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1459 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1460 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1461 Sched<[WriteCvtI2F]>;
1463 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1464 (ins DstRC:$src1, x86memop:$src),
1465 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1466 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1467 } // neverHasSideEffects = 1
1470 let Predicates = [UseAVX] in {
1471 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1472 "cvttss2si\t{$src, $dst|$dst, $src}",
1475 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1476 "cvttss2si\t{$src, $dst|$dst, $src}",
1478 XS, VEX, VEX_W, VEX_LIG;
1479 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1480 "cvttsd2si\t{$src, $dst|$dst, $src}",
1483 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1484 "cvttsd2si\t{$src, $dst|$dst, $src}",
1486 XD, VEX, VEX_W, VEX_LIG;
1488 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1489 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1490 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1491 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1492 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1493 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1494 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1495 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1496 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1497 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1498 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1499 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1500 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1501 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1502 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1503 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1505 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1506 // register, but the same isn't true when only using memory operands,
1507 // provide other assembly "l" and "q" forms to address this explicitly
1508 // where appropriate to do so.
1509 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1510 XS, VEX_4V, VEX_LIG;
1511 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1512 XS, VEX_4V, VEX_W, VEX_LIG;
1513 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1514 XD, VEX_4V, VEX_LIG;
1515 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1516 XD, VEX_4V, VEX_W, VEX_LIG;
1518 let Predicates = [UseAVX] in {
1519 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1520 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1521 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1522 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1524 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1525 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1526 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1527 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1528 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1529 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1530 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1531 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1533 def : Pat<(f32 (sint_to_fp GR32:$src)),
1534 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1535 def : Pat<(f32 (sint_to_fp GR64:$src)),
1536 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1537 def : Pat<(f64 (sint_to_fp GR32:$src)),
1538 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1539 def : Pat<(f64 (sint_to_fp GR64:$src)),
1540 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1543 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1544 "cvttss2si\t{$src, $dst|$dst, $src}",
1545 SSE_CVT_SS2SI_32>, XS;
1546 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1547 "cvttss2si\t{$src, $dst|$dst, $src}",
1548 SSE_CVT_SS2SI_64>, XS, REX_W;
1549 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1550 "cvttsd2si\t{$src, $dst|$dst, $src}",
1552 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1553 "cvttsd2si\t{$src, $dst|$dst, $src}",
1554 SSE_CVT_SD2SI>, XD, REX_W;
1555 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1556 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1557 SSE_CVT_Scalar>, XS;
1558 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1559 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1560 SSE_CVT_Scalar>, XS, REX_W;
1561 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1562 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1563 SSE_CVT_Scalar>, XD;
1564 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1565 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1566 SSE_CVT_Scalar>, XD, REX_W;
1568 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1569 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1570 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1571 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1572 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1573 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1574 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1575 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1576 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1577 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1578 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1579 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1580 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1581 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1582 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1583 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1585 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1586 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1587 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1588 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1590 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1591 // and/or XMM operand(s).
1593 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1594 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1595 string asm, OpndItins itins> {
1596 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1597 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1598 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1599 Sched<[itins.Sched]>;
1600 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1601 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1602 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1603 Sched<[itins.Sched.Folded]>;
1606 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1607 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1608 PatFrag ld_frag, string asm, OpndItins itins,
1610 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1612 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1613 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1614 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1615 itins.rr>, Sched<[itins.Sched]>;
1616 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1617 (ins DstRC:$src1, x86memop:$src2),
1619 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1620 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1621 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1622 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1625 let Predicates = [UseAVX] in {
1626 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1627 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1628 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1629 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1630 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1631 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1633 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1634 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1635 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1636 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1639 let isCodeGenOnly = 1 in {
1640 let Predicates = [UseAVX] in {
1641 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1642 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1643 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1644 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1645 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1646 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1648 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1649 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1650 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1651 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1652 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1653 SSE_CVT_Scalar, 0>, XD,
1656 let Constraints = "$src1 = $dst" in {
1657 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1658 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1659 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1660 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1661 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1662 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1663 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1664 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1665 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1666 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1667 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1668 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1670 } // isCodeGenOnly = 1
1674 // Aliases for intrinsics
1675 let isCodeGenOnly = 1 in {
1676 let Predicates = [UseAVX] in {
1677 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1678 ssmem, sse_load_f32, "cvttss2si",
1679 SSE_CVT_SS2SI_32>, XS, VEX;
1680 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1681 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1682 "cvttss2si", SSE_CVT_SS2SI_64>,
1684 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1685 sdmem, sse_load_f64, "cvttsd2si",
1686 SSE_CVT_SD2SI>, XD, VEX;
1687 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1688 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1689 "cvttsd2si", SSE_CVT_SD2SI>,
1692 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1693 ssmem, sse_load_f32, "cvttss2si",
1694 SSE_CVT_SS2SI_32>, XS;
1695 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1696 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1697 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1698 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1699 sdmem, sse_load_f64, "cvttsd2si",
1701 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1702 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1703 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1704 } // isCodeGenOnly = 1
1706 let Predicates = [UseAVX] in {
1707 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1708 ssmem, sse_load_f32, "cvtss2si",
1709 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1710 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1711 ssmem, sse_load_f32, "cvtss2si",
1712 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1714 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1715 ssmem, sse_load_f32, "cvtss2si",
1716 SSE_CVT_SS2SI_32>, XS;
1717 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1718 ssmem, sse_load_f32, "cvtss2si",
1719 SSE_CVT_SS2SI_64>, XS, REX_W;
1721 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1722 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1723 SSEPackedSingle, SSE_CVT_PS>,
1724 TB, VEX, Requires<[HasAVX]>;
1725 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1726 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1727 SSEPackedSingle, SSE_CVT_PS>,
1728 TB, VEX, VEX_L, Requires<[HasAVX]>;
1730 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1731 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1732 SSEPackedSingle, SSE_CVT_PS>,
1733 TB, Requires<[UseSSE2]>;
1735 let Predicates = [UseAVX] in {
1736 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1737 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1738 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1739 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1740 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1741 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1742 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1743 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1744 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1745 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1746 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1747 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1748 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1749 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1750 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1751 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1754 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1755 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1756 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1757 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1758 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1759 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1760 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1761 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1762 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1763 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1764 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1765 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1766 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1767 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1768 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1769 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1773 // Convert scalar double to scalar single
1774 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1775 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1776 (ins FR64:$src1, FR64:$src2),
1777 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1778 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1779 Sched<[WriteCvtF2F]>;
1781 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1782 (ins FR64:$src1, f64mem:$src2),
1783 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1784 [], IIC_SSE_CVT_Scalar_RM>,
1785 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1786 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1789 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1792 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1793 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1794 [(set FR32:$dst, (fround FR64:$src))],
1795 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1796 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1797 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1798 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1799 IIC_SSE_CVT_Scalar_RM>,
1801 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1803 let isCodeGenOnly = 1 in {
1804 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1805 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1806 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1808 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1809 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1810 Sched<[WriteCvtF2F]>;
1811 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1812 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1813 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1814 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1815 VR128:$src1, sse_load_f64:$src2))],
1816 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1817 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1819 let Constraints = "$src1 = $dst" in {
1820 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1821 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1822 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1824 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1825 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1826 Sched<[WriteCvtF2F]>;
1827 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1828 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1829 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1830 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1831 VR128:$src1, sse_load_f64:$src2))],
1832 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1833 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1835 } // isCodeGenOnly = 1
1837 // Convert scalar single to scalar double
1838 // SSE2 instructions with XS prefix
1839 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1840 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1841 (ins FR32:$src1, FR32:$src2),
1842 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1843 [], IIC_SSE_CVT_Scalar_RR>,
1844 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1845 Sched<[WriteCvtF2F]>;
1847 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1848 (ins FR32:$src1, f32mem:$src2),
1849 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1850 [], IIC_SSE_CVT_Scalar_RM>,
1851 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1852 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1855 def : Pat<(f64 (fextend FR32:$src)),
1856 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1857 def : Pat<(fextend (loadf32 addr:$src)),
1858 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1860 def : Pat<(extloadf32 addr:$src),
1861 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1862 Requires<[UseAVX, OptForSize]>;
1863 def : Pat<(extloadf32 addr:$src),
1864 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1865 Requires<[UseAVX, OptForSpeed]>;
1867 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1868 "cvtss2sd\t{$src, $dst|$dst, $src}",
1869 [(set FR64:$dst, (fextend FR32:$src))],
1870 IIC_SSE_CVT_Scalar_RR>, XS,
1871 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1872 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1873 "cvtss2sd\t{$src, $dst|$dst, $src}",
1874 [(set FR64:$dst, (extloadf32 addr:$src))],
1875 IIC_SSE_CVT_Scalar_RM>, XS,
1876 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1878 // extload f32 -> f64. This matches load+fextend because we have a hack in
1879 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1881 // Since these loads aren't folded into the fextend, we have to match it
1883 def : Pat<(fextend (loadf32 addr:$src)),
1884 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1885 def : Pat<(extloadf32 addr:$src),
1886 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1888 let isCodeGenOnly = 1 in {
1889 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1890 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1891 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1893 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1894 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1895 Sched<[WriteCvtF2F]>;
1896 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1897 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1898 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1900 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1901 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1902 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1903 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1904 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1905 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1906 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1908 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1909 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1910 Sched<[WriteCvtF2F]>;
1911 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1912 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1913 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1915 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1916 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1917 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1919 } // isCodeGenOnly = 1
1921 // Convert packed single/double fp to doubleword
1922 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1923 "cvtps2dq\t{$src, $dst|$dst, $src}",
1924 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1925 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1926 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1927 "cvtps2dq\t{$src, $dst|$dst, $src}",
1929 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1930 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1931 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1932 "cvtps2dq\t{$src, $dst|$dst, $src}",
1934 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1935 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1936 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1937 "cvtps2dq\t{$src, $dst|$dst, $src}",
1939 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1940 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1941 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1942 "cvtps2dq\t{$src, $dst|$dst, $src}",
1943 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1944 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1945 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1946 "cvtps2dq\t{$src, $dst|$dst, $src}",
1948 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1949 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1952 // Convert Packed Double FP to Packed DW Integers
1953 let Predicates = [HasAVX] in {
1954 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1955 // register, but the same isn't true when using memory operands instead.
1956 // Provide other assembly rr and rm forms to address this explicitly.
1957 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1958 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1959 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1960 VEX, Sched<[WriteCvtF2I]>;
1963 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1964 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1965 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1966 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1968 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
1969 Sched<[WriteCvtF2ILd]>;
1972 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1973 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1975 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
1976 Sched<[WriteCvtF2I]>;
1977 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1978 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1980 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
1981 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1982 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1983 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1986 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1987 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1989 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1990 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
1991 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1992 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1993 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1994 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
1996 // Convert with truncation packed single/double fp to doubleword
1997 // SSE2 packed instructions with XS prefix
1998 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1999 "cvttps2dq\t{$src, $dst|$dst, $src}",
2001 (int_x86_sse2_cvttps2dq VR128:$src))],
2002 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2003 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2004 "cvttps2dq\t{$src, $dst|$dst, $src}",
2005 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2006 (loadv4f32 addr:$src)))],
2007 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2008 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2009 "cvttps2dq\t{$src, $dst|$dst, $src}",
2011 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2012 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2013 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2014 "cvttps2dq\t{$src, $dst|$dst, $src}",
2015 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2016 (loadv8f32 addr:$src)))],
2017 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2018 Sched<[WriteCvtF2ILd]>;
2020 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2021 "cvttps2dq\t{$src, $dst|$dst, $src}",
2022 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2023 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2024 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2025 "cvttps2dq\t{$src, $dst|$dst, $src}",
2027 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2028 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2030 let Predicates = [HasAVX] in {
2031 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2032 (VCVTDQ2PSrr VR128:$src)>;
2033 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2034 (VCVTDQ2PSrm addr:$src)>;
2036 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2037 (VCVTDQ2PSrr VR128:$src)>;
2038 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2039 (VCVTDQ2PSrm addr:$src)>;
2041 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2042 (VCVTTPS2DQrr VR128:$src)>;
2043 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2044 (VCVTTPS2DQrm addr:$src)>;
2046 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2047 (VCVTDQ2PSYrr VR256:$src)>;
2048 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2049 (VCVTDQ2PSYrm addr:$src)>;
2051 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2052 (VCVTTPS2DQYrr VR256:$src)>;
2053 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2054 (VCVTTPS2DQYrm addr:$src)>;
2057 let Predicates = [UseSSE2] in {
2058 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2059 (CVTDQ2PSrr VR128:$src)>;
2060 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2061 (CVTDQ2PSrm addr:$src)>;
2063 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2064 (CVTDQ2PSrr VR128:$src)>;
2065 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2066 (CVTDQ2PSrm addr:$src)>;
2068 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2069 (CVTTPS2DQrr VR128:$src)>;
2070 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2071 (CVTTPS2DQrm addr:$src)>;
2074 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2075 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2077 (int_x86_sse2_cvttpd2dq VR128:$src))],
2078 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2080 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2081 // register, but the same isn't true when using memory operands instead.
2082 // Provide other assembly rr and rm forms to address this explicitly.
2085 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2086 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
2087 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2088 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2089 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2090 (loadv2f64 addr:$src)))],
2091 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2094 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2095 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2097 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2098 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2099 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2100 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2102 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2103 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2104 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2105 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2107 let Predicates = [HasAVX] in {
2108 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2109 (VCVTTPD2DQYrr VR256:$src)>;
2110 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2111 (VCVTTPD2DQYrm addr:$src)>;
2112 } // Predicates = [HasAVX]
2114 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2115 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2116 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2117 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2118 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2119 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2120 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2121 (memopv2f64 addr:$src)))],
2123 Sched<[WriteCvtF2ILd]>;
2125 // Convert packed single to packed double
2126 let Predicates = [HasAVX] in {
2127 // SSE2 instructions without OpSize prefix
2128 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2129 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2130 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2131 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2132 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2133 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2134 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2135 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2136 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2137 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2139 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2140 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2141 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2142 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2145 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2148 let Predicates = [UseSSE2] in {
2149 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2150 "cvtps2pd\t{$src, $dst|$dst, $src}",
2151 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2152 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2153 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2154 "cvtps2pd\t{$src, $dst|$dst, $src}",
2155 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2156 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2159 // Convert Packed DW Integers to Packed Double FP
2160 let Predicates = [HasAVX] in {
2161 let neverHasSideEffects = 1, mayLoad = 1 in
2162 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2163 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2164 []>, VEX, Sched<[WriteCvtI2FLd]>;
2165 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2166 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2168 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2169 Sched<[WriteCvtI2F]>;
2170 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2171 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2173 (int_x86_avx_cvtdq2_pd_256
2174 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2175 Sched<[WriteCvtI2FLd]>;
2176 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2177 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2179 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2180 Sched<[WriteCvtI2F]>;
2183 let neverHasSideEffects = 1, mayLoad = 1 in
2184 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2185 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2186 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2187 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2188 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2189 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2190 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2192 // AVX 256-bit register conversion intrinsics
2193 let Predicates = [HasAVX] in {
2194 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2195 (VCVTDQ2PDYrr VR128:$src)>;
2196 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2197 (VCVTDQ2PDYrm addr:$src)>;
2198 } // Predicates = [HasAVX]
2200 // Convert packed double to packed single
2201 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2202 // register, but the same isn't true when using memory operands instead.
2203 // Provide other assembly rr and rm forms to address this explicitly.
2204 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2205 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2206 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2207 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2210 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2211 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2212 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2213 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2215 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2216 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2219 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2220 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2222 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2223 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2224 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2225 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2227 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2228 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2229 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2230 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2232 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2233 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2234 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2235 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2236 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2237 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2239 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2240 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2243 // AVX 256-bit register conversion intrinsics
2244 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2245 // whenever possible to avoid declaring two versions of each one.
2246 let Predicates = [HasAVX] in {
2247 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2248 (VCVTDQ2PSYrr VR256:$src)>;
2249 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2250 (VCVTDQ2PSYrm addr:$src)>;
2252 // Match fround and fextend for 128/256-bit conversions
2253 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2254 (VCVTPD2PSrr VR128:$src)>;
2255 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2256 (VCVTPD2PSXrm addr:$src)>;
2257 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2258 (VCVTPD2PSYrr VR256:$src)>;
2259 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2260 (VCVTPD2PSYrm addr:$src)>;
2262 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2263 (VCVTPS2PDrr VR128:$src)>;
2264 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2265 (VCVTPS2PDYrr VR128:$src)>;
2266 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2267 (VCVTPS2PDYrm addr:$src)>;
2270 let Predicates = [UseSSE2] in {
2271 // Match fround and fextend for 128 conversions
2272 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2273 (CVTPD2PSrr VR128:$src)>;
2274 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2275 (CVTPD2PSrm addr:$src)>;
2277 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2278 (CVTPS2PDrr VR128:$src)>;
2281 //===----------------------------------------------------------------------===//
2282 // SSE 1 & 2 - Compare Instructions
2283 //===----------------------------------------------------------------------===//
2285 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2286 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2287 Operand CC, SDNode OpNode, ValueType VT,
2288 PatFrag ld_frag, string asm, string asm_alt,
2290 def rr : SIi8<0xC2, MRMSrcReg,
2291 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2292 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2293 itins.rr>, Sched<[itins.Sched]>;
2294 def rm : SIi8<0xC2, MRMSrcMem,
2295 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2296 [(set RC:$dst, (OpNode (VT RC:$src1),
2297 (ld_frag addr:$src2), imm:$cc))],
2299 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2301 // Accept explicit immediate argument form instead of comparison code.
2302 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2303 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2304 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2305 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2307 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2308 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2309 IIC_SSE_ALU_F32S_RM>,
2310 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2314 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2315 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2316 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2318 XS, VEX_4V, VEX_LIG;
2319 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2320 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2321 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2322 SSE_ALU_F32S>, // same latency as 32 bit compare
2323 XD, VEX_4V, VEX_LIG;
2325 let Constraints = "$src1 = $dst" in {
2326 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2327 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2328 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2330 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2331 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2332 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2337 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2338 Intrinsic Int, string asm, OpndItins itins> {
2339 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2340 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2341 [(set VR128:$dst, (Int VR128:$src1,
2342 VR128:$src, imm:$cc))],
2344 Sched<[itins.Sched]>;
2345 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2346 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2347 [(set VR128:$dst, (Int VR128:$src1,
2348 (load addr:$src), imm:$cc))],
2350 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2353 let isCodeGenOnly = 1 in {
2354 // Aliases to match intrinsics which expect XMM operand(s).
2355 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2356 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2359 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2360 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2361 SSE_ALU_F32S>, // same latency as f32
2363 let Constraints = "$src1 = $dst" in {
2364 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2365 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2367 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2368 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2375 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2376 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2377 ValueType vt, X86MemOperand x86memop,
2378 PatFrag ld_frag, string OpcodeStr> {
2379 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2380 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2381 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2384 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2385 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2386 [(set EFLAGS, (OpNode (vt RC:$src1),
2387 (ld_frag addr:$src2)))],
2389 Sched<[WriteFAddLd, ReadAfterLd]>;
2392 let Defs = [EFLAGS] in {
2393 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2394 "ucomiss">, TB, VEX, VEX_LIG;
2395 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2396 "ucomisd">, PD, VEX, VEX_LIG;
2397 let Pattern = []<dag> in {
2398 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2399 "comiss">, TB, VEX, VEX_LIG;
2400 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2401 "comisd">, PD, VEX, VEX_LIG;
2404 let isCodeGenOnly = 1 in {
2405 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2406 load, "ucomiss">, TB, VEX;
2407 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2408 load, "ucomisd">, PD, VEX;
2410 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2411 load, "comiss">, TB, VEX;
2412 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2413 load, "comisd">, PD, VEX;
2415 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2417 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2420 let Pattern = []<dag> in {
2421 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2423 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2427 let isCodeGenOnly = 1 in {
2428 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2429 load, "ucomiss">, TB;
2430 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2431 load, "ucomisd">, PD;
2433 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2435 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2438 } // Defs = [EFLAGS]
2440 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2441 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2442 Operand CC, Intrinsic Int, string asm,
2443 string asm_alt, Domain d,
2444 OpndItins itins = SSE_ALU_F32P> {
2445 def rri : PIi8<0xC2, MRMSrcReg,
2446 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2447 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2450 def rmi : PIi8<0xC2, MRMSrcMem,
2451 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2452 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2454 Sched<[WriteFAddLd, ReadAfterLd]>;
2456 // Accept explicit immediate argument form instead of comparison code.
2457 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2458 def rri_alt : PIi8<0xC2, MRMSrcReg,
2459 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2460 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2461 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2462 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2463 asm_alt, [], itins.rm, d>,
2464 Sched<[WriteFAddLd, ReadAfterLd]>;
2468 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2469 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2470 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2471 SSEPackedSingle>, TB, VEX_4V;
2472 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2473 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2474 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2475 SSEPackedDouble>, PD, VEX_4V;
2476 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2477 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2478 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2479 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2480 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2481 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2482 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2483 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2484 let Constraints = "$src1 = $dst" in {
2485 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2486 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2487 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2488 SSEPackedSingle, SSE_ALU_F32P>, TB;
2489 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2490 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2491 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2492 SSEPackedDouble, SSE_ALU_F64P>, PD;
2495 let Predicates = [HasAVX] in {
2496 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2497 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2498 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2499 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2500 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2501 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2502 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2503 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2505 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2506 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2507 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2508 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2509 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2510 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2511 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2512 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2515 let Predicates = [UseSSE1] in {
2516 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2517 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2518 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2519 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2522 let Predicates = [UseSSE2] in {
2523 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2524 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2525 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2526 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2529 //===----------------------------------------------------------------------===//
2530 // SSE 1 & 2 - Shuffle Instructions
2531 //===----------------------------------------------------------------------===//
2533 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2534 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2535 ValueType vt, string asm, PatFrag mem_frag,
2536 Domain d, bit IsConvertibleToThreeAddress = 0> {
2537 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2538 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2539 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2540 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2541 Sched<[WriteShuffleLd, ReadAfterLd]>;
2542 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2543 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2544 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2545 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2546 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2547 Sched<[WriteShuffle]>;
2550 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2551 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2552 loadv4f32, SSEPackedSingle>, TB, VEX_4V;
2553 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2554 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2555 loadv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2556 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2557 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2558 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2559 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2560 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2561 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2563 let Constraints = "$src1 = $dst" in {
2564 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2565 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2566 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>, TB;
2567 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2568 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2569 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>, PD;
2572 let Predicates = [HasAVX] in {
2573 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2574 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2575 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2576 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2577 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2579 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2580 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2581 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2582 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2583 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2586 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2587 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2588 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2589 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2590 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2592 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2593 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2594 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2595 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2596 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2599 let Predicates = [UseSSE1] in {
2600 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2601 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2602 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2603 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2604 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2607 let Predicates = [UseSSE2] in {
2608 // Generic SHUFPD patterns
2609 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2610 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2611 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2612 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2613 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2616 //===----------------------------------------------------------------------===//
2617 // SSE 1 & 2 - Unpack Instructions
2618 //===----------------------------------------------------------------------===//
2620 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2621 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2622 PatFrag mem_frag, RegisterClass RC,
2623 X86MemOperand x86memop, string asm,
2625 def rr : PI<opc, MRMSrcReg,
2626 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2628 (vt (OpNode RC:$src1, RC:$src2)))],
2629 IIC_SSE_UNPCK, d>, Sched<[WriteShuffle]>;
2630 def rm : PI<opc, MRMSrcMem,
2631 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2633 (vt (OpNode RC:$src1,
2634 (mem_frag addr:$src2))))],
2636 Sched<[WriteShuffleLd, ReadAfterLd]>;
2639 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2640 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2641 SSEPackedSingle>, TB, VEX_4V;
2642 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2643 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2644 SSEPackedDouble>, PD, VEX_4V;
2645 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2646 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2647 SSEPackedSingle>, TB, VEX_4V;
2648 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2649 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2650 SSEPackedDouble>, PD, VEX_4V;
2652 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2653 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2654 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2655 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2656 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2657 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2658 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2659 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2660 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2661 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2662 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2663 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2665 let Constraints = "$src1 = $dst" in {
2666 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2667 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2668 SSEPackedSingle>, TB;
2669 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2670 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2671 SSEPackedDouble>, PD;
2672 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2673 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2674 SSEPackedSingle>, TB;
2675 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2676 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2677 SSEPackedDouble>, PD;
2678 } // Constraints = "$src1 = $dst"
2680 let Predicates = [HasAVX1Only] in {
2681 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2682 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2683 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2684 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2685 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2686 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2687 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2688 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2690 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2691 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2692 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2693 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2694 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2695 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2696 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2697 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2700 let Predicates = [HasAVX] in {
2701 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2702 // problem is during lowering, where it's not possible to recognize the load
2703 // fold cause it has two uses through a bitcast. One use disappears at isel
2704 // time and the fold opportunity reappears.
2705 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2706 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2709 let Predicates = [UseSSE2] in {
2710 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2711 // problem is during lowering, where it's not possible to recognize the load
2712 // fold cause it has two uses through a bitcast. One use disappears at isel
2713 // time and the fold opportunity reappears.
2714 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2715 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2718 //===----------------------------------------------------------------------===//
2719 // SSE 1 & 2 - Extract Floating-Point Sign mask
2720 //===----------------------------------------------------------------------===//
2722 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2723 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2725 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2726 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2727 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2728 Sched<[WriteVecLogic]>;
2731 let Predicates = [HasAVX] in {
2732 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2733 "movmskps", SSEPackedSingle>, TB, VEX;
2734 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2735 "movmskpd", SSEPackedDouble>, PD, VEX;
2736 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2737 "movmskps", SSEPackedSingle>, TB,
2739 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2740 "movmskpd", SSEPackedDouble>, PD,
2743 def : Pat<(i32 (X86fgetsign FR32:$src)),
2744 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2745 def : Pat<(i64 (X86fgetsign FR32:$src)),
2746 (SUBREG_TO_REG (i64 0),
2747 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2748 def : Pat<(i32 (X86fgetsign FR64:$src)),
2749 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2750 def : Pat<(i64 (X86fgetsign FR64:$src)),
2751 (SUBREG_TO_REG (i64 0),
2752 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2755 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2756 SSEPackedSingle>, TB;
2757 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2758 SSEPackedDouble>, PD;
2760 def : Pat<(i32 (X86fgetsign FR32:$src)),
2761 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2762 Requires<[UseSSE1]>;
2763 def : Pat<(i64 (X86fgetsign FR32:$src)),
2764 (SUBREG_TO_REG (i64 0),
2765 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2766 Requires<[UseSSE1]>;
2767 def : Pat<(i32 (X86fgetsign FR64:$src)),
2768 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2769 Requires<[UseSSE2]>;
2770 def : Pat<(i64 (X86fgetsign FR64:$src)),
2771 (SUBREG_TO_REG (i64 0),
2772 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2773 Requires<[UseSSE2]>;
2775 //===---------------------------------------------------------------------===//
2776 // SSE2 - Packed Integer Logical Instructions
2777 //===---------------------------------------------------------------------===//
2779 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2781 /// PDI_binop_rm - Simple SSE2 binary operator.
2782 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2783 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2784 X86MemOperand x86memop, OpndItins itins,
2785 bit IsCommutable, bit Is2Addr> {
2786 let isCommutable = IsCommutable in
2787 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2788 (ins RC:$src1, RC:$src2),
2790 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2791 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2792 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2793 Sched<[itins.Sched]>;
2794 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2795 (ins RC:$src1, x86memop:$src2),
2797 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2798 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2799 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2800 (bitconvert (memop_frag addr:$src2)))))],
2802 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2804 } // ExeDomain = SSEPackedInt
2806 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2807 ValueType OpVT128, ValueType OpVT256,
2808 OpndItins itins, bit IsCommutable = 0> {
2809 let Predicates = [HasAVX] in
2810 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2811 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2813 let Constraints = "$src1 = $dst" in
2814 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2815 memopv2i64, i128mem, itins, IsCommutable, 1>;
2817 let Predicates = [HasAVX2] in
2818 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2819 OpVT256, VR256, loadv4i64, i256mem, itins,
2820 IsCommutable, 0>, VEX_4V, VEX_L;
2823 // These are ordered here for pattern ordering requirements with the fp versions
2825 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2826 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2827 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2828 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2829 SSE_BIT_ITINS_P, 0>;
2831 //===----------------------------------------------------------------------===//
2832 // SSE 1 & 2 - Logical Instructions
2833 //===----------------------------------------------------------------------===//
2835 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2837 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2838 SDNode OpNode, OpndItins itins> {
2839 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2840 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2843 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2844 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2847 let Constraints = "$src1 = $dst" in {
2848 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2849 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2852 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2853 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2858 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2859 let isCodeGenOnly = 1 in {
2860 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2862 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2864 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2867 let isCommutable = 0 in
2868 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2872 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2874 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2876 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2877 !strconcat(OpcodeStr, "ps"), f256mem,
2878 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2879 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2880 (loadv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2882 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2883 !strconcat(OpcodeStr, "pd"), f256mem,
2884 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2885 (bc_v4i64 (v4f64 VR256:$src2))))],
2886 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2887 (loadv4i64 addr:$src2)))], 0>,
2890 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2891 // are all promoted to v2i64, and the patterns are covered by the int
2892 // version. This is needed in SSE only, because v2i64 isn't supported on
2893 // SSE1, but only on SSE2.
2894 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2895 !strconcat(OpcodeStr, "ps"), f128mem, [],
2896 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2897 (loadv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2899 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2900 !strconcat(OpcodeStr, "pd"), f128mem,
2901 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2902 (bc_v2i64 (v2f64 VR128:$src2))))],
2903 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2904 (loadv2i64 addr:$src2)))], 0>,
2907 let Constraints = "$src1 = $dst" in {
2908 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2909 !strconcat(OpcodeStr, "ps"), f128mem,
2910 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2911 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2912 (memopv2i64 addr:$src2)))]>, TB;
2914 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2915 !strconcat(OpcodeStr, "pd"), f128mem,
2916 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2917 (bc_v2i64 (v2f64 VR128:$src2))))],
2918 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2919 (memopv2i64 addr:$src2)))]>, PD;
2923 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2924 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2925 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2926 let isCommutable = 0 in
2927 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2929 //===----------------------------------------------------------------------===//
2930 // SSE 1 & 2 - Arithmetic Instructions
2931 //===----------------------------------------------------------------------===//
2933 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2936 /// In addition, we also have a special variant of the scalar form here to
2937 /// represent the associated intrinsic operation. This form is unlike the
2938 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2939 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2941 /// These three forms can each be reg+reg or reg+mem.
2944 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2946 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2947 SDNode OpNode, SizeItins itins> {
2948 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2949 VR128, v4f32, f128mem, loadv4f32,
2950 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2951 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2952 VR128, v2f64, f128mem, loadv2f64,
2953 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
2955 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2956 OpNode, VR256, v8f32, f256mem, loadv8f32,
2957 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2958 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2959 OpNode, VR256, v4f64, f256mem, loadv4f64,
2960 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
2962 let Constraints = "$src1 = $dst" in {
2963 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2964 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2966 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2967 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2972 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2974 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2975 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
2976 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2977 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
2979 let Constraints = "$src1 = $dst" in {
2980 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2981 OpNode, FR32, f32mem, itins.s>, XS;
2982 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2983 OpNode, FR64, f64mem, itins.d>, XD;
2987 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2989 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2990 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2991 itins.s, 0>, XS, VEX_4V, VEX_LIG;
2992 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2993 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2994 itins.d, 0>, XD, VEX_4V, VEX_LIG;
2996 let Constraints = "$src1 = $dst" in {
2997 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2998 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3000 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3001 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3006 // Binary Arithmetic instructions
3007 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3008 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3009 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3010 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3011 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3012 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3013 let isCommutable = 0 in {
3014 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3015 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3016 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3017 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3018 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3019 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3020 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3021 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3022 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3023 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3024 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3025 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3028 let isCodeGenOnly = 1 in {
3029 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3030 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3031 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3032 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3035 // Patterns used to select SSE scalar fp arithmetic instructions from
3036 // a scalar fp operation followed by a blend.
3038 // These patterns know, for example, how to select an ADDSS from a
3039 // float add plus vector insert.
3041 // The effect is that the backend no longer emits unnecessary vector
3042 // insert instructions immediately after SSE scalar fp instructions
3043 // like addss or mulss.
3045 // For example, given the following code:
3046 // __m128 foo(__m128 A, __m128 B) {
3051 // previously we generated:
3052 // addss %xmm0, %xmm1
3053 // movss %xmm1, %xmm0
3056 // addss %xmm1, %xmm0
3058 let Predicates = [UseSSE1] in {
3059 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3060 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3062 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3063 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3064 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3066 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3067 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3068 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3070 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3071 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3072 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3074 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3077 let Predicates = [UseSSE2] in {
3078 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3080 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3081 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3083 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3084 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3085 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3087 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3088 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3089 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3091 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3092 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3093 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3095 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3098 let Predicates = [UseSSE41] in {
3099 // If the subtarget has SSE4.1 but not AVX, the vector insert
3100 // instruction is lowered into a X86insrtps rather than a X86Movss.
3101 // When selecting SSE scalar single-precision fp arithmetic instructions,
3102 // make sure that we correctly match the X86insrtps.
3104 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3105 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3106 FR32:$src))), (iPTR 0))),
3107 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3108 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3109 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3110 FR32:$src))), (iPTR 0))),
3111 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3112 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3113 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3114 FR32:$src))), (iPTR 0))),
3115 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3116 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3117 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3118 FR32:$src))), (iPTR 0))),
3119 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3122 let Predicates = [HasAVX] in {
3123 // The following patterns select AVX Scalar single/double precision fp
3124 // arithmetic instructions.
3126 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3127 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3129 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3130 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3131 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3133 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3134 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3135 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3137 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3138 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3139 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3141 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3142 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3143 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3144 FR32:$src))), (iPTR 0))),
3145 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3146 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3147 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3148 FR32:$src))), (iPTR 0))),
3149 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3150 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3151 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3152 FR32:$src))), (iPTR 0))),
3153 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3154 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3155 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3156 FR32:$src))), (iPTR 0))),
3157 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3160 // Patterns used to select SSE scalar fp arithmetic instructions from
3161 // a vector packed single/double fp operation followed by a vector insert.
3163 // The effect is that the backend converts the packed fp instruction
3164 // followed by a vector insert into a single SSE scalar fp instruction.
3166 // For example, given the following code:
3167 // __m128 foo(__m128 A, __m128 B) {
3168 // __m128 C = A + B;
3169 // return (__m128) {c[0], a[1], a[2], a[3]};
3172 // previously we generated:
3173 // addps %xmm0, %xmm1
3174 // movss %xmm1, %xmm0
3177 // addss %xmm1, %xmm0
3179 let Predicates = [UseSSE1] in {
3180 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3181 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3182 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3183 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3184 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3185 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3186 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3187 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3188 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3189 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3190 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3191 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3194 let Predicates = [UseSSE2] in {
3195 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3196 // from a packed double-precision fp instruction plus movsd.
3198 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3199 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3200 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3201 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3202 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3203 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3204 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3205 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3206 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3207 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3208 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3209 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3212 let Predicates = [HasAVX] in {
3213 // The following patterns select AVX Scalar single/double precision fp
3214 // arithmetic instructions from a packed single precision fp instruction
3215 // plus movss/movsd.
3217 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3218 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3219 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3220 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3221 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3222 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3223 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3224 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3225 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3226 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3227 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3228 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3229 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3230 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3231 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3232 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3233 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3234 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3235 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3236 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3237 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3238 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3239 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3240 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3244 /// In addition, we also have a special variant of the scalar form here to
3245 /// represent the associated intrinsic operation. This form is unlike the
3246 /// plain scalar form, in that it takes an entire vector (instead of a
3247 /// scalar) and leaves the top elements undefined.
3249 /// And, we have a special variant form for a full-vector intrinsic form.
3251 let Sched = WriteFSqrt in {
3252 def SSE_SQRTPS : OpndItins<
3253 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3256 def SSE_SQRTSS : OpndItins<
3257 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3260 def SSE_SQRTPD : OpndItins<
3261 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3264 def SSE_SQRTSD : OpndItins<
3265 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3269 let Sched = WriteFRcp in {
3270 def SSE_RCPP : OpndItins<
3271 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3274 def SSE_RCPS : OpndItins<
3275 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3279 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3280 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3281 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3282 let Predicates = [HasAVX], hasSideEffects = 0 in {
3283 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3284 (ins FR32:$src1, FR32:$src2),
3285 !strconcat("v", OpcodeStr,
3286 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3287 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3288 let mayLoad = 1 in {
3289 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3290 (ins FR32:$src1,f32mem:$src2),
3291 !strconcat("v", OpcodeStr,
3292 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3293 []>, VEX_4V, VEX_LIG,
3294 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3295 let isCodeGenOnly = 1 in
3296 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3297 (ins VR128:$src1, ssmem:$src2),
3298 !strconcat("v", OpcodeStr,
3299 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3300 []>, VEX_4V, VEX_LIG,
3301 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3305 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3306 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3307 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3308 // For scalar unary operations, fold a load into the operation
3309 // only in OptForSize mode. It eliminates an instruction, but it also
3310 // eliminates a whole-register clobber (the load), so it introduces a
3311 // partial register update condition.
3312 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3313 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3314 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3315 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3316 let isCodeGenOnly = 1 in {
3317 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3318 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3319 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3320 Sched<[itins.Sched]>;
3321 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3322 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3323 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3324 Sched<[itins.Sched.Folded]>;
3328 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3329 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3331 let Predicates = [HasAVX], hasSideEffects = 0 in {
3332 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3333 (ins FR32:$src1, FR32:$src2),
3334 !strconcat("v", OpcodeStr,
3335 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3336 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3337 let mayLoad = 1 in {
3338 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3339 (ins FR32:$src1,f32mem:$src2),
3340 !strconcat("v", OpcodeStr,
3341 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3342 []>, VEX_4V, VEX_LIG,
3343 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3344 let isCodeGenOnly = 1 in
3345 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3346 (ins VR128:$src1, ssmem:$src2),
3347 !strconcat("v", OpcodeStr,
3348 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3349 []>, VEX_4V, VEX_LIG,
3350 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3354 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3355 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3356 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3357 // For scalar unary operations, fold a load into the operation
3358 // only in OptForSize mode. It eliminates an instruction, but it also
3359 // eliminates a whole-register clobber (the load), so it introduces a
3360 // partial register update condition.
3361 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3362 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3363 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3364 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3365 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3366 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3367 (ins VR128:$src1, VR128:$src2),
3368 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3369 [], itins.rr>, Sched<[itins.Sched]>;
3370 let mayLoad = 1, hasSideEffects = 0 in
3371 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3372 (ins VR128:$src1, ssmem:$src2),
3373 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3374 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3378 /// sse1_fp_unop_p - SSE1 unops in packed form.
3379 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3381 let Predicates = [HasAVX] in {
3382 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3383 !strconcat("v", OpcodeStr,
3384 "ps\t{$src, $dst|$dst, $src}"),
3385 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3386 itins.rr>, VEX, Sched<[itins.Sched]>;
3387 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3388 !strconcat("v", OpcodeStr,
3389 "ps\t{$src, $dst|$dst, $src}"),
3390 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3391 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3392 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3393 !strconcat("v", OpcodeStr,
3394 "ps\t{$src, $dst|$dst, $src}"),
3395 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3396 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3397 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3398 !strconcat("v", OpcodeStr,
3399 "ps\t{$src, $dst|$dst, $src}"),
3400 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3401 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3404 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3405 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3406 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3407 Sched<[itins.Sched]>;
3408 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3409 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3410 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3411 Sched<[itins.Sched.Folded]>;
3414 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3415 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3416 Intrinsic V4F32Int, Intrinsic V8F32Int,
3418 let isCodeGenOnly = 1 in {
3419 let Predicates = [HasAVX] in {
3420 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3421 !strconcat("v", OpcodeStr,
3422 "ps\t{$src, $dst|$dst, $src}"),
3423 [(set VR128:$dst, (V4F32Int VR128:$src))],
3424 itins.rr>, VEX, Sched<[itins.Sched]>;
3425 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3426 !strconcat("v", OpcodeStr,
3427 "ps\t{$src, $dst|$dst, $src}"),
3428 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3429 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3430 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3431 !strconcat("v", OpcodeStr,
3432 "ps\t{$src, $dst|$dst, $src}"),
3433 [(set VR256:$dst, (V8F32Int VR256:$src))],
3434 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3435 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3437 !strconcat("v", OpcodeStr,
3438 "ps\t{$src, $dst|$dst, $src}"),
3439 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3440 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3443 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3444 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3445 [(set VR128:$dst, (V4F32Int VR128:$src))],
3446 itins.rr>, Sched<[itins.Sched]>;
3447 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3448 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3449 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3450 itins.rm>, Sched<[itins.Sched.Folded]>;
3451 } // isCodeGenOnly = 1
3454 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3455 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3456 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3457 let Predicates = [HasAVX], hasSideEffects = 0 in {
3458 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3459 (ins FR64:$src1, FR64:$src2),
3460 !strconcat("v", OpcodeStr,
3461 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3462 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3463 let mayLoad = 1 in {
3464 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3465 (ins FR64:$src1,f64mem:$src2),
3466 !strconcat("v", OpcodeStr,
3467 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3468 []>, VEX_4V, VEX_LIG,
3469 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3470 let isCodeGenOnly = 1 in
3471 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3472 (ins VR128:$src1, sdmem:$src2),
3473 !strconcat("v", OpcodeStr,
3474 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3475 []>, VEX_4V, VEX_LIG,
3476 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3480 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3481 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3482 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3483 Sched<[itins.Sched]>;
3484 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3485 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3486 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3487 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3488 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3489 let isCodeGenOnly = 1 in {
3490 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3491 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3492 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3493 Sched<[itins.Sched]>;
3494 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3495 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3496 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3497 Sched<[itins.Sched.Folded]>;
3501 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3502 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3503 SDNode OpNode, OpndItins itins> {
3504 let Predicates = [HasAVX] in {
3505 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3506 !strconcat("v", OpcodeStr,
3507 "pd\t{$src, $dst|$dst, $src}"),
3508 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3509 itins.rr>, VEX, Sched<[itins.Sched]>;
3510 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3511 !strconcat("v", OpcodeStr,
3512 "pd\t{$src, $dst|$dst, $src}"),
3513 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3514 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3515 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3516 !strconcat("v", OpcodeStr,
3517 "pd\t{$src, $dst|$dst, $src}"),
3518 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3519 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3520 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3521 !strconcat("v", OpcodeStr,
3522 "pd\t{$src, $dst|$dst, $src}"),
3523 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3524 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3527 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3528 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3529 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3530 Sched<[itins.Sched]>;
3531 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3532 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3533 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3534 Sched<[itins.Sched.Folded]>;
3538 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3540 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3541 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3543 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3545 // Reciprocal approximations. Note that these typically require refinement
3546 // in order to obtain suitable precision.
3547 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3548 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3549 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3550 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3551 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3552 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3553 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3554 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3556 let Predicates = [UseAVX] in {
3557 def : Pat<(f32 (fsqrt FR32:$src)),
3558 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3559 def : Pat<(f32 (fsqrt (load addr:$src))),
3560 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3561 Requires<[HasAVX, OptForSize]>;
3562 def : Pat<(f64 (fsqrt FR64:$src)),
3563 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3564 def : Pat<(f64 (fsqrt (load addr:$src))),
3565 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3566 Requires<[HasAVX, OptForSize]>;
3568 def : Pat<(f32 (X86frsqrt FR32:$src)),
3569 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3570 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3571 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3572 Requires<[HasAVX, OptForSize]>;
3574 def : Pat<(f32 (X86frcp FR32:$src)),
3575 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3576 def : Pat<(f32 (X86frcp (load addr:$src))),
3577 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3578 Requires<[HasAVX, OptForSize]>;
3580 let Predicates = [UseAVX] in {
3581 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3582 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3583 (COPY_TO_REGCLASS VR128:$src, FR32)),
3585 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3586 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3588 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3589 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3590 (COPY_TO_REGCLASS VR128:$src, FR64)),
3592 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3593 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3596 let Predicates = [HasAVX] in {
3597 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3598 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3599 (COPY_TO_REGCLASS VR128:$src, FR32)),
3601 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3602 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3604 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3605 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3606 (COPY_TO_REGCLASS VR128:$src, FR32)),
3608 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3609 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3612 // Reciprocal approximations. Note that these typically require refinement
3613 // in order to obtain suitable precision.
3614 let Predicates = [UseSSE1] in {
3615 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3616 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3617 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3618 (RCPSSr_Int VR128:$src, VR128:$src)>;
3621 // There is no f64 version of the reciprocal approximation instructions.
3623 //===----------------------------------------------------------------------===//
3624 // SSE 1 & 2 - Non-temporal stores
3625 //===----------------------------------------------------------------------===//
3627 let AddedComplexity = 400 in { // Prefer non-temporal versions
3628 let SchedRW = [WriteStore] in {
3629 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3630 (ins f128mem:$dst, VR128:$src),
3631 "movntps\t{$src, $dst|$dst, $src}",
3632 [(alignednontemporalstore (v4f32 VR128:$src),
3634 IIC_SSE_MOVNT>, VEX;
3635 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3636 (ins f128mem:$dst, VR128:$src),
3637 "movntpd\t{$src, $dst|$dst, $src}",
3638 [(alignednontemporalstore (v2f64 VR128:$src),
3640 IIC_SSE_MOVNT>, VEX;
3642 let ExeDomain = SSEPackedInt in
3643 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3644 (ins f128mem:$dst, VR128:$src),
3645 "movntdq\t{$src, $dst|$dst, $src}",
3646 [(alignednontemporalstore (v2i64 VR128:$src),
3648 IIC_SSE_MOVNT>, VEX;
3650 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3651 (ins f256mem:$dst, VR256:$src),
3652 "movntps\t{$src, $dst|$dst, $src}",
3653 [(alignednontemporalstore (v8f32 VR256:$src),
3655 IIC_SSE_MOVNT>, VEX, VEX_L;
3656 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3657 (ins f256mem:$dst, VR256:$src),
3658 "movntpd\t{$src, $dst|$dst, $src}",
3659 [(alignednontemporalstore (v4f64 VR256:$src),
3661 IIC_SSE_MOVNT>, VEX, VEX_L;
3662 let ExeDomain = SSEPackedInt in
3663 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3664 (ins f256mem:$dst, VR256:$src),
3665 "movntdq\t{$src, $dst|$dst, $src}",
3666 [(alignednontemporalstore (v4i64 VR256:$src),
3668 IIC_SSE_MOVNT>, VEX, VEX_L;
3670 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3671 "movntps\t{$src, $dst|$dst, $src}",
3672 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3674 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3675 "movntpd\t{$src, $dst|$dst, $src}",
3676 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3679 let ExeDomain = SSEPackedInt in
3680 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3681 "movntdq\t{$src, $dst|$dst, $src}",
3682 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3685 // There is no AVX form for instructions below this point
3686 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3687 "movnti{l}\t{$src, $dst|$dst, $src}",
3688 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3690 TB, Requires<[HasSSE2]>;
3691 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3692 "movnti{q}\t{$src, $dst|$dst, $src}",
3693 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3695 TB, Requires<[HasSSE2]>;
3696 } // SchedRW = [WriteStore]
3698 } // AddedComplexity
3700 //===----------------------------------------------------------------------===//
3701 // SSE 1 & 2 - Prefetch and memory fence
3702 //===----------------------------------------------------------------------===//
3704 // Prefetch intrinsic.
3705 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3706 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3707 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3708 IIC_SSE_PREFETCH>, TB;
3709 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3710 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3711 IIC_SSE_PREFETCH>, TB;
3712 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3713 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3714 IIC_SSE_PREFETCH>, TB;
3715 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3716 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3717 IIC_SSE_PREFETCH>, TB;
3720 // FIXME: How should these memory instructions be modeled?
3721 let SchedRW = [WriteLoad] in {
3723 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3724 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3725 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3727 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3728 // was introduced with SSE2, it's backward compatible.
3729 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3730 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3731 REP, Requires<[HasSSE2]>;
3733 // Load, store, and memory fence
3734 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3735 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3736 TB, Requires<[HasSSE1]>;
3737 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3738 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3739 TB, Requires<[HasSSE2]>;
3740 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3741 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3742 TB, Requires<[HasSSE2]>;
3745 def : Pat<(X86SFence), (SFENCE)>;
3746 def : Pat<(X86LFence), (LFENCE)>;
3747 def : Pat<(X86MFence), (MFENCE)>;
3749 //===----------------------------------------------------------------------===//
3750 // SSE 1 & 2 - Load/Store XCSR register
3751 //===----------------------------------------------------------------------===//
3753 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3754 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3755 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3756 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3757 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3758 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3760 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3761 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3762 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3763 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3764 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3765 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3767 //===---------------------------------------------------------------------===//
3768 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3769 //===---------------------------------------------------------------------===//
3771 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3773 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3774 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3775 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3777 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3778 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3780 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3781 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3783 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3784 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3789 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3790 SchedRW = [WriteMove] in {
3791 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3792 "movdqa\t{$src, $dst|$dst, $src}", [],
3795 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3796 "movdqa\t{$src, $dst|$dst, $src}", [],
3797 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3798 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3799 "movdqu\t{$src, $dst|$dst, $src}", [],
3802 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3803 "movdqu\t{$src, $dst|$dst, $src}", [],
3804 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3807 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3808 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3809 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3810 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3812 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3813 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3815 let Predicates = [HasAVX] in {
3816 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3817 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3819 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3820 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3825 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3826 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3827 (ins i128mem:$dst, VR128:$src),
3828 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3830 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3831 (ins i256mem:$dst, VR256:$src),
3832 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3834 let Predicates = [HasAVX] in {
3835 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3836 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3838 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3839 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3844 let SchedRW = [WriteMove] in {
3845 let neverHasSideEffects = 1 in
3846 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3847 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3849 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3850 "movdqu\t{$src, $dst|$dst, $src}",
3851 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3854 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3855 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3856 "movdqa\t{$src, $dst|$dst, $src}", [],
3859 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3860 "movdqu\t{$src, $dst|$dst, $src}",
3861 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3865 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3866 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3867 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3868 "movdqa\t{$src, $dst|$dst, $src}",
3869 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3871 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3872 "movdqu\t{$src, $dst|$dst, $src}",
3873 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3875 XS, Requires<[UseSSE2]>;
3878 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3879 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3880 "movdqa\t{$src, $dst|$dst, $src}",
3881 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3883 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3884 "movdqu\t{$src, $dst|$dst, $src}",
3885 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3887 XS, Requires<[UseSSE2]>;
3890 } // ExeDomain = SSEPackedInt
3892 let Predicates = [HasAVX] in {
3893 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3894 (VMOVDQUmr addr:$dst, VR128:$src)>;
3895 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3896 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3898 let Predicates = [UseSSE2] in
3899 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3900 (MOVDQUmr addr:$dst, VR128:$src)>;
3902 //===---------------------------------------------------------------------===//
3903 // SSE2 - Packed Integer Arithmetic Instructions
3904 //===---------------------------------------------------------------------===//
3906 let Sched = WriteVecIMul in
3907 def SSE_PMADD : OpndItins<
3908 IIC_SSE_PMADD, IIC_SSE_PMADD
3911 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3913 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3914 RegisterClass RC, PatFrag memop_frag,
3915 X86MemOperand x86memop,
3917 bit IsCommutable = 0,
3919 let isCommutable = IsCommutable in
3920 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3921 (ins RC:$src1, RC:$src2),
3923 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3924 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3925 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3926 Sched<[itins.Sched]>;
3927 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3928 (ins RC:$src1, x86memop:$src2),
3930 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3931 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3932 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3933 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3936 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3937 Intrinsic IntId256, OpndItins itins,
3938 bit IsCommutable = 0> {
3939 let Predicates = [HasAVX] in
3940 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3941 VR128, loadv2i64, i128mem, itins,
3942 IsCommutable, 0>, VEX_4V;
3944 let Constraints = "$src1 = $dst" in
3945 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3946 i128mem, itins, IsCommutable, 1>;
3948 let Predicates = [HasAVX2] in
3949 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3950 VR256, loadv4i64, i256mem, itins,
3951 IsCommutable, 0>, VEX_4V, VEX_L;
3954 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3955 string OpcodeStr, SDNode OpNode,
3956 SDNode OpNode2, RegisterClass RC,
3957 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3958 ShiftOpndItins itins,
3960 // src2 is always 128-bit
3961 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3962 (ins RC:$src1, VR128:$src2),
3964 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3965 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3966 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3967 itins.rr>, Sched<[WriteVecShift]>;
3968 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3969 (ins RC:$src1, i128mem:$src2),
3971 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3972 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3973 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3974 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
3975 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3976 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3977 (ins RC:$src1, i8imm:$src2),
3979 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3980 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3981 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3982 Sched<[WriteVecShift]>;
3985 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3986 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3987 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3988 PatFrag memop_frag, X86MemOperand x86memop,
3990 bit IsCommutable = 0, bit Is2Addr = 1> {
3991 let isCommutable = IsCommutable in
3992 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3993 (ins RC:$src1, RC:$src2),
3995 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3996 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3997 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3998 Sched<[itins.Sched]>;
3999 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4000 (ins RC:$src1, x86memop:$src2),
4002 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4003 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4004 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4005 (bitconvert (memop_frag addr:$src2)))))]>,
4006 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4008 } // ExeDomain = SSEPackedInt
4010 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4011 SSE_INTALU_ITINS_P, 1>;
4012 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4013 SSE_INTALU_ITINS_P, 1>;
4014 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4015 SSE_INTALU_ITINS_P, 1>;
4016 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4017 SSE_INTALUQ_ITINS_P, 1>;
4018 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4019 SSE_INTMUL_ITINS_P, 1>;
4020 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4021 SSE_INTALU_ITINS_P, 0>;
4022 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4023 SSE_INTALU_ITINS_P, 0>;
4024 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4025 SSE_INTALU_ITINS_P, 0>;
4026 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4027 SSE_INTALUQ_ITINS_P, 0>;
4028 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4029 SSE_INTALU_ITINS_P, 0>;
4030 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4031 SSE_INTALU_ITINS_P, 0>;
4032 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4033 SSE_INTALU_ITINS_P, 1>;
4034 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4035 SSE_INTALU_ITINS_P, 1>;
4036 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4037 SSE_INTALU_ITINS_P, 1>;
4038 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4039 SSE_INTALU_ITINS_P, 1>;
4042 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4043 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4044 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4045 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4046 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4047 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4048 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4049 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4050 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4051 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4052 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4053 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4054 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
4055 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
4056 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
4057 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
4058 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4059 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4060 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4061 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4062 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4063 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4064 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4065 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4067 let Predicates = [HasAVX] in
4068 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4069 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4071 let Predicates = [HasAVX2] in
4072 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4073 VR256, loadv4i64, i256mem,
4074 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4075 let Constraints = "$src1 = $dst" in
4076 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4077 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4079 //===---------------------------------------------------------------------===//
4080 // SSE2 - Packed Integer Logical Instructions
4081 //===---------------------------------------------------------------------===//
4083 let Predicates = [HasAVX] in {
4084 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4085 VR128, v8i16, v8i16, bc_v8i16,
4086 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4087 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4088 VR128, v4i32, v4i32, bc_v4i32,
4089 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4090 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4091 VR128, v2i64, v2i64, bc_v2i64,
4092 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4094 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4095 VR128, v8i16, v8i16, bc_v8i16,
4096 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4097 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4098 VR128, v4i32, v4i32, bc_v4i32,
4099 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4100 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4101 VR128, v2i64, v2i64, bc_v2i64,
4102 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4104 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4105 VR128, v8i16, v8i16, bc_v8i16,
4106 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4107 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4108 VR128, v4i32, v4i32, bc_v4i32,
4109 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4111 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4112 // 128-bit logical shifts.
4113 def VPSLLDQri : PDIi8<0x73, MRM7r,
4114 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4115 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4117 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4119 def VPSRLDQri : PDIi8<0x73, MRM3r,
4120 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4121 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4123 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4125 // PSRADQri doesn't exist in SSE[1-3].
4127 } // Predicates = [HasAVX]
4129 let Predicates = [HasAVX2] in {
4130 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4131 VR256, v16i16, v8i16, bc_v8i16,
4132 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4133 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4134 VR256, v8i32, v4i32, bc_v4i32,
4135 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4136 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4137 VR256, v4i64, v2i64, bc_v2i64,
4138 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4140 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4141 VR256, v16i16, v8i16, bc_v8i16,
4142 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4143 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4144 VR256, v8i32, v4i32, bc_v4i32,
4145 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4146 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4147 VR256, v4i64, v2i64, bc_v2i64,
4148 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4150 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4151 VR256, v16i16, v8i16, bc_v8i16,
4152 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4153 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4154 VR256, v8i32, v4i32, bc_v4i32,
4155 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4157 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4158 // 256-bit logical shifts.
4159 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4160 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4161 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4163 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4165 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4166 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4167 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4169 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4171 // PSRADQYri doesn't exist in SSE[1-3].
4173 } // Predicates = [HasAVX2]
4175 let Constraints = "$src1 = $dst" in {
4176 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4177 VR128, v8i16, v8i16, bc_v8i16,
4178 SSE_INTSHIFT_ITINS_P>;
4179 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4180 VR128, v4i32, v4i32, bc_v4i32,
4181 SSE_INTSHIFT_ITINS_P>;
4182 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4183 VR128, v2i64, v2i64, bc_v2i64,
4184 SSE_INTSHIFT_ITINS_P>;
4186 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4187 VR128, v8i16, v8i16, bc_v8i16,
4188 SSE_INTSHIFT_ITINS_P>;
4189 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4190 VR128, v4i32, v4i32, bc_v4i32,
4191 SSE_INTSHIFT_ITINS_P>;
4192 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4193 VR128, v2i64, v2i64, bc_v2i64,
4194 SSE_INTSHIFT_ITINS_P>;
4196 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4197 VR128, v8i16, v8i16, bc_v8i16,
4198 SSE_INTSHIFT_ITINS_P>;
4199 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4200 VR128, v4i32, v4i32, bc_v4i32,
4201 SSE_INTSHIFT_ITINS_P>;
4203 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4204 // 128-bit logical shifts.
4205 def PSLLDQri : PDIi8<0x73, MRM7r,
4206 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4207 "pslldq\t{$src2, $dst|$dst, $src2}",
4209 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4210 IIC_SSE_INTSHDQ_P_RI>;
4211 def PSRLDQri : PDIi8<0x73, MRM3r,
4212 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4213 "psrldq\t{$src2, $dst|$dst, $src2}",
4215 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4216 IIC_SSE_INTSHDQ_P_RI>;
4217 // PSRADQri doesn't exist in SSE[1-3].
4219 } // Constraints = "$src1 = $dst"
4221 let Predicates = [HasAVX] in {
4222 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4223 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4224 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4225 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4226 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4227 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4229 // Shift up / down and insert zero's.
4230 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4231 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4232 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4233 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4236 let Predicates = [HasAVX2] in {
4237 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4238 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4239 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4240 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4243 let Predicates = [UseSSE2] in {
4244 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4245 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4246 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4247 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4248 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4249 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4251 // Shift up / down and insert zero's.
4252 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4253 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4254 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4255 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4258 //===---------------------------------------------------------------------===//
4259 // SSE2 - Packed Integer Comparison Instructions
4260 //===---------------------------------------------------------------------===//
4262 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4263 SSE_INTALU_ITINS_P, 1>;
4264 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4265 SSE_INTALU_ITINS_P, 1>;
4266 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4267 SSE_INTALU_ITINS_P, 1>;
4268 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4269 SSE_INTALU_ITINS_P, 0>;
4270 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4271 SSE_INTALU_ITINS_P, 0>;
4272 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4273 SSE_INTALU_ITINS_P, 0>;
4275 //===---------------------------------------------------------------------===//
4276 // SSE2 - Packed Integer Pack Instructions
4277 //===---------------------------------------------------------------------===//
4279 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4280 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
4281 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4282 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
4283 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4284 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
4286 //===---------------------------------------------------------------------===//
4287 // SSE2 - Packed Integer Shuffle Instructions
4288 //===---------------------------------------------------------------------===//
4290 let ExeDomain = SSEPackedInt in {
4291 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4293 let Predicates = [HasAVX] in {
4294 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4295 (ins VR128:$src1, i8imm:$src2),
4296 !strconcat("v", OpcodeStr,
4297 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4299 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4300 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4301 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4302 (ins i128mem:$src1, i8imm:$src2),
4303 !strconcat("v", OpcodeStr,
4304 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4306 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4307 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4308 Sched<[WriteShuffleLd]>;
4311 let Predicates = [HasAVX2] in {
4312 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4313 (ins VR256:$src1, i8imm:$src2),
4314 !strconcat("v", OpcodeStr,
4315 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4317 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4318 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4319 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4320 (ins i256mem:$src1, i8imm:$src2),
4321 !strconcat("v", OpcodeStr,
4322 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4324 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4325 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4326 Sched<[WriteShuffleLd]>;
4329 let Predicates = [UseSSE2] in {
4330 def ri : Ii8<0x70, MRMSrcReg,
4331 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4332 !strconcat(OpcodeStr,
4333 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4335 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4336 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4337 def mi : Ii8<0x70, MRMSrcMem,
4338 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4339 !strconcat(OpcodeStr,
4340 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4342 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4343 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4344 Sched<[WriteShuffleLd]>;
4347 } // ExeDomain = SSEPackedInt
4349 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4350 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4351 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4353 let Predicates = [HasAVX] in {
4354 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4355 (VPSHUFDmi addr:$src1, imm:$imm)>;
4356 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4357 (VPSHUFDri VR128:$src1, imm:$imm)>;
4360 let Predicates = [UseSSE2] in {
4361 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4362 (PSHUFDmi addr:$src1, imm:$imm)>;
4363 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4364 (PSHUFDri VR128:$src1, imm:$imm)>;
4367 //===---------------------------------------------------------------------===//
4368 // SSE2 - Packed Integer Unpack Instructions
4369 //===---------------------------------------------------------------------===//
4371 let ExeDomain = SSEPackedInt in {
4372 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4373 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4374 def rr : PDI<opc, MRMSrcReg,
4375 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4377 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4378 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4379 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4380 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4381 def rm : PDI<opc, MRMSrcMem,
4382 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4384 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4385 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4386 [(set VR128:$dst, (OpNode VR128:$src1,
4387 (bc_frag (memopv2i64
4390 Sched<[WriteShuffleLd, ReadAfterLd]>;
4393 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4394 SDNode OpNode, PatFrag bc_frag> {
4395 def Yrr : PDI<opc, MRMSrcReg,
4396 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4397 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4398 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4399 Sched<[WriteShuffle]>;
4400 def Yrm : PDI<opc, MRMSrcMem,
4401 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4402 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4403 [(set VR256:$dst, (OpNode VR256:$src1,
4404 (bc_frag (memopv4i64 addr:$src2))))]>,
4405 Sched<[WriteShuffleLd, ReadAfterLd]>;
4408 let Predicates = [HasAVX] in {
4409 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4410 bc_v16i8, 0>, VEX_4V;
4411 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4412 bc_v8i16, 0>, VEX_4V;
4413 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4414 bc_v4i32, 0>, VEX_4V;
4415 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4416 bc_v2i64, 0>, VEX_4V;
4418 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4419 bc_v16i8, 0>, VEX_4V;
4420 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4421 bc_v8i16, 0>, VEX_4V;
4422 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4423 bc_v4i32, 0>, VEX_4V;
4424 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4425 bc_v2i64, 0>, VEX_4V;
4428 let Predicates = [HasAVX2] in {
4429 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4430 bc_v32i8>, VEX_4V, VEX_L;
4431 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4432 bc_v16i16>, VEX_4V, VEX_L;
4433 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4434 bc_v8i32>, VEX_4V, VEX_L;
4435 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4436 bc_v4i64>, VEX_4V, VEX_L;
4438 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4439 bc_v32i8>, VEX_4V, VEX_L;
4440 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4441 bc_v16i16>, VEX_4V, VEX_L;
4442 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4443 bc_v8i32>, VEX_4V, VEX_L;
4444 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4445 bc_v4i64>, VEX_4V, VEX_L;
4448 let Constraints = "$src1 = $dst" in {
4449 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4451 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4453 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4455 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4458 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4460 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4462 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4464 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4467 } // ExeDomain = SSEPackedInt
4469 //===---------------------------------------------------------------------===//
4470 // SSE2 - Packed Integer Extract and Insert
4471 //===---------------------------------------------------------------------===//
4473 let ExeDomain = SSEPackedInt in {
4474 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4475 def rri : Ii8<0xC4, MRMSrcReg,
4476 (outs VR128:$dst), (ins VR128:$src1,
4477 GR32orGR64:$src2, i32i8imm:$src3),
4479 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4480 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4482 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4483 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4484 def rmi : Ii8<0xC4, MRMSrcMem,
4485 (outs VR128:$dst), (ins VR128:$src1,
4486 i16mem:$src2, i32i8imm:$src3),
4488 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4489 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4491 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4492 imm:$src3))], IIC_SSE_PINSRW>,
4493 Sched<[WriteShuffleLd, ReadAfterLd]>;
4497 let Predicates = [HasAVX] in
4498 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4499 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4500 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4501 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4502 imm:$src2))]>, PD, VEX,
4503 Sched<[WriteShuffle]>;
4504 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4505 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4506 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4507 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4508 imm:$src2))], IIC_SSE_PEXTRW>,
4509 Sched<[WriteShuffleLd, ReadAfterLd]>;
4512 let Predicates = [HasAVX] in
4513 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4515 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4516 defm PINSRW : sse2_pinsrw, PD;
4518 } // ExeDomain = SSEPackedInt
4520 //===---------------------------------------------------------------------===//
4521 // SSE2 - Packed Mask Creation
4522 //===---------------------------------------------------------------------===//
4524 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4526 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4528 "pmovmskb\t{$src, $dst|$dst, $src}",
4529 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4530 IIC_SSE_MOVMSK>, VEX;
4532 let Predicates = [HasAVX2] in {
4533 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4535 "pmovmskb\t{$src, $dst|$dst, $src}",
4536 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4540 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4541 "pmovmskb\t{$src, $dst|$dst, $src}",
4542 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4545 } // ExeDomain = SSEPackedInt
4547 //===---------------------------------------------------------------------===//
4548 // SSE2 - Conditional Store
4549 //===---------------------------------------------------------------------===//
4551 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4553 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4554 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4555 (ins VR128:$src, VR128:$mask),
4556 "maskmovdqu\t{$mask, $src|$src, $mask}",
4557 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4558 IIC_SSE_MASKMOV>, VEX;
4559 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4560 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4561 (ins VR128:$src, VR128:$mask),
4562 "maskmovdqu\t{$mask, $src|$src, $mask}",
4563 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4564 IIC_SSE_MASKMOV>, VEX;
4566 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4567 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4568 "maskmovdqu\t{$mask, $src|$src, $mask}",
4569 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4571 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4572 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4573 "maskmovdqu\t{$mask, $src|$src, $mask}",
4574 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4577 } // ExeDomain = SSEPackedInt
4579 //===---------------------------------------------------------------------===//
4580 // SSE2 - Move Doubleword
4581 //===---------------------------------------------------------------------===//
4583 //===---------------------------------------------------------------------===//
4584 // Move Int Doubleword to Packed Double Int
4586 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4587 "movd\t{$src, $dst|$dst, $src}",
4589 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4590 VEX, Sched<[WriteMove]>;
4591 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4592 "movd\t{$src, $dst|$dst, $src}",
4594 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4596 VEX, Sched<[WriteLoad]>;
4597 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4598 "movq\t{$src, $dst|$dst, $src}",
4600 (v2i64 (scalar_to_vector GR64:$src)))],
4601 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4602 let isCodeGenOnly = 1 in
4603 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4604 "movq\t{$src, $dst|$dst, $src}",
4605 [(set FR64:$dst, (bitconvert GR64:$src))],
4606 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4608 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4609 "movd\t{$src, $dst|$dst, $src}",
4611 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4613 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4614 "movd\t{$src, $dst|$dst, $src}",
4616 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4617 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4618 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4619 "mov{d|q}\t{$src, $dst|$dst, $src}",
4621 (v2i64 (scalar_to_vector GR64:$src)))],
4622 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4623 let isCodeGenOnly = 1 in
4624 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4625 "mov{d|q}\t{$src, $dst|$dst, $src}",
4626 [(set FR64:$dst, (bitconvert GR64:$src))],
4627 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4629 //===---------------------------------------------------------------------===//
4630 // Move Int Doubleword to Single Scalar
4632 let isCodeGenOnly = 1 in {
4633 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4634 "movd\t{$src, $dst|$dst, $src}",
4635 [(set FR32:$dst, (bitconvert GR32:$src))],
4636 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4638 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4639 "movd\t{$src, $dst|$dst, $src}",
4640 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4642 VEX, Sched<[WriteLoad]>;
4643 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4644 "movd\t{$src, $dst|$dst, $src}",
4645 [(set FR32:$dst, (bitconvert GR32:$src))],
4646 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4648 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4649 "movd\t{$src, $dst|$dst, $src}",
4650 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4651 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4654 //===---------------------------------------------------------------------===//
4655 // Move Packed Doubleword Int to Packed Double Int
4657 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4658 "movd\t{$src, $dst|$dst, $src}",
4659 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4660 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4662 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4663 (ins i32mem:$dst, VR128:$src),
4664 "movd\t{$src, $dst|$dst, $src}",
4665 [(store (i32 (vector_extract (v4i32 VR128:$src),
4666 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4667 VEX, Sched<[WriteLoad]>;
4668 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4669 "movd\t{$src, $dst|$dst, $src}",
4670 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4671 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4673 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4674 "movd\t{$src, $dst|$dst, $src}",
4675 [(store (i32 (vector_extract (v4i32 VR128:$src),
4676 (iPTR 0))), addr:$dst)],
4677 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4679 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4680 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4682 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4683 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4685 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4686 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4688 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4689 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4691 //===---------------------------------------------------------------------===//
4692 // Move Packed Doubleword Int first element to Doubleword Int
4694 let SchedRW = [WriteMove] in {
4695 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4696 "movq\t{$src, $dst|$dst, $src}",
4697 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4702 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4703 "mov{d|q}\t{$src, $dst|$dst, $src}",
4704 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4709 //===---------------------------------------------------------------------===//
4710 // Bitcast FR64 <-> GR64
4712 let isCodeGenOnly = 1 in {
4713 let Predicates = [UseAVX] in
4714 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4715 "movq\t{$src, $dst|$dst, $src}",
4716 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4717 VEX, Sched<[WriteLoad]>;
4718 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4719 "movq\t{$src, $dst|$dst, $src}",
4720 [(set GR64:$dst, (bitconvert FR64:$src))],
4721 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4722 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4723 "movq\t{$src, $dst|$dst, $src}",
4724 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4725 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4727 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4728 "movq\t{$src, $dst|$dst, $src}",
4729 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4730 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4731 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4732 "mov{d|q}\t{$src, $dst|$dst, $src}",
4733 [(set GR64:$dst, (bitconvert FR64:$src))],
4734 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4735 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4736 "movq\t{$src, $dst|$dst, $src}",
4737 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4738 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4741 //===---------------------------------------------------------------------===//
4742 // Move Scalar Single to Double Int
4744 let isCodeGenOnly = 1 in {
4745 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4746 "movd\t{$src, $dst|$dst, $src}",
4747 [(set GR32:$dst, (bitconvert FR32:$src))],
4748 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4749 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4750 "movd\t{$src, $dst|$dst, $src}",
4751 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4752 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4753 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4754 "movd\t{$src, $dst|$dst, $src}",
4755 [(set GR32:$dst, (bitconvert FR32:$src))],
4756 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4757 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4758 "movd\t{$src, $dst|$dst, $src}",
4759 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4760 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4763 //===---------------------------------------------------------------------===//
4764 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4766 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4767 let AddedComplexity = 15 in {
4768 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4769 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4770 [(set VR128:$dst, (v2i64 (X86vzmovl
4771 (v2i64 (scalar_to_vector GR64:$src)))))],
4774 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4775 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4776 [(set VR128:$dst, (v2i64 (X86vzmovl
4777 (v2i64 (scalar_to_vector GR64:$src)))))],
4780 } // isCodeGenOnly, SchedRW
4782 let Predicates = [UseAVX] in {
4783 let AddedComplexity = 15 in
4784 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4785 (VMOVDI2PDIrr GR32:$src)>;
4787 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4788 let AddedComplexity = 20 in {
4789 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4790 (VMOVDI2PDIrm addr:$src)>;
4791 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4792 (VMOVDI2PDIrm addr:$src)>;
4793 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4794 (VMOVDI2PDIrm addr:$src)>;
4796 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4797 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4798 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4799 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4800 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4801 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4802 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4805 let Predicates = [UseSSE2] in {
4806 let AddedComplexity = 15 in
4807 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4808 (MOVDI2PDIrr GR32:$src)>;
4810 let AddedComplexity = 20 in {
4811 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4812 (MOVDI2PDIrm addr:$src)>;
4813 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4814 (MOVDI2PDIrm addr:$src)>;
4815 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4816 (MOVDI2PDIrm addr:$src)>;
4820 // These are the correct encodings of the instructions so that we know how to
4821 // read correct assembly, even though we continue to emit the wrong ones for
4822 // compatibility with Darwin's buggy assembler.
4823 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4824 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4825 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4826 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4827 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4828 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4829 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4830 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4831 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4833 //===---------------------------------------------------------------------===//
4834 // SSE2 - Move Quadword
4835 //===---------------------------------------------------------------------===//
4837 //===---------------------------------------------------------------------===//
4838 // Move Quadword Int to Packed Quadword Int
4841 let SchedRW = [WriteLoad] in {
4842 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4843 "vmovq\t{$src, $dst|$dst, $src}",
4845 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4846 VEX, Requires<[UseAVX]>;
4847 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4848 "movq\t{$src, $dst|$dst, $src}",
4850 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4852 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4855 //===---------------------------------------------------------------------===//
4856 // Move Packed Quadword Int to Quadword Int
4858 let SchedRW = [WriteStore] in {
4859 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4860 "movq\t{$src, $dst|$dst, $src}",
4861 [(store (i64 (vector_extract (v2i64 VR128:$src),
4862 (iPTR 0))), addr:$dst)],
4863 IIC_SSE_MOVDQ>, VEX;
4864 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4865 "movq\t{$src, $dst|$dst, $src}",
4866 [(store (i64 (vector_extract (v2i64 VR128:$src),
4867 (iPTR 0))), addr:$dst)],
4871 // For disassembler only
4872 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4873 SchedRW = [WriteVecLogic] in {
4874 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4875 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
4876 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4877 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
4880 //===---------------------------------------------------------------------===//
4881 // Store / copy lower 64-bits of a XMM register.
4883 let Predicates = [UseAVX] in
4884 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4885 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
4886 let Predicates = [UseSSE2] in
4887 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4888 (MOVPQI2QImr addr:$dst, VR128:$src)>;
4890 let isCodeGenOnly = 1, AddedComplexity = 20 in {
4891 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4892 "vmovq\t{$src, $dst|$dst, $src}",
4894 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4895 (loadi64 addr:$src))))))],
4897 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
4899 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4900 "movq\t{$src, $dst|$dst, $src}",
4902 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4903 (loadi64 addr:$src))))))],
4905 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4908 let Predicates = [UseAVX], AddedComplexity = 20 in {
4909 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4910 (VMOVZQI2PQIrm addr:$src)>;
4911 def : Pat<(v2i64 (X86vzload addr:$src)),
4912 (VMOVZQI2PQIrm addr:$src)>;
4915 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4916 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4917 (MOVZQI2PQIrm addr:$src)>;
4918 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4921 let Predicates = [HasAVX] in {
4922 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4923 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4924 def : Pat<(v4i64 (X86vzload addr:$src)),
4925 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4928 //===---------------------------------------------------------------------===//
4929 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4930 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4932 let SchedRW = [WriteVecLogic] in {
4933 let AddedComplexity = 15 in
4934 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4935 "vmovq\t{$src, $dst|$dst, $src}",
4936 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4938 XS, VEX, Requires<[UseAVX]>;
4939 let AddedComplexity = 15 in
4940 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4941 "movq\t{$src, $dst|$dst, $src}",
4942 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4944 XS, Requires<[UseSSE2]>;
4947 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
4948 let AddedComplexity = 20 in
4949 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4950 "vmovq\t{$src, $dst|$dst, $src}",
4951 [(set VR128:$dst, (v2i64 (X86vzmovl
4952 (loadv2i64 addr:$src))))],
4954 XS, VEX, Requires<[UseAVX]>;
4955 let AddedComplexity = 20 in {
4956 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4957 "movq\t{$src, $dst|$dst, $src}",
4958 [(set VR128:$dst, (v2i64 (X86vzmovl
4959 (loadv2i64 addr:$src))))],
4961 XS, Requires<[UseSSE2]>;
4963 } // isCodeGenOnly, SchedRW
4965 let AddedComplexity = 20 in {
4966 let Predicates = [UseAVX] in {
4967 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4968 (VMOVZPQILo2PQIrr VR128:$src)>;
4970 let Predicates = [UseSSE2] in {
4971 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4972 (MOVZPQILo2PQIrr VR128:$src)>;
4976 //===---------------------------------------------------------------------===//
4977 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4978 //===---------------------------------------------------------------------===//
4979 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4980 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4981 X86MemOperand x86memop> {
4982 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4983 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4984 [(set RC:$dst, (vt (OpNode RC:$src)))],
4985 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4986 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4987 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4988 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4989 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4992 let Predicates = [HasAVX] in {
4993 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4994 v4f32, VR128, loadv4f32, f128mem>, VEX;
4995 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4996 v4f32, VR128, loadv4f32, f128mem>, VEX;
4997 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4998 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
4999 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5000 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5002 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5003 memopv4f32, f128mem>;
5004 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5005 memopv4f32, f128mem>;
5007 let Predicates = [HasAVX] in {
5008 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5009 (VMOVSHDUPrr VR128:$src)>;
5010 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5011 (VMOVSHDUPrm addr:$src)>;
5012 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5013 (VMOVSLDUPrr VR128:$src)>;
5014 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5015 (VMOVSLDUPrm addr:$src)>;
5016 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5017 (VMOVSHDUPYrr VR256:$src)>;
5018 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5019 (VMOVSHDUPYrm addr:$src)>;
5020 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5021 (VMOVSLDUPYrr VR256:$src)>;
5022 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5023 (VMOVSLDUPYrm addr:$src)>;
5026 let Predicates = [UseSSE3] in {
5027 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5028 (MOVSHDUPrr VR128:$src)>;
5029 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5030 (MOVSHDUPrm addr:$src)>;
5031 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5032 (MOVSLDUPrr VR128:$src)>;
5033 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5034 (MOVSLDUPrm addr:$src)>;
5037 //===---------------------------------------------------------------------===//
5038 // SSE3 - Replicate Double FP - MOVDDUP
5039 //===---------------------------------------------------------------------===//
5041 multiclass sse3_replicate_dfp<string OpcodeStr> {
5042 let neverHasSideEffects = 1 in
5043 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5044 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5045 [], IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
5046 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5047 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5050 (scalar_to_vector (loadf64 addr:$src)))))],
5051 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
5054 // FIXME: Merge with above classe when there're patterns for the ymm version
5055 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5056 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5057 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5058 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5059 Sched<[WriteShuffle]>;
5060 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5061 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5064 (scalar_to_vector (loadf64 addr:$src)))))]>,
5065 Sched<[WriteShuffleLd]>;
5068 let Predicates = [HasAVX] in {
5069 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5070 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5073 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5075 let Predicates = [HasAVX] in {
5076 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5077 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5078 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5079 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5080 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5081 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5082 def : Pat<(X86Movddup (bc_v2f64
5083 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5084 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5087 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5088 (VMOVDDUPYrm addr:$src)>;
5089 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5090 (VMOVDDUPYrm addr:$src)>;
5091 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5092 (VMOVDDUPYrm addr:$src)>;
5093 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5094 (VMOVDDUPYrr VR256:$src)>;
5097 let Predicates = [UseSSE3] in {
5098 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5099 (MOVDDUPrm addr:$src)>;
5100 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5101 (MOVDDUPrm addr:$src)>;
5102 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5103 (MOVDDUPrm addr:$src)>;
5104 def : Pat<(X86Movddup (bc_v2f64
5105 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5106 (MOVDDUPrm addr:$src)>;
5109 //===---------------------------------------------------------------------===//
5110 // SSE3 - Move Unaligned Integer
5111 //===---------------------------------------------------------------------===//
5113 let SchedRW = [WriteLoad] in {
5114 let Predicates = [HasAVX] in {
5115 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5116 "vlddqu\t{$src, $dst|$dst, $src}",
5117 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5118 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5119 "vlddqu\t{$src, $dst|$dst, $src}",
5120 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5123 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5124 "lddqu\t{$src, $dst|$dst, $src}",
5125 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5129 //===---------------------------------------------------------------------===//
5130 // SSE3 - Arithmetic
5131 //===---------------------------------------------------------------------===//
5133 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5134 X86MemOperand x86memop, OpndItins itins,
5136 def rr : I<0xD0, MRMSrcReg,
5137 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5139 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5140 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5141 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5142 Sched<[itins.Sched]>;
5143 def rm : I<0xD0, MRMSrcMem,
5144 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5146 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5147 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5148 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5149 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5152 let Predicates = [HasAVX] in {
5153 let ExeDomain = SSEPackedSingle in {
5154 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5155 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5156 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5157 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5159 let ExeDomain = SSEPackedDouble in {
5160 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5161 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5162 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5163 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5166 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5167 let ExeDomain = SSEPackedSingle in
5168 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5169 f128mem, SSE_ALU_F32P>, XD;
5170 let ExeDomain = SSEPackedDouble in
5171 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5172 f128mem, SSE_ALU_F64P>, PD;
5175 //===---------------------------------------------------------------------===//
5176 // SSE3 Instructions
5177 //===---------------------------------------------------------------------===//
5180 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5181 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5182 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5184 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5185 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5186 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5189 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5191 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5192 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5193 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5194 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5196 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5197 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5198 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5200 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5201 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5202 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5205 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5207 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5208 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5209 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5210 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5213 let Predicates = [HasAVX] in {
5214 let ExeDomain = SSEPackedSingle in {
5215 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5216 X86fhadd, 0>, VEX_4V;
5217 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5218 X86fhsub, 0>, VEX_4V;
5219 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5220 X86fhadd, 0>, VEX_4V, VEX_L;
5221 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5222 X86fhsub, 0>, VEX_4V, VEX_L;
5224 let ExeDomain = SSEPackedDouble in {
5225 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5226 X86fhadd, 0>, VEX_4V;
5227 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5228 X86fhsub, 0>, VEX_4V;
5229 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5230 X86fhadd, 0>, VEX_4V, VEX_L;
5231 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5232 X86fhsub, 0>, VEX_4V, VEX_L;
5236 let Constraints = "$src1 = $dst" in {
5237 let ExeDomain = SSEPackedSingle in {
5238 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5239 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5241 let ExeDomain = SSEPackedDouble in {
5242 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5243 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5247 //===---------------------------------------------------------------------===//
5248 // SSSE3 - Packed Absolute Instructions
5249 //===---------------------------------------------------------------------===//
5252 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5253 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5254 Intrinsic IntId128> {
5255 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5257 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5258 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5259 Sched<[WriteVecALU]>;
5261 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5263 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5266 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5267 Sched<[WriteVecALULd]>;
5270 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5271 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5272 Intrinsic IntId256> {
5273 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5275 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5276 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5277 Sched<[WriteVecALU]>;
5279 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5281 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5284 (bitconvert (memopv4i64 addr:$src))))]>,
5285 Sched<[WriteVecALULd]>;
5288 // Helper fragments to match sext vXi1 to vXiY.
5289 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5291 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5292 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5293 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5295 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5296 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5298 let Predicates = [HasAVX] in {
5299 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5300 int_x86_ssse3_pabs_b_128>, VEX;
5301 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5302 int_x86_ssse3_pabs_w_128>, VEX;
5303 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5304 int_x86_ssse3_pabs_d_128>, VEX;
5307 (bc_v2i64 (v16i1sextv16i8)),
5308 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5309 (VPABSBrr128 VR128:$src)>;
5311 (bc_v2i64 (v8i1sextv8i16)),
5312 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5313 (VPABSWrr128 VR128:$src)>;
5315 (bc_v2i64 (v4i1sextv4i32)),
5316 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5317 (VPABSDrr128 VR128:$src)>;
5320 let Predicates = [HasAVX2] in {
5321 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5322 int_x86_avx2_pabs_b>, VEX, VEX_L;
5323 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5324 int_x86_avx2_pabs_w>, VEX, VEX_L;
5325 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5326 int_x86_avx2_pabs_d>, VEX, VEX_L;
5329 (bc_v4i64 (v32i1sextv32i8)),
5330 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5331 (VPABSBrr256 VR256:$src)>;
5333 (bc_v4i64 (v16i1sextv16i16)),
5334 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5335 (VPABSWrr256 VR256:$src)>;
5337 (bc_v4i64 (v8i1sextv8i32)),
5338 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5339 (VPABSDrr256 VR256:$src)>;
5342 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5343 int_x86_ssse3_pabs_b_128>;
5344 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5345 int_x86_ssse3_pabs_w_128>;
5346 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5347 int_x86_ssse3_pabs_d_128>;
5349 let Predicates = [HasSSSE3] in {
5351 (bc_v2i64 (v16i1sextv16i8)),
5352 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5353 (PABSBrr128 VR128:$src)>;
5355 (bc_v2i64 (v8i1sextv8i16)),
5356 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5357 (PABSWrr128 VR128:$src)>;
5359 (bc_v2i64 (v4i1sextv4i32)),
5360 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5361 (PABSDrr128 VR128:$src)>;
5364 //===---------------------------------------------------------------------===//
5365 // SSSE3 - Packed Binary Operator Instructions
5366 //===---------------------------------------------------------------------===//
5368 let Sched = WriteVecALU in {
5369 def SSE_PHADDSUBD : OpndItins<
5370 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5372 def SSE_PHADDSUBSW : OpndItins<
5373 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5375 def SSE_PHADDSUBW : OpndItins<
5376 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5379 let Sched = WriteShuffle in
5380 def SSE_PSHUFB : OpndItins<
5381 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5383 let Sched = WriteVecALU in
5384 def SSE_PSIGN : OpndItins<
5385 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5387 let Sched = WriteVecIMul in
5388 def SSE_PMULHRSW : OpndItins<
5389 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5392 /// SS3I_binop_rm - Simple SSSE3 bin op
5393 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5394 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5395 X86MemOperand x86memop, OpndItins itins,
5397 let isCommutable = 1 in
5398 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5399 (ins RC:$src1, RC:$src2),
5401 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5402 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5403 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5404 Sched<[itins.Sched]>;
5405 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5406 (ins RC:$src1, x86memop:$src2),
5408 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5409 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5411 (OpVT (OpNode RC:$src1,
5412 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5413 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5416 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5417 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5418 Intrinsic IntId128, OpndItins itins,
5420 let isCommutable = 1 in
5421 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5422 (ins VR128:$src1, VR128:$src2),
5424 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5425 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5426 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5427 Sched<[itins.Sched]>;
5428 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5429 (ins VR128:$src1, i128mem:$src2),
5431 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5432 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5434 (IntId128 VR128:$src1,
5435 (bitconvert (memopv2i64 addr:$src2))))]>,
5436 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5439 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5440 Intrinsic IntId256> {
5441 let isCommutable = 1 in
5442 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5443 (ins VR256:$src1, VR256:$src2),
5444 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5445 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>;
5446 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5447 (ins VR256:$src1, i256mem:$src2),
5448 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5450 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>;
5453 let ImmT = NoImm, Predicates = [HasAVX] in {
5454 let isCommutable = 0 in {
5455 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5457 SSE_PHADDSUBW, 0>, VEX_4V;
5458 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5460 SSE_PHADDSUBD, 0>, VEX_4V;
5461 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5463 SSE_PHADDSUBW, 0>, VEX_4V;
5464 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5466 SSE_PHADDSUBD, 0>, VEX_4V;
5467 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5469 SSE_PSIGN, 0>, VEX_4V;
5470 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5472 SSE_PSIGN, 0>, VEX_4V;
5473 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5475 SSE_PSIGN, 0>, VEX_4V;
5476 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5478 SSE_PSHUFB, 0>, VEX_4V;
5479 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5480 int_x86_ssse3_phadd_sw_128,
5481 SSE_PHADDSUBSW, 0>, VEX_4V;
5482 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5483 int_x86_ssse3_phsub_sw_128,
5484 SSE_PHADDSUBSW, 0>, VEX_4V;
5485 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5486 int_x86_ssse3_pmadd_ub_sw_128,
5487 SSE_PMADD, 0>, VEX_4V;
5489 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5490 int_x86_ssse3_pmul_hr_sw_128,
5491 SSE_PMULHRSW, 0>, VEX_4V;
5494 let ImmT = NoImm, Predicates = [HasAVX2] in {
5495 let isCommutable = 0 in {
5496 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5498 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5499 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5501 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5502 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5504 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5505 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5507 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5508 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5510 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5511 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5513 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5514 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5516 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5517 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5519 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5520 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5521 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5522 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5523 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5524 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5525 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5527 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5528 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5531 // None of these have i8 immediate fields.
5532 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5533 let isCommutable = 0 in {
5534 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5535 memopv2i64, i128mem, SSE_PHADDSUBW>;
5536 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5537 memopv2i64, i128mem, SSE_PHADDSUBD>;
5538 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5539 memopv2i64, i128mem, SSE_PHADDSUBW>;
5540 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5541 memopv2i64, i128mem, SSE_PHADDSUBD>;
5542 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5543 memopv2i64, i128mem, SSE_PSIGN>;
5544 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5545 memopv2i64, i128mem, SSE_PSIGN>;
5546 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5547 memopv2i64, i128mem, SSE_PSIGN>;
5548 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5549 memopv2i64, i128mem, SSE_PSHUFB>;
5550 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5551 int_x86_ssse3_phadd_sw_128,
5553 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5554 int_x86_ssse3_phsub_sw_128,
5556 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5557 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5559 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5560 int_x86_ssse3_pmul_hr_sw_128,
5564 //===---------------------------------------------------------------------===//
5565 // SSSE3 - Packed Align Instruction Patterns
5566 //===---------------------------------------------------------------------===//
5568 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5569 let neverHasSideEffects = 1 in {
5570 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5571 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5573 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5575 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5576 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5578 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5579 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5581 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5583 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5584 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5588 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5589 let neverHasSideEffects = 1 in {
5590 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5591 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5593 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5594 []>, Sched<[WriteShuffle]>;
5596 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5597 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5599 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5600 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5604 let Predicates = [HasAVX] in
5605 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5606 let Predicates = [HasAVX2] in
5607 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5608 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5609 defm PALIGN : ssse3_palignr<"palignr">;
5611 let Predicates = [HasAVX2] in {
5612 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5613 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5614 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5615 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5616 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5617 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5618 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5619 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5622 let Predicates = [HasAVX] in {
5623 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5624 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5625 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5626 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5627 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5628 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5629 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5630 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5633 let Predicates = [UseSSSE3] in {
5634 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5635 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5636 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5637 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5638 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5639 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5640 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5641 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5644 //===---------------------------------------------------------------------===//
5645 // SSSE3 - Thread synchronization
5646 //===---------------------------------------------------------------------===//
5648 let SchedRW = [WriteSystem] in {
5649 let usesCustomInserter = 1 in {
5650 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5651 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5652 Requires<[HasSSE3]>;
5655 let Uses = [EAX, ECX, EDX] in
5656 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5657 TB, Requires<[HasSSE3]>;
5658 let Uses = [ECX, EAX] in
5659 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5660 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5661 TB, Requires<[HasSSE3]>;
5664 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5665 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5667 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5668 Requires<[Not64BitMode]>;
5669 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5670 Requires<[In64BitMode]>;
5672 //===----------------------------------------------------------------------===//
5673 // SSE4.1 - Packed Move with Sign/Zero Extend
5674 //===----------------------------------------------------------------------===//
5676 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5677 OpndItins itins = DEFAULT_ITINS> {
5678 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5679 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5680 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>;
5682 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5683 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5685 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5689 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5691 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5692 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5693 [(set VR256:$dst, (IntId VR128:$src))]>;
5695 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5696 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5697 [(set VR256:$dst, (IntId (load addr:$src)))]>;
5700 let Predicates = [HasAVX] in {
5701 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5702 int_x86_sse41_pmovsxbw>, VEX;
5703 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5704 int_x86_sse41_pmovsxwd>, VEX;
5705 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5706 int_x86_sse41_pmovsxdq>, VEX;
5707 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5708 int_x86_sse41_pmovzxbw>, VEX;
5709 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5710 int_x86_sse41_pmovzxwd>, VEX;
5711 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5712 int_x86_sse41_pmovzxdq>, VEX;
5715 let Predicates = [HasAVX2] in {
5716 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5717 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5718 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5719 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5720 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5721 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5722 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5723 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5724 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5725 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5726 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5727 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5730 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw, SSE_INTALU_ITINS_P>;
5731 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd, SSE_INTALU_ITINS_P>;
5732 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq, SSE_INTALU_ITINS_P>;
5733 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw, SSE_INTALU_ITINS_P>;
5734 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd, SSE_INTALU_ITINS_P>;
5735 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq, SSE_INTALU_ITINS_P>;
5737 let Predicates = [HasAVX] in {
5738 // Common patterns involving scalar load.
5739 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5740 (VPMOVSXBWrm addr:$src)>;
5741 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5742 (VPMOVSXBWrm addr:$src)>;
5743 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5744 (VPMOVSXBWrm addr:$src)>;
5746 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5747 (VPMOVSXWDrm addr:$src)>;
5748 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5749 (VPMOVSXWDrm addr:$src)>;
5750 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5751 (VPMOVSXWDrm addr:$src)>;
5753 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5754 (VPMOVSXDQrm addr:$src)>;
5755 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5756 (VPMOVSXDQrm addr:$src)>;
5757 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5758 (VPMOVSXDQrm addr:$src)>;
5760 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5761 (VPMOVZXBWrm addr:$src)>;
5762 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5763 (VPMOVZXBWrm addr:$src)>;
5764 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5765 (VPMOVZXBWrm addr:$src)>;
5767 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5768 (VPMOVZXWDrm addr:$src)>;
5769 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5770 (VPMOVZXWDrm addr:$src)>;
5771 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5772 (VPMOVZXWDrm addr:$src)>;
5774 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5775 (VPMOVZXDQrm addr:$src)>;
5776 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5777 (VPMOVZXDQrm addr:$src)>;
5778 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5779 (VPMOVZXDQrm addr:$src)>;
5782 let Predicates = [UseSSE41] in {
5783 // Common patterns involving scalar load.
5784 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5785 (PMOVSXBWrm addr:$src)>;
5786 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5787 (PMOVSXBWrm addr:$src)>;
5788 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5789 (PMOVSXBWrm addr:$src)>;
5791 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5792 (PMOVSXWDrm addr:$src)>;
5793 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5794 (PMOVSXWDrm addr:$src)>;
5795 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5796 (PMOVSXWDrm addr:$src)>;
5798 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5799 (PMOVSXDQrm addr:$src)>;
5800 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5801 (PMOVSXDQrm addr:$src)>;
5802 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5803 (PMOVSXDQrm addr:$src)>;
5805 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5806 (PMOVZXBWrm addr:$src)>;
5807 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5808 (PMOVZXBWrm addr:$src)>;
5809 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5810 (PMOVZXBWrm addr:$src)>;
5812 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5813 (PMOVZXWDrm addr:$src)>;
5814 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5815 (PMOVZXWDrm addr:$src)>;
5816 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5817 (PMOVZXWDrm addr:$src)>;
5819 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5820 (PMOVZXDQrm addr:$src)>;
5821 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5822 (PMOVZXDQrm addr:$src)>;
5823 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5824 (PMOVZXDQrm addr:$src)>;
5827 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5828 OpndItins itins = DEFAULT_ITINS> {
5829 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5830 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5831 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>;
5833 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5834 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5836 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
5840 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5842 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5844 [(set VR256:$dst, (IntId VR128:$src))]>;
5846 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5849 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>;
5852 let Predicates = [HasAVX] in {
5853 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5855 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5857 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5859 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5863 let Predicates = [HasAVX2] in {
5864 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5865 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5866 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5867 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5868 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5869 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5870 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5871 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5874 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
5875 SSE_INTALU_ITINS_P>;
5876 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
5877 SSE_INTALU_ITINS_P>;
5878 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
5879 SSE_INTALU_ITINS_P>;
5880 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
5881 SSE_INTALU_ITINS_P>;
5883 let Predicates = [HasAVX] in {
5884 // Common patterns involving scalar load
5885 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5886 (VPMOVSXBDrm addr:$src)>;
5887 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5888 (VPMOVSXWQrm addr:$src)>;
5890 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5891 (VPMOVZXBDrm addr:$src)>;
5892 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5893 (VPMOVZXWQrm addr:$src)>;
5896 let Predicates = [UseSSE41] in {
5897 // Common patterns involving scalar load
5898 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5899 (PMOVSXBDrm addr:$src)>;
5900 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5901 (PMOVSXWQrm addr:$src)>;
5903 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5904 (PMOVZXBDrm addr:$src)>;
5905 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5906 (PMOVZXWQrm addr:$src)>;
5909 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5910 OpndItins itins = DEFAULT_ITINS> {
5911 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5912 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5913 [(set VR128:$dst, (IntId VR128:$src))]>;
5915 // Expecting a i16 load any extended to i32 value.
5916 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5917 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5918 [(set VR128:$dst, (IntId (bitconvert
5919 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>;
5922 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5924 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5925 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5926 [(set VR256:$dst, (IntId VR128:$src))]>;
5928 // Expecting a i16 load any extended to i32 value.
5929 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5930 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5931 [(set VR256:$dst, (IntId (bitconvert
5932 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>;
5935 let Predicates = [HasAVX] in {
5936 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5938 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5941 let Predicates = [HasAVX2] in {
5942 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5943 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5944 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5945 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5947 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
5948 SSE_INTALU_ITINS_P>;
5949 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
5950 SSE_INTALU_ITINS_P>;
5952 let Predicates = [HasAVX2] in {
5953 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5954 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5955 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
5957 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5958 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
5960 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5962 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
5963 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5964 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
5965 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5966 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
5967 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5969 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
5970 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5971 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
5972 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5974 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
5975 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5977 def : Pat<(v8i32 (X86vsext (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5978 (VPMOVSXWDYrm addr:$src)>;
5979 def : Pat<(v4i64 (X86vsext (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5980 (VPMOVSXDQYrm addr:$src)>;
5982 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5983 (scalar_to_vector (loadi64 addr:$src))))))),
5984 (VPMOVSXBDYrm addr:$src)>;
5985 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5986 (scalar_to_vector (loadf64 addr:$src))))))),
5987 (VPMOVSXBDYrm addr:$src)>;
5989 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5990 (scalar_to_vector (loadi64 addr:$src))))))),
5991 (VPMOVSXWQYrm addr:$src)>;
5992 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5993 (scalar_to_vector (loadf64 addr:$src))))))),
5994 (VPMOVSXWQYrm addr:$src)>;
5996 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5997 (scalar_to_vector (loadi32 addr:$src))))))),
5998 (VPMOVSXBQYrm addr:$src)>;
6001 let Predicates = [HasAVX] in {
6002 // Common patterns involving scalar load
6003 def : Pat<(int_x86_sse41_pmovsxbq
6004 (bitconvert (v4i32 (X86vzmovl
6005 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6006 (VPMOVSXBQrm addr:$src)>;
6008 def : Pat<(int_x86_sse41_pmovzxbq
6009 (bitconvert (v4i32 (X86vzmovl
6010 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6011 (VPMOVZXBQrm addr:$src)>;
6014 let Predicates = [UseSSE41] in {
6015 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
6016 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
6017 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
6019 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
6020 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
6022 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
6024 // Common patterns involving scalar load
6025 def : Pat<(int_x86_sse41_pmovsxbq
6026 (bitconvert (v4i32 (X86vzmovl
6027 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6028 (PMOVSXBQrm addr:$src)>;
6030 def : Pat<(int_x86_sse41_pmovzxbq
6031 (bitconvert (v4i32 (X86vzmovl
6032 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6033 (PMOVZXBQrm addr:$src)>;
6035 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6036 (scalar_to_vector (loadi64 addr:$src))))))),
6037 (PMOVSXWDrm addr:$src)>;
6038 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6039 (scalar_to_vector (loadf64 addr:$src))))))),
6040 (PMOVSXWDrm addr:$src)>;
6041 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6042 (scalar_to_vector (loadi32 addr:$src))))))),
6043 (PMOVSXBDrm addr:$src)>;
6044 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6045 (scalar_to_vector (loadi32 addr:$src))))))),
6046 (PMOVSXWQrm addr:$src)>;
6047 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6048 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6049 (PMOVSXBQrm addr:$src)>;
6050 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6051 (scalar_to_vector (loadi64 addr:$src))))))),
6052 (PMOVSXDQrm addr:$src)>;
6053 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6054 (scalar_to_vector (loadf64 addr:$src))))))),
6055 (PMOVSXDQrm addr:$src)>;
6056 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6057 (scalar_to_vector (loadi64 addr:$src))))))),
6058 (PMOVSXBWrm addr:$src)>;
6059 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6060 (scalar_to_vector (loadf64 addr:$src))))))),
6061 (PMOVSXBWrm addr:$src)>;
6064 let Predicates = [HasAVX2] in {
6065 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
6066 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
6067 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
6069 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
6070 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
6072 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
6074 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
6075 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6076 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
6077 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6078 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
6079 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6081 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
6082 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6083 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
6084 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6086 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
6087 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6090 let Predicates = [HasAVX] in {
6091 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
6092 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
6093 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
6095 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
6096 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
6098 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
6100 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6101 (VPMOVZXBWrm addr:$src)>;
6102 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6103 (VPMOVZXBWrm addr:$src)>;
6104 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6105 (VPMOVZXBDrm addr:$src)>;
6106 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6107 (VPMOVZXBQrm addr:$src)>;
6109 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6110 (VPMOVZXWDrm addr:$src)>;
6111 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6112 (VPMOVZXWDrm addr:$src)>;
6113 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6114 (VPMOVZXWQrm addr:$src)>;
6116 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6117 (VPMOVZXDQrm addr:$src)>;
6118 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6119 (VPMOVZXDQrm addr:$src)>;
6120 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6121 (VPMOVZXDQrm addr:$src)>;
6123 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
6124 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
6125 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
6127 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
6128 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
6130 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
6132 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6133 (scalar_to_vector (loadi64 addr:$src))))))),
6134 (VPMOVSXWDrm addr:$src)>;
6135 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6136 (scalar_to_vector (loadi64 addr:$src))))))),
6137 (VPMOVSXDQrm addr:$src)>;
6138 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6139 (scalar_to_vector (loadf64 addr:$src))))))),
6140 (VPMOVSXWDrm addr:$src)>;
6141 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6142 (scalar_to_vector (loadf64 addr:$src))))))),
6143 (VPMOVSXDQrm addr:$src)>;
6144 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6145 (scalar_to_vector (loadi64 addr:$src))))))),
6146 (VPMOVSXBWrm addr:$src)>;
6147 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6148 (scalar_to_vector (loadf64 addr:$src))))))),
6149 (VPMOVSXBWrm addr:$src)>;
6151 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6152 (scalar_to_vector (loadi32 addr:$src))))))),
6153 (VPMOVSXBDrm addr:$src)>;
6154 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6155 (scalar_to_vector (loadi32 addr:$src))))))),
6156 (VPMOVSXWQrm addr:$src)>;
6157 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6158 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6159 (VPMOVSXBQrm addr:$src)>;
6162 let Predicates = [UseSSE41] in {
6163 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6164 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6165 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6167 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6168 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6170 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6172 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6173 (PMOVZXBWrm addr:$src)>;
6174 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6175 (PMOVZXBWrm addr:$src)>;
6176 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6177 (PMOVZXBDrm addr:$src)>;
6178 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6179 (PMOVZXBQrm addr:$src)>;
6181 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6182 (PMOVZXWDrm addr:$src)>;
6183 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6184 (PMOVZXWDrm addr:$src)>;
6185 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6186 (PMOVZXWQrm addr:$src)>;
6188 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6189 (PMOVZXDQrm addr:$src)>;
6190 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6191 (PMOVZXDQrm addr:$src)>;
6192 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6193 (PMOVZXDQrm addr:$src)>;
6196 //===----------------------------------------------------------------------===//
6197 // SSE4.1 - Extract Instructions
6198 //===----------------------------------------------------------------------===//
6200 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6201 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6202 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6203 (ins VR128:$src1, i32i8imm:$src2),
6204 !strconcat(OpcodeStr,
6205 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6206 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6208 let neverHasSideEffects = 1, mayStore = 1 in
6209 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6210 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6211 !strconcat(OpcodeStr,
6212 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6213 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6214 imm:$src2)))), addr:$dst)]>;
6217 let Predicates = [HasAVX] in
6218 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6220 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6223 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6224 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6225 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6226 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6227 (ins VR128:$src1, i32i8imm:$src2),
6228 !strconcat(OpcodeStr,
6229 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6232 let neverHasSideEffects = 1, mayStore = 1 in
6233 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6234 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6235 !strconcat(OpcodeStr,
6236 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6237 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6238 imm:$src2)))), addr:$dst)]>;
6241 let Predicates = [HasAVX] in
6242 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6244 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6247 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6248 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6249 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6250 (ins VR128:$src1, i32i8imm:$src2),
6251 !strconcat(OpcodeStr,
6252 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6254 (extractelt (v4i32 VR128:$src1), imm:$src2))]>;
6255 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6256 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6257 !strconcat(OpcodeStr,
6258 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6259 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6263 let Predicates = [HasAVX] in
6264 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6266 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6268 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6269 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6270 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6271 (ins VR128:$src1, i32i8imm:$src2),
6272 !strconcat(OpcodeStr,
6273 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6275 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, REX_W;
6276 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6277 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6278 !strconcat(OpcodeStr,
6279 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6280 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6281 addr:$dst)]>, REX_W;
6284 let Predicates = [HasAVX] in
6285 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6287 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6289 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6291 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6292 OpndItins itins = DEFAULT_ITINS> {
6293 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6294 (ins VR128:$src1, i32i8imm:$src2),
6295 !strconcat(OpcodeStr,
6296 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6297 [(set GR32orGR64:$dst,
6298 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6300 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6301 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6302 !strconcat(OpcodeStr,
6303 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6304 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6305 addr:$dst)], itins.rm>;
6308 let ExeDomain = SSEPackedSingle in {
6309 let Predicates = [UseAVX] in
6310 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6311 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6314 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6315 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6318 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6320 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6323 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6324 Requires<[UseSSE41]>;
6326 //===----------------------------------------------------------------------===//
6327 // SSE4.1 - Insert Instructions
6328 //===----------------------------------------------------------------------===//
6330 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6331 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6332 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6334 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6336 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6338 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>;
6339 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6340 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6342 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6344 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6346 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6350 let Predicates = [HasAVX] in
6351 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6352 let Constraints = "$src1 = $dst" in
6353 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6355 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6356 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6357 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6359 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6361 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6363 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>;
6364 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6365 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6367 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6369 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6371 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6375 let Predicates = [HasAVX] in
6376 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6377 let Constraints = "$src1 = $dst" in
6378 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6380 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6381 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6382 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6384 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6386 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6388 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>;
6389 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6390 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6392 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6394 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6396 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6400 let Predicates = [HasAVX] in
6401 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6402 let Constraints = "$src1 = $dst" in
6403 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6405 // insertps has a few different modes, there's the first two here below which
6406 // are optimized inserts that won't zero arbitrary elements in the destination
6407 // vector. The next one matches the intrinsic and could zero arbitrary elements
6408 // in the target vector.
6409 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6410 OpndItins itins = DEFAULT_ITINS> {
6411 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6412 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6414 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6416 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6418 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>;
6419 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6420 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6422 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6424 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6426 (X86insrtps VR128:$src1,
6427 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6428 imm:$src3))], itins.rm>;
6431 let ExeDomain = SSEPackedSingle in {
6432 let Predicates = [UseAVX] in
6433 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6434 let Constraints = "$src1 = $dst" in
6435 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6438 //===----------------------------------------------------------------------===//
6439 // SSE4.1 - Round Instructions
6440 //===----------------------------------------------------------------------===//
6442 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6443 X86MemOperand x86memop, RegisterClass RC,
6444 PatFrag mem_frag32, PatFrag mem_frag64,
6445 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6446 let ExeDomain = SSEPackedSingle in {
6447 // Intrinsic operation, reg.
6448 // Vector intrinsic operation, reg
6449 def PSr : SS4AIi8<opcps, MRMSrcReg,
6450 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6451 !strconcat(OpcodeStr,
6452 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6453 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6454 IIC_SSE_ROUNDPS_REG>;
6456 // Vector intrinsic operation, mem
6457 def PSm : SS4AIi8<opcps, MRMSrcMem,
6458 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6459 !strconcat(OpcodeStr,
6460 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6462 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6463 IIC_SSE_ROUNDPS_MEM>;
6464 } // ExeDomain = SSEPackedSingle
6466 let ExeDomain = SSEPackedDouble in {
6467 // Vector intrinsic operation, reg
6468 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6469 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6470 !strconcat(OpcodeStr,
6471 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6472 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6473 IIC_SSE_ROUNDPS_REG>;
6475 // Vector intrinsic operation, mem
6476 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6477 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6478 !strconcat(OpcodeStr,
6479 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6481 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6482 IIC_SSE_ROUNDPS_REG>;
6483 } // ExeDomain = SSEPackedDouble
6486 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6489 Intrinsic F64Int, bit Is2Addr = 1> {
6490 let ExeDomain = GenericDomain in {
6492 let hasSideEffects = 0 in
6493 def SSr : SS4AIi8<opcss, MRMSrcReg,
6494 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6496 !strconcat(OpcodeStr,
6497 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6498 !strconcat(OpcodeStr,
6499 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6502 // Intrinsic operation, reg.
6503 let isCodeGenOnly = 1 in
6504 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6505 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6507 !strconcat(OpcodeStr,
6508 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6509 !strconcat(OpcodeStr,
6510 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6511 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>;
6513 // Intrinsic operation, mem.
6514 def SSm : SS4AIi8<opcss, MRMSrcMem,
6515 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6517 !strconcat(OpcodeStr,
6518 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6519 !strconcat(OpcodeStr,
6520 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6522 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>;
6525 let hasSideEffects = 0 in
6526 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6527 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6529 !strconcat(OpcodeStr,
6530 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6531 !strconcat(OpcodeStr,
6532 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6535 // Intrinsic operation, reg.
6536 let isCodeGenOnly = 1 in
6537 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6538 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6540 !strconcat(OpcodeStr,
6541 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6542 !strconcat(OpcodeStr,
6543 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6544 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>;
6546 // Intrinsic operation, mem.
6547 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6548 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6550 !strconcat(OpcodeStr,
6551 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6552 !strconcat(OpcodeStr,
6553 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6555 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>;
6556 } // ExeDomain = GenericDomain
6559 // FP round - roundss, roundps, roundsd, roundpd
6560 let Predicates = [HasAVX] in {
6562 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6563 loadv4f32, loadv2f64,
6564 int_x86_sse41_round_ps,
6565 int_x86_sse41_round_pd>, VEX;
6566 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6567 loadv8f32, loadv4f64,
6568 int_x86_avx_round_ps_256,
6569 int_x86_avx_round_pd_256>, VEX, VEX_L;
6570 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6571 int_x86_sse41_round_ss,
6572 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6574 def : Pat<(ffloor FR32:$src),
6575 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6576 def : Pat<(f64 (ffloor FR64:$src)),
6577 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6578 def : Pat<(f32 (fnearbyint FR32:$src)),
6579 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6580 def : Pat<(f64 (fnearbyint FR64:$src)),
6581 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6582 def : Pat<(f32 (fceil FR32:$src)),
6583 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6584 def : Pat<(f64 (fceil FR64:$src)),
6585 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6586 def : Pat<(f32 (frint FR32:$src)),
6587 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6588 def : Pat<(f64 (frint FR64:$src)),
6589 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6590 def : Pat<(f32 (ftrunc FR32:$src)),
6591 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6592 def : Pat<(f64 (ftrunc FR64:$src)),
6593 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6595 def : Pat<(v4f32 (ffloor VR128:$src)),
6596 (VROUNDPSr VR128:$src, (i32 0x1))>;
6597 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6598 (VROUNDPSr VR128:$src, (i32 0xC))>;
6599 def : Pat<(v4f32 (fceil VR128:$src)),
6600 (VROUNDPSr VR128:$src, (i32 0x2))>;
6601 def : Pat<(v4f32 (frint VR128:$src)),
6602 (VROUNDPSr VR128:$src, (i32 0x4))>;
6603 def : Pat<(v4f32 (ftrunc VR128:$src)),
6604 (VROUNDPSr VR128:$src, (i32 0x3))>;
6606 def : Pat<(v2f64 (ffloor VR128:$src)),
6607 (VROUNDPDr VR128:$src, (i32 0x1))>;
6608 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6609 (VROUNDPDr VR128:$src, (i32 0xC))>;
6610 def : Pat<(v2f64 (fceil VR128:$src)),
6611 (VROUNDPDr VR128:$src, (i32 0x2))>;
6612 def : Pat<(v2f64 (frint VR128:$src)),
6613 (VROUNDPDr VR128:$src, (i32 0x4))>;
6614 def : Pat<(v2f64 (ftrunc VR128:$src)),
6615 (VROUNDPDr VR128:$src, (i32 0x3))>;
6617 def : Pat<(v8f32 (ffloor VR256:$src)),
6618 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6619 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6620 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6621 def : Pat<(v8f32 (fceil VR256:$src)),
6622 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6623 def : Pat<(v8f32 (frint VR256:$src)),
6624 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6625 def : Pat<(v8f32 (ftrunc VR256:$src)),
6626 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6628 def : Pat<(v4f64 (ffloor VR256:$src)),
6629 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6630 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6631 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6632 def : Pat<(v4f64 (fceil VR256:$src)),
6633 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6634 def : Pat<(v4f64 (frint VR256:$src)),
6635 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6636 def : Pat<(v4f64 (ftrunc VR256:$src)),
6637 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6640 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6641 memopv4f32, memopv2f64,
6642 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6643 let Constraints = "$src1 = $dst" in
6644 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6645 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6647 let Predicates = [UseSSE41] in {
6648 def : Pat<(ffloor FR32:$src),
6649 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6650 def : Pat<(f64 (ffloor FR64:$src)),
6651 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6652 def : Pat<(f32 (fnearbyint FR32:$src)),
6653 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6654 def : Pat<(f64 (fnearbyint FR64:$src)),
6655 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6656 def : Pat<(f32 (fceil FR32:$src)),
6657 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6658 def : Pat<(f64 (fceil FR64:$src)),
6659 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6660 def : Pat<(f32 (frint FR32:$src)),
6661 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6662 def : Pat<(f64 (frint FR64:$src)),
6663 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6664 def : Pat<(f32 (ftrunc FR32:$src)),
6665 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6666 def : Pat<(f64 (ftrunc FR64:$src)),
6667 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6669 def : Pat<(v4f32 (ffloor VR128:$src)),
6670 (ROUNDPSr VR128:$src, (i32 0x1))>;
6671 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6672 (ROUNDPSr VR128:$src, (i32 0xC))>;
6673 def : Pat<(v4f32 (fceil VR128:$src)),
6674 (ROUNDPSr VR128:$src, (i32 0x2))>;
6675 def : Pat<(v4f32 (frint VR128:$src)),
6676 (ROUNDPSr VR128:$src, (i32 0x4))>;
6677 def : Pat<(v4f32 (ftrunc VR128:$src)),
6678 (ROUNDPSr VR128:$src, (i32 0x3))>;
6680 def : Pat<(v2f64 (ffloor VR128:$src)),
6681 (ROUNDPDr VR128:$src, (i32 0x1))>;
6682 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6683 (ROUNDPDr VR128:$src, (i32 0xC))>;
6684 def : Pat<(v2f64 (fceil VR128:$src)),
6685 (ROUNDPDr VR128:$src, (i32 0x2))>;
6686 def : Pat<(v2f64 (frint VR128:$src)),
6687 (ROUNDPDr VR128:$src, (i32 0x4))>;
6688 def : Pat<(v2f64 (ftrunc VR128:$src)),
6689 (ROUNDPDr VR128:$src, (i32 0x3))>;
6692 //===----------------------------------------------------------------------===//
6693 // SSE4.1 - Packed Bit Test
6694 //===----------------------------------------------------------------------===//
6696 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6697 // the intel intrinsic that corresponds to this.
6698 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6699 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6700 "vptest\t{$src2, $src1|$src1, $src2}",
6701 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6703 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6704 "vptest\t{$src2, $src1|$src1, $src2}",
6705 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6708 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6709 "vptest\t{$src2, $src1|$src1, $src2}",
6710 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6712 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6713 "vptest\t{$src2, $src1|$src1, $src2}",
6714 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6718 let Defs = [EFLAGS] in {
6719 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6720 "ptest\t{$src2, $src1|$src1, $src2}",
6721 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>;
6722 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6723 "ptest\t{$src2, $src1|$src1, $src2}",
6724 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>;
6727 // The bit test instructions below are AVX only
6728 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6729 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6730 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6731 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6732 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, VEX;
6733 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6734 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6735 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>, VEX;
6738 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6739 let ExeDomain = SSEPackedSingle in {
6740 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6741 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6744 let ExeDomain = SSEPackedDouble in {
6745 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6746 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6751 //===----------------------------------------------------------------------===//
6752 // SSE4.1 - Misc Instructions
6753 //===----------------------------------------------------------------------===//
6755 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6756 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6757 "popcnt{w}\t{$src, $dst|$dst, $src}",
6758 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6761 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6762 "popcnt{w}\t{$src, $dst|$dst, $src}",
6763 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6764 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize16, XS;
6766 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6767 "popcnt{l}\t{$src, $dst|$dst, $src}",
6768 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6771 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6772 "popcnt{l}\t{$src, $dst|$dst, $src}",
6773 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6774 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6776 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6777 "popcnt{q}\t{$src, $dst|$dst, $src}",
6778 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6781 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6782 "popcnt{q}\t{$src, $dst|$dst, $src}",
6783 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6784 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6789 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6790 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6791 Intrinsic IntId128> {
6792 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6794 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6795 [(set VR128:$dst, (IntId128 VR128:$src))]>;
6796 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6800 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>;
6803 let Predicates = [HasAVX] in
6804 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6805 int_x86_sse41_phminposuw>, VEX;
6806 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6807 int_x86_sse41_phminposuw>;
6809 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6810 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6811 Intrinsic IntId128, bit Is2Addr = 1,
6812 OpndItins itins = DEFAULT_ITINS> {
6813 let isCommutable = 1 in
6814 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6815 (ins VR128:$src1, VR128:$src2),
6817 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6818 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6819 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
6821 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6822 (ins VR128:$src1, i128mem:$src2),
6824 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6827 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
6831 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6832 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6833 Intrinsic IntId256> {
6834 let isCommutable = 1 in
6835 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6836 (ins VR256:$src1, VR256:$src2),
6837 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6838 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>;
6839 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6840 (ins VR256:$src1, i256mem:$src2),
6841 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6843 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>;
6847 /// SS48I_binop_rm - Simple SSE41 binary operator.
6848 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6849 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6850 X86MemOperand x86memop, bit Is2Addr = 1,
6851 OpndItins itins = DEFAULT_ITINS> {
6852 let isCommutable = 1 in
6853 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6854 (ins RC:$src1, RC:$src2),
6856 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6857 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6858 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
6859 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6860 (ins RC:$src1, x86memop:$src2),
6862 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6863 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6865 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>;
6868 let Predicates = [HasAVX] in {
6869 let isCommutable = 0 in
6870 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6872 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6873 loadv2i64, i128mem, 0>, VEX_4V;
6874 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6875 loadv2i64, i128mem, 0>, VEX_4V;
6876 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6877 loadv2i64, i128mem, 0>, VEX_4V;
6878 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6879 loadv2i64, i128mem, 0>, VEX_4V;
6880 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6881 loadv2i64, i128mem, 0>, VEX_4V;
6882 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6883 loadv2i64, i128mem, 0>, VEX_4V;
6884 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6885 loadv2i64, i128mem, 0>, VEX_4V;
6886 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6887 loadv2i64, i128mem, 0>, VEX_4V;
6888 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6892 let Predicates = [HasAVX2] in {
6893 let isCommutable = 0 in
6894 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6895 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6896 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6897 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6898 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6899 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6900 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6901 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6902 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6903 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6904 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6905 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6906 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6907 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6908 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6909 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6910 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6911 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6912 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6913 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6916 let Constraints = "$src1 = $dst" in {
6917 let isCommutable = 0 in
6918 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6919 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6920 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6921 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6922 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6923 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6924 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6925 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6926 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6927 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6928 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6929 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6930 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6931 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6932 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6933 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6934 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6935 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq,
6936 1, SSE_INTMUL_ITINS_P>;
6939 let Predicates = [HasAVX] in {
6940 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6941 memopv2i64, i128mem, 0>, VEX_4V;
6942 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6943 memopv2i64, i128mem, 0>, VEX_4V;
6945 let Predicates = [HasAVX2] in {
6946 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6947 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6948 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6949 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6952 let Constraints = "$src1 = $dst" in {
6953 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6954 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6955 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6956 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6959 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6960 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6961 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6962 X86MemOperand x86memop, bit Is2Addr = 1,
6963 OpndItins itins = DEFAULT_ITINS> {
6964 let isCommutable = 1 in
6965 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6966 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6968 !strconcat(OpcodeStr,
6969 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6970 !strconcat(OpcodeStr,
6971 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6972 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>;
6973 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6974 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6976 !strconcat(OpcodeStr,
6977 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6978 !strconcat(OpcodeStr,
6979 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6982 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>;
6985 let Predicates = [HasAVX] in {
6986 let isCommutable = 0 in {
6987 let ExeDomain = SSEPackedSingle in {
6988 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6989 VR128, loadv4f32, f128mem, 0>, VEX_4V;
6990 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6991 int_x86_avx_blend_ps_256, VR256, loadv8f32,
6992 f256mem, 0>, VEX_4V, VEX_L;
6994 let ExeDomain = SSEPackedDouble in {
6995 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6996 VR128, loadv2f64, f128mem, 0>, VEX_4V;
6997 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6998 int_x86_avx_blend_pd_256,VR256, loadv4f64,
6999 f256mem, 0>, VEX_4V, VEX_L;
7001 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7002 VR128, loadv2i64, i128mem, 0>, VEX_4V;
7003 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7004 VR128, loadv2i64, i128mem, 0>, VEX_4V;
7006 let ExeDomain = SSEPackedSingle in
7007 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7008 VR128, loadv4f32, f128mem, 0>, VEX_4V;
7009 let ExeDomain = SSEPackedDouble in
7010 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7011 VR128, loadv2f64, f128mem, 0>, VEX_4V;
7012 let ExeDomain = SSEPackedSingle in
7013 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7014 VR256, loadv8f32, i256mem, 0>, VEX_4V, VEX_L;
7017 let Predicates = [HasAVX2] in {
7018 let isCommutable = 0 in {
7019 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7020 VR256, loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7021 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7022 VR256, loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7026 let Constraints = "$src1 = $dst" in {
7027 let isCommutable = 0 in {
7028 let ExeDomain = SSEPackedSingle in
7029 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7030 VR128, memopv4f32, f128mem,
7031 1, SSE_INTALU_ITINS_P>;
7032 let ExeDomain = SSEPackedDouble in
7033 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7034 VR128, memopv2f64, f128mem,
7035 1, SSE_INTALU_ITINS_P>;
7036 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7037 VR128, memopv2i64, i128mem,
7038 1, SSE_INTALU_ITINS_P>;
7039 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7040 VR128, memopv2i64, i128mem,
7041 1, SSE_INTMUL_ITINS_P>;
7043 let ExeDomain = SSEPackedSingle in
7044 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7045 VR128, memopv4f32, f128mem, 1,
7047 let ExeDomain = SSEPackedDouble in
7048 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7049 VR128, memopv2f64, f128mem, 1,
7053 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7054 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7055 RegisterClass RC, X86MemOperand x86memop,
7056 PatFrag mem_frag, Intrinsic IntId> {
7057 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7058 (ins RC:$src1, RC:$src2, RC:$src3),
7059 !strconcat(OpcodeStr,
7060 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7061 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7062 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM;
7064 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7065 (ins RC:$src1, x86memop:$src2, RC:$src3),
7066 !strconcat(OpcodeStr,
7067 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7069 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7071 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM;
7074 let Predicates = [HasAVX] in {
7075 let ExeDomain = SSEPackedDouble in {
7076 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7077 loadv2f64, int_x86_sse41_blendvpd>;
7078 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7079 loadv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
7080 } // ExeDomain = SSEPackedDouble
7081 let ExeDomain = SSEPackedSingle in {
7082 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7083 loadv4f32, int_x86_sse41_blendvps>;
7084 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7085 loadv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
7086 } // ExeDomain = SSEPackedSingle
7087 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7088 loadv2i64, int_x86_sse41_pblendvb>;
7091 let Predicates = [HasAVX2] in {
7092 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7093 loadv4i64, int_x86_avx2_pblendvb>, VEX_L;
7096 let Predicates = [HasAVX] in {
7097 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7098 (v16i8 VR128:$src2))),
7099 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7100 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7101 (v4i32 VR128:$src2))),
7102 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7103 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7104 (v4f32 VR128:$src2))),
7105 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7106 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7107 (v2i64 VR128:$src2))),
7108 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7109 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7110 (v2f64 VR128:$src2))),
7111 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7112 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7113 (v8i32 VR256:$src2))),
7114 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7115 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7116 (v8f32 VR256:$src2))),
7117 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7118 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7119 (v4i64 VR256:$src2))),
7120 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7121 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7122 (v4f64 VR256:$src2))),
7123 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7125 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7127 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7128 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7130 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7132 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7134 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7135 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7137 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7138 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7140 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7143 let Predicates = [HasAVX2] in {
7144 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7145 (v32i8 VR256:$src2))),
7146 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7147 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7149 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7152 /// SS41I_ternary_int - SSE 4.1 ternary operator
7153 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7154 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7155 X86MemOperand x86memop, Intrinsic IntId,
7156 OpndItins itins = DEFAULT_ITINS> {
7157 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7158 (ins VR128:$src1, VR128:$src2),
7159 !strconcat(OpcodeStr,
7160 "\t{$src2, $dst|$dst, $src2}"),
7161 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7164 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7165 (ins VR128:$src1, x86memop:$src2),
7166 !strconcat(OpcodeStr,
7167 "\t{$src2, $dst|$dst, $src2}"),
7170 (bitconvert (mem_frag addr:$src2)), XMM0))],
7175 let ExeDomain = SSEPackedDouble in
7176 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7177 int_x86_sse41_blendvpd>;
7178 let ExeDomain = SSEPackedSingle in
7179 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7180 int_x86_sse41_blendvps>;
7181 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7182 int_x86_sse41_pblendvb>;
7184 // Aliases with the implicit xmm0 argument
7185 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7186 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7187 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7188 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7189 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7190 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7191 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7192 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7193 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7194 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7195 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7196 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7198 let Predicates = [UseSSE41] in {
7199 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7200 (v16i8 VR128:$src2))),
7201 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7202 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7203 (v4i32 VR128:$src2))),
7204 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7205 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7206 (v4f32 VR128:$src2))),
7207 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7208 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7209 (v2i64 VR128:$src2))),
7210 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7211 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7212 (v2f64 VR128:$src2))),
7213 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7215 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7217 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7218 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7220 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7221 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7223 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7227 let Predicates = [HasAVX] in
7228 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7229 "vmovntdqa\t{$src, $dst|$dst, $src}",
7230 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7232 let Predicates = [HasAVX2] in
7233 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7234 "vmovntdqa\t{$src, $dst|$dst, $src}",
7235 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7237 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7238 "movntdqa\t{$src, $dst|$dst, $src}",
7239 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7241 //===----------------------------------------------------------------------===//
7242 // SSE4.2 - Compare Instructions
7243 //===----------------------------------------------------------------------===//
7245 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7246 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7247 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7248 X86MemOperand x86memop, bit Is2Addr = 1> {
7249 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7250 (ins RC:$src1, RC:$src2),
7252 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7253 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7254 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7255 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7256 (ins RC:$src1, x86memop:$src2),
7258 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7259 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7261 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7264 let Predicates = [HasAVX] in
7265 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7266 loadv2i64, i128mem, 0>, VEX_4V;
7268 let Predicates = [HasAVX2] in
7269 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7270 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7272 let Constraints = "$src1 = $dst" in
7273 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7274 memopv2i64, i128mem>;
7276 //===----------------------------------------------------------------------===//
7277 // SSE4.2 - String/text Processing Instructions
7278 //===----------------------------------------------------------------------===//
7280 // Packed Compare Implicit Length Strings, Return Mask
7281 multiclass pseudo_pcmpistrm<string asm> {
7282 def REG : PseudoI<(outs VR128:$dst),
7283 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7284 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7286 def MEM : PseudoI<(outs VR128:$dst),
7287 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7288 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7289 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7292 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7293 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7294 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7297 multiclass pcmpistrm_SS42AI<string asm> {
7298 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7299 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7300 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7303 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7304 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7305 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7309 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7310 let Predicates = [HasAVX] in
7311 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7312 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7315 // Packed Compare Explicit Length Strings, Return Mask
7316 multiclass pseudo_pcmpestrm<string asm> {
7317 def REG : PseudoI<(outs VR128:$dst),
7318 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7319 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7320 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7321 def MEM : PseudoI<(outs VR128:$dst),
7322 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7323 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7324 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7327 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7328 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7329 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7332 multiclass SS42AI_pcmpestrm<string asm> {
7333 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7334 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7335 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7338 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7339 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7340 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7344 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7345 let Predicates = [HasAVX] in
7346 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7347 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7350 // Packed Compare Implicit Length Strings, Return Index
7351 multiclass pseudo_pcmpistri<string asm> {
7352 def REG : PseudoI<(outs GR32:$dst),
7353 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7354 [(set GR32:$dst, EFLAGS,
7355 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7356 def MEM : PseudoI<(outs GR32:$dst),
7357 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7358 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7359 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7362 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7363 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7364 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7367 multiclass SS42AI_pcmpistri<string asm> {
7368 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7369 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7370 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7373 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7374 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7375 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7379 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7380 let Predicates = [HasAVX] in
7381 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7382 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7385 // Packed Compare Explicit Length Strings, Return Index
7386 multiclass pseudo_pcmpestri<string asm> {
7387 def REG : PseudoI<(outs GR32:$dst),
7388 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7389 [(set GR32:$dst, EFLAGS,
7390 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7391 def MEM : PseudoI<(outs GR32:$dst),
7392 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7393 [(set GR32:$dst, EFLAGS,
7394 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7398 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7399 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7400 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7403 multiclass SS42AI_pcmpestri<string asm> {
7404 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7405 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7406 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7409 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7410 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7411 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7415 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7416 let Predicates = [HasAVX] in
7417 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7418 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7421 //===----------------------------------------------------------------------===//
7422 // SSE4.2 - CRC Instructions
7423 //===----------------------------------------------------------------------===//
7425 // No CRC instructions have AVX equivalents
7427 // crc intrinsic instruction
7428 // This set of instructions are only rm, the only difference is the size
7430 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7431 RegisterClass RCIn, SDPatternOperator Int> :
7432 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7433 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7434 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>;
7436 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7437 X86MemOperand x86memop, SDPatternOperator Int> :
7438 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7439 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7440 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7443 let Constraints = "$src1 = $dst" in {
7444 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7445 int_x86_sse42_crc32_32_8>;
7446 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7447 int_x86_sse42_crc32_32_8>;
7448 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7449 int_x86_sse42_crc32_32_16>, OpSize16;
7450 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7451 int_x86_sse42_crc32_32_16>, OpSize16;
7452 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7453 int_x86_sse42_crc32_32_32>, OpSize32;
7454 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7455 int_x86_sse42_crc32_32_32>, OpSize32;
7456 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7457 int_x86_sse42_crc32_64_64>, REX_W;
7458 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7459 int_x86_sse42_crc32_64_64>, REX_W;
7460 let hasSideEffects = 0 in {
7462 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7464 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7469 //===----------------------------------------------------------------------===//
7470 // SHA-NI Instructions
7471 //===----------------------------------------------------------------------===//
7473 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7475 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7476 (ins VR128:$src1, VR128:$src2),
7477 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7479 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7480 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7482 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7483 (ins VR128:$src1, i128mem:$src2),
7484 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7486 (set VR128:$dst, (IntId VR128:$src1,
7487 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7488 (set VR128:$dst, (IntId VR128:$src1,
7489 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7492 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7493 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7494 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7495 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7497 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7498 (i8 imm:$src3)))]>, TA;
7499 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7500 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7501 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7503 (int_x86_sha1rnds4 VR128:$src1,
7504 (bc_v4i32 (memopv2i64 addr:$src2)),
7505 (i8 imm:$src3)))]>, TA;
7507 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7508 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7509 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7512 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7514 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7515 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7518 // Aliases with explicit %xmm0
7519 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7520 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7521 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7522 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7524 //===----------------------------------------------------------------------===//
7525 // AES-NI Instructions
7526 //===----------------------------------------------------------------------===//
7528 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7529 Intrinsic IntId128, bit Is2Addr = 1> {
7530 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7531 (ins VR128:$src1, VR128:$src2),
7533 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7534 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7535 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>;
7536 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7537 (ins VR128:$src1, i128mem:$src2),
7539 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7540 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7542 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>;
7545 // Perform One Round of an AES Encryption/Decryption Flow
7546 let Predicates = [HasAVX, HasAES] in {
7547 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7548 int_x86_aesni_aesenc, 0>, VEX_4V;
7549 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7550 int_x86_aesni_aesenclast, 0>, VEX_4V;
7551 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7552 int_x86_aesni_aesdec, 0>, VEX_4V;
7553 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7554 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7557 let Constraints = "$src1 = $dst" in {
7558 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7559 int_x86_aesni_aesenc>;
7560 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7561 int_x86_aesni_aesenclast>;
7562 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7563 int_x86_aesni_aesdec>;
7564 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7565 int_x86_aesni_aesdeclast>;
7568 // Perform the AES InvMixColumn Transformation
7569 let Predicates = [HasAVX, HasAES] in {
7570 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7572 "vaesimc\t{$src1, $dst|$dst, $src1}",
7574 (int_x86_aesni_aesimc VR128:$src1))]>,
7576 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7577 (ins i128mem:$src1),
7578 "vaesimc\t{$src1, $dst|$dst, $src1}",
7579 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7582 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7584 "aesimc\t{$src1, $dst|$dst, $src1}",
7586 (int_x86_aesni_aesimc VR128:$src1))]>;
7587 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7588 (ins i128mem:$src1),
7589 "aesimc\t{$src1, $dst|$dst, $src1}",
7590 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>;
7592 // AES Round Key Generation Assist
7593 let Predicates = [HasAVX, HasAES] in {
7594 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7595 (ins VR128:$src1, i8imm:$src2),
7596 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7598 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7600 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7601 (ins i128mem:$src1, i8imm:$src2),
7602 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7604 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7607 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7608 (ins VR128:$src1, i8imm:$src2),
7609 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7611 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>;
7612 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7613 (ins i128mem:$src1, i8imm:$src2),
7614 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7616 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>;
7618 //===----------------------------------------------------------------------===//
7619 // PCLMUL Instructions
7620 //===----------------------------------------------------------------------===//
7622 // AVX carry-less Multiplication instructions
7623 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7624 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7625 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7627 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7629 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7630 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7631 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7632 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7633 (loadv2i64 addr:$src2), imm:$src3))]>;
7635 // Carry-less Multiplication instructions
7636 let Constraints = "$src1 = $dst" in {
7637 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7638 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7639 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7641 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7642 IIC_SSE_PCLMULQDQ_RR>;
7644 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7645 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7646 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7647 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7648 (memopv2i64 addr:$src2), imm:$src3))],
7649 IIC_SSE_PCLMULQDQ_RM>;
7650 } // Constraints = "$src1 = $dst"
7653 multiclass pclmul_alias<string asm, int immop> {
7654 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7655 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7657 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7658 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7660 def : InstAlias<!strconcat("vpclmul", asm,
7661 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7662 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7664 def : InstAlias<!strconcat("vpclmul", asm,
7665 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7666 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7668 defm : pclmul_alias<"hqhq", 0x11>;
7669 defm : pclmul_alias<"hqlq", 0x01>;
7670 defm : pclmul_alias<"lqhq", 0x10>;
7671 defm : pclmul_alias<"lqlq", 0x00>;
7673 //===----------------------------------------------------------------------===//
7674 // SSE4A Instructions
7675 //===----------------------------------------------------------------------===//
7677 let Predicates = [HasSSE4A] in {
7679 let Constraints = "$src = $dst" in {
7680 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7681 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7682 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7683 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7685 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7686 (ins VR128:$src, VR128:$mask),
7687 "extrq\t{$mask, $src|$src, $mask}",
7688 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7689 VR128:$mask))]>, PD;
7691 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7692 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7693 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7694 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7695 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7696 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7697 (ins VR128:$src, VR128:$mask),
7698 "insertq\t{$mask, $src|$src, $mask}",
7699 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7700 VR128:$mask))]>, XD;
7703 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7704 "movntss\t{$src, $dst|$dst, $src}",
7705 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7707 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7708 "movntsd\t{$src, $dst|$dst, $src}",
7709 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7712 //===----------------------------------------------------------------------===//
7714 //===----------------------------------------------------------------------===//
7716 //===----------------------------------------------------------------------===//
7717 // VBROADCAST - Load from memory and broadcast to all elements of the
7718 // destination operand
7720 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7721 X86MemOperand x86memop, Intrinsic Int> :
7722 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7723 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7724 [(set RC:$dst, (Int addr:$src))]>, VEX;
7726 // AVX2 adds register forms
7727 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7729 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7730 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7731 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7733 let ExeDomain = SSEPackedSingle in {
7734 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7735 int_x86_avx_vbroadcast_ss>;
7736 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7737 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7739 let ExeDomain = SSEPackedDouble in
7740 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7741 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7742 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7743 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7745 let ExeDomain = SSEPackedSingle in {
7746 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7747 int_x86_avx2_vbroadcast_ss_ps>;
7748 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7749 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7751 let ExeDomain = SSEPackedDouble in
7752 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7753 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7755 let Predicates = [HasAVX2] in
7756 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7757 int_x86_avx2_vbroadcasti128>, VEX_L;
7759 let Predicates = [HasAVX] in
7760 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7761 (VBROADCASTF128 addr:$src)>;
7764 //===----------------------------------------------------------------------===//
7765 // VINSERTF128 - Insert packed floating-point values
7767 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7768 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7769 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7770 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7773 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7774 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7775 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7779 let Predicates = [HasAVX] in {
7780 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7782 (VINSERTF128rr VR256:$src1, VR128:$src2,
7783 (INSERT_get_vinsert128_imm VR256:$ins))>;
7784 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7786 (VINSERTF128rr VR256:$src1, VR128:$src2,
7787 (INSERT_get_vinsert128_imm VR256:$ins))>;
7789 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7791 (VINSERTF128rm VR256:$src1, addr:$src2,
7792 (INSERT_get_vinsert128_imm VR256:$ins))>;
7793 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7795 (VINSERTF128rm VR256:$src1, addr:$src2,
7796 (INSERT_get_vinsert128_imm VR256:$ins))>;
7799 let Predicates = [HasAVX1Only] in {
7800 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7802 (VINSERTF128rr VR256:$src1, VR128:$src2,
7803 (INSERT_get_vinsert128_imm VR256:$ins))>;
7804 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7806 (VINSERTF128rr VR256:$src1, VR128:$src2,
7807 (INSERT_get_vinsert128_imm VR256:$ins))>;
7808 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7810 (VINSERTF128rr VR256:$src1, VR128:$src2,
7811 (INSERT_get_vinsert128_imm VR256:$ins))>;
7812 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7814 (VINSERTF128rr VR256:$src1, VR128:$src2,
7815 (INSERT_get_vinsert128_imm VR256:$ins))>;
7817 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7819 (VINSERTF128rm VR256:$src1, addr:$src2,
7820 (INSERT_get_vinsert128_imm VR256:$ins))>;
7821 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7822 (bc_v4i32 (loadv2i64 addr:$src2)),
7824 (VINSERTF128rm VR256:$src1, addr:$src2,
7825 (INSERT_get_vinsert128_imm VR256:$ins))>;
7826 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7827 (bc_v16i8 (loadv2i64 addr:$src2)),
7829 (VINSERTF128rm VR256:$src1, addr:$src2,
7830 (INSERT_get_vinsert128_imm VR256:$ins))>;
7831 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7832 (bc_v8i16 (loadv2i64 addr:$src2)),
7834 (VINSERTF128rm VR256:$src1, addr:$src2,
7835 (INSERT_get_vinsert128_imm VR256:$ins))>;
7838 //===----------------------------------------------------------------------===//
7839 // VEXTRACTF128 - Extract packed floating-point values
7841 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7842 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7843 (ins VR256:$src1, i8imm:$src2),
7844 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7847 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7848 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7849 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7854 let Predicates = [HasAVX] in {
7855 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7856 (v4f32 (VEXTRACTF128rr
7857 (v8f32 VR256:$src1),
7858 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7859 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7860 (v2f64 (VEXTRACTF128rr
7861 (v4f64 VR256:$src1),
7862 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7864 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7865 (iPTR imm))), addr:$dst),
7866 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7867 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7868 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7869 (iPTR imm))), addr:$dst),
7870 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7871 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7874 let Predicates = [HasAVX1Only] in {
7875 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7876 (v2i64 (VEXTRACTF128rr
7877 (v4i64 VR256:$src1),
7878 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7879 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7880 (v4i32 (VEXTRACTF128rr
7881 (v8i32 VR256:$src1),
7882 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7883 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7884 (v8i16 (VEXTRACTF128rr
7885 (v16i16 VR256:$src1),
7886 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7887 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7888 (v16i8 (VEXTRACTF128rr
7889 (v32i8 VR256:$src1),
7890 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7892 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7893 (iPTR imm))), addr:$dst),
7894 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7895 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7896 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7897 (iPTR imm))), addr:$dst),
7898 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7899 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7900 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7901 (iPTR imm))), addr:$dst),
7902 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7903 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7904 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7905 (iPTR imm))), addr:$dst),
7906 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7907 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7910 //===----------------------------------------------------------------------===//
7911 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7913 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7914 Intrinsic IntLd, Intrinsic IntLd256,
7915 Intrinsic IntSt, Intrinsic IntSt256> {
7916 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7917 (ins VR128:$src1, f128mem:$src2),
7918 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7919 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7921 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7922 (ins VR256:$src1, f256mem:$src2),
7923 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7924 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7926 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7927 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7928 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7929 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7930 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7931 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7932 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7933 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7936 let ExeDomain = SSEPackedSingle in
7937 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7938 int_x86_avx_maskload_ps,
7939 int_x86_avx_maskload_ps_256,
7940 int_x86_avx_maskstore_ps,
7941 int_x86_avx_maskstore_ps_256>;
7942 let ExeDomain = SSEPackedDouble in
7943 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7944 int_x86_avx_maskload_pd,
7945 int_x86_avx_maskload_pd_256,
7946 int_x86_avx_maskstore_pd,
7947 int_x86_avx_maskstore_pd_256>;
7949 //===----------------------------------------------------------------------===//
7950 // VPERMIL - Permute Single and Double Floating-Point Values
7952 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7953 RegisterClass RC, X86MemOperand x86memop_f,
7954 X86MemOperand x86memop_i, PatFrag i_frag,
7955 Intrinsic IntVar, ValueType vt> {
7956 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7957 (ins RC:$src1, RC:$src2),
7958 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7959 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7960 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7961 (ins RC:$src1, x86memop_i:$src2),
7962 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7963 [(set RC:$dst, (IntVar RC:$src1,
7964 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7966 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7967 (ins RC:$src1, i8imm:$src2),
7968 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7969 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7970 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7971 (ins x86memop_f:$src1, i8imm:$src2),
7972 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7974 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7977 let ExeDomain = SSEPackedSingle in {
7978 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7979 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7980 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7981 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7983 let ExeDomain = SSEPackedDouble in {
7984 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7985 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7986 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7987 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7990 let Predicates = [HasAVX] in {
7991 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7992 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7993 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7994 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7995 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (loadv4i64 addr:$src1)),
7997 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7998 def : Pat<(v4i64 (X86VPermilp (loadv4i64 addr:$src1), (i8 imm:$imm))),
7999 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8001 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
8002 (VPERMILPDri VR128:$src1, imm:$imm)>;
8003 def : Pat<(v2i64 (X86VPermilp (loadv2i64 addr:$src1), (i8 imm:$imm))),
8004 (VPERMILPDmi addr:$src1, imm:$imm)>;
8007 //===----------------------------------------------------------------------===//
8008 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8010 let ExeDomain = SSEPackedSingle in {
8011 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8012 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8013 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8014 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8015 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8016 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8017 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8018 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8019 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8020 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8023 let Predicates = [HasAVX] in {
8024 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8025 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8026 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8027 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8028 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8031 let Predicates = [HasAVX1Only] in {
8032 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8033 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8034 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8035 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8036 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8037 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8038 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8039 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8041 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8042 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8043 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8044 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8045 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8046 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8047 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8048 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8049 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8050 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8051 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8052 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8055 //===----------------------------------------------------------------------===//
8056 // VZERO - Zero YMM registers
8058 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8059 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8060 // Zero All YMM registers
8061 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8062 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
8064 // Zero Upper bits of YMM registers
8065 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8066 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
8069 //===----------------------------------------------------------------------===//
8070 // Half precision conversion instructions
8071 //===----------------------------------------------------------------------===//
8072 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8073 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8074 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8075 [(set RC:$dst, (Int VR128:$src))]>,
8077 let neverHasSideEffects = 1, mayLoad = 1 in
8078 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8079 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX;
8082 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8083 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8084 (ins RC:$src1, i32i8imm:$src2),
8085 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8086 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8088 let neverHasSideEffects = 1, mayStore = 1 in
8089 def mr : Ii8<0x1D, MRMDestMem, (outs),
8090 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8091 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8095 let Predicates = [HasF16C] in {
8096 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8097 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8098 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8099 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8102 //===----------------------------------------------------------------------===//
8103 // AVX2 Instructions
8104 //===----------------------------------------------------------------------===//
8106 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8107 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8108 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8109 X86MemOperand x86memop> {
8110 let isCommutable = 1 in
8111 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8112 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
8113 !strconcat(OpcodeStr,
8114 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8115 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8117 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8118 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
8119 !strconcat(OpcodeStr,
8120 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8123 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8127 let isCommutable = 0 in {
8128 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8129 VR128, loadv2i64, i128mem>;
8130 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8131 VR256, loadv4i64, i256mem>, VEX_L;
8134 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8136 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8137 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8139 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8141 //===----------------------------------------------------------------------===//
8142 // VPBROADCAST - Load from memory and broadcast to all elements of the
8143 // destination operand
8145 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8146 X86MemOperand x86memop, PatFrag ld_frag,
8147 Intrinsic Int128, Intrinsic Int256> {
8148 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8149 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8150 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
8151 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8152 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8154 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
8155 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8156 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8157 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
8158 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8159 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8161 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8165 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8166 int_x86_avx2_pbroadcastb_128,
8167 int_x86_avx2_pbroadcastb_256>;
8168 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8169 int_x86_avx2_pbroadcastw_128,
8170 int_x86_avx2_pbroadcastw_256>;
8171 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8172 int_x86_avx2_pbroadcastd_128,
8173 int_x86_avx2_pbroadcastd_256>;
8174 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8175 int_x86_avx2_pbroadcastq_128,
8176 int_x86_avx2_pbroadcastq_256>;
8178 let Predicates = [HasAVX2] in {
8179 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8180 (VPBROADCASTBrm addr:$src)>;
8181 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8182 (VPBROADCASTBYrm addr:$src)>;
8183 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8184 (VPBROADCASTWrm addr:$src)>;
8185 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8186 (VPBROADCASTWYrm addr:$src)>;
8187 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8188 (VPBROADCASTDrm addr:$src)>;
8189 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8190 (VPBROADCASTDYrm addr:$src)>;
8191 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8192 (VPBROADCASTQrm addr:$src)>;
8193 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8194 (VPBROADCASTQYrm addr:$src)>;
8196 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8197 (VPBROADCASTBrr VR128:$src)>;
8198 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8199 (VPBROADCASTBYrr VR128:$src)>;
8200 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8201 (VPBROADCASTWrr VR128:$src)>;
8202 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8203 (VPBROADCASTWYrr VR128:$src)>;
8204 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8205 (VPBROADCASTDrr VR128:$src)>;
8206 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8207 (VPBROADCASTDYrr VR128:$src)>;
8208 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8209 (VPBROADCASTQrr VR128:$src)>;
8210 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8211 (VPBROADCASTQYrr VR128:$src)>;
8212 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8213 (VBROADCASTSSrr VR128:$src)>;
8214 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8215 (VBROADCASTSSYrr VR128:$src)>;
8216 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8217 (VPBROADCASTQrr VR128:$src)>;
8218 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8219 (VBROADCASTSDYrr VR128:$src)>;
8221 // Provide fallback in case the load node that is used in the patterns above
8222 // is used by additional users, which prevents the pattern selection.
8223 let AddedComplexity = 20 in {
8224 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8225 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8226 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8227 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8228 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8229 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8231 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8232 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8233 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8234 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8235 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8236 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8240 // AVX1 broadcast patterns
8241 let Predicates = [HasAVX1Only] in {
8242 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8243 (VBROADCASTSSYrm addr:$src)>;
8244 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8245 (VBROADCASTSDYrm addr:$src)>;
8246 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8247 (VBROADCASTSSrm addr:$src)>;
8250 let Predicates = [HasAVX] in {
8251 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8252 (VBROADCASTSSYrm addr:$src)>;
8253 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8254 (VBROADCASTSDYrm addr:$src)>;
8255 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8256 (VBROADCASTSSrm addr:$src)>;
8258 // Provide fallback in case the load node that is used in the patterns above
8259 // is used by additional users, which prevents the pattern selection.
8260 let AddedComplexity = 20 in {
8261 // 128bit broadcasts:
8262 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8263 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8264 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8265 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8266 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8267 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8268 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8269 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8270 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8271 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8273 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8274 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8275 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8276 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8277 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8278 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8279 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8280 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8281 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8282 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8286 //===----------------------------------------------------------------------===//
8287 // VPERM - Permute instructions
8290 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8292 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8293 (ins VR256:$src1, VR256:$src2),
8294 !strconcat(OpcodeStr,
8295 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8297 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8299 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8300 (ins VR256:$src1, i256mem:$src2),
8301 !strconcat(OpcodeStr,
8302 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8304 (OpVT (X86VPermv VR256:$src1,
8305 (bitconvert (mem_frag addr:$src2)))))]>,
8309 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32>;
8310 let ExeDomain = SSEPackedSingle in
8311 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32>;
8313 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8315 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8316 (ins VR256:$src1, i8imm:$src2),
8317 !strconcat(OpcodeStr,
8318 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8320 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8322 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8323 (ins i256mem:$src1, i8imm:$src2),
8324 !strconcat(OpcodeStr,
8325 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8327 (OpVT (X86VPermi (mem_frag addr:$src1),
8328 (i8 imm:$src2))))]>, VEX, VEX_L;
8331 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64>, VEX_W;
8332 let ExeDomain = SSEPackedDouble in
8333 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64>, VEX_W;
8335 //===----------------------------------------------------------------------===//
8336 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8338 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8339 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8340 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8341 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8342 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8343 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8344 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8345 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8346 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8347 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8349 let Predicates = [HasAVX2] in {
8350 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8351 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8352 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8353 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8354 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8355 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8357 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8359 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8360 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8361 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8362 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8363 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8365 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8369 //===----------------------------------------------------------------------===//
8370 // VINSERTI128 - Insert packed integer values
8372 let neverHasSideEffects = 1 in {
8373 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8374 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8375 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8378 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8379 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8380 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8384 let Predicates = [HasAVX2] in {
8385 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8387 (VINSERTI128rr VR256:$src1, VR128:$src2,
8388 (INSERT_get_vinsert128_imm VR256:$ins))>;
8389 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8391 (VINSERTI128rr VR256:$src1, VR128:$src2,
8392 (INSERT_get_vinsert128_imm VR256:$ins))>;
8393 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8395 (VINSERTI128rr VR256:$src1, VR128:$src2,
8396 (INSERT_get_vinsert128_imm VR256:$ins))>;
8397 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8399 (VINSERTI128rr VR256:$src1, VR128:$src2,
8400 (INSERT_get_vinsert128_imm VR256:$ins))>;
8402 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8404 (VINSERTI128rm VR256:$src1, addr:$src2,
8405 (INSERT_get_vinsert128_imm VR256:$ins))>;
8406 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8407 (bc_v4i32 (loadv2i64 addr:$src2)),
8409 (VINSERTI128rm VR256:$src1, addr:$src2,
8410 (INSERT_get_vinsert128_imm VR256:$ins))>;
8411 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8412 (bc_v16i8 (loadv2i64 addr:$src2)),
8414 (VINSERTI128rm VR256:$src1, addr:$src2,
8415 (INSERT_get_vinsert128_imm VR256:$ins))>;
8416 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8417 (bc_v8i16 (loadv2i64 addr:$src2)),
8419 (VINSERTI128rm VR256:$src1, addr:$src2,
8420 (INSERT_get_vinsert128_imm VR256:$ins))>;
8423 //===----------------------------------------------------------------------===//
8424 // VEXTRACTI128 - Extract packed integer values
8426 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8427 (ins VR256:$src1, i8imm:$src2),
8428 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8430 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8432 let neverHasSideEffects = 1, mayStore = 1 in
8433 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8434 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8435 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8438 let Predicates = [HasAVX2] in {
8439 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8440 (v2i64 (VEXTRACTI128rr
8441 (v4i64 VR256:$src1),
8442 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8443 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8444 (v4i32 (VEXTRACTI128rr
8445 (v8i32 VR256:$src1),
8446 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8447 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8448 (v8i16 (VEXTRACTI128rr
8449 (v16i16 VR256:$src1),
8450 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8451 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8452 (v16i8 (VEXTRACTI128rr
8453 (v32i8 VR256:$src1),
8454 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8456 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8457 (iPTR imm))), addr:$dst),
8458 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8459 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8460 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8461 (iPTR imm))), addr:$dst),
8462 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8463 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8464 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8465 (iPTR imm))), addr:$dst),
8466 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8467 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8468 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8469 (iPTR imm))), addr:$dst),
8470 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8471 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8474 //===----------------------------------------------------------------------===//
8475 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8477 multiclass avx2_pmovmask<string OpcodeStr,
8478 Intrinsic IntLd128, Intrinsic IntLd256,
8479 Intrinsic IntSt128, Intrinsic IntSt256> {
8480 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8481 (ins VR128:$src1, i128mem:$src2),
8482 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8483 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8484 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8485 (ins VR256:$src1, i256mem:$src2),
8486 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8487 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8489 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8490 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8491 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8492 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8493 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8494 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8495 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8496 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8499 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8500 int_x86_avx2_maskload_d,
8501 int_x86_avx2_maskload_d_256,
8502 int_x86_avx2_maskstore_d,
8503 int_x86_avx2_maskstore_d_256>;
8504 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8505 int_x86_avx2_maskload_q,
8506 int_x86_avx2_maskload_q_256,
8507 int_x86_avx2_maskstore_q,
8508 int_x86_avx2_maskstore_q_256>, VEX_W;
8511 //===----------------------------------------------------------------------===//
8512 // Variable Bit Shifts
8514 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8515 ValueType vt128, ValueType vt256> {
8516 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8517 (ins VR128:$src1, VR128:$src2),
8518 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8520 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8522 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8523 (ins VR128:$src1, i128mem:$src2),
8524 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8526 (vt128 (OpNode VR128:$src1,
8527 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8529 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8530 (ins VR256:$src1, VR256:$src2),
8531 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8533 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8535 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8536 (ins VR256:$src1, i256mem:$src2),
8537 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8539 (vt256 (OpNode VR256:$src1,
8540 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8544 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8545 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8546 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8547 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8548 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8550 //===----------------------------------------------------------------------===//
8551 // VGATHER - GATHER Operations
8552 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8553 X86MemOperand memop128, X86MemOperand memop256> {
8554 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8555 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8556 !strconcat(OpcodeStr,
8557 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8559 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8560 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8561 !strconcat(OpcodeStr,
8562 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8563 []>, VEX_4VOp3, VEX_L;
8566 let mayLoad = 1, Constraints
8567 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8569 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8570 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8571 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8572 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8573 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8574 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8575 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8576 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;