1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
22 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
23 [SDNPCommutative, SDNPAssociative]>;
24 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
25 [SDNPCommutative, SDNPAssociative]>;
26 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
28 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
30 def X86s2vec : SDNode<"X86ISD::S2VEC",
31 SDTypeProfile<1, 1, []>, []>;
32 def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
33 SDTypeProfile<1, 1, []>, []>;
34 def X86pextrw : SDNode<"X86ISD::PEXTRW",
35 SDTypeProfile<1, 2, []>, []>;
36 def X86pinsrw : SDNode<"X86ISD::PINSRW",
37 SDTypeProfile<1, 3, []>, []>;
39 //===----------------------------------------------------------------------===//
40 // SSE pattern fragments
41 //===----------------------------------------------------------------------===//
43 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
44 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
46 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
47 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
48 def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
49 def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
50 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
51 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
53 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
54 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
55 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
56 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
57 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
58 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
60 def fp32imm0 : PatLeaf<(f32 fpimm), [{
61 return N->isExactlyValue(+0.0);
64 def PSxLDQ_imm : SDNodeXForm<imm, [{
65 // Transformation function: imm >> 3
66 return getI32Imm(N->getValue() >> 3);
69 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
71 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
72 return getI8Imm(X86::getShuffleSHUFImmediate(N));
75 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
77 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
78 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
81 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
83 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
84 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
87 def SSE_splat_mask : PatLeaf<(build_vector), [{
88 return X86::isSplatMask(N);
89 }], SHUFFLE_get_shuf_imm>;
91 def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
92 return X86::isMOVLHPSMask(N);
95 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
96 return X86::isMOVHLPSMask(N);
99 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
100 return X86::isMOVHPMask(N);
103 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
104 return X86::isMOVLPMask(N);
107 def MOVS_shuffle_mask : PatLeaf<(build_vector), [{
108 return X86::isMOVSMask(N);
111 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
112 return X86::isUNPCKLMask(N);
115 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
116 return X86::isUNPCKHMask(N);
119 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
120 return X86::isUNPCKL_v_undef_Mask(N);
123 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
124 return X86::isPSHUFDMask(N);
125 }], SHUFFLE_get_shuf_imm>;
127 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
128 return X86::isPSHUFHWMask(N);
129 }], SHUFFLE_get_pshufhw_imm>;
131 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
132 return X86::isPSHUFLWMask(N);
133 }], SHUFFLE_get_pshuflw_imm>;
135 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isPSHUFDMask(N);
137 }], SHUFFLE_get_shuf_imm>;
139 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isSHUFPMask(N);
141 }], SHUFFLE_get_shuf_imm>;
143 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isSHUFPMask(N);
145 }], SHUFFLE_get_shuf_imm>;
147 //===----------------------------------------------------------------------===//
148 // SSE scalar FP Instructions
149 //===----------------------------------------------------------------------===//
151 // Instruction templates
152 // SSI - SSE1 instructions with XS prefix.
153 // SDI - SSE2 instructions with XD prefix.
154 // PSI - SSE1 instructions with TB prefix.
155 // PDI - SSE2 instructions with TB and OpSize prefixes.
156 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
157 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
158 // S3SI - SSE3 instructions with XD prefix.
159 // S3DI - SSE3 instructions with TB and OpSize prefixes.
160 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
161 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
162 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
163 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
164 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
165 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
166 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
167 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
168 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
169 : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasSSE1]> {
170 let Pattern = pattern;
172 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
173 : X86Inst<o, F, Imm8, ops, asm>, TB, OpSize, Requires<[HasSSE2]> {
174 let Pattern = pattern;
176 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
177 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
178 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
179 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
181 //===----------------------------------------------------------------------===//
182 // Helpers for defining instructions that directly correspond to intrinsics.
183 class SS_Intr<bits<8> o, string asm, Intrinsic IntId>
184 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
185 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
186 class SS_Intm<bits<8> o, string asm, Intrinsic IntId>
187 : SSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
188 [(set VR128:$dst, (v4f32 (IntId (load addr:$src))))]>;
189 class SD_Intr<bits<8> o, string asm, Intrinsic IntId>
190 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
191 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
192 class SD_Intm<bits<8> o, string asm, Intrinsic IntId>
193 : SDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
194 [(set VR128:$dst, (v2f64 (IntId (load addr:$src))))]>;
196 class SS_Intrr<bits<8> o, string asm, Intrinsic IntId>
197 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
198 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
199 class SS_Intrm<bits<8> o, string asm, Intrinsic IntId>
200 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
201 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
202 class SD_Intrr<bits<8> o, string asm, Intrinsic IntId>
203 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
204 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
205 class SD_Intrm<bits<8> o, string asm, Intrinsic IntId>
206 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
207 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
209 class PS_Intr<bits<8> o, string asm, Intrinsic IntId>
210 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
211 [(set VR128:$dst, (IntId VR128:$src))]>;
212 class PS_Intm<bits<8> o, string asm, Intrinsic IntId>
213 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
214 [(set VR128:$dst, (IntId (loadv4f32 addr:$src)))]>;
215 class PD_Intr<bits<8> o, string asm, Intrinsic IntId>
216 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
217 [(set VR128:$dst, (IntId VR128:$src))]>;
218 class PD_Intm<bits<8> o, string asm, Intrinsic IntId>
219 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
220 [(set VR128:$dst, (IntId (loadv2f64 addr:$src)))]>;
222 class PS_Intrr<bits<8> o, string asm, Intrinsic IntId>
223 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
224 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
225 class PS_Intrm<bits<8> o, string asm, Intrinsic IntId>
226 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
227 [(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))]>;
228 class PD_Intrr<bits<8> o, string asm, Intrinsic IntId>
229 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
230 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
231 class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
232 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
233 [(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
235 class S3S_Intrr<bits<8> o, string asm, Intrinsic IntId>
236 : S3SI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
237 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
238 class S3S_Intrm<bits<8> o, string asm, Intrinsic IntId>
239 : S3SI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
240 [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
241 (loadv4f32 addr:$src2))))]>;
242 class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
243 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
244 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
245 class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
246 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
247 [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
248 (loadv2f64 addr:$src2))))]>;
250 // Some 'special' instructions
251 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
252 "#IMPLICIT_DEF $dst",
253 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
254 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
255 "#IMPLICIT_DEF $dst",
256 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
258 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
259 // scheduler into a branch sequence.
260 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
261 def CMOV_FR32 : I<0, Pseudo,
262 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
263 "#CMOV_FR32 PSEUDO!",
264 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
265 def CMOV_FR64 : I<0, Pseudo,
266 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
267 "#CMOV_FR64 PSEUDO!",
268 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
269 def CMOV_V4F32 : I<0, Pseudo,
270 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
271 "#CMOV_V4F32 PSEUDO!",
273 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
274 def CMOV_V2F64 : I<0, Pseudo,
275 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
276 "#CMOV_V2F64 PSEUDO!",
278 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
279 def CMOV_V2I64 : I<0, Pseudo,
280 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
281 "#CMOV_V2I64 PSEUDO!",
283 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
287 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
288 "movss {$src, $dst|$dst, $src}", []>;
289 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
290 "movss {$src, $dst|$dst, $src}",
291 [(set FR32:$dst, (loadf32 addr:$src))]>;
292 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
293 "movsd {$src, $dst|$dst, $src}", []>;
294 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
295 "movsd {$src, $dst|$dst, $src}",
296 [(set FR64:$dst, (loadf64 addr:$src))]>;
298 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
299 "movss {$src, $dst|$dst, $src}",
300 [(store FR32:$src, addr:$dst)]>;
301 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
302 "movsd {$src, $dst|$dst, $src}",
303 [(store FR64:$src, addr:$dst)]>;
305 // Arithmetic instructions
306 let isTwoAddress = 1 in {
307 let isCommutable = 1 in {
308 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
309 "addss {$src2, $dst|$dst, $src2}",
310 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
311 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
312 "addsd {$src2, $dst|$dst, $src2}",
313 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
314 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
315 "mulss {$src2, $dst|$dst, $src2}",
316 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
317 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
318 "mulsd {$src2, $dst|$dst, $src2}",
319 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
322 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
323 "addss {$src2, $dst|$dst, $src2}",
324 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
325 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
326 "addsd {$src2, $dst|$dst, $src2}",
327 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
328 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
329 "mulss {$src2, $dst|$dst, $src2}",
330 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
331 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
332 "mulsd {$src2, $dst|$dst, $src2}",
333 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
335 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
336 "divss {$src2, $dst|$dst, $src2}",
337 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
338 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
339 "divss {$src2, $dst|$dst, $src2}",
340 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
341 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
342 "divsd {$src2, $dst|$dst, $src2}",
343 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
344 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
345 "divsd {$src2, $dst|$dst, $src2}",
346 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
348 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
349 "subss {$src2, $dst|$dst, $src2}",
350 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
351 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
352 "subss {$src2, $dst|$dst, $src2}",
353 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
354 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
355 "subsd {$src2, $dst|$dst, $src2}",
356 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
357 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
358 "subsd {$src2, $dst|$dst, $src2}",
359 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
362 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
363 "sqrtss {$src, $dst|$dst, $src}",
364 [(set FR32:$dst, (fsqrt FR32:$src))]>;
365 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
366 "sqrtss {$src, $dst|$dst, $src}",
367 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
368 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
369 "sqrtsd {$src, $dst|$dst, $src}",
370 [(set FR64:$dst, (fsqrt FR64:$src))]>;
371 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
372 "sqrtsd {$src, $dst|$dst, $src}",
373 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
375 def RSQRTSSr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
376 "rsqrtss {$src, $dst|$dst, $src}", []>;
377 def RSQRTSSm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
378 "rsqrtss {$src, $dst|$dst, $src}", []>;
379 def RCPSSr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
380 "rcpss {$src, $dst|$dst, $src}", []>;
381 def RCPSSm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
382 "rcpss {$src, $dst|$dst, $src}", []>;
384 let isTwoAddress = 1 in {
385 def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
386 "maxss {$src2, $dst|$dst, $src2}", []>;
387 def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
388 "maxss {$src2, $dst|$dst, $src2}", []>;
389 def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
390 "maxsd {$src2, $dst|$dst, $src2}", []>;
391 def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
392 "maxsd {$src2, $dst|$dst, $src2}", []>;
393 def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
394 "minss {$src2, $dst|$dst, $src2}", []>;
395 def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
396 "minss {$src2, $dst|$dst, $src2}", []>;
397 def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
398 "minsd {$src2, $dst|$dst, $src2}", []>;
399 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
400 "minsd {$src2, $dst|$dst, $src2}", []>;
403 // Aliases to match intrinsics which expect XMM operand(s).
404 let isTwoAddress = 1 in {
405 let isCommutable = 1 in {
406 def Int_ADDSSrr : SS_Intrr<0x58, "addss {$src2, $dst|$dst, $src2}",
408 def Int_ADDSDrr : SD_Intrr<0x58, "addsd {$src2, $dst|$dst, $src2}",
409 int_x86_sse2_add_sd>;
410 def Int_MULSSrr : SS_Intrr<0x59, "mulss {$src2, $dst|$dst, $src2}",
412 def Int_MULSDrr : SD_Intrr<0x59, "mulsd {$src2, $dst|$dst, $src2}",
413 int_x86_sse2_mul_sd>;
416 def Int_ADDSSrm : SS_Intrm<0x58, "addss {$src2, $dst|$dst, $src2}",
418 def Int_ADDSDrm : SD_Intrm<0x58, "addsd {$src2, $dst|$dst, $src2}",
419 int_x86_sse2_add_sd>;
420 def Int_MULSSrm : SS_Intrm<0x59, "mulss {$src2, $dst|$dst, $src2}",
422 def Int_MULSDrm : SD_Intrm<0x59, "mulsd {$src2, $dst|$dst, $src2}",
423 int_x86_sse2_mul_sd>;
425 def Int_DIVSSrr : SS_Intrr<0x5E, "divss {$src2, $dst|$dst, $src2}",
427 def Int_DIVSSrm : SS_Intrm<0x5E, "divss {$src2, $dst|$dst, $src2}",
429 def Int_DIVSDrr : SD_Intrr<0x5E, "divsd {$src2, $dst|$dst, $src2}",
430 int_x86_sse2_div_sd>;
431 def Int_DIVSDrm : SD_Intrm<0x5E, "divsd {$src2, $dst|$dst, $src2}",
432 int_x86_sse2_div_sd>;
434 def Int_SUBSSrr : SS_Intrr<0x5C, "subss {$src2, $dst|$dst, $src2}",
436 def Int_SUBSSrm : SS_Intrm<0x5C, "subss {$src2, $dst|$dst, $src2}",
438 def Int_SUBSDrr : SD_Intrr<0x5C, "subsd {$src2, $dst|$dst, $src2}",
439 int_x86_sse2_sub_sd>;
440 def Int_SUBSDrm : SD_Intrm<0x5C, "subsd {$src2, $dst|$dst, $src2}",
441 int_x86_sse2_sub_sd>;
444 def Int_SQRTSSr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}",
445 int_x86_sse_sqrt_ss>;
446 def Int_SQRTSSm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}",
447 int_x86_sse_sqrt_ss>;
448 def Int_SQRTSDr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}",
449 int_x86_sse2_sqrt_sd>;
450 def Int_SQRTSDm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}",
451 int_x86_sse2_sqrt_sd>;
453 def Int_RSQRTSSr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}",
454 int_x86_sse_rsqrt_ss>;
455 def Int_RSQRTSSm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}",
456 int_x86_sse_rsqrt_ss>;
457 def Int_RCPSSr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}",
459 def Int_RCPSSm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}",
462 let isTwoAddress = 1 in {
463 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}",
465 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}",
467 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
468 int_x86_sse2_max_sd>;
469 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
470 int_x86_sse2_max_sd>;
471 def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}",
473 def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}",
475 def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}",
476 int_x86_sse2_min_sd>;
477 def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}",
478 int_x86_sse2_min_sd>;
481 // Conversion instructions
482 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, FR32:$src),
483 "cvtss2si {$src, $dst|$dst, $src}", []>;
484 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
485 "cvtss2si {$src, $dst|$dst, $src}", []>;
487 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
488 "cvttss2si {$src, $dst|$dst, $src}",
489 [(set R32:$dst, (fp_to_sint FR32:$src))]>;
490 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
491 "cvttss2si {$src, $dst|$dst, $src}",
492 [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
493 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
494 "cvttsd2si {$src, $dst|$dst, $src}",
495 [(set R32:$dst, (fp_to_sint FR64:$src))]>;
496 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
497 "cvttsd2si {$src, $dst|$dst, $src}",
498 [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
499 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
500 "cvtsd2ss {$src, $dst|$dst, $src}",
501 [(set FR32:$dst, (fround FR64:$src))]>;
502 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
503 "cvtsd2ss {$src, $dst|$dst, $src}",
504 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
505 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
506 "cvtsi2ss {$src, $dst|$dst, $src}",
507 [(set FR32:$dst, (sint_to_fp R32:$src))]>;
508 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
509 "cvtsi2ss {$src, $dst|$dst, $src}",
510 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
511 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
512 "cvtsi2sd {$src, $dst|$dst, $src}",
513 [(set FR64:$dst, (sint_to_fp R32:$src))]>;
514 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
515 "cvtsi2sd {$src, $dst|$dst, $src}",
516 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
517 // SSE2 instructions with XS prefix
518 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
519 "cvtss2sd {$src, $dst|$dst, $src}",
520 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
522 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
523 "cvtss2sd {$src, $dst|$dst, $src}",
524 [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
527 // Aliases to match intrinsics which expect XMM operand(s).
528 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
529 "cvttsd2si {$src, $dst|$dst, $src}",
530 [(set R32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
531 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
532 "cvttsd2si {$src, $dst|$dst, $src}",
533 [(set R32:$dst, (int_x86_sse2_cvttsd2si
534 (loadv2f64 addr:$src)))]>;
536 def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
537 "cvtsd2si {$src, $dst|$dst, $src}",
538 [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
539 def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
540 "cvtsd2si {$src, $dst|$dst, $src}",
541 [(set R32:$dst, (int_x86_sse2_cvtsd2si
542 (loadv2f64 addr:$src)))]>;
544 // Comparison instructions
545 let isTwoAddress = 1 in {
546 def CMPSSrr : SSI<0xC2, MRMSrcReg,
547 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
548 "cmp${cc}ss {$src, $dst|$dst, $src}",
550 def CMPSSrm : SSI<0xC2, MRMSrcMem,
551 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
552 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
553 def CMPSDrr : SDI<0xC2, MRMSrcReg,
554 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
555 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
556 def CMPSDrm : SDI<0xC2, MRMSrcMem,
557 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
558 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
561 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
562 "ucomiss {$src2, $src1|$src1, $src2}",
563 [(X86cmp FR32:$src1, FR32:$src2)]>;
564 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
565 "ucomiss {$src2, $src1|$src1, $src2}",
566 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
567 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
568 "ucomisd {$src2, $src1|$src1, $src2}",
569 [(X86cmp FR64:$src1, FR64:$src2)]>;
570 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
571 "ucomisd {$src2, $src1|$src1, $src2}",
572 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
574 // Aliases to match intrinsics which expect XMM operand(s).
575 let isTwoAddress = 1 in {
576 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
577 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
578 "cmp${cc}ss {$src, $dst|$dst, $src}",
579 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
580 VR128:$src, imm:$cc))]>;
581 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
582 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
583 "cmp${cc}ss {$src, $dst|$dst, $src}",
584 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
585 (load addr:$src), imm:$cc))]>;
586 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
587 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
588 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
589 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
590 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
591 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
594 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
595 "ucomiss {$src2, $src1|$src1, $src2}",
596 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
597 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
598 "ucomiss {$src2, $src1|$src1, $src2}",
599 [(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
600 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
601 "ucomisd {$src2, $src1|$src1, $src2}",
602 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
603 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
604 "ucomisd {$src2, $src1|$src1, $src2}",
605 [(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
607 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
608 "comiss {$src2, $src1|$src1, $src2}",
609 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
610 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
611 "comiss {$src2, $src1|$src1, $src2}",
612 [(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
613 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
614 "comisd {$src2, $src1|$src1, $src2}",
615 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
616 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
617 "comisd {$src2, $src1|$src1, $src2}",
618 [(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
620 // Aliases of packed instructions for scalar use. These all have names that
623 // Alias instructions that map fld0 to pxor for sse.
624 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
625 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
626 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
627 Requires<[HasSSE1]>, TB, OpSize;
628 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
629 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
630 Requires<[HasSSE2]>, TB, OpSize;
632 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
633 // Upper bits are disregarded.
634 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
635 "movaps {$src, $dst|$dst, $src}", []>;
636 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
637 "movapd {$src, $dst|$dst, $src}", []>;
639 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
640 // Upper bits are disregarded.
641 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
642 "movaps {$src, $dst|$dst, $src}",
643 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
644 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
645 "movapd {$src, $dst|$dst, $src}",
646 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
648 // Alias bitwise logical operations using SSE logical ops on packed FP values.
649 let isTwoAddress = 1 in {
650 let isCommutable = 1 in {
651 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
652 "andps {$src2, $dst|$dst, $src2}",
653 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
654 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
655 "andpd {$src2, $dst|$dst, $src2}",
656 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
657 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
658 "orps {$src2, $dst|$dst, $src2}", []>;
659 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
660 "orpd {$src2, $dst|$dst, $src2}", []>;
661 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
662 "xorps {$src2, $dst|$dst, $src2}",
663 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
664 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
665 "xorpd {$src2, $dst|$dst, $src2}",
666 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
668 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
669 "andps {$src2, $dst|$dst, $src2}",
670 [(set FR32:$dst, (X86fand FR32:$src1,
671 (X86loadpf32 addr:$src2)))]>;
672 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
673 "andpd {$src2, $dst|$dst, $src2}",
674 [(set FR64:$dst, (X86fand FR64:$src1,
675 (X86loadpf64 addr:$src2)))]>;
676 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
677 "orps {$src2, $dst|$dst, $src2}", []>;
678 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
679 "orpd {$src2, $dst|$dst, $src2}", []>;
680 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
681 "xorps {$src2, $dst|$dst, $src2}",
682 [(set FR32:$dst, (X86fxor FR32:$src1,
683 (X86loadpf32 addr:$src2)))]>;
684 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
685 "xorpd {$src2, $dst|$dst, $src2}",
686 [(set FR64:$dst, (X86fxor FR64:$src1,
687 (X86loadpf64 addr:$src2)))]>;
689 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
690 "andnps {$src2, $dst|$dst, $src2}", []>;
691 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
692 "andnps {$src2, $dst|$dst, $src2}", []>;
693 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
694 "andnpd {$src2, $dst|$dst, $src2}", []>;
695 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
696 "andnpd {$src2, $dst|$dst, $src2}", []>;
699 //===----------------------------------------------------------------------===//
700 // SSE packed FP Instructions
701 //===----------------------------------------------------------------------===//
703 // Some 'special' instructions
704 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
705 "#IMPLICIT_DEF $dst",
706 [(set VR128:$dst, (v4f32 (undef)))]>,
710 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
711 "movaps {$src, $dst|$dst, $src}", []>;
712 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
713 "movaps {$src, $dst|$dst, $src}",
714 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
715 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
716 "movapd {$src, $dst|$dst, $src}", []>;
717 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
718 "movapd {$src, $dst|$dst, $src}",
719 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
721 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
722 "movaps {$src, $dst|$dst, $src}",
723 [(store (v4f32 VR128:$src), addr:$dst)]>;
724 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
725 "movapd {$src, $dst|$dst, $src}",
726 [(store (v2f64 VR128:$src), addr:$dst)]>;
728 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
729 "movups {$src, $dst|$dst, $src}", []>;
730 def MOVUPSrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
731 "movups {$src, $dst|$dst, $src}",
732 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
733 def MOVUPSmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
734 "movups {$src, $dst|$dst, $src}",
735 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
736 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
737 "movupd {$src, $dst|$dst, $src}", []>;
738 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
739 "movupd {$src, $dst|$dst, $src}",
740 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
741 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
742 "movupd {$src, $dst|$dst, $src}",
743 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
744 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
745 "movdqu {$src, $dst|$dst, $src}",
746 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
747 XS, Requires<[HasSSE2]>;
748 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
749 "movdqu {$src, $dst|$dst, $src}",
750 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
751 XS, Requires<[HasSSE2]>;
753 let isTwoAddress = 1 in {
754 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
755 "movlps {$src2, $dst|$dst, $src2}",
757 (v4f32 (vector_shuffle VR128:$src1,
758 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
759 MOVLP_shuffle_mask)))]>;
760 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
761 "movlpd {$src2, $dst|$dst, $src2}",
763 (v2f64 (vector_shuffle VR128:$src1,
764 (scalar_to_vector (loadf64 addr:$src2)),
765 MOVLP_shuffle_mask)))]>;
766 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
767 "movhps {$src2, $dst|$dst, $src2}",
769 (v4f32 (vector_shuffle VR128:$src1,
770 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
771 MOVHP_shuffle_mask)))]>;
772 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
773 "movhpd {$src2, $dst|$dst, $src2}",
775 (v2f64 (vector_shuffle VR128:$src1,
776 (scalar_to_vector (loadf64 addr:$src2)),
777 MOVHP_shuffle_mask)))]>;
780 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
781 "movlps {$src, $dst|$dst, $src}",
782 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
783 (i32 0))), addr:$dst)]>;
784 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
785 "movlpd {$src, $dst|$dst, $src}",
786 [(store (f64 (vector_extract (v2f64 VR128:$src),
787 (i32 0))), addr:$dst)]>;
789 // v2f64 extract element 1 is always custom lowered to unpack high to low
790 // and extract element 0 so the non-store version isn't too horrible.
791 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
792 "movhps {$src, $dst|$dst, $src}",
793 [(store (f64 (vector_extract
794 (v2f64 (vector_shuffle
795 (bc_v2f64 (v4f32 VR128:$src)), (undef),
796 UNPCKH_shuffle_mask)), (i32 0))),
798 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
799 "movhpd {$src, $dst|$dst, $src}",
800 [(store (f64 (vector_extract
801 (v2f64 (vector_shuffle VR128:$src, (undef),
802 UNPCKH_shuffle_mask)), (i32 0))),
805 let isTwoAddress = 1 in {
806 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
807 "movlhps {$src2, $dst|$dst, $src2}",
809 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
810 MOVLHPS_shuffle_mask)))]>;
812 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
813 "movhlps {$src2, $dst|$dst, $src2}",
815 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
816 MOVHLPS_shuffle_mask)))]>;
819 // Conversion instructions
820 def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
821 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
822 def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
823 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
824 def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
825 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
826 def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
827 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
829 // SSE2 instructions without OpSize prefix
830 def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
831 "cvtdq2ps {$src, $dst|$dst, $src}",
832 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
833 TB, Requires<[HasSSE2]>;
834 def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
835 "cvtdq2ps {$src, $dst|$dst, $src}",
836 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
837 (bc_v4i32 (loadv2i64 addr:$src))))]>,
838 TB, Requires<[HasSSE2]>;
840 // SSE2 instructions with XS prefix
841 def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
842 "cvtdq2pd {$src, $dst|$dst, $src}",
843 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
844 XS, Requires<[HasSSE2]>;
845 def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
846 "cvtdq2pd {$src, $dst|$dst, $src}",
847 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
848 (bc_v4i32 (loadv2i64 addr:$src))))]>,
849 XS, Requires<[HasSSE2]>;
851 def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
852 "cvtps2pi {$src, $dst|$dst, $src}", []>;
853 def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
854 "cvtps2pi {$src, $dst|$dst, $src}", []>;
855 def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
856 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
857 def CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
858 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
860 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
861 "cvtps2dq {$src, $dst|$dst, $src}",
862 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
863 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
864 "cvtps2dq {$src, $dst|$dst, $src}",
865 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
866 (loadv4f32 addr:$src)))]>;
867 // SSE2 packed instructions with XS prefix
868 def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
869 "cvttps2dq {$src, $dst|$dst, $src}",
870 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
871 XS, Requires<[HasSSE2]>;
872 def CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
873 "cvttps2dq {$src, $dst|$dst, $src}",
874 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
875 (loadv4f32 addr:$src)))]>,
876 XS, Requires<[HasSSE2]>;
878 // SSE2 packed instructions with XD prefix
879 def CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
880 "cvtpd2dq {$src, $dst|$dst, $src}",
881 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
882 XD, Requires<[HasSSE2]>;
883 def CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
884 "cvtpd2dq {$src, $dst|$dst, $src}",
885 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
886 (loadv2f64 addr:$src)))]>,
887 XD, Requires<[HasSSE2]>;
888 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
889 "cvttpd2dq {$src, $dst|$dst, $src}",
890 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
891 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
892 "cvttpd2dq {$src, $dst|$dst, $src}",
893 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
894 (loadv2f64 addr:$src)))]>;
896 // SSE2 instructions without OpSize prefix
897 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
898 "cvtps2pd {$src, $dst|$dst, $src}",
899 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
900 TB, Requires<[HasSSE2]>;
901 def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
902 "cvtps2pd {$src, $dst|$dst, $src}",
903 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
904 (loadv4f32 addr:$src)))]>,
905 TB, Requires<[HasSSE2]>;
907 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
908 "cvtpd2ps {$src, $dst|$dst, $src}",
909 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
910 def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
911 "cvtpd2ps {$src, $dst|$dst, $src}",
912 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
913 (loadv2f64 addr:$src)))]>;
916 let isTwoAddress = 1 in {
917 let isCommutable = 1 in {
918 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
919 "addps {$src2, $dst|$dst, $src2}",
920 [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
921 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
922 "addpd {$src2, $dst|$dst, $src2}",
923 [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
924 def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
925 "mulps {$src2, $dst|$dst, $src2}",
926 [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
927 def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
928 "mulpd {$src2, $dst|$dst, $src2}",
929 [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
932 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
933 "addps {$src2, $dst|$dst, $src2}",
934 [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
935 (load addr:$src2))))]>;
936 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
937 "addpd {$src2, $dst|$dst, $src2}",
938 [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
939 (load addr:$src2))))]>;
940 def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
941 "mulps {$src2, $dst|$dst, $src2}",
942 [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
943 (load addr:$src2))))]>;
944 def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
945 "mulpd {$src2, $dst|$dst, $src2}",
946 [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
947 (load addr:$src2))))]>;
949 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
950 "divps {$src2, $dst|$dst, $src2}",
951 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
952 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
953 "divps {$src2, $dst|$dst, $src2}",
954 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
955 (load addr:$src2))))]>;
956 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
957 "divpd {$src2, $dst|$dst, $src2}",
958 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
959 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
960 "divpd {$src2, $dst|$dst, $src2}",
961 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
962 (load addr:$src2))))]>;
964 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
965 "subps {$src2, $dst|$dst, $src2}",
966 [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
967 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
968 "subps {$src2, $dst|$dst, $src2}",
969 [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
970 (load addr:$src2))))]>;
971 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
972 "subpd {$src2, $dst|$dst, $src2}",
973 [(set VR128:$dst, (v2f64 (fsub VR128:$src1, VR128:$src2)))]>;
974 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
975 "subpd {$src2, $dst|$dst, $src2}",
976 [(set VR128:$dst, (v2f64 (fsub VR128:$src1,
977 (load addr:$src2))))]>;
980 def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
981 int_x86_sse_sqrt_ps>;
982 def SQRTPSm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}",
983 int_x86_sse_sqrt_ps>;
984 def SQRTPDr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}",
985 int_x86_sse2_sqrt_pd>;
986 def SQRTPDm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}",
987 int_x86_sse2_sqrt_pd>;
989 def RSQRTPSr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}",
990 int_x86_sse_rsqrt_ps>;
991 def RSQRTPSm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}",
992 int_x86_sse_rsqrt_ps>;
993 def RCPPSr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}",
995 def RCPPSm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}",
998 let isTwoAddress = 1 in {
999 def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1000 int_x86_sse_max_ps>;
1001 def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1002 int_x86_sse_max_ps>;
1003 def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1004 int_x86_sse2_max_pd>;
1005 def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1006 int_x86_sse2_max_pd>;
1007 def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}",
1008 int_x86_sse_min_ps>;
1009 def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}",
1010 int_x86_sse_min_ps>;
1011 def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1012 int_x86_sse2_min_pd>;
1013 def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1014 int_x86_sse2_min_pd>;
1018 let isTwoAddress = 1 in {
1019 let isCommutable = 1 in {
1020 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1021 "andps {$src2, $dst|$dst, $src2}",
1022 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1023 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1024 "andpd {$src2, $dst|$dst, $src2}",
1026 (and (bc_v2i64 (v2f64 VR128:$src1)),
1027 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1028 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1029 "orps {$src2, $dst|$dst, $src2}",
1030 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1031 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1032 "orpd {$src2, $dst|$dst, $src2}",
1034 (or (bc_v2i64 (v2f64 VR128:$src1)),
1035 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1036 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1037 "xorps {$src2, $dst|$dst, $src2}",
1038 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1039 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1040 "xorpd {$src2, $dst|$dst, $src2}",
1042 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1043 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1045 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1046 "andps {$src2, $dst|$dst, $src2}",
1047 [(set VR128:$dst, (and VR128:$src1,
1048 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1049 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1050 "andpd {$src2, $dst|$dst, $src2}",
1052 (and (bc_v2i64 (v2f64 VR128:$src1)),
1053 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1054 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1055 "orps {$src2, $dst|$dst, $src2}",
1056 [(set VR128:$dst, (or VR128:$src1,
1057 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1058 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1059 "orpd {$src2, $dst|$dst, $src2}",
1061 (or (bc_v2i64 (v2f64 VR128:$src1)),
1062 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1063 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1064 "xorps {$src2, $dst|$dst, $src2}",
1065 [(set VR128:$dst, (xor VR128:$src1,
1066 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1067 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1068 "xorpd {$src2, $dst|$dst, $src2}",
1070 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1071 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1072 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1073 "andnps {$src2, $dst|$dst, $src2}",
1074 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1075 (bc_v2i64 (v4i32 immAllOnesV))),
1077 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1078 "andnps {$src2, $dst|$dst, $src2}",
1079 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1080 (bc_v2i64 (v4i32 immAllOnesV))),
1081 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1082 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1083 "andnpd {$src2, $dst|$dst, $src2}",
1085 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1086 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1087 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1088 "andnpd {$src2, $dst|$dst, $src2}",
1090 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1091 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1094 let isTwoAddress = 1 in {
1095 def CMPPSrr : PSIi8<0xC2, MRMSrcReg,
1096 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1097 "cmp${cc}ps {$src, $dst|$dst, $src}",
1098 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1099 VR128:$src, imm:$cc))]>;
1100 def CMPPSrm : PSIi8<0xC2, MRMSrcMem,
1101 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1102 "cmp${cc}ps {$src, $dst|$dst, $src}",
1103 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1104 (load addr:$src), imm:$cc))]>;
1105 def CMPPDrr : PDIi8<0xC2, MRMSrcReg,
1106 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1107 "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
1108 def CMPPDrm : PDIi8<0xC2, MRMSrcMem,
1109 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1110 "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
1113 // Shuffle and unpack instructions
1114 let isTwoAddress = 1 in {
1115 def SHUFPSrr : PSIi8<0xC6, MRMSrcReg,
1116 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1117 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1118 [(set VR128:$dst, (v4f32 (vector_shuffle
1119 VR128:$src1, VR128:$src2,
1120 SHUFP_shuffle_mask:$src3)))]>;
1121 def SHUFPSrm : PSIi8<0xC6, MRMSrcMem,
1122 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1123 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1124 [(set VR128:$dst, (v4f32 (vector_shuffle
1125 VR128:$src1, (load addr:$src2),
1126 SHUFP_shuffle_mask:$src3)))]>;
1127 def SHUFPDrr : PDIi8<0xC6, MRMSrcReg,
1128 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1129 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1130 [(set VR128:$dst, (v2f64 (vector_shuffle
1131 VR128:$src1, VR128:$src2,
1132 SHUFP_shuffle_mask:$src3)))]>;
1133 def SHUFPDrm : PDIi8<0xC6, MRMSrcMem,
1134 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1135 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1136 [(set VR128:$dst, (v2f64 (vector_shuffle
1137 VR128:$src1, (load addr:$src2),
1138 SHUFP_shuffle_mask:$src3)))]>;
1140 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1141 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1142 "unpckhps {$src2, $dst|$dst, $src2}",
1143 [(set VR128:$dst, (v4f32 (vector_shuffle
1144 VR128:$src1, VR128:$src2,
1145 UNPCKH_shuffle_mask)))]>;
1146 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1147 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1148 "unpckhps {$src2, $dst|$dst, $src2}",
1149 [(set VR128:$dst, (v4f32 (vector_shuffle
1150 VR128:$src1, (load addr:$src2),
1151 UNPCKH_shuffle_mask)))]>;
1152 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1153 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1154 "unpckhpd {$src2, $dst|$dst, $src2}",
1155 [(set VR128:$dst, (v2f64 (vector_shuffle
1156 VR128:$src1, VR128:$src2,
1157 UNPCKH_shuffle_mask)))]>;
1158 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1159 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1160 "unpckhpd {$src2, $dst|$dst, $src2}",
1161 [(set VR128:$dst, (v2f64 (vector_shuffle
1162 VR128:$src1, (load addr:$src2),
1163 UNPCKH_shuffle_mask)))]>;
1165 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1166 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1167 "unpcklps {$src2, $dst|$dst, $src2}",
1168 [(set VR128:$dst, (v4f32 (vector_shuffle
1169 VR128:$src1, VR128:$src2,
1170 UNPCKL_shuffle_mask)))]>;
1171 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1172 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1173 "unpcklps {$src2, $dst|$dst, $src2}",
1174 [(set VR128:$dst, (v4f32 (vector_shuffle
1175 VR128:$src1, (load addr:$src2),
1176 UNPCKL_shuffle_mask)))]>;
1177 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1178 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1179 "unpcklpd {$src2, $dst|$dst, $src2}",
1180 [(set VR128:$dst, (v2f64 (vector_shuffle
1181 VR128:$src1, VR128:$src2,
1182 UNPCKL_shuffle_mask)))]>;
1183 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1184 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1185 "unpcklpd {$src2, $dst|$dst, $src2}",
1186 [(set VR128:$dst, (v2f64 (vector_shuffle
1187 VR128:$src1, (load addr:$src2),
1188 UNPCKL_shuffle_mask)))]>;
1192 let isTwoAddress = 1 in {
1193 def HADDPSrr : S3S_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1194 int_x86_sse3_hadd_ps>;
1195 def HADDPSrm : S3S_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1196 int_x86_sse3_hadd_ps>;
1197 def HADDPDrr : S3D_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1198 int_x86_sse3_hadd_pd>;
1199 def HADDPDrm : S3D_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1200 int_x86_sse3_hadd_pd>;
1201 def HSUBPSrr : S3S_Intrr<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
1202 int_x86_sse3_hsub_ps>;
1203 def HSUBPSrm : S3S_Intrm<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
1204 int_x86_sse3_hsub_ps>;
1205 def HSUBPDrr : S3D_Intrr<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
1206 int_x86_sse3_hsub_pd>;
1207 def HSUBPDrm : S3D_Intrm<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
1208 int_x86_sse3_hsub_pd>;
1211 //===----------------------------------------------------------------------===//
1212 // SSE integer instructions
1213 //===----------------------------------------------------------------------===//
1215 // Move Instructions
1216 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1217 "movdqa {$src, $dst|$dst, $src}", []>;
1218 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1219 "movdqa {$src, $dst|$dst, $src}",
1220 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1221 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1222 "movdqa {$src, $dst|$dst, $src}",
1223 [(store (v2i64 VR128:$src), addr:$dst)]>;
1225 // 128-bit Integer Arithmetic
1226 let isTwoAddress = 1 in {
1227 let isCommutable = 1 in {
1228 def PADDBrr : PDI<0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1229 "paddb {$src2, $dst|$dst, $src2}",
1230 [(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))]>;
1231 def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1232 "paddw {$src2, $dst|$dst, $src2}",
1233 [(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))]>;
1234 def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1235 "paddd {$src2, $dst|$dst, $src2}",
1236 [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
1238 def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1239 "paddq {$src2, $dst|$dst, $src2}",
1240 [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
1242 def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1243 "paddb {$src2, $dst|$dst, $src2}",
1244 [(set VR128:$dst, (v16i8 (add VR128:$src1,
1245 (load addr:$src2))))]>;
1246 def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1247 "paddw {$src2, $dst|$dst, $src2}",
1248 [(set VR128:$dst, (v8i16 (add VR128:$src1,
1249 (load addr:$src2))))]>;
1250 def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1251 "paddd {$src2, $dst|$dst, $src2}",
1252 [(set VR128:$dst, (v4i32 (add VR128:$src1,
1253 (load addr:$src2))))]>;
1254 def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1255 "paddd {$src2, $dst|$dst, $src2}",
1256 [(set VR128:$dst, (v2i64 (add VR128:$src1,
1257 (load addr:$src2))))]>;
1259 def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1260 "psubb {$src2, $dst|$dst, $src2}",
1261 [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
1262 def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1263 "psubw {$src2, $dst|$dst, $src2}",
1264 [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))]>;
1265 def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1266 "psubd {$src2, $dst|$dst, $src2}",
1267 [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
1268 def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1269 "psubq {$src2, $dst|$dst, $src2}",
1270 [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
1272 def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1273 "psubb {$src2, $dst|$dst, $src2}",
1274 [(set VR128:$dst, (v16i8 (sub VR128:$src1,
1275 (load addr:$src2))))]>;
1276 def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1277 "psubw {$src2, $dst|$dst, $src2}",
1278 [(set VR128:$dst, (v8i16 (sub VR128:$src1,
1279 (load addr:$src2))))]>;
1280 def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1281 "psubd {$src2, $dst|$dst, $src2}",
1282 [(set VR128:$dst, (v4i32 (sub VR128:$src1,
1283 (load addr:$src2))))]>;
1284 def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1285 "psubd {$src2, $dst|$dst, $src2}",
1286 [(set VR128:$dst, (v2i64 (sub VR128:$src1,
1287 (load addr:$src2))))]>;
1290 let isTwoAddress = 1 in {
1291 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1292 "pslldq {$src2, $dst|$dst, $src2}", []>;
1293 def PSRLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1294 "psrldq {$src2, $dst|$dst, $src2}", []>;
1298 let isTwoAddress = 1 in {
1299 let isCommutable = 1 in {
1300 def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1301 "pand {$src2, $dst|$dst, $src2}",
1302 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1304 def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1305 "pand {$src2, $dst|$dst, $src2}",
1306 [(set VR128:$dst, (v2i64 (and VR128:$src1,
1307 (load addr:$src2))))]>;
1308 def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1309 "por {$src2, $dst|$dst, $src2}",
1310 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1312 def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1313 "por {$src2, $dst|$dst, $src2}",
1314 [(set VR128:$dst, (v2i64 (or VR128:$src1,
1315 (load addr:$src2))))]>;
1316 def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1317 "pxor {$src2, $dst|$dst, $src2}",
1318 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1320 def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1321 "pxor {$src2, $dst|$dst, $src2}",
1322 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
1323 (load addr:$src2))))]>;
1326 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1327 "pandn {$src2, $dst|$dst, $src2}",
1328 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1331 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1332 "pandn {$src2, $dst|$dst, $src2}",
1333 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1334 (load addr:$src2))))]>;
1337 // Pack instructions
1338 let isTwoAddress = 1 in {
1339 def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1341 "packsswb {$src2, $dst|$dst, $src2}",
1342 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1345 def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1347 "packsswb {$src2, $dst|$dst, $src2}",
1348 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1350 (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
1351 def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1353 "packssdw {$src2, $dst|$dst, $src2}",
1354 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1357 def PACKSSDWrm : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1359 "packssdw {$src2, $dst|$dst, $src2}",
1360 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1362 (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
1363 def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1365 "packuswb {$src2, $dst|$dst, $src2}",
1366 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1369 def PACKUSWBrm : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1371 "packuswb {$src2, $dst|$dst, $src2}",
1372 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1374 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1377 // Shuffle and unpack instructions
1378 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1379 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1380 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1381 [(set VR128:$dst, (v4i32 (vector_shuffle
1382 VR128:$src1, (undef),
1383 PSHUFD_shuffle_mask:$src2)))]>;
1384 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1385 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1386 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1387 [(set VR128:$dst, (v4i32 (vector_shuffle
1388 (bc_v4i32 (loadv2i64 addr:$src1)),
1390 PSHUFD_shuffle_mask:$src2)))]>;
1392 // SSE2 with ImmT == Imm8 and XS prefix.
1393 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1394 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1395 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1396 [(set VR128:$dst, (v8i16 (vector_shuffle
1397 VR128:$src1, (undef),
1398 PSHUFHW_shuffle_mask:$src2)))]>,
1399 XS, Requires<[HasSSE2]>;
1400 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1401 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1402 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1403 [(set VR128:$dst, (v8i16 (vector_shuffle
1404 (bc_v8i16 (loadv2i64 addr:$src1)),
1406 PSHUFHW_shuffle_mask:$src2)))]>,
1407 XS, Requires<[HasSSE2]>;
1409 // SSE2 with ImmT == Imm8 and XD prefix.
1410 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1411 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1412 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1413 [(set VR128:$dst, (v8i16 (vector_shuffle
1414 VR128:$src1, (undef),
1415 PSHUFLW_shuffle_mask:$src2)))]>,
1416 XD, Requires<[HasSSE2]>;
1417 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1418 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1419 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1420 [(set VR128:$dst, (v8i16 (vector_shuffle
1421 (bc_v8i16 (loadv2i64 addr:$src1)),
1423 PSHUFLW_shuffle_mask:$src2)))]>,
1424 XD, Requires<[HasSSE2]>;
1426 let isTwoAddress = 1 in {
1427 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1428 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1429 "punpcklbw {$src2, $dst|$dst, $src2}",
1431 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1432 UNPCKL_shuffle_mask)))]>;
1433 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1434 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1435 "punpcklbw {$src2, $dst|$dst, $src2}",
1437 (v16i8 (vector_shuffle VR128:$src1,
1438 (bc_v16i8 (loadv2i64 addr:$src2)),
1439 UNPCKL_shuffle_mask)))]>;
1440 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1441 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1442 "punpcklwd {$src2, $dst|$dst, $src2}",
1444 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1445 UNPCKL_shuffle_mask)))]>;
1446 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1447 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1448 "punpcklwd {$src2, $dst|$dst, $src2}",
1450 (v8i16 (vector_shuffle VR128:$src1,
1451 (bc_v8i16 (loadv2i64 addr:$src2)),
1452 UNPCKL_shuffle_mask)))]>;
1453 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1454 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1455 "punpckldq {$src2, $dst|$dst, $src2}",
1457 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1458 UNPCKL_shuffle_mask)))]>;
1459 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1460 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1461 "punpckldq {$src2, $dst|$dst, $src2}",
1463 (v4i32 (vector_shuffle VR128:$src1,
1464 (bc_v4i32 (loadv2i64 addr:$src2)),
1465 UNPCKL_shuffle_mask)))]>;
1466 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1467 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1468 "punpcklqdq {$src2, $dst|$dst, $src2}",
1470 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1471 UNPCKL_shuffle_mask)))]>;
1472 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1473 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1474 "punpcklqdq {$src2, $dst|$dst, $src2}",
1476 (v2i64 (vector_shuffle VR128:$src1,
1477 (loadv2i64 addr:$src2),
1478 UNPCKL_shuffle_mask)))]>;
1480 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1481 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1482 "punpckhbw {$src2, $dst|$dst, $src2}",
1484 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1485 UNPCKH_shuffle_mask)))]>;
1486 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1487 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1488 "punpckhbw {$src2, $dst|$dst, $src2}",
1490 (v16i8 (vector_shuffle VR128:$src1,
1491 (bc_v16i8 (loadv2i64 addr:$src2)),
1492 UNPCKH_shuffle_mask)))]>;
1493 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1494 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1495 "punpckhwd {$src2, $dst|$dst, $src2}",
1497 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1498 UNPCKH_shuffle_mask)))]>;
1499 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1500 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1501 "punpckhwd {$src2, $dst|$dst, $src2}",
1503 (v8i16 (vector_shuffle VR128:$src1,
1504 (bc_v8i16 (loadv2i64 addr:$src2)),
1505 UNPCKH_shuffle_mask)))]>;
1506 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1507 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1508 "punpckhdq {$src2, $dst|$dst, $src2}",
1510 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1511 UNPCKH_shuffle_mask)))]>;
1512 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1513 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1514 "punpckhdq {$src2, $dst|$dst, $src2}",
1516 (v4i32 (vector_shuffle VR128:$src1,
1517 (bc_v4i32 (loadv2i64 addr:$src2)),
1518 UNPCKH_shuffle_mask)))]>;
1519 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1520 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1521 "punpckhdq {$src2, $dst|$dst, $src2}",
1523 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1524 UNPCKH_shuffle_mask)))]>;
1525 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1526 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1527 "punpckhqdq {$src2, $dst|$dst, $src2}",
1529 (v2i64 (vector_shuffle VR128:$src1,
1530 (loadv2i64 addr:$src2),
1531 UNPCKH_shuffle_mask)))]>;
1535 def PEXTRWr : PDIi8<0xC5, MRMSrcReg,
1536 (ops R32:$dst, VR128:$src1, i32i8imm:$src2),
1537 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1538 [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1),
1539 (i32 imm:$src2)))]>;
1540 def PEXTRWm : PDIi8<0xC5, MRMSrcMem,
1541 (ops R32:$dst, i128mem:$src1, i32i8imm:$src2),
1542 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1543 [(set R32:$dst, (X86pextrw
1544 (bc_v8i16 (loadv2i64 addr:$src1)),
1545 (i32 imm:$src2)))]>;
1547 let isTwoAddress = 1 in {
1548 def PINSRWr : PDIi8<0xC4, MRMSrcReg,
1549 (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
1550 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1551 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1552 R32:$src2, (i32 imm:$src3))))]>;
1553 def PINSRWm : PDIi8<0xC4, MRMSrcMem,
1554 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
1555 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1557 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1558 (i32 (anyext (loadi16 addr:$src2))),
1559 (i32 imm:$src3))))]>;
1562 //===----------------------------------------------------------------------===//
1563 // Miscellaneous Instructions
1564 //===----------------------------------------------------------------------===//
1567 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
1568 "movmskps {$src, $dst|$dst, $src}",
1569 [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1570 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
1571 "movmskpd {$src, $dst|$dst, $src}",
1572 [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))]>;
1574 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
1575 "pmovmskb {$src, $dst|$dst, $src}",
1576 [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1578 // Conditional store
1579 def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
1580 "maskmovdqu {$mask, $src|$src, $mask}",
1581 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1584 // Prefetching loads
1585 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
1586 "prefetcht0 $src", []>;
1587 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
1588 "prefetcht1 $src", []>;
1589 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
1590 "prefetcht2 $src", []>;
1591 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
1592 "prefetchtnta $src", []>;
1594 // Non-temporal stores
1595 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1596 "movntps {$src, $dst|$dst, $src}",
1597 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1598 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1599 "movntpd {$src, $dst|$dst, $src}",
1600 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1601 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1602 "movntdq {$src, $dst|$dst, $src}",
1603 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1604 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
1605 "movnti {$src, $dst|$dst, $src}",
1606 [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>,
1607 TB, Requires<[HasSSE2]>;
1610 def SFENCE : I<0xAE, MRM7m, (ops),
1611 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
1614 def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),
1616 [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
1617 def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
1619 [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
1621 //===----------------------------------------------------------------------===//
1622 // Alias Instructions
1623 //===----------------------------------------------------------------------===//
1625 // Alias instructions that map zero vector to pxor / xorp* for sse.
1626 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1627 def V_SET0_PI : PDI<0xEF, MRMInitReg, (ops VR128:$dst),
1629 [(set VR128:$dst, (v2i64 immAllZerosV))]>;
1630 def V_SET0_PS : PSI<0x57, MRMInitReg, (ops VR128:$dst),
1632 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1633 def V_SET0_PD : PDI<0x57, MRMInitReg, (ops VR128:$dst),
1635 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1637 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
1638 "pcmpeqd $dst, $dst",
1639 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
1641 // FR32 / FR64 to 128-bit vector conversion.
1642 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
1643 "movss {$src, $dst|$dst, $src}",
1645 (v4f32 (scalar_to_vector FR32:$src)))]>;
1646 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1647 "movss {$src, $dst|$dst, $src}",
1649 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1650 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
1651 "movsd {$src, $dst|$dst, $src}",
1653 (v2f64 (scalar_to_vector FR64:$src)))]>;
1654 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1655 "movsd {$src, $dst|$dst, $src}",
1657 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
1659 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
1660 "movd {$src, $dst|$dst, $src}",
1662 (v4i32 (scalar_to_vector R32:$src)))]>;
1663 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1664 "movd {$src, $dst|$dst, $src}",
1666 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
1667 // SSE2 instructions with XS prefix
1668 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
1669 "movq {$src, $dst|$dst, $src}",
1671 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
1672 Requires<[HasSSE2]>;
1673 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1674 "movq {$src, $dst|$dst, $src}",
1676 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
1677 Requires<[HasSSE2]>;
1678 // FIXME: may not be able to eliminate this movss with coalescing the src and
1679 // dest register classes are different. We really want to write this pattern
1681 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (i32 0))),
1682 // (f32 FR32:$src)>;
1683 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
1684 "movss {$src, $dst|$dst, $src}",
1685 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1687 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
1688 "movss {$src, $dst|$dst, $src}",
1689 [(store (f32 (vector_extract (v4f32 VR128:$src),
1690 (i32 0))), addr:$dst)]>;
1691 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
1692 "movsd {$src, $dst|$dst, $src}",
1693 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
1695 def MOVPDI2DIrr : PDI<0x6E, MRMSrcReg, (ops R32:$dst, VR128:$src),
1696 "movd {$src, $dst|$dst, $src}",
1697 [(set R32:$dst, (vector_extract (v4i32 VR128:$src),
1699 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
1700 "movd {$src, $dst|$dst, $src}",
1701 [(store (i32 (vector_extract (v4i32 VR128:$src),
1702 (i32 0))), addr:$dst)]>;
1704 // Move to lower bits of a VR128, leaving upper bits alone.
1705 // Three operand (but two address) aliases.
1706 let isTwoAddress = 1 in {
1707 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
1708 "movss {$src2, $dst|$dst, $src2}", []>;
1709 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
1710 "movsd {$src2, $dst|$dst, $src2}", []>;
1711 def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2),
1712 "movd {$src2, $dst|$dst, $src2}", []>;
1714 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1715 "movss {$src2, $dst|$dst, $src2}",
1717 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1718 MOVS_shuffle_mask)))]>;
1719 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1720 "movsd {$src2, $dst|$dst, $src2}",
1722 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
1723 MOVS_shuffle_mask)))]>;
1726 // Store / copy lower 64-bits of a XMM register.
1727 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1728 "movq {$src, $dst|$dst, $src}",
1729 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
1731 // FIXME: Temporary workaround since 2-wide shuffle is broken.
1732 def MOVLQ128rr : PDI<0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1733 "movq {$src, $dst|$dst, $src}",
1734 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>;
1736 // Move to lower bits of a VR128 and zeroing upper bits.
1737 // Loading from memory automatically zeroing upper bits.
1738 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1739 "movss {$src, $dst|$dst, $src}",
1741 (v4f32 (X86zexts2vec (loadf32 addr:$src))))]>;
1742 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1743 "movsd {$src, $dst|$dst, $src}",
1745 (v2f64 (X86zexts2vec (loadf64 addr:$src))))]>;
1746 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1747 "movd {$src, $dst|$dst, $src}",
1749 (v4i32 (X86zexts2vec (loadi32 addr:$src))))]>;
1750 def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1751 "movq {$src, $dst|$dst, $src}",
1753 (bc_v2i64 (v2f64 (X86zexts2vec
1754 (loadf64 addr:$src)))))]>;
1756 //===----------------------------------------------------------------------===//
1757 // Non-Instruction Patterns
1758 //===----------------------------------------------------------------------===//
1760 // 128-bit vector undef's.
1761 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1762 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1763 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1764 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1765 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1767 // 128-bit vector all zero's.
1768 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0_PI))>, Requires<[HasSSE2]>;
1769 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0_PI))>, Requires<[HasSSE2]>;
1770 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0_PI))>, Requires<[HasSSE2]>;
1772 // 128-bit vector all one's.
1773 def : Pat<(v16i8 immAllOnesV), (v16i8 (V_SETALLONES))>, Requires<[HasSSE2]>;
1774 def : Pat<(v8i16 immAllOnesV), (v8i16 (V_SETALLONES))>, Requires<[HasSSE2]>;
1775 def : Pat<(v4i32 immAllOnesV), (v4i32 (V_SETALLONES))>, Requires<[HasSSE2]>;
1776 def : Pat<(v2i64 immAllOnesV), (v2i64 (V_SETALLONES))>, Requires<[HasSSE2]>;
1777 def : Pat<(v4f32 immAllOnesV), (v4f32 (V_SETALLONES))>, Requires<[HasSSE1]>;
1779 // Store 128-bit integer vector values.
1780 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1781 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1782 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1783 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1784 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1785 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1787 // Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
1789 def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
1790 Requires<[HasSSE2]>;
1791 def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
1792 Requires<[HasSSE2]>;
1795 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
1796 Requires<[HasSSE2]>;
1797 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>,
1798 Requires<[HasSSE2]>;
1799 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>,
1800 Requires<[HasSSE2]>;
1801 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>,
1802 Requires<[HasSSE2]>;
1803 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>,
1804 Requires<[HasSSE2]>;
1805 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
1806 Requires<[HasSSE2]>;
1807 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
1808 Requires<[HasSSE2]>;
1809 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
1810 Requires<[HasSSE2]>;
1811 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>,
1812 Requires<[HasSSE2]>;
1813 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
1814 Requires<[HasSSE2]>;
1815 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
1816 Requires<[HasSSE2]>;
1817 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
1818 Requires<[HasSSE2]>;
1819 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
1820 Requires<[HasSSE2]>;
1821 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>,
1822 Requires<[HasSSE2]>;
1823 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>,
1824 Requires<[HasSSE2]>;
1825 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
1826 Requires<[HasSSE2]>;
1827 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
1828 Requires<[HasSSE2]>;
1829 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
1830 Requires<[HasSSE2]>;
1831 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>,
1832 Requires<[HasSSE2]>;
1833 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>,
1834 Requires<[HasSSE2]>;
1835 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>,
1836 Requires<[HasSSE2]>;
1837 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
1838 Requires<[HasSSE2]>;
1839 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>,
1840 Requires<[HasSSE2]>;
1841 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>,
1842 Requires<[HasSSE2]>;
1843 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>,
1844 Requires<[HasSSE2]>;
1845 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>,
1846 Requires<[HasSSE2]>;
1847 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>,
1848 Requires<[HasSSE2]>;
1849 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>,
1850 Requires<[HasSSE2]>;
1851 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>,
1852 Requires<[HasSSE2]>;
1853 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>,
1854 Requires<[HasSSE2]>;
1856 // Zeroing a VR128 then do a MOVS* to the lower bits.
1857 def : Pat<(v2f64 (X86zexts2vec FR64:$src)),
1858 (MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>;
1859 def : Pat<(v4f32 (X86zexts2vec FR32:$src)),
1860 (MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>;
1861 def : Pat<(v4i32 (X86zexts2vec R32:$src)),
1862 (MOVLDI2PDIrr (V_SET0_PI), R32:$src)>, Requires<[HasSSE2]>;
1863 def : Pat<(v8i16 (X86zexts2vec R16:$src)),
1864 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr16 R16:$src))>, Requires<[HasSSE2]>;
1865 def : Pat<(v16i8 (X86zexts2vec R8:$src)),
1866 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
1868 // Splat v2f64 / v2i64
1869 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_mask:$sm),
1870 (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
1871 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_mask:$sm),
1872 (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
1875 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
1876 (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
1877 Requires<[HasSSE1]>;
1879 // Special unary SHUFPSrr case.
1880 // FIXME: when we want non two-address code, then we should use PSHUFD?
1881 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
1882 SHUFP_unary_shuffle_mask:$sm),
1883 (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm))>,
1884 Requires<[HasSSE1]>;
1885 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
1886 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
1887 SHUFP_unary_shuffle_mask:$sm),
1888 (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm))>,
1889 Requires<[HasSSE2]>;
1890 // Special binary v4i32 shuffle cases with SHUFPS.
1891 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
1892 PSHUFD_binary_shuffle_mask:$sm),
1893 (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
1894 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
1895 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
1896 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
1897 (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
1898 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
1900 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
1901 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
1902 UNPCKL_v_undef_shuffle_mask)),
1903 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1904 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
1905 UNPCKL_v_undef_shuffle_mask)),
1906 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1907 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
1908 UNPCKL_v_undef_shuffle_mask)),
1909 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1910 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1911 UNPCKL_v_undef_shuffle_mask)),
1912 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
1914 // 128-bit logical shifts
1915 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1916 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
1917 Requires<[HasSSE2]>;
1918 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1919 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
1920 Requires<[HasSSE2]>;
1922 // Some special case pandn patterns.
1923 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
1925 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
1926 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
1928 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
1929 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
1931 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
1933 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
1934 (load addr:$src2))),
1935 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
1936 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
1937 (load addr:$src2))),
1938 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
1939 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
1940 (load addr:$src2))),
1941 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;