1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
22 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
23 [SDNPCommutative, SDNPAssociative]>;
24 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
25 [SDNPCommutative, SDNPAssociative]>;
26 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
28 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
30 def X86s2vec : SDNode<"X86ISD::S2VEC",
31 SDTypeProfile<1, 1, []>, []>;
32 def X86pextrw : SDNode<"X86ISD::PEXTRW",
33 SDTypeProfile<1, 2, []>, []>;
34 def X86pinsrw : SDNode<"X86ISD::PINSRW",
35 SDTypeProfile<1, 3, []>, []>;
37 //===----------------------------------------------------------------------===//
38 // SSE pattern fragments
39 //===----------------------------------------------------------------------===//
41 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
42 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
44 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
45 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
46 def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
47 def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
48 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
49 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
51 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
52 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
53 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
54 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
55 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
56 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
58 def fp32imm0 : PatLeaf<(f32 fpimm), [{
59 return N->isExactlyValue(+0.0);
62 def PSxLDQ_imm : SDNodeXForm<imm, [{
63 // Transformation function: imm >> 3
64 return getI32Imm(N->getValue() >> 3);
67 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
69 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
70 return getI8Imm(X86::getShuffleSHUFImmediate(N));
73 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
75 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
76 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
79 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
81 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
82 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
85 def SSE_splat_mask : PatLeaf<(build_vector), [{
86 return X86::isSplatMask(N);
87 }], SHUFFLE_get_shuf_imm>;
89 def SSE_splat_v2_mask : PatLeaf<(build_vector), [{
90 return X86::isSplatMask(N);
93 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
94 return X86::isMOVHLPSMask(N);
97 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
98 return X86::isMOVHPMask(N);
101 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
102 return X86::isMOVLPMask(N);
105 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
106 return X86::isMOVLMask(N);
109 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
110 return X86::isMOVSHDUPMask(N);
113 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
114 return X86::isMOVSLDUPMask(N);
117 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
118 return X86::isUNPCKLMask(N);
121 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
122 return X86::isUNPCKHMask(N);
125 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
126 return X86::isUNPCKL_v_undef_Mask(N);
129 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
130 return X86::isPSHUFDMask(N);
131 }], SHUFFLE_get_shuf_imm>;
133 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
134 return X86::isPSHUFHWMask(N);
135 }], SHUFFLE_get_pshufhw_imm>;
137 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
138 return X86::isPSHUFLWMask(N);
139 }], SHUFFLE_get_pshuflw_imm>;
141 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
142 return X86::isPSHUFDMask(N);
143 }], SHUFFLE_get_shuf_imm>;
145 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
146 return X86::isSHUFPMask(N);
147 }], SHUFFLE_get_shuf_imm>;
149 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
150 return X86::isSHUFPMask(N);
151 }], SHUFFLE_get_shuf_imm>;
153 //===----------------------------------------------------------------------===//
154 // SSE scalar FP Instructions
155 //===----------------------------------------------------------------------===//
157 // Instruction templates
158 // SSI - SSE1 instructions with XS prefix.
159 // SDI - SSE2 instructions with XD prefix.
160 // PSI - SSE1 instructions with TB prefix.
161 // PDI - SSE2 instructions with TB and OpSize prefixes.
162 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
163 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
164 // S3I - SSE3 instructions with TB and OpSize prefixes.
165 // S3SI - SSE3 instructions with XS prefix.
166 // S3DI - SSE3 instructions with XD prefix.
167 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
168 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
169 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
170 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
171 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
172 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
173 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
174 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
175 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
176 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
177 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
178 : Ii8<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
180 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
181 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
182 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
183 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
184 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
185 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
187 //===----------------------------------------------------------------------===//
188 // Helpers for defining instructions that directly correspond to intrinsics.
189 class SS_Intr<bits<8> o, string asm, Intrinsic IntId>
190 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
191 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
192 class SS_Intm<bits<8> o, string asm, Intrinsic IntId>
193 : SSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
194 [(set VR128:$dst, (v4f32 (IntId (load addr:$src))))]>;
195 class SD_Intr<bits<8> o, string asm, Intrinsic IntId>
196 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
197 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
198 class SD_Intm<bits<8> o, string asm, Intrinsic IntId>
199 : SDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
200 [(set VR128:$dst, (v2f64 (IntId (load addr:$src))))]>;
202 class SS_Intrr<bits<8> o, string asm, Intrinsic IntId>
203 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
204 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
205 class SS_Intrm<bits<8> o, string asm, Intrinsic IntId>
206 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
207 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
208 class SD_Intrr<bits<8> o, string asm, Intrinsic IntId>
209 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
210 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
211 class SD_Intrm<bits<8> o, string asm, Intrinsic IntId>
212 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
213 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
215 class PS_Intr<bits<8> o, string asm, Intrinsic IntId>
216 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
217 [(set VR128:$dst, (IntId VR128:$src))]>;
218 class PS_Intm<bits<8> o, string asm, Intrinsic IntId>
219 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
220 [(set VR128:$dst, (IntId (loadv4f32 addr:$src)))]>;
221 class PD_Intr<bits<8> o, string asm, Intrinsic IntId>
222 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
223 [(set VR128:$dst, (IntId VR128:$src))]>;
224 class PD_Intm<bits<8> o, string asm, Intrinsic IntId>
225 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
226 [(set VR128:$dst, (IntId (loadv2f64 addr:$src)))]>;
228 class PS_Intrr<bits<8> o, string asm, Intrinsic IntId>
229 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
230 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
231 class PS_Intrm<bits<8> o, string asm, Intrinsic IntId>
232 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
233 [(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))]>;
234 class PD_Intrr<bits<8> o, string asm, Intrinsic IntId>
235 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
236 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
237 class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
238 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
239 [(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
241 class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
242 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
243 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
244 class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
245 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
246 [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
247 (loadv4f32 addr:$src2))))]>;
248 class S3_Intrr<bits<8> o, string asm, Intrinsic IntId>
249 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
250 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
251 class S3_Intrm<bits<8> o, string asm, Intrinsic IntId>
252 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
253 [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
254 (loadv2f64 addr:$src2))))]>;
256 // Some 'special' instructions
257 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
258 "#IMPLICIT_DEF $dst",
259 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
260 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
261 "#IMPLICIT_DEF $dst",
262 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
264 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
265 // scheduler into a branch sequence.
266 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
267 def CMOV_FR32 : I<0, Pseudo,
268 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
269 "#CMOV_FR32 PSEUDO!",
270 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
271 def CMOV_FR64 : I<0, Pseudo,
272 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
273 "#CMOV_FR64 PSEUDO!",
274 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
275 def CMOV_V4F32 : I<0, Pseudo,
276 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
277 "#CMOV_V4F32 PSEUDO!",
279 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
280 def CMOV_V2F64 : I<0, Pseudo,
281 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
282 "#CMOV_V2F64 PSEUDO!",
284 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
285 def CMOV_V2I64 : I<0, Pseudo,
286 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
287 "#CMOV_V2I64 PSEUDO!",
289 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
293 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
294 "movss {$src, $dst|$dst, $src}", []>;
295 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
296 "movss {$src, $dst|$dst, $src}",
297 [(set FR32:$dst, (loadf32 addr:$src))]>;
298 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
299 "movsd {$src, $dst|$dst, $src}", []>;
300 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
301 "movsd {$src, $dst|$dst, $src}",
302 [(set FR64:$dst, (loadf64 addr:$src))]>;
304 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
305 "movss {$src, $dst|$dst, $src}",
306 [(store FR32:$src, addr:$dst)]>;
307 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
308 "movsd {$src, $dst|$dst, $src}",
309 [(store FR64:$src, addr:$dst)]>;
311 // Arithmetic instructions
312 let isTwoAddress = 1 in {
313 let isCommutable = 1 in {
314 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
315 "addss {$src2, $dst|$dst, $src2}",
316 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
317 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
318 "addsd {$src2, $dst|$dst, $src2}",
319 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
320 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
321 "mulss {$src2, $dst|$dst, $src2}",
322 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
323 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
324 "mulsd {$src2, $dst|$dst, $src2}",
325 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
328 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
329 "addss {$src2, $dst|$dst, $src2}",
330 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
331 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
332 "addsd {$src2, $dst|$dst, $src2}",
333 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
334 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
335 "mulss {$src2, $dst|$dst, $src2}",
336 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
337 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
338 "mulsd {$src2, $dst|$dst, $src2}",
339 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
341 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
342 "divss {$src2, $dst|$dst, $src2}",
343 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
344 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
345 "divss {$src2, $dst|$dst, $src2}",
346 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
347 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
348 "divsd {$src2, $dst|$dst, $src2}",
349 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
350 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
351 "divsd {$src2, $dst|$dst, $src2}",
352 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
354 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
355 "subss {$src2, $dst|$dst, $src2}",
356 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
357 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
358 "subss {$src2, $dst|$dst, $src2}",
359 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
360 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
361 "subsd {$src2, $dst|$dst, $src2}",
362 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
363 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
364 "subsd {$src2, $dst|$dst, $src2}",
365 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
368 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
369 "sqrtss {$src, $dst|$dst, $src}",
370 [(set FR32:$dst, (fsqrt FR32:$src))]>;
371 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
372 "sqrtss {$src, $dst|$dst, $src}",
373 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
374 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
375 "sqrtsd {$src, $dst|$dst, $src}",
376 [(set FR64:$dst, (fsqrt FR64:$src))]>;
377 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
378 "sqrtsd {$src, $dst|$dst, $src}",
379 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
381 def RSQRTSSr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
382 "rsqrtss {$src, $dst|$dst, $src}", []>;
383 def RSQRTSSm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
384 "rsqrtss {$src, $dst|$dst, $src}", []>;
385 def RCPSSr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
386 "rcpss {$src, $dst|$dst, $src}", []>;
387 def RCPSSm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
388 "rcpss {$src, $dst|$dst, $src}", []>;
390 let isTwoAddress = 1 in {
391 let isCommutable = 1 in {
392 def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
393 "maxss {$src2, $dst|$dst, $src2}", []>;
394 def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
395 "maxsd {$src2, $dst|$dst, $src2}", []>;
396 def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
397 "minss {$src2, $dst|$dst, $src2}", []>;
398 def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
399 "minsd {$src2, $dst|$dst, $src2}", []>;
401 def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
402 "maxss {$src2, $dst|$dst, $src2}", []>;
403 def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
404 "maxsd {$src2, $dst|$dst, $src2}", []>;
405 def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
406 "minss {$src2, $dst|$dst, $src2}", []>;
407 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
408 "minsd {$src2, $dst|$dst, $src2}", []>;
411 // Aliases to match intrinsics which expect XMM operand(s).
412 let isTwoAddress = 1 in {
413 let isCommutable = 1 in {
414 def Int_ADDSSrr : SS_Intrr<0x58, "addss {$src2, $dst|$dst, $src2}",
416 def Int_ADDSDrr : SD_Intrr<0x58, "addsd {$src2, $dst|$dst, $src2}",
417 int_x86_sse2_add_sd>;
418 def Int_MULSSrr : SS_Intrr<0x59, "mulss {$src2, $dst|$dst, $src2}",
420 def Int_MULSDrr : SD_Intrr<0x59, "mulsd {$src2, $dst|$dst, $src2}",
421 int_x86_sse2_mul_sd>;
424 def Int_ADDSSrm : SS_Intrm<0x58, "addss {$src2, $dst|$dst, $src2}",
426 def Int_ADDSDrm : SD_Intrm<0x58, "addsd {$src2, $dst|$dst, $src2}",
427 int_x86_sse2_add_sd>;
428 def Int_MULSSrm : SS_Intrm<0x59, "mulss {$src2, $dst|$dst, $src2}",
430 def Int_MULSDrm : SD_Intrm<0x59, "mulsd {$src2, $dst|$dst, $src2}",
431 int_x86_sse2_mul_sd>;
433 def Int_DIVSSrr : SS_Intrr<0x5E, "divss {$src2, $dst|$dst, $src2}",
435 def Int_DIVSSrm : SS_Intrm<0x5E, "divss {$src2, $dst|$dst, $src2}",
437 def Int_DIVSDrr : SD_Intrr<0x5E, "divsd {$src2, $dst|$dst, $src2}",
438 int_x86_sse2_div_sd>;
439 def Int_DIVSDrm : SD_Intrm<0x5E, "divsd {$src2, $dst|$dst, $src2}",
440 int_x86_sse2_div_sd>;
442 def Int_SUBSSrr : SS_Intrr<0x5C, "subss {$src2, $dst|$dst, $src2}",
444 def Int_SUBSSrm : SS_Intrm<0x5C, "subss {$src2, $dst|$dst, $src2}",
446 def Int_SUBSDrr : SD_Intrr<0x5C, "subsd {$src2, $dst|$dst, $src2}",
447 int_x86_sse2_sub_sd>;
448 def Int_SUBSDrm : SD_Intrm<0x5C, "subsd {$src2, $dst|$dst, $src2}",
449 int_x86_sse2_sub_sd>;
452 def Int_SQRTSSr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}",
453 int_x86_sse_sqrt_ss>;
454 def Int_SQRTSSm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}",
455 int_x86_sse_sqrt_ss>;
456 def Int_SQRTSDr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}",
457 int_x86_sse2_sqrt_sd>;
458 def Int_SQRTSDm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}",
459 int_x86_sse2_sqrt_sd>;
461 def Int_RSQRTSSr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}",
462 int_x86_sse_rsqrt_ss>;
463 def Int_RSQRTSSm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}",
464 int_x86_sse_rsqrt_ss>;
465 def Int_RCPSSr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}",
467 def Int_RCPSSm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}",
470 let isTwoAddress = 1 in {
471 let isCommutable = 1 in {
472 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}",
474 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
475 int_x86_sse2_max_sd>;
476 def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}",
478 def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}",
479 int_x86_sse2_min_sd>;
481 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}",
483 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
484 int_x86_sse2_max_sd>;
485 def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}",
487 def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}",
488 int_x86_sse2_min_sd>;
491 // Conversion instructions
492 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src),
493 "cvttss2si {$src, $dst|$dst, $src}",
494 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
495 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
496 "cvttss2si {$src, $dst|$dst, $src}",
497 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
498 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src),
499 "cvttsd2si {$src, $dst|$dst, $src}",
500 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
501 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src),
502 "cvttsd2si {$src, $dst|$dst, $src}",
503 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
504 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
505 "cvtsd2ss {$src, $dst|$dst, $src}",
506 [(set FR32:$dst, (fround FR64:$src))]>;
507 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
508 "cvtsd2ss {$src, $dst|$dst, $src}",
509 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
510 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src),
511 "cvtsi2ss {$src, $dst|$dst, $src}",
512 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
513 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
514 "cvtsi2ss {$src, $dst|$dst, $src}",
515 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
516 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src),
517 "cvtsi2sd {$src, $dst|$dst, $src}",
518 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
519 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
520 "cvtsi2sd {$src, $dst|$dst, $src}",
521 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
523 // SSE2 instructions with XS prefix
524 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
525 "cvtss2sd {$src, $dst|$dst, $src}",
526 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
528 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
529 "cvtss2sd {$src, $dst|$dst, $src}",
530 [(set FR64:$dst, (extload addr:$src, f32))]>, XS,
533 // Match intrinsics which expect XMM operand(s).
534 def Int_CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
535 "cvtss2si {$src, $dst|$dst, $src}",
536 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
537 def Int_CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
538 "cvtss2si {$src, $dst|$dst, $src}",
539 [(set GR32:$dst, (int_x86_sse_cvtss2si
540 (loadv4f32 addr:$src)))]>;
541 def Int_CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
542 "cvtsd2si {$src, $dst|$dst, $src}",
543 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
544 def Int_CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
545 "cvtsd2si {$src, $dst|$dst, $src}",
546 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
547 (loadv2f64 addr:$src)))]>;
549 // Aliases for intrinsics
550 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
551 "cvttss2si {$src, $dst|$dst, $src}",
552 [(set GR32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
553 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
554 "cvttss2si {$src, $dst|$dst, $src}",
555 [(set GR32:$dst, (int_x86_sse_cvttss2si
556 (loadv4f32 addr:$src)))]>;
557 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
558 "cvttsd2si {$src, $dst|$dst, $src}",
559 [(set GR32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
560 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
561 "cvttsd2si {$src, $dst|$dst, $src}",
562 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
563 (loadv2f64 addr:$src)))]>;
565 let isTwoAddress = 1 in {
566 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
567 (ops VR128:$dst, VR128:$src1, GR32:$src2),
568 "cvtsi2ss {$src2, $dst|$dst, $src2}",
569 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
571 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
572 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
573 "cvtsi2ss {$src2, $dst|$dst, $src2}",
574 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
575 (loadi32 addr:$src2)))]>;
578 // Comparison instructions
579 let isTwoAddress = 1 in {
580 def CMPSSrr : SSI<0xC2, MRMSrcReg,
581 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
582 "cmp${cc}ss {$src, $dst|$dst, $src}",
584 def CMPSSrm : SSI<0xC2, MRMSrcMem,
585 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
586 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
587 def CMPSDrr : SDI<0xC2, MRMSrcReg,
588 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
589 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
590 def CMPSDrm : SDI<0xC2, MRMSrcMem,
591 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
592 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
595 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
596 "ucomiss {$src2, $src1|$src1, $src2}",
597 [(X86cmp FR32:$src1, FR32:$src2)]>;
598 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
599 "ucomiss {$src2, $src1|$src1, $src2}",
600 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
601 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
602 "ucomisd {$src2, $src1|$src1, $src2}",
603 [(X86cmp FR64:$src1, FR64:$src2)]>;
604 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
605 "ucomisd {$src2, $src1|$src1, $src2}",
606 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
608 // Aliases to match intrinsics which expect XMM operand(s).
609 let isTwoAddress = 1 in {
610 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
611 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
612 "cmp${cc}ss {$src, $dst|$dst, $src}",
613 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
614 VR128:$src, imm:$cc))]>;
615 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
616 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
617 "cmp${cc}ss {$src, $dst|$dst, $src}",
618 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
619 (load addr:$src), imm:$cc))]>;
620 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
621 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
622 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
623 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
624 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
625 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
628 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
629 "ucomiss {$src2, $src1|$src1, $src2}",
630 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
631 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
632 "ucomiss {$src2, $src1|$src1, $src2}",
633 [(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
634 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
635 "ucomisd {$src2, $src1|$src1, $src2}",
636 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
637 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
638 "ucomisd {$src2, $src1|$src1, $src2}",
639 [(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
641 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
642 "comiss {$src2, $src1|$src1, $src2}",
643 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
644 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
645 "comiss {$src2, $src1|$src1, $src2}",
646 [(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
647 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
648 "comisd {$src2, $src1|$src1, $src2}",
649 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
650 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
651 "comisd {$src2, $src1|$src1, $src2}",
652 [(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
654 // Aliases of packed instructions for scalar use. These all have names that
657 // Alias instructions that map fld0 to pxor for sse.
658 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
659 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
660 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
661 Requires<[HasSSE1]>, TB, OpSize;
662 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
663 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
664 Requires<[HasSSE2]>, TB, OpSize;
666 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
667 // Upper bits are disregarded.
668 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
669 "movaps {$src, $dst|$dst, $src}", []>;
670 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
671 "movapd {$src, $dst|$dst, $src}", []>;
673 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
674 // Upper bits are disregarded.
675 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
676 "movaps {$src, $dst|$dst, $src}",
677 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
678 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
679 "movapd {$src, $dst|$dst, $src}",
680 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
682 // Alias bitwise logical operations using SSE logical ops on packed FP values.
683 let isTwoAddress = 1 in {
684 let isCommutable = 1 in {
685 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
686 "andps {$src2, $dst|$dst, $src2}",
687 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
688 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
689 "andpd {$src2, $dst|$dst, $src2}",
690 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
691 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
692 "orps {$src2, $dst|$dst, $src2}", []>;
693 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
694 "orpd {$src2, $dst|$dst, $src2}", []>;
695 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
696 "xorps {$src2, $dst|$dst, $src2}",
697 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
698 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
699 "xorpd {$src2, $dst|$dst, $src2}",
700 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
702 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
703 "andps {$src2, $dst|$dst, $src2}",
704 [(set FR32:$dst, (X86fand FR32:$src1,
705 (X86loadpf32 addr:$src2)))]>;
706 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
707 "andpd {$src2, $dst|$dst, $src2}",
708 [(set FR64:$dst, (X86fand FR64:$src1,
709 (X86loadpf64 addr:$src2)))]>;
710 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
711 "orps {$src2, $dst|$dst, $src2}", []>;
712 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
713 "orpd {$src2, $dst|$dst, $src2}", []>;
714 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
715 "xorps {$src2, $dst|$dst, $src2}",
716 [(set FR32:$dst, (X86fxor FR32:$src1,
717 (X86loadpf32 addr:$src2)))]>;
718 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
719 "xorpd {$src2, $dst|$dst, $src2}",
720 [(set FR64:$dst, (X86fxor FR64:$src1,
721 (X86loadpf64 addr:$src2)))]>;
723 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
724 "andnps {$src2, $dst|$dst, $src2}", []>;
725 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
726 "andnps {$src2, $dst|$dst, $src2}", []>;
727 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
728 "andnpd {$src2, $dst|$dst, $src2}", []>;
729 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
730 "andnpd {$src2, $dst|$dst, $src2}", []>;
733 //===----------------------------------------------------------------------===//
734 // SSE packed FP Instructions
735 //===----------------------------------------------------------------------===//
737 // Some 'special' instructions
738 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
739 "#IMPLICIT_DEF $dst",
740 [(set VR128:$dst, (v4f32 (undef)))]>,
744 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
745 "movaps {$src, $dst|$dst, $src}", []>;
746 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
747 "movaps {$src, $dst|$dst, $src}",
748 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
749 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
750 "movapd {$src, $dst|$dst, $src}", []>;
751 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
752 "movapd {$src, $dst|$dst, $src}",
753 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
755 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
756 "movaps {$src, $dst|$dst, $src}",
757 [(store (v4f32 VR128:$src), addr:$dst)]>;
758 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
759 "movapd {$src, $dst|$dst, $src}",
760 [(store (v2f64 VR128:$src), addr:$dst)]>;
762 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
763 "movups {$src, $dst|$dst, $src}", []>;
764 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
765 "movups {$src, $dst|$dst, $src}",
766 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
767 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
768 "movups {$src, $dst|$dst, $src}",
769 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
770 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
771 "movupd {$src, $dst|$dst, $src}", []>;
772 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
773 "movupd {$src, $dst|$dst, $src}",
774 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
775 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
776 "movupd {$src, $dst|$dst, $src}",
777 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
779 let isTwoAddress = 1 in {
780 let AddedComplexity = 20 in {
781 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
782 "movlps {$src2, $dst|$dst, $src2}",
784 (v4f32 (vector_shuffle VR128:$src1,
785 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
786 MOVLP_shuffle_mask)))]>;
787 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
788 "movlpd {$src2, $dst|$dst, $src2}",
790 (v2f64 (vector_shuffle VR128:$src1,
791 (scalar_to_vector (loadf64 addr:$src2)),
792 MOVLP_shuffle_mask)))]>;
793 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
794 "movhps {$src2, $dst|$dst, $src2}",
796 (v4f32 (vector_shuffle VR128:$src1,
797 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
798 MOVHP_shuffle_mask)))]>;
799 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
800 "movhpd {$src2, $dst|$dst, $src2}",
802 (v2f64 (vector_shuffle VR128:$src1,
803 (scalar_to_vector (loadf64 addr:$src2)),
804 MOVHP_shuffle_mask)))]>;
808 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
809 "movlps {$src, $dst|$dst, $src}",
810 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
811 (iPTR 0))), addr:$dst)]>;
812 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
813 "movlpd {$src, $dst|$dst, $src}",
814 [(store (f64 (vector_extract (v2f64 VR128:$src),
815 (iPTR 0))), addr:$dst)]>;
817 // v2f64 extract element 1 is always custom lowered to unpack high to low
818 // and extract element 0 so the non-store version isn't too horrible.
819 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
820 "movhps {$src, $dst|$dst, $src}",
821 [(store (f64 (vector_extract
822 (v2f64 (vector_shuffle
823 (bc_v2f64 (v4f32 VR128:$src)), (undef),
824 UNPCKH_shuffle_mask)), (iPTR 0))),
826 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
827 "movhpd {$src, $dst|$dst, $src}",
828 [(store (f64 (vector_extract
829 (v2f64 (vector_shuffle VR128:$src, (undef),
830 UNPCKH_shuffle_mask)), (iPTR 0))),
833 let isTwoAddress = 1 in {
834 let AddedComplexity = 20 in {
835 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
836 "movlhps {$src2, $dst|$dst, $src2}",
838 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
839 MOVHP_shuffle_mask)))]>;
841 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
842 "movhlps {$src2, $dst|$dst, $src2}",
844 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
845 MOVHLPS_shuffle_mask)))]>;
849 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
850 "movshdup {$src, $dst|$dst, $src}",
851 [(set VR128:$dst, (v4f32 (vector_shuffle
853 MOVSHDUP_shuffle_mask)))]>;
854 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
855 "movshdup {$src, $dst|$dst, $src}",
856 [(set VR128:$dst, (v4f32 (vector_shuffle
857 (loadv4f32 addr:$src), (undef),
858 MOVSHDUP_shuffle_mask)))]>;
860 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
861 "movsldup {$src, $dst|$dst, $src}",
862 [(set VR128:$dst, (v4f32 (vector_shuffle
864 MOVSLDUP_shuffle_mask)))]>;
865 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
866 "movsldup {$src, $dst|$dst, $src}",
867 [(set VR128:$dst, (v4f32 (vector_shuffle
868 (loadv4f32 addr:$src), (undef),
869 MOVSLDUP_shuffle_mask)))]>;
871 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
872 "movddup {$src, $dst|$dst, $src}",
873 [(set VR128:$dst, (v2f64 (vector_shuffle
875 SSE_splat_v2_mask)))]>;
876 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
877 "movddup {$src, $dst|$dst, $src}",
878 [(set VR128:$dst, (v2f64 (vector_shuffle
879 (scalar_to_vector (loadf64 addr:$src)),
881 SSE_splat_v2_mask)))]>;
883 // SSE2 instructions without OpSize prefix
884 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
885 "cvtdq2ps {$src, $dst|$dst, $src}",
886 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
887 TB, Requires<[HasSSE2]>;
888 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
889 "cvtdq2ps {$src, $dst|$dst, $src}",
890 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
891 (bc_v4i32 (loadv2i64 addr:$src))))]>,
892 TB, Requires<[HasSSE2]>;
894 // SSE2 instructions with XS prefix
895 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
896 "cvtdq2pd {$src, $dst|$dst, $src}",
897 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
898 XS, Requires<[HasSSE2]>;
899 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
900 "cvtdq2pd {$src, $dst|$dst, $src}",
901 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
902 (bc_v4i32 (loadv2i64 addr:$src))))]>,
903 XS, Requires<[HasSSE2]>;
905 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
906 "cvtps2dq {$src, $dst|$dst, $src}",
907 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
908 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
909 "cvtps2dq {$src, $dst|$dst, $src}",
910 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
911 (loadv4f32 addr:$src)))]>;
912 // SSE2 packed instructions with XS prefix
913 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
914 "cvttps2dq {$src, $dst|$dst, $src}",
915 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
916 XS, Requires<[HasSSE2]>;
917 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
918 "cvttps2dq {$src, $dst|$dst, $src}",
919 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
920 (loadv4f32 addr:$src)))]>,
921 XS, Requires<[HasSSE2]>;
923 // SSE2 packed instructions with XD prefix
924 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
925 "cvtpd2dq {$src, $dst|$dst, $src}",
926 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
927 XD, Requires<[HasSSE2]>;
928 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
929 "cvtpd2dq {$src, $dst|$dst, $src}",
930 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
931 (loadv2f64 addr:$src)))]>,
932 XD, Requires<[HasSSE2]>;
933 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
934 "cvttpd2dq {$src, $dst|$dst, $src}",
935 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
936 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
937 "cvttpd2dq {$src, $dst|$dst, $src}",
938 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
939 (loadv2f64 addr:$src)))]>;
941 // SSE2 instructions without OpSize prefix
942 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
943 "cvtps2pd {$src, $dst|$dst, $src}",
944 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
945 TB, Requires<[HasSSE2]>;
946 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
947 "cvtps2pd {$src, $dst|$dst, $src}",
948 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
949 (loadv4f32 addr:$src)))]>,
950 TB, Requires<[HasSSE2]>;
952 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
953 "cvtpd2ps {$src, $dst|$dst, $src}",
954 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
955 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
956 "cvtpd2ps {$src, $dst|$dst, $src}",
957 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
958 (loadv2f64 addr:$src)))]>;
960 // Match intrinsics which expect XMM operand(s).
961 // Aliases for intrinsics
962 let isTwoAddress = 1 in {
963 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
964 (ops VR128:$dst, VR128:$src1, GR32:$src2),
965 "cvtsi2sd {$src2, $dst|$dst, $src2}",
966 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
968 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
969 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
970 "cvtsi2sd {$src2, $dst|$dst, $src2}",
971 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
972 (loadi32 addr:$src2)))]>;
973 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
974 (ops VR128:$dst, VR128:$src1, VR128:$src2),
975 "cvtsd2ss {$src2, $dst|$dst, $src2}",
976 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
978 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
979 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
980 "cvtsd2ss {$src2, $dst|$dst, $src2}",
981 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
982 (loadv2f64 addr:$src2)))]>;
983 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
984 (ops VR128:$dst, VR128:$src1, VR128:$src2),
985 "cvtss2sd {$src2, $dst|$dst, $src2}",
986 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
989 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
990 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
991 "cvtss2sd {$src2, $dst|$dst, $src2}",
992 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
993 (loadv4f32 addr:$src2)))]>, XS,
998 let isTwoAddress = 1 in {
999 let isCommutable = 1 in {
1000 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1001 "addps {$src2, $dst|$dst, $src2}",
1002 [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
1003 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1004 "addpd {$src2, $dst|$dst, $src2}",
1005 [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
1006 def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1007 "mulps {$src2, $dst|$dst, $src2}",
1008 [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
1009 def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1010 "mulpd {$src2, $dst|$dst, $src2}",
1011 [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
1014 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1015 "addps {$src2, $dst|$dst, $src2}",
1016 [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
1017 (load addr:$src2))))]>;
1018 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1019 "addpd {$src2, $dst|$dst, $src2}",
1020 [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
1021 (load addr:$src2))))]>;
1022 def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1023 "mulps {$src2, $dst|$dst, $src2}",
1024 [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
1025 (load addr:$src2))))]>;
1026 def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1027 "mulpd {$src2, $dst|$dst, $src2}",
1028 [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
1029 (load addr:$src2))))]>;
1031 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1032 "divps {$src2, $dst|$dst, $src2}",
1033 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
1034 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1035 "divps {$src2, $dst|$dst, $src2}",
1036 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
1037 (load addr:$src2))))]>;
1038 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1039 "divpd {$src2, $dst|$dst, $src2}",
1040 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
1041 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1042 "divpd {$src2, $dst|$dst, $src2}",
1043 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
1044 (load addr:$src2))))]>;
1046 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1047 "subps {$src2, $dst|$dst, $src2}",
1048 [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
1049 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1050 "subps {$src2, $dst|$dst, $src2}",
1051 [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
1052 (load addr:$src2))))]>;
1053 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1054 "subpd {$src2, $dst|$dst, $src2}",
1055 [(set VR128:$dst, (v2f64 (fsub VR128:$src1, VR128:$src2)))]>;
1056 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1057 "subpd {$src2, $dst|$dst, $src2}",
1058 [(set VR128:$dst, (v2f64 (fsub VR128:$src1,
1059 (load addr:$src2))))]>;
1061 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
1062 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1063 "addsubps {$src2, $dst|$dst, $src2}",
1064 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1066 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
1067 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1068 "addsubps {$src2, $dst|$dst, $src2}",
1069 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1070 (loadv4f32 addr:$src2)))]>;
1071 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
1072 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1073 "addsubpd {$src2, $dst|$dst, $src2}",
1074 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1076 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
1077 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1078 "addsubpd {$src2, $dst|$dst, $src2}",
1079 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1080 (loadv2f64 addr:$src2)))]>;
1083 def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
1084 int_x86_sse_sqrt_ps>;
1085 def SQRTPSm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}",
1086 int_x86_sse_sqrt_ps>;
1087 def SQRTPDr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1088 int_x86_sse2_sqrt_pd>;
1089 def SQRTPDm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1090 int_x86_sse2_sqrt_pd>;
1092 def RSQRTPSr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1093 int_x86_sse_rsqrt_ps>;
1094 def RSQRTPSm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1095 int_x86_sse_rsqrt_ps>;
1096 def RCPPSr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}",
1097 int_x86_sse_rcp_ps>;
1098 def RCPPSm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}",
1099 int_x86_sse_rcp_ps>;
1101 let isTwoAddress = 1 in {
1102 let isCommutable = 1 in {
1103 def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1104 int_x86_sse_max_ps>;
1105 def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1106 int_x86_sse2_max_pd>;
1107 def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}",
1108 int_x86_sse_min_ps>;
1109 def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1110 int_x86_sse2_min_pd>;
1112 def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1113 int_x86_sse_max_ps>;
1114 def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1115 int_x86_sse2_max_pd>;
1116 def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}",
1117 int_x86_sse_min_ps>;
1118 def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1119 int_x86_sse2_min_pd>;
1123 let isTwoAddress = 1 in {
1124 let isCommutable = 1 in {
1125 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1126 "andps {$src2, $dst|$dst, $src2}",
1127 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1128 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1129 "andpd {$src2, $dst|$dst, $src2}",
1131 (and (bc_v2i64 (v2f64 VR128:$src1)),
1132 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1133 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1134 "orps {$src2, $dst|$dst, $src2}",
1135 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1136 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1137 "orpd {$src2, $dst|$dst, $src2}",
1139 (or (bc_v2i64 (v2f64 VR128:$src1)),
1140 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1141 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1142 "xorps {$src2, $dst|$dst, $src2}",
1143 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1144 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1145 "xorpd {$src2, $dst|$dst, $src2}",
1147 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1148 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1150 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1151 "andps {$src2, $dst|$dst, $src2}",
1152 [(set VR128:$dst, (and VR128:$src1,
1153 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1154 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1155 "andpd {$src2, $dst|$dst, $src2}",
1157 (and (bc_v2i64 (v2f64 VR128:$src1)),
1158 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1159 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1160 "orps {$src2, $dst|$dst, $src2}",
1161 [(set VR128:$dst, (or VR128:$src1,
1162 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1163 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1164 "orpd {$src2, $dst|$dst, $src2}",
1166 (or (bc_v2i64 (v2f64 VR128:$src1)),
1167 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1168 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1169 "xorps {$src2, $dst|$dst, $src2}",
1170 [(set VR128:$dst, (xor VR128:$src1,
1171 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1172 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1173 "xorpd {$src2, $dst|$dst, $src2}",
1175 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1176 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1177 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1178 "andnps {$src2, $dst|$dst, $src2}",
1179 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1180 (bc_v2i64 (v4i32 immAllOnesV))),
1182 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1183 "andnps {$src2, $dst|$dst, $src2}",
1184 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1185 (bc_v2i64 (v4i32 immAllOnesV))),
1186 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1187 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1188 "andnpd {$src2, $dst|$dst, $src2}",
1190 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1191 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1192 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1193 "andnpd {$src2, $dst|$dst, $src2}",
1195 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1196 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1199 let isTwoAddress = 1 in {
1200 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1201 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1202 "cmp${cc}ps {$src, $dst|$dst, $src}",
1203 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1204 VR128:$src, imm:$cc))]>;
1205 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1206 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1207 "cmp${cc}ps {$src, $dst|$dst, $src}",
1208 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1209 (load addr:$src), imm:$cc))]>;
1210 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1211 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1212 "cmp${cc}pd {$src, $dst|$dst, $src}",
1213 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1214 VR128:$src, imm:$cc))]>;
1215 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1216 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1217 "cmp${cc}pd {$src, $dst|$dst, $src}",
1218 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1219 (load addr:$src), imm:$cc))]>;
1222 // Shuffle and unpack instructions
1223 let isTwoAddress = 1 in {
1224 let isCommutable = 1, isConvertibleToThreeAddress = 1 in // Convert to pshufd
1225 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1226 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1227 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1228 [(set VR128:$dst, (v4f32 (vector_shuffle
1229 VR128:$src1, VR128:$src2,
1230 SHUFP_shuffle_mask:$src3)))]>;
1231 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1232 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1233 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1234 [(set VR128:$dst, (v4f32 (vector_shuffle
1235 VR128:$src1, (load addr:$src2),
1236 SHUFP_shuffle_mask:$src3)))]>;
1237 let isCommutable = 1 in
1238 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1239 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1240 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1241 [(set VR128:$dst, (v2f64 (vector_shuffle
1242 VR128:$src1, VR128:$src2,
1243 SHUFP_shuffle_mask:$src3)))]>;
1244 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1245 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1246 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1247 [(set VR128:$dst, (v2f64 (vector_shuffle
1248 VR128:$src1, (load addr:$src2),
1249 SHUFP_shuffle_mask:$src3)))]>;
1251 let AddedComplexity = 10 in {
1252 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1253 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1254 "unpckhps {$src2, $dst|$dst, $src2}",
1255 [(set VR128:$dst, (v4f32 (vector_shuffle
1256 VR128:$src1, VR128:$src2,
1257 UNPCKH_shuffle_mask)))]>;
1258 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1259 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1260 "unpckhps {$src2, $dst|$dst, $src2}",
1261 [(set VR128:$dst, (v4f32 (vector_shuffle
1262 VR128:$src1, (load addr:$src2),
1263 UNPCKH_shuffle_mask)))]>;
1264 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1265 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1266 "unpckhpd {$src2, $dst|$dst, $src2}",
1267 [(set VR128:$dst, (v2f64 (vector_shuffle
1268 VR128:$src1, VR128:$src2,
1269 UNPCKH_shuffle_mask)))]>;
1270 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1271 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1272 "unpckhpd {$src2, $dst|$dst, $src2}",
1273 [(set VR128:$dst, (v2f64 (vector_shuffle
1274 VR128:$src1, (load addr:$src2),
1275 UNPCKH_shuffle_mask)))]>;
1277 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1278 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1279 "unpcklps {$src2, $dst|$dst, $src2}",
1280 [(set VR128:$dst, (v4f32 (vector_shuffle
1281 VR128:$src1, VR128:$src2,
1282 UNPCKL_shuffle_mask)))]>;
1283 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1284 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1285 "unpcklps {$src2, $dst|$dst, $src2}",
1286 [(set VR128:$dst, (v4f32 (vector_shuffle
1287 VR128:$src1, (load addr:$src2),
1288 UNPCKL_shuffle_mask)))]>;
1289 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1290 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1291 "unpcklpd {$src2, $dst|$dst, $src2}",
1292 [(set VR128:$dst, (v2f64 (vector_shuffle
1293 VR128:$src1, VR128:$src2,
1294 UNPCKL_shuffle_mask)))]>;
1295 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1296 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1297 "unpcklpd {$src2, $dst|$dst, $src2}",
1298 [(set VR128:$dst, (v2f64 (vector_shuffle
1299 VR128:$src1, (load addr:$src2),
1300 UNPCKL_shuffle_mask)))]>;
1301 } // AddedComplexity
1305 let isTwoAddress = 1 in {
1306 def HADDPSrr : S3D_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1307 int_x86_sse3_hadd_ps>;
1308 def HADDPSrm : S3D_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1309 int_x86_sse3_hadd_ps>;
1310 def HADDPDrr : S3_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1311 int_x86_sse3_hadd_pd>;
1312 def HADDPDrm : S3_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1313 int_x86_sse3_hadd_pd>;
1314 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1315 int_x86_sse3_hsub_ps>;
1316 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1317 int_x86_sse3_hsub_ps>;
1318 def HSUBPDrr : S3_Intrr<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1319 int_x86_sse3_hsub_pd>;
1320 def HSUBPDrm : S3_Intrm<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1321 int_x86_sse3_hsub_pd>;
1324 //===----------------------------------------------------------------------===//
1325 // SSE integer instructions
1326 //===----------------------------------------------------------------------===//
1328 // Move Instructions
1329 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1330 "movdqa {$src, $dst|$dst, $src}", []>;
1331 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1332 "movdqa {$src, $dst|$dst, $src}",
1333 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1334 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1335 "movdqa {$src, $dst|$dst, $src}",
1336 [(store (v2i64 VR128:$src), addr:$dst)]>;
1337 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1338 "movdqu {$src, $dst|$dst, $src}",
1339 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1340 XS, Requires<[HasSSE2]>;
1341 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1342 "movdqu {$src, $dst|$dst, $src}",
1343 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1344 XS, Requires<[HasSSE2]>;
1345 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1346 "lddqu {$src, $dst|$dst, $src}",
1347 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
1349 // 128-bit Integer Arithmetic
1350 let isTwoAddress = 1 in {
1351 let isCommutable = 1 in {
1352 def PADDBrr : PDI<0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1353 "paddb {$src2, $dst|$dst, $src2}",
1354 [(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))]>;
1355 def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1356 "paddw {$src2, $dst|$dst, $src2}",
1357 [(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))]>;
1358 def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1359 "paddd {$src2, $dst|$dst, $src2}",
1360 [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
1362 def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1363 "paddq {$src2, $dst|$dst, $src2}",
1364 [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
1366 def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1367 "paddb {$src2, $dst|$dst, $src2}",
1368 [(set VR128:$dst, (add VR128:$src1,
1369 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1370 def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1371 "paddw {$src2, $dst|$dst, $src2}",
1372 [(set VR128:$dst, (add VR128:$src1,
1373 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1374 def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1375 "paddd {$src2, $dst|$dst, $src2}",
1376 [(set VR128:$dst, (add VR128:$src1,
1377 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1378 def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1379 "paddd {$src2, $dst|$dst, $src2}",
1380 [(set VR128:$dst, (add VR128:$src1,
1381 (loadv2i64 addr:$src2)))]>;
1383 let isCommutable = 1 in {
1384 def PADDSBrr : PDI<0xEC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1385 "paddsb {$src2, $dst|$dst, $src2}",
1386 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1388 def PADDSWrr : PDI<0xED, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1389 "paddsw {$src2, $dst|$dst, $src2}",
1390 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1392 def PADDUSBrr : PDI<0xDC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1393 "paddusb {$src2, $dst|$dst, $src2}",
1394 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1396 def PADDUSWrr : PDI<0xDD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1397 "paddusw {$src2, $dst|$dst, $src2}",
1398 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1401 def PADDSBrm : PDI<0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1402 "paddsb {$src2, $dst|$dst, $src2}",
1403 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1404 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1405 def PADDSWrm : PDI<0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1406 "paddsw {$src2, $dst|$dst, $src2}",
1407 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1408 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1409 def PADDUSBrm : PDI<0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1410 "paddusb {$src2, $dst|$dst, $src2}",
1411 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1412 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1413 def PADDUSWrm : PDI<0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1414 "paddusw {$src2, $dst|$dst, $src2}",
1415 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1416 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1419 def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1420 "psubb {$src2, $dst|$dst, $src2}",
1421 [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
1422 def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1423 "psubw {$src2, $dst|$dst, $src2}",
1424 [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))]>;
1425 def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1426 "psubd {$src2, $dst|$dst, $src2}",
1427 [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
1428 def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1429 "psubq {$src2, $dst|$dst, $src2}",
1430 [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
1432 def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1433 "psubb {$src2, $dst|$dst, $src2}",
1434 [(set VR128:$dst, (sub VR128:$src1,
1435 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1436 def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1437 "psubw {$src2, $dst|$dst, $src2}",
1438 [(set VR128:$dst, (sub VR128:$src1,
1439 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1440 def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1441 "psubd {$src2, $dst|$dst, $src2}",
1442 [(set VR128:$dst, (sub VR128:$src1,
1443 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1444 def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1445 "psubd {$src2, $dst|$dst, $src2}",
1446 [(set VR128:$dst, (sub VR128:$src1,
1447 (loadv2i64 addr:$src2)))]>;
1449 def PSUBSBrr : PDI<0xE8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1450 "psubsb {$src2, $dst|$dst, $src2}",
1451 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1453 def PSUBSWrr : PDI<0xE9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1454 "psubsw {$src2, $dst|$dst, $src2}",
1455 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1457 def PSUBUSBrr : PDI<0xD8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1458 "psubusb {$src2, $dst|$dst, $src2}",
1459 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1461 def PSUBUSWrr : PDI<0xD9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1462 "psubusw {$src2, $dst|$dst, $src2}",
1463 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1466 def PSUBSBrm : PDI<0xE8, MRMSrcMem,
1467 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1468 "psubsb {$src2, $dst|$dst, $src2}",
1469 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1470 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1471 def PSUBSWrm : PDI<0xE9, MRMSrcMem,
1472 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1473 "psubsw {$src2, $dst|$dst, $src2}",
1474 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1475 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1476 def PSUBUSBrm : PDI<0xD8, MRMSrcMem,
1477 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1478 "psubusb {$src2, $dst|$dst, $src2}",
1479 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1480 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1481 def PSUBUSWrm : PDI<0xD9, MRMSrcMem,
1482 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1483 "psubusw {$src2, $dst|$dst, $src2}",
1484 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1485 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1487 let isCommutable = 1 in {
1488 def PMULHUWrr : PDI<0xE4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1489 "pmulhuw {$src2, $dst|$dst, $src2}",
1490 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1492 def PMULHWrr : PDI<0xE5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1493 "pmulhw {$src2, $dst|$dst, $src2}",
1494 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1496 def PMULLWrr : PDI<0xD5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1497 "pmullw {$src2, $dst|$dst, $src2}",
1498 [(set VR128:$dst, (v8i16 (mul VR128:$src1, VR128:$src2)))]>;
1499 def PMULUDQrr : PDI<0xF4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1500 "pmuludq {$src2, $dst|$dst, $src2}",
1501 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1504 def PMULHUWrm : PDI<0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1505 "pmulhuw {$src2, $dst|$dst, $src2}",
1506 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1507 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1508 def PMULHWrm : PDI<0xE5, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1509 "pmulhw {$src2, $dst|$dst, $src2}",
1510 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1511 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1512 def PMULLWrm : PDI<0xD5, MRMSrcMem,
1513 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1514 "pmullw {$src2, $dst|$dst, $src2}",
1515 [(set VR128:$dst, (v8i16 (mul VR128:$src1,
1516 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1517 def PMULUDQrm : PDI<0xF4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1518 "pmuludq {$src2, $dst|$dst, $src2}",
1519 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1520 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1522 let isCommutable = 1 in {
1523 def PMADDWDrr : PDI<0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1524 "pmaddwd {$src2, $dst|$dst, $src2}",
1525 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1528 def PMADDWDrm : PDI<0xF5, MRMSrcMem,
1529 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1530 "pmaddwd {$src2, $dst|$dst, $src2}",
1531 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1532 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1534 let isCommutable = 1 in {
1535 def PAVGBrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1536 "pavgb {$src2, $dst|$dst, $src2}",
1537 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1539 def PAVGWrr : PDI<0xE3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1540 "pavgw {$src2, $dst|$dst, $src2}",
1541 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1544 def PAVGBrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1545 "pavgb {$src2, $dst|$dst, $src2}",
1546 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1547 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1548 def PAVGWrm : PDI<0xE3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1549 "pavgw {$src2, $dst|$dst, $src2}",
1550 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1551 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1553 let isCommutable = 1 in {
1554 def PMAXUBrr : PDI<0xDE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1555 "pmaxub {$src2, $dst|$dst, $src2}",
1556 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1558 def PMAXSWrr : PDI<0xEE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1559 "pmaxsw {$src2, $dst|$dst, $src2}",
1560 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1563 def PMAXUBrm : PDI<0xDE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1564 "pmaxub {$src2, $dst|$dst, $src2}",
1565 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1566 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1567 def PMAXSWrm : PDI<0xEE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1568 "pmaxsw {$src2, $dst|$dst, $src2}",
1569 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1570 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1572 let isCommutable = 1 in {
1573 def PMINUBrr : PDI<0xDA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1574 "pminub {$src2, $dst|$dst, $src2}",
1575 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1577 def PMINSWrr : PDI<0xEA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1578 "pminsw {$src2, $dst|$dst, $src2}",
1579 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1582 def PMINUBrm : PDI<0xDA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1583 "pminub {$src2, $dst|$dst, $src2}",
1584 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1585 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1586 def PMINSWrm : PDI<0xEA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1587 "pminsw {$src2, $dst|$dst, $src2}",
1588 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1589 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1592 let isCommutable = 1 in {
1593 def PSADBWrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1594 "psadbw {$src2, $dst|$dst, $src2}",
1595 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1598 def PSADBWrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1599 "psadbw {$src2, $dst|$dst, $src2}",
1600 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1601 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1604 let isTwoAddress = 1 in {
1605 def PSLLWrr : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1606 "psllw {$src2, $dst|$dst, $src2}",
1607 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1609 def PSLLWrm : PDIi8<0xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1610 "psllw {$src2, $dst|$dst, $src2}",
1611 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1612 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1613 def PSLLWri : PDIi8<0x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1614 "psllw {$src2, $dst|$dst, $src2}",
1615 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1616 (scalar_to_vector (i32 imm:$src2))))]>;
1617 def PSLLDrr : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1618 "pslld {$src2, $dst|$dst, $src2}",
1619 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1621 def PSLLDrm : PDIi8<0xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1622 "pslld {$src2, $dst|$dst, $src2}",
1623 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1624 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1625 def PSLLDri : PDIi8<0x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1626 "pslld {$src2, $dst|$dst, $src2}",
1627 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1628 (scalar_to_vector (i32 imm:$src2))))]>;
1629 def PSLLQrr : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1630 "psllq {$src2, $dst|$dst, $src2}",
1631 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1633 def PSLLQrm : PDIi8<0xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1634 "psllq {$src2, $dst|$dst, $src2}",
1635 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1636 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1637 def PSLLQri : PDIi8<0x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1638 "psllq {$src2, $dst|$dst, $src2}",
1639 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1640 (scalar_to_vector (i32 imm:$src2))))]>;
1641 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1642 "pslldq {$src2, $dst|$dst, $src2}", []>;
1644 def PSRLWrr : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1645 "psrlw {$src2, $dst|$dst, $src2}",
1646 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1648 def PSRLWrm : PDIi8<0xD1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1649 "psrlw {$src2, $dst|$dst, $src2}",
1650 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1651 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1652 def PSRLWri : PDIi8<0x71, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1653 "psrlw {$src2, $dst|$dst, $src2}",
1654 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1655 (scalar_to_vector (i32 imm:$src2))))]>;
1656 def PSRLDrr : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1657 "psrld {$src2, $dst|$dst, $src2}",
1658 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1660 def PSRLDrm : PDIi8<0xD2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1661 "psrld {$src2, $dst|$dst, $src2}",
1662 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1663 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1664 def PSRLDri : PDIi8<0x72, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1665 "psrld {$src2, $dst|$dst, $src2}",
1666 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1667 (scalar_to_vector (i32 imm:$src2))))]>;
1668 def PSRLQrr : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1669 "psrlq {$src2, $dst|$dst, $src2}",
1670 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1672 def PSRLQrm : PDIi8<0xD3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1673 "psrlq {$src2, $dst|$dst, $src2}",
1674 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1675 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1676 def PSRLQri : PDIi8<0x73, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1677 "psrlq {$src2, $dst|$dst, $src2}",
1678 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1679 (scalar_to_vector (i32 imm:$src2))))]>;
1680 def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1681 "psrldq {$src2, $dst|$dst, $src2}", []>;
1683 def PSRAWrr : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1684 "psraw {$src2, $dst|$dst, $src2}",
1685 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1687 def PSRAWrm : PDIi8<0xE1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1688 "psraw {$src2, $dst|$dst, $src2}",
1689 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1690 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1691 def PSRAWri : PDIi8<0x71, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1692 "psraw {$src2, $dst|$dst, $src2}",
1693 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1694 (scalar_to_vector (i32 imm:$src2))))]>;
1695 def PSRADrr : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1696 "psrad {$src2, $dst|$dst, $src2}",
1697 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1699 def PSRADrm : PDIi8<0xE2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1700 "psrad {$src2, $dst|$dst, $src2}",
1701 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1702 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1703 def PSRADri : PDIi8<0x72, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1704 "psrad {$src2, $dst|$dst, $src2}",
1705 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1706 (scalar_to_vector (i32 imm:$src2))))]>;
1710 let isTwoAddress = 1 in {
1711 let isCommutable = 1 in {
1712 def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1713 "pand {$src2, $dst|$dst, $src2}",
1714 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1715 def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1716 "por {$src2, $dst|$dst, $src2}",
1717 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1718 def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1719 "pxor {$src2, $dst|$dst, $src2}",
1720 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1723 def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1724 "pand {$src2, $dst|$dst, $src2}",
1725 [(set VR128:$dst, (v2i64 (and VR128:$src1,
1726 (load addr:$src2))))]>;
1727 def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1728 "por {$src2, $dst|$dst, $src2}",
1729 [(set VR128:$dst, (v2i64 (or VR128:$src1,
1730 (load addr:$src2))))]>;
1731 def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1732 "pxor {$src2, $dst|$dst, $src2}",
1733 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
1734 (load addr:$src2))))]>;
1736 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1737 "pandn {$src2, $dst|$dst, $src2}",
1738 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1741 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1742 "pandn {$src2, $dst|$dst, $src2}",
1743 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1744 (load addr:$src2))))]>;
1747 // SSE2 Integer comparison
1748 let isTwoAddress = 1 in {
1749 def PCMPEQBrr : PDI<0x74, MRMSrcReg,
1750 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1751 "pcmpeqb {$src2, $dst|$dst, $src2}",
1752 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1754 def PCMPEQBrm : PDI<0x74, MRMSrcMem,
1755 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1756 "pcmpeqb {$src2, $dst|$dst, $src2}",
1757 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1758 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1759 def PCMPEQWrr : PDI<0x75, MRMSrcReg,
1760 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1761 "pcmpeqw {$src2, $dst|$dst, $src2}",
1762 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1764 def PCMPEQWrm : PDI<0x75, MRMSrcMem,
1765 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1766 "pcmpeqw {$src2, $dst|$dst, $src2}",
1767 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1768 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1769 def PCMPEQDrr : PDI<0x76, MRMSrcReg,
1770 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1771 "pcmpeqd {$src2, $dst|$dst, $src2}",
1772 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1774 def PCMPEQDrm : PDI<0x76, MRMSrcMem,
1775 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1776 "pcmpeqd {$src2, $dst|$dst, $src2}",
1777 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1778 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1780 def PCMPGTBrr : PDI<0x64, MRMSrcReg,
1781 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1782 "pcmpgtb {$src2, $dst|$dst, $src2}",
1783 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1785 def PCMPGTBrm : PDI<0x64, MRMSrcMem,
1786 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1787 "pcmpgtb {$src2, $dst|$dst, $src2}",
1788 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1789 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1790 def PCMPGTWrr : PDI<0x65, MRMSrcReg,
1791 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1792 "pcmpgtw {$src2, $dst|$dst, $src2}",
1793 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1795 def PCMPGTWrm : PDI<0x65, MRMSrcMem,
1796 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1797 "pcmpgtw {$src2, $dst|$dst, $src2}",
1798 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1799 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1800 def PCMPGTDrr : PDI<0x66, MRMSrcReg,
1801 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1802 "pcmpgtd {$src2, $dst|$dst, $src2}",
1803 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1805 def PCMPGTDrm : PDI<0x66, MRMSrcMem,
1806 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1807 "pcmpgtd {$src2, $dst|$dst, $src2}",
1808 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1809 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1812 // Pack instructions
1813 let isTwoAddress = 1 in {
1814 def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1816 "packsswb {$src2, $dst|$dst, $src2}",
1817 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1820 def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1822 "packsswb {$src2, $dst|$dst, $src2}",
1823 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1825 (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
1826 def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1828 "packssdw {$src2, $dst|$dst, $src2}",
1829 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1832 def PACKSSDWrm : PDI<0x6B, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1834 "packssdw {$src2, $dst|$dst, $src2}",
1835 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1837 (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
1838 def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1840 "packuswb {$src2, $dst|$dst, $src2}",
1841 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1844 def PACKUSWBrm : PDI<0x67, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1846 "packuswb {$src2, $dst|$dst, $src2}",
1847 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1849 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1852 // Shuffle and unpack instructions
1853 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1854 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1855 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1856 [(set VR128:$dst, (v4i32 (vector_shuffle
1857 VR128:$src1, (undef),
1858 PSHUFD_shuffle_mask:$src2)))]>;
1859 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1860 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1861 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1862 [(set VR128:$dst, (v4i32 (vector_shuffle
1863 (bc_v4i32 (loadv2i64 addr:$src1)),
1865 PSHUFD_shuffle_mask:$src2)))]>;
1867 // SSE2 with ImmT == Imm8 and XS prefix.
1868 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1869 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1870 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1871 [(set VR128:$dst, (v8i16 (vector_shuffle
1872 VR128:$src1, (undef),
1873 PSHUFHW_shuffle_mask:$src2)))]>,
1874 XS, Requires<[HasSSE2]>;
1875 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1876 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1877 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1878 [(set VR128:$dst, (v8i16 (vector_shuffle
1879 (bc_v8i16 (loadv2i64 addr:$src1)),
1881 PSHUFHW_shuffle_mask:$src2)))]>,
1882 XS, Requires<[HasSSE2]>;
1884 // SSE2 with ImmT == Imm8 and XD prefix.
1885 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1886 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1887 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1888 [(set VR128:$dst, (v8i16 (vector_shuffle
1889 VR128:$src1, (undef),
1890 PSHUFLW_shuffle_mask:$src2)))]>,
1891 XD, Requires<[HasSSE2]>;
1892 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1893 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1894 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1895 [(set VR128:$dst, (v8i16 (vector_shuffle
1896 (bc_v8i16 (loadv2i64 addr:$src1)),
1898 PSHUFLW_shuffle_mask:$src2)))]>,
1899 XD, Requires<[HasSSE2]>;
1901 let isTwoAddress = 1 in {
1902 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1903 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1904 "punpcklbw {$src2, $dst|$dst, $src2}",
1906 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1907 UNPCKL_shuffle_mask)))]>;
1908 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1909 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1910 "punpcklbw {$src2, $dst|$dst, $src2}",
1912 (v16i8 (vector_shuffle VR128:$src1,
1913 (bc_v16i8 (loadv2i64 addr:$src2)),
1914 UNPCKL_shuffle_mask)))]>;
1915 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1916 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1917 "punpcklwd {$src2, $dst|$dst, $src2}",
1919 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1920 UNPCKL_shuffle_mask)))]>;
1921 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1922 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1923 "punpcklwd {$src2, $dst|$dst, $src2}",
1925 (v8i16 (vector_shuffle VR128:$src1,
1926 (bc_v8i16 (loadv2i64 addr:$src2)),
1927 UNPCKL_shuffle_mask)))]>;
1928 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1929 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1930 "punpckldq {$src2, $dst|$dst, $src2}",
1932 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1933 UNPCKL_shuffle_mask)))]>;
1934 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1935 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1936 "punpckldq {$src2, $dst|$dst, $src2}",
1938 (v4i32 (vector_shuffle VR128:$src1,
1939 (bc_v4i32 (loadv2i64 addr:$src2)),
1940 UNPCKL_shuffle_mask)))]>;
1941 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1942 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1943 "punpcklqdq {$src2, $dst|$dst, $src2}",
1945 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1946 UNPCKL_shuffle_mask)))]>;
1947 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1948 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1949 "punpcklqdq {$src2, $dst|$dst, $src2}",
1951 (v2i64 (vector_shuffle VR128:$src1,
1952 (loadv2i64 addr:$src2),
1953 UNPCKL_shuffle_mask)))]>;
1955 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1956 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1957 "punpckhbw {$src2, $dst|$dst, $src2}",
1959 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1960 UNPCKH_shuffle_mask)))]>;
1961 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1962 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1963 "punpckhbw {$src2, $dst|$dst, $src2}",
1965 (v16i8 (vector_shuffle VR128:$src1,
1966 (bc_v16i8 (loadv2i64 addr:$src2)),
1967 UNPCKH_shuffle_mask)))]>;
1968 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1969 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1970 "punpckhwd {$src2, $dst|$dst, $src2}",
1972 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1973 UNPCKH_shuffle_mask)))]>;
1974 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1975 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1976 "punpckhwd {$src2, $dst|$dst, $src2}",
1978 (v8i16 (vector_shuffle VR128:$src1,
1979 (bc_v8i16 (loadv2i64 addr:$src2)),
1980 UNPCKH_shuffle_mask)))]>;
1981 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1982 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1983 "punpckhdq {$src2, $dst|$dst, $src2}",
1985 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1986 UNPCKH_shuffle_mask)))]>;
1987 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1988 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1989 "punpckhdq {$src2, $dst|$dst, $src2}",
1991 (v4i32 (vector_shuffle VR128:$src1,
1992 (bc_v4i32 (loadv2i64 addr:$src2)),
1993 UNPCKH_shuffle_mask)))]>;
1994 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1995 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1996 "punpckhqdq {$src2, $dst|$dst, $src2}",
1998 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1999 UNPCKH_shuffle_mask)))]>;
2000 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2001 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
2002 "punpckhqdq {$src2, $dst|$dst, $src2}",
2004 (v2i64 (vector_shuffle VR128:$src1,
2005 (loadv2i64 addr:$src2),
2006 UNPCKH_shuffle_mask)))]>;
2010 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2011 (ops GR32:$dst, VR128:$src1, i32i8imm:$src2),
2012 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
2013 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2014 (i32 imm:$src2)))]>;
2015 let isTwoAddress = 1 in {
2016 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2017 (ops VR128:$dst, VR128:$src1, GR32:$src2, i32i8imm:$src3),
2018 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2019 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2020 GR32:$src2, (iPTR imm:$src3))))]>;
2021 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2022 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
2023 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2025 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2026 (i32 (anyext (loadi16 addr:$src2))),
2027 (iPTR imm:$src3))))]>;
2030 //===----------------------------------------------------------------------===//
2031 // Miscellaneous Instructions
2032 //===----------------------------------------------------------------------===//
2035 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
2036 "movmskps {$src, $dst|$dst, $src}",
2037 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
2038 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
2039 "movmskpd {$src, $dst|$dst, $src}",
2040 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
2042 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src),
2043 "pmovmskb {$src, $dst|$dst, $src}",
2044 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2046 // Conditional store
2047 def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
2048 "maskmovdqu {$mask, $src|$src, $mask}",
2049 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
2052 // Prefetching loads
2053 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
2054 "prefetcht0 $src", []>;
2055 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
2056 "prefetcht1 $src", []>;
2057 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
2058 "prefetcht2 $src", []>;
2059 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
2060 "prefetchtnta $src", []>;
2062 // Non-temporal stores
2063 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2064 "movntps {$src, $dst|$dst, $src}",
2065 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2066 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2067 "movntpd {$src, $dst|$dst, $src}",
2068 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2069 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
2070 "movntdq {$src, $dst|$dst, $src}",
2071 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2072 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src),
2073 "movnti {$src, $dst|$dst, $src}",
2074 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2075 TB, Requires<[HasSSE2]>;
2078 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
2079 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
2080 TB, Requires<[HasSSE2]>;
2082 // Load, store, and memory fence
2083 def SFENCE : I<0xAE, MRM7m, (ops),
2084 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
2085 def LFENCE : I<0xAE, MRM5m, (ops),
2086 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2087 def MFENCE : I<0xAE, MRM6m, (ops),
2088 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2091 def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src),
2093 [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
2094 def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
2096 [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
2098 // Thread synchronization
2099 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
2100 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,
2101 TB, Requires<[HasSSE3]>;
2102 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
2103 [(int_x86_sse3_mwait ECX, EAX)]>,
2104 TB, Requires<[HasSSE3]>;
2106 //===----------------------------------------------------------------------===//
2107 // Alias Instructions
2108 //===----------------------------------------------------------------------===//
2110 // Alias instructions that map zero vector to pxor / xorp* for sse.
2111 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2112 def V_SET0_PI : PDI<0xEF, MRMInitReg, (ops VR128:$dst),
2114 [(set VR128:$dst, (v2i64 immAllZerosV))]>;
2115 def V_SET0_PS : PSI<0x57, MRMInitReg, (ops VR128:$dst),
2117 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2118 def V_SET0_PD : PDI<0x57, MRMInitReg, (ops VR128:$dst),
2120 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2122 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
2123 "pcmpeqd $dst, $dst",
2124 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
2126 // FR32 / FR64 to 128-bit vector conversion.
2127 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
2128 "movss {$src, $dst|$dst, $src}",
2130 (v4f32 (scalar_to_vector FR32:$src)))]>;
2131 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2132 "movss {$src, $dst|$dst, $src}",
2134 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
2135 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
2136 "movsd {$src, $dst|$dst, $src}",
2138 (v2f64 (scalar_to_vector FR64:$src)))]>;
2139 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2140 "movsd {$src, $dst|$dst, $src}",
2142 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2144 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
2145 "movd {$src, $dst|$dst, $src}",
2147 (v4i32 (scalar_to_vector GR32:$src)))]>;
2148 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2149 "movd {$src, $dst|$dst, $src}",
2151 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2152 // SSE2 instructions with XS prefix
2153 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
2154 "movq {$src, $dst|$dst, $src}",
2156 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
2157 Requires<[HasSSE2]>;
2158 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2159 "movq {$src, $dst|$dst, $src}",
2161 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2162 Requires<[HasSSE2]>;
2163 // FIXME: may not be able to eliminate this movss with coalescing the src and
2164 // dest register classes are different. We really want to write this pattern
2166 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2167 // (f32 FR32:$src)>;
2168 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
2169 "movss {$src, $dst|$dst, $src}",
2170 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
2172 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
2173 "movss {$src, $dst|$dst, $src}",
2174 [(store (f32 (vector_extract (v4f32 VR128:$src),
2175 (iPTR 0))), addr:$dst)]>;
2176 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
2177 "movsd {$src, $dst|$dst, $src}",
2178 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2180 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
2181 "movsd {$src, $dst|$dst, $src}",
2182 [(store (f64 (vector_extract (v2f64 VR128:$src),
2183 (iPTR 0))), addr:$dst)]>;
2184 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src),
2185 "movd {$src, $dst|$dst, $src}",
2186 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2188 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
2189 "movd {$src, $dst|$dst, $src}",
2190 [(store (i32 (vector_extract (v4i32 VR128:$src),
2191 (iPTR 0))), addr:$dst)]>;
2193 // Move to lower bits of a VR128, leaving upper bits alone.
2194 // Three operand (but two address) aliases.
2195 let isTwoAddress = 1 in {
2196 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
2197 "movss {$src2, $dst|$dst, $src2}", []>;
2198 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
2199 "movsd {$src2, $dst|$dst, $src2}", []>;
2201 let AddedComplexity = 20 in {
2202 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2203 "movss {$src2, $dst|$dst, $src2}",
2205 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2206 MOVL_shuffle_mask)))]>;
2207 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2208 "movsd {$src2, $dst|$dst, $src2}",
2210 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2211 MOVL_shuffle_mask)))]>;
2215 // Store / copy lower 64-bits of a XMM register.
2216 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
2217 "movq {$src, $dst|$dst, $src}",
2218 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2220 // Move to lower bits of a VR128 and zeroing upper bits.
2221 // Loading from memory automatically zeroing upper bits.
2222 let AddedComplexity = 20 in {
2223 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2224 "movss {$src, $dst|$dst, $src}",
2225 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
2226 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
2227 MOVL_shuffle_mask)))]>;
2228 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2229 "movsd {$src, $dst|$dst, $src}",
2230 [(set VR128:$dst, (v2f64 (vector_shuffle immAllZerosV,
2231 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2232 MOVL_shuffle_mask)))]>;
2233 // movd / movq to XMM register zero-extends
2234 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
2235 "movd {$src, $dst|$dst, $src}",
2236 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
2237 (v4i32 (scalar_to_vector GR32:$src)),
2238 MOVL_shuffle_mask)))]>;
2239 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2240 "movd {$src, $dst|$dst, $src}",
2241 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
2242 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
2243 MOVL_shuffle_mask)))]>;
2244 // Moving from XMM to XMM but still clear upper 64 bits.
2245 def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2246 "movq {$src, $dst|$dst, $src}",
2247 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
2248 XS, Requires<[HasSSE2]>;
2249 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2250 "movq {$src, $dst|$dst, $src}",
2251 [(set VR128:$dst, (int_x86_sse2_movl_dq
2252 (bc_v4i32 (loadv2i64 addr:$src))))]>,
2253 XS, Requires<[HasSSE2]>;
2256 //===----------------------------------------------------------------------===//
2257 // Non-Instruction Patterns
2258 //===----------------------------------------------------------------------===//
2260 // 128-bit vector undef's.
2261 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2262 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2263 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2264 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2265 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2267 // 128-bit vector all zero's.
2268 def : Pat<(v16i8 immAllZerosV), (V_SET0_PI)>, Requires<[HasSSE2]>;
2269 def : Pat<(v8i16 immAllZerosV), (V_SET0_PI)>, Requires<[HasSSE2]>;
2270 def : Pat<(v4i32 immAllZerosV), (V_SET0_PI)>, Requires<[HasSSE2]>;
2272 // 128-bit vector all one's.
2273 def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2274 def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2275 def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2276 def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2277 def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
2279 // Store 128-bit integer vector values.
2280 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2281 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2282 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2283 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2284 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2285 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2287 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
2289 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2290 Requires<[HasSSE2]>;
2291 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2292 Requires<[HasSSE2]>;
2295 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
2296 Requires<[HasSSE2]>;
2297 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>,
2298 Requires<[HasSSE2]>;
2299 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>,
2300 Requires<[HasSSE2]>;
2301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>,
2302 Requires<[HasSSE2]>;
2303 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>,
2304 Requires<[HasSSE2]>;
2305 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2306 Requires<[HasSSE2]>;
2307 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2308 Requires<[HasSSE2]>;
2309 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2310 Requires<[HasSSE2]>;
2311 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>,
2312 Requires<[HasSSE2]>;
2313 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
2314 Requires<[HasSSE2]>;
2315 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>,
2316 Requires<[HasSSE2]>;
2317 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>,
2318 Requires<[HasSSE2]>;
2319 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>,
2320 Requires<[HasSSE2]>;
2321 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>,
2322 Requires<[HasSSE2]>;
2323 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>,
2324 Requires<[HasSSE2]>;
2325 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>,
2326 Requires<[HasSSE2]>;
2327 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>,
2328 Requires<[HasSSE2]>;
2329 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>,
2330 Requires<[HasSSE2]>;
2331 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>,
2332 Requires<[HasSSE2]>;
2333 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>,
2334 Requires<[HasSSE2]>;
2335 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>,
2336 Requires<[HasSSE2]>;
2337 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
2338 Requires<[HasSSE2]>;
2339 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>,
2340 Requires<[HasSSE2]>;
2341 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>,
2342 Requires<[HasSSE2]>;
2343 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>,
2344 Requires<[HasSSE2]>;
2345 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>,
2346 Requires<[HasSSE2]>;
2347 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>,
2348 Requires<[HasSSE2]>;
2349 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>,
2350 Requires<[HasSSE2]>;
2351 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>,
2352 Requires<[HasSSE2]>;
2353 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>,
2354 Requires<[HasSSE2]>;
2356 // Move scalar to XMM zero-extended
2357 // movd to XMM register zero-extends
2358 let AddedComplexity = 20 in {
2359 def : Pat<(v8i16 (vector_shuffle immAllZerosV,
2360 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2361 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2362 def : Pat<(v16i8 (vector_shuffle immAllZerosV,
2363 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2364 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2365 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2366 def : Pat<(v2f64 (vector_shuffle immAllZerosV,
2367 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2368 (MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>;
2369 def : Pat<(v4f32 (vector_shuffle immAllZerosV,
2370 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2371 (MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>;
2374 // Splat v2f64 / v2i64
2375 let AddedComplexity = 10 in {
2376 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2377 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2378 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2379 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2383 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2384 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
2385 Requires<[HasSSE1]>;
2387 // Special unary SHUFPSrri case.
2388 // FIXME: when we want non two-address code, then we should use PSHUFD?
2389 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2390 SHUFP_unary_shuffle_mask:$sm),
2391 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2392 Requires<[HasSSE1]>;
2393 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2394 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
2395 SHUFP_unary_shuffle_mask:$sm),
2396 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2397 Requires<[HasSSE2]>;
2398 // Special binary v4i32 shuffle cases with SHUFPS.
2399 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2400 PSHUFD_binary_shuffle_mask:$sm),
2401 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2402 Requires<[HasSSE2]>;
2403 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2404 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2405 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2406 Requires<[HasSSE2]>;
2408 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2409 let AddedComplexity = 10 in {
2410 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2411 UNPCKL_v_undef_shuffle_mask)),
2412 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2413 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2414 UNPCKL_v_undef_shuffle_mask)),
2415 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2416 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2417 UNPCKL_v_undef_shuffle_mask)),
2418 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2419 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2420 UNPCKL_v_undef_shuffle_mask)),
2421 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2424 let AddedComplexity = 20 in {
2425 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2426 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2427 MOVSHDUP_shuffle_mask)),
2428 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2429 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2430 MOVSHDUP_shuffle_mask)),
2431 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2433 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2434 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2435 MOVSLDUP_shuffle_mask)),
2436 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2437 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2438 MOVSLDUP_shuffle_mask)),
2439 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2442 let AddedComplexity = 20 in {
2443 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2444 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2445 MOVHP_shuffle_mask)),
2446 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2448 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2449 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2450 MOVHLPS_shuffle_mask)),
2451 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2453 // vector_shuffle v1, undef <2, 3, ?, ?> using MOVHLPS
2454 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2455 UNPCKH_shuffle_mask)),
2456 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2457 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2458 UNPCKH_shuffle_mask)),
2459 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2461 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2462 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2463 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2464 MOVLP_shuffle_mask)),
2465 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2466 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2467 MOVLP_shuffle_mask)),
2468 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2469 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2470 MOVHP_shuffle_mask)),
2471 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2472 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2473 MOVHP_shuffle_mask)),
2474 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2476 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2477 MOVLP_shuffle_mask)),
2478 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2479 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2480 MOVLP_shuffle_mask)),
2481 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2482 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2483 MOVHP_shuffle_mask)),
2484 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2485 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2486 MOVLP_shuffle_mask)),
2487 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2489 // Setting the lowest element in the vector.
2490 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2491 MOVL_shuffle_mask)),
2492 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2493 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2494 MOVL_shuffle_mask)),
2495 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2497 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2498 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2499 MOVLP_shuffle_mask)),
2500 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2501 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2502 MOVLP_shuffle_mask)),
2503 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2505 // Set lowest element and zero upper elements.
2506 def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2507 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2508 MOVL_shuffle_mask)),
2509 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2512 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2513 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2514 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2515 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2516 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2517 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2518 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2519 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2520 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2521 Requires<[HasSSE2]>;
2522 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2523 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2524 Requires<[HasSSE2]>;
2525 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2526 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2527 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2528 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2529 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2530 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2531 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2532 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2533 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2534 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2535 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2536 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2537 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2538 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2539 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2540 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2542 // 128-bit logical shifts
2543 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2544 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2545 Requires<[HasSSE2]>;
2546 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2547 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2548 Requires<[HasSSE2]>;
2550 // Some special case pandn patterns.
2551 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2553 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2554 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2556 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2557 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2559 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2561 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2562 (load addr:$src2))),
2563 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2564 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2565 (load addr:$src2))),
2566 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2567 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2568 (load addr:$src2))),
2569 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;