1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
244 Domain d, OpndItins itins, bit Is2Addr = 1> {
245 let isCommutable = 1 in {
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
251 Sched<[itins.Sched]>;
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
258 Sched<[itins.Sched.Folded, ReadAfterLd]>;
261 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
262 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
263 string asm, string SSEVer, string FPSizeStr,
264 Operand memopr, ComplexPattern mem_cpat,
265 Domain d, OpndItins itins, bit Is2Addr = 1> {
266 let isCodeGenOnly = 1 in {
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
269 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 [(set RC:$dst, (!cast<Intrinsic>(
272 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
273 RC:$src1, RC:$src2))], itins.rr, d>,
274 Sched<[itins.Sched]>;
275 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
277 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
279 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
280 SSEVer, "_", OpcodeStr, FPSizeStr))
281 RC:$src1, mem_cpat:$src2))], itins.rm, d>,
282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
286 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
288 RegisterClass RC, ValueType vt,
289 X86MemOperand x86memop, PatFrag mem_frag,
290 Domain d, OpndItins itins, bit Is2Addr = 1> {
291 let isCommutable = 1 in
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
297 Sched<[itins.Sched]>;
299 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
305 Sched<[itins.Sched.Folded, ReadAfterLd]>;
308 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
309 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
310 string OpcodeStr, X86MemOperand x86memop,
311 list<dag> pat_rr, list<dag> pat_rm,
313 let isCommutable = 1, hasSideEffects = 0 in
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
318 pat_rr, NoItinerary, d>,
319 Sched<[WriteVecLogic]>;
320 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
324 pat_rm, NoItinerary, d>,
325 Sched<[WriteVecLogicLd, ReadAfterLd]>;
328 //===----------------------------------------------------------------------===//
329 // Non-instruction patterns
330 //===----------------------------------------------------------------------===//
332 // A vector extract of the first f32/f64 position is a subregister copy
333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
338 // A 128-bit subvector extract from the first 256-bit vector position
339 // is a subregister copy that needs no instruction.
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
355 // A 128-bit subvector insert to the first 256-bit vector position
356 // is a subregister copy that needs no instruction.
357 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
372 // Implicitly promote a 32-bit scalar to a vector.
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 // Implicitly promote a 64-bit scalar to a vector.
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
383 // Bitcasts between 128-bit vector types. Return the original type since
384 // no instruction is needed for the conversion
385 let Predicates = [HasSSE2] in {
386 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
387 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
388 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
392 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
397 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
402 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
407 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
412 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
418 // Bitcasts between 256-bit vector types. Return the original type since
419 // no instruction is needed for the conversion
420 let Predicates = [HasAVX] in {
421 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
422 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
423 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
427 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
432 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
437 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
442 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
447 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
453 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
454 // This is expanded by ExpandPostRAPseudos.
455 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
456 isPseudo = 1, SchedRW = [WriteZero] in {
457 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
458 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
459 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
460 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
463 //===----------------------------------------------------------------------===//
464 // AVX & SSE - Zero/One Vectors
465 //===----------------------------------------------------------------------===//
467 // Alias instruction that maps zero vector to pxor / xorp* for sse.
468 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
469 // swizzled by ExecutionDepsFix to pxor.
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-zeros value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
478 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
479 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
480 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
482 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
485 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
486 // and doesn't need it because on sandy bridge the register is set to zero
487 // at the rename stage without using any execution unit, so SET0PSY
488 // and SET0PDY can be used for vector int instructions without penalty
489 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
490 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
491 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
492 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
495 let Predicates = [HasAVX] in
496 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
498 let Predicates = [HasAVX2] in {
499 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
500 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
501 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
505 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
506 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
507 let Predicates = [HasAVX1Only] in {
508 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
509 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
510 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
513 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
514 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
517 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
518 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
521 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
522 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
525 // We set canFoldAsLoad because this can be converted to a constant-pool
526 // load of an all-ones value if folding it would be beneficial.
527 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
528 isPseudo = 1, SchedRW = [WriteZero] in {
529 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
530 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
531 let Predicates = [HasAVX2] in
532 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
533 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
537 //===----------------------------------------------------------------------===//
538 // SSE 1 & 2 - Move FP Scalar Instructions
540 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
541 // register copies because it's a partial register update; Register-to-register
542 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
543 // that the insert be implementable in terms of a copy, and just mentioned, we
544 // don't use movss/movsd for copies.
545 //===----------------------------------------------------------------------===//
547 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
548 X86MemOperand x86memop, string base_opc,
549 string asm_opr, Domain d = GenericDomain> {
550 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
551 (ins VR128:$src1, RC:$src2),
552 !strconcat(base_opc, asm_opr),
553 [(set VR128:$dst, (vt (OpNode VR128:$src1,
554 (scalar_to_vector RC:$src2))))],
555 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
557 // For the disassembler
558 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
559 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
560 (ins VR128:$src1, RC:$src2),
561 !strconcat(base_opc, asm_opr),
562 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
565 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
566 X86MemOperand x86memop, string OpcodeStr,
567 Domain d = GenericDomain> {
569 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
573 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
575 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
576 VEX, VEX_LIG, Sched<[WriteStore]>;
578 let Constraints = "$src1 = $dst" in {
579 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
580 "\t{$src2, $dst|$dst, $src2}", d>;
583 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
585 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
589 // Loading from memory automatically zeroing upper bits.
590 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
591 PatFrag mem_pat, string OpcodeStr,
592 Domain d = GenericDomain> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
604 SSEPackedSingle>, XS;
605 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
606 SSEPackedDouble>, XD;
608 let canFoldAsLoad = 1, isReMaterializable = 1 in {
609 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
610 SSEPackedSingle>, XS;
612 let AddedComplexity = 20 in
613 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
614 SSEPackedDouble>, XD;
618 let Predicates = [UseAVX] in {
619 let AddedComplexity = 20 in {
620 // MOVSSrm zeros the high parts of the register; represent this
621 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
624 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
629 // MOVSDrm zeros the high parts of the register; represent this
630 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
631 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzload addr:$src)),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
642 // Represent the same patterns above but in the form they appear for
644 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
645 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
646 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
647 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
648 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
649 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
652 // Extract and store.
653 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
655 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
656 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
658 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
660 // Shuffle with VMOVSS
661 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
662 (VMOVSSrr (v4i32 VR128:$src1),
663 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
664 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
665 (VMOVSSrr (v4f32 VR128:$src1),
666 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
669 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
670 (SUBREG_TO_REG (i32 0),
671 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
672 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
674 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
675 (SUBREG_TO_REG (i32 0),
676 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
677 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
680 // Shuffle with VMOVSD
681 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
682 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
683 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
694 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
696 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
697 (SUBREG_TO_REG (i32 0),
698 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
699 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
702 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
703 // is during lowering, where it's not possible to recognize the fold cause
704 // it has two uses through a bitcast. One use disappears at isel time and the
705 // fold opportunity reappears.
706 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
707 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 let Predicates = [UseSSE1] in {
717 let Predicates = [NoSSE41], AddedComplexity = 15 in {
718 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
719 // MOVSS to the lower bits.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
721 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
722 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
723 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
728 let AddedComplexity = 20 in {
729 // MOVSSrm already zeros the high parts of the register.
730 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
731 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
732 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
738 // Extract and store.
739 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
741 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
743 // Shuffle with MOVSS
744 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
745 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
746 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
750 let Predicates = [UseSSE2] in {
751 let Predicates = [NoSSE41], AddedComplexity = 15 in {
752 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
753 // MOVSD to the lower bits.
754 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
755 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
758 let AddedComplexity = 20 in {
759 // MOVSDrm already zeros the high parts of the register.
760 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzload addr:$src)),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 // Extract and store.
773 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
775 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
777 // Shuffle with MOVSD
778 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
779 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
780 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
788 // is during lowering, where it's not possible to recognize the fold because
789 // it has two uses through a bitcast. One use disappears at isel time and the
790 // fold opportunity reappears.
791 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 //===----------------------------------------------------------------------===//
802 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
803 //===----------------------------------------------------------------------===//
805 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
806 X86MemOperand x86memop, PatFrag ld_frag,
807 string asm, Domain d,
809 bit IsReMaterializable = 1> {
810 let hasSideEffects = 0 in
811 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
812 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
813 Sched<[WriteFShuffle]>;
814 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
815 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
816 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
817 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
821 let Predicates = [HasAVX, NoVLX] in {
822 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
823 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
825 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
826 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
828 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
829 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
831 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
832 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let Predicates = [UseSSE1] in {
850 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
851 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
853 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
854 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
857 let Predicates = [UseSSE2] in {
858 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
859 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
861 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
862 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
867 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
868 "movaps\t{$src, $dst|$dst, $src}",
869 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
870 IIC_SSE_MOVA_P_MR>, VEX;
871 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
872 "movapd\t{$src, $dst|$dst, $src}",
873 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
874 IIC_SSE_MOVA_P_MR>, VEX;
875 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movups\t{$src, $dst|$dst, $src}",
877 [(store (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVU_P_MR>, VEX;
879 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movupd\t{$src, $dst|$dst, $src}",
881 [(store (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVU_P_MR>, VEX;
883 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
884 "movaps\t{$src, $dst|$dst, $src}",
885 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
886 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
887 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
888 "movapd\t{$src, $dst|$dst, $src}",
889 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
890 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
891 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movups\t{$src, $dst|$dst, $src}",
893 [(store (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
895 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movupd\t{$src, $dst|$dst, $src}",
897 [(store (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
902 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
903 SchedRW = [WriteFShuffle] in {
904 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
906 "movaps\t{$src, $dst|$dst, $src}", [],
907 IIC_SSE_MOVA_P_RR>, VEX;
908 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
910 "movapd\t{$src, $dst|$dst, $src}", [],
911 IIC_SSE_MOVA_P_RR>, VEX;
912 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
914 "movups\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVU_P_RR>, VEX;
916 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
918 "movupd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVU_P_RR>, VEX;
920 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
922 "movaps\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
924 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
926 "movapd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
928 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
930 "movups\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
932 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
934 "movupd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
938 let Predicates = [HasAVX] in {
939 def : Pat<(v8i32 (X86vzmovl
940 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v4i64 (X86vzmovl
943 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v8f32 (X86vzmovl
946 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
948 def : Pat<(v4f64 (X86vzmovl
949 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
950 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
954 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
955 (VMOVUPSYmr addr:$dst, VR256:$src)>;
956 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
957 (VMOVUPDYmr addr:$dst, VR256:$src)>;
959 let SchedRW = [WriteStore] in {
960 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movaps\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
964 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movapd\t{$src, $dst|$dst, $src}",
966 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
968 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}",
970 [(store (v4f32 VR128:$src), addr:$dst)],
972 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
973 "movupd\t{$src, $dst|$dst, $src}",
974 [(store (v2f64 VR128:$src), addr:$dst)],
979 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
980 SchedRW = [WriteFShuffle] in {
981 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movaps\t{$src, $dst|$dst, $src}", [],
984 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movapd\t{$src, $dst|$dst, $src}", [],
987 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
988 "movups\t{$src, $dst|$dst, $src}", [],
990 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
991 "movupd\t{$src, $dst|$dst, $src}", [],
995 let Predicates = [HasAVX] in {
996 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
999 (VMOVUPDmr addr:$dst, VR128:$src)>;
1002 let Predicates = [UseSSE1] in
1003 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1004 (MOVUPSmr addr:$dst, VR128:$src)>;
1005 let Predicates = [UseSSE2] in
1006 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1007 (MOVUPDmr addr:$dst, VR128:$src)>;
1009 // Use vmovaps/vmovups for AVX integer load/store.
1010 let Predicates = [HasAVX, NoVLX] in {
1011 // 128-bit load/store
1012 def : Pat<(alignedloadv2i64 addr:$src),
1013 (VMOVAPSrm addr:$src)>;
1014 def : Pat<(loadv2i64 addr:$src),
1015 (VMOVUPSrm addr:$src)>;
1017 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1034 // 256-bit load/store
1035 def : Pat<(alignedloadv4i64 addr:$src),
1036 (VMOVAPSYrm addr:$src)>;
1037 def : Pat<(loadv4i64 addr:$src),
1038 (VMOVUPSYrm addr:$src)>;
1039 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1056 // Special patterns for storing subvector extracts of lower 128-bits
1057 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1058 def : Pat<(alignedstore (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(alignedstore (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(alignedstore (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(alignedstore (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(alignedstore (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(alignedstore (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1077 def : Pat<(store (v2f64 (extract_subvector
1078 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1079 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1080 def : Pat<(store (v4f32 (extract_subvector
1081 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1082 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1083 def : Pat<(store (v2i64 (extract_subvector
1084 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1085 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1086 def : Pat<(store (v4i32 (extract_subvector
1087 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1088 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1089 def : Pat<(store (v8i16 (extract_subvector
1090 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1091 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1092 def : Pat<(store (v16i8 (extract_subvector
1093 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1094 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1097 // Use movaps / movups for SSE integer load / store (one byte shorter).
1098 // The instructions selected below are then converted to MOVDQA/MOVDQU
1099 // during the SSE domain pass.
1100 let Predicates = [UseSSE1] in {
1101 def : Pat<(alignedloadv2i64 addr:$src),
1102 (MOVAPSrm addr:$src)>;
1103 def : Pat<(loadv2i64 addr:$src),
1104 (MOVUPSrm addr:$src)>;
1106 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1107 (MOVAPSmr addr:$dst, VR128:$src)>;
1108 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1115 (MOVUPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1124 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1125 // bits are disregarded. FIXME: Set encoding to pseudo!
1126 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1127 let isCodeGenOnly = 1 in {
1128 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1129 "movaps\t{$src, $dst|$dst, $src}",
1130 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1131 IIC_SSE_MOVA_P_RM>, VEX;
1132 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1133 "movapd\t{$src, $dst|$dst, $src}",
1134 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1135 IIC_SSE_MOVA_P_RM>, VEX;
1136 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1137 "movaps\t{$src, $dst|$dst, $src}",
1138 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1140 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1141 "movapd\t{$src, $dst|$dst, $src}",
1142 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1147 //===----------------------------------------------------------------------===//
1148 // SSE 1 & 2 - Move Low packed FP Instructions
1149 //===----------------------------------------------------------------------===//
1151 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1152 string base_opc, string asm_opr,
1153 InstrItinClass itin> {
1154 def PSrm : PI<opc, MRMSrcMem,
1155 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1156 !strconcat(base_opc, "s", asm_opr),
1158 (psnode VR128:$src1,
1159 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1160 itin, SSEPackedSingle>, PS,
1161 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1163 def PDrm : PI<opc, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1165 !strconcat(base_opc, "d", asm_opr),
1166 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1167 (scalar_to_vector (loadf64 addr:$src2)))))],
1168 itin, SSEPackedDouble>, PD,
1169 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1173 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1174 string base_opc, InstrItinClass itin> {
1175 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1179 let Constraints = "$src1 = $dst" in
1180 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1181 "\t{$src2, $dst|$dst, $src2}",
1185 let AddedComplexity = 20 in {
1186 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1190 let SchedRW = [WriteStore] in {
1191 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1192 "movlps\t{$src, $dst|$dst, $src}",
1193 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1194 (iPTR 0))), addr:$dst)],
1195 IIC_SSE_MOV_LH>, VEX;
1196 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1197 "movlpd\t{$src, $dst|$dst, $src}",
1198 [(store (f64 (vector_extract (v2f64 VR128:$src),
1199 (iPTR 0))), addr:$dst)],
1200 IIC_SSE_MOV_LH>, VEX;
1201 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1202 "movlps\t{$src, $dst|$dst, $src}",
1203 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1204 (iPTR 0))), addr:$dst)],
1206 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1207 "movlpd\t{$src, $dst|$dst, $src}",
1208 [(store (f64 (vector_extract (v2f64 VR128:$src),
1209 (iPTR 0))), addr:$dst)],
1213 let Predicates = [HasAVX] in {
1214 // Shuffle with VMOVLPS
1215 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1216 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1220 // Shuffle with VMOVLPD
1221 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1222 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1226 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1227 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1235 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1236 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1238 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1239 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1241 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1244 let Predicates = [UseSSE1] in {
1245 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1246 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1247 (iPTR 0))), addr:$src1),
1248 (MOVLPSmr addr:$src1, VR128:$src2)>;
1250 // Shuffle with MOVLPS
1251 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1252 (MOVLPSrm VR128:$src1, addr:$src2)>;
1253 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(X86Movlps VR128:$src1,
1256 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1257 (MOVLPSrm VR128:$src1, addr:$src2)>;
1260 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1262 (MOVLPSmr addr:$src1, VR128:$src2)>;
1263 def : Pat<(store (v4i32 (X86Movlps
1264 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1266 (MOVLPSmr addr:$src1, VR128:$src2)>;
1269 let Predicates = [UseSSE2] in {
1270 // Shuffle with MOVLPD
1271 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1272 (MOVLPDrm VR128:$src1, addr:$src2)>;
1273 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1276 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1277 (MOVLPDrm VR128:$src1, addr:$src2)>;
1280 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1282 (MOVLPDmr addr:$src1, VR128:$src2)>;
1283 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1285 (MOVLPDmr addr:$src1, VR128:$src2)>;
1288 //===----------------------------------------------------------------------===//
1289 // SSE 1 & 2 - Move Hi packed FP Instructions
1290 //===----------------------------------------------------------------------===//
1292 let AddedComplexity = 20 in {
1293 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1297 let SchedRW = [WriteStore] in {
1298 // v2f64 extract element 1 is always custom lowered to unpack high to low
1299 // and extract element 0 so the non-store version isn't too horrible.
1300 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1301 "movhps\t{$src, $dst|$dst, $src}",
1302 [(store (f64 (vector_extract
1303 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1304 (bc_v2f64 (v4f32 VR128:$src))),
1305 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1306 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1307 "movhpd\t{$src, $dst|$dst, $src}",
1308 [(store (f64 (vector_extract
1309 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1310 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1311 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1312 "movhps\t{$src, $dst|$dst, $src}",
1313 [(store (f64 (vector_extract
1314 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1315 (bc_v2f64 (v4f32 VR128:$src))),
1316 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1317 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1318 "movhpd\t{$src, $dst|$dst, $src}",
1319 [(store (f64 (vector_extract
1320 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1321 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(X86Movlhps VR128:$src1,
1327 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1328 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1329 def : Pat<(X86Movlhps VR128:$src1,
1330 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1331 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1335 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1336 // is during lowering, where it's not possible to recognize the load fold
1337 // cause it has two uses through a bitcast. One use disappears at isel time
1338 // and the fold opportunity reappears.
1339 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1340 (scalar_to_vector (loadf64 addr:$src2)))),
1341 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1342 // Also handle an i64 load because that may get selected as a faster way to
1344 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1345 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1346 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1348 def : Pat<(store (f64 (vector_extract
1349 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1350 (iPTR 0))), addr:$dst),
1351 (VMOVHPDmr addr:$dst, VR128:$src)>;
1354 let Predicates = [UseSSE1] in {
1356 def : Pat<(X86Movlhps VR128:$src1,
1357 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1358 (MOVHPSrm VR128:$src1, addr:$src2)>;
1359 def : Pat<(X86Movlhps VR128:$src1,
1360 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1361 (MOVHPSrm VR128:$src1, addr:$src2)>;
1364 let Predicates = [UseSSE2] in {
1367 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1368 // is during lowering, where it's not possible to recognize the load fold
1369 // cause it has two uses through a bitcast. One use disappears at isel time
1370 // and the fold opportunity reappears.
1371 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1372 (scalar_to_vector (loadf64 addr:$src2)))),
1373 (MOVHPDrm VR128:$src1, addr:$src2)>;
1374 // Also handle an i64 load because that may get selected as a faster way to
1376 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1377 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1378 (MOVHPDrm VR128:$src1, addr:$src2)>;
1380 def : Pat<(store (f64 (vector_extract
1381 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1382 (iPTR 0))), addr:$dst),
1383 (MOVHPDmr addr:$dst, VR128:$src)>;
1386 //===----------------------------------------------------------------------===//
1387 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1388 //===----------------------------------------------------------------------===//
1390 let AddedComplexity = 20, Predicates = [UseAVX] in {
1391 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1392 (ins VR128:$src1, VR128:$src2),
1393 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1395 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1397 VEX_4V, Sched<[WriteFShuffle]>;
1398 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1399 (ins VR128:$src1, VR128:$src2),
1400 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1402 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1404 VEX_4V, Sched<[WriteFShuffle]>;
1406 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1407 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1408 (ins VR128:$src1, VR128:$src2),
1409 "movlhps\t{$src2, $dst|$dst, $src2}",
1411 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1412 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1413 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1414 (ins VR128:$src1, VR128:$src2),
1415 "movhlps\t{$src2, $dst|$dst, $src2}",
1417 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1418 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1421 let Predicates = [UseAVX] in {
1423 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1424 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1425 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1429 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1430 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1433 let Predicates = [UseSSE1] in {
1435 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1436 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1437 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1441 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1442 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1445 //===----------------------------------------------------------------------===//
1446 // SSE 1 & 2 - Conversion Instructions
1447 //===----------------------------------------------------------------------===//
1449 def SSE_CVT_PD : OpndItins<
1450 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1453 let Sched = WriteCvtI2F in
1454 def SSE_CVT_PS : OpndItins<
1455 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1458 let Sched = WriteCvtI2F in
1459 def SSE_CVT_Scalar : OpndItins<
1460 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1463 let Sched = WriteCvtF2I in
1464 def SSE_CVT_SS2SI_32 : OpndItins<
1465 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1468 let Sched = WriteCvtF2I in
1469 def SSE_CVT_SS2SI_64 : OpndItins<
1470 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1473 let Sched = WriteCvtF2I in
1474 def SSE_CVT_SD2SI : OpndItins<
1475 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1478 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1479 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1480 string asm, OpndItins itins> {
1481 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1482 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1483 itins.rr>, Sched<[itins.Sched]>;
1484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1485 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1486 itins.rm>, Sched<[itins.Sched.Folded]>;
1489 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1490 X86MemOperand x86memop, string asm, Domain d,
1492 let hasSideEffects = 0 in {
1493 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1494 [], itins.rr, d>, Sched<[itins.Sched]>;
1496 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1497 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1501 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1502 X86MemOperand x86memop, string asm> {
1503 let hasSideEffects = 0, Predicates = [UseAVX] in {
1504 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1505 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1506 Sched<[WriteCvtI2F]>;
1508 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1509 (ins DstRC:$src1, x86memop:$src),
1510 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1511 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1512 } // hasSideEffects = 0
1515 let Predicates = [UseAVX] in {
1516 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1517 "cvttss2si\t{$src, $dst|$dst, $src}",
1520 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1521 "cvttss2si\t{$src, $dst|$dst, $src}",
1523 XS, VEX, VEX_W, VEX_LIG;
1524 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1525 "cvttsd2si\t{$src, $dst|$dst, $src}",
1528 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1529 "cvttsd2si\t{$src, $dst|$dst, $src}",
1531 XD, VEX, VEX_W, VEX_LIG;
1533 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1534 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1537 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1541 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1545 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1550 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1551 // register, but the same isn't true when only using memory operands,
1552 // provide other assembly "l" and "q" forms to address this explicitly
1553 // where appropriate to do so.
1554 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1555 XS, VEX_4V, VEX_LIG;
1556 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1557 XS, VEX_4V, VEX_W, VEX_LIG;
1558 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1559 XD, VEX_4V, VEX_LIG;
1560 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1561 XD, VEX_4V, VEX_W, VEX_LIG;
1563 let Predicates = [UseAVX] in {
1564 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1565 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1566 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1569 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1570 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1571 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1572 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1574 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1576 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1578 def : Pat<(f32 (sint_to_fp GR32:$src)),
1579 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR64:$src)),
1581 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1582 def : Pat<(f64 (sint_to_fp GR32:$src)),
1583 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR64:$src)),
1585 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1588 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1589 "cvttss2si\t{$src, $dst|$dst, $src}",
1590 SSE_CVT_SS2SI_32>, XS;
1591 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1592 "cvttss2si\t{$src, $dst|$dst, $src}",
1593 SSE_CVT_SS2SI_64>, XS, REX_W;
1594 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1595 "cvttsd2si\t{$src, $dst|$dst, $src}",
1597 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1598 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 SSE_CVT_SD2SI>, XD, REX_W;
1600 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1601 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1602 SSE_CVT_Scalar>, XS;
1603 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1604 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1605 SSE_CVT_Scalar>, XS, REX_W;
1606 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1607 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1608 SSE_CVT_Scalar>, XD;
1609 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1610 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1611 SSE_CVT_Scalar>, XD, REX_W;
1613 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1614 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1617 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1621 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1622 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1625 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1630 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1631 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1632 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1635 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1636 // and/or XMM operand(s).
1638 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1639 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1640 string asm, OpndItins itins> {
1641 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1642 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1643 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1644 Sched<[itins.Sched]>;
1645 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1646 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1647 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1648 Sched<[itins.Sched.Folded]>;
1651 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1652 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1653 PatFrag ld_frag, string asm, OpndItins itins,
1655 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1657 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1658 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1659 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1660 itins.rr>, Sched<[itins.Sched]>;
1661 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1662 (ins DstRC:$src1, x86memop:$src2),
1664 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1665 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1666 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1667 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1670 let Predicates = [UseAVX] in {
1671 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1672 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1673 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1674 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1675 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1676 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1678 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1679 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1680 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1684 let isCodeGenOnly = 1 in {
1685 let Predicates = [UseAVX] in {
1686 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1687 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1688 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1689 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1690 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1691 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1693 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1694 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1695 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1696 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1697 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1698 SSE_CVT_Scalar, 0>, XD,
1701 let Constraints = "$src1 = $dst" in {
1702 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1703 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1704 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1705 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1706 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1707 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1708 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1709 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1710 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1711 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1712 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1713 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1715 } // isCodeGenOnly = 1
1719 // Aliases for intrinsics
1720 let isCodeGenOnly = 1 in {
1721 let Predicates = [UseAVX] in {
1722 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1723 ssmem, sse_load_f32, "cvttss2si",
1724 SSE_CVT_SS2SI_32>, XS, VEX;
1725 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1726 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1727 "cvttss2si", SSE_CVT_SS2SI_64>,
1729 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1730 sdmem, sse_load_f64, "cvttsd2si",
1731 SSE_CVT_SD2SI>, XD, VEX;
1732 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1733 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1734 "cvttsd2si", SSE_CVT_SD2SI>,
1737 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1738 ssmem, sse_load_f32, "cvttss2si",
1739 SSE_CVT_SS2SI_32>, XS;
1740 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1741 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1742 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1743 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1744 sdmem, sse_load_f64, "cvttsd2si",
1746 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1747 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1748 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1749 } // isCodeGenOnly = 1
1751 let Predicates = [UseAVX] in {
1752 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1753 ssmem, sse_load_f32, "cvtss2si",
1754 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1755 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1756 ssmem, sse_load_f32, "cvtss2si",
1757 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1759 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1760 ssmem, sse_load_f32, "cvtss2si",
1761 SSE_CVT_SS2SI_32>, XS;
1762 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1763 ssmem, sse_load_f32, "cvtss2si",
1764 SSE_CVT_SS2SI_64>, XS, REX_W;
1766 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1767 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1768 SSEPackedSingle, SSE_CVT_PS>,
1769 PS, VEX, Requires<[HasAVX]>;
1770 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1771 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1772 SSEPackedSingle, SSE_CVT_PS>,
1773 PS, VEX, VEX_L, Requires<[HasAVX]>;
1775 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1776 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1777 SSEPackedSingle, SSE_CVT_PS>,
1778 PS, Requires<[UseSSE2]>;
1780 let Predicates = [UseAVX] in {
1781 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1782 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1785 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1789 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1790 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1793 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1799 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1800 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1803 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1807 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1808 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1811 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1818 // Convert scalar double to scalar single
1819 let hasSideEffects = 0, Predicates = [UseAVX] in {
1820 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1821 (ins FR64:$src1, FR64:$src2),
1822 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1823 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1824 Sched<[WriteCvtF2F]>;
1826 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1827 (ins FR64:$src1, f64mem:$src2),
1828 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1829 [], IIC_SSE_CVT_Scalar_RM>,
1830 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1831 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1834 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1837 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1838 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1839 [(set FR32:$dst, (fround FR64:$src))],
1840 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1841 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1842 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1843 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1844 IIC_SSE_CVT_Scalar_RM>,
1846 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1848 let isCodeGenOnly = 1 in {
1849 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1851 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1853 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1854 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1855 Sched<[WriteCvtF2F]>;
1856 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1857 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1858 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1859 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1860 VR128:$src1, sse_load_f64:$src2))],
1861 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1862 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1864 let Constraints = "$src1 = $dst" in {
1865 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1869 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1870 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1871 Sched<[WriteCvtF2F]>;
1872 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1873 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1874 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1875 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1876 VR128:$src1, sse_load_f64:$src2))],
1877 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1878 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1880 } // isCodeGenOnly = 1
1882 // Convert scalar single to scalar double
1883 // SSE2 instructions with XS prefix
1884 let hasSideEffects = 0, Predicates = [UseAVX] in {
1885 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1886 (ins FR32:$src1, FR32:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1888 [], IIC_SSE_CVT_Scalar_RR>,
1889 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1890 Sched<[WriteCvtF2F]>;
1892 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1893 (ins FR32:$src1, f32mem:$src2),
1894 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1895 [], IIC_SSE_CVT_Scalar_RM>,
1896 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1897 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1900 def : Pat<(f64 (fextend FR32:$src)),
1901 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1902 def : Pat<(fextend (loadf32 addr:$src)),
1903 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1905 def : Pat<(extloadf32 addr:$src),
1906 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1907 Requires<[UseAVX, OptForSize]>;
1908 def : Pat<(extloadf32 addr:$src),
1909 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1910 Requires<[UseAVX, OptForSpeed]>;
1912 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1913 "cvtss2sd\t{$src, $dst|$dst, $src}",
1914 [(set FR64:$dst, (fextend FR32:$src))],
1915 IIC_SSE_CVT_Scalar_RR>, XS,
1916 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1917 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1918 "cvtss2sd\t{$src, $dst|$dst, $src}",
1919 [(set FR64:$dst, (extloadf32 addr:$src))],
1920 IIC_SSE_CVT_Scalar_RM>, XS,
1921 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1923 // extload f32 -> f64. This matches load+fextend because we have a hack in
1924 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1926 // Since these loads aren't folded into the fextend, we have to match it
1928 def : Pat<(fextend (loadf32 addr:$src)),
1929 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1930 def : Pat<(extloadf32 addr:$src),
1931 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1933 let isCodeGenOnly = 1 in {
1934 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1935 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1936 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1938 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1939 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1940 Sched<[WriteCvtF2F]>;
1941 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1942 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1943 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1945 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1946 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1947 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1948 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1949 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1950 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1951 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1953 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1954 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1955 Sched<[WriteCvtF2F]>;
1956 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1957 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1958 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1960 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1961 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1962 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1964 } // isCodeGenOnly = 1
1966 // Convert packed single/double fp to doubleword
1967 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvtps2dq\t{$src, $dst|$dst, $src}",
1969 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1970 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1971 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1972 "cvtps2dq\t{$src, $dst|$dst, $src}",
1974 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1975 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1976 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1977 "cvtps2dq\t{$src, $dst|$dst, $src}",
1979 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1980 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1981 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1982 "cvtps2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1985 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1986 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvtps2dq\t{$src, $dst|$dst, $src}",
1988 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1989 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1990 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1991 "cvtps2dq\t{$src, $dst|$dst, $src}",
1993 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1994 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1997 // Convert Packed Double FP to Packed DW Integers
1998 let Predicates = [HasAVX] in {
1999 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2000 // register, but the same isn't true when using memory operands instead.
2001 // Provide other assembly rr and rm forms to address this explicitly.
2002 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2003 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2004 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2005 VEX, Sched<[WriteCvtF2I]>;
2008 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2009 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2010 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2011 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2013 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2014 Sched<[WriteCvtF2ILd]>;
2017 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2018 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2020 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2021 Sched<[WriteCvtF2I]>;
2022 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2023 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2025 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2026 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2027 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2028 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2031 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2032 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2034 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2035 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2036 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2037 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2038 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2039 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2041 // Convert with truncation packed single/double fp to doubleword
2042 // SSE2 packed instructions with XS prefix
2043 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttps2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttps2dq VR128:$src))],
2047 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2048 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2049 "cvttps2dq\t{$src, $dst|$dst, $src}",
2050 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2051 (loadv4f32 addr:$src)))],
2052 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2053 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2054 "cvttps2dq\t{$src, $dst|$dst, $src}",
2056 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2057 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2058 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2059 "cvttps2dq\t{$src, $dst|$dst, $src}",
2060 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2061 (loadv8f32 addr:$src)))],
2062 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2063 Sched<[WriteCvtF2ILd]>;
2065 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2066 "cvttps2dq\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2068 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2069 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2070 "cvttps2dq\t{$src, $dst|$dst, $src}",
2072 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2073 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2075 let Predicates = [HasAVX] in {
2076 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2077 (VCVTDQ2PSrr VR128:$src)>;
2078 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2079 (VCVTDQ2PSrm addr:$src)>;
2081 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2082 (VCVTDQ2PSrr VR128:$src)>;
2083 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2084 (VCVTDQ2PSrm addr:$src)>;
2086 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2087 (VCVTTPS2DQrr VR128:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2089 (VCVTTPS2DQrm addr:$src)>;
2091 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2092 (VCVTDQ2PSYrr VR256:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2094 (VCVTDQ2PSYrm addr:$src)>;
2096 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2097 (VCVTTPS2DQYrr VR256:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2099 (VCVTTPS2DQYrm addr:$src)>;
2102 let Predicates = [UseSSE2] in {
2103 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2104 (CVTDQ2PSrr VR128:$src)>;
2105 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2106 (CVTDQ2PSrm addr:$src)>;
2108 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2109 (CVTDQ2PSrr VR128:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2111 (CVTDQ2PSrm addr:$src)>;
2113 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2114 (CVTTPS2DQrr VR128:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2116 (CVTTPS2DQrm addr:$src)>;
2119 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2120 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2122 (int_x86_sse2_cvttpd2dq VR128:$src))],
2123 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2125 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2126 // register, but the same isn't true when using memory operands instead.
2127 // Provide other assembly rr and rm forms to address this explicitly.
2130 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2131 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2132 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2133 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2134 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2135 (loadv2f64 addr:$src)))],
2136 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2139 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2140 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2142 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2143 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2144 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2145 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2147 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2148 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2149 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2150 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2152 let Predicates = [HasAVX] in {
2153 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2154 (VCVTTPD2DQYrr VR256:$src)>;
2155 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2156 (VCVTTPD2DQYrm addr:$src)>;
2157 } // Predicates = [HasAVX]
2159 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2160 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2161 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2162 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2163 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2164 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2165 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2166 (memopv2f64 addr:$src)))],
2168 Sched<[WriteCvtF2ILd]>;
2170 // Convert packed single to packed double
2171 let Predicates = [HasAVX] in {
2172 // SSE2 instructions without OpSize prefix
2173 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2174 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2175 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2176 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2177 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2178 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2179 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2180 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2181 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2182 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2184 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2185 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2186 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2187 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2189 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2190 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2193 let Predicates = [UseSSE2] in {
2194 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2195 "cvtps2pd\t{$src, $dst|$dst, $src}",
2196 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2197 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2198 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2199 "cvtps2pd\t{$src, $dst|$dst, $src}",
2200 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2201 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2204 // Convert Packed DW Integers to Packed Double FP
2205 let Predicates = [HasAVX] in {
2206 let hasSideEffects = 0, mayLoad = 1 in
2207 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2208 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2209 []>, VEX, Sched<[WriteCvtI2FLd]>;
2210 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2211 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2213 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2214 Sched<[WriteCvtI2F]>;
2215 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2216 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2218 (int_x86_avx_cvtdq2_pd_256
2219 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2220 Sched<[WriteCvtI2FLd]>;
2221 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2222 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2224 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2225 Sched<[WriteCvtI2F]>;
2228 let hasSideEffects = 0, mayLoad = 1 in
2229 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2230 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2231 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2232 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2233 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2234 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2235 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2237 // AVX register conversion intrinsics
2238 let Predicates = [HasAVX] in {
2239 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2240 (VCVTDQ2PDrr VR128:$src)>;
2241 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2242 (VCVTDQ2PDrm addr:$src)>;
2244 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2245 (VCVTDQ2PDYrr VR128:$src)>;
2246 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2247 (VCVTDQ2PDYrm addr:$src)>;
2248 } // Predicates = [HasAVX]
2250 // SSE2 register conversion intrinsics
2251 let Predicates = [HasSSE2] in {
2252 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2253 (CVTDQ2PDrr VR128:$src)>;
2254 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2255 (CVTDQ2PDrm addr:$src)>;
2256 } // Predicates = [HasSSE2]
2258 // Convert packed double to packed single
2259 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2260 // register, but the same isn't true when using memory operands instead.
2261 // Provide other assembly rr and rm forms to address this explicitly.
2262 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2263 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2264 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2265 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2268 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2269 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2270 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2271 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2273 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2274 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2277 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2278 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2280 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2281 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2282 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2283 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2285 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2286 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2287 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2288 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2290 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2291 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2292 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2293 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2294 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2295 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2297 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2298 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2301 // AVX 256-bit register conversion intrinsics
2302 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2303 // whenever possible to avoid declaring two versions of each one.
2304 let Predicates = [HasAVX] in {
2305 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2306 (VCVTDQ2PSYrr VR256:$src)>;
2307 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2308 (VCVTDQ2PSYrm addr:$src)>;
2310 // Match fround and fextend for 128/256-bit conversions
2311 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2312 (VCVTPD2PSrr VR128:$src)>;
2313 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2314 (VCVTPD2PSXrm addr:$src)>;
2315 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2316 (VCVTPD2PSYrr VR256:$src)>;
2317 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2318 (VCVTPD2PSYrm addr:$src)>;
2320 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2321 (VCVTPS2PDrr VR128:$src)>;
2322 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2323 (VCVTPS2PDYrr VR128:$src)>;
2324 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2325 (VCVTPS2PDYrm addr:$src)>;
2328 let Predicates = [UseSSE2] in {
2329 // Match fround and fextend for 128 conversions
2330 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2331 (CVTPD2PSrr VR128:$src)>;
2332 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2333 (CVTPD2PSrm addr:$src)>;
2335 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2336 (CVTPS2PDrr VR128:$src)>;
2339 //===----------------------------------------------------------------------===//
2340 // SSE 1 & 2 - Compare Instructions
2341 //===----------------------------------------------------------------------===//
2343 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2344 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2345 Operand CC, SDNode OpNode, ValueType VT,
2346 PatFrag ld_frag, string asm, string asm_alt,
2347 OpndItins itins, ImmLeaf immLeaf> {
2348 def rr : SIi8<0xC2, MRMSrcReg,
2349 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2350 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2351 itins.rr>, Sched<[itins.Sched]>;
2352 def rm : SIi8<0xC2, MRMSrcMem,
2353 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2354 [(set RC:$dst, (OpNode (VT RC:$src1),
2355 (ld_frag addr:$src2), immLeaf:$cc))],
2357 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2359 // Accept explicit immediate argument form instead of comparison code.
2360 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2361 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2362 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2363 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2365 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2366 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2367 IIC_SSE_ALU_F32S_RM>,
2368 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2372 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2373 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2374 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2375 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2376 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2377 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2378 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2379 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2380 XD, VEX_4V, VEX_LIG;
2382 let Constraints = "$src1 = $dst" in {
2383 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2384 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2385 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2387 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2388 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2389 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2390 SSE_ALU_F64S, i8immZExt3>, XD;
2393 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2394 Intrinsic Int, string asm, OpndItins itins,
2396 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2397 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2398 [(set VR128:$dst, (Int VR128:$src1,
2399 VR128:$src, immLeaf:$cc))],
2401 Sched<[itins.Sched]>;
2402 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2403 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2404 [(set VR128:$dst, (Int VR128:$src1,
2405 (load addr:$src), immLeaf:$cc))],
2407 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2410 let isCodeGenOnly = 1 in {
2411 // Aliases to match intrinsics which expect XMM operand(s).
2412 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2413 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2414 SSE_ALU_F32S, i8immZExt5>,
2416 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2417 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2418 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2420 let Constraints = "$src1 = $dst" in {
2421 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2422 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2423 SSE_ALU_F32S, i8immZExt3>, XS;
2424 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2425 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2426 SSE_ALU_F64S, i8immZExt3>,
2432 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2433 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2434 ValueType vt, X86MemOperand x86memop,
2435 PatFrag ld_frag, string OpcodeStr> {
2436 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2437 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2438 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2441 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2442 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2443 [(set EFLAGS, (OpNode (vt RC:$src1),
2444 (ld_frag addr:$src2)))],
2446 Sched<[WriteFAddLd, ReadAfterLd]>;
2449 let Defs = [EFLAGS] in {
2450 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2451 "ucomiss">, PS, VEX, VEX_LIG;
2452 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2453 "ucomisd">, PD, VEX, VEX_LIG;
2454 let Pattern = []<dag> in {
2455 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2456 "comiss">, PS, VEX, VEX_LIG;
2457 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2458 "comisd">, PD, VEX, VEX_LIG;
2461 let isCodeGenOnly = 1 in {
2462 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2463 load, "ucomiss">, PS, VEX;
2464 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2465 load, "ucomisd">, PD, VEX;
2467 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2468 load, "comiss">, PS, VEX;
2469 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2470 load, "comisd">, PD, VEX;
2472 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2474 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2477 let Pattern = []<dag> in {
2478 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2480 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2484 let isCodeGenOnly = 1 in {
2485 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2486 load, "ucomiss">, PS;
2487 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2488 load, "ucomisd">, PD;
2490 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2492 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2495 } // Defs = [EFLAGS]
2497 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2498 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2499 Operand CC, Intrinsic Int, string asm,
2500 string asm_alt, Domain d, ImmLeaf immLeaf,
2501 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2502 let isCommutable = 1 in
2503 def rri : PIi8<0xC2, MRMSrcReg,
2504 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2505 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2508 def rmi : PIi8<0xC2, MRMSrcMem,
2509 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2510 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2512 Sched<[WriteFAddLd, ReadAfterLd]>;
2514 // Accept explicit immediate argument form instead of comparison code.
2515 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2516 def rri_alt : PIi8<0xC2, MRMSrcReg,
2517 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2518 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2520 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2521 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2522 asm_alt, [], itins.rm, d>,
2523 Sched<[WriteFAddLd, ReadAfterLd]>;
2527 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2528 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2529 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2530 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2531 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2532 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2533 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2534 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2535 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2536 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2537 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2538 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2539 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2540 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2541 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2542 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2543 let Constraints = "$src1 = $dst" in {
2544 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2545 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2546 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2547 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2548 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2549 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2550 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2551 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2554 let Predicates = [HasAVX] in {
2555 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2556 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2557 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2558 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2559 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2560 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2561 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2562 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2564 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2565 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2566 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2567 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2568 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2569 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2570 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2571 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2574 let Predicates = [UseSSE1] in {
2575 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2576 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2577 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2578 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2581 let Predicates = [UseSSE2] in {
2582 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2583 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2584 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2585 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2588 //===----------------------------------------------------------------------===//
2589 // SSE 1 & 2 - Shuffle Instructions
2590 //===----------------------------------------------------------------------===//
2592 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2593 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2594 ValueType vt, string asm, PatFrag mem_frag,
2596 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2597 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2598 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2599 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2600 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2601 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2602 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2603 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2604 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2605 Sched<[WriteFShuffle]>;
2608 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2609 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2610 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2611 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2612 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2613 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2614 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2615 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2616 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2617 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2618 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2619 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2621 let Constraints = "$src1 = $dst" in {
2622 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2623 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2624 memopv4f32, SSEPackedSingle>, PS;
2625 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2626 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2627 memopv2f64, SSEPackedDouble>, PD;
2630 let Predicates = [HasAVX] in {
2631 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2632 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2633 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2634 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2635 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2637 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2638 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2639 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2640 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2641 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2644 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2645 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2646 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2647 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2648 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2650 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2651 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2652 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2653 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2654 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2657 let Predicates = [UseSSE1] in {
2658 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2659 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2660 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2661 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2662 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2665 let Predicates = [UseSSE2] in {
2666 // Generic SHUFPD patterns
2667 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2668 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2669 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2670 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2671 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2674 //===----------------------------------------------------------------------===//
2675 // SSE 1 & 2 - Unpack FP Instructions
2676 //===----------------------------------------------------------------------===//
2678 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2679 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2680 PatFrag mem_frag, RegisterClass RC,
2681 X86MemOperand x86memop, string asm,
2683 def rr : PI<opc, MRMSrcReg,
2684 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2686 (vt (OpNode RC:$src1, RC:$src2)))],
2687 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2688 def rm : PI<opc, MRMSrcMem,
2689 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2691 (vt (OpNode RC:$src1,
2692 (mem_frag addr:$src2))))],
2694 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2697 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2698 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2699 SSEPackedSingle>, PS, VEX_4V;
2700 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2701 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2702 SSEPackedDouble>, PD, VEX_4V;
2703 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2704 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2705 SSEPackedSingle>, PS, VEX_4V;
2706 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2707 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2708 SSEPackedDouble>, PD, VEX_4V;
2710 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2711 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2712 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2713 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2714 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2715 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2716 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2717 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2718 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2719 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2720 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2721 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2723 let Constraints = "$src1 = $dst" in {
2724 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2725 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2726 SSEPackedSingle>, PS;
2727 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2728 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2729 SSEPackedDouble>, PD;
2730 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2731 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2732 SSEPackedSingle>, PS;
2733 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2734 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2735 SSEPackedDouble>, PD;
2736 } // Constraints = "$src1 = $dst"
2738 let Predicates = [HasAVX1Only] in {
2739 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2740 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2741 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2742 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2743 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2744 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2745 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2746 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2748 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2749 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2750 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2751 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2752 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2753 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2754 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2755 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2758 //===----------------------------------------------------------------------===//
2759 // SSE 1 & 2 - Extract Floating-Point Sign mask
2760 //===----------------------------------------------------------------------===//
2762 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2763 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2765 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2766 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2767 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2768 Sched<[WriteVecLogic]>;
2771 let Predicates = [HasAVX] in {
2772 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2773 "movmskps", SSEPackedSingle>, PS, VEX;
2774 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2775 "movmskpd", SSEPackedDouble>, PD, VEX;
2776 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2777 "movmskps", SSEPackedSingle>, PS,
2779 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2780 "movmskpd", SSEPackedDouble>, PD,
2783 def : Pat<(i32 (X86fgetsign FR32:$src)),
2784 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2785 def : Pat<(i64 (X86fgetsign FR32:$src)),
2786 (SUBREG_TO_REG (i64 0),
2787 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2788 def : Pat<(i32 (X86fgetsign FR64:$src)),
2789 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2790 def : Pat<(i64 (X86fgetsign FR64:$src)),
2791 (SUBREG_TO_REG (i64 0),
2792 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2795 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2796 SSEPackedSingle>, PS;
2797 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2798 SSEPackedDouble>, PD;
2800 def : Pat<(i32 (X86fgetsign FR32:$src)),
2801 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2802 Requires<[UseSSE1]>;
2803 def : Pat<(i64 (X86fgetsign FR32:$src)),
2804 (SUBREG_TO_REG (i64 0),
2805 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2806 Requires<[UseSSE1]>;
2807 def : Pat<(i32 (X86fgetsign FR64:$src)),
2808 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2809 Requires<[UseSSE2]>;
2810 def : Pat<(i64 (X86fgetsign FR64:$src)),
2811 (SUBREG_TO_REG (i64 0),
2812 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2813 Requires<[UseSSE2]>;
2815 //===---------------------------------------------------------------------===//
2816 // SSE2 - Packed Integer Logical Instructions
2817 //===---------------------------------------------------------------------===//
2819 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2821 /// PDI_binop_rm - Simple SSE2 binary operator.
2822 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2823 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2824 X86MemOperand x86memop, OpndItins itins,
2825 bit IsCommutable, bit Is2Addr> {
2826 let isCommutable = IsCommutable in
2827 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2828 (ins RC:$src1, RC:$src2),
2830 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2831 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2832 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2833 Sched<[itins.Sched]>;
2834 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2835 (ins RC:$src1, x86memop:$src2),
2837 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2838 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2839 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2840 (bitconvert (memop_frag addr:$src2)))))],
2842 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2844 } // ExeDomain = SSEPackedInt
2846 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2847 ValueType OpVT128, ValueType OpVT256,
2848 OpndItins itins, bit IsCommutable = 0, Predicate prd> {
2849 let Predicates = [HasAVX, prd] in
2850 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2851 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2853 let Constraints = "$src1 = $dst" in
2854 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2855 memopv2i64, i128mem, itins, IsCommutable, 1>;
2857 let Predicates = [HasAVX2, prd] in
2858 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2859 OpVT256, VR256, loadv4i64, i256mem, itins,
2860 IsCommutable, 0>, VEX_4V, VEX_L;
2863 // These are ordered here for pattern ordering requirements with the fp versions
2865 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2866 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2867 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2868 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2869 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2870 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2871 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2872 SSE_VEC_BIT_ITINS_P, 0, NoVLX>;
2874 //===----------------------------------------------------------------------===//
2875 // SSE 1 & 2 - Logical Instructions
2876 //===----------------------------------------------------------------------===//
2878 // Multiclass for scalars using the X86 logical operation aliases for FP.
2879 multiclass sse12_fp_packed_scalar_logical_alias<
2880 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2881 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2882 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2885 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2886 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2889 let Constraints = "$src1 = $dst" in {
2890 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2891 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2893 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2894 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2898 let isCodeGenOnly = 1 in {
2899 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2901 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2903 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2906 let isCommutable = 0 in
2907 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2911 // Multiclass for vectors using the X86 logical operation aliases for FP.
2912 multiclass sse12_fp_packed_vector_logical_alias<
2913 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2914 let Predicates = [HasAVX, NoVLX] in {
2915 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2916 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2919 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2920 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2924 let Constraints = "$src1 = $dst" in {
2925 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2926 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2929 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2930 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2935 let isCodeGenOnly = 1 in {
2936 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2938 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2940 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2943 let isCommutable = 0 in
2944 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2948 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2950 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2952 let Predicates = [HasAVX, NoVLX] in {
2953 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2954 !strconcat(OpcodeStr, "ps"), f256mem,
2955 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2956 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2957 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2959 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2960 !strconcat(OpcodeStr, "pd"), f256mem,
2961 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2962 (bc_v4i64 (v4f64 VR256:$src2))))],
2963 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2964 (loadv4i64 addr:$src2)))], 0>,
2967 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2968 // are all promoted to v2i64, and the patterns are covered by the int
2969 // version. This is needed in SSE only, because v2i64 isn't supported on
2970 // SSE1, but only on SSE2.
2971 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2972 !strconcat(OpcodeStr, "ps"), f128mem, [],
2973 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2974 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2976 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2977 !strconcat(OpcodeStr, "pd"), f128mem,
2978 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2979 (bc_v2i64 (v2f64 VR128:$src2))))],
2980 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2981 (loadv2i64 addr:$src2)))], 0>,
2985 let Constraints = "$src1 = $dst" in {
2986 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2987 !strconcat(OpcodeStr, "ps"), f128mem,
2988 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2989 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2990 (memopv2i64 addr:$src2)))]>, PS;
2992 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2993 !strconcat(OpcodeStr, "pd"), f128mem,
2994 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2995 (bc_v2i64 (v2f64 VR128:$src2))))],
2996 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2997 (memopv2i64 addr:$src2)))]>, PD;
3001 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
3002 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
3003 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
3004 let isCommutable = 0 in
3005 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
3007 // AVX1 requires type coercions in order to fold loads directly into logical
3009 let Predicates = [HasAVX1Only] in {
3010 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3011 (VANDPSYrm VR256:$src1, addr:$src2)>;
3012 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3013 (VORPSYrm VR256:$src1, addr:$src2)>;
3014 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3015 (VXORPSYrm VR256:$src1, addr:$src2)>;
3016 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3017 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3020 //===----------------------------------------------------------------------===//
3021 // SSE 1 & 2 - Arithmetic Instructions
3022 //===----------------------------------------------------------------------===//
3024 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3027 /// In addition, we also have a special variant of the scalar form here to
3028 /// represent the associated intrinsic operation. This form is unlike the
3029 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3030 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3032 /// These three forms can each be reg+reg or reg+mem.
3035 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3037 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3038 SDNode OpNode, SizeItins itins> {
3039 let Predicates = [HasAVX, NoVLX] in {
3040 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3041 VR128, v4f32, f128mem, loadv4f32,
3042 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3043 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3044 VR128, v2f64, f128mem, loadv2f64,
3045 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3047 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3048 OpNode, VR256, v8f32, f256mem, loadv8f32,
3049 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3050 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3051 OpNode, VR256, v4f64, f256mem, loadv4f64,
3052 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3055 let Constraints = "$src1 = $dst" in {
3056 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3057 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3059 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3060 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3065 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3067 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3068 OpNode, FR32, f32mem, SSEPackedSingle, itins.s, 0>,
3069 XS, VEX_4V, VEX_LIG;
3070 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3071 OpNode, FR64, f64mem, SSEPackedDouble, itins.d, 0>,
3072 XD, VEX_4V, VEX_LIG;
3074 let Constraints = "$src1 = $dst" in {
3075 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3076 OpNode, FR32, f32mem, SSEPackedSingle,
3078 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3079 OpNode, FR64, f64mem, SSEPackedDouble,
3084 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3086 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3087 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3088 SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3089 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3090 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3091 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3093 let Constraints = "$src1 = $dst" in {
3094 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3095 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3096 SSEPackedSingle, itins.s>, XS;
3097 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3098 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3099 SSEPackedDouble, itins.d>, XD;
3103 // Binary Arithmetic instructions
3104 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3105 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3106 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3107 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3108 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3109 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3110 let isCommutable = 0 in {
3111 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3112 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3113 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3114 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3115 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3116 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3117 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3118 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3119 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3120 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3121 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3122 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3125 let isCodeGenOnly = 1 in {
3126 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3127 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3128 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3129 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3132 // Patterns used to select SSE scalar fp arithmetic instructions from
3135 // (1) a scalar fp operation followed by a blend
3137 // The effect is that the backend no longer emits unnecessary vector
3138 // insert instructions immediately after SSE scalar fp instructions
3139 // like addss or mulss.
3141 // For example, given the following code:
3142 // __m128 foo(__m128 A, __m128 B) {
3147 // Previously we generated:
3148 // addss %xmm0, %xmm1
3149 // movss %xmm1, %xmm0
3152 // addss %xmm1, %xmm0
3154 // (2) a vector packed single/double fp operation followed by a vector insert
3156 // The effect is that the backend converts the packed fp instruction
3157 // followed by a vector insert into a single SSE scalar fp instruction.
3159 // For example, given the following code:
3160 // __m128 foo(__m128 A, __m128 B) {
3161 // __m128 C = A + B;
3162 // return (__m128) {c[0], a[1], a[2], a[3]};
3165 // Previously we generated:
3166 // addps %xmm0, %xmm1
3167 // movss %xmm1, %xmm0
3170 // addss %xmm1, %xmm0
3172 // TODO: Some canonicalization in lowering would simplify the number of
3173 // patterns we have to try to match.
3174 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3175 let Predicates = [UseSSE1] in {
3176 // extracted scalar math op with insert via movss
3177 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3178 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3180 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3181 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3183 // vector math op with insert via movss
3184 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3185 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3186 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3189 // With SSE 4.1, blendi is preferred to movsd, so match that too.
3190 let Predicates = [UseSSE41] in {
3191 // extracted scalar math op with insert via blend
3192 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3193 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3194 FR32:$src))), (i8 1))),
3195 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3196 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3198 // vector math op with insert via blend
3199 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3200 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3201 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3205 // Repeat everything for AVX, except for the movss + scalar combo...
3206 // because that one shouldn't occur with AVX codegen?
3207 let Predicates = [HasAVX] in {
3208 // extracted scalar math op with insert via blend
3209 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3210 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3211 FR32:$src))), (i8 1))),
3212 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3213 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3215 // vector math op with insert via movss
3216 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3217 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3218 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3220 // vector math op with insert via blend
3221 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3222 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3223 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3227 defm : scalar_math_f32_patterns<fadd, "ADD">;
3228 defm : scalar_math_f32_patterns<fsub, "SUB">;
3229 defm : scalar_math_f32_patterns<fmul, "MUL">;
3230 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3232 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3233 let Predicates = [UseSSE2] in {
3234 // extracted scalar math op with insert via movsd
3235 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3236 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3238 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3239 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3241 // vector math op with insert via movsd
3242 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3243 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3244 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3247 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3248 let Predicates = [UseSSE41] in {
3249 // extracted scalar math op with insert via blend
3250 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3251 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3252 FR64:$src))), (i8 1))),
3253 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3254 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3256 // vector math op with insert via blend
3257 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3258 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3259 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3262 // Repeat everything for AVX.
3263 let Predicates = [HasAVX] in {
3264 // extracted scalar math op with insert via movsd
3265 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3266 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3268 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3269 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3271 // extracted scalar math op with insert via blend
3272 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3273 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3274 FR64:$src))), (i8 1))),
3275 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3276 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3278 // vector math op with insert via movsd
3279 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3280 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3281 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3283 // vector math op with insert via blend
3284 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3285 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3286 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3290 defm : scalar_math_f64_patterns<fadd, "ADD">;
3291 defm : scalar_math_f64_patterns<fsub, "SUB">;
3292 defm : scalar_math_f64_patterns<fmul, "MUL">;
3293 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3297 /// In addition, we also have a special variant of the scalar form here to
3298 /// represent the associated intrinsic operation. This form is unlike the
3299 /// plain scalar form, in that it takes an entire vector (instead of a
3300 /// scalar) and leaves the top elements undefined.
3302 /// And, we have a special variant form for a full-vector intrinsic form.
3304 let Sched = WriteFSqrt in {
3305 def SSE_SQRTPS : OpndItins<
3306 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3309 def SSE_SQRTSS : OpndItins<
3310 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3313 def SSE_SQRTPD : OpndItins<
3314 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3317 def SSE_SQRTSD : OpndItins<
3318 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3322 let Sched = WriteFRsqrt in {
3323 def SSE_RSQRTPS : OpndItins<
3324 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3327 def SSE_RSQRTSS : OpndItins<
3328 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3332 let Sched = WriteFRcp in {
3333 def SSE_RCPP : OpndItins<
3334 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3337 def SSE_RCPS : OpndItins<
3338 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3342 /// sse_fp_unop_s - SSE1 unops in scalar form
3343 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3344 /// the HW instructions are 2 operand / destructive.
3345 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3346 ValueType vt, ValueType ScalarVT,
3347 X86MemOperand x86memop, Operand vec_memop,
3348 ComplexPattern mem_cpat, Intrinsic Intr,
3349 SDNode OpNode, Domain d, OpndItins itins,
3350 Predicate target, string Suffix> {
3351 let hasSideEffects = 0 in {
3352 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3353 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3354 [(set RC:$dst, (OpNode RC:$src1))], itins.rr, d>, Sched<[itins.Sched]>,
3357 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3358 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3359 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm, d>,
3360 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3361 Requires<[target, OptForSize]>;
3363 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3364 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3365 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3366 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3368 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3369 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3370 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3374 let Predicates = [target] in {
3375 def : Pat<(vt (OpNode mem_cpat:$src)),
3376 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3377 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3378 // These are unary operations, but they are modeled as having 2 source operands
3379 // because the high elements of the destination are unchanged in SSE.
3380 def : Pat<(Intr VR128:$src),
3381 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3382 def : Pat<(Intr (load addr:$src)),
3383 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3384 addr:$src), VR128))>;
3385 def : Pat<(Intr mem_cpat:$src),
3386 (!cast<Instruction>(NAME#Suffix##m_Int)
3387 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3391 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3392 ValueType vt, ValueType ScalarVT,
3393 X86MemOperand x86memop, Operand vec_memop,
3394 ComplexPattern mem_cpat,
3395 Intrinsic Intr, SDNode OpNode, Domain d,
3396 OpndItins itins, string Suffix> {
3397 let hasSideEffects = 0 in {
3398 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3399 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3400 [], itins.rr, d>, Sched<[itins.Sched]>;
3402 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3403 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3404 [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3405 let isCodeGenOnly = 1 in {
3406 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3407 (ins VR128:$src1, VR128:$src2),
3408 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3409 []>, Sched<[itins.Sched.Folded]>;
3411 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3412 (ins VR128:$src1, vec_memop:$src2),
3413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3414 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3418 let Predicates = [UseAVX] in {
3419 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3420 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3422 def : Pat<(vt (OpNode mem_cpat:$src)),
3423 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3427 let Predicates = [HasAVX] in {
3428 def : Pat<(Intr VR128:$src),
3429 (!cast<Instruction>("V"#NAME#Suffix##r_Int) (vt (IMPLICIT_DEF)),
3432 def : Pat<(Intr mem_cpat:$src),
3433 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3434 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3436 let Predicates = [UseAVX, OptForSize] in
3437 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3438 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3442 /// sse1_fp_unop_p - SSE1 unops in packed form.
3443 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3445 let Predicates = [HasAVX] in {
3446 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3447 !strconcat("v", OpcodeStr,
3448 "ps\t{$src, $dst|$dst, $src}"),
3449 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3450 itins.rr>, VEX, Sched<[itins.Sched]>;
3451 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3452 !strconcat("v", OpcodeStr,
3453 "ps\t{$src, $dst|$dst, $src}"),
3454 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3455 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3456 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3457 !strconcat("v", OpcodeStr,
3458 "ps\t{$src, $dst|$dst, $src}"),
3459 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3460 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3461 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3462 !strconcat("v", OpcodeStr,
3463 "ps\t{$src, $dst|$dst, $src}"),
3464 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3465 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3468 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3469 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3470 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3471 Sched<[itins.Sched]>;
3472 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3473 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3474 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3475 Sched<[itins.Sched.Folded]>;
3478 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3479 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3480 SDNode OpNode, OpndItins itins> {
3481 let Predicates = [HasAVX] in {
3482 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3483 !strconcat("v", OpcodeStr,
3484 "pd\t{$src, $dst|$dst, $src}"),
3485 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3486 itins.rr>, VEX, Sched<[itins.Sched]>;
3487 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3488 !strconcat("v", OpcodeStr,
3489 "pd\t{$src, $dst|$dst, $src}"),
3490 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3491 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3492 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3493 !strconcat("v", OpcodeStr,
3494 "pd\t{$src, $dst|$dst, $src}"),
3495 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3496 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3497 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3498 !strconcat("v", OpcodeStr,
3499 "pd\t{$src, $dst|$dst, $src}"),
3500 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3501 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3504 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3505 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3506 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3507 Sched<[itins.Sched]>;
3508 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3509 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3510 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3511 Sched<[itins.Sched.Folded]>;
3514 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3516 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3517 ssmem, sse_load_f32,
3518 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3519 SSEPackedSingle, itins, UseSSE1, "SS">, XS;
3520 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3521 f32mem, ssmem, sse_load_f32,
3522 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3523 SSEPackedSingle, itins, "SS">, XS, VEX_4V, VEX_LIG;
3526 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3528 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3529 sdmem, sse_load_f64,
3530 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3531 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3532 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3533 f64mem, sdmem, sse_load_f64,
3534 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3535 OpNode, SSEPackedDouble, itins, "SD">,
3536 XD, VEX_4V, VEX_LIG;
3540 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3541 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3542 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3543 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3545 // Reciprocal approximations. Note that these typically require refinement
3546 // in order to obtain suitable precision.
3547 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3548 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>;
3549 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3550 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>;
3552 // There is no f64 version of the reciprocal approximation instructions.
3554 // TODO: We should add *scalar* op patterns for these just like we have for
3555 // the binops above. If the binop and unop patterns could all be unified
3556 // that would be even better.
3558 multiclass scalar_unary_math_patterns<Intrinsic Intr, string OpcPrefix,
3559 SDNode Move, ValueType VT,
3560 Predicate BasePredicate> {
3561 let Predicates = [BasePredicate] in {
3562 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3563 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3566 // With SSE 4.1, blendi is preferred to movs*, so match that too.
3567 let Predicates = [UseSSE41] in {
3568 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3569 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3572 // Repeat for AVX versions of the instructions.
3573 let Predicates = [HasAVX] in {
3574 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3575 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3577 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3578 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3582 defm : scalar_unary_math_patterns<int_x86_sse_rcp_ss, "RCPSS", X86Movss,
3584 defm : scalar_unary_math_patterns<int_x86_sse_rsqrt_ss, "RSQRTSS", X86Movss,
3586 defm : scalar_unary_math_patterns<int_x86_sse_sqrt_ss, "SQRTSS", X86Movss,
3588 defm : scalar_unary_math_patterns<int_x86_sse2_sqrt_sd, "SQRTSD", X86Movsd,
3592 //===----------------------------------------------------------------------===//
3593 // SSE 1 & 2 - Non-temporal stores
3594 //===----------------------------------------------------------------------===//
3596 let AddedComplexity = 400 in { // Prefer non-temporal versions
3597 let SchedRW = [WriteStore] in {
3598 let Predicates = [HasAVX, NoVLX] in {
3599 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3600 (ins f128mem:$dst, VR128:$src),
3601 "movntps\t{$src, $dst|$dst, $src}",
3602 [(alignednontemporalstore (v4f32 VR128:$src),
3604 IIC_SSE_MOVNT>, VEX;
3605 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3606 (ins f128mem:$dst, VR128:$src),
3607 "movntpd\t{$src, $dst|$dst, $src}",
3608 [(alignednontemporalstore (v2f64 VR128:$src),
3610 IIC_SSE_MOVNT>, VEX;
3612 let ExeDomain = SSEPackedInt in
3613 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3614 (ins f128mem:$dst, VR128:$src),
3615 "movntdq\t{$src, $dst|$dst, $src}",
3616 [(alignednontemporalstore (v2i64 VR128:$src),
3618 IIC_SSE_MOVNT>, VEX;
3620 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3621 (ins f256mem:$dst, VR256:$src),
3622 "movntps\t{$src, $dst|$dst, $src}",
3623 [(alignednontemporalstore (v8f32 VR256:$src),
3625 IIC_SSE_MOVNT>, VEX, VEX_L;
3626 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3627 (ins f256mem:$dst, VR256:$src),
3628 "movntpd\t{$src, $dst|$dst, $src}",
3629 [(alignednontemporalstore (v4f64 VR256:$src),
3631 IIC_SSE_MOVNT>, VEX, VEX_L;
3632 let ExeDomain = SSEPackedInt in
3633 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3634 (ins f256mem:$dst, VR256:$src),
3635 "movntdq\t{$src, $dst|$dst, $src}",
3636 [(alignednontemporalstore (v4i64 VR256:$src),
3638 IIC_SSE_MOVNT>, VEX, VEX_L;
3641 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3642 "movntps\t{$src, $dst|$dst, $src}",
3643 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3645 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3646 "movntpd\t{$src, $dst|$dst, $src}",
3647 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3650 let ExeDomain = SSEPackedInt in
3651 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3652 "movntdq\t{$src, $dst|$dst, $src}",
3653 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3656 // There is no AVX form for instructions below this point
3657 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3658 "movnti{l}\t{$src, $dst|$dst, $src}",
3659 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3661 PS, Requires<[HasSSE2]>;
3662 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3663 "movnti{q}\t{$src, $dst|$dst, $src}",
3664 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3666 PS, Requires<[HasSSE2]>;
3667 } // SchedRW = [WriteStore]
3669 let Predicates = [HasAVX2, NoVLX] in {
3670 def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst),
3671 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3672 def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst),
3673 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3674 def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst),
3675 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3678 let Predicates = [HasAVX, NoVLX] in {
3679 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3680 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3681 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3682 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3683 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3684 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3687 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3688 (MOVNTDQmr addr:$dst, VR128:$src)>;
3689 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3690 (MOVNTDQmr addr:$dst, VR128:$src)>;
3691 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3692 (MOVNTDQmr addr:$dst, VR128:$src)>;
3694 } // AddedComplexity
3696 //===----------------------------------------------------------------------===//
3697 // SSE 1 & 2 - Prefetch and memory fence
3698 //===----------------------------------------------------------------------===//
3700 // Prefetch intrinsic.
3701 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3702 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3703 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3704 IIC_SSE_PREFETCH>, TB;
3705 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3706 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3707 IIC_SSE_PREFETCH>, TB;
3708 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3709 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3710 IIC_SSE_PREFETCH>, TB;
3711 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3712 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3713 IIC_SSE_PREFETCH>, TB;
3716 // FIXME: How should flush instruction be modeled?
3717 let SchedRW = [WriteLoad] in {
3719 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3720 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3721 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3724 let SchedRW = [WriteNop] in {
3725 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3726 // was introduced with SSE2, it's backward compatible.
3727 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3728 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3729 OBXS, Requires<[HasSSE2]>;
3732 let SchedRW = [WriteFence] in {
3733 // Load, store, and memory fence
3734 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3735 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3736 PS, Requires<[HasSSE1]>;
3737 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3738 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3739 TB, Requires<[HasSSE2]>;
3740 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3741 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3742 TB, Requires<[HasSSE2]>;
3745 def : Pat<(X86SFence), (SFENCE)>;
3746 def : Pat<(X86LFence), (LFENCE)>;
3747 def : Pat<(X86MFence), (MFENCE)>;
3749 //===----------------------------------------------------------------------===//
3750 // SSE 1 & 2 - Load/Store XCSR register
3751 //===----------------------------------------------------------------------===//
3753 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3754 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3755 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3756 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3757 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3758 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3760 let Predicates = [UseSSE1] in {
3761 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3762 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3763 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3764 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3765 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3766 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3769 //===---------------------------------------------------------------------===//
3770 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3771 //===---------------------------------------------------------------------===//
3773 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3775 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3776 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3777 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3779 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3780 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3782 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3783 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3785 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3786 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3791 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3792 SchedRW = [WriteMove] in {
3793 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3794 "movdqa\t{$src, $dst|$dst, $src}", [],
3797 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3798 "movdqa\t{$src, $dst|$dst, $src}", [],
3799 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3800 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3801 "movdqu\t{$src, $dst|$dst, $src}", [],
3804 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3805 "movdqu\t{$src, $dst|$dst, $src}", [],
3806 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3809 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3810 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3811 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3812 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3814 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3815 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3817 let Predicates = [HasAVX] in {
3818 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3819 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3821 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3822 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3827 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3828 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3829 (ins i128mem:$dst, VR128:$src),
3830 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3832 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3833 (ins i256mem:$dst, VR256:$src),
3834 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3836 let Predicates = [HasAVX] in {
3837 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3838 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3840 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3841 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3846 let SchedRW = [WriteMove] in {
3847 let hasSideEffects = 0 in
3848 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3849 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3851 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3852 "movdqu\t{$src, $dst|$dst, $src}",
3853 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3856 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3857 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3858 "movdqa\t{$src, $dst|$dst, $src}", [],
3861 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3862 "movdqu\t{$src, $dst|$dst, $src}",
3863 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3867 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3868 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3869 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3870 "movdqa\t{$src, $dst|$dst, $src}",
3871 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3873 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3874 "movdqu\t{$src, $dst|$dst, $src}",
3875 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3877 XS, Requires<[UseSSE2]>;
3880 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3881 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3882 "movdqa\t{$src, $dst|$dst, $src}",
3883 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3885 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3886 "movdqu\t{$src, $dst|$dst, $src}",
3887 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3889 XS, Requires<[UseSSE2]>;
3892 } // ExeDomain = SSEPackedInt
3894 let Predicates = [HasAVX] in {
3895 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3896 (VMOVDQUmr addr:$dst, VR128:$src)>;
3897 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3898 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3900 let Predicates = [UseSSE2] in
3901 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3902 (MOVDQUmr addr:$dst, VR128:$src)>;
3904 //===---------------------------------------------------------------------===//
3905 // SSE2 - Packed Integer Arithmetic Instructions
3906 //===---------------------------------------------------------------------===//
3908 let Sched = WriteVecIMul in
3909 def SSE_PMADD : OpndItins<
3910 IIC_SSE_PMADD, IIC_SSE_PMADD
3913 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3915 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3916 RegisterClass RC, PatFrag memop_frag,
3917 X86MemOperand x86memop,
3919 bit IsCommutable = 0,
3921 let isCommutable = IsCommutable in
3922 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3923 (ins RC:$src1, RC:$src2),
3925 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3926 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3927 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3928 Sched<[itins.Sched]>;
3929 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3930 (ins RC:$src1, x86memop:$src2),
3932 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3933 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3934 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3935 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3938 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3939 Intrinsic IntId256, OpndItins itins,
3940 bit IsCommutable = 0> {
3941 let Predicates = [HasAVX] in
3942 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3943 VR128, loadv2i64, i128mem, itins,
3944 IsCommutable, 0>, VEX_4V;
3946 let Constraints = "$src1 = $dst" in
3947 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3948 i128mem, itins, IsCommutable, 1>;
3950 let Predicates = [HasAVX2] in
3951 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3952 VR256, loadv4i64, i256mem, itins,
3953 IsCommutable, 0>, VEX_4V, VEX_L;
3956 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3957 string OpcodeStr, SDNode OpNode,
3958 SDNode OpNode2, RegisterClass RC,
3959 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3960 PatFrag ld_frag, ShiftOpndItins itins,
3962 // src2 is always 128-bit
3963 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3964 (ins RC:$src1, VR128:$src2),
3966 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3967 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3968 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3969 itins.rr>, Sched<[WriteVecShift]>;
3970 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3971 (ins RC:$src1, i128mem:$src2),
3973 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3974 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3975 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3976 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3977 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3978 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3979 (ins RC:$src1, u8imm:$src2),
3981 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3982 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3983 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3984 Sched<[WriteVecShift]>;
3987 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3988 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3989 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3990 PatFrag memop_frag, X86MemOperand x86memop,
3992 bit IsCommutable = 0, bit Is2Addr = 1> {
3993 let isCommutable = IsCommutable in
3994 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3995 (ins RC:$src1, RC:$src2),
3997 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3998 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3999 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4000 Sched<[itins.Sched]>;
4001 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4002 (ins RC:$src1, x86memop:$src2),
4004 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4005 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4006 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4007 (bitconvert (memop_frag addr:$src2)))))]>,
4008 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4010 } // ExeDomain = SSEPackedInt
4012 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4013 SSE_INTALU_ITINS_P, 1, NoBWI>;
4014 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4015 SSE_INTALU_ITINS_P, 1, NoBWI>;
4016 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4017 SSE_INTALU_ITINS_P, 1, NoVLX>;
4018 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4019 SSE_INTALUQ_ITINS_P, 1, NoVLX>;
4020 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4021 SSE_INTMUL_ITINS_P, 1, NoBWI>;
4022 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4023 SSE_INTMUL_ITINS_P, 1, NoBWI>;
4024 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4025 SSE_INTMUL_ITINS_P, 1, NoBWI>;
4026 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4027 SSE_INTALU_ITINS_P, 0, NoBWI>;
4028 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4029 SSE_INTALU_ITINS_P, 0, NoBWI>;
4030 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4031 SSE_INTALU_ITINS_P, 0, NoVLX>;
4032 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4033 SSE_INTALUQ_ITINS_P, 0, NoVLX>;
4034 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4035 SSE_INTALU_ITINS_P, 0, NoBWI>;
4036 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4037 SSE_INTALU_ITINS_P, 0, NoBWI>;
4038 defm PMINUB : PDI_binop_all<0xDA, "pminub", umin, v16i8, v32i8,
4039 SSE_INTALU_ITINS_P, 1, NoBWI>;
4040 defm PMINSW : PDI_binop_all<0xEA, "pminsw", smin, v8i16, v16i16,
4041 SSE_INTALU_ITINS_P, 1, NoBWI>;
4042 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", umax, v16i8, v32i8,
4043 SSE_INTALU_ITINS_P, 1, NoBWI>;
4044 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", smax, v8i16, v16i16,
4045 SSE_INTALU_ITINS_P, 1, NoBWI>;
4048 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4049 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4050 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4051 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4052 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4053 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4054 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4055 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4056 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4057 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4058 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4059 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4060 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4061 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4062 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4063 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4064 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4065 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4066 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4067 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4069 let Predicates = [HasAVX2] in
4070 def : Pat<(v32i8 (X86psadbw (v32i8 VR256:$src1),
4071 (v32i8 VR256:$src2))),
4072 (VPSADBWYrr VR256:$src2, VR256:$src1)>;
4074 let Predicates = [HasAVX] in
4075 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4076 (v16i8 VR128:$src2))),
4077 (VPSADBWrr VR128:$src2, VR128:$src1)>;
4079 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4080 (v16i8 VR128:$src2))),
4081 (PSADBWrr VR128:$src2, VR128:$src1)>;
4083 let Predicates = [HasAVX] in
4084 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4085 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4087 let Predicates = [HasAVX2] in
4088 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4089 VR256, loadv4i64, i256mem,
4090 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4091 let Constraints = "$src1 = $dst" in
4092 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4093 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4095 //===---------------------------------------------------------------------===//
4096 // SSE2 - Packed Integer Logical Instructions
4097 //===---------------------------------------------------------------------===//
4099 let Predicates = [HasAVX, NoVLX] in {
4100 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4101 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4102 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4103 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4104 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4105 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4106 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4107 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4108 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4110 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4111 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4112 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4113 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4114 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4115 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4116 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4117 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4118 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4120 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4121 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4122 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4123 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4124 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4125 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4127 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4128 // 128-bit logical shifts.
4129 def VPSLLDQri : PDIi8<0x73, MRM7r,
4130 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4131 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4133 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4135 def VPSRLDQri : PDIi8<0x73, MRM3r,
4136 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4137 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4139 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4141 // PSRADQri doesn't exist in SSE[1-3].
4143 } // Predicates = [HasAVX]
4145 let Predicates = [HasAVX2, NoVLX] in {
4146 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4147 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4148 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4149 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4150 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4151 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4152 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4153 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4154 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4156 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4157 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4158 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4159 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4160 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4161 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4162 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4163 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4164 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4166 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4167 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4168 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4169 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4170 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4171 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4173 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4174 // 256-bit logical shifts.
4175 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4176 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4177 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4179 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4181 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4182 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4183 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4185 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4187 // PSRADQYri doesn't exist in SSE[1-3].
4189 } // Predicates = [HasAVX2]
4191 let Constraints = "$src1 = $dst" in {
4192 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4193 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4194 SSE_INTSHIFT_ITINS_P>;
4195 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4196 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4197 SSE_INTSHIFT_ITINS_P>;
4198 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4199 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4200 SSE_INTSHIFT_ITINS_P>;
4202 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4203 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4204 SSE_INTSHIFT_ITINS_P>;
4205 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4206 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4207 SSE_INTSHIFT_ITINS_P>;
4208 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4209 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4210 SSE_INTSHIFT_ITINS_P>;
4212 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4213 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4214 SSE_INTSHIFT_ITINS_P>;
4215 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4216 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4217 SSE_INTSHIFT_ITINS_P>;
4219 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4220 // 128-bit logical shifts.
4221 def PSLLDQri : PDIi8<0x73, MRM7r,
4222 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4223 "pslldq\t{$src2, $dst|$dst, $src2}",
4225 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4226 IIC_SSE_INTSHDQ_P_RI>;
4227 def PSRLDQri : PDIi8<0x73, MRM3r,
4228 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4229 "psrldq\t{$src2, $dst|$dst, $src2}",
4231 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4232 IIC_SSE_INTSHDQ_P_RI>;
4233 // PSRADQri doesn't exist in SSE[1-3].
4235 } // Constraints = "$src1 = $dst"
4237 //===---------------------------------------------------------------------===//
4238 // SSE2 - Packed Integer Comparison Instructions
4239 //===---------------------------------------------------------------------===//
4241 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4242 SSE_INTALU_ITINS_P, 1, NoBWI>;
4243 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4244 SSE_INTALU_ITINS_P, 1, NoBWI>;
4245 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4246 SSE_INTALU_ITINS_P, 1, NoVLX>;
4247 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4248 SSE_INTALU_ITINS_P, 0, NoBWI>;
4249 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4250 SSE_INTALU_ITINS_P, 0, NoBWI>;
4251 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4252 SSE_INTALU_ITINS_P, 0, NoVLX>;
4254 //===---------------------------------------------------------------------===//
4255 // SSE2 - Packed Integer Shuffle Instructions
4256 //===---------------------------------------------------------------------===//
4258 let ExeDomain = SSEPackedInt in {
4259 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4261 let Predicates = [HasAVX] in {
4262 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4263 (ins VR128:$src1, u8imm:$src2),
4264 !strconcat("v", OpcodeStr,
4265 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4267 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4268 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4269 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4270 (ins i128mem:$src1, u8imm:$src2),
4271 !strconcat("v", OpcodeStr,
4272 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4274 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4275 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4276 Sched<[WriteShuffleLd]>;
4279 let Predicates = [HasAVX2] in {
4280 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4281 (ins VR256:$src1, u8imm:$src2),
4282 !strconcat("v", OpcodeStr,
4283 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4285 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4286 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4287 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4288 (ins i256mem:$src1, u8imm:$src2),
4289 !strconcat("v", OpcodeStr,
4290 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4292 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4293 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4294 Sched<[WriteShuffleLd]>;
4297 let Predicates = [UseSSE2] in {
4298 def ri : Ii8<0x70, MRMSrcReg,
4299 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4300 !strconcat(OpcodeStr,
4301 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4303 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4304 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4305 def mi : Ii8<0x70, MRMSrcMem,
4306 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4307 !strconcat(OpcodeStr,
4308 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4310 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4311 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4312 Sched<[WriteShuffleLd, ReadAfterLd]>;
4315 } // ExeDomain = SSEPackedInt
4317 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4318 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4319 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4321 let Predicates = [HasAVX] in {
4322 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4323 (VPSHUFDmi addr:$src1, imm:$imm)>;
4324 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4325 (VPSHUFDri VR128:$src1, imm:$imm)>;
4328 let Predicates = [UseSSE2] in {
4329 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4330 (PSHUFDmi addr:$src1, imm:$imm)>;
4331 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4332 (PSHUFDri VR128:$src1, imm:$imm)>;
4335 //===---------------------------------------------------------------------===//
4336 // Packed Integer Pack Instructions (SSE & AVX)
4337 //===---------------------------------------------------------------------===//
4339 let ExeDomain = SSEPackedInt in {
4340 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4341 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4342 PatFrag ld_frag, bit Is2Addr = 1> {
4343 def rr : PDI<opc, MRMSrcReg,
4344 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4347 !strconcat(OpcodeStr,
4348 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4350 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4351 Sched<[WriteShuffle]>;
4352 def rm : PDI<opc, MRMSrcMem,
4353 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4355 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4356 !strconcat(OpcodeStr,
4357 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4359 (OutVT (OpNode VR128:$src1,
4360 (bc_frag (ld_frag addr:$src2)))))]>,
4361 Sched<[WriteShuffleLd, ReadAfterLd]>;
4364 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4365 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4366 def Yrr : PDI<opc, MRMSrcReg,
4367 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4368 !strconcat(OpcodeStr,
4369 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4371 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4372 Sched<[WriteShuffle]>;
4373 def Yrm : PDI<opc, MRMSrcMem,
4374 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4375 !strconcat(OpcodeStr,
4376 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4378 (OutVT (OpNode VR256:$src1,
4379 (bc_frag (loadv4i64 addr:$src2)))))]>,
4380 Sched<[WriteShuffleLd, ReadAfterLd]>;
4383 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4384 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4385 PatFrag ld_frag, bit Is2Addr = 1> {
4386 def rr : SS48I<opc, MRMSrcReg,
4387 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4389 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4390 !strconcat(OpcodeStr,
4391 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4393 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4394 Sched<[WriteShuffle]>;
4395 def rm : SS48I<opc, MRMSrcMem,
4396 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4398 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4399 !strconcat(OpcodeStr,
4400 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4402 (OutVT (OpNode VR128:$src1,
4403 (bc_frag (ld_frag addr:$src2)))))]>,
4404 Sched<[WriteShuffleLd, ReadAfterLd]>;
4407 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4408 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4409 def Yrr : SS48I<opc, MRMSrcReg,
4410 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4411 !strconcat(OpcodeStr,
4412 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4414 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4415 Sched<[WriteShuffle]>;
4416 def Yrm : SS48I<opc, MRMSrcMem,
4417 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4418 !strconcat(OpcodeStr,
4419 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4421 (OutVT (OpNode VR256:$src1,
4422 (bc_frag (loadv4i64 addr:$src2)))))]>,
4423 Sched<[WriteShuffleLd, ReadAfterLd]>;
4426 let Predicates = [HasAVX] in {
4427 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4428 bc_v8i16, loadv2i64, 0>, VEX_4V;
4429 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4430 bc_v4i32, loadv2i64, 0>, VEX_4V;
4432 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4433 bc_v8i16, loadv2i64, 0>, VEX_4V;
4434 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4435 bc_v4i32, loadv2i64, 0>, VEX_4V;
4438 let Predicates = [HasAVX2] in {
4439 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4440 bc_v16i16>, VEX_4V, VEX_L;
4441 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4442 bc_v8i32>, VEX_4V, VEX_L;
4444 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4445 bc_v16i16>, VEX_4V, VEX_L;
4446 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4447 bc_v8i32>, VEX_4V, VEX_L;
4450 let Constraints = "$src1 = $dst" in {
4451 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4452 bc_v8i16, memopv2i64>;
4453 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4454 bc_v4i32, memopv2i64>;
4456 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4457 bc_v8i16, memopv2i64>;
4459 let Predicates = [HasSSE41] in
4460 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4461 bc_v4i32, memopv2i64>;
4463 } // ExeDomain = SSEPackedInt
4465 //===---------------------------------------------------------------------===//
4466 // SSE2 - Packed Integer Unpack Instructions
4467 //===---------------------------------------------------------------------===//
4469 let ExeDomain = SSEPackedInt in {
4470 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4471 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4473 def rr : PDI<opc, MRMSrcReg,
4474 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4476 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4477 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4478 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4479 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4480 def rm : PDI<opc, MRMSrcMem,
4481 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4483 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4484 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4485 [(set VR128:$dst, (OpNode VR128:$src1,
4486 (bc_frag (ld_frag addr:$src2))))],
4488 Sched<[WriteShuffleLd, ReadAfterLd]>;
4491 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4492 SDNode OpNode, PatFrag bc_frag> {
4493 def Yrr : PDI<opc, MRMSrcReg,
4494 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4495 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4496 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4497 Sched<[WriteShuffle]>;
4498 def Yrm : PDI<opc, MRMSrcMem,
4499 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4500 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4501 [(set VR256:$dst, (OpNode VR256:$src1,
4502 (bc_frag (loadv4i64 addr:$src2))))]>,
4503 Sched<[WriteShuffleLd, ReadAfterLd]>;
4506 let Predicates = [HasAVX] in {
4507 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4508 bc_v16i8, loadv2i64, 0>, VEX_4V;
4509 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4510 bc_v8i16, loadv2i64, 0>, VEX_4V;
4511 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4512 bc_v4i32, loadv2i64, 0>, VEX_4V;
4513 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4514 bc_v2i64, loadv2i64, 0>, VEX_4V;
4516 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4517 bc_v16i8, loadv2i64, 0>, VEX_4V;
4518 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4519 bc_v8i16, loadv2i64, 0>, VEX_4V;
4520 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4521 bc_v4i32, loadv2i64, 0>, VEX_4V;
4522 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4523 bc_v2i64, loadv2i64, 0>, VEX_4V;
4526 let Predicates = [HasAVX2] in {
4527 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4528 bc_v32i8>, VEX_4V, VEX_L;
4529 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4530 bc_v16i16>, VEX_4V, VEX_L;
4531 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4532 bc_v8i32>, VEX_4V, VEX_L;
4533 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4534 bc_v4i64>, VEX_4V, VEX_L;
4536 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4537 bc_v32i8>, VEX_4V, VEX_L;
4538 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4539 bc_v16i16>, VEX_4V, VEX_L;
4540 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4541 bc_v8i32>, VEX_4V, VEX_L;
4542 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4543 bc_v4i64>, VEX_4V, VEX_L;
4546 let Constraints = "$src1 = $dst" in {
4547 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4548 bc_v16i8, memopv2i64>;
4549 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4550 bc_v8i16, memopv2i64>;
4551 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4552 bc_v4i32, memopv2i64>;
4553 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4554 bc_v2i64, memopv2i64>;
4556 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4557 bc_v16i8, memopv2i64>;
4558 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4559 bc_v8i16, memopv2i64>;
4560 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4561 bc_v4i32, memopv2i64>;
4562 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4563 bc_v2i64, memopv2i64>;
4565 } // ExeDomain = SSEPackedInt
4567 //===---------------------------------------------------------------------===//
4568 // SSE2 - Packed Integer Extract and Insert
4569 //===---------------------------------------------------------------------===//
4571 let ExeDomain = SSEPackedInt in {
4572 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4573 def rri : Ii8<0xC4, MRMSrcReg,
4574 (outs VR128:$dst), (ins VR128:$src1,
4575 GR32orGR64:$src2, u8imm:$src3),
4577 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4578 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4580 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4581 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4582 def rmi : Ii8<0xC4, MRMSrcMem,
4583 (outs VR128:$dst), (ins VR128:$src1,
4584 i16mem:$src2, u8imm:$src3),
4586 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4587 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4589 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4590 imm:$src3))], IIC_SSE_PINSRW>,
4591 Sched<[WriteShuffleLd, ReadAfterLd]>;
4595 let Predicates = [HasAVX] in
4596 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4597 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4598 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4599 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4600 imm:$src2))]>, PD, VEX,
4601 Sched<[WriteShuffle]>;
4602 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4603 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4604 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4605 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4606 imm:$src2))], IIC_SSE_PEXTRW>,
4607 Sched<[WriteShuffleLd, ReadAfterLd]>;
4610 let Predicates = [HasAVX] in
4611 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4613 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4614 defm PINSRW : sse2_pinsrw, PD;
4616 } // ExeDomain = SSEPackedInt
4618 //===---------------------------------------------------------------------===//
4619 // SSE2 - Packed Mask Creation
4620 //===---------------------------------------------------------------------===//
4622 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4624 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4626 "pmovmskb\t{$src, $dst|$dst, $src}",
4627 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4628 IIC_SSE_MOVMSK>, VEX;
4630 let Predicates = [HasAVX2] in {
4631 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4633 "pmovmskb\t{$src, $dst|$dst, $src}",
4634 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4638 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4639 "pmovmskb\t{$src, $dst|$dst, $src}",
4640 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4643 } // ExeDomain = SSEPackedInt
4645 //===---------------------------------------------------------------------===//
4646 // SSE2 - Conditional Store
4647 //===---------------------------------------------------------------------===//
4649 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4651 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4652 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4653 (ins VR128:$src, VR128:$mask),
4654 "maskmovdqu\t{$mask, $src|$src, $mask}",
4655 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4656 IIC_SSE_MASKMOV>, VEX;
4657 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4658 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4659 (ins VR128:$src, VR128:$mask),
4660 "maskmovdqu\t{$mask, $src|$src, $mask}",
4661 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4662 IIC_SSE_MASKMOV>, VEX;
4664 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4665 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4666 "maskmovdqu\t{$mask, $src|$src, $mask}",
4667 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4669 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4670 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4671 "maskmovdqu\t{$mask, $src|$src, $mask}",
4672 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4675 } // ExeDomain = SSEPackedInt
4677 //===---------------------------------------------------------------------===//
4678 // SSE2 - Move Doubleword
4679 //===---------------------------------------------------------------------===//
4681 //===---------------------------------------------------------------------===//
4682 // Move Int Doubleword to Packed Double Int
4684 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4685 "movd\t{$src, $dst|$dst, $src}",
4687 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4688 VEX, Sched<[WriteMove]>;
4689 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4690 "movd\t{$src, $dst|$dst, $src}",
4692 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4694 VEX, Sched<[WriteLoad]>;
4695 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4696 "movq\t{$src, $dst|$dst, $src}",
4698 (v2i64 (scalar_to_vector GR64:$src)))],
4699 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4700 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4701 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4702 "movq\t{$src, $dst|$dst, $src}",
4703 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4704 let isCodeGenOnly = 1 in
4705 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4706 "movq\t{$src, $dst|$dst, $src}",
4707 [(set FR64:$dst, (bitconvert GR64:$src))],
4708 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4710 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4711 "movd\t{$src, $dst|$dst, $src}",
4713 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4715 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4716 "movd\t{$src, $dst|$dst, $src}",
4718 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4719 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4720 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4721 "mov{d|q}\t{$src, $dst|$dst, $src}",
4723 (v2i64 (scalar_to_vector GR64:$src)))],
4724 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4725 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4726 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4727 "mov{d|q}\t{$src, $dst|$dst, $src}",
4728 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4729 let isCodeGenOnly = 1 in
4730 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4731 "mov{d|q}\t{$src, $dst|$dst, $src}",
4732 [(set FR64:$dst, (bitconvert GR64:$src))],
4733 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4735 //===---------------------------------------------------------------------===//
4736 // Move Int Doubleword to Single Scalar
4738 let isCodeGenOnly = 1 in {
4739 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4740 "movd\t{$src, $dst|$dst, $src}",
4741 [(set FR32:$dst, (bitconvert GR32:$src))],
4742 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4744 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4745 "movd\t{$src, $dst|$dst, $src}",
4746 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4748 VEX, Sched<[WriteLoad]>;
4749 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4750 "movd\t{$src, $dst|$dst, $src}",
4751 [(set FR32:$dst, (bitconvert GR32:$src))],
4752 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4754 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4755 "movd\t{$src, $dst|$dst, $src}",
4756 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4757 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4760 //===---------------------------------------------------------------------===//
4761 // Move Packed Doubleword Int to Packed Double Int
4763 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4764 "movd\t{$src, $dst|$dst, $src}",
4765 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4766 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4768 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4769 (ins i32mem:$dst, VR128:$src),
4770 "movd\t{$src, $dst|$dst, $src}",
4771 [(store (i32 (vector_extract (v4i32 VR128:$src),
4772 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4773 VEX, Sched<[WriteStore]>;
4774 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4775 "movd\t{$src, $dst|$dst, $src}",
4776 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4777 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4779 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4780 "movd\t{$src, $dst|$dst, $src}",
4781 [(store (i32 (vector_extract (v4i32 VR128:$src),
4782 (iPTR 0))), addr:$dst)],
4783 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4785 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4786 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4788 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4789 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4791 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4792 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4794 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4795 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4797 //===---------------------------------------------------------------------===//
4798 // Move Packed Doubleword Int first element to Doubleword Int
4800 let SchedRW = [WriteMove] in {
4801 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4802 "movq\t{$src, $dst|$dst, $src}",
4803 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4808 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4809 "mov{d|q}\t{$src, $dst|$dst, $src}",
4810 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4815 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4816 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4817 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4818 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4819 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4820 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4821 "mov{d|q}\t{$src, $dst|$dst, $src}",
4822 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4824 //===---------------------------------------------------------------------===//
4825 // Bitcast FR64 <-> GR64
4827 let isCodeGenOnly = 1 in {
4828 let Predicates = [UseAVX] in
4829 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4830 "movq\t{$src, $dst|$dst, $src}",
4831 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4832 VEX, Sched<[WriteLoad]>;
4833 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4834 "movq\t{$src, $dst|$dst, $src}",
4835 [(set GR64:$dst, (bitconvert FR64:$src))],
4836 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4837 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4838 "movq\t{$src, $dst|$dst, $src}",
4839 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4840 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4842 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4843 "movq\t{$src, $dst|$dst, $src}",
4844 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4845 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4846 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4847 "mov{d|q}\t{$src, $dst|$dst, $src}",
4848 [(set GR64:$dst, (bitconvert FR64:$src))],
4849 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4850 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4851 "movq\t{$src, $dst|$dst, $src}",
4852 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4853 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4856 //===---------------------------------------------------------------------===//
4857 // Move Scalar Single to Double Int
4859 let isCodeGenOnly = 1 in {
4860 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4861 "movd\t{$src, $dst|$dst, $src}",
4862 [(set GR32:$dst, (bitconvert FR32:$src))],
4863 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4864 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4865 "movd\t{$src, $dst|$dst, $src}",
4866 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4867 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4868 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4869 "movd\t{$src, $dst|$dst, $src}",
4870 [(set GR32:$dst, (bitconvert FR32:$src))],
4871 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4872 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4873 "movd\t{$src, $dst|$dst, $src}",
4874 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4875 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4878 //===---------------------------------------------------------------------===//
4879 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4881 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4882 let AddedComplexity = 15 in {
4883 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4884 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4885 [(set VR128:$dst, (v2i64 (X86vzmovl
4886 (v2i64 (scalar_to_vector GR64:$src)))))],
4889 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4890 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4891 [(set VR128:$dst, (v2i64 (X86vzmovl
4892 (v2i64 (scalar_to_vector GR64:$src)))))],
4895 } // isCodeGenOnly, SchedRW
4897 let Predicates = [UseAVX] in {
4898 let AddedComplexity = 15 in
4899 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4900 (VMOVDI2PDIrr GR32:$src)>;
4902 // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part.
4903 // These instructions also write zeros in the high part of a 256-bit register.
4904 let AddedComplexity = 20 in {
4905 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4906 (VMOVDI2PDIrm addr:$src)>;
4907 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4908 (VMOVDI2PDIrm addr:$src)>;
4909 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4910 (VMOVDI2PDIrm addr:$src)>;
4911 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4912 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
4913 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrm addr:$src), sub_xmm)>;
4915 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4916 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4917 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4918 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4919 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4920 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4921 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4924 let Predicates = [UseSSE2] in {
4925 let AddedComplexity = 15 in
4926 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4927 (MOVDI2PDIrr GR32:$src)>;
4929 let AddedComplexity = 20 in {
4930 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4931 (MOVDI2PDIrm addr:$src)>;
4932 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4933 (MOVDI2PDIrm addr:$src)>;
4934 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4935 (MOVDI2PDIrm addr:$src)>;
4939 // These are the correct encodings of the instructions so that we know how to
4940 // read correct assembly, even though we continue to emit the wrong ones for
4941 // compatibility with Darwin's buggy assembler.
4942 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4943 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4944 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4945 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4946 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4947 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4948 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4949 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4950 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4952 //===---------------------------------------------------------------------===//
4953 // SSE2 - Move Quadword
4954 //===---------------------------------------------------------------------===//
4956 //===---------------------------------------------------------------------===//
4957 // Move Quadword Int to Packed Quadword Int
4960 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4961 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4962 "vmovq\t{$src, $dst|$dst, $src}",
4964 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4965 VEX, Requires<[UseAVX]>;
4966 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4967 "movq\t{$src, $dst|$dst, $src}",
4969 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4971 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4972 } // ExeDomain, SchedRW
4974 //===---------------------------------------------------------------------===//
4975 // Move Packed Quadword Int to Quadword Int
4977 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4978 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4979 "movq\t{$src, $dst|$dst, $src}",
4980 [(store (i64 (vector_extract (v2i64 VR128:$src),
4981 (iPTR 0))), addr:$dst)],
4982 IIC_SSE_MOVDQ>, VEX;
4983 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4984 "movq\t{$src, $dst|$dst, $src}",
4985 [(store (i64 (vector_extract (v2i64 VR128:$src),
4986 (iPTR 0))), addr:$dst)],
4988 } // ExeDomain, SchedRW
4990 // For disassembler only
4991 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4992 SchedRW = [WriteVecLogic] in {
4993 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4994 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
4995 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4996 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
4999 //===---------------------------------------------------------------------===//
5000 // Store / copy lower 64-bits of a XMM register.
5002 let Predicates = [HasAVX] in
5003 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5004 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5005 let Predicates = [UseSSE2] in
5006 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5007 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5009 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
5010 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5011 "vmovq\t{$src, $dst|$dst, $src}",
5013 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5014 (loadi64 addr:$src))))))],
5016 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5018 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5019 "movq\t{$src, $dst|$dst, $src}",
5021 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5022 (loadi64 addr:$src))))))],
5024 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5025 } // ExeDomain, isCodeGenOnly, AddedComplexity
5027 let Predicates = [UseAVX], AddedComplexity = 20 in {
5028 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5029 (VMOVZQI2PQIrm addr:$src)>;
5030 def : Pat<(v2i64 (X86vzload addr:$src)),
5031 (VMOVZQI2PQIrm addr:$src)>;
5032 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5033 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
5034 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
5037 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5038 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5039 (MOVZQI2PQIrm addr:$src)>;
5040 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5043 let Predicates = [HasAVX] in {
5044 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5045 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5046 def : Pat<(v4i64 (X86vzload addr:$src)),
5047 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5050 //===---------------------------------------------------------------------===//
5051 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5052 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5054 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5055 let AddedComplexity = 15 in
5056 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5057 "vmovq\t{$src, $dst|$dst, $src}",
5058 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5060 XS, VEX, Requires<[UseAVX]>;
5061 let AddedComplexity = 15 in
5062 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5063 "movq\t{$src, $dst|$dst, $src}",
5064 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5066 XS, Requires<[UseSSE2]>;
5067 } // ExeDomain, SchedRW
5069 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5070 let AddedComplexity = 20 in
5071 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5072 "vmovq\t{$src, $dst|$dst, $src}",
5073 [(set VR128:$dst, (v2i64 (X86vzmovl
5074 (loadv2i64 addr:$src))))],
5076 XS, VEX, Requires<[UseAVX]>;
5077 let AddedComplexity = 20 in {
5078 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5079 "movq\t{$src, $dst|$dst, $src}",
5080 [(set VR128:$dst, (v2i64 (X86vzmovl
5081 (loadv2i64 addr:$src))))],
5083 XS, Requires<[UseSSE2]>;
5085 } // ExeDomain, isCodeGenOnly, SchedRW
5087 let AddedComplexity = 20 in {
5088 let Predicates = [UseAVX] in {
5089 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5090 (VMOVZPQILo2PQIrr VR128:$src)>;
5092 let Predicates = [UseSSE2] in {
5093 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5094 (MOVZPQILo2PQIrr VR128:$src)>;
5098 //===---------------------------------------------------------------------===//
5099 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5100 //===---------------------------------------------------------------------===//
5101 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5102 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5103 X86MemOperand x86memop> {
5104 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5105 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5106 [(set RC:$dst, (vt (OpNode RC:$src)))],
5107 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5108 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5109 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5110 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5111 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5114 let Predicates = [HasAVX] in {
5115 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5116 v4f32, VR128, loadv4f32, f128mem>, VEX;
5117 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5118 v4f32, VR128, loadv4f32, f128mem>, VEX;
5119 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5120 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5121 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5122 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5124 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5125 memopv4f32, f128mem>;
5126 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5127 memopv4f32, f128mem>;
5129 let Predicates = [HasAVX] in {
5130 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5131 (VMOVSHDUPrr VR128:$src)>;
5132 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5133 (VMOVSHDUPrm addr:$src)>;
5134 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5135 (VMOVSLDUPrr VR128:$src)>;
5136 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5137 (VMOVSLDUPrm addr:$src)>;
5138 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5139 (VMOVSHDUPYrr VR256:$src)>;
5140 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5141 (VMOVSHDUPYrm addr:$src)>;
5142 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5143 (VMOVSLDUPYrr VR256:$src)>;
5144 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5145 (VMOVSLDUPYrm addr:$src)>;
5148 let Predicates = [UseSSE3] in {
5149 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5150 (MOVSHDUPrr VR128:$src)>;
5151 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5152 (MOVSHDUPrm addr:$src)>;
5153 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5154 (MOVSLDUPrr VR128:$src)>;
5155 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5156 (MOVSLDUPrm addr:$src)>;
5159 //===---------------------------------------------------------------------===//
5160 // SSE3 - Replicate Double FP - MOVDDUP
5161 //===---------------------------------------------------------------------===//
5163 multiclass sse3_replicate_dfp<string OpcodeStr> {
5164 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5165 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5166 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5167 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5168 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5169 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5172 (scalar_to_vector (loadf64 addr:$src)))))],
5173 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5176 // FIXME: Merge with above classe when there're patterns for the ymm version
5177 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5178 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5179 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5180 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5181 Sched<[WriteFShuffle]>;
5182 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5183 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5186 (scalar_to_vector (loadf64 addr:$src)))))]>,
5190 let Predicates = [HasAVX] in {
5191 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5192 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5195 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5197 let Predicates = [HasAVX] in {
5198 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5199 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5200 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5201 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5202 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5203 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5204 def : Pat<(X86Movddup (bc_v2f64
5205 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5206 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5209 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5210 (VMOVDDUPYrm addr:$src)>;
5211 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5212 (VMOVDDUPYrm addr:$src)>;
5213 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5214 (VMOVDDUPYrm addr:$src)>;
5215 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5216 (VMOVDDUPYrr VR256:$src)>;
5219 let Predicates = [UseAVX, OptForSize] in {
5220 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5221 (VMOVDDUPrm addr:$src)>;
5222 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5223 (VMOVDDUPrm addr:$src)>;
5226 let Predicates = [UseSSE3] in {
5227 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5228 (MOVDDUPrm addr:$src)>;
5229 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5230 (MOVDDUPrm addr:$src)>;
5231 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5232 (MOVDDUPrm addr:$src)>;
5233 def : Pat<(X86Movddup (bc_v2f64
5234 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5235 (MOVDDUPrm addr:$src)>;
5238 //===---------------------------------------------------------------------===//
5239 // SSE3 - Move Unaligned Integer
5240 //===---------------------------------------------------------------------===//
5242 let SchedRW = [WriteLoad] in {
5243 let Predicates = [HasAVX] in {
5244 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5245 "vlddqu\t{$src, $dst|$dst, $src}",
5246 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5247 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5248 "vlddqu\t{$src, $dst|$dst, $src}",
5249 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5252 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5253 "lddqu\t{$src, $dst|$dst, $src}",
5254 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5258 //===---------------------------------------------------------------------===//
5259 // SSE3 - Arithmetic
5260 //===---------------------------------------------------------------------===//
5262 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5263 X86MemOperand x86memop, OpndItins itins,
5264 PatFrag ld_frag, bit Is2Addr = 1> {
5265 def rr : I<0xD0, MRMSrcReg,
5266 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5268 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5269 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5270 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5271 Sched<[itins.Sched]>;
5272 def rm : I<0xD0, MRMSrcMem,
5273 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5275 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5276 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5277 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5278 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5281 let Predicates = [HasAVX] in {
5282 let ExeDomain = SSEPackedSingle in {
5283 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5284 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5285 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5286 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5288 let ExeDomain = SSEPackedDouble in {
5289 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5290 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5291 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5292 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5295 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5296 let ExeDomain = SSEPackedSingle in
5297 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5298 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5299 let ExeDomain = SSEPackedDouble in
5300 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5301 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5304 // Patterns used to select 'addsub' instructions.
5305 let Predicates = [HasAVX] in {
5306 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5307 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5308 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5309 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5310 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5311 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5312 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5313 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5315 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5316 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5317 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5318 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5319 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5320 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5321 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5322 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5325 let Predicates = [UseSSE3] in {
5326 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5327 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5328 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5329 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5330 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5331 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5332 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5333 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5336 //===---------------------------------------------------------------------===//
5337 // SSE3 Instructions
5338 //===---------------------------------------------------------------------===//
5341 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5342 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5344 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5348 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5351 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5353 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5354 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5355 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5356 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5358 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5359 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5361 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5363 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5364 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5365 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5368 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5370 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5371 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5372 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5373 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5376 let Predicates = [HasAVX] in {
5377 let ExeDomain = SSEPackedSingle in {
5378 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5379 X86fhadd, loadv4f32, 0>, VEX_4V;
5380 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5381 X86fhsub, loadv4f32, 0>, VEX_4V;
5382 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5383 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5384 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5385 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5387 let ExeDomain = SSEPackedDouble in {
5388 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5389 X86fhadd, loadv2f64, 0>, VEX_4V;
5390 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5391 X86fhsub, loadv2f64, 0>, VEX_4V;
5392 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5393 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5394 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5395 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5399 let Constraints = "$src1 = $dst" in {
5400 let ExeDomain = SSEPackedSingle in {
5401 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5403 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5406 let ExeDomain = SSEPackedDouble in {
5407 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5409 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5414 //===---------------------------------------------------------------------===//
5415 // SSSE3 - Packed Absolute Instructions
5416 //===---------------------------------------------------------------------===//
5419 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5420 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5422 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5424 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5425 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5426 Sched<[WriteVecALU]>;
5428 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5430 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5433 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5434 Sched<[WriteVecALULd]>;
5437 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5438 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5439 Intrinsic IntId256> {
5440 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5442 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5443 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5444 Sched<[WriteVecALU]>;
5446 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5448 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5451 (bitconvert (loadv4i64 addr:$src))))]>,
5452 Sched<[WriteVecALULd]>;
5455 // Helper fragments to match sext vXi1 to vXiY.
5456 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5458 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5459 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5460 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5462 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5463 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5465 let Predicates = [HasAVX] in {
5466 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5468 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5470 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5474 (bc_v2i64 (v16i1sextv16i8)),
5475 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5476 (VPABSBrr128 VR128:$src)>;
5478 (bc_v2i64 (v8i1sextv8i16)),
5479 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5480 (VPABSWrr128 VR128:$src)>;
5482 (bc_v2i64 (v4i1sextv4i32)),
5483 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5484 (VPABSDrr128 VR128:$src)>;
5487 let Predicates = [HasAVX2] in {
5488 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5489 int_x86_avx2_pabs_b>, VEX, VEX_L;
5490 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5491 int_x86_avx2_pabs_w>, VEX, VEX_L;
5492 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5493 int_x86_avx2_pabs_d>, VEX, VEX_L;
5496 (bc_v4i64 (v32i1sextv32i8)),
5497 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5498 (VPABSBrr256 VR256:$src)>;
5500 (bc_v4i64 (v16i1sextv16i16)),
5501 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5502 (VPABSWrr256 VR256:$src)>;
5504 (bc_v4i64 (v8i1sextv8i32)),
5505 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5506 (VPABSDrr256 VR256:$src)>;
5509 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5511 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5513 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5516 let Predicates = [HasSSSE3] in {
5518 (bc_v2i64 (v16i1sextv16i8)),
5519 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5520 (PABSBrr128 VR128:$src)>;
5522 (bc_v2i64 (v8i1sextv8i16)),
5523 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5524 (PABSWrr128 VR128:$src)>;
5526 (bc_v2i64 (v4i1sextv4i32)),
5527 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5528 (PABSDrr128 VR128:$src)>;
5531 //===---------------------------------------------------------------------===//
5532 // SSSE3 - Packed Binary Operator Instructions
5533 //===---------------------------------------------------------------------===//
5535 let Sched = WriteVecALU in {
5536 def SSE_PHADDSUBD : OpndItins<
5537 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5539 def SSE_PHADDSUBSW : OpndItins<
5540 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5542 def SSE_PHADDSUBW : OpndItins<
5543 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5546 let Sched = WriteShuffle in
5547 def SSE_PSHUFB : OpndItins<
5548 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5550 let Sched = WriteVecALU in
5551 def SSE_PSIGN : OpndItins<
5552 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5554 let Sched = WriteVecIMul in
5555 def SSE_PMULHRSW : OpndItins<
5556 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5559 /// SS3I_binop_rm - Simple SSSE3 bin op
5560 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5561 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5562 X86MemOperand x86memop, OpndItins itins,
5564 let isCommutable = 1 in
5565 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5566 (ins RC:$src1, RC:$src2),
5568 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5569 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5570 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5571 Sched<[itins.Sched]>;
5572 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5573 (ins RC:$src1, x86memop:$src2),
5575 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5576 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5578 (OpVT (OpNode RC:$src1,
5579 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5580 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5583 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5584 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5585 Intrinsic IntId128, OpndItins itins,
5586 PatFrag ld_frag, bit Is2Addr = 1> {
5587 let isCommutable = 1 in
5588 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5589 (ins VR128:$src1, VR128:$src2),
5591 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5592 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5593 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5594 Sched<[itins.Sched]>;
5595 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5596 (ins VR128:$src1, i128mem:$src2),
5598 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5599 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5601 (IntId128 VR128:$src1,
5602 (bitconvert (ld_frag addr:$src2))))]>,
5603 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5606 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5608 X86FoldableSchedWrite Sched> {
5609 let isCommutable = 1 in
5610 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5611 (ins VR256:$src1, VR256:$src2),
5612 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5613 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5615 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5616 (ins VR256:$src1, i256mem:$src2),
5617 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5619 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5620 Sched<[Sched.Folded, ReadAfterLd]>;
5623 let ImmT = NoImm, Predicates = [HasAVX] in {
5624 let isCommutable = 0 in {
5625 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5627 SSE_PHADDSUBW, 0>, VEX_4V;
5628 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5630 SSE_PHADDSUBD, 0>, VEX_4V;
5631 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5633 SSE_PHADDSUBW, 0>, VEX_4V;
5634 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5636 SSE_PHADDSUBD, 0>, VEX_4V;
5637 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5639 SSE_PSIGN, 0>, VEX_4V;
5640 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5642 SSE_PSIGN, 0>, VEX_4V;
5643 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5645 SSE_PSIGN, 0>, VEX_4V;
5646 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5648 SSE_PSHUFB, 0>, VEX_4V;
5649 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5650 int_x86_ssse3_phadd_sw_128,
5651 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5652 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5653 int_x86_ssse3_phsub_sw_128,
5654 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5655 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5656 int_x86_ssse3_pmadd_ub_sw_128,
5657 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5659 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5660 int_x86_ssse3_pmul_hr_sw_128,
5661 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5664 let ImmT = NoImm, Predicates = [HasAVX2] in {
5665 let isCommutable = 0 in {
5666 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5668 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5669 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5671 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5672 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5674 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5675 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5677 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5678 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5680 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5681 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5683 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5684 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5686 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5687 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5689 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5690 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5691 int_x86_avx2_phadd_sw,
5692 WriteVecALU>, VEX_4V, VEX_L;
5693 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5694 int_x86_avx2_phsub_sw,
5695 WriteVecALU>, VEX_4V, VEX_L;
5696 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5697 int_x86_avx2_pmadd_ub_sw,
5698 WriteVecIMul>, VEX_4V, VEX_L;
5700 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5701 int_x86_avx2_pmul_hr_sw,
5702 WriteVecIMul>, VEX_4V, VEX_L;
5705 // None of these have i8 immediate fields.
5706 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5707 let isCommutable = 0 in {
5708 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5709 memopv2i64, i128mem, SSE_PHADDSUBW>;
5710 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5711 memopv2i64, i128mem, SSE_PHADDSUBD>;
5712 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5713 memopv2i64, i128mem, SSE_PHADDSUBW>;
5714 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5715 memopv2i64, i128mem, SSE_PHADDSUBD>;
5716 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5717 memopv2i64, i128mem, SSE_PSIGN>;
5718 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5719 memopv2i64, i128mem, SSE_PSIGN>;
5720 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5721 memopv2i64, i128mem, SSE_PSIGN>;
5722 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5723 memopv2i64, i128mem, SSE_PSHUFB>;
5724 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5725 int_x86_ssse3_phadd_sw_128,
5726 SSE_PHADDSUBSW, memopv2i64>;
5727 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5728 int_x86_ssse3_phsub_sw_128,
5729 SSE_PHADDSUBSW, memopv2i64>;
5730 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5731 int_x86_ssse3_pmadd_ub_sw_128,
5732 SSE_PMADD, memopv2i64>;
5734 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5735 int_x86_ssse3_pmul_hr_sw_128,
5736 SSE_PMULHRSW, memopv2i64>;
5739 //===---------------------------------------------------------------------===//
5740 // SSSE3 - Packed Align Instruction Patterns
5741 //===---------------------------------------------------------------------===//
5743 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5744 let hasSideEffects = 0 in {
5745 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5746 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5748 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5750 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5751 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5753 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5754 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5756 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5758 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5759 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5763 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5764 let hasSideEffects = 0 in {
5765 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5766 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5768 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5769 []>, Sched<[WriteShuffle]>;
5771 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5772 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5774 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5775 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5779 let Predicates = [HasAVX] in
5780 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5781 let Predicates = [HasAVX2] in
5782 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5783 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5784 defm PALIGN : ssse3_palignr<"palignr">;
5786 let Predicates = [HasAVX2] in {
5787 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5788 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5789 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5790 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5791 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5792 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5793 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5794 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5797 let Predicates = [HasAVX] in {
5798 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5799 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5800 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5801 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5802 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5803 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5804 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5805 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5808 let Predicates = [UseSSSE3] in {
5809 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5810 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5811 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5812 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5813 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5814 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5815 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5816 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5819 //===---------------------------------------------------------------------===//
5820 // SSSE3 - Thread synchronization
5821 //===---------------------------------------------------------------------===//
5823 let SchedRW = [WriteSystem] in {
5824 let usesCustomInserter = 1 in {
5825 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5826 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5827 Requires<[HasSSE3]>;
5830 let Uses = [EAX, ECX, EDX] in
5831 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5832 TB, Requires<[HasSSE3]>;
5833 let Uses = [ECX, EAX] in
5834 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5835 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5836 TB, Requires<[HasSSE3]>;
5839 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5840 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5842 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5843 Requires<[Not64BitMode]>;
5844 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5845 Requires<[In64BitMode]>;
5847 //===----------------------------------------------------------------------===//
5848 // SSE4.1 - Packed Move with Sign/Zero Extend
5849 //===----------------------------------------------------------------------===//
5851 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5852 RegisterClass OutRC, RegisterClass InRC,
5854 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5855 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5857 Sched<[itins.Sched]>;
5859 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5860 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5862 itins.rm>, Sched<[itins.Sched.Folded]>;
5865 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5866 X86MemOperand MemOp, X86MemOperand MemYOp,
5867 OpndItins SSEItins, OpndItins AVXItins,
5868 OpndItins AVX2Itins> {
5869 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5870 let Predicates = [HasAVX, NoVLX] in
5871 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5872 VR128, VR128, AVXItins>, VEX;
5873 let Predicates = [HasAVX2, NoVLX] in
5874 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5875 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5878 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5879 X86MemOperand MemOp, X86MemOperand MemYOp> {
5880 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5882 SSE_INTALU_ITINS_SHUFF_P,
5883 DEFAULT_ITINS_SHUFFLESCHED,
5884 DEFAULT_ITINS_SHUFFLESCHED>;
5885 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5886 !strconcat("pmovzx", OpcodeStr),
5888 SSE_INTALU_ITINS_SHUFF_P,
5889 DEFAULT_ITINS_SHUFFLESCHED,
5890 DEFAULT_ITINS_SHUFFLESCHED>;
5893 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5894 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5895 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5897 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5898 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5900 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5903 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5904 // Register-Register patterns
5905 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5906 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5907 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5908 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5909 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5910 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5912 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5913 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5914 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5915 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5917 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5918 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5920 // On AVX2, we also support 256bit inputs.
5921 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5922 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5923 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5924 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5925 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5926 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5928 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5929 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5930 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5931 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5933 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5934 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5936 // Simple Register-Memory patterns
5937 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5938 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5939 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5940 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5941 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5942 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5944 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5945 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5946 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5947 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5949 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5950 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5952 // AVX2 Register-Memory patterns
5953 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5954 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5955 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5956 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5957 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5958 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5959 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5960 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5962 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5963 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5964 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5965 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5966 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5967 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5968 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5969 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5971 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5972 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5973 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5974 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5975 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5976 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5977 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5978 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5980 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5981 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5982 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5983 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5984 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5985 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5986 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5987 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5989 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5990 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5991 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5992 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5993 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5994 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5995 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5996 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5998 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5999 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6000 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6001 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6002 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6003 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6004 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6005 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6008 let Predicates = [HasAVX2, NoVLX] in {
6009 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6010 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6013 // SSE4.1/AVX patterns.
6014 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6015 SDNode ExtOp, PatFrag ExtLoad16> {
6016 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6017 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6018 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6019 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6020 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6021 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6023 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6024 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6025 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6026 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6028 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6029 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6031 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6032 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6033 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6034 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6035 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6036 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6038 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6039 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6040 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6041 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6043 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6044 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6046 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6047 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6048 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6049 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6050 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6051 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6052 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6053 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6054 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6055 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6057 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6058 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6059 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6060 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6061 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6062 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6063 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6064 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6066 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6067 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6068 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6069 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6070 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6071 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6072 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6073 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6075 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6076 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6077 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6078 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6079 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6080 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6081 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6082 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6083 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6084 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6086 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6087 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6088 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6089 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6090 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6091 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6092 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6093 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6095 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6096 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6097 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6098 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6099 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6100 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6101 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6102 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6103 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6104 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6107 let Predicates = [HasAVX, NoVLX] in {
6108 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6109 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6112 let Predicates = [UseSSE41] in {
6113 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6114 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6117 //===----------------------------------------------------------------------===//
6118 // SSE4.1 - Extract Instructions
6119 //===----------------------------------------------------------------------===//
6121 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6122 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6123 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6124 (ins VR128:$src1, u8imm:$src2),
6125 !strconcat(OpcodeStr,
6126 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6127 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6129 Sched<[WriteShuffle]>;
6130 let hasSideEffects = 0, mayStore = 1,
6131 SchedRW = [WriteShuffleLd, WriteRMW] in
6132 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6133 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6134 !strconcat(OpcodeStr,
6135 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6136 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6137 imm:$src2)))), addr:$dst)]>;
6140 let Predicates = [HasAVX] in
6141 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6143 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6146 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6147 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6148 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6149 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6150 (ins VR128:$src1, u8imm:$src2),
6151 !strconcat(OpcodeStr,
6152 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6153 []>, Sched<[WriteShuffle]>;
6155 let hasSideEffects = 0, mayStore = 1,
6156 SchedRW = [WriteShuffleLd, WriteRMW] in
6157 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6158 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6159 !strconcat(OpcodeStr,
6160 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6161 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6162 imm:$src2)))), addr:$dst)]>;
6165 let Predicates = [HasAVX] in
6166 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6168 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6171 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6172 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6173 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6174 (ins VR128:$src1, u8imm:$src2),
6175 !strconcat(OpcodeStr,
6176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6178 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6179 Sched<[WriteShuffle]>;
6180 let SchedRW = [WriteShuffleLd, WriteRMW] in
6181 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6182 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6183 !strconcat(OpcodeStr,
6184 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6185 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6189 let Predicates = [HasAVX] in
6190 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6192 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6194 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6195 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6196 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6197 (ins VR128:$src1, u8imm:$src2),
6198 !strconcat(OpcodeStr,
6199 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6201 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6202 Sched<[WriteShuffle]>, REX_W;
6203 let SchedRW = [WriteShuffleLd, WriteRMW] in
6204 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6205 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6206 !strconcat(OpcodeStr,
6207 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6208 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6209 addr:$dst)]>, REX_W;
6212 let Predicates = [HasAVX] in
6213 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6215 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6217 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6219 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6220 OpndItins itins = DEFAULT_ITINS> {
6221 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6222 (ins VR128:$src1, u8imm:$src2),
6223 !strconcat(OpcodeStr,
6224 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6225 [(set GR32orGR64:$dst,
6226 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6227 itins.rr>, Sched<[WriteFBlend]>;
6228 let SchedRW = [WriteFBlendLd, WriteRMW] in
6229 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6230 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6231 !strconcat(OpcodeStr,
6232 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6233 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6234 addr:$dst)], itins.rm>;
6237 let ExeDomain = SSEPackedSingle in {
6238 let Predicates = [UseAVX] in
6239 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6240 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6243 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6244 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6247 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6249 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6252 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6253 Requires<[UseSSE41]>;
6255 //===----------------------------------------------------------------------===//
6256 // SSE4.1 - Insert Instructions
6257 //===----------------------------------------------------------------------===//
6259 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6260 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6261 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6263 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6265 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6267 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6268 Sched<[WriteShuffle]>;
6269 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6270 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6272 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6274 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6276 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6277 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6280 let Predicates = [HasAVX] in
6281 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6282 let Constraints = "$src1 = $dst" in
6283 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6285 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6286 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6287 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6289 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6291 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6293 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6294 Sched<[WriteShuffle]>;
6295 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6296 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6298 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6300 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6302 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6303 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6306 let Predicates = [HasAVX] in
6307 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6308 let Constraints = "$src1 = $dst" in
6309 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6311 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6312 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6313 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6315 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6317 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6319 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6320 Sched<[WriteShuffle]>;
6321 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6322 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6324 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6326 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6328 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6329 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6332 let Predicates = [HasAVX] in
6333 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6334 let Constraints = "$src1 = $dst" in
6335 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6337 // insertps has a few different modes, there's the first two here below which
6338 // are optimized inserts that won't zero arbitrary elements in the destination
6339 // vector. The next one matches the intrinsic and could zero arbitrary elements
6340 // in the target vector.
6341 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6342 OpndItins itins = DEFAULT_ITINS> {
6343 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6344 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6346 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6348 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6350 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6351 Sched<[WriteFShuffle]>;
6352 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6353 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6355 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6357 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6359 (X86insertps VR128:$src1,
6360 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6361 imm:$src3))], itins.rm>,
6362 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6365 let ExeDomain = SSEPackedSingle in {
6366 let Predicates = [UseAVX] in
6367 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6368 let Constraints = "$src1 = $dst" in
6369 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6372 let Predicates = [UseSSE41] in {
6373 // If we're inserting an element from a load or a null pshuf of a load,
6374 // fold the load into the insertps instruction.
6375 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6376 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6378 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6379 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6380 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6381 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6384 let Predicates = [UseAVX] in {
6385 // If we're inserting an element from a vbroadcast of a load, fold the
6386 // load into the X86insertps instruction.
6387 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6388 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6389 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6390 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6391 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6392 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6395 //===----------------------------------------------------------------------===//
6396 // SSE4.1 - Round Instructions
6397 //===----------------------------------------------------------------------===//
6399 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6400 X86MemOperand x86memop, RegisterClass RC,
6401 PatFrag mem_frag32, PatFrag mem_frag64,
6402 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6403 let ExeDomain = SSEPackedSingle in {
6404 // Intrinsic operation, reg.
6405 // Vector intrinsic operation, reg
6406 def PSr : SS4AIi8<opcps, MRMSrcReg,
6407 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6408 !strconcat(OpcodeStr,
6409 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6410 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6411 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6413 // Vector intrinsic operation, mem
6414 def PSm : SS4AIi8<opcps, MRMSrcMem,
6415 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6416 !strconcat(OpcodeStr,
6417 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6419 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6420 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6421 } // ExeDomain = SSEPackedSingle
6423 let ExeDomain = SSEPackedDouble in {
6424 // Vector intrinsic operation, reg
6425 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6426 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6427 !strconcat(OpcodeStr,
6428 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6429 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6430 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6432 // Vector intrinsic operation, mem
6433 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6434 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6435 !strconcat(OpcodeStr,
6436 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6438 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6439 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6440 } // ExeDomain = SSEPackedDouble
6443 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6446 Intrinsic F64Int, bit Is2Addr = 1> {
6447 let ExeDomain = GenericDomain in {
6449 let hasSideEffects = 0 in
6450 def SSr : SS4AIi8<opcss, MRMSrcReg,
6451 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6453 !strconcat(OpcodeStr,
6454 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6455 !strconcat(OpcodeStr,
6456 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6457 []>, Sched<[WriteFAdd]>;
6459 // Intrinsic operation, reg.
6460 let isCodeGenOnly = 1 in
6461 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6462 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6464 !strconcat(OpcodeStr,
6465 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6466 !strconcat(OpcodeStr,
6467 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6468 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6471 // Intrinsic operation, mem.
6472 def SSm : SS4AIi8<opcss, MRMSrcMem,
6473 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6475 !strconcat(OpcodeStr,
6476 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6477 !strconcat(OpcodeStr,
6478 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6480 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6481 Sched<[WriteFAddLd, ReadAfterLd]>;
6484 let hasSideEffects = 0 in
6485 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6486 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6488 !strconcat(OpcodeStr,
6489 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6490 !strconcat(OpcodeStr,
6491 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6492 []>, Sched<[WriteFAdd]>;
6494 // Intrinsic operation, reg.
6495 let isCodeGenOnly = 1 in
6496 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6497 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6499 !strconcat(OpcodeStr,
6500 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6501 !strconcat(OpcodeStr,
6502 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6503 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6506 // Intrinsic operation, mem.
6507 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6508 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6510 !strconcat(OpcodeStr,
6511 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6512 !strconcat(OpcodeStr,
6513 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6515 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6516 Sched<[WriteFAddLd, ReadAfterLd]>;
6517 } // ExeDomain = GenericDomain
6520 // FP round - roundss, roundps, roundsd, roundpd
6521 let Predicates = [HasAVX] in {
6523 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6524 loadv4f32, loadv2f64,
6525 int_x86_sse41_round_ps,
6526 int_x86_sse41_round_pd>, VEX;
6527 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6528 loadv8f32, loadv4f64,
6529 int_x86_avx_round_ps_256,
6530 int_x86_avx_round_pd_256>, VEX, VEX_L;
6531 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6532 int_x86_sse41_round_ss,
6533 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6536 let Predicates = [UseAVX] in {
6537 def : Pat<(ffloor FR32:$src),
6538 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6539 def : Pat<(f64 (ffloor FR64:$src)),
6540 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6541 def : Pat<(f32 (fnearbyint FR32:$src)),
6542 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6543 def : Pat<(f64 (fnearbyint FR64:$src)),
6544 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6545 def : Pat<(f32 (fceil FR32:$src)),
6546 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6547 def : Pat<(f64 (fceil FR64:$src)),
6548 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6549 def : Pat<(f32 (frint FR32:$src)),
6550 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6551 def : Pat<(f64 (frint FR64:$src)),
6552 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6553 def : Pat<(f32 (ftrunc FR32:$src)),
6554 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6555 def : Pat<(f64 (ftrunc FR64:$src)),
6556 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6559 let Predicates = [HasAVX] in {
6560 def : Pat<(v4f32 (ffloor VR128:$src)),
6561 (VROUNDPSr VR128:$src, (i32 0x1))>;
6562 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6563 (VROUNDPSr VR128:$src, (i32 0xC))>;
6564 def : Pat<(v4f32 (fceil VR128:$src)),
6565 (VROUNDPSr VR128:$src, (i32 0x2))>;
6566 def : Pat<(v4f32 (frint VR128:$src)),
6567 (VROUNDPSr VR128:$src, (i32 0x4))>;
6568 def : Pat<(v4f32 (ftrunc VR128:$src)),
6569 (VROUNDPSr VR128:$src, (i32 0x3))>;
6571 def : Pat<(v2f64 (ffloor VR128:$src)),
6572 (VROUNDPDr VR128:$src, (i32 0x1))>;
6573 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6574 (VROUNDPDr VR128:$src, (i32 0xC))>;
6575 def : Pat<(v2f64 (fceil VR128:$src)),
6576 (VROUNDPDr VR128:$src, (i32 0x2))>;
6577 def : Pat<(v2f64 (frint VR128:$src)),
6578 (VROUNDPDr VR128:$src, (i32 0x4))>;
6579 def : Pat<(v2f64 (ftrunc VR128:$src)),
6580 (VROUNDPDr VR128:$src, (i32 0x3))>;
6582 def : Pat<(v8f32 (ffloor VR256:$src)),
6583 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6584 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6585 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6586 def : Pat<(v8f32 (fceil VR256:$src)),
6587 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6588 def : Pat<(v8f32 (frint VR256:$src)),
6589 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6590 def : Pat<(v8f32 (ftrunc VR256:$src)),
6591 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6593 def : Pat<(v4f64 (ffloor VR256:$src)),
6594 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6595 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6596 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6597 def : Pat<(v4f64 (fceil VR256:$src)),
6598 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6599 def : Pat<(v4f64 (frint VR256:$src)),
6600 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6601 def : Pat<(v4f64 (ftrunc VR256:$src)),
6602 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6605 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6606 memopv4f32, memopv2f64,
6607 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6608 let Constraints = "$src1 = $dst" in
6609 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6610 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6612 let Predicates = [UseSSE41] in {
6613 def : Pat<(ffloor FR32:$src),
6614 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6615 def : Pat<(f64 (ffloor FR64:$src)),
6616 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6617 def : Pat<(f32 (fnearbyint FR32:$src)),
6618 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6619 def : Pat<(f64 (fnearbyint FR64:$src)),
6620 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6621 def : Pat<(f32 (fceil FR32:$src)),
6622 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6623 def : Pat<(f64 (fceil FR64:$src)),
6624 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6625 def : Pat<(f32 (frint FR32:$src)),
6626 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6627 def : Pat<(f64 (frint FR64:$src)),
6628 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6629 def : Pat<(f32 (ftrunc FR32:$src)),
6630 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6631 def : Pat<(f64 (ftrunc FR64:$src)),
6632 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6634 def : Pat<(v4f32 (ffloor VR128:$src)),
6635 (ROUNDPSr VR128:$src, (i32 0x1))>;
6636 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6637 (ROUNDPSr VR128:$src, (i32 0xC))>;
6638 def : Pat<(v4f32 (fceil VR128:$src)),
6639 (ROUNDPSr VR128:$src, (i32 0x2))>;
6640 def : Pat<(v4f32 (frint VR128:$src)),
6641 (ROUNDPSr VR128:$src, (i32 0x4))>;
6642 def : Pat<(v4f32 (ftrunc VR128:$src)),
6643 (ROUNDPSr VR128:$src, (i32 0x3))>;
6645 def : Pat<(v2f64 (ffloor VR128:$src)),
6646 (ROUNDPDr VR128:$src, (i32 0x1))>;
6647 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6648 (ROUNDPDr VR128:$src, (i32 0xC))>;
6649 def : Pat<(v2f64 (fceil VR128:$src)),
6650 (ROUNDPDr VR128:$src, (i32 0x2))>;
6651 def : Pat<(v2f64 (frint VR128:$src)),
6652 (ROUNDPDr VR128:$src, (i32 0x4))>;
6653 def : Pat<(v2f64 (ftrunc VR128:$src)),
6654 (ROUNDPDr VR128:$src, (i32 0x3))>;
6657 //===----------------------------------------------------------------------===//
6658 // SSE4.1 - Packed Bit Test
6659 //===----------------------------------------------------------------------===//
6661 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6662 // the intel intrinsic that corresponds to this.
6663 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6664 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6665 "vptest\t{$src2, $src1|$src1, $src2}",
6666 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6667 Sched<[WriteVecLogic]>, VEX;
6668 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6669 "vptest\t{$src2, $src1|$src1, $src2}",
6670 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6671 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6673 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6674 "vptest\t{$src2, $src1|$src1, $src2}",
6675 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6676 Sched<[WriteVecLogic]>, VEX, VEX_L;
6677 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6678 "vptest\t{$src2, $src1|$src1, $src2}",
6679 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6680 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6683 let Defs = [EFLAGS] in {
6684 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6685 "ptest\t{$src2, $src1|$src1, $src2}",
6686 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6687 Sched<[WriteVecLogic]>;
6688 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6689 "ptest\t{$src2, $src1|$src1, $src2}",
6690 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6691 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6694 // The bit test instructions below are AVX only
6695 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6696 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6697 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6698 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6699 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6700 Sched<[WriteVecLogic]>, VEX;
6701 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6702 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6703 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6704 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6707 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6708 let ExeDomain = SSEPackedSingle in {
6709 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6710 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6713 let ExeDomain = SSEPackedDouble in {
6714 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6715 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6720 //===----------------------------------------------------------------------===//
6721 // SSE4.1 - Misc Instructions
6722 //===----------------------------------------------------------------------===//
6724 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6725 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6726 "popcnt{w}\t{$src, $dst|$dst, $src}",
6727 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6728 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6730 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6731 "popcnt{w}\t{$src, $dst|$dst, $src}",
6732 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6733 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6734 Sched<[WriteFAddLd]>, OpSize16, XS;
6736 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6737 "popcnt{l}\t{$src, $dst|$dst, $src}",
6738 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6739 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6742 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6743 "popcnt{l}\t{$src, $dst|$dst, $src}",
6744 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6745 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6746 Sched<[WriteFAddLd]>, OpSize32, XS;
6748 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6749 "popcnt{q}\t{$src, $dst|$dst, $src}",
6750 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6751 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6752 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6753 "popcnt{q}\t{$src, $dst|$dst, $src}",
6754 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6755 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6756 Sched<[WriteFAddLd]>, XS;
6761 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6762 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6763 Intrinsic IntId128, PatFrag ld_frag,
6764 X86FoldableSchedWrite Sched> {
6765 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6767 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6768 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6770 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6772 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6774 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6775 Sched<[Sched.Folded]>;
6778 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6779 // model, although the naming is misleading.
6780 let Predicates = [HasAVX] in
6781 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6782 int_x86_sse41_phminposuw, loadv2i64,
6784 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6785 int_x86_sse41_phminposuw, memopv2i64,
6788 /// SS48I_binop_rm - Simple SSE41 binary operator.
6789 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6790 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6791 X86MemOperand x86memop, bit Is2Addr = 1,
6792 OpndItins itins = SSE_INTALU_ITINS_P> {
6793 let isCommutable = 1 in
6794 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6795 (ins RC:$src1, RC:$src2),
6797 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6798 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6799 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6800 Sched<[itins.Sched]>;
6801 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6802 (ins RC:$src1, x86memop:$src2),
6804 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6805 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6807 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6808 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6811 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6813 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6814 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6815 PatFrag memop_frag, X86MemOperand x86memop,
6817 bit IsCommutable = 0, bit Is2Addr = 1> {
6818 let isCommutable = IsCommutable in
6819 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6820 (ins RC:$src1, RC:$src2),
6822 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6823 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6824 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6825 Sched<[itins.Sched]>;
6826 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6827 (ins RC:$src1, x86memop:$src2),
6829 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6830 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6831 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6832 (bitconvert (memop_frag addr:$src2)))))]>,
6833 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6836 let Predicates = [HasAVX, NoVLX] in {
6837 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", smin, v16i8, VR128,
6838 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6840 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", smin, v4i32, VR128,
6841 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6843 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", umin, v4i32, VR128,
6844 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6846 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", umin, v8i16, VR128,
6847 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6849 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v16i8, VR128,
6850 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6852 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v4i32, VR128,
6853 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6855 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", umax, v4i32, VR128,
6856 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6858 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v8i16, VR128,
6859 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6861 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6862 VR128, loadv2i64, i128mem,
6863 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6866 let Predicates = [HasAVX2, NoVLX] in {
6867 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", smin, v32i8, VR256,
6868 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6870 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", smin, v8i32, VR256,
6871 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6873 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", umin, v8i32, VR256,
6874 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6876 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", umin, v16i16, VR256,
6877 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6879 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v32i8, VR256,
6880 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6882 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v8i32, VR256,
6883 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6885 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", umax, v8i32, VR256,
6886 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6888 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v16i16, VR256,
6889 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6891 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6892 VR256, loadv4i64, i256mem,
6893 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6896 let Constraints = "$src1 = $dst" in {
6897 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", smin, v16i8, VR128,
6898 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6899 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", smin, v4i32, VR128,
6900 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6901 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", umin, v4i32, VR128,
6902 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6903 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", umin, v8i16, VR128,
6904 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6905 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", smax, v16i8, VR128,
6906 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6907 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", smax, v4i32, VR128,
6908 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6909 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", umax, v4i32, VR128,
6910 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6911 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", umax, v8i16, VR128,
6912 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6913 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6914 VR128, memopv2i64, i128mem,
6915 SSE_INTMUL_ITINS_P, 1>;
6918 let Predicates = [HasAVX, NoVLX] in {
6919 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6920 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6922 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6923 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6926 let Predicates = [HasAVX2] in {
6927 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6928 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6930 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6931 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6935 let Constraints = "$src1 = $dst" in {
6936 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6937 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6938 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6939 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6942 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6943 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6944 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6945 X86MemOperand x86memop, bit Is2Addr = 1,
6946 OpndItins itins = DEFAULT_ITINS> {
6947 let isCommutable = 1 in
6948 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6949 (ins RC:$src1, RC:$src2, u8imm:$src3),
6951 !strconcat(OpcodeStr,
6952 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6953 !strconcat(OpcodeStr,
6954 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6955 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6956 Sched<[itins.Sched]>;
6957 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6958 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6960 !strconcat(OpcodeStr,
6961 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6962 !strconcat(OpcodeStr,
6963 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6966 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6967 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6970 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6971 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6972 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6973 X86MemOperand x86memop, bit Is2Addr = 1,
6974 OpndItins itins = DEFAULT_ITINS> {
6975 let isCommutable = 1 in
6976 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6977 (ins RC:$src1, RC:$src2, u8imm:$src3),
6979 !strconcat(OpcodeStr,
6980 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6981 !strconcat(OpcodeStr,
6982 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6983 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
6984 itins.rr>, Sched<[itins.Sched]>;
6985 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6986 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6988 !strconcat(OpcodeStr,
6989 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6990 !strconcat(OpcodeStr,
6991 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6993 (OpVT (OpNode RC:$src1,
6994 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
6995 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6998 let Predicates = [HasAVX] in {
6999 let isCommutable = 0 in {
7000 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7001 VR128, loadv2i64, i128mem, 0,
7002 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7005 let ExeDomain = SSEPackedSingle in {
7006 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
7007 VR128, loadv4f32, f128mem, 0,
7008 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7009 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
7010 VR256, loadv8f32, f256mem, 0,
7011 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7013 let ExeDomain = SSEPackedDouble in {
7014 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
7015 VR128, loadv2f64, f128mem, 0,
7016 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7017 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
7018 VR256, loadv4f64, f256mem, 0,
7019 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7021 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
7022 VR128, loadv2i64, i128mem, 0,
7023 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7025 let ExeDomain = SSEPackedSingle in
7026 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7027 VR128, loadv4f32, f128mem, 0,
7028 SSE_DPPS_ITINS>, VEX_4V;
7029 let ExeDomain = SSEPackedDouble in
7030 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7031 VR128, loadv2f64, f128mem, 0,
7032 SSE_DPPS_ITINS>, VEX_4V;
7033 let ExeDomain = SSEPackedSingle in
7034 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7035 VR256, loadv8f32, i256mem, 0,
7036 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7039 let Predicates = [HasAVX2] in {
7040 let isCommutable = 0 in {
7041 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7042 VR256, loadv4i64, i256mem, 0,
7043 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7045 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
7046 VR256, loadv4i64, i256mem, 0,
7047 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7050 let Constraints = "$src1 = $dst" in {
7051 let isCommutable = 0 in {
7052 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7053 VR128, memopv2i64, i128mem,
7054 1, SSE_MPSADBW_ITINS>;
7056 let ExeDomain = SSEPackedSingle in
7057 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7058 VR128, memopv4f32, f128mem,
7059 1, SSE_INTALU_ITINS_FBLEND_P>;
7060 let ExeDomain = SSEPackedDouble in
7061 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7062 VR128, memopv2f64, f128mem,
7063 1, SSE_INTALU_ITINS_FBLEND_P>;
7064 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7065 VR128, memopv2i64, i128mem,
7066 1, SSE_INTALU_ITINS_BLEND_P>;
7067 let ExeDomain = SSEPackedSingle in
7068 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7069 VR128, memopv4f32, f128mem, 1,
7071 let ExeDomain = SSEPackedDouble in
7072 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7073 VR128, memopv2f64, f128mem, 1,
7077 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7078 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7079 RegisterClass RC, X86MemOperand x86memop,
7080 PatFrag mem_frag, Intrinsic IntId,
7081 X86FoldableSchedWrite Sched> {
7082 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7083 (ins RC:$src1, RC:$src2, RC:$src3),
7084 !strconcat(OpcodeStr,
7085 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7086 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7087 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7090 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7091 (ins RC:$src1, x86memop:$src2, RC:$src3),
7092 !strconcat(OpcodeStr,
7093 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7095 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7097 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7098 Sched<[Sched.Folded, ReadAfterLd]>;
7101 let Predicates = [HasAVX] in {
7102 let ExeDomain = SSEPackedDouble in {
7103 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7104 loadv2f64, int_x86_sse41_blendvpd,
7106 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7107 loadv4f64, int_x86_avx_blendv_pd_256,
7108 WriteFVarBlend>, VEX_L;
7109 } // ExeDomain = SSEPackedDouble
7110 let ExeDomain = SSEPackedSingle in {
7111 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7112 loadv4f32, int_x86_sse41_blendvps,
7114 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7115 loadv8f32, int_x86_avx_blendv_ps_256,
7116 WriteFVarBlend>, VEX_L;
7117 } // ExeDomain = SSEPackedSingle
7118 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7119 loadv2i64, int_x86_sse41_pblendvb,
7123 let Predicates = [HasAVX2] in {
7124 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7125 loadv4i64, int_x86_avx2_pblendvb,
7126 WriteVarBlend>, VEX_L;
7129 let Predicates = [HasAVX] in {
7130 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7131 (v16i8 VR128:$src2))),
7132 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7133 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7134 (v4i32 VR128:$src2))),
7135 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7136 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7137 (v4f32 VR128:$src2))),
7138 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7139 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7140 (v2i64 VR128:$src2))),
7141 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7142 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7143 (v2f64 VR128:$src2))),
7144 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7145 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7146 (v8i32 VR256:$src2))),
7147 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7148 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7149 (v8f32 VR256:$src2))),
7150 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7151 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7152 (v4i64 VR256:$src2))),
7153 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7154 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7155 (v4f64 VR256:$src2))),
7156 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7159 let Predicates = [HasAVX2] in {
7160 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7161 (v32i8 VR256:$src2))),
7162 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7166 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7167 // on targets where they have equal performance. These were changed to use
7168 // blends because blends have better throughput on SandyBridge and Haswell, but
7169 // movs[s/d] are 1-2 byte shorter instructions.
7170 let Predicates = [UseAVX] in {
7171 let AddedComplexity = 15 in {
7172 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7173 // MOVS{S,D} to the lower bits.
7174 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7175 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7176 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7177 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7178 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7179 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7180 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7181 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7183 // Move low f32 and clear high bits.
7184 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7185 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7187 // Move low f64 and clear high bits.
7188 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7189 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7192 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7193 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7194 (SUBREG_TO_REG (i32 0),
7195 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7197 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7198 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7199 (SUBREG_TO_REG (i64 0),
7200 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7203 // These will incur an FP/int domain crossing penalty, but it may be the only
7204 // way without AVX2. Do not add any complexity because we may be able to match
7205 // more optimal patterns defined earlier in this file.
7206 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7207 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7208 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7209 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7212 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7213 // on targets where they have equal performance. These were changed to use
7214 // blends because blends have better throughput on SandyBridge and Haswell, but
7215 // movs[s/d] are 1-2 byte shorter instructions.
7216 let Predicates = [UseSSE41] in {
7217 // With SSE41 we can use blends for these patterns.
7218 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7219 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7220 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7221 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7222 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7223 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7227 /// SS41I_ternary_int - SSE 4.1 ternary operator
7228 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7229 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7230 X86MemOperand x86memop, Intrinsic IntId,
7231 OpndItins itins = DEFAULT_ITINS> {
7232 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7233 (ins VR128:$src1, VR128:$src2),
7234 !strconcat(OpcodeStr,
7235 "\t{$src2, $dst|$dst, $src2}"),
7236 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7237 itins.rr>, Sched<[itins.Sched]>;
7239 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7240 (ins VR128:$src1, x86memop:$src2),
7241 !strconcat(OpcodeStr,
7242 "\t{$src2, $dst|$dst, $src2}"),
7245 (bitconvert (mem_frag addr:$src2)), XMM0))],
7246 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7250 let ExeDomain = SSEPackedDouble in
7251 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7252 int_x86_sse41_blendvpd,
7253 DEFAULT_ITINS_FBLENDSCHED>;
7254 let ExeDomain = SSEPackedSingle in
7255 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7256 int_x86_sse41_blendvps,
7257 DEFAULT_ITINS_FBLENDSCHED>;
7258 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7259 int_x86_sse41_pblendvb,
7260 DEFAULT_ITINS_VARBLENDSCHED>;
7262 // Aliases with the implicit xmm0 argument
7263 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7264 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7265 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7266 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7267 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7268 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7269 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7270 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7271 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7272 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7273 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7274 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7276 let Predicates = [UseSSE41] in {
7277 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7278 (v16i8 VR128:$src2))),
7279 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7280 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7281 (v4i32 VR128:$src2))),
7282 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7283 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7284 (v4f32 VR128:$src2))),
7285 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7286 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7287 (v2i64 VR128:$src2))),
7288 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7289 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7290 (v2f64 VR128:$src2))),
7291 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7294 let SchedRW = [WriteLoad] in {
7295 let Predicates = [HasAVX] in
7296 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7297 "vmovntdqa\t{$src, $dst|$dst, $src}",
7298 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7300 let Predicates = [HasAVX2] in
7301 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7302 "vmovntdqa\t{$src, $dst|$dst, $src}",
7303 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7305 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7306 "movntdqa\t{$src, $dst|$dst, $src}",
7307 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7310 //===----------------------------------------------------------------------===//
7311 // SSE4.2 - Compare Instructions
7312 //===----------------------------------------------------------------------===//
7314 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7315 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7316 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7317 X86MemOperand x86memop, bit Is2Addr = 1> {
7318 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7319 (ins RC:$src1, RC:$src2),
7321 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7322 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7323 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7324 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7325 (ins RC:$src1, x86memop:$src2),
7327 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7328 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7330 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7333 let Predicates = [HasAVX] in
7334 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7335 loadv2i64, i128mem, 0>, VEX_4V;
7337 let Predicates = [HasAVX2] in
7338 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7339 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7341 let Constraints = "$src1 = $dst" in
7342 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7343 memopv2i64, i128mem>;
7345 //===----------------------------------------------------------------------===//
7346 // SSE4.2 - String/text Processing Instructions
7347 //===----------------------------------------------------------------------===//
7349 // Packed Compare Implicit Length Strings, Return Mask
7350 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7351 def REG : PseudoI<(outs VR128:$dst),
7352 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7353 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7355 def MEM : PseudoI<(outs VR128:$dst),
7356 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7357 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7358 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7361 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7362 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7364 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7365 Requires<[UseSSE42]>;
7368 multiclass pcmpistrm_SS42AI<string asm> {
7369 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7370 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7371 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7372 []>, Sched<[WritePCmpIStrM]>;
7374 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7375 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7376 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7377 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7380 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7381 let Predicates = [HasAVX] in
7382 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7383 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7386 // Packed Compare Explicit Length Strings, Return Mask
7387 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7388 def REG : PseudoI<(outs VR128:$dst),
7389 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7390 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7391 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7392 def MEM : PseudoI<(outs VR128:$dst),
7393 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7394 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7395 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7398 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7399 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7401 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7402 Requires<[UseSSE42]>;
7405 multiclass SS42AI_pcmpestrm<string asm> {
7406 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7407 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7408 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7409 []>, Sched<[WritePCmpEStrM]>;
7411 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7412 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7413 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7414 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7417 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7418 let Predicates = [HasAVX] in
7419 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7420 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7423 // Packed Compare Implicit Length Strings, Return Index
7424 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7425 def REG : PseudoI<(outs GR32:$dst),
7426 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7427 [(set GR32:$dst, EFLAGS,
7428 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7429 def MEM : PseudoI<(outs GR32:$dst),
7430 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7431 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7432 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7435 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7436 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7438 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7439 Requires<[UseSSE42]>;
7442 multiclass SS42AI_pcmpistri<string asm> {
7443 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7444 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7445 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7446 []>, Sched<[WritePCmpIStrI]>;
7448 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7449 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7450 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7451 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7454 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7455 let Predicates = [HasAVX] in
7456 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7457 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7460 // Packed Compare Explicit Length Strings, Return Index
7461 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7462 def REG : PseudoI<(outs GR32:$dst),
7463 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7464 [(set GR32:$dst, EFLAGS,
7465 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7466 def MEM : PseudoI<(outs GR32:$dst),
7467 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7468 [(set GR32:$dst, EFLAGS,
7469 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7473 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7474 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7476 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7477 Requires<[UseSSE42]>;
7480 multiclass SS42AI_pcmpestri<string asm> {
7481 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7482 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7483 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7484 []>, Sched<[WritePCmpEStrI]>;
7486 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7487 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7488 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7489 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7492 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7493 let Predicates = [HasAVX] in
7494 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7495 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7498 //===----------------------------------------------------------------------===//
7499 // SSE4.2 - CRC Instructions
7500 //===----------------------------------------------------------------------===//
7502 // No CRC instructions have AVX equivalents
7504 // crc intrinsic instruction
7505 // This set of instructions are only rm, the only difference is the size
7507 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7508 RegisterClass RCIn, SDPatternOperator Int> :
7509 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7510 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7511 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7514 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7515 X86MemOperand x86memop, SDPatternOperator Int> :
7516 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7517 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7518 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7519 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7521 let Constraints = "$src1 = $dst" in {
7522 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7523 int_x86_sse42_crc32_32_8>;
7524 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7525 int_x86_sse42_crc32_32_8>;
7526 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7527 int_x86_sse42_crc32_32_16>, OpSize16;
7528 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7529 int_x86_sse42_crc32_32_16>, OpSize16;
7530 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7531 int_x86_sse42_crc32_32_32>, OpSize32;
7532 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7533 int_x86_sse42_crc32_32_32>, OpSize32;
7534 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7535 int_x86_sse42_crc32_64_64>, REX_W;
7536 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7537 int_x86_sse42_crc32_64_64>, REX_W;
7538 let hasSideEffects = 0 in {
7540 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7542 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7547 //===----------------------------------------------------------------------===//
7548 // SHA-NI Instructions
7549 //===----------------------------------------------------------------------===//
7551 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7553 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7554 (ins VR128:$src1, VR128:$src2),
7555 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7557 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7558 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7560 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7561 (ins VR128:$src1, i128mem:$src2),
7562 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7564 (set VR128:$dst, (IntId VR128:$src1,
7565 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7566 (set VR128:$dst, (IntId VR128:$src1,
7567 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7570 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7571 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7572 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7573 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7575 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7576 (i8 imm:$src3)))]>, TA;
7577 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7578 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7579 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7581 (int_x86_sha1rnds4 VR128:$src1,
7582 (bc_v4i32 (memopv2i64 addr:$src2)),
7583 (i8 imm:$src3)))]>, TA;
7585 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7586 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7587 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7590 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7592 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7593 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7596 // Aliases with explicit %xmm0
7597 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7598 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7599 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7600 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7602 //===----------------------------------------------------------------------===//
7603 // AES-NI Instructions
7604 //===----------------------------------------------------------------------===//
7606 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7607 PatFrag ld_frag, bit Is2Addr = 1> {
7608 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7609 (ins VR128:$src1, VR128:$src2),
7611 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7612 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7613 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7614 Sched<[WriteAESDecEnc]>;
7615 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7616 (ins VR128:$src1, i128mem:$src2),
7618 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7619 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7621 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7622 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7625 // Perform One Round of an AES Encryption/Decryption Flow
7626 let Predicates = [HasAVX, HasAES] in {
7627 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7628 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7629 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7630 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7631 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7632 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7633 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7634 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7637 let Constraints = "$src1 = $dst" in {
7638 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7639 int_x86_aesni_aesenc, memopv2i64>;
7640 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7641 int_x86_aesni_aesenclast, memopv2i64>;
7642 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7643 int_x86_aesni_aesdec, memopv2i64>;
7644 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7645 int_x86_aesni_aesdeclast, memopv2i64>;
7648 // Perform the AES InvMixColumn Transformation
7649 let Predicates = [HasAVX, HasAES] in {
7650 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7652 "vaesimc\t{$src1, $dst|$dst, $src1}",
7654 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7656 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7657 (ins i128mem:$src1),
7658 "vaesimc\t{$src1, $dst|$dst, $src1}",
7659 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7660 Sched<[WriteAESIMCLd]>, VEX;
7662 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7664 "aesimc\t{$src1, $dst|$dst, $src1}",
7666 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7667 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7668 (ins i128mem:$src1),
7669 "aesimc\t{$src1, $dst|$dst, $src1}",
7670 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7671 Sched<[WriteAESIMCLd]>;
7673 // AES Round Key Generation Assist
7674 let Predicates = [HasAVX, HasAES] in {
7675 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7676 (ins VR128:$src1, u8imm:$src2),
7677 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7679 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7680 Sched<[WriteAESKeyGen]>, VEX;
7681 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7682 (ins i128mem:$src1, u8imm:$src2),
7683 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7685 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7686 Sched<[WriteAESKeyGenLd]>, VEX;
7688 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7689 (ins VR128:$src1, u8imm:$src2),
7690 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7692 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7693 Sched<[WriteAESKeyGen]>;
7694 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7695 (ins i128mem:$src1, u8imm:$src2),
7696 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7698 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7699 Sched<[WriteAESKeyGenLd]>;
7701 //===----------------------------------------------------------------------===//
7702 // PCLMUL Instructions
7703 //===----------------------------------------------------------------------===//
7705 // AVX carry-less Multiplication instructions
7706 let isCommutable = 1 in
7707 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7708 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7709 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7711 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7712 Sched<[WriteCLMul]>;
7714 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7715 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7716 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7717 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7718 (loadv2i64 addr:$src2), imm:$src3))]>,
7719 Sched<[WriteCLMulLd, ReadAfterLd]>;
7721 // Carry-less Multiplication instructions
7722 let Constraints = "$src1 = $dst" in {
7723 let isCommutable = 1 in
7724 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7725 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7726 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7728 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7729 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7731 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7732 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7733 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7734 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7735 (memopv2i64 addr:$src2), imm:$src3))],
7736 IIC_SSE_PCLMULQDQ_RM>,
7737 Sched<[WriteCLMulLd, ReadAfterLd]>;
7738 } // Constraints = "$src1 = $dst"
7741 multiclass pclmul_alias<string asm, int immop> {
7742 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7743 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7745 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7746 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7748 def : InstAlias<!strconcat("vpclmul", asm,
7749 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7750 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7753 def : InstAlias<!strconcat("vpclmul", asm,
7754 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7755 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7758 defm : pclmul_alias<"hqhq", 0x11>;
7759 defm : pclmul_alias<"hqlq", 0x01>;
7760 defm : pclmul_alias<"lqhq", 0x10>;
7761 defm : pclmul_alias<"lqlq", 0x00>;
7763 //===----------------------------------------------------------------------===//
7764 // SSE4A Instructions
7765 //===----------------------------------------------------------------------===//
7767 let Predicates = [HasSSE4A] in {
7769 let Constraints = "$src = $dst" in {
7770 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7771 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7772 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7773 [(set VR128:$dst, (X86extrqi VR128:$src, imm:$len,
7775 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7776 (ins VR128:$src, VR128:$mask),
7777 "extrq\t{$mask, $src|$src, $mask}",
7778 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7779 VR128:$mask))]>, PD;
7781 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7782 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7783 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7784 [(set VR128:$dst, (X86insertqi VR128:$src, VR128:$src2,
7785 imm:$len, imm:$idx))]>, XD;
7786 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7787 (ins VR128:$src, VR128:$mask),
7788 "insertq\t{$mask, $src|$src, $mask}",
7789 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7790 VR128:$mask))]>, XD;
7793 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7794 "movntss\t{$src, $dst|$dst, $src}",
7795 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7797 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7798 "movntsd\t{$src, $dst|$dst, $src}",
7799 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7802 //===----------------------------------------------------------------------===//
7804 //===----------------------------------------------------------------------===//
7806 //===----------------------------------------------------------------------===//
7807 // VBROADCAST - Load from memory and broadcast to all elements of the
7808 // destination operand
7810 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7811 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
7812 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7813 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7814 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
7816 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
7817 X86MemOperand x86memop, ValueType VT,
7818 PatFrag ld_frag, SchedWrite Sched> :
7819 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7820 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7821 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7822 Sched<[Sched]>, VEX {
7826 // AVX2 adds register forms
7827 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7828 Intrinsic Int, SchedWrite Sched> :
7829 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7830 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7831 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
7833 let ExeDomain = SSEPackedSingle in {
7834 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
7835 f32mem, v4f32, loadf32, WriteLoad>;
7836 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
7837 f32mem, v8f32, loadf32,
7838 WriteFShuffleLd>, VEX_L;
7840 let ExeDomain = SSEPackedDouble in
7841 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
7842 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7843 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7844 int_x86_avx_vbroadcastf128_pd_256,
7845 WriteFShuffleLd>, VEX_L;
7847 let ExeDomain = SSEPackedSingle in {
7848 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7849 int_x86_avx2_vbroadcast_ss_ps,
7851 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7852 int_x86_avx2_vbroadcast_ss_ps_256,
7853 WriteFShuffle256>, VEX_L;
7855 let ExeDomain = SSEPackedDouble in
7856 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7857 int_x86_avx2_vbroadcast_sd_pd_256,
7858 WriteFShuffle256>, VEX_L;
7860 let mayLoad = 1, Predicates = [HasAVX2] in
7861 def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
7863 "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
7864 Sched<[WriteLoad]>, VEX, VEX_L;
7866 let Predicates = [HasAVX] in
7867 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7868 (VBROADCASTF128 addr:$src)>;
7871 //===----------------------------------------------------------------------===//
7872 // VINSERTF128 - Insert packed floating-point values
7874 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7875 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7876 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7877 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7878 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7880 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7881 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7882 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7883 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7886 let Predicates = [HasAVX] in {
7887 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7889 (VINSERTF128rr VR256:$src1, VR128:$src2,
7890 (INSERT_get_vinsert128_imm VR256:$ins))>;
7891 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7893 (VINSERTF128rr VR256:$src1, VR128:$src2,
7894 (INSERT_get_vinsert128_imm VR256:$ins))>;
7896 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7898 (VINSERTF128rm VR256:$src1, addr:$src2,
7899 (INSERT_get_vinsert128_imm VR256:$ins))>;
7900 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7902 (VINSERTF128rm VR256:$src1, addr:$src2,
7903 (INSERT_get_vinsert128_imm VR256:$ins))>;
7906 let Predicates = [HasAVX1Only] in {
7907 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7909 (VINSERTF128rr VR256:$src1, VR128:$src2,
7910 (INSERT_get_vinsert128_imm VR256:$ins))>;
7911 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7913 (VINSERTF128rr VR256:$src1, VR128:$src2,
7914 (INSERT_get_vinsert128_imm VR256:$ins))>;
7915 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7917 (VINSERTF128rr VR256:$src1, VR128:$src2,
7918 (INSERT_get_vinsert128_imm VR256:$ins))>;
7919 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7921 (VINSERTF128rr VR256:$src1, VR128:$src2,
7922 (INSERT_get_vinsert128_imm VR256:$ins))>;
7924 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7926 (VINSERTF128rm VR256:$src1, addr:$src2,
7927 (INSERT_get_vinsert128_imm VR256:$ins))>;
7928 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7929 (bc_v4i32 (loadv2i64 addr:$src2)),
7931 (VINSERTF128rm VR256:$src1, addr:$src2,
7932 (INSERT_get_vinsert128_imm VR256:$ins))>;
7933 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7934 (bc_v16i8 (loadv2i64 addr:$src2)),
7936 (VINSERTF128rm VR256:$src1, addr:$src2,
7937 (INSERT_get_vinsert128_imm VR256:$ins))>;
7938 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7939 (bc_v8i16 (loadv2i64 addr:$src2)),
7941 (VINSERTF128rm VR256:$src1, addr:$src2,
7942 (INSERT_get_vinsert128_imm VR256:$ins))>;
7945 //===----------------------------------------------------------------------===//
7946 // VEXTRACTF128 - Extract packed floating-point values
7948 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7949 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7950 (ins VR256:$src1, u8imm:$src2),
7951 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7952 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7954 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7955 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7956 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7957 []>, Sched<[WriteStore]>, VEX, VEX_L;
7961 let Predicates = [HasAVX] in {
7962 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7963 (v4f32 (VEXTRACTF128rr
7964 (v8f32 VR256:$src1),
7965 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7966 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7967 (v2f64 (VEXTRACTF128rr
7968 (v4f64 VR256:$src1),
7969 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7971 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7972 (iPTR imm))), addr:$dst),
7973 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7974 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7975 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7976 (iPTR imm))), addr:$dst),
7977 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7978 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7981 let Predicates = [HasAVX1Only] in {
7982 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7983 (v2i64 (VEXTRACTF128rr
7984 (v4i64 VR256:$src1),
7985 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7986 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7987 (v4i32 (VEXTRACTF128rr
7988 (v8i32 VR256:$src1),
7989 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7990 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7991 (v8i16 (VEXTRACTF128rr
7992 (v16i16 VR256:$src1),
7993 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7994 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7995 (v16i8 (VEXTRACTF128rr
7996 (v32i8 VR256:$src1),
7997 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7999 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8000 (iPTR imm))), addr:$dst),
8001 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8002 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8003 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8004 (iPTR imm))), addr:$dst),
8005 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8006 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8007 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8008 (iPTR imm))), addr:$dst),
8009 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8010 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8011 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8012 (iPTR imm))), addr:$dst),
8013 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8014 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8017 //===----------------------------------------------------------------------===//
8018 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8020 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8021 Intrinsic IntLd, Intrinsic IntLd256,
8022 Intrinsic IntSt, Intrinsic IntSt256> {
8023 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8024 (ins VR128:$src1, f128mem:$src2),
8025 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8026 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8028 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8029 (ins VR256:$src1, f256mem:$src2),
8030 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8031 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8033 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8034 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8035 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8036 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8037 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8038 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8039 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8040 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8043 let ExeDomain = SSEPackedSingle in
8044 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8045 int_x86_avx_maskload_ps,
8046 int_x86_avx_maskload_ps_256,
8047 int_x86_avx_maskstore_ps,
8048 int_x86_avx_maskstore_ps_256>;
8049 let ExeDomain = SSEPackedDouble in
8050 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8051 int_x86_avx_maskload_pd,
8052 int_x86_avx_maskload_pd_256,
8053 int_x86_avx_maskstore_pd,
8054 int_x86_avx_maskstore_pd_256>;
8056 //===----------------------------------------------------------------------===//
8057 // VPERMIL - Permute Single and Double Floating-Point Values
8059 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8060 RegisterClass RC, X86MemOperand x86memop_f,
8061 X86MemOperand x86memop_i, PatFrag i_frag,
8062 Intrinsic IntVar, ValueType vt> {
8063 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8064 (ins RC:$src1, RC:$src2),
8065 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8066 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8067 Sched<[WriteFShuffle]>;
8068 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8069 (ins RC:$src1, x86memop_i:$src2),
8070 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8071 [(set RC:$dst, (IntVar RC:$src1,
8072 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8073 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8075 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8076 (ins RC:$src1, u8imm:$src2),
8077 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8078 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8079 Sched<[WriteFShuffle]>;
8080 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8081 (ins x86memop_f:$src1, u8imm:$src2),
8082 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8084 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8085 Sched<[WriteFShuffleLd]>;
8088 let ExeDomain = SSEPackedSingle in {
8089 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8090 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8091 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8092 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8094 let ExeDomain = SSEPackedDouble in {
8095 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8096 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8097 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8098 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8101 let Predicates = [HasAVX] in {
8102 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8103 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8104 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8105 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8106 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8107 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8108 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8109 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8111 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8112 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8113 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8114 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8115 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8117 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8118 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8119 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8121 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8122 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8123 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8124 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8125 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8126 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8127 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8128 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8130 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8131 (VPERMILPDri VR128:$src1, imm:$imm)>;
8132 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8133 (VPERMILPDmi addr:$src1, imm:$imm)>;
8136 //===----------------------------------------------------------------------===//
8137 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8139 let ExeDomain = SSEPackedSingle in {
8140 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8141 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8142 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8143 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8144 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8145 Sched<[WriteFShuffle]>;
8146 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8147 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8148 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8149 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8150 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8151 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8154 let Predicates = [HasAVX] in {
8155 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8156 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8157 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8158 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8159 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8162 let Predicates = [HasAVX1Only] in {
8163 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8164 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8165 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8166 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8167 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8168 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8169 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8170 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8172 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8173 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8174 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8175 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8176 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8177 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8178 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8179 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8180 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8181 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8182 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8183 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8186 //===----------------------------------------------------------------------===//
8187 // VZERO - Zero YMM registers
8189 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8190 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8191 // Zero All YMM registers
8192 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8193 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8195 // Zero Upper bits of YMM registers
8196 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8197 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8200 //===----------------------------------------------------------------------===//
8201 // Half precision conversion instructions
8202 //===----------------------------------------------------------------------===//
8203 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8204 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8205 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8206 [(set RC:$dst, (Int VR128:$src))]>,
8207 T8PD, VEX, Sched<[WriteCvtF2F]>;
8208 let hasSideEffects = 0, mayLoad = 1 in
8209 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8210 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8211 Sched<[WriteCvtF2FLd]>;
8214 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8215 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8216 (ins RC:$src1, i32u8imm:$src2),
8217 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8218 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8219 TAPD, VEX, Sched<[WriteCvtF2F]>;
8220 let hasSideEffects = 0, mayStore = 1,
8221 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8222 def mr : Ii8<0x1D, MRMDestMem, (outs),
8223 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8224 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8228 let Predicates = [HasF16C] in {
8229 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8230 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8231 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8232 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8234 // Pattern match vcvtph2ps of a scalar i64 load.
8235 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8236 (VCVTPH2PSrm addr:$src)>;
8237 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8238 (VCVTPH2PSrm addr:$src)>;
8240 def : Pat<(store (f64 (vector_extract (bc_v2f64 (v8i16
8241 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8243 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8244 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v8i16
8245 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8247 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8248 def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
8250 (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
8253 // Patterns for matching conversions from float to half-float and vice versa.
8254 let Predicates = [HasF16C] in {
8255 def : Pat<(fp_to_f16 FR32:$src),
8256 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8257 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8259 def : Pat<(f16_to_fp GR16:$src),
8260 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8261 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8263 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8264 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8265 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8268 //===----------------------------------------------------------------------===//
8269 // AVX2 Instructions
8270 //===----------------------------------------------------------------------===//
8272 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8273 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8274 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8275 X86MemOperand x86memop> {
8276 let isCommutable = 1 in
8277 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8278 (ins RC:$src1, RC:$src2, u8imm:$src3),
8279 !strconcat(OpcodeStr,
8280 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8281 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8282 Sched<[WriteBlend]>, VEX_4V;
8283 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8284 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8285 !strconcat(OpcodeStr,
8286 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8288 (OpVT (OpNode RC:$src1,
8289 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8290 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8293 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8294 VR128, loadv2i64, i128mem>;
8295 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8296 VR256, loadv4i64, i256mem>, VEX_L;
8298 //===----------------------------------------------------------------------===//
8299 // VPBROADCAST - Load from memory and broadcast to all elements of the
8300 // destination operand
8302 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8303 X86MemOperand x86memop, PatFrag ld_frag,
8304 Intrinsic Int128, Intrinsic Int256> {
8305 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8306 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8307 [(set VR128:$dst, (Int128 VR128:$src))]>,
8308 Sched<[WriteShuffle]>, VEX;
8309 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8310 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8312 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8313 Sched<[WriteLoad]>, VEX;
8314 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8315 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8316 [(set VR256:$dst, (Int256 VR128:$src))]>,
8317 Sched<[WriteShuffle256]>, VEX, VEX_L;
8318 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8319 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8321 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8322 Sched<[WriteLoad]>, VEX, VEX_L;
8325 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8326 int_x86_avx2_pbroadcastb_128,
8327 int_x86_avx2_pbroadcastb_256>;
8328 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8329 int_x86_avx2_pbroadcastw_128,
8330 int_x86_avx2_pbroadcastw_256>;
8331 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8332 int_x86_avx2_pbroadcastd_128,
8333 int_x86_avx2_pbroadcastd_256>;
8334 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8335 int_x86_avx2_pbroadcastq_128,
8336 int_x86_avx2_pbroadcastq_256>;
8338 let Predicates = [HasAVX2] in {
8339 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8340 (VPBROADCASTBrm addr:$src)>;
8341 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8342 (VPBROADCASTBYrm addr:$src)>;
8343 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8344 (VPBROADCASTWrm addr:$src)>;
8345 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8346 (VPBROADCASTWYrm addr:$src)>;
8347 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8348 (VPBROADCASTDrm addr:$src)>;
8349 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8350 (VPBROADCASTDYrm addr:$src)>;
8351 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8352 (VPBROADCASTQrm addr:$src)>;
8353 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8354 (VPBROADCASTQYrm addr:$src)>;
8356 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8357 (VPBROADCASTBrr VR128:$src)>;
8358 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8359 (VPBROADCASTBYrr VR128:$src)>;
8360 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8361 (VPBROADCASTWrr VR128:$src)>;
8362 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8363 (VPBROADCASTWYrr VR128:$src)>;
8364 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8365 (VPBROADCASTDrr VR128:$src)>;
8366 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8367 (VPBROADCASTDYrr VR128:$src)>;
8368 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8369 (VPBROADCASTQrr VR128:$src)>;
8370 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8371 (VPBROADCASTQYrr VR128:$src)>;
8372 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8373 (VBROADCASTSSrr VR128:$src)>;
8374 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8375 (VBROADCASTSSYrr VR128:$src)>;
8376 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8377 (VPBROADCASTQrr VR128:$src)>;
8378 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8379 (VBROADCASTSDYrr VR128:$src)>;
8381 // Provide aliases for broadcast from the same register class that
8382 // automatically does the extract.
8383 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8384 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8386 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8387 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8389 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8390 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8392 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8393 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8395 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8396 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8398 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8399 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8402 // Provide fallback in case the load node that is used in the patterns above
8403 // is used by additional users, which prevents the pattern selection.
8404 let AddedComplexity = 20 in {
8405 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8406 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8407 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8408 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8409 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8410 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8412 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8413 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8414 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8415 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8416 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8417 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8419 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8420 (VPBROADCASTBrr (COPY_TO_REGCLASS
8421 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8423 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8424 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8425 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8428 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8429 (VPBROADCASTWrr (COPY_TO_REGCLASS
8430 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8432 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8433 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8434 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8437 // The patterns for VPBROADCASTD are not needed because they would match
8438 // the exact same thing as VBROADCASTSS patterns.
8440 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8441 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8442 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8446 // AVX1 broadcast patterns
8447 let Predicates = [HasAVX1Only] in {
8448 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8449 (VBROADCASTSSYrm addr:$src)>;
8450 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8451 (VBROADCASTSDYrm addr:$src)>;
8452 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8453 (VBROADCASTSSrm addr:$src)>;
8456 let Predicates = [HasAVX] in {
8457 // Provide fallback in case the load node that is used in the patterns above
8458 // is used by additional users, which prevents the pattern selection.
8459 let AddedComplexity = 20 in {
8460 // 128bit broadcasts:
8461 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8462 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8463 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8464 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8465 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8466 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8467 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8468 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8469 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8470 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8472 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8473 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8474 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8475 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8476 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8477 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8478 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8479 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8480 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8481 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8484 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8485 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8486 def : Pat<(v2i64 (X86VBroadcast i64:$src)),
8487 (VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8490 //===----------------------------------------------------------------------===//
8491 // VPERM - Permute instructions
8494 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8495 ValueType OpVT, X86FoldableSchedWrite Sched> {
8496 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8497 (ins VR256:$src1, VR256:$src2),
8498 !strconcat(OpcodeStr,
8499 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8501 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8502 Sched<[Sched]>, VEX_4V, VEX_L;
8503 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8504 (ins VR256:$src1, i256mem:$src2),
8505 !strconcat(OpcodeStr,
8506 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8508 (OpVT (X86VPermv VR256:$src1,
8509 (bitconvert (mem_frag addr:$src2)))))]>,
8510 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8513 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8514 let ExeDomain = SSEPackedSingle in
8515 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8517 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8518 ValueType OpVT, X86FoldableSchedWrite Sched> {
8519 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8520 (ins VR256:$src1, u8imm:$src2),
8521 !strconcat(OpcodeStr,
8522 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8524 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8525 Sched<[Sched]>, VEX, VEX_L;
8526 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8527 (ins i256mem:$src1, u8imm:$src2),
8528 !strconcat(OpcodeStr,
8529 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8531 (OpVT (X86VPermi (mem_frag addr:$src1),
8532 (i8 imm:$src2))))]>,
8533 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8536 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8537 WriteShuffle256>, VEX_W;
8538 let ExeDomain = SSEPackedDouble in
8539 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8540 WriteFShuffle256>, VEX_W;
8542 //===----------------------------------------------------------------------===//
8543 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8545 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8546 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8547 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8548 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8549 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8551 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8552 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8553 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8554 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8556 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8558 let Predicates = [HasAVX2] in {
8559 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8560 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8561 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8562 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8563 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8564 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8566 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8568 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8569 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8570 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8571 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8572 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8574 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8578 //===----------------------------------------------------------------------===//
8579 // VINSERTI128 - Insert packed integer values
8581 let hasSideEffects = 0 in {
8582 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8583 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8584 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8585 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8587 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8588 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8589 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8590 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8593 let Predicates = [HasAVX2] in {
8594 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8596 (VINSERTI128rr VR256:$src1, VR128:$src2,
8597 (INSERT_get_vinsert128_imm VR256:$ins))>;
8598 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8600 (VINSERTI128rr VR256:$src1, VR128:$src2,
8601 (INSERT_get_vinsert128_imm VR256:$ins))>;
8602 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8604 (VINSERTI128rr VR256:$src1, VR128:$src2,
8605 (INSERT_get_vinsert128_imm VR256:$ins))>;
8606 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8608 (VINSERTI128rr VR256:$src1, VR128:$src2,
8609 (INSERT_get_vinsert128_imm VR256:$ins))>;
8611 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8613 (VINSERTI128rm VR256:$src1, addr:$src2,
8614 (INSERT_get_vinsert128_imm VR256:$ins))>;
8615 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8616 (bc_v4i32 (loadv2i64 addr:$src2)),
8618 (VINSERTI128rm VR256:$src1, addr:$src2,
8619 (INSERT_get_vinsert128_imm VR256:$ins))>;
8620 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8621 (bc_v16i8 (loadv2i64 addr:$src2)),
8623 (VINSERTI128rm VR256:$src1, addr:$src2,
8624 (INSERT_get_vinsert128_imm VR256:$ins))>;
8625 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8626 (bc_v8i16 (loadv2i64 addr:$src2)),
8628 (VINSERTI128rm VR256:$src1, addr:$src2,
8629 (INSERT_get_vinsert128_imm VR256:$ins))>;
8632 //===----------------------------------------------------------------------===//
8633 // VEXTRACTI128 - Extract packed integer values
8635 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8636 (ins VR256:$src1, u8imm:$src2),
8637 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8638 Sched<[WriteShuffle256]>, VEX, VEX_L;
8639 let hasSideEffects = 0, mayStore = 1 in
8640 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8641 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8642 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8643 Sched<[WriteStore]>, VEX, VEX_L;
8645 let Predicates = [HasAVX2] in {
8646 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8647 (v2i64 (VEXTRACTI128rr
8648 (v4i64 VR256:$src1),
8649 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8650 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8651 (v4i32 (VEXTRACTI128rr
8652 (v8i32 VR256:$src1),
8653 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8654 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8655 (v8i16 (VEXTRACTI128rr
8656 (v16i16 VR256:$src1),
8657 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8658 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8659 (v16i8 (VEXTRACTI128rr
8660 (v32i8 VR256:$src1),
8661 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8663 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8664 (iPTR imm))), addr:$dst),
8665 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8666 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8667 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8668 (iPTR imm))), addr:$dst),
8669 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8670 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8671 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8672 (iPTR imm))), addr:$dst),
8673 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8674 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8675 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8676 (iPTR imm))), addr:$dst),
8677 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8678 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8681 //===----------------------------------------------------------------------===//
8682 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8684 multiclass avx2_pmovmask<string OpcodeStr,
8685 Intrinsic IntLd128, Intrinsic IntLd256,
8686 Intrinsic IntSt128, Intrinsic IntSt256> {
8687 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8688 (ins VR128:$src1, i128mem:$src2),
8689 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8690 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8691 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8692 (ins VR256:$src1, i256mem:$src2),
8693 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8694 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8696 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8697 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8698 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8699 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8700 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8701 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8702 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8703 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8706 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8707 int_x86_avx2_maskload_d,
8708 int_x86_avx2_maskload_d_256,
8709 int_x86_avx2_maskstore_d,
8710 int_x86_avx2_maskstore_d_256>;
8711 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8712 int_x86_avx2_maskload_q,
8713 int_x86_avx2_maskload_q_256,
8714 int_x86_avx2_maskstore_q,
8715 int_x86_avx2_maskstore_q_256>, VEX_W;
8717 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8718 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8720 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8721 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8723 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8724 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8726 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8727 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8729 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8730 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8732 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8733 (bc_v8f32 (v8i32 immAllZerosV)))),
8734 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8736 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8737 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8740 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8741 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8743 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8744 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8746 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8747 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8750 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8751 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8753 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8754 (bc_v4f32 (v4i32 immAllZerosV)))),
8755 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8757 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8758 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8761 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8762 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8764 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8765 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8767 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8768 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8771 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8772 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8774 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8775 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8777 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8778 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8780 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8781 (v4f64 immAllZerosV))),
8782 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8784 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8785 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8788 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8789 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8791 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8792 (bc_v4i64 (v8i32 immAllZerosV)))),
8793 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8795 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8796 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8799 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8800 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8802 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8803 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8805 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8806 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8808 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8809 (v2f64 immAllZerosV))),
8810 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8812 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8813 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8816 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8817 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8819 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8820 (bc_v2i64 (v4i32 immAllZerosV)))),
8821 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8823 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8824 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8827 //===----------------------------------------------------------------------===//
8828 // Variable Bit Shifts
8830 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8831 ValueType vt128, ValueType vt256> {
8832 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8833 (ins VR128:$src1, VR128:$src2),
8834 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8836 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8837 VEX_4V, Sched<[WriteVarVecShift]>;
8838 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8839 (ins VR128:$src1, i128mem:$src2),
8840 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8842 (vt128 (OpNode VR128:$src1,
8843 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8844 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8845 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8846 (ins VR256:$src1, VR256:$src2),
8847 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8849 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8850 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8851 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8852 (ins VR256:$src1, i256mem:$src2),
8853 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8855 (vt256 (OpNode VR256:$src1,
8856 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8857 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8860 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8861 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8862 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8863 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8864 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8866 //===----------------------------------------------------------------------===//
8867 // VGATHER - GATHER Operations
8868 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8869 X86MemOperand memop128, X86MemOperand memop256> {
8870 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8871 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8872 !strconcat(OpcodeStr,
8873 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8875 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8876 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8877 !strconcat(OpcodeStr,
8878 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8879 []>, VEX_4VOp3, VEX_L;
8882 let mayLoad = 1, Constraints
8883 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8885 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8886 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8887 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8888 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8890 let ExeDomain = SSEPackedDouble in {
8891 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8892 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8895 let ExeDomain = SSEPackedSingle in {
8896 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8897 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;