1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 def SSE_BIT_ITINS_P : OpndItins<
124 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
127 let Sched = WriteVecALU in {
128 def SSE_INTALU_ITINS_P : OpndItins<
129 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
132 def SSE_INTALUQ_ITINS_P : OpndItins<
133 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
137 let Sched = WriteVecIMul in
138 def SSE_INTMUL_ITINS_P : OpndItins<
139 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
142 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
143 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
146 def SSE_MOVA_ITINS : OpndItins<
147 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
150 def SSE_MOVU_ITINS : OpndItins<
151 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
154 def SSE_DPPD_ITINS : OpndItins<
155 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
158 def SSE_DPPS_ITINS : OpndItins<
159 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
162 def DEFAULT_ITINS : OpndItins<
163 IIC_ALU_NONMEM, IIC_ALU_MEM
166 def SSE_EXTRACT_ITINS : OpndItins<
167 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
170 def SSE_INSERT_ITINS : OpndItins<
171 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
174 def SSE_MPSADBW_ITINS : OpndItins<
175 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
178 def SSE_PMULLD_ITINS : OpndItins<
179 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
182 //===----------------------------------------------------------------------===//
183 // SSE 1 & 2 Instructions Classes
184 //===----------------------------------------------------------------------===//
186 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
187 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
188 RegisterClass RC, X86MemOperand x86memop,
191 let isCommutable = 1 in {
192 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
194 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
196 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
197 Sched<[itins.Sched]>;
199 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
201 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
203 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
204 Sched<[itins.Sched.Folded, ReadAfterLd]>;
207 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
208 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
209 string asm, string SSEVer, string FPSizeStr,
210 Operand memopr, ComplexPattern mem_cpat,
213 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
215 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
216 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
217 [(set RC:$dst, (!cast<Intrinsic>(
218 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
219 RC:$src1, RC:$src2))], itins.rr>,
220 Sched<[itins.Sched]>;
221 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
223 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
224 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
225 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
226 SSEVer, "_", OpcodeStr, FPSizeStr))
227 RC:$src1, mem_cpat:$src2))], itins.rm>,
228 Sched<[itins.Sched.Folded, ReadAfterLd]>;
231 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
232 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
233 RegisterClass RC, ValueType vt,
234 X86MemOperand x86memop, PatFrag mem_frag,
235 Domain d, OpndItins itins, bit Is2Addr = 1> {
236 let isCommutable = 1 in
237 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
241 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
242 Sched<[itins.Sched]>;
244 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
246 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
247 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
248 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
250 Sched<[itins.Sched.Folded, ReadAfterLd]>;
253 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
254 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
255 string OpcodeStr, X86MemOperand x86memop,
256 list<dag> pat_rr, list<dag> pat_rm,
258 let isCommutable = 1, hasSideEffects = 0 in
259 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
261 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
262 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
263 pat_rr, NoItinerary, d>,
264 Sched<[WriteVecLogic]>;
265 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
267 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
269 pat_rm, NoItinerary, d>,
270 Sched<[WriteVecLogicLd, ReadAfterLd]>;
273 //===----------------------------------------------------------------------===//
274 // Non-instruction patterns
275 //===----------------------------------------------------------------------===//
277 // A vector extract of the first f32/f64 position is a subregister copy
278 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
279 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
280 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
281 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
283 // A 128-bit subvector extract from the first 256-bit vector position
284 // is a subregister copy that needs no instruction.
285 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
286 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
287 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
288 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
290 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
291 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
292 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
293 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
295 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
296 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
297 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
298 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
300 // A 128-bit subvector insert to the first 256-bit vector position
301 // is a subregister copy that needs no instruction.
302 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
303 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
304 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
305 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
306 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
307 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
308 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
309 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
310 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
311 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
312 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
313 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
314 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
317 // Implicitly promote a 32-bit scalar to a vector.
318 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
319 (COPY_TO_REGCLASS FR32:$src, VR128)>;
320 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
321 (COPY_TO_REGCLASS FR32:$src, VR128)>;
322 // Implicitly promote a 64-bit scalar to a vector.
323 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
324 (COPY_TO_REGCLASS FR64:$src, VR128)>;
325 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
326 (COPY_TO_REGCLASS FR64:$src, VR128)>;
328 // Bitcasts between 128-bit vector types. Return the original type since
329 // no instruction is needed for the conversion
330 let Predicates = [HasSSE2] in {
331 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
332 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
333 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
334 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
335 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
336 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
337 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
338 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
339 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
340 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
341 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
342 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
343 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
344 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
345 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
346 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
347 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
348 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
349 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
350 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
351 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
352 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
353 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
354 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
355 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
356 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
357 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
358 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
359 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
360 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
363 // Bitcasts between 256-bit vector types. Return the original type since
364 // no instruction is needed for the conversion
365 let Predicates = [HasAVX] in {
366 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
367 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
368 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
369 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
370 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
371 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
372 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
373 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
374 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
375 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
376 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
377 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
378 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
379 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
380 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
381 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
382 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
383 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
384 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
385 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
386 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
387 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
388 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
389 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
390 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
391 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
392 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
393 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
394 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
395 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
398 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
399 // This is expanded by ExpandPostRAPseudos.
400 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
401 isPseudo = 1, SchedRW = [WriteZero] in {
402 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
403 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
404 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
405 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
408 //===----------------------------------------------------------------------===//
409 // AVX & SSE - Zero/One Vectors
410 //===----------------------------------------------------------------------===//
412 // Alias instruction that maps zero vector to pxor / xorp* for sse.
413 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
414 // swizzled by ExecutionDepsFix to pxor.
415 // We set canFoldAsLoad because this can be converted to a constant-pool
416 // load of an all-zeros value if folding it would be beneficial.
417 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
418 isPseudo = 1, SchedRW = [WriteZero] in {
419 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
420 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
423 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
424 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
425 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
426 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
427 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
430 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
431 // and doesn't need it because on sandy bridge the register is set to zero
432 // at the rename stage without using any execution unit, so SET0PSY
433 // and SET0PDY can be used for vector int instructions without penalty
434 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
435 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
436 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
437 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
440 let Predicates = [HasAVX] in
441 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
443 let Predicates = [HasAVX2] in {
444 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
445 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
446 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
447 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
450 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
451 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
452 let Predicates = [HasAVX1Only] in {
453 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
454 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
455 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
457 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
458 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
459 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
461 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
462 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
463 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
465 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
466 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
467 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-ones value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
476 let Predicates = [HasAVX2] in
477 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
478 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
482 //===----------------------------------------------------------------------===//
483 // SSE 1 & 2 - Move FP Scalar Instructions
485 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
486 // register copies because it's a partial register update; Register-to-register
487 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
488 // that the insert be implementable in terms of a copy, and just mentioned, we
489 // don't use movss/movsd for copies.
490 //===----------------------------------------------------------------------===//
492 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
493 X86MemOperand x86memop, string base_opc,
495 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
496 (ins VR128:$src1, RC:$src2),
497 !strconcat(base_opc, asm_opr),
498 [(set VR128:$dst, (vt (OpNode VR128:$src1,
499 (scalar_to_vector RC:$src2))))],
500 IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
502 // For the disassembler
503 let isCodeGenOnly = 1, hasSideEffects = 0 in
504 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
505 (ins VR128:$src1, RC:$src2),
506 !strconcat(base_opc, asm_opr),
507 [], IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
510 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
511 X86MemOperand x86memop, string OpcodeStr> {
513 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
514 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
517 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
519 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
520 VEX, VEX_LIG, Sched<[WriteStore]>;
522 let Constraints = "$src1 = $dst" in {
523 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
524 "\t{$src2, $dst|$dst, $src2}">;
527 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
528 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
529 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
533 // Loading from memory automatically zeroing upper bits.
534 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
535 PatFrag mem_pat, string OpcodeStr> {
536 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
538 [(set RC:$dst, (mem_pat addr:$src))],
539 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
540 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
541 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
542 [(set RC:$dst, (mem_pat addr:$src))],
543 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
546 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
547 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
549 let canFoldAsLoad = 1, isReMaterializable = 1 in {
550 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
552 let AddedComplexity = 20 in
553 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
557 let Predicates = [UseAVX] in {
558 let AddedComplexity = 15 in {
559 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
560 // MOVS{S,D} to the lower bits.
561 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
562 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
563 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
564 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
565 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
566 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
567 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
568 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
570 // Move low f32 and clear high bits.
571 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
572 (SUBREG_TO_REG (i32 0),
573 (VMOVSSrr (v4f32 (V_SET0)),
574 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
575 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
576 (SUBREG_TO_REG (i32 0),
577 (VMOVSSrr (v4i32 (V_SET0)),
578 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
581 let AddedComplexity = 20 in {
582 // MOVSSrm zeros the high parts of the register; represent this
583 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
584 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
585 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
586 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
587 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
588 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
589 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
591 // MOVSDrm zeros the high parts of the register; represent this
592 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
593 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
594 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
595 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
596 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
597 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
598 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
599 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
600 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
601 def : Pat<(v2f64 (X86vzload addr:$src)),
602 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
604 // Represent the same patterns above but in the form they appear for
606 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
607 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
608 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
609 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
610 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
612 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
613 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
616 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
617 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
618 (SUBREG_TO_REG (i32 0),
619 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
621 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
622 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
623 (SUBREG_TO_REG (i64 0),
624 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
626 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
627 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
628 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
630 // Move low f64 and clear high bits.
631 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
632 (SUBREG_TO_REG (i32 0),
633 (VMOVSDrr (v2f64 (V_SET0)),
634 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
636 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
637 (SUBREG_TO_REG (i32 0),
638 (VMOVSDrr (v2i64 (V_SET0)),
639 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
641 // Extract and store.
642 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
644 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
645 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
647 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
649 // Shuffle with VMOVSS
650 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
651 (VMOVSSrr (v4i32 VR128:$src1),
652 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
653 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
654 (VMOVSSrr (v4f32 VR128:$src1),
655 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
658 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
659 (SUBREG_TO_REG (i32 0),
660 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
661 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
663 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
666 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
669 // Shuffle with VMOVSD
670 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
671 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
674 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
675 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
676 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
680 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
681 (SUBREG_TO_REG (i32 0),
682 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
683 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
685 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
686 (SUBREG_TO_REG (i32 0),
687 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
688 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
692 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
693 // is during lowering, where it's not possible to recognize the fold cause
694 // it has two uses through a bitcast. One use disappears at isel time and the
695 // fold opportunity reappears.
696 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
697 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
698 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
699 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
700 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
701 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
702 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
703 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
706 let Predicates = [UseSSE1] in {
707 let AddedComplexity = 15 in {
708 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
709 // MOVSS to the lower bits.
710 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
711 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
712 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
713 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
714 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
715 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
718 let AddedComplexity = 20 in {
719 // MOVSSrm already zeros the high parts of the register.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
721 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
722 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
723 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
724 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
728 // Extract and store.
729 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
731 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
733 // Shuffle with MOVSS
734 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
735 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
736 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
737 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
740 let Predicates = [UseSSE2] in {
741 let AddedComplexity = 15 in {
742 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
743 // MOVSD to the lower bits.
744 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
745 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
748 let AddedComplexity = 20 in {
749 // MOVSDrm already zeros the high parts of the register.
750 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
751 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
752 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
753 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
754 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
755 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
756 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
757 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
758 def : Pat<(v2f64 (X86vzload addr:$src)),
759 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 // Extract and store.
763 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
765 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
767 // Shuffle with MOVSD
768 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
769 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
770 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
771 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
772 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
773 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
774 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
775 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
777 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
778 // is during lowering, where it's not possible to recognize the fold cause
779 // it has two uses through a bitcast. One use disappears at isel time and the
780 // fold opportunity reappears.
781 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
782 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
783 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
784 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
785 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
786 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
788 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
791 //===----------------------------------------------------------------------===//
792 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
793 //===----------------------------------------------------------------------===//
795 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
796 X86MemOperand x86memop, PatFrag ld_frag,
797 string asm, Domain d,
799 bit IsReMaterializable = 1> {
800 let neverHasSideEffects = 1 in
801 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
802 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
804 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
805 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
806 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
807 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
811 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
812 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
814 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
815 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
817 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
818 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
820 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
821 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
824 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
829 TB, OpSize, VEX, VEX_L;
830 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 TB, OpSize, VEX, VEX_L;
836 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
837 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
839 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
840 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
842 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
843 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
845 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
846 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let SchedRW = [WriteStore] in {
850 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
851 "movaps\t{$src, $dst|$dst, $src}",
852 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
853 IIC_SSE_MOVA_P_MR>, VEX;
854 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
855 "movapd\t{$src, $dst|$dst, $src}",
856 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
857 IIC_SSE_MOVA_P_MR>, VEX;
858 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
859 "movups\t{$src, $dst|$dst, $src}",
860 [(store (v4f32 VR128:$src), addr:$dst)],
861 IIC_SSE_MOVU_P_MR>, VEX;
862 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
863 "movupd\t{$src, $dst|$dst, $src}",
864 [(store (v2f64 VR128:$src), addr:$dst)],
865 IIC_SSE_MOVU_P_MR>, VEX;
866 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
870 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
874 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v8f32 VR256:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
878 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v4f64 VR256:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
885 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
886 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
888 "movaps\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVA_P_RR>, VEX;
890 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
892 "movapd\t{$src, $dst|$dst, $src}", [],
893 IIC_SSE_MOVA_P_RR>, VEX;
894 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
896 "movups\t{$src, $dst|$dst, $src}", [],
897 IIC_SSE_MOVU_P_RR>, VEX;
898 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
900 "movupd\t{$src, $dst|$dst, $src}", [],
901 IIC_SSE_MOVU_P_RR>, VEX;
902 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
904 "movaps\t{$src, $dst|$dst, $src}", [],
905 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
906 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
908 "movapd\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
910 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
912 "movups\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
914 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
916 "movupd\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
920 let Predicates = [HasAVX] in {
921 def : Pat<(v8i32 (X86vzmovl
922 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
923 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
924 def : Pat<(v4i64 (X86vzmovl
925 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
926 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
927 def : Pat<(v8f32 (X86vzmovl
928 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
929 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
930 def : Pat<(v4f64 (X86vzmovl
931 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
932 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
936 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
937 (VMOVUPSYmr addr:$dst, VR256:$src)>;
938 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
939 (VMOVUPDYmr addr:$dst, VR256:$src)>;
941 let SchedRW = [WriteStore] in {
942 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
943 "movaps\t{$src, $dst|$dst, $src}",
944 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
946 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
947 "movapd\t{$src, $dst|$dst, $src}",
948 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
950 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
951 "movups\t{$src, $dst|$dst, $src}",
952 [(store (v4f32 VR128:$src), addr:$dst)],
954 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
955 "movupd\t{$src, $dst|$dst, $src}",
956 [(store (v2f64 VR128:$src), addr:$dst)],
961 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
962 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
963 "movaps\t{$src, $dst|$dst, $src}", [],
965 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
966 "movapd\t{$src, $dst|$dst, $src}", [],
968 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}", [],
971 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
972 "movupd\t{$src, $dst|$dst, $src}", [],
976 let Predicates = [HasAVX] in {
977 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
978 (VMOVUPSmr addr:$dst, VR128:$src)>;
979 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
980 (VMOVUPDmr addr:$dst, VR128:$src)>;
983 let Predicates = [UseSSE1] in
984 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
985 (MOVUPSmr addr:$dst, VR128:$src)>;
986 let Predicates = [UseSSE2] in
987 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
988 (MOVUPDmr addr:$dst, VR128:$src)>;
990 // Use vmovaps/vmovups for AVX integer load/store.
991 let Predicates = [HasAVX] in {
992 // 128-bit load/store
993 def : Pat<(alignedloadv2i64 addr:$src),
994 (VMOVAPSrm addr:$src)>;
995 def : Pat<(loadv2i64 addr:$src),
996 (VMOVUPSrm addr:$src)>;
998 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
999 (VMOVAPSmr addr:$dst, VR128:$src)>;
1000 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1001 (VMOVAPSmr addr:$dst, VR128:$src)>;
1002 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1003 (VMOVAPSmr addr:$dst, VR128:$src)>;
1004 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1005 (VMOVAPSmr addr:$dst, VR128:$src)>;
1006 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1007 (VMOVUPSmr addr:$dst, VR128:$src)>;
1008 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1009 (VMOVUPSmr addr:$dst, VR128:$src)>;
1010 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1011 (VMOVUPSmr addr:$dst, VR128:$src)>;
1012 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1013 (VMOVUPSmr addr:$dst, VR128:$src)>;
1015 // 256-bit load/store
1016 def : Pat<(alignedloadv4i64 addr:$src),
1017 (VMOVAPSYrm addr:$src)>;
1018 def : Pat<(loadv4i64 addr:$src),
1019 (VMOVUPSYrm addr:$src)>;
1020 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1021 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1022 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1023 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1024 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1025 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1026 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1027 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1028 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1029 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1030 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1031 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1032 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1033 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1034 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1035 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1037 // Special patterns for storing subvector extracts of lower 128-bits
1038 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1039 def : Pat<(alignedstore (v2f64 (extract_subvector
1040 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1041 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1042 def : Pat<(alignedstore (v4f32 (extract_subvector
1043 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1044 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1045 def : Pat<(alignedstore (v2i64 (extract_subvector
1046 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1047 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1048 def : Pat<(alignedstore (v4i32 (extract_subvector
1049 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1050 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1051 def : Pat<(alignedstore (v8i16 (extract_subvector
1052 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1053 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1054 def : Pat<(alignedstore (v16i8 (extract_subvector
1055 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1056 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1058 def : Pat<(store (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(store (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(store (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(store (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(store (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(store (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1078 // Use movaps / movups for SSE integer load / store (one byte shorter).
1079 // The instructions selected below are then converted to MOVDQA/MOVDQU
1080 // during the SSE domain pass.
1081 let Predicates = [UseSSE1] in {
1082 def : Pat<(alignedloadv2i64 addr:$src),
1083 (MOVAPSrm addr:$src)>;
1084 def : Pat<(loadv2i64 addr:$src),
1085 (MOVUPSrm addr:$src)>;
1087 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1088 (MOVAPSmr addr:$dst, VR128:$src)>;
1089 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1090 (MOVAPSmr addr:$dst, VR128:$src)>;
1091 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1092 (MOVAPSmr addr:$dst, VR128:$src)>;
1093 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1094 (MOVAPSmr addr:$dst, VR128:$src)>;
1095 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1096 (MOVUPSmr addr:$dst, VR128:$src)>;
1097 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1098 (MOVUPSmr addr:$dst, VR128:$src)>;
1099 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1100 (MOVUPSmr addr:$dst, VR128:$src)>;
1101 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1102 (MOVUPSmr addr:$dst, VR128:$src)>;
1105 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1106 // bits are disregarded. FIXME: Set encoding to pseudo!
1107 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1108 let isCodeGenOnly = 1 in {
1109 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1110 "movaps\t{$src, $dst|$dst, $src}",
1111 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 IIC_SSE_MOVA_P_RM>, VEX;
1113 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1114 "movapd\t{$src, $dst|$dst, $src}",
1115 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1116 IIC_SSE_MOVA_P_RM>, VEX;
1118 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1119 "movaps\t{$src, $dst|$dst, $src}",
1120 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1122 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1123 "movapd\t{$src, $dst|$dst, $src}",
1124 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1128 //===----------------------------------------------------------------------===//
1129 // SSE 1 & 2 - Move Low packed FP Instructions
1130 //===----------------------------------------------------------------------===//
1132 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1133 string base_opc, string asm_opr,
1134 InstrItinClass itin> {
1135 def PSrm : PI<opc, MRMSrcMem,
1136 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1137 !strconcat(base_opc, "s", asm_opr),
1139 (psnode VR128:$src1,
1140 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1141 itin, SSEPackedSingle>, TB,
1142 Sched<[WriteShuffleLd, ReadAfterLd]>;
1144 def PDrm : PI<opc, MRMSrcMem,
1145 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1146 !strconcat(base_opc, "d", asm_opr),
1147 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1148 (scalar_to_vector (loadf64 addr:$src2)))))],
1149 itin, SSEPackedDouble>, TB, OpSize,
1150 Sched<[WriteShuffleLd, ReadAfterLd]>;
1154 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1155 string base_opc, InstrItinClass itin> {
1156 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1157 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1160 let Constraints = "$src1 = $dst" in
1161 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1162 "\t{$src2, $dst|$dst, $src2}",
1166 let AddedComplexity = 20 in {
1167 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1171 let SchedRW = [WriteStore] in {
1172 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1173 "movlps\t{$src, $dst|$dst, $src}",
1174 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1175 (iPTR 0))), addr:$dst)],
1176 IIC_SSE_MOV_LH>, VEX;
1177 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1178 "movlpd\t{$src, $dst|$dst, $src}",
1179 [(store (f64 (vector_extract (v2f64 VR128:$src),
1180 (iPTR 0))), addr:$dst)],
1181 IIC_SSE_MOV_LH>, VEX;
1182 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1183 "movlps\t{$src, $dst|$dst, $src}",
1184 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1185 (iPTR 0))), addr:$dst)],
1187 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1188 "movlpd\t{$src, $dst|$dst, $src}",
1189 [(store (f64 (vector_extract (v2f64 VR128:$src),
1190 (iPTR 0))), addr:$dst)],
1194 let Predicates = [HasAVX] in {
1195 // Shuffle with VMOVLPS
1196 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1197 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1198 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1199 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1201 // Shuffle with VMOVLPD
1202 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1203 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1204 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1205 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1208 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1210 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1211 def : Pat<(store (v4i32 (X86Movlps
1212 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1213 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1214 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1216 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1217 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1219 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1222 let Predicates = [UseSSE1] in {
1223 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1224 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1225 (iPTR 0))), addr:$src1),
1226 (MOVLPSmr addr:$src1, VR128:$src2)>;
1228 // Shuffle with MOVLPS
1229 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1230 (MOVLPSrm VR128:$src1, addr:$src2)>;
1231 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1232 (MOVLPSrm VR128:$src1, addr:$src2)>;
1233 def : Pat<(X86Movlps VR128:$src1,
1234 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1235 (MOVLPSrm VR128:$src1, addr:$src2)>;
1238 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1240 (MOVLPSmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v4i32 (X86Movlps
1242 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1244 (MOVLPSmr addr:$src1, VR128:$src2)>;
1247 let Predicates = [UseSSE2] in {
1248 // Shuffle with MOVLPD
1249 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1250 (MOVLPDrm VR128:$src1, addr:$src2)>;
1251 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1252 (MOVLPDrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1257 (MOVLPDmr addr:$src1, VR128:$src2)>;
1258 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1260 (MOVLPDmr addr:$src1, VR128:$src2)>;
1263 //===----------------------------------------------------------------------===//
1264 // SSE 1 & 2 - Move Hi packed FP Instructions
1265 //===----------------------------------------------------------------------===//
1267 let AddedComplexity = 20 in {
1268 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1272 let SchedRW = [WriteStore] in {
1273 // v2f64 extract element 1 is always custom lowered to unpack high to low
1274 // and extract element 0 so the non-store version isn't too horrible.
1275 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1276 "movhps\t{$src, $dst|$dst, $src}",
1277 [(store (f64 (vector_extract
1278 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1279 (bc_v2f64 (v4f32 VR128:$src))),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1281 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1282 "movhpd\t{$src, $dst|$dst, $src}",
1283 [(store (f64 (vector_extract
1284 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1285 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1286 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1287 "movhps\t{$src, $dst|$dst, $src}",
1288 [(store (f64 (vector_extract
1289 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1290 (bc_v2f64 (v4f32 VR128:$src))),
1291 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1292 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1293 "movhpd\t{$src, $dst|$dst, $src}",
1294 [(store (f64 (vector_extract
1295 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1296 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1299 let Predicates = [HasAVX] in {
1301 def : Pat<(X86Movlhps VR128:$src1,
1302 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1303 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1304 def : Pat<(X86Movlhps VR128:$src1,
1305 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1306 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1308 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1309 // is during lowering, where it's not possible to recognize the load fold
1310 // cause it has two uses through a bitcast. One use disappears at isel time
1311 // and the fold opportunity reappears.
1312 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1313 (scalar_to_vector (loadf64 addr:$src2)))),
1314 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1317 let Predicates = [UseSSE1] in {
1319 def : Pat<(X86Movlhps VR128:$src1,
1320 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1321 (MOVHPSrm VR128:$src1, addr:$src2)>;
1322 def : Pat<(X86Movlhps VR128:$src1,
1323 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1324 (MOVHPSrm VR128:$src1, addr:$src2)>;
1327 let Predicates = [UseSSE2] in {
1328 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1329 // is during lowering, where it's not possible to recognize the load fold
1330 // cause it has two uses through a bitcast. One use disappears at isel time
1331 // and the fold opportunity reappears.
1332 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1333 (scalar_to_vector (loadf64 addr:$src2)))),
1334 (MOVHPDrm VR128:$src1, addr:$src2)>;
1337 //===----------------------------------------------------------------------===//
1338 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1339 //===----------------------------------------------------------------------===//
1341 let AddedComplexity = 20, Predicates = [UseAVX] in {
1342 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1343 (ins VR128:$src1, VR128:$src2),
1344 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1346 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1348 VEX_4V, Sched<[WriteShuffle]>;
1349 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1350 (ins VR128:$src1, VR128:$src2),
1351 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1353 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 VEX_4V, Sched<[WriteShuffle]>;
1357 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1358 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1359 (ins VR128:$src1, VR128:$src2),
1360 "movlhps\t{$src2, $dst|$dst, $src2}",
1362 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1363 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1364 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1365 (ins VR128:$src1, VR128:$src2),
1366 "movhlps\t{$src2, $dst|$dst, $src2}",
1368 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1369 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1372 let Predicates = [UseAVX] in {
1374 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1375 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1376 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1377 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1380 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1381 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1384 let Predicates = [UseSSE1] in {
1386 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1387 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1388 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1389 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1392 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1393 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1396 //===----------------------------------------------------------------------===//
1397 // SSE 1 & 2 - Conversion Instructions
1398 //===----------------------------------------------------------------------===//
1400 def SSE_CVT_PD : OpndItins<
1401 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1404 let Sched = WriteCvtI2F in
1405 def SSE_CVT_PS : OpndItins<
1406 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1409 let Sched = WriteCvtI2F in
1410 def SSE_CVT_Scalar : OpndItins<
1411 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1414 let Sched = WriteCvtF2I in
1415 def SSE_CVT_SS2SI_32 : OpndItins<
1416 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1419 let Sched = WriteCvtF2I in
1420 def SSE_CVT_SS2SI_64 : OpndItins<
1421 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1424 let Sched = WriteCvtF2I in
1425 def SSE_CVT_SD2SI : OpndItins<
1426 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1429 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1431 string asm, OpndItins itins> {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1433 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1434 itins.rr>, Sched<[itins.Sched]>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1436 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1437 itins.rm>, Sched<[itins.Sched.Folded]>;
1440 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1441 X86MemOperand x86memop, string asm, Domain d,
1443 let neverHasSideEffects = 1 in {
1444 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1445 [], itins.rr, d>, Sched<[itins.Sched]>;
1447 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1448 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1452 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1453 X86MemOperand x86memop, string asm> {
1454 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1455 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1456 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1457 Sched<[WriteCvtI2F]>;
1459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1460 (ins DstRC:$src1, x86memop:$src),
1461 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1462 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1463 } // neverHasSideEffects = 1
1466 let Predicates = [UseAVX] in {
1467 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1468 "cvttss2si\t{$src, $dst|$dst, $src}",
1471 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1472 "cvttss2si\t{$src, $dst|$dst, $src}",
1474 XS, VEX, VEX_W, VEX_LIG;
1475 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1476 "cvttsd2si\t{$src, $dst|$dst, $src}",
1479 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1480 "cvttsd2si\t{$src, $dst|$dst, $src}",
1482 XD, VEX, VEX_W, VEX_LIG;
1484 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1485 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1486 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1487 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1488 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1489 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1490 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1491 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1492 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1493 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1494 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1495 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1496 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1497 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1498 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1499 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1501 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1502 // register, but the same isn't true when only using memory operands,
1503 // provide other assembly "l" and "q" forms to address this explicitly
1504 // where appropriate to do so.
1505 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1506 XS, VEX_4V, VEX_LIG;
1507 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1508 XS, VEX_4V, VEX_W, VEX_LIG;
1509 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1510 XD, VEX_4V, VEX_LIG;
1511 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1512 XD, VEX_4V, VEX_W, VEX_LIG;
1514 let Predicates = [UseAVX] in {
1515 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1516 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1517 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1518 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1520 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1521 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1522 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1523 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1524 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1525 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1526 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1527 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1529 def : Pat<(f32 (sint_to_fp GR32:$src)),
1530 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1531 def : Pat<(f32 (sint_to_fp GR64:$src)),
1532 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1533 def : Pat<(f64 (sint_to_fp GR32:$src)),
1534 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1535 def : Pat<(f64 (sint_to_fp GR64:$src)),
1536 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1539 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1540 "cvttss2si\t{$src, $dst|$dst, $src}",
1541 SSE_CVT_SS2SI_32>, XS;
1542 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1543 "cvttss2si\t{$src, $dst|$dst, $src}",
1544 SSE_CVT_SS2SI_64>, XS, REX_W;
1545 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1546 "cvttsd2si\t{$src, $dst|$dst, $src}",
1548 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1549 "cvttsd2si\t{$src, $dst|$dst, $src}",
1550 SSE_CVT_SD2SI>, XD, REX_W;
1551 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1552 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1553 SSE_CVT_Scalar>, XS;
1554 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1555 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1556 SSE_CVT_Scalar>, XS, REX_W;
1557 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1558 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1559 SSE_CVT_Scalar>, XD;
1560 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1561 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1562 SSE_CVT_Scalar>, XD, REX_W;
1564 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1565 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1566 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1567 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1568 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1569 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1570 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1571 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1572 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1573 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1574 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1575 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1576 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1577 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1578 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1579 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1581 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1582 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1583 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1584 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1586 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1587 // and/or XMM operand(s).
1589 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1590 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1591 string asm, OpndItins itins> {
1592 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1593 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1594 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1595 Sched<[itins.Sched]>;
1596 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1597 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1598 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1599 Sched<[itins.Sched.Folded]>;
1602 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1603 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1604 PatFrag ld_frag, string asm, OpndItins itins,
1606 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1608 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1609 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1610 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1611 itins.rr>, Sched<[itins.Sched]>;
1612 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1613 (ins DstRC:$src1, x86memop:$src2),
1615 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1616 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1617 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1618 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1621 let Predicates = [UseAVX] in {
1622 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1623 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1624 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1625 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1626 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1627 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1629 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1630 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1631 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1632 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1635 let Predicates = [UseAVX] in {
1636 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1637 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1638 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1639 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1640 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1641 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1643 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1644 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1645 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1646 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1647 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1648 SSE_CVT_Scalar, 0>, XD,
1651 let Constraints = "$src1 = $dst" in {
1652 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1653 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1654 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1655 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1656 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1657 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1658 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1659 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1660 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1661 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1662 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1663 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1668 // Aliases for intrinsics
1669 let Predicates = [UseAVX] in {
1670 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1671 ssmem, sse_load_f32, "cvttss2si",
1672 SSE_CVT_SS2SI_32>, XS, VEX;
1673 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1674 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1675 "cvttss2si", SSE_CVT_SS2SI_64>,
1677 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1678 sdmem, sse_load_f64, "cvttsd2si",
1679 SSE_CVT_SD2SI>, XD, VEX;
1680 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1681 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1682 "cvttsd2si", SSE_CVT_SD2SI>,
1685 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1686 ssmem, sse_load_f32, "cvttss2si",
1687 SSE_CVT_SS2SI_32>, XS;
1688 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1689 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1690 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1691 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1692 sdmem, sse_load_f64, "cvttsd2si",
1694 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1695 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1696 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1698 let Predicates = [UseAVX] in {
1699 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1700 ssmem, sse_load_f32, "cvtss2si",
1701 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1702 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1703 ssmem, sse_load_f32, "cvtss2si",
1704 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1706 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1707 ssmem, sse_load_f32, "cvtss2si",
1708 SSE_CVT_SS2SI_32>, XS;
1709 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1710 ssmem, sse_load_f32, "cvtss2si",
1711 SSE_CVT_SS2SI_64>, XS, REX_W;
1713 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1714 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1715 SSEPackedSingle, SSE_CVT_PS>,
1716 TB, VEX, Requires<[HasAVX]>;
1717 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1718 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1719 SSEPackedSingle, SSE_CVT_PS>,
1720 TB, VEX, VEX_L, Requires<[HasAVX]>;
1722 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1723 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1724 SSEPackedSingle, SSE_CVT_PS>,
1725 TB, Requires<[UseSSE2]>;
1727 let Predicates = [UseAVX] in {
1728 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1729 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1730 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1731 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1732 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1733 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1734 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1735 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1736 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1737 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1738 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1739 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1740 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1741 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1742 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1743 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1746 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1747 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1748 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1749 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1750 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1751 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1752 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1753 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1754 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1755 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1756 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1757 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1758 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1759 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1760 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1761 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1765 // Convert scalar double to scalar single
1766 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1767 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1768 (ins FR64:$src1, FR64:$src2),
1769 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1770 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1771 Sched<[WriteCvtF2F]>;
1773 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1774 (ins FR64:$src1, f64mem:$src2),
1775 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1776 [], IIC_SSE_CVT_Scalar_RM>,
1777 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1778 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1781 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1784 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1785 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1786 [(set FR32:$dst, (fround FR64:$src))],
1787 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1788 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1789 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1790 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1791 IIC_SSE_CVT_Scalar_RM>,
1793 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1795 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1796 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1797 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1799 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1800 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1801 Sched<[WriteCvtF2F]>;
1802 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1803 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1804 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1805 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1806 VR128:$src1, sse_load_f64:$src2))],
1807 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1808 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1810 let Constraints = "$src1 = $dst" in {
1811 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1812 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1813 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1815 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1816 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1817 Sched<[WriteCvtF2F]>;
1818 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1819 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1820 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1821 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1822 VR128:$src1, sse_load_f64:$src2))],
1823 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1824 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1827 // Convert scalar single to scalar double
1828 // SSE2 instructions with XS prefix
1829 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1830 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1831 (ins FR32:$src1, FR32:$src2),
1832 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1833 [], IIC_SSE_CVT_Scalar_RR>,
1834 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1835 Sched<[WriteCvtF2F]>;
1837 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1838 (ins FR32:$src1, f32mem:$src2),
1839 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1840 [], IIC_SSE_CVT_Scalar_RM>,
1841 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1842 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1845 def : Pat<(f64 (fextend FR32:$src)),
1846 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1847 def : Pat<(fextend (loadf32 addr:$src)),
1848 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1850 def : Pat<(extloadf32 addr:$src),
1851 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1852 Requires<[UseAVX, OptForSize]>;
1853 def : Pat<(extloadf32 addr:$src),
1854 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1855 Requires<[UseAVX, OptForSpeed]>;
1857 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1858 "cvtss2sd\t{$src, $dst|$dst, $src}",
1859 [(set FR64:$dst, (fextend FR32:$src))],
1860 IIC_SSE_CVT_Scalar_RR>, XS,
1861 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1862 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1863 "cvtss2sd\t{$src, $dst|$dst, $src}",
1864 [(set FR64:$dst, (extloadf32 addr:$src))],
1865 IIC_SSE_CVT_Scalar_RM>, XS,
1866 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1868 // extload f32 -> f64. This matches load+fextend because we have a hack in
1869 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1871 // Since these loads aren't folded into the fextend, we have to match it
1873 def : Pat<(fextend (loadf32 addr:$src)),
1874 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1875 def : Pat<(extloadf32 addr:$src),
1876 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1878 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1879 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1880 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1882 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1883 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1884 Sched<[WriteCvtF2F]>;
1885 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1886 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1889 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1890 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1891 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1892 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1893 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1894 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1895 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1897 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1898 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1899 Sched<[WriteCvtF2F]>;
1900 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1901 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1902 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1904 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1905 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1906 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1909 // Convert packed single/double fp to doubleword
1910 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvtps2dq\t{$src, $dst|$dst, $src}",
1912 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1913 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1914 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1915 "cvtps2dq\t{$src, $dst|$dst, $src}",
1917 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1918 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1919 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1920 "cvtps2dq\t{$src, $dst|$dst, $src}",
1922 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1923 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1924 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1925 "cvtps2dq\t{$src, $dst|$dst, $src}",
1927 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1928 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1929 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1930 "cvtps2dq\t{$src, $dst|$dst, $src}",
1931 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1932 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1933 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1934 "cvtps2dq\t{$src, $dst|$dst, $src}",
1936 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1937 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1940 // Convert Packed Double FP to Packed DW Integers
1941 let Predicates = [HasAVX] in {
1942 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1943 // register, but the same isn't true when using memory operands instead.
1944 // Provide other assembly rr and rm forms to address this explicitly.
1945 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1946 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1947 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1948 VEX, Sched<[WriteCvtF2I]>;
1951 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1952 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1953 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1954 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1956 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX,
1957 Sched<[WriteCvtF2ILd]>;
1960 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1961 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1963 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
1964 Sched<[WriteCvtF2I]>;
1965 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1966 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1968 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1969 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1970 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1971 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1974 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1975 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1977 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1978 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
1979 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1980 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1981 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1982 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
1984 // Convert with truncation packed single/double fp to doubleword
1985 // SSE2 packed instructions with XS prefix
1986 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvttps2dq\t{$src, $dst|$dst, $src}",
1989 (int_x86_sse2_cvttps2dq VR128:$src))],
1990 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1991 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1992 "cvttps2dq\t{$src, $dst|$dst, $src}",
1993 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1994 (memopv4f32 addr:$src)))],
1995 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1996 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1997 "cvttps2dq\t{$src, $dst|$dst, $src}",
1999 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2000 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2001 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2002 "cvttps2dq\t{$src, $dst|$dst, $src}",
2003 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2004 (memopv8f32 addr:$src)))],
2005 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2006 Sched<[WriteCvtF2ILd]>;
2008 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2009 "cvttps2dq\t{$src, $dst|$dst, $src}",
2010 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2011 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2012 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2013 "cvttps2dq\t{$src, $dst|$dst, $src}",
2015 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2016 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2018 let Predicates = [HasAVX] in {
2019 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2020 (VCVTDQ2PSrr VR128:$src)>;
2021 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2022 (VCVTDQ2PSrm addr:$src)>;
2024 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2025 (VCVTDQ2PSrr VR128:$src)>;
2026 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2027 (VCVTDQ2PSrm addr:$src)>;
2029 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2030 (VCVTTPS2DQrr VR128:$src)>;
2031 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2032 (VCVTTPS2DQrm addr:$src)>;
2034 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2035 (VCVTDQ2PSYrr VR256:$src)>;
2036 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
2037 (VCVTDQ2PSYrm addr:$src)>;
2039 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2040 (VCVTTPS2DQYrr VR256:$src)>;
2041 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
2042 (VCVTTPS2DQYrm addr:$src)>;
2045 let Predicates = [UseSSE2] in {
2046 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2047 (CVTDQ2PSrr VR128:$src)>;
2048 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2049 (CVTDQ2PSrm addr:$src)>;
2051 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2052 (CVTDQ2PSrr VR128:$src)>;
2053 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2054 (CVTDQ2PSrm addr:$src)>;
2056 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2057 (CVTTPS2DQrr VR128:$src)>;
2058 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2059 (CVTTPS2DQrm addr:$src)>;
2062 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2063 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2065 (int_x86_sse2_cvttpd2dq VR128:$src))],
2066 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2068 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2069 // register, but the same isn't true when using memory operands instead.
2070 // Provide other assembly rr and rm forms to address this explicitly.
2073 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2074 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
2075 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2076 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2077 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2078 (memopv2f64 addr:$src)))],
2079 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2082 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2083 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2085 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2086 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2087 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2088 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2090 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
2091 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2092 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2093 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2095 let Predicates = [HasAVX] in {
2096 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2097 (VCVTTPD2DQYrr VR256:$src)>;
2098 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
2099 (VCVTTPD2DQYrm addr:$src)>;
2100 } // Predicates = [HasAVX]
2102 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2103 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2104 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2105 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2106 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2107 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2108 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2109 (memopv2f64 addr:$src)))],
2111 Sched<[WriteCvtF2ILd]>;
2113 // Convert packed single to packed double
2114 let Predicates = [HasAVX] in {
2115 // SSE2 instructions without OpSize prefix
2116 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2117 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2118 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2119 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2120 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2121 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2122 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2123 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2124 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2125 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2127 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2128 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2129 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2130 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2132 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2133 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2136 let Predicates = [UseSSE2] in {
2137 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2138 "cvtps2pd\t{$src, $dst|$dst, $src}",
2139 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2140 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2141 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2142 "cvtps2pd\t{$src, $dst|$dst, $src}",
2143 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2144 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2147 // Convert Packed DW Integers to Packed Double FP
2148 let Predicates = [HasAVX] in {
2149 let neverHasSideEffects = 1, mayLoad = 1 in
2150 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2151 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2152 []>, VEX, Sched<[WriteCvtI2FLd]>;
2153 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2154 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2156 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2157 Sched<[WriteCvtI2F]>;
2158 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2159 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2161 (int_x86_avx_cvtdq2_pd_256
2162 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L,
2163 Sched<[WriteCvtI2FLd]>;
2164 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2165 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2167 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2168 Sched<[WriteCvtI2F]>;
2171 let neverHasSideEffects = 1, mayLoad = 1 in
2172 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2173 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2174 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2175 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2180 // AVX 256-bit register conversion intrinsics
2181 let Predicates = [HasAVX] in {
2182 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2183 (VCVTDQ2PDYrr VR128:$src)>;
2184 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2185 (VCVTDQ2PDYrm addr:$src)>;
2186 } // Predicates = [HasAVX]
2188 // Convert packed double to packed single
2189 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2190 // register, but the same isn't true when using memory operands instead.
2191 // Provide other assembly rr and rm forms to address this explicitly.
2192 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2193 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2194 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2195 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2198 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2199 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2200 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2201 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2203 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2204 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2207 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2208 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2210 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2211 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2212 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2213 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2215 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2216 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2217 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2218 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2220 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2221 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2222 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2223 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2224 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2225 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2227 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2228 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2231 // AVX 256-bit register conversion intrinsics
2232 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2233 // whenever possible to avoid declaring two versions of each one.
2234 let Predicates = [HasAVX] in {
2235 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2236 (VCVTDQ2PSYrr VR256:$src)>;
2237 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2238 (VCVTDQ2PSYrm addr:$src)>;
2240 // Match fround and fextend for 128/256-bit conversions
2241 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2242 (VCVTPD2PSrr VR128:$src)>;
2243 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2244 (VCVTPD2PSXrm addr:$src)>;
2245 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2246 (VCVTPD2PSYrr VR256:$src)>;
2247 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2248 (VCVTPD2PSYrm addr:$src)>;
2250 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2251 (VCVTPS2PDrr VR128:$src)>;
2252 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2253 (VCVTPS2PDYrr VR128:$src)>;
2254 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2255 (VCVTPS2PDYrm addr:$src)>;
2258 let Predicates = [UseSSE2] in {
2259 // Match fround and fextend for 128 conversions
2260 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2261 (CVTPD2PSrr VR128:$src)>;
2262 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2263 (CVTPD2PSrm addr:$src)>;
2265 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2266 (CVTPS2PDrr VR128:$src)>;
2269 //===----------------------------------------------------------------------===//
2270 // SSE 1 & 2 - Compare Instructions
2271 //===----------------------------------------------------------------------===//
2273 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2274 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2275 Operand CC, SDNode OpNode, ValueType VT,
2276 PatFrag ld_frag, string asm, string asm_alt,
2278 def rr : SIi8<0xC2, MRMSrcReg,
2279 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2280 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2281 itins.rr>, Sched<[itins.Sched]>;
2282 def rm : SIi8<0xC2, MRMSrcMem,
2283 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2284 [(set RC:$dst, (OpNode (VT RC:$src1),
2285 (ld_frag addr:$src2), imm:$cc))],
2287 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2289 // Accept explicit immediate argument form instead of comparison code.
2290 let neverHasSideEffects = 1 in {
2291 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2292 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2293 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2295 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2296 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2297 IIC_SSE_ALU_F32S_RM>,
2298 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2302 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2303 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2304 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2306 XS, VEX_4V, VEX_LIG;
2307 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2308 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2309 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2310 SSE_ALU_F32S>, // same latency as 32 bit compare
2311 XD, VEX_4V, VEX_LIG;
2313 let Constraints = "$src1 = $dst" in {
2314 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2315 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2316 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2318 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2319 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2320 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2325 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2326 Intrinsic Int, string asm, OpndItins itins> {
2327 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2328 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2329 [(set VR128:$dst, (Int VR128:$src1,
2330 VR128:$src, imm:$cc))],
2332 Sched<[itins.Sched]>;
2333 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2334 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2335 [(set VR128:$dst, (Int VR128:$src1,
2336 (load addr:$src), imm:$cc))],
2338 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2341 // Aliases to match intrinsics which expect XMM operand(s).
2342 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2343 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2346 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2347 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2348 SSE_ALU_F32S>, // same latency as f32
2350 let Constraints = "$src1 = $dst" in {
2351 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2352 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2354 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2355 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2361 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2362 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2363 ValueType vt, X86MemOperand x86memop,
2364 PatFrag ld_frag, string OpcodeStr> {
2365 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2366 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2367 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2370 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2371 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2372 [(set EFLAGS, (OpNode (vt RC:$src1),
2373 (ld_frag addr:$src2)))],
2375 Sched<[WriteFAddLd, ReadAfterLd]>;
2378 let Defs = [EFLAGS] in {
2379 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2380 "ucomiss">, TB, VEX, VEX_LIG;
2381 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2382 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2383 let Pattern = []<dag> in {
2384 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2385 "comiss">, TB, VEX, VEX_LIG;
2386 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2387 "comisd">, TB, OpSize, VEX, VEX_LIG;
2390 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2391 load, "ucomiss">, TB, VEX;
2392 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2393 load, "ucomisd">, TB, OpSize, VEX;
2395 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2396 load, "comiss">, TB, VEX;
2397 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2398 load, "comisd">, TB, OpSize, VEX;
2399 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2401 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2402 "ucomisd">, TB, OpSize;
2404 let Pattern = []<dag> in {
2405 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2407 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2408 "comisd">, TB, OpSize;
2411 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2412 load, "ucomiss">, TB;
2413 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2414 load, "ucomisd">, TB, OpSize;
2416 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2418 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2419 "comisd">, TB, OpSize;
2420 } // Defs = [EFLAGS]
2422 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2423 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2424 Operand CC, Intrinsic Int, string asm,
2425 string asm_alt, Domain d,
2426 OpndItins itins = SSE_ALU_F32P> {
2427 def rri : PIi8<0xC2, MRMSrcReg,
2428 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2429 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2432 def rmi : PIi8<0xC2, MRMSrcMem,
2433 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2434 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2436 Sched<[WriteFAddLd, ReadAfterLd]>;
2438 // Accept explicit immediate argument form instead of comparison code.
2439 let neverHasSideEffects = 1 in {
2440 def rri_alt : PIi8<0xC2, MRMSrcReg,
2441 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2442 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2443 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2444 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2445 asm_alt, [], itins.rm, d>,
2446 Sched<[WriteFAddLd, ReadAfterLd]>;
2450 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2451 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2452 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2453 SSEPackedSingle>, TB, VEX_4V;
2454 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2455 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2456 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2457 SSEPackedDouble>, TB, OpSize, VEX_4V;
2458 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2459 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2460 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2461 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2462 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2463 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2464 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2465 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2466 let Constraints = "$src1 = $dst" in {
2467 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2468 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2469 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2470 SSEPackedSingle, SSE_ALU_F32P>, TB;
2471 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2472 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2473 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2474 SSEPackedDouble, SSE_ALU_F64P>, TB, OpSize;
2477 let Predicates = [HasAVX] in {
2478 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2479 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2480 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2481 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2482 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2483 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2484 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2485 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2487 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2488 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2489 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2490 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2491 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2492 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2493 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2494 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2497 let Predicates = [UseSSE1] in {
2498 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2499 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2500 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2501 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2504 let Predicates = [UseSSE2] in {
2505 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2506 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2507 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2508 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2511 //===----------------------------------------------------------------------===//
2512 // SSE 1 & 2 - Shuffle Instructions
2513 //===----------------------------------------------------------------------===//
2515 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2516 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2517 ValueType vt, string asm, PatFrag mem_frag,
2518 Domain d, bit IsConvertibleToThreeAddress = 0> {
2519 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2520 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2521 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2522 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2523 Sched<[WriteShuffleLd, ReadAfterLd]>;
2524 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2525 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2526 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2527 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2528 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2529 Sched<[WriteShuffle]>;
2532 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2533 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2534 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2535 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2536 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2537 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2538 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2539 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2540 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2541 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2542 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2543 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2545 let Constraints = "$src1 = $dst" in {
2546 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2547 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2548 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2550 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2551 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2552 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2556 let Predicates = [HasAVX] in {
2557 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2558 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2559 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2560 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2561 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2563 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2564 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2565 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2566 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2567 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2570 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2571 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2572 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2573 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2574 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2576 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2577 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2578 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2579 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2580 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2583 let Predicates = [UseSSE1] in {
2584 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2585 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2586 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2587 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2588 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2591 let Predicates = [UseSSE2] in {
2592 // Generic SHUFPD patterns
2593 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2594 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2595 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2596 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2597 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2600 //===----------------------------------------------------------------------===//
2601 // SSE 1 & 2 - Unpack Instructions
2602 //===----------------------------------------------------------------------===//
2604 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2605 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2606 PatFrag mem_frag, RegisterClass RC,
2607 X86MemOperand x86memop, string asm,
2609 def rr : PI<opc, MRMSrcReg,
2610 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2612 (vt (OpNode RC:$src1, RC:$src2)))],
2613 IIC_SSE_UNPCK, d>, Sched<[WriteShuffle]>;
2614 def rm : PI<opc, MRMSrcMem,
2615 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2617 (vt (OpNode RC:$src1,
2618 (mem_frag addr:$src2))))],
2620 Sched<[WriteShuffleLd, ReadAfterLd]>;
2623 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2624 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2625 SSEPackedSingle>, TB, VEX_4V;
2626 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2627 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2628 SSEPackedDouble>, TB, OpSize, VEX_4V;
2629 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2630 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2631 SSEPackedSingle>, TB, VEX_4V;
2632 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2633 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2634 SSEPackedDouble>, TB, OpSize, VEX_4V;
2636 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2637 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2638 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2639 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2640 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2641 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2642 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2643 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2644 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2645 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2646 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2647 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2649 let Constraints = "$src1 = $dst" in {
2650 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2651 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2652 SSEPackedSingle>, TB;
2653 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2654 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2655 SSEPackedDouble>, TB, OpSize;
2656 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2657 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2658 SSEPackedSingle>, TB;
2659 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2660 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2661 SSEPackedDouble>, TB, OpSize;
2662 } // Constraints = "$src1 = $dst"
2664 let Predicates = [HasAVX1Only] in {
2665 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2666 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2667 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2668 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2669 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2670 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2671 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2672 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2674 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2675 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2676 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2677 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2678 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2679 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2680 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2681 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2684 let Predicates = [HasAVX] in {
2685 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2686 // problem is during lowering, where it's not possible to recognize the load
2687 // fold cause it has two uses through a bitcast. One use disappears at isel
2688 // time and the fold opportunity reappears.
2689 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2690 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2693 let Predicates = [UseSSE2] in {
2694 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2695 // problem is during lowering, where it's not possible to recognize the load
2696 // fold cause it has two uses through a bitcast. One use disappears at isel
2697 // time and the fold opportunity reappears.
2698 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2699 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2702 //===----------------------------------------------------------------------===//
2703 // SSE 1 & 2 - Extract Floating-Point Sign mask
2704 //===----------------------------------------------------------------------===//
2706 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2707 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2709 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2710 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2711 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2712 Sched<[WriteVecLogic]>;
2713 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2714 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2715 IIC_SSE_MOVMSK, d>, REX_W, Sched<[WriteVecLogic]>;
2718 let Predicates = [HasAVX] in {
2719 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2720 "movmskps", SSEPackedSingle>, TB, VEX;
2721 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2722 "movmskpd", SSEPackedDouble>, TB,
2724 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2725 "movmskps", SSEPackedSingle>, TB,
2727 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2728 "movmskpd", SSEPackedDouble>, TB,
2731 def : Pat<(i32 (X86fgetsign FR32:$src)),
2732 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2733 def : Pat<(i64 (X86fgetsign FR32:$src)),
2734 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2735 def : Pat<(i32 (X86fgetsign FR64:$src)),
2736 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2737 def : Pat<(i64 (X86fgetsign FR64:$src)),
2738 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2741 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2742 SSEPackedSingle>, TB;
2743 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2744 SSEPackedDouble>, TB, OpSize;
2746 def : Pat<(i32 (X86fgetsign FR32:$src)),
2747 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2748 Requires<[UseSSE1]>;
2749 def : Pat<(i64 (X86fgetsign FR32:$src)),
2750 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2751 Requires<[UseSSE1]>;
2752 def : Pat<(i32 (X86fgetsign FR64:$src)),
2753 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2754 Requires<[UseSSE2]>;
2755 def : Pat<(i64 (X86fgetsign FR64:$src)),
2756 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2757 Requires<[UseSSE2]>;
2759 //===---------------------------------------------------------------------===//
2760 // SSE2 - Packed Integer Logical Instructions
2761 //===---------------------------------------------------------------------===//
2763 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2765 /// PDI_binop_rm - Simple SSE2 binary operator.
2766 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2767 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2768 X86MemOperand x86memop, OpndItins itins,
2769 bit IsCommutable, bit Is2Addr> {
2770 let isCommutable = IsCommutable in
2771 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2772 (ins RC:$src1, RC:$src2),
2774 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2775 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2776 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2777 Sched<[itins.Sched]>;
2778 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2779 (ins RC:$src1, x86memop:$src2),
2781 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2782 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2783 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2784 (bitconvert (memop_frag addr:$src2)))))],
2786 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2788 } // ExeDomain = SSEPackedInt
2790 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2791 ValueType OpVT128, ValueType OpVT256,
2792 OpndItins itins, bit IsCommutable = 0> {
2793 let Predicates = [HasAVX] in
2794 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2795 VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2797 let Constraints = "$src1 = $dst" in
2798 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2799 memopv2i64, i128mem, itins, IsCommutable, 1>;
2801 let Predicates = [HasAVX2] in
2802 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2803 OpVT256, VR256, memopv4i64, i256mem, itins,
2804 IsCommutable, 0>, VEX_4V, VEX_L;
2807 // These are ordered here for pattern ordering requirements with the fp versions
2809 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2810 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2811 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2812 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2813 SSE_BIT_ITINS_P, 0>;
2815 //===----------------------------------------------------------------------===//
2816 // SSE 1 & 2 - Logical Instructions
2817 //===----------------------------------------------------------------------===//
2819 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2821 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2822 SDNode OpNode, OpndItins itins> {
2823 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2824 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2827 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2828 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2831 let Constraints = "$src1 = $dst" in {
2832 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2833 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2836 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2837 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2842 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2843 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2845 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2847 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2850 let isCommutable = 0 in
2851 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2854 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2856 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2858 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2859 !strconcat(OpcodeStr, "ps"), f256mem,
2860 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2861 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2862 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2864 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2865 !strconcat(OpcodeStr, "pd"), f256mem,
2866 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2867 (bc_v4i64 (v4f64 VR256:$src2))))],
2868 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2869 (memopv4i64 addr:$src2)))], 0>,
2870 TB, OpSize, VEX_4V, VEX_L;
2872 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2873 // are all promoted to v2i64, and the patterns are covered by the int
2874 // version. This is needed in SSE only, because v2i64 isn't supported on
2875 // SSE1, but only on SSE2.
2876 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2877 !strconcat(OpcodeStr, "ps"), f128mem, [],
2878 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2879 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2881 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2882 !strconcat(OpcodeStr, "pd"), f128mem,
2883 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2884 (bc_v2i64 (v2f64 VR128:$src2))))],
2885 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2886 (memopv2i64 addr:$src2)))], 0>,
2889 let Constraints = "$src1 = $dst" in {
2890 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2891 !strconcat(OpcodeStr, "ps"), f128mem,
2892 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2893 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2894 (memopv2i64 addr:$src2)))]>, TB;
2896 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2897 !strconcat(OpcodeStr, "pd"), f128mem,
2898 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2899 (bc_v2i64 (v2f64 VR128:$src2))))],
2900 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2901 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2905 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2906 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2907 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2908 let isCommutable = 0 in
2909 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2911 //===----------------------------------------------------------------------===//
2912 // SSE 1 & 2 - Arithmetic Instructions
2913 //===----------------------------------------------------------------------===//
2915 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2918 /// In addition, we also have a special variant of the scalar form here to
2919 /// represent the associated intrinsic operation. This form is unlike the
2920 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2921 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2923 /// These three forms can each be reg+reg or reg+mem.
2926 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2928 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2929 SDNode OpNode, SizeItins itins> {
2930 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2931 VR128, v4f32, f128mem, memopv4f32,
2932 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2933 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2934 VR128, v2f64, f128mem, memopv2f64,
2935 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2937 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2938 OpNode, VR256, v8f32, f256mem, memopv8f32,
2939 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2940 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2941 OpNode, VR256, v4f64, f256mem, memopv4f64,
2942 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2944 let Constraints = "$src1 = $dst" in {
2945 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2946 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2948 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2949 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2950 itins.d>, TB, OpSize;
2954 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2956 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2957 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
2958 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2959 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
2961 let Constraints = "$src1 = $dst" in {
2962 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2963 OpNode, FR32, f32mem, itins.s>, XS;
2964 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2965 OpNode, FR64, f64mem, itins.d>, XD;
2969 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2971 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2972 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2973 itins.s, 0>, XS, VEX_4V, VEX_LIG;
2974 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2975 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2976 itins.d, 0>, XD, VEX_4V, VEX_LIG;
2978 let Constraints = "$src1 = $dst" in {
2979 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2980 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2982 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2983 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2988 // Binary Arithmetic instructions
2989 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2990 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2991 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2992 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2993 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2994 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2995 let isCommutable = 0 in {
2996 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2997 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2998 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2999 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3000 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3001 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3002 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3003 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3004 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3005 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3006 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3007 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3010 let isCodeGenOnly = 1 in {
3011 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3012 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3013 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3014 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3018 /// In addition, we also have a special variant of the scalar form here to
3019 /// represent the associated intrinsic operation. This form is unlike the
3020 /// plain scalar form, in that it takes an entire vector (instead of a
3021 /// scalar) and leaves the top elements undefined.
3023 /// And, we have a special variant form for a full-vector intrinsic form.
3025 let Sched = WriteFSqrt in {
3026 def SSE_SQRTPS : OpndItins<
3027 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3030 def SSE_SQRTSS : OpndItins<
3031 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3034 def SSE_SQRTPD : OpndItins<
3035 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3038 def SSE_SQRTSD : OpndItins<
3039 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3043 let Sched = WriteFRcp in {
3044 def SSE_RCPP : OpndItins<
3045 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3048 def SSE_RCPS : OpndItins<
3049 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3053 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3054 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3055 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3056 let Predicates = [HasAVX], hasSideEffects = 0 in {
3057 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3058 (ins FR32:$src1, FR32:$src2),
3059 !strconcat("v", OpcodeStr,
3060 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3061 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3062 let mayLoad = 1 in {
3063 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3064 (ins FR32:$src1,f32mem:$src2),
3065 !strconcat("v", OpcodeStr,
3066 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3067 []>, VEX_4V, VEX_LIG,
3068 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3069 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3070 (ins VR128:$src1, ssmem:$src2),
3071 !strconcat("v", OpcodeStr,
3072 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3073 []>, VEX_4V, VEX_LIG,
3074 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3078 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3079 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3080 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3081 // For scalar unary operations, fold a load into the operation
3082 // only in OptForSize mode. It eliminates an instruction, but it also
3083 // eliminates a whole-register clobber (the load), so it introduces a
3084 // partial register update condition.
3085 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3086 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3087 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3088 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3089 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3090 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3091 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3092 Sched<[itins.Sched]>;
3093 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3094 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3095 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3096 Sched<[itins.Sched.Folded]>;
3099 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3100 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3102 let Predicates = [HasAVX], hasSideEffects = 0 in {
3103 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3104 (ins FR32:$src1, FR32:$src2),
3105 !strconcat("v", OpcodeStr,
3106 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3107 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3108 let mayLoad = 1 in {
3109 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3110 (ins FR32:$src1,f32mem:$src2),
3111 !strconcat("v", OpcodeStr,
3112 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3113 []>, VEX_4V, VEX_LIG,
3114 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3115 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3116 (ins VR128:$src1, ssmem:$src2),
3117 !strconcat("v", OpcodeStr,
3118 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3119 []>, VEX_4V, VEX_LIG,
3120 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3124 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3125 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3126 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3127 // For scalar unary operations, fold a load into the operation
3128 // only in OptForSize mode. It eliminates an instruction, but it also
3129 // eliminates a whole-register clobber (the load), so it introduces a
3130 // partial register update condition.
3131 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3132 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3133 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3134 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3135 let Constraints = "$src1 = $dst" in {
3136 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3137 (ins VR128:$src1, VR128:$src2),
3138 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3139 [], itins.rr>, Sched<[itins.Sched]>;
3140 let mayLoad = 1, hasSideEffects = 0 in
3141 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3142 (ins VR128:$src1, ssmem:$src2),
3143 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3144 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3148 /// sse1_fp_unop_p - SSE1 unops in packed form.
3149 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3151 let Predicates = [HasAVX] in {
3152 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3153 !strconcat("v", OpcodeStr,
3154 "ps\t{$src, $dst|$dst, $src}"),
3155 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3156 itins.rr>, VEX, Sched<[itins.Sched]>;
3157 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3158 !strconcat("v", OpcodeStr,
3159 "ps\t{$src, $dst|$dst, $src}"),
3160 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))],
3161 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3162 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3163 !strconcat("v", OpcodeStr,
3164 "ps\t{$src, $dst|$dst, $src}"),
3165 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3166 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3167 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3168 !strconcat("v", OpcodeStr,
3169 "ps\t{$src, $dst|$dst, $src}"),
3170 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3171 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3174 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3175 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3176 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3177 Sched<[itins.Sched]>;
3178 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3179 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3180 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3181 Sched<[itins.Sched.Folded]>;
3184 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3185 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3186 Intrinsic V4F32Int, Intrinsic V8F32Int,
3188 let Predicates = [HasAVX] in {
3189 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3190 !strconcat("v", OpcodeStr,
3191 "ps\t{$src, $dst|$dst, $src}"),
3192 [(set VR128:$dst, (V4F32Int VR128:$src))],
3193 itins.rr>, VEX, Sched<[itins.Sched]>;
3194 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3195 !strconcat("v", OpcodeStr,
3196 "ps\t{$src, $dst|$dst, $src}"),
3197 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3198 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3199 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3200 !strconcat("v", OpcodeStr,
3201 "ps\t{$src, $dst|$dst, $src}"),
3202 [(set VR256:$dst, (V8F32Int VR256:$src))],
3203 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3204 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3206 !strconcat("v", OpcodeStr,
3207 "ps\t{$src, $dst|$dst, $src}"),
3208 [(set VR256:$dst, (V8F32Int (memopv8f32 addr:$src)))],
3209 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3212 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3213 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3214 [(set VR128:$dst, (V4F32Int VR128:$src))],
3215 itins.rr>, Sched<[itins.Sched]>;
3216 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3217 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3218 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3219 itins.rm>, Sched<[itins.Sched.Folded]>;
3222 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3223 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3224 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3225 let Predicates = [HasAVX], hasSideEffects = 0 in {
3226 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3227 (ins FR64:$src1, FR64:$src2),
3228 !strconcat("v", OpcodeStr,
3229 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3230 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3231 let mayLoad = 1 in {
3232 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3233 (ins FR64:$src1,f64mem:$src2),
3234 !strconcat("v", OpcodeStr,
3235 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3236 []>, VEX_4V, VEX_LIG,
3237 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3238 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3239 (ins VR128:$src1, sdmem:$src2),
3240 !strconcat("v", OpcodeStr,
3241 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3242 []>, VEX_4V, VEX_LIG,
3243 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3247 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3248 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3249 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3250 Sched<[itins.Sched]>;
3251 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3252 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3253 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3254 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3255 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3256 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3257 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3258 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3259 Sched<[itins.Sched]>;
3260 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3261 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3262 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3263 Sched<[itins.Sched.Folded]>;
3266 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3267 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3268 SDNode OpNode, OpndItins itins> {
3269 let Predicates = [HasAVX] in {
3270 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3271 !strconcat("v", OpcodeStr,
3272 "pd\t{$src, $dst|$dst, $src}"),
3273 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3274 itins.rr>, VEX, Sched<[itins.Sched]>;
3275 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3276 !strconcat("v", OpcodeStr,
3277 "pd\t{$src, $dst|$dst, $src}"),
3278 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))],
3279 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3280 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3281 !strconcat("v", OpcodeStr,
3282 "pd\t{$src, $dst|$dst, $src}"),
3283 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3284 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3285 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3286 !strconcat("v", OpcodeStr,
3287 "pd\t{$src, $dst|$dst, $src}"),
3288 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3289 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3292 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3293 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3294 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3295 Sched<[itins.Sched]>;
3296 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3297 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3298 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3299 Sched<[itins.Sched.Folded]>;
3303 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3305 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3306 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3308 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3310 // Reciprocal approximations. Note that these typically require refinement
3311 // in order to obtain suitable precision.
3312 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3313 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3314 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3315 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3316 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3317 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3318 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3319 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3321 let Predicates = [UseAVX] in {
3322 def : Pat<(f32 (fsqrt FR32:$src)),
3323 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3324 def : Pat<(f32 (fsqrt (load addr:$src))),
3325 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3326 Requires<[HasAVX, OptForSize]>;
3327 def : Pat<(f64 (fsqrt FR64:$src)),
3328 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3329 def : Pat<(f64 (fsqrt (load addr:$src))),
3330 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3331 Requires<[HasAVX, OptForSize]>;
3333 def : Pat<(f32 (X86frsqrt FR32:$src)),
3334 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3335 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3336 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3337 Requires<[HasAVX, OptForSize]>;
3339 def : Pat<(f32 (X86frcp FR32:$src)),
3340 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3341 def : Pat<(f32 (X86frcp (load addr:$src))),
3342 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3343 Requires<[HasAVX, OptForSize]>;
3345 let Predicates = [UseAVX] in {
3346 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3347 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3348 (COPY_TO_REGCLASS VR128:$src, FR32)),
3350 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3351 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3353 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3354 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3355 (COPY_TO_REGCLASS VR128:$src, FR64)),
3357 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3358 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3361 let Predicates = [HasAVX] in {
3362 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3363 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3364 (COPY_TO_REGCLASS VR128:$src, FR32)),
3366 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3367 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3369 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3370 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3371 (COPY_TO_REGCLASS VR128:$src, FR32)),
3373 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3374 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3377 // Reciprocal approximations. Note that these typically require refinement
3378 // in order to obtain suitable precision.
3379 let Predicates = [UseSSE1] in {
3380 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3381 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3382 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3383 (RCPSSr_Int VR128:$src, VR128:$src)>;
3386 // There is no f64 version of the reciprocal approximation instructions.
3388 //===----------------------------------------------------------------------===//
3389 // SSE 1 & 2 - Non-temporal stores
3390 //===----------------------------------------------------------------------===//
3392 let AddedComplexity = 400 in { // Prefer non-temporal versions
3393 let SchedRW = [WriteStore] in {
3394 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3395 (ins f128mem:$dst, VR128:$src),
3396 "movntps\t{$src, $dst|$dst, $src}",
3397 [(alignednontemporalstore (v4f32 VR128:$src),
3399 IIC_SSE_MOVNT>, VEX;
3400 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3401 (ins f128mem:$dst, VR128:$src),
3402 "movntpd\t{$src, $dst|$dst, $src}",
3403 [(alignednontemporalstore (v2f64 VR128:$src),
3405 IIC_SSE_MOVNT>, VEX;
3407 let ExeDomain = SSEPackedInt in
3408 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3409 (ins f128mem:$dst, VR128:$src),
3410 "movntdq\t{$src, $dst|$dst, $src}",
3411 [(alignednontemporalstore (v2i64 VR128:$src),
3413 IIC_SSE_MOVNT>, VEX;
3415 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3416 (ins f256mem:$dst, VR256:$src),
3417 "movntps\t{$src, $dst|$dst, $src}",
3418 [(alignednontemporalstore (v8f32 VR256:$src),
3420 IIC_SSE_MOVNT>, VEX, VEX_L;
3421 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3422 (ins f256mem:$dst, VR256:$src),
3423 "movntpd\t{$src, $dst|$dst, $src}",
3424 [(alignednontemporalstore (v4f64 VR256:$src),
3426 IIC_SSE_MOVNT>, VEX, VEX_L;
3427 let ExeDomain = SSEPackedInt in
3428 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3429 (ins f256mem:$dst, VR256:$src),
3430 "movntdq\t{$src, $dst|$dst, $src}",
3431 [(alignednontemporalstore (v4i64 VR256:$src),
3433 IIC_SSE_MOVNT>, VEX, VEX_L;
3435 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3436 "movntps\t{$src, $dst|$dst, $src}",
3437 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3439 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3440 "movntpd\t{$src, $dst|$dst, $src}",
3441 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3444 let ExeDomain = SSEPackedInt in
3445 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3446 "movntdq\t{$src, $dst|$dst, $src}",
3447 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3450 // There is no AVX form for instructions below this point
3451 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3452 "movnti{l}\t{$src, $dst|$dst, $src}",
3453 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3455 TB, Requires<[HasSSE2]>;
3456 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3457 "movnti{q}\t{$src, $dst|$dst, $src}",
3458 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3460 TB, Requires<[HasSSE2]>;
3461 } // SchedRW = [WriteStore]
3463 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3464 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3466 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3467 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3468 } // AddedComplexity
3470 //===----------------------------------------------------------------------===//
3471 // SSE 1 & 2 - Prefetch and memory fence
3472 //===----------------------------------------------------------------------===//
3474 // Prefetch intrinsic.
3475 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3476 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3477 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3478 IIC_SSE_PREFETCH>, TB;
3479 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3480 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3481 IIC_SSE_PREFETCH>, TB;
3482 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3483 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3484 IIC_SSE_PREFETCH>, TB;
3485 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3486 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3487 IIC_SSE_PREFETCH>, TB;
3490 // FIXME: How should these memory instructions be modeled?
3491 let SchedRW = [WriteLoad] in {
3493 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3494 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3495 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3497 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3498 // was introduced with SSE2, it's backward compatible.
3499 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3501 // Load, store, and memory fence
3502 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3503 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3504 TB, Requires<[HasSSE1]>;
3505 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3506 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3507 TB, Requires<[HasSSE2]>;
3508 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3509 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3510 TB, Requires<[HasSSE2]>;
3513 def : Pat<(X86SFence), (SFENCE)>;
3514 def : Pat<(X86LFence), (LFENCE)>;
3515 def : Pat<(X86MFence), (MFENCE)>;
3517 //===----------------------------------------------------------------------===//
3518 // SSE 1 & 2 - Load/Store XCSR register
3519 //===----------------------------------------------------------------------===//
3521 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3522 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3523 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3524 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3525 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3526 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3528 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3529 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3530 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3531 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3532 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3533 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3535 //===---------------------------------------------------------------------===//
3536 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3537 //===---------------------------------------------------------------------===//
3539 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3541 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3542 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3543 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3545 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3546 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3548 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3549 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3551 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3552 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3557 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
3558 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3559 "movdqa\t{$src, $dst|$dst, $src}", [],
3562 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3563 "movdqa\t{$src, $dst|$dst, $src}", [],
3564 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3565 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3566 "movdqu\t{$src, $dst|$dst, $src}", [],
3569 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3570 "movdqu\t{$src, $dst|$dst, $src}", [],
3571 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3574 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3575 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3576 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3577 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3579 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3580 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3582 let Predicates = [HasAVX] in {
3583 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3584 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3586 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3587 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3592 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3593 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3594 (ins i128mem:$dst, VR128:$src),
3595 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3597 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3598 (ins i256mem:$dst, VR256:$src),
3599 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3601 let Predicates = [HasAVX] in {
3602 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3603 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3605 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3606 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3611 let SchedRW = [WriteMove] in {
3612 let neverHasSideEffects = 1 in
3613 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3614 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3616 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3617 "movdqu\t{$src, $dst|$dst, $src}",
3618 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3621 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3622 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3623 "movdqa\t{$src, $dst|$dst, $src}", [],
3626 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3627 "movdqu\t{$src, $dst|$dst, $src}",
3628 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3632 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3633 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3634 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3635 "movdqa\t{$src, $dst|$dst, $src}",
3636 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3638 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3639 "movdqu\t{$src, $dst|$dst, $src}",
3640 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3642 XS, Requires<[UseSSE2]>;
3645 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3646 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3647 "movdqa\t{$src, $dst|$dst, $src}",
3648 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3650 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3651 "movdqu\t{$src, $dst|$dst, $src}",
3652 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3654 XS, Requires<[UseSSE2]>;
3657 } // ExeDomain = SSEPackedInt
3659 let Predicates = [HasAVX] in {
3660 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3661 (VMOVDQUmr addr:$dst, VR128:$src)>;
3662 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3663 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3665 let Predicates = [UseSSE2] in
3666 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3667 (MOVDQUmr addr:$dst, VR128:$src)>;
3669 //===---------------------------------------------------------------------===//
3670 // SSE2 - Packed Integer Arithmetic Instructions
3671 //===---------------------------------------------------------------------===//
3673 let Sched = WriteVecIMul in
3674 def SSE_PMADD : OpndItins<
3675 IIC_SSE_PMADD, IIC_SSE_PMADD
3678 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3680 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3681 RegisterClass RC, PatFrag memop_frag,
3682 X86MemOperand x86memop,
3684 bit IsCommutable = 0,
3686 let isCommutable = IsCommutable in
3687 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3688 (ins RC:$src1, RC:$src2),
3690 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3691 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3692 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3693 Sched<[itins.Sched]>;
3694 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3695 (ins RC:$src1, x86memop:$src2),
3697 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3698 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3699 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3700 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3703 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3704 Intrinsic IntId256, OpndItins itins,
3705 bit IsCommutable = 0> {
3706 let Predicates = [HasAVX] in
3707 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3708 VR128, memopv2i64, i128mem, itins,
3709 IsCommutable, 0>, VEX_4V;
3711 let Constraints = "$src1 = $dst" in
3712 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3713 i128mem, itins, IsCommutable, 1>;
3715 let Predicates = [HasAVX2] in
3716 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3717 VR256, memopv4i64, i256mem, itins,
3718 IsCommutable, 0>, VEX_4V, VEX_L;
3721 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3722 string OpcodeStr, SDNode OpNode,
3723 SDNode OpNode2, RegisterClass RC,
3724 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3725 ShiftOpndItins itins,
3727 // src2 is always 128-bit
3728 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3729 (ins RC:$src1, VR128:$src2),
3731 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3732 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3733 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3734 itins.rr>, Sched<[WriteVecShift]>;
3735 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3736 (ins RC:$src1, i128mem:$src2),
3738 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3739 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3740 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3741 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
3742 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3743 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3744 (ins RC:$src1, i32i8imm:$src2),
3746 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3747 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3748 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>,
3749 Sched<[WriteVecShift]>;
3752 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3753 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3754 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3755 PatFrag memop_frag, X86MemOperand x86memop,
3757 bit IsCommutable = 0, bit Is2Addr = 1> {
3758 let isCommutable = IsCommutable in
3759 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3760 (ins RC:$src1, RC:$src2),
3762 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3763 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3764 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3765 Sched<[itins.Sched]>;
3766 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3767 (ins RC:$src1, x86memop:$src2),
3769 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3770 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3771 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3772 (bitconvert (memop_frag addr:$src2)))))]>,
3773 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3775 } // ExeDomain = SSEPackedInt
3777 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3778 SSE_INTALU_ITINS_P, 1>;
3779 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3780 SSE_INTALU_ITINS_P, 1>;
3781 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3782 SSE_INTALU_ITINS_P, 1>;
3783 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3784 SSE_INTALUQ_ITINS_P, 1>;
3785 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3786 SSE_INTMUL_ITINS_P, 1>;
3787 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3788 SSE_INTALU_ITINS_P, 0>;
3789 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3790 SSE_INTALU_ITINS_P, 0>;
3791 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3792 SSE_INTALU_ITINS_P, 0>;
3793 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3794 SSE_INTALUQ_ITINS_P, 0>;
3795 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3796 SSE_INTALU_ITINS_P, 0>;
3797 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3798 SSE_INTALU_ITINS_P, 0>;
3799 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3800 SSE_INTALU_ITINS_P, 1>;
3801 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3802 SSE_INTALU_ITINS_P, 1>;
3803 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3804 SSE_INTALU_ITINS_P, 1>;
3805 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3806 SSE_INTALU_ITINS_P, 1>;
3809 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
3810 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
3811 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3812 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
3813 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3814 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
3815 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3816 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
3817 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3818 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
3819 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3820 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
3821 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3822 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
3823 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3824 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
3825 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3826 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
3827 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3828 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
3829 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3830 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
3831 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3832 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
3834 let Predicates = [HasAVX] in
3835 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3836 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3838 let Predicates = [HasAVX2] in
3839 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3840 VR256, memopv4i64, i256mem,
3841 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3842 let Constraints = "$src1 = $dst" in
3843 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3844 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3846 //===---------------------------------------------------------------------===//
3847 // SSE2 - Packed Integer Logical Instructions
3848 //===---------------------------------------------------------------------===//
3850 let Predicates = [HasAVX] in {
3851 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3852 VR128, v8i16, v8i16, bc_v8i16,
3853 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3854 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3855 VR128, v4i32, v4i32, bc_v4i32,
3856 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3857 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3858 VR128, v2i64, v2i64, bc_v2i64,
3859 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3861 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3862 VR128, v8i16, v8i16, bc_v8i16,
3863 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3864 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3865 VR128, v4i32, v4i32, bc_v4i32,
3866 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3867 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3868 VR128, v2i64, v2i64, bc_v2i64,
3869 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3871 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3872 VR128, v8i16, v8i16, bc_v8i16,
3873 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3874 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3875 VR128, v4i32, v4i32, bc_v4i32,
3876 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3878 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3879 // 128-bit logical shifts.
3880 def VPSLLDQri : PDIi8<0x73, MRM7r,
3881 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3882 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3884 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3886 def VPSRLDQri : PDIi8<0x73, MRM3r,
3887 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3888 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3890 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3892 // PSRADQri doesn't exist in SSE[1-3].
3894 } // Predicates = [HasAVX]
3896 let Predicates = [HasAVX2] in {
3897 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3898 VR256, v16i16, v8i16, bc_v8i16,
3899 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3900 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3901 VR256, v8i32, v4i32, bc_v4i32,
3902 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3903 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3904 VR256, v4i64, v2i64, bc_v2i64,
3905 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3907 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3908 VR256, v16i16, v8i16, bc_v8i16,
3909 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3910 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3911 VR256, v8i32, v4i32, bc_v4i32,
3912 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3913 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3914 VR256, v4i64, v2i64, bc_v2i64,
3915 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3917 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3918 VR256, v16i16, v8i16, bc_v8i16,
3919 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3920 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3921 VR256, v8i32, v4i32, bc_v4i32,
3922 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3924 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3925 // 256-bit logical shifts.
3926 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3927 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3928 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3930 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3932 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3933 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3934 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3936 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3938 // PSRADQYri doesn't exist in SSE[1-3].
3940 } // Predicates = [HasAVX2]
3942 let Constraints = "$src1 = $dst" in {
3943 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3944 VR128, v8i16, v8i16, bc_v8i16,
3945 SSE_INTSHIFT_ITINS_P>;
3946 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3947 VR128, v4i32, v4i32, bc_v4i32,
3948 SSE_INTSHIFT_ITINS_P>;
3949 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3950 VR128, v2i64, v2i64, bc_v2i64,
3951 SSE_INTSHIFT_ITINS_P>;
3953 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3954 VR128, v8i16, v8i16, bc_v8i16,
3955 SSE_INTSHIFT_ITINS_P>;
3956 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3957 VR128, v4i32, v4i32, bc_v4i32,
3958 SSE_INTSHIFT_ITINS_P>;
3959 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3960 VR128, v2i64, v2i64, bc_v2i64,
3961 SSE_INTSHIFT_ITINS_P>;
3963 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3964 VR128, v8i16, v8i16, bc_v8i16,
3965 SSE_INTSHIFT_ITINS_P>;
3966 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3967 VR128, v4i32, v4i32, bc_v4i32,
3968 SSE_INTSHIFT_ITINS_P>;
3970 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3971 // 128-bit logical shifts.
3972 def PSLLDQri : PDIi8<0x73, MRM7r,
3973 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3974 "pslldq\t{$src2, $dst|$dst, $src2}",
3976 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
3977 IIC_SSE_INTSHDQ_P_RI>;
3978 def PSRLDQri : PDIi8<0x73, MRM3r,
3979 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3980 "psrldq\t{$src2, $dst|$dst, $src2}",
3982 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
3983 IIC_SSE_INTSHDQ_P_RI>;
3984 // PSRADQri doesn't exist in SSE[1-3].
3986 } // Constraints = "$src1 = $dst"
3988 let Predicates = [HasAVX] in {
3989 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3990 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3991 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3992 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3993 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3994 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3996 // Shift up / down and insert zero's.
3997 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3998 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3999 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4000 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4003 let Predicates = [HasAVX2] in {
4004 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4005 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4006 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4007 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4010 let Predicates = [UseSSE2] in {
4011 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4012 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4013 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4014 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4015 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4016 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4018 // Shift up / down and insert zero's.
4019 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4020 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4021 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4022 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4025 //===---------------------------------------------------------------------===//
4026 // SSE2 - Packed Integer Comparison Instructions
4027 //===---------------------------------------------------------------------===//
4029 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4030 SSE_INTALU_ITINS_P, 1>;
4031 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4032 SSE_INTALU_ITINS_P, 1>;
4033 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4034 SSE_INTALU_ITINS_P, 1>;
4035 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4036 SSE_INTALU_ITINS_P, 0>;
4037 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4038 SSE_INTALU_ITINS_P, 0>;
4039 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4040 SSE_INTALU_ITINS_P, 0>;
4042 //===---------------------------------------------------------------------===//
4043 // SSE2 - Packed Integer Pack Instructions
4044 //===---------------------------------------------------------------------===//
4046 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4047 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
4048 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4049 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
4050 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4051 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
4053 //===---------------------------------------------------------------------===//
4054 // SSE2 - Packed Integer Shuffle Instructions
4055 //===---------------------------------------------------------------------===//
4057 let ExeDomain = SSEPackedInt in {
4058 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4060 let Predicates = [HasAVX] in {
4061 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4062 (ins VR128:$src1, i8imm:$src2),
4063 !strconcat("v", OpcodeStr,
4064 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4066 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4067 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4068 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4069 (ins i128mem:$src1, i8imm:$src2),
4070 !strconcat("v", OpcodeStr,
4071 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4073 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4074 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4075 Sched<[WriteShuffleLd]>;
4078 let Predicates = [HasAVX2] in {
4079 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4080 (ins VR256:$src1, i8imm:$src2),
4081 !strconcat("v", OpcodeStr,
4082 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4084 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4085 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4086 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4087 (ins i256mem:$src1, i8imm:$src2),
4088 !strconcat("v", OpcodeStr,
4089 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4091 (vt256 (OpNode (bitconvert (memopv4i64 addr:$src1)),
4092 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4093 Sched<[WriteShuffleLd]>;
4096 let Predicates = [UseSSE2] in {
4097 def ri : Ii8<0x70, MRMSrcReg,
4098 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4099 !strconcat(OpcodeStr,
4100 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4102 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4103 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4104 def mi : Ii8<0x70, MRMSrcMem,
4105 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4106 !strconcat(OpcodeStr,
4107 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4109 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4110 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4111 Sched<[WriteShuffleLd]>;
4114 } // ExeDomain = SSEPackedInt
4116 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4117 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4118 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4120 let Predicates = [HasAVX] in {
4121 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4122 (VPSHUFDmi addr:$src1, imm:$imm)>;
4123 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4124 (VPSHUFDri VR128:$src1, imm:$imm)>;
4127 let Predicates = [UseSSE2] in {
4128 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4129 (PSHUFDmi addr:$src1, imm:$imm)>;
4130 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4131 (PSHUFDri VR128:$src1, imm:$imm)>;
4134 //===---------------------------------------------------------------------===//
4135 // SSE2 - Packed Integer Unpack Instructions
4136 //===---------------------------------------------------------------------===//
4138 let ExeDomain = SSEPackedInt in {
4139 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4140 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4141 def rr : PDI<opc, MRMSrcReg,
4142 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4144 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4145 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4146 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4147 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4148 def rm : PDI<opc, MRMSrcMem,
4149 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4151 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4152 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4153 [(set VR128:$dst, (OpNode VR128:$src1,
4154 (bc_frag (memopv2i64
4157 Sched<[WriteShuffleLd, ReadAfterLd]>;
4160 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4161 SDNode OpNode, PatFrag bc_frag> {
4162 def Yrr : PDI<opc, MRMSrcReg,
4163 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4164 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4165 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4166 Sched<[WriteShuffle]>;
4167 def Yrm : PDI<opc, MRMSrcMem,
4168 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4169 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4170 [(set VR256:$dst, (OpNode VR256:$src1,
4171 (bc_frag (memopv4i64 addr:$src2))))]>,
4172 Sched<[WriteShuffleLd, ReadAfterLd]>;
4175 let Predicates = [HasAVX] in {
4176 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4177 bc_v16i8, 0>, VEX_4V;
4178 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4179 bc_v8i16, 0>, VEX_4V;
4180 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4181 bc_v4i32, 0>, VEX_4V;
4182 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4183 bc_v2i64, 0>, VEX_4V;
4185 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4186 bc_v16i8, 0>, VEX_4V;
4187 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4188 bc_v8i16, 0>, VEX_4V;
4189 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4190 bc_v4i32, 0>, VEX_4V;
4191 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4192 bc_v2i64, 0>, VEX_4V;
4195 let Predicates = [HasAVX2] in {
4196 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4197 bc_v32i8>, VEX_4V, VEX_L;
4198 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4199 bc_v16i16>, VEX_4V, VEX_L;
4200 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4201 bc_v8i32>, VEX_4V, VEX_L;
4202 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4203 bc_v4i64>, VEX_4V, VEX_L;
4205 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4206 bc_v32i8>, VEX_4V, VEX_L;
4207 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4208 bc_v16i16>, VEX_4V, VEX_L;
4209 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4210 bc_v8i32>, VEX_4V, VEX_L;
4211 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4212 bc_v4i64>, VEX_4V, VEX_L;
4215 let Constraints = "$src1 = $dst" in {
4216 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4218 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4220 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4222 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4225 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4227 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4229 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4231 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4234 } // ExeDomain = SSEPackedInt
4236 //===---------------------------------------------------------------------===//
4237 // SSE2 - Packed Integer Extract and Insert
4238 //===---------------------------------------------------------------------===//
4240 let ExeDomain = SSEPackedInt in {
4241 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4242 def rri : Ii8<0xC4, MRMSrcReg,
4243 (outs VR128:$dst), (ins VR128:$src1,
4244 GR32:$src2, i32i8imm:$src3),
4246 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4247 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4249 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>,
4250 Sched<[WriteShuffle]>;
4251 def rmi : Ii8<0xC4, MRMSrcMem,
4252 (outs VR128:$dst), (ins VR128:$src1,
4253 i16mem:$src2, i32i8imm:$src3),
4255 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4256 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4258 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4259 imm:$src3))], IIC_SSE_PINSRW>,
4260 Sched<[WriteShuffleLd, ReadAfterLd]>;
4264 let Predicates = [HasAVX] in
4265 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4266 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4267 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4268 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4269 imm:$src2))]>, TB, OpSize, VEX,
4270 Sched<[WriteShuffle]>;
4271 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4272 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4273 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4274 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4275 imm:$src2))], IIC_SSE_PEXTRW>,
4276 Sched<[WriteShuffleLd, ReadAfterLd]>;
4279 let Predicates = [HasAVX] in {
4280 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4281 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4282 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4283 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4284 []>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>;
4287 let Constraints = "$src1 = $dst" in
4288 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4290 } // ExeDomain = SSEPackedInt
4292 //===---------------------------------------------------------------------===//
4293 // SSE2 - Packed Mask Creation
4294 //===---------------------------------------------------------------------===//
4296 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4298 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4299 "pmovmskb\t{$src, $dst|$dst, $src}",
4300 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4301 IIC_SSE_MOVMSK>, VEX;
4302 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4303 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4305 let Predicates = [HasAVX2] in {
4306 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4307 "pmovmskb\t{$src, $dst|$dst, $src}",
4308 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4309 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4310 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4313 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4314 "pmovmskb\t{$src, $dst|$dst, $src}",
4315 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4318 } // ExeDomain = SSEPackedInt
4320 //===---------------------------------------------------------------------===//
4321 // SSE2 - Conditional Store
4322 //===---------------------------------------------------------------------===//
4324 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4326 let Uses = [EDI], Predicates = [HasAVX,In32BitMode] in
4327 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4328 (ins VR128:$src, VR128:$mask),
4329 "maskmovdqu\t{$mask, $src|$src, $mask}",
4330 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4331 IIC_SSE_MASKMOV>, VEX;
4332 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4333 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4334 (ins VR128:$src, VR128:$mask),
4335 "maskmovdqu\t{$mask, $src|$src, $mask}",
4336 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4337 IIC_SSE_MASKMOV>, VEX;
4339 let Uses = [EDI], Predicates = [UseSSE2,In32BitMode] in
4340 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4341 "maskmovdqu\t{$mask, $src|$src, $mask}",
4342 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4344 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4345 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4346 "maskmovdqu\t{$mask, $src|$src, $mask}",
4347 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4350 } // ExeDomain = SSEPackedInt
4352 //===---------------------------------------------------------------------===//
4353 // SSE2 - Move Doubleword
4354 //===---------------------------------------------------------------------===//
4356 //===---------------------------------------------------------------------===//
4357 // Move Int Doubleword to Packed Double Int
4359 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4360 "movd\t{$src, $dst|$dst, $src}",
4362 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4363 VEX, Sched<[WriteMove]>;
4364 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4365 "movd\t{$src, $dst|$dst, $src}",
4367 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4369 VEX, Sched<[WriteLoad]>;
4370 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4371 "movq\t{$src, $dst|$dst, $src}",
4373 (v2i64 (scalar_to_vector GR64:$src)))],
4374 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4375 let isCodeGenOnly = 1 in
4376 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4377 "movq\t{$src, $dst|$dst, $src}",
4378 [(set FR64:$dst, (bitconvert GR64:$src))],
4379 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4381 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4382 "movd\t{$src, $dst|$dst, $src}",
4384 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4386 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4387 "movd\t{$src, $dst|$dst, $src}",
4389 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4390 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4391 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4392 "mov{d|q}\t{$src, $dst|$dst, $src}",
4394 (v2i64 (scalar_to_vector GR64:$src)))],
4395 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4396 let isCodeGenOnly = 1 in
4397 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4398 "mov{d|q}\t{$src, $dst|$dst, $src}",
4399 [(set FR64:$dst, (bitconvert GR64:$src))],
4400 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4402 //===---------------------------------------------------------------------===//
4403 // Move Int Doubleword to Single Scalar
4405 let isCodeGenOnly = 1 in {
4406 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4407 "movd\t{$src, $dst|$dst, $src}",
4408 [(set FR32:$dst, (bitconvert GR32:$src))],
4409 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4411 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4412 "movd\t{$src, $dst|$dst, $src}",
4413 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4415 VEX, Sched<[WriteLoad]>;
4416 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4417 "movd\t{$src, $dst|$dst, $src}",
4418 [(set FR32:$dst, (bitconvert GR32:$src))],
4419 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4421 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4422 "movd\t{$src, $dst|$dst, $src}",
4423 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4424 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4427 //===---------------------------------------------------------------------===//
4428 // Move Packed Doubleword Int to Packed Double Int
4430 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4431 "movd\t{$src, $dst|$dst, $src}",
4432 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4433 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4435 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4436 (ins i32mem:$dst, VR128:$src),
4437 "movd\t{$src, $dst|$dst, $src}",
4438 [(store (i32 (vector_extract (v4i32 VR128:$src),
4439 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4440 VEX, Sched<[WriteLoad]>;
4441 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4442 "movd\t{$src, $dst|$dst, $src}",
4443 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4444 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4446 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4447 "movd\t{$src, $dst|$dst, $src}",
4448 [(store (i32 (vector_extract (v4i32 VR128:$src),
4449 (iPTR 0))), addr:$dst)],
4450 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4452 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4453 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4455 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4456 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4458 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4459 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4461 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4462 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4464 //===---------------------------------------------------------------------===//
4465 // Move Packed Doubleword Int first element to Doubleword Int
4467 let SchedRW = [WriteMove] in {
4468 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4469 "movq\t{$src, $dst|$dst, $src}",
4470 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4475 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4476 "mov{d|q}\t{$src, $dst|$dst, $src}",
4477 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4482 //===---------------------------------------------------------------------===//
4483 // Bitcast FR64 <-> GR64
4485 let isCodeGenOnly = 1 in {
4486 let Predicates = [UseAVX] in
4487 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4488 "movq\t{$src, $dst|$dst, $src}",
4489 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4490 VEX, Sched<[WriteLoad]>;
4491 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4492 "movq\t{$src, $dst|$dst, $src}",
4493 [(set GR64:$dst, (bitconvert FR64:$src))],
4494 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4495 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4496 "movq\t{$src, $dst|$dst, $src}",
4497 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4498 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4500 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4501 "movq\t{$src, $dst|$dst, $src}",
4502 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4503 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4504 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4505 "mov{d|q}\t{$src, $dst|$dst, $src}",
4506 [(set GR64:$dst, (bitconvert FR64:$src))],
4507 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4508 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4509 "movq\t{$src, $dst|$dst, $src}",
4510 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4511 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4514 //===---------------------------------------------------------------------===//
4515 // Move Scalar Single to Double Int
4517 let isCodeGenOnly = 1 in {
4518 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4519 "movd\t{$src, $dst|$dst, $src}",
4520 [(set GR32:$dst, (bitconvert FR32:$src))],
4521 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4522 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4523 "movd\t{$src, $dst|$dst, $src}",
4524 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4525 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4526 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4527 "movd\t{$src, $dst|$dst, $src}",
4528 [(set GR32:$dst, (bitconvert FR32:$src))],
4529 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4530 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4531 "movd\t{$src, $dst|$dst, $src}",
4532 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4533 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4536 //===---------------------------------------------------------------------===//
4537 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4539 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4540 let AddedComplexity = 15 in {
4541 def VMOVZDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4542 "movd\t{$src, $dst|$dst, $src}",
4543 [(set VR128:$dst, (v4i32 (X86vzmovl
4544 (v4i32 (scalar_to_vector GR32:$src)))))],
4545 IIC_SSE_MOVDQ>, VEX;
4546 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4547 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4548 [(set VR128:$dst, (v2i64 (X86vzmovl
4549 (v2i64 (scalar_to_vector GR64:$src)))))],
4553 let AddedComplexity = 15 in {
4554 def MOVZDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4555 "movd\t{$src, $dst|$dst, $src}",
4556 [(set VR128:$dst, (v4i32 (X86vzmovl
4557 (v4i32 (scalar_to_vector GR32:$src)))))],
4559 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4560 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4561 [(set VR128:$dst, (v2i64 (X86vzmovl
4562 (v2i64 (scalar_to_vector GR64:$src)))))],
4565 } // isCodeGenOnly, SchedRW
4567 let isCodeGenOnly = 1, AddedComplexity = 20, SchedRW = [WriteLoad] in {
4568 def VMOVZDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4569 "movd\t{$src, $dst|$dst, $src}",
4571 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4572 (loadi32 addr:$src))))))],
4573 IIC_SSE_MOVDQ>, VEX;
4574 def MOVZDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4575 "movd\t{$src, $dst|$dst, $src}",
4577 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4578 (loadi32 addr:$src))))))],
4580 } // isCodeGenOnly, AddedComplexity, SchedRW
4582 let Predicates = [UseAVX] in {
4583 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4584 let AddedComplexity = 20 in {
4585 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4586 (VMOVZDI2PDIrm addr:$src)>;
4587 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4588 (VMOVZDI2PDIrm addr:$src)>;
4590 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4591 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4592 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4593 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4594 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4595 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4596 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4599 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4600 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4601 (MOVZDI2PDIrm addr:$src)>;
4602 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4603 (MOVZDI2PDIrm addr:$src)>;
4606 // These are the correct encodings of the instructions so that we know how to
4607 // read correct assembly, even though we continue to emit the wrong ones for
4608 // compatibility with Darwin's buggy assembler.
4609 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4610 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4611 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4612 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4613 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4614 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4615 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4616 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4617 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4619 //===---------------------------------------------------------------------===//
4620 // SSE2 - Move Quadword
4621 //===---------------------------------------------------------------------===//
4623 //===---------------------------------------------------------------------===//
4624 // Move Quadword Int to Packed Quadword Int
4627 let SchedRW = [WriteLoad] in {
4628 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4629 "vmovq\t{$src, $dst|$dst, $src}",
4631 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4632 VEX, Requires<[UseAVX]>;
4633 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4634 "movq\t{$src, $dst|$dst, $src}",
4636 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4638 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4641 //===---------------------------------------------------------------------===//
4642 // Move Packed Quadword Int to Quadword Int
4644 let SchedRW = [WriteStore] in {
4645 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4646 "movq\t{$src, $dst|$dst, $src}",
4647 [(store (i64 (vector_extract (v2i64 VR128:$src),
4648 (iPTR 0))), addr:$dst)],
4649 IIC_SSE_MOVDQ>, VEX;
4650 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4651 "movq\t{$src, $dst|$dst, $src}",
4652 [(store (i64 (vector_extract (v2i64 VR128:$src),
4653 (iPTR 0))), addr:$dst)],
4657 //===---------------------------------------------------------------------===//
4658 // Store / copy lower 64-bits of a XMM register.
4660 def VMOVLQ128mr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4661 "movq\t{$src, $dst|$dst, $src}",
4662 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX,
4663 Sched<[WriteStore]>;
4664 def MOVLQ128mr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4665 "movq\t{$src, $dst|$dst, $src}",
4666 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4667 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4669 let isCodeGenOnly = 1, AddedComplexity = 20 in {
4670 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4671 "vmovq\t{$src, $dst|$dst, $src}",
4673 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4674 (loadi64 addr:$src))))))],
4676 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
4678 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4679 "movq\t{$src, $dst|$dst, $src}",
4681 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4682 (loadi64 addr:$src))))))],
4684 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4687 let Predicates = [UseAVX], AddedComplexity = 20 in {
4688 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4689 (VMOVZQI2PQIrm addr:$src)>;
4690 def : Pat<(v2i64 (X86vzload addr:$src)),
4691 (VMOVZQI2PQIrm addr:$src)>;
4694 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4695 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4696 (MOVZQI2PQIrm addr:$src)>;
4697 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4700 let Predicates = [HasAVX] in {
4701 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4702 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4703 def : Pat<(v4i64 (X86vzload addr:$src)),
4704 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4707 //===---------------------------------------------------------------------===//
4708 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4709 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4711 let SchedRW = [WriteVecLogic] in {
4712 let AddedComplexity = 15 in
4713 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4714 "vmovq\t{$src, $dst|$dst, $src}",
4715 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4717 XS, VEX, Requires<[UseAVX]>;
4718 let AddedComplexity = 15 in
4719 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4720 "movq\t{$src, $dst|$dst, $src}",
4721 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4723 XS, Requires<[UseSSE2]>;
4726 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
4727 let AddedComplexity = 20 in
4728 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4729 "vmovq\t{$src, $dst|$dst, $src}",
4730 [(set VR128:$dst, (v2i64 (X86vzmovl
4731 (loadv2i64 addr:$src))))],
4733 XS, VEX, Requires<[UseAVX]>;
4734 let AddedComplexity = 20 in {
4735 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4736 "movq\t{$src, $dst|$dst, $src}",
4737 [(set VR128:$dst, (v2i64 (X86vzmovl
4738 (loadv2i64 addr:$src))))],
4740 XS, Requires<[UseSSE2]>;
4742 } // isCodeGenOnly, SchedRW
4744 let AddedComplexity = 20 in {
4745 let Predicates = [UseAVX] in {
4746 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4747 (VMOVZPQILo2PQIrr VR128:$src)>;
4749 let Predicates = [UseSSE2] in {
4750 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4751 (MOVZPQILo2PQIrr VR128:$src)>;
4755 //===---------------------------------------------------------------------===//
4756 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4757 //===---------------------------------------------------------------------===//
4758 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4759 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4760 X86MemOperand x86memop> {
4761 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4763 [(set RC:$dst, (vt (OpNode RC:$src)))],
4764 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4765 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4766 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4767 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4768 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4771 let Predicates = [HasAVX] in {
4772 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4773 v4f32, VR128, memopv4f32, f128mem>, VEX;
4774 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4775 v4f32, VR128, memopv4f32, f128mem>, VEX;
4776 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4777 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4778 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4779 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4781 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4782 memopv4f32, f128mem>;
4783 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4784 memopv4f32, f128mem>;
4786 let Predicates = [HasAVX] in {
4787 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4788 (VMOVSHDUPrr VR128:$src)>;
4789 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4790 (VMOVSHDUPrm addr:$src)>;
4791 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4792 (VMOVSLDUPrr VR128:$src)>;
4793 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4794 (VMOVSLDUPrm addr:$src)>;
4795 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4796 (VMOVSHDUPYrr VR256:$src)>;
4797 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4798 (VMOVSHDUPYrm addr:$src)>;
4799 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4800 (VMOVSLDUPYrr VR256:$src)>;
4801 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4802 (VMOVSLDUPYrm addr:$src)>;
4805 let Predicates = [UseSSE3] in {
4806 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4807 (MOVSHDUPrr VR128:$src)>;
4808 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4809 (MOVSHDUPrm addr:$src)>;
4810 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4811 (MOVSLDUPrr VR128:$src)>;
4812 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4813 (MOVSLDUPrm addr:$src)>;
4816 //===---------------------------------------------------------------------===//
4817 // SSE3 - Replicate Double FP - MOVDDUP
4818 //===---------------------------------------------------------------------===//
4820 multiclass sse3_replicate_dfp<string OpcodeStr> {
4821 let neverHasSideEffects = 1 in
4822 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4823 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4824 [], IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4825 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4826 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4829 (scalar_to_vector (loadf64 addr:$src)))))],
4830 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4833 // FIXME: Merge with above classe when there're patterns for the ymm version
4834 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4835 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4836 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4837 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
4838 Sched<[WriteShuffle]>;
4839 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4840 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4843 (scalar_to_vector (loadf64 addr:$src)))))]>,
4844 Sched<[WriteShuffleLd]>;
4847 let Predicates = [HasAVX] in {
4848 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4849 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4852 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4854 let Predicates = [HasAVX] in {
4855 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4856 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4857 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4858 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4859 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4860 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4861 def : Pat<(X86Movddup (bc_v2f64
4862 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4863 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4866 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4867 (VMOVDDUPYrm addr:$src)>;
4868 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4869 (VMOVDDUPYrm addr:$src)>;
4870 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4871 (VMOVDDUPYrm addr:$src)>;
4872 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4873 (VMOVDDUPYrr VR256:$src)>;
4876 let Predicates = [UseSSE3] in {
4877 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4878 (MOVDDUPrm addr:$src)>;
4879 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4880 (MOVDDUPrm addr:$src)>;
4881 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4882 (MOVDDUPrm addr:$src)>;
4883 def : Pat<(X86Movddup (bc_v2f64
4884 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4885 (MOVDDUPrm addr:$src)>;
4888 //===---------------------------------------------------------------------===//
4889 // SSE3 - Move Unaligned Integer
4890 //===---------------------------------------------------------------------===//
4892 let SchedRW = [WriteLoad] in {
4893 let Predicates = [HasAVX] in {
4894 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4895 "vlddqu\t{$src, $dst|$dst, $src}",
4896 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4897 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4898 "vlddqu\t{$src, $dst|$dst, $src}",
4899 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
4902 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4903 "lddqu\t{$src, $dst|$dst, $src}",
4904 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4908 //===---------------------------------------------------------------------===//
4909 // SSE3 - Arithmetic
4910 //===---------------------------------------------------------------------===//
4912 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4913 X86MemOperand x86memop, OpndItins itins,
4915 def rr : I<0xD0, MRMSrcReg,
4916 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4918 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4919 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4920 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
4921 Sched<[itins.Sched]>;
4922 def rm : I<0xD0, MRMSrcMem,
4923 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4925 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4926 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4927 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
4928 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4931 let Predicates = [HasAVX] in {
4932 let ExeDomain = SSEPackedSingle in {
4933 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4934 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
4935 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4936 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
4938 let ExeDomain = SSEPackedDouble in {
4939 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4940 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
4941 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4942 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
4945 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
4946 let ExeDomain = SSEPackedSingle in
4947 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4948 f128mem, SSE_ALU_F32P>, TB, XD;
4949 let ExeDomain = SSEPackedDouble in
4950 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4951 f128mem, SSE_ALU_F64P>, TB, OpSize;
4954 //===---------------------------------------------------------------------===//
4955 // SSE3 Instructions
4956 //===---------------------------------------------------------------------===//
4959 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4960 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4961 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4963 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4964 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4965 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
4968 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4970 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4971 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4972 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4973 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
4975 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4976 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4977 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4979 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4980 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4981 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
4984 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4986 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4987 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4988 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4989 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
4992 let Predicates = [HasAVX] in {
4993 let ExeDomain = SSEPackedSingle in {
4994 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4995 X86fhadd, 0>, VEX_4V;
4996 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4997 X86fhsub, 0>, VEX_4V;
4998 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4999 X86fhadd, 0>, VEX_4V, VEX_L;
5000 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5001 X86fhsub, 0>, VEX_4V, VEX_L;
5003 let ExeDomain = SSEPackedDouble in {
5004 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5005 X86fhadd, 0>, VEX_4V;
5006 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5007 X86fhsub, 0>, VEX_4V;
5008 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5009 X86fhadd, 0>, VEX_4V, VEX_L;
5010 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5011 X86fhsub, 0>, VEX_4V, VEX_L;
5015 let Constraints = "$src1 = $dst" in {
5016 let ExeDomain = SSEPackedSingle in {
5017 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5018 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5020 let ExeDomain = SSEPackedDouble in {
5021 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5022 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5026 //===---------------------------------------------------------------------===//
5027 // SSSE3 - Packed Absolute Instructions
5028 //===---------------------------------------------------------------------===//
5031 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5032 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5033 Intrinsic IntId128> {
5034 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5036 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5037 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5038 OpSize, Sched<[WriteVecALU]>;
5040 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5042 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5045 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5046 OpSize, Sched<[WriteVecALULd]>;
5049 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5050 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5051 Intrinsic IntId256> {
5052 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5054 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5055 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5056 OpSize, Sched<[WriteVecALU]>;
5058 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5060 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5063 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5064 Sched<[WriteVecALULd]>;
5067 // Helper fragments to match sext vXi1 to vXiY.
5068 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5070 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i32 15)))>;
5071 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i32 31)))>;
5072 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5074 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i32 15)))>;
5075 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i32 31)))>;
5077 let Predicates = [HasAVX] in {
5078 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5079 int_x86_ssse3_pabs_b_128>, VEX;
5080 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5081 int_x86_ssse3_pabs_w_128>, VEX;
5082 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5083 int_x86_ssse3_pabs_d_128>, VEX;
5086 (bc_v2i64 (v16i1sextv16i8)),
5087 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5088 (VPABSBrr128 VR128:$src)>;
5090 (bc_v2i64 (v8i1sextv8i16)),
5091 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5092 (VPABSWrr128 VR128:$src)>;
5094 (bc_v2i64 (v4i1sextv4i32)),
5095 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5096 (VPABSDrr128 VR128:$src)>;
5099 let Predicates = [HasAVX2] in {
5100 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5101 int_x86_avx2_pabs_b>, VEX, VEX_L;
5102 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5103 int_x86_avx2_pabs_w>, VEX, VEX_L;
5104 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5105 int_x86_avx2_pabs_d>, VEX, VEX_L;
5108 (bc_v4i64 (v32i1sextv32i8)),
5109 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5110 (VPABSBrr256 VR256:$src)>;
5112 (bc_v4i64 (v16i1sextv16i16)),
5113 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5114 (VPABSWrr256 VR256:$src)>;
5116 (bc_v4i64 (v8i1sextv8i32)),
5117 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5118 (VPABSDrr256 VR256:$src)>;
5121 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5122 int_x86_ssse3_pabs_b_128>;
5123 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5124 int_x86_ssse3_pabs_w_128>;
5125 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5126 int_x86_ssse3_pabs_d_128>;
5128 let Predicates = [HasSSSE3] in {
5130 (bc_v2i64 (v16i1sextv16i8)),
5131 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5132 (PABSBrr128 VR128:$src)>;
5134 (bc_v2i64 (v8i1sextv8i16)),
5135 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5136 (PABSWrr128 VR128:$src)>;
5138 (bc_v2i64 (v4i1sextv4i32)),
5139 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5140 (PABSDrr128 VR128:$src)>;
5143 //===---------------------------------------------------------------------===//
5144 // SSSE3 - Packed Binary Operator Instructions
5145 //===---------------------------------------------------------------------===//
5147 let Sched = WriteVecALU in {
5148 def SSE_PHADDSUBD : OpndItins<
5149 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5151 def SSE_PHADDSUBSW : OpndItins<
5152 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5154 def SSE_PHADDSUBW : OpndItins<
5155 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5158 let Sched = WriteShuffle in
5159 def SSE_PSHUFB : OpndItins<
5160 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5162 let Sched = WriteVecALU in
5163 def SSE_PSIGN : OpndItins<
5164 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5166 let Sched = WriteVecIMul in
5167 def SSE_PMULHRSW : OpndItins<
5168 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5171 /// SS3I_binop_rm - Simple SSSE3 bin op
5172 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5173 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5174 X86MemOperand x86memop, OpndItins itins,
5176 let isCommutable = 1 in
5177 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5178 (ins RC:$src1, RC:$src2),
5180 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5181 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5182 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5183 OpSize, Sched<[itins.Sched]>;
5184 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5185 (ins RC:$src1, x86memop:$src2),
5187 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5188 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5190 (OpVT (OpNode RC:$src1,
5191 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5192 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5195 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5196 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5197 Intrinsic IntId128, OpndItins itins,
5199 let isCommutable = 1 in
5200 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5201 (ins VR128:$src1, VR128:$src2),
5203 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5204 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5205 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5206 OpSize, Sched<[itins.Sched]>;
5207 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5208 (ins VR128:$src1, i128mem:$src2),
5210 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5211 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5213 (IntId128 VR128:$src1,
5214 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5215 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5218 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5219 Intrinsic IntId256> {
5220 let isCommutable = 1 in
5221 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5222 (ins VR256:$src1, VR256:$src2),
5223 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5224 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5226 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5227 (ins VR256:$src1, i256mem:$src2),
5228 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5230 (IntId256 VR256:$src1,
5231 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5234 let ImmT = NoImm, Predicates = [HasAVX] in {
5235 let isCommutable = 0 in {
5236 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5237 memopv2i64, i128mem,
5238 SSE_PHADDSUBW, 0>, VEX_4V;
5239 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5240 memopv2i64, i128mem,
5241 SSE_PHADDSUBD, 0>, VEX_4V;
5242 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5243 memopv2i64, i128mem,
5244 SSE_PHADDSUBW, 0>, VEX_4V;
5245 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5246 memopv2i64, i128mem,
5247 SSE_PHADDSUBD, 0>, VEX_4V;
5248 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5249 memopv2i64, i128mem,
5250 SSE_PSIGN, 0>, VEX_4V;
5251 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5252 memopv2i64, i128mem,
5253 SSE_PSIGN, 0>, VEX_4V;
5254 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5255 memopv2i64, i128mem,
5256 SSE_PSIGN, 0>, VEX_4V;
5257 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5258 memopv2i64, i128mem,
5259 SSE_PSHUFB, 0>, VEX_4V;
5260 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5261 int_x86_ssse3_phadd_sw_128,
5262 SSE_PHADDSUBSW, 0>, VEX_4V;
5263 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5264 int_x86_ssse3_phsub_sw_128,
5265 SSE_PHADDSUBSW, 0>, VEX_4V;
5266 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5267 int_x86_ssse3_pmadd_ub_sw_128,
5268 SSE_PMADD, 0>, VEX_4V;
5270 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5271 int_x86_ssse3_pmul_hr_sw_128,
5272 SSE_PMULHRSW, 0>, VEX_4V;
5275 let ImmT = NoImm, Predicates = [HasAVX2] in {
5276 let isCommutable = 0 in {
5277 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5278 memopv4i64, i256mem,
5279 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5280 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5281 memopv4i64, i256mem,
5282 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5283 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5284 memopv4i64, i256mem,
5285 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5286 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5287 memopv4i64, i256mem,
5288 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5289 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5290 memopv4i64, i256mem,
5291 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5292 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5293 memopv4i64, i256mem,
5294 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5295 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5296 memopv4i64, i256mem,
5297 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5298 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5299 memopv4i64, i256mem,
5300 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5301 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5302 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5303 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5304 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5305 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5306 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5308 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5309 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5312 // None of these have i8 immediate fields.
5313 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5314 let isCommutable = 0 in {
5315 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5316 memopv2i64, i128mem, SSE_PHADDSUBW>;
5317 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5318 memopv2i64, i128mem, SSE_PHADDSUBD>;
5319 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5320 memopv2i64, i128mem, SSE_PHADDSUBW>;
5321 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5322 memopv2i64, i128mem, SSE_PHADDSUBD>;
5323 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5324 memopv2i64, i128mem, SSE_PSIGN>;
5325 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5326 memopv2i64, i128mem, SSE_PSIGN>;
5327 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5328 memopv2i64, i128mem, SSE_PSIGN>;
5329 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5330 memopv2i64, i128mem, SSE_PSHUFB>;
5331 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5332 int_x86_ssse3_phadd_sw_128,
5334 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5335 int_x86_ssse3_phsub_sw_128,
5337 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5338 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5340 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5341 int_x86_ssse3_pmul_hr_sw_128,
5345 //===---------------------------------------------------------------------===//
5346 // SSSE3 - Packed Align Instruction Patterns
5347 //===---------------------------------------------------------------------===//
5349 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5350 let neverHasSideEffects = 1 in {
5351 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5352 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5354 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5356 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5357 [], IIC_SSE_PALIGNRR>, OpSize, Sched<[WriteShuffle]>;
5359 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5360 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5362 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5364 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5365 [], IIC_SSE_PALIGNRM>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5369 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5370 let neverHasSideEffects = 1 in {
5371 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5372 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5374 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5375 []>, OpSize, Sched<[WriteShuffle]>;
5377 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5378 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5380 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5381 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5385 let Predicates = [HasAVX] in
5386 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5387 let Predicates = [HasAVX2] in
5388 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5389 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5390 defm PALIGN : ssse3_palignr<"palignr">;
5392 let Predicates = [HasAVX2] in {
5393 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5394 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5395 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5396 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5397 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5398 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5399 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5400 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5403 let Predicates = [HasAVX] in {
5404 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5405 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5406 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5407 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5408 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5409 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5410 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5411 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5414 let Predicates = [UseSSSE3] in {
5415 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5416 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5417 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5418 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5419 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5420 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5421 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5422 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5425 //===---------------------------------------------------------------------===//
5426 // SSSE3 - Thread synchronization
5427 //===---------------------------------------------------------------------===//
5429 let SchedRW = [WriteSystem] in {
5430 let usesCustomInserter = 1 in {
5431 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5432 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5433 Requires<[HasSSE3]>;
5436 let Uses = [EAX, ECX, EDX] in
5437 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5438 TB, Requires<[HasSSE3]>;
5439 let Uses = [ECX, EAX] in
5440 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5441 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5442 TB, Requires<[HasSSE3]>;
5445 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[In32BitMode]>;
5446 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5448 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5449 Requires<[In32BitMode]>;
5450 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5451 Requires<[In64BitMode]>;
5453 //===----------------------------------------------------------------------===//
5454 // SSE4.1 - Packed Move with Sign/Zero Extend
5455 //===----------------------------------------------------------------------===//
5457 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5458 OpndItins itins = DEFAULT_ITINS> {
5459 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5460 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5461 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5463 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5464 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5466 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5470 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5472 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5473 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5474 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5476 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5477 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5478 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5482 let Predicates = [HasAVX] in {
5483 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5484 int_x86_sse41_pmovsxbw>, VEX;
5485 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5486 int_x86_sse41_pmovsxwd>, VEX;
5487 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5488 int_x86_sse41_pmovsxdq>, VEX;
5489 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5490 int_x86_sse41_pmovzxbw>, VEX;
5491 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5492 int_x86_sse41_pmovzxwd>, VEX;
5493 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5494 int_x86_sse41_pmovzxdq>, VEX;
5497 let Predicates = [HasAVX2] in {
5498 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5499 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5500 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5501 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5502 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5503 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5504 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5505 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5506 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5507 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5508 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5509 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5512 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw, SSE_INTALU_ITINS_P>;
5513 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd, SSE_INTALU_ITINS_P>;
5514 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq, SSE_INTALU_ITINS_P>;
5515 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw, SSE_INTALU_ITINS_P>;
5516 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd, SSE_INTALU_ITINS_P>;
5517 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq, SSE_INTALU_ITINS_P>;
5519 let Predicates = [HasAVX] in {
5520 // Common patterns involving scalar load.
5521 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5522 (VPMOVSXBWrm addr:$src)>;
5523 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5524 (VPMOVSXBWrm addr:$src)>;
5525 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5526 (VPMOVSXBWrm addr:$src)>;
5528 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5529 (VPMOVSXWDrm addr:$src)>;
5530 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5531 (VPMOVSXWDrm addr:$src)>;
5532 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5533 (VPMOVSXWDrm addr:$src)>;
5535 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5536 (VPMOVSXDQrm addr:$src)>;
5537 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5538 (VPMOVSXDQrm addr:$src)>;
5539 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5540 (VPMOVSXDQrm addr:$src)>;
5542 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5543 (VPMOVZXBWrm addr:$src)>;
5544 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5545 (VPMOVZXBWrm addr:$src)>;
5546 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5547 (VPMOVZXBWrm addr:$src)>;
5549 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5550 (VPMOVZXWDrm addr:$src)>;
5551 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5552 (VPMOVZXWDrm addr:$src)>;
5553 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5554 (VPMOVZXWDrm addr:$src)>;
5556 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5557 (VPMOVZXDQrm addr:$src)>;
5558 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5559 (VPMOVZXDQrm addr:$src)>;
5560 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5561 (VPMOVZXDQrm addr:$src)>;
5564 let Predicates = [UseSSE41] in {
5565 // Common patterns involving scalar load.
5566 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5567 (PMOVSXBWrm addr:$src)>;
5568 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5569 (PMOVSXBWrm addr:$src)>;
5570 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5571 (PMOVSXBWrm addr:$src)>;
5573 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5574 (PMOVSXWDrm addr:$src)>;
5575 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5576 (PMOVSXWDrm addr:$src)>;
5577 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5578 (PMOVSXWDrm addr:$src)>;
5580 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5581 (PMOVSXDQrm addr:$src)>;
5582 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5583 (PMOVSXDQrm addr:$src)>;
5584 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5585 (PMOVSXDQrm addr:$src)>;
5587 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5588 (PMOVZXBWrm addr:$src)>;
5589 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5590 (PMOVZXBWrm addr:$src)>;
5591 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5592 (PMOVZXBWrm addr:$src)>;
5594 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5595 (PMOVZXWDrm addr:$src)>;
5596 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5597 (PMOVZXWDrm addr:$src)>;
5598 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5599 (PMOVZXWDrm addr:$src)>;
5601 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5602 (PMOVZXDQrm addr:$src)>;
5603 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5604 (PMOVZXDQrm addr:$src)>;
5605 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5606 (PMOVZXDQrm addr:$src)>;
5609 let Predicates = [HasAVX2] in {
5610 let AddedComplexity = 15 in {
5611 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5612 (VPMOVZXDQYrr VR128:$src)>;
5613 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5614 (VPMOVZXWDYrr VR128:$src)>;
5617 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5618 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5621 let Predicates = [HasAVX] in {
5622 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5623 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5626 let Predicates = [UseSSE41] in {
5627 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5628 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5632 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5633 OpndItins itins = DEFAULT_ITINS> {
5634 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5635 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5636 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5638 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5639 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5641 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
5646 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5648 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5649 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5650 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5652 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5653 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5655 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5659 let Predicates = [HasAVX] in {
5660 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5662 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5664 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5666 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5670 let Predicates = [HasAVX2] in {
5671 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5672 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5673 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5674 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5675 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5676 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5677 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5678 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5681 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
5682 SSE_INTALU_ITINS_P>;
5683 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
5684 SSE_INTALU_ITINS_P>;
5685 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
5686 SSE_INTALU_ITINS_P>;
5687 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
5688 SSE_INTALU_ITINS_P>;
5690 let Predicates = [HasAVX] in {
5691 // Common patterns involving scalar load
5692 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5693 (VPMOVSXBDrm addr:$src)>;
5694 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5695 (VPMOVSXWQrm addr:$src)>;
5697 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5698 (VPMOVZXBDrm addr:$src)>;
5699 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5700 (VPMOVZXWQrm addr:$src)>;
5703 let Predicates = [UseSSE41] in {
5704 // Common patterns involving scalar load
5705 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5706 (PMOVSXBDrm addr:$src)>;
5707 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5708 (PMOVSXWQrm addr:$src)>;
5710 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5711 (PMOVZXBDrm addr:$src)>;
5712 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5713 (PMOVZXWQrm addr:$src)>;
5716 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5717 OpndItins itins = DEFAULT_ITINS> {
5718 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5719 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5720 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5722 // Expecting a i16 load any extended to i32 value.
5723 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5724 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5725 [(set VR128:$dst, (IntId (bitconvert
5726 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5730 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5732 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5733 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5734 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5736 // Expecting a i16 load any extended to i32 value.
5737 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5738 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5739 [(set VR256:$dst, (IntId (bitconvert
5740 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5744 let Predicates = [HasAVX] in {
5745 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5747 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5750 let Predicates = [HasAVX2] in {
5751 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5752 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5753 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5754 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5756 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
5757 SSE_INTALU_ITINS_P>;
5758 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
5759 SSE_INTALU_ITINS_P>;
5761 let Predicates = [HasAVX2] in {
5762 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5763 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5764 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
5766 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5767 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
5769 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5771 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
5772 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5773 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
5774 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5775 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
5776 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5778 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
5779 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5780 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
5781 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5783 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
5784 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5786 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5787 (VPMOVSXWDYrm addr:$src)>;
5788 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5789 (VPMOVSXDQYrm addr:$src)>;
5791 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5792 (scalar_to_vector (loadi64 addr:$src))))))),
5793 (VPMOVSXBDYrm addr:$src)>;
5794 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5795 (scalar_to_vector (loadf64 addr:$src))))))),
5796 (VPMOVSXBDYrm addr:$src)>;
5798 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5799 (scalar_to_vector (loadi64 addr:$src))))))),
5800 (VPMOVSXWQYrm addr:$src)>;
5801 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5802 (scalar_to_vector (loadf64 addr:$src))))))),
5803 (VPMOVSXWQYrm addr:$src)>;
5805 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5806 (scalar_to_vector (loadi32 addr:$src))))))),
5807 (VPMOVSXBQYrm addr:$src)>;
5810 let Predicates = [HasAVX] in {
5811 // Common patterns involving scalar load
5812 def : Pat<(int_x86_sse41_pmovsxbq
5813 (bitconvert (v4i32 (X86vzmovl
5814 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5815 (VPMOVSXBQrm addr:$src)>;
5817 def : Pat<(int_x86_sse41_pmovzxbq
5818 (bitconvert (v4i32 (X86vzmovl
5819 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5820 (VPMOVZXBQrm addr:$src)>;
5823 let Predicates = [UseSSE41] in {
5824 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5825 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
5826 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
5828 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5829 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
5831 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5833 // Common patterns involving scalar load
5834 def : Pat<(int_x86_sse41_pmovsxbq
5835 (bitconvert (v4i32 (X86vzmovl
5836 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5837 (PMOVSXBQrm addr:$src)>;
5839 def : Pat<(int_x86_sse41_pmovzxbq
5840 (bitconvert (v4i32 (X86vzmovl
5841 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5842 (PMOVZXBQrm addr:$src)>;
5844 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5845 (scalar_to_vector (loadi64 addr:$src))))))),
5846 (PMOVSXWDrm addr:$src)>;
5847 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5848 (scalar_to_vector (loadf64 addr:$src))))))),
5849 (PMOVSXWDrm addr:$src)>;
5850 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5851 (scalar_to_vector (loadi32 addr:$src))))))),
5852 (PMOVSXBDrm addr:$src)>;
5853 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5854 (scalar_to_vector (loadi32 addr:$src))))))),
5855 (PMOVSXWQrm addr:$src)>;
5856 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5857 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5858 (PMOVSXBQrm addr:$src)>;
5859 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5860 (scalar_to_vector (loadi64 addr:$src))))))),
5861 (PMOVSXDQrm addr:$src)>;
5862 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5863 (scalar_to_vector (loadf64 addr:$src))))))),
5864 (PMOVSXDQrm addr:$src)>;
5865 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5866 (scalar_to_vector (loadi64 addr:$src))))))),
5867 (PMOVSXBWrm addr:$src)>;
5868 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5869 (scalar_to_vector (loadf64 addr:$src))))))),
5870 (PMOVSXBWrm addr:$src)>;
5873 let Predicates = [HasAVX2] in {
5874 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5875 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5876 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5878 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5879 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5881 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5883 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5884 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5885 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5886 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5887 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5888 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5890 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5891 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5892 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5893 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5895 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5896 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5899 let Predicates = [HasAVX] in {
5900 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5901 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5902 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5904 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5905 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5907 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5909 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5910 (VPMOVZXBWrm addr:$src)>;
5911 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5912 (VPMOVZXBWrm addr:$src)>;
5913 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5914 (VPMOVZXBDrm addr:$src)>;
5915 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5916 (VPMOVZXBQrm addr:$src)>;
5918 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5919 (VPMOVZXWDrm addr:$src)>;
5920 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5921 (VPMOVZXWDrm addr:$src)>;
5922 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5923 (VPMOVZXWQrm addr:$src)>;
5925 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5926 (VPMOVZXDQrm addr:$src)>;
5927 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5928 (VPMOVZXDQrm addr:$src)>;
5929 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5930 (VPMOVZXDQrm addr:$src)>;
5932 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5933 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
5934 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
5936 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5937 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
5939 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5941 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5942 (scalar_to_vector (loadi64 addr:$src))))))),
5943 (VPMOVSXWDrm addr:$src)>;
5944 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5945 (scalar_to_vector (loadi64 addr:$src))))))),
5946 (VPMOVSXDQrm addr:$src)>;
5947 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5948 (scalar_to_vector (loadf64 addr:$src))))))),
5949 (VPMOVSXWDrm addr:$src)>;
5950 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5951 (scalar_to_vector (loadf64 addr:$src))))))),
5952 (VPMOVSXDQrm addr:$src)>;
5953 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5954 (scalar_to_vector (loadi64 addr:$src))))))),
5955 (VPMOVSXBWrm addr:$src)>;
5956 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5957 (scalar_to_vector (loadf64 addr:$src))))))),
5958 (VPMOVSXBWrm addr:$src)>;
5960 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5961 (scalar_to_vector (loadi32 addr:$src))))))),
5962 (VPMOVSXBDrm addr:$src)>;
5963 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5964 (scalar_to_vector (loadi32 addr:$src))))))),
5965 (VPMOVSXWQrm addr:$src)>;
5966 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5967 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5968 (VPMOVSXBQrm addr:$src)>;
5971 let Predicates = [UseSSE41] in {
5972 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
5973 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
5974 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
5976 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
5977 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
5979 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
5981 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5982 (PMOVZXBWrm addr:$src)>;
5983 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5984 (PMOVZXBWrm addr:$src)>;
5985 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5986 (PMOVZXBDrm addr:$src)>;
5987 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5988 (PMOVZXBQrm addr:$src)>;
5990 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5991 (PMOVZXWDrm addr:$src)>;
5992 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5993 (PMOVZXWDrm addr:$src)>;
5994 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5995 (PMOVZXWQrm addr:$src)>;
5997 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5998 (PMOVZXDQrm addr:$src)>;
5999 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6000 (PMOVZXDQrm addr:$src)>;
6001 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6002 (PMOVZXDQrm addr:$src)>;
6005 //===----------------------------------------------------------------------===//
6006 // SSE4.1 - Extract Instructions
6007 //===----------------------------------------------------------------------===//
6009 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6010 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6011 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6012 (ins VR128:$src1, i32i8imm:$src2),
6013 !strconcat(OpcodeStr,
6014 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6015 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
6017 let neverHasSideEffects = 1, mayStore = 1 in
6018 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6019 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6020 !strconcat(OpcodeStr,
6021 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6024 // There's an AssertZext in the way of writing the store pattern
6025 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6028 let Predicates = [HasAVX] in {
6029 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6030 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
6031 (ins VR128:$src1, i32i8imm:$src2),
6032 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
6035 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6038 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6039 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6040 let neverHasSideEffects = 1, mayStore = 1 in
6041 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6042 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6043 !strconcat(OpcodeStr,
6044 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6047 // There's an AssertZext in the way of writing the store pattern
6048 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6051 let Predicates = [HasAVX] in
6052 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6054 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6057 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6058 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6059 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6060 (ins VR128:$src1, i32i8imm:$src2),
6061 !strconcat(OpcodeStr,
6062 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6064 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6065 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6066 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6067 !strconcat(OpcodeStr,
6068 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6069 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6070 addr:$dst)]>, OpSize;
6073 let Predicates = [HasAVX] in
6074 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6076 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6078 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6079 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6080 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6081 (ins VR128:$src1, i32i8imm:$src2),
6082 !strconcat(OpcodeStr,
6083 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6085 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6086 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6087 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6088 !strconcat(OpcodeStr,
6089 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6090 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6091 addr:$dst)]>, OpSize, REX_W;
6094 let Predicates = [HasAVX] in
6095 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6097 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6099 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6101 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6102 OpndItins itins = DEFAULT_ITINS> {
6103 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6104 (ins VR128:$src1, i32i8imm:$src2),
6105 !strconcat(OpcodeStr,
6106 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6108 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6111 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6112 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6113 !strconcat(OpcodeStr,
6114 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6115 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6116 addr:$dst)], itins.rm>, OpSize;
6119 let ExeDomain = SSEPackedSingle in {
6120 let Predicates = [UseAVX] in {
6121 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6122 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6123 (ins VR128:$src1, i32i8imm:$src2),
6124 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6127 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6130 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6131 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6134 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6136 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6139 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6140 Requires<[UseSSE41]>;
6142 //===----------------------------------------------------------------------===//
6143 // SSE4.1 - Insert Instructions
6144 //===----------------------------------------------------------------------===//
6146 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6147 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6148 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6150 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6152 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6154 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6155 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6156 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6158 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6160 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6162 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6163 imm:$src3))]>, OpSize;
6166 let Predicates = [HasAVX] in
6167 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6168 let Constraints = "$src1 = $dst" in
6169 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6171 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6172 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6173 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6175 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6177 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6179 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6181 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6182 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6184 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6186 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6188 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6189 imm:$src3)))]>, OpSize;
6192 let Predicates = [HasAVX] in
6193 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6194 let Constraints = "$src1 = $dst" in
6195 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6197 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6198 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6199 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6201 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6203 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6205 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6207 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6208 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6210 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6212 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6214 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6215 imm:$src3)))]>, OpSize;
6218 let Predicates = [HasAVX] in
6219 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6220 let Constraints = "$src1 = $dst" in
6221 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6223 // insertps has a few different modes, there's the first two here below which
6224 // are optimized inserts that won't zero arbitrary elements in the destination
6225 // vector. The next one matches the intrinsic and could zero arbitrary elements
6226 // in the target vector.
6227 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6228 OpndItins itins = DEFAULT_ITINS> {
6229 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6230 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6232 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6234 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6236 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6238 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6239 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6241 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6243 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6245 (X86insrtps VR128:$src1,
6246 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6247 imm:$src3))], itins.rm>, OpSize;
6250 let ExeDomain = SSEPackedSingle in {
6251 let Predicates = [UseAVX] in
6252 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6253 let Constraints = "$src1 = $dst" in
6254 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6257 //===----------------------------------------------------------------------===//
6258 // SSE4.1 - Round Instructions
6259 //===----------------------------------------------------------------------===//
6261 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6262 X86MemOperand x86memop, RegisterClass RC,
6263 PatFrag mem_frag32, PatFrag mem_frag64,
6264 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6265 let ExeDomain = SSEPackedSingle in {
6266 // Intrinsic operation, reg.
6267 // Vector intrinsic operation, reg
6268 def PSr : SS4AIi8<opcps, MRMSrcReg,
6269 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6270 !strconcat(OpcodeStr,
6271 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6272 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6273 IIC_SSE_ROUNDPS_REG>,
6276 // Vector intrinsic operation, mem
6277 def PSm : SS4AIi8<opcps, MRMSrcMem,
6278 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6279 !strconcat(OpcodeStr,
6280 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6282 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6283 IIC_SSE_ROUNDPS_MEM>,
6285 } // ExeDomain = SSEPackedSingle
6287 let ExeDomain = SSEPackedDouble in {
6288 // Vector intrinsic operation, reg
6289 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6290 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6291 !strconcat(OpcodeStr,
6292 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6293 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6294 IIC_SSE_ROUNDPS_REG>,
6297 // Vector intrinsic operation, mem
6298 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6299 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6300 !strconcat(OpcodeStr,
6301 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6303 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6304 IIC_SSE_ROUNDPS_REG>,
6306 } // ExeDomain = SSEPackedDouble
6309 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6312 Intrinsic F64Int, bit Is2Addr = 1> {
6313 let ExeDomain = GenericDomain in {
6315 let hasSideEffects = 0 in
6316 def SSr : SS4AIi8<opcss, MRMSrcReg,
6317 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6319 !strconcat(OpcodeStr,
6320 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6321 !strconcat(OpcodeStr,
6322 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6325 // Intrinsic operation, reg.
6326 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6327 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6329 !strconcat(OpcodeStr,
6330 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6331 !strconcat(OpcodeStr,
6332 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6333 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6336 // Intrinsic operation, mem.
6337 def SSm : SS4AIi8<opcss, MRMSrcMem,
6338 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6340 !strconcat(OpcodeStr,
6341 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6342 !strconcat(OpcodeStr,
6343 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6345 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6349 let hasSideEffects = 0 in
6350 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6351 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6353 !strconcat(OpcodeStr,
6354 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6355 !strconcat(OpcodeStr,
6356 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6359 // Intrinsic operation, reg.
6360 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6361 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6363 !strconcat(OpcodeStr,
6364 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6365 !strconcat(OpcodeStr,
6366 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6367 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6370 // Intrinsic operation, mem.
6371 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6372 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6374 !strconcat(OpcodeStr,
6375 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6376 !strconcat(OpcodeStr,
6377 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6379 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6381 } // ExeDomain = GenericDomain
6384 // FP round - roundss, roundps, roundsd, roundpd
6385 let Predicates = [HasAVX] in {
6387 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6388 memopv4f32, memopv2f64,
6389 int_x86_sse41_round_ps,
6390 int_x86_sse41_round_pd>, VEX;
6391 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6392 memopv8f32, memopv4f64,
6393 int_x86_avx_round_ps_256,
6394 int_x86_avx_round_pd_256>, VEX, VEX_L;
6395 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6396 int_x86_sse41_round_ss,
6397 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6399 def : Pat<(ffloor FR32:$src),
6400 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6401 def : Pat<(f64 (ffloor FR64:$src)),
6402 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6403 def : Pat<(f32 (fnearbyint FR32:$src)),
6404 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6405 def : Pat<(f64 (fnearbyint FR64:$src)),
6406 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6407 def : Pat<(f32 (fceil FR32:$src)),
6408 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6409 def : Pat<(f64 (fceil FR64:$src)),
6410 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6411 def : Pat<(f32 (frint FR32:$src)),
6412 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6413 def : Pat<(f64 (frint FR64:$src)),
6414 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6415 def : Pat<(f32 (ftrunc FR32:$src)),
6416 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6417 def : Pat<(f64 (ftrunc FR64:$src)),
6418 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6420 def : Pat<(v4f32 (ffloor VR128:$src)),
6421 (VROUNDPSr VR128:$src, (i32 0x1))>;
6422 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6423 (VROUNDPSr VR128:$src, (i32 0xC))>;
6424 def : Pat<(v4f32 (fceil VR128:$src)),
6425 (VROUNDPSr VR128:$src, (i32 0x2))>;
6426 def : Pat<(v4f32 (frint VR128:$src)),
6427 (VROUNDPSr VR128:$src, (i32 0x4))>;
6428 def : Pat<(v4f32 (ftrunc VR128:$src)),
6429 (VROUNDPSr VR128:$src, (i32 0x3))>;
6431 def : Pat<(v2f64 (ffloor VR128:$src)),
6432 (VROUNDPDr VR128:$src, (i32 0x1))>;
6433 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6434 (VROUNDPDr VR128:$src, (i32 0xC))>;
6435 def : Pat<(v2f64 (fceil VR128:$src)),
6436 (VROUNDPDr VR128:$src, (i32 0x2))>;
6437 def : Pat<(v2f64 (frint VR128:$src)),
6438 (VROUNDPDr VR128:$src, (i32 0x4))>;
6439 def : Pat<(v2f64 (ftrunc VR128:$src)),
6440 (VROUNDPDr VR128:$src, (i32 0x3))>;
6442 def : Pat<(v8f32 (ffloor VR256:$src)),
6443 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6444 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6445 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6446 def : Pat<(v8f32 (fceil VR256:$src)),
6447 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6448 def : Pat<(v8f32 (frint VR256:$src)),
6449 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6450 def : Pat<(v8f32 (ftrunc VR256:$src)),
6451 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6453 def : Pat<(v4f64 (ffloor VR256:$src)),
6454 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6455 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6456 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6457 def : Pat<(v4f64 (fceil VR256:$src)),
6458 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6459 def : Pat<(v4f64 (frint VR256:$src)),
6460 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6461 def : Pat<(v4f64 (ftrunc VR256:$src)),
6462 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6465 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6466 memopv4f32, memopv2f64,
6467 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6468 let Constraints = "$src1 = $dst" in
6469 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6470 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6472 let Predicates = [UseSSE41] in {
6473 def : Pat<(ffloor FR32:$src),
6474 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6475 def : Pat<(f64 (ffloor FR64:$src)),
6476 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6477 def : Pat<(f32 (fnearbyint FR32:$src)),
6478 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6479 def : Pat<(f64 (fnearbyint FR64:$src)),
6480 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6481 def : Pat<(f32 (fceil FR32:$src)),
6482 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6483 def : Pat<(f64 (fceil FR64:$src)),
6484 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6485 def : Pat<(f32 (frint FR32:$src)),
6486 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6487 def : Pat<(f64 (frint FR64:$src)),
6488 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6489 def : Pat<(f32 (ftrunc FR32:$src)),
6490 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6491 def : Pat<(f64 (ftrunc FR64:$src)),
6492 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6494 def : Pat<(v4f32 (ffloor VR128:$src)),
6495 (ROUNDPSr VR128:$src, (i32 0x1))>;
6496 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6497 (ROUNDPSr VR128:$src, (i32 0xC))>;
6498 def : Pat<(v4f32 (fceil VR128:$src)),
6499 (ROUNDPSr VR128:$src, (i32 0x2))>;
6500 def : Pat<(v4f32 (frint VR128:$src)),
6501 (ROUNDPSr VR128:$src, (i32 0x4))>;
6502 def : Pat<(v4f32 (ftrunc VR128:$src)),
6503 (ROUNDPSr VR128:$src, (i32 0x3))>;
6505 def : Pat<(v2f64 (ffloor VR128:$src)),
6506 (ROUNDPDr VR128:$src, (i32 0x1))>;
6507 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6508 (ROUNDPDr VR128:$src, (i32 0xC))>;
6509 def : Pat<(v2f64 (fceil VR128:$src)),
6510 (ROUNDPDr VR128:$src, (i32 0x2))>;
6511 def : Pat<(v2f64 (frint VR128:$src)),
6512 (ROUNDPDr VR128:$src, (i32 0x4))>;
6513 def : Pat<(v2f64 (ftrunc VR128:$src)),
6514 (ROUNDPDr VR128:$src, (i32 0x3))>;
6517 //===----------------------------------------------------------------------===//
6518 // SSE4.1 - Packed Bit Test
6519 //===----------------------------------------------------------------------===//
6521 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6522 // the intel intrinsic that corresponds to this.
6523 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6524 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6525 "vptest\t{$src2, $src1|$src1, $src2}",
6526 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6528 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6529 "vptest\t{$src2, $src1|$src1, $src2}",
6530 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6533 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6534 "vptest\t{$src2, $src1|$src1, $src2}",
6535 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6537 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6538 "vptest\t{$src2, $src1|$src1, $src2}",
6539 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6543 let Defs = [EFLAGS] in {
6544 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6545 "ptest\t{$src2, $src1|$src1, $src2}",
6546 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6548 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6549 "ptest\t{$src2, $src1|$src1, $src2}",
6550 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6554 // The bit test instructions below are AVX only
6555 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6556 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6557 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6558 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6559 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6560 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6561 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6562 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6566 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6567 let ExeDomain = SSEPackedSingle in {
6568 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6569 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6572 let ExeDomain = SSEPackedDouble in {
6573 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6574 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6579 //===----------------------------------------------------------------------===//
6580 // SSE4.1 - Misc Instructions
6581 //===----------------------------------------------------------------------===//
6583 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6584 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6585 "popcnt{w}\t{$src, $dst|$dst, $src}",
6586 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6589 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6590 "popcnt{w}\t{$src, $dst|$dst, $src}",
6591 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6592 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize, XS;
6594 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6595 "popcnt{l}\t{$src, $dst|$dst, $src}",
6596 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6599 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6600 "popcnt{l}\t{$src, $dst|$dst, $src}",
6601 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6602 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6604 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6605 "popcnt{q}\t{$src, $dst|$dst, $src}",
6606 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6609 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6610 "popcnt{q}\t{$src, $dst|$dst, $src}",
6611 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6612 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6617 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6618 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6619 Intrinsic IntId128> {
6620 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6622 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6623 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6624 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6626 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6629 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6632 let Predicates = [HasAVX] in
6633 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6634 int_x86_sse41_phminposuw>, VEX;
6635 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6636 int_x86_sse41_phminposuw>;
6638 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6639 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6640 Intrinsic IntId128, bit Is2Addr = 1,
6641 OpndItins itins = DEFAULT_ITINS> {
6642 let isCommutable = 1 in
6643 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6644 (ins VR128:$src1, VR128:$src2),
6646 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6647 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6648 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
6650 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6651 (ins VR128:$src1, i128mem:$src2),
6653 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6654 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6656 (IntId128 VR128:$src1,
6657 (bitconvert (memopv2i64 addr:$src2))))],
6661 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6662 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6663 Intrinsic IntId256> {
6664 let isCommutable = 1 in
6665 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6666 (ins VR256:$src1, VR256:$src2),
6667 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6668 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6669 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6670 (ins VR256:$src1, i256mem:$src2),
6671 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6673 (IntId256 VR256:$src1,
6674 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6678 /// SS48I_binop_rm - Simple SSE41 binary operator.
6679 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6680 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6681 X86MemOperand x86memop, bit Is2Addr = 1,
6682 OpndItins itins = DEFAULT_ITINS> {
6683 let isCommutable = 1 in
6684 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6685 (ins RC:$src1, RC:$src2),
6687 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6688 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6689 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6690 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6691 (ins RC:$src1, x86memop:$src2),
6693 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6694 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6696 (OpVT (OpNode RC:$src1,
6697 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6700 let Predicates = [HasAVX] in {
6701 let isCommutable = 0 in
6702 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6704 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6705 memopv2i64, i128mem, 0>, VEX_4V;
6706 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6707 memopv2i64, i128mem, 0>, VEX_4V;
6708 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6709 memopv2i64, i128mem, 0>, VEX_4V;
6710 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6711 memopv2i64, i128mem, 0>, VEX_4V;
6712 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6713 memopv2i64, i128mem, 0>, VEX_4V;
6714 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6715 memopv2i64, i128mem, 0>, VEX_4V;
6716 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6717 memopv2i64, i128mem, 0>, VEX_4V;
6718 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6719 memopv2i64, i128mem, 0>, VEX_4V;
6720 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6724 let Predicates = [HasAVX2] in {
6725 let isCommutable = 0 in
6726 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6727 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6728 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6729 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6730 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6731 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6732 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6733 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6734 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6735 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6736 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6737 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6738 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6739 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6740 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6741 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6742 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6743 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6744 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6745 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6748 let Constraints = "$src1 = $dst" in {
6749 let isCommutable = 0 in
6750 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6751 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6752 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6753 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6754 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6755 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6756 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6757 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6758 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6759 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6760 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6761 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6762 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6763 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6764 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6765 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6766 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6767 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq,
6768 1, SSE_INTMUL_ITINS_P>;
6771 let Predicates = [HasAVX] in {
6772 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6773 memopv2i64, i128mem, 0>, VEX_4V;
6774 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6775 memopv2i64, i128mem, 0>, VEX_4V;
6777 let Predicates = [HasAVX2] in {
6778 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6779 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6780 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6781 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6784 let Constraints = "$src1 = $dst" in {
6785 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6786 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6787 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6788 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6791 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6792 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6793 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6794 X86MemOperand x86memop, bit Is2Addr = 1,
6795 OpndItins itins = DEFAULT_ITINS> {
6796 let isCommutable = 1 in
6797 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6798 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6800 !strconcat(OpcodeStr,
6801 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6802 !strconcat(OpcodeStr,
6803 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6804 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6806 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6807 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6809 !strconcat(OpcodeStr,
6810 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6811 !strconcat(OpcodeStr,
6812 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6815 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6819 let Predicates = [HasAVX] in {
6820 let isCommutable = 0 in {
6821 let ExeDomain = SSEPackedSingle in {
6822 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6823 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6824 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6825 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6826 f256mem, 0>, VEX_4V, VEX_L;
6828 let ExeDomain = SSEPackedDouble in {
6829 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6830 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6831 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6832 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6833 f256mem, 0>, VEX_4V, VEX_L;
6835 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6836 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6837 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6838 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6840 let ExeDomain = SSEPackedSingle in
6841 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6842 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6843 let ExeDomain = SSEPackedDouble in
6844 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6845 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6846 let ExeDomain = SSEPackedSingle in
6847 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6848 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6851 let Predicates = [HasAVX2] in {
6852 let isCommutable = 0 in {
6853 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6854 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6855 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6856 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6860 let Constraints = "$src1 = $dst" in {
6861 let isCommutable = 0 in {
6862 let ExeDomain = SSEPackedSingle in
6863 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6864 VR128, memopv4f32, f128mem,
6865 1, SSE_INTALU_ITINS_P>;
6866 let ExeDomain = SSEPackedDouble in
6867 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6868 VR128, memopv2f64, f128mem,
6869 1, SSE_INTALU_ITINS_P>;
6870 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6871 VR128, memopv2i64, i128mem,
6872 1, SSE_INTALU_ITINS_P>;
6873 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6874 VR128, memopv2i64, i128mem,
6875 1, SSE_INTMUL_ITINS_P>;
6877 let ExeDomain = SSEPackedSingle in
6878 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6879 VR128, memopv4f32, f128mem, 1,
6881 let ExeDomain = SSEPackedDouble in
6882 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6883 VR128, memopv2f64, f128mem, 1,
6887 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6888 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6889 RegisterClass RC, X86MemOperand x86memop,
6890 PatFrag mem_frag, Intrinsic IntId> {
6891 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6892 (ins RC:$src1, RC:$src2, RC:$src3),
6893 !strconcat(OpcodeStr,
6894 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6895 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6896 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6898 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6899 (ins RC:$src1, x86memop:$src2, RC:$src3),
6900 !strconcat(OpcodeStr,
6901 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6903 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6905 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6908 let Predicates = [HasAVX] in {
6909 let ExeDomain = SSEPackedDouble in {
6910 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6911 memopv2f64, int_x86_sse41_blendvpd>;
6912 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6913 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6914 } // ExeDomain = SSEPackedDouble
6915 let ExeDomain = SSEPackedSingle in {
6916 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6917 memopv4f32, int_x86_sse41_blendvps>;
6918 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6919 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6920 } // ExeDomain = SSEPackedSingle
6921 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6922 memopv2i64, int_x86_sse41_pblendvb>;
6925 let Predicates = [HasAVX2] in {
6926 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6927 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6930 let Predicates = [HasAVX] in {
6931 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6932 (v16i8 VR128:$src2))),
6933 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6934 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6935 (v4i32 VR128:$src2))),
6936 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6937 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6938 (v4f32 VR128:$src2))),
6939 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6940 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6941 (v2i64 VR128:$src2))),
6942 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6943 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6944 (v2f64 VR128:$src2))),
6945 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6946 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6947 (v8i32 VR256:$src2))),
6948 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6949 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6950 (v8f32 VR256:$src2))),
6951 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6952 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6953 (v4i64 VR256:$src2))),
6954 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6955 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6956 (v4f64 VR256:$src2))),
6957 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6959 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6961 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6962 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6964 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6966 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6968 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6969 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6971 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6972 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6974 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6977 let Predicates = [HasAVX2] in {
6978 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6979 (v32i8 VR256:$src2))),
6980 (VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
6981 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6983 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6986 /// SS41I_ternary_int - SSE 4.1 ternary operator
6987 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6988 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6989 X86MemOperand x86memop, Intrinsic IntId,
6990 OpndItins itins = DEFAULT_ITINS> {
6991 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6992 (ins VR128:$src1, VR128:$src2),
6993 !strconcat(OpcodeStr,
6994 "\t{$src2, $dst|$dst, $src2}"),
6995 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
6998 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6999 (ins VR128:$src1, x86memop:$src2),
7000 !strconcat(OpcodeStr,
7001 "\t{$src2, $dst|$dst, $src2}"),
7004 (bitconvert (mem_frag addr:$src2)), XMM0))],
7009 let ExeDomain = SSEPackedDouble in
7010 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7011 int_x86_sse41_blendvpd>;
7012 let ExeDomain = SSEPackedSingle in
7013 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7014 int_x86_sse41_blendvps>;
7015 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7016 int_x86_sse41_pblendvb>;
7018 // Aliases with the implicit xmm0 argument
7019 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7020 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7021 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7022 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7023 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7024 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7025 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7026 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7027 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7028 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7029 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7030 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7032 let Predicates = [UseSSE41] in {
7033 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7034 (v16i8 VR128:$src2))),
7035 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7036 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7037 (v4i32 VR128:$src2))),
7038 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7039 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7040 (v4f32 VR128:$src2))),
7041 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7042 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7043 (v2i64 VR128:$src2))),
7044 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7045 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7046 (v2f64 VR128:$src2))),
7047 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7049 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7051 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7052 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7054 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7055 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7057 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7061 let Predicates = [HasAVX] in
7062 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7063 "vmovntdqa\t{$src, $dst|$dst, $src}",
7064 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7066 let Predicates = [HasAVX2] in
7067 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7068 "vmovntdqa\t{$src, $dst|$dst, $src}",
7069 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7071 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7072 "movntdqa\t{$src, $dst|$dst, $src}",
7073 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7076 //===----------------------------------------------------------------------===//
7077 // SSE4.2 - Compare Instructions
7078 //===----------------------------------------------------------------------===//
7080 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7081 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7082 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7083 X86MemOperand x86memop, bit Is2Addr = 1> {
7084 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7085 (ins RC:$src1, RC:$src2),
7087 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7088 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7089 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7091 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7092 (ins RC:$src1, x86memop:$src2),
7094 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7095 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7097 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7100 let Predicates = [HasAVX] in
7101 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7102 memopv2i64, i128mem, 0>, VEX_4V;
7104 let Predicates = [HasAVX2] in
7105 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7106 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
7108 let Constraints = "$src1 = $dst" in
7109 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7110 memopv2i64, i128mem>;
7112 //===----------------------------------------------------------------------===//
7113 // SSE4.2 - String/text Processing Instructions
7114 //===----------------------------------------------------------------------===//
7116 // Packed Compare Implicit Length Strings, Return Mask
7117 multiclass pseudo_pcmpistrm<string asm> {
7118 def REG : PseudoI<(outs VR128:$dst),
7119 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7120 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7122 def MEM : PseudoI<(outs VR128:$dst),
7123 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7124 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7125 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7128 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7129 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7130 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7133 multiclass pcmpistrm_SS42AI<string asm> {
7134 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7135 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7136 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7139 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7140 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7141 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7145 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7146 let Predicates = [HasAVX] in
7147 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7148 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7151 // Packed Compare Explicit Length Strings, Return Mask
7152 multiclass pseudo_pcmpestrm<string asm> {
7153 def REG : PseudoI<(outs VR128:$dst),
7154 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7155 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7156 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7157 def MEM : PseudoI<(outs VR128:$dst),
7158 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7159 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7160 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7163 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7164 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7165 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7168 multiclass SS42AI_pcmpestrm<string asm> {
7169 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7170 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7171 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7174 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7175 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7176 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7180 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7181 let Predicates = [HasAVX] in
7182 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7183 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7186 // Packed Compare Implicit Length Strings, Return Index
7187 multiclass pseudo_pcmpistri<string asm> {
7188 def REG : PseudoI<(outs GR32:$dst),
7189 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7190 [(set GR32:$dst, EFLAGS,
7191 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7192 def MEM : PseudoI<(outs GR32:$dst),
7193 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7194 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7195 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7198 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7199 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7200 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7203 multiclass SS42AI_pcmpistri<string asm> {
7204 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7205 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7206 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7209 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7210 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7211 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7215 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7216 let Predicates = [HasAVX] in
7217 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7218 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7221 // Packed Compare Explicit Length Strings, Return Index
7222 multiclass pseudo_pcmpestri<string asm> {
7223 def REG : PseudoI<(outs GR32:$dst),
7224 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7225 [(set GR32:$dst, EFLAGS,
7226 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7227 def MEM : PseudoI<(outs GR32:$dst),
7228 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7229 [(set GR32:$dst, EFLAGS,
7230 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7234 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7235 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7236 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7239 multiclass SS42AI_pcmpestri<string asm> {
7240 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7241 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7242 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7245 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7246 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7247 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7251 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7252 let Predicates = [HasAVX] in
7253 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7254 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7257 //===----------------------------------------------------------------------===//
7258 // SSE4.2 - CRC Instructions
7259 //===----------------------------------------------------------------------===//
7261 // No CRC instructions have AVX equivalents
7263 // crc intrinsic instruction
7264 // This set of instructions are only rm, the only difference is the size
7266 let Constraints = "$src1 = $dst" in {
7267 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7268 (ins GR32:$src1, i8mem:$src2),
7269 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7271 (int_x86_sse42_crc32_32_8 GR32:$src1,
7272 (load addr:$src2)))], IIC_CRC32_MEM>;
7273 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7274 (ins GR32:$src1, GR8:$src2),
7275 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7277 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))],
7279 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7280 (ins GR32:$src1, i16mem:$src2),
7281 "crc32{w}\t{$src2, $src1|$src1, $src2}",
7283 (int_x86_sse42_crc32_32_16 GR32:$src1,
7284 (load addr:$src2)))], IIC_CRC32_MEM>,
7286 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7287 (ins GR32:$src1, GR16:$src2),
7288 "crc32{w}\t{$src2, $src1|$src1, $src2}",
7290 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))],
7293 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7294 (ins GR32:$src1, i32mem:$src2),
7295 "crc32{l}\t{$src2, $src1|$src1, $src2}",
7297 (int_x86_sse42_crc32_32_32 GR32:$src1,
7298 (load addr:$src2)))], IIC_CRC32_MEM>;
7299 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7300 (ins GR32:$src1, GR32:$src2),
7301 "crc32{l}\t{$src2, $src1|$src1, $src2}",
7303 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))],
7305 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7306 (ins GR64:$src1, i8mem:$src2),
7307 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7309 (int_x86_sse42_crc32_64_8 GR64:$src1,
7310 (load addr:$src2)))], IIC_CRC32_MEM>,
7312 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7313 (ins GR64:$src1, GR8:$src2),
7314 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7316 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))],
7319 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7320 (ins GR64:$src1, i64mem:$src2),
7321 "crc32{q}\t{$src2, $src1|$src1, $src2}",
7323 (int_x86_sse42_crc32_64_64 GR64:$src1,
7324 (load addr:$src2)))], IIC_CRC32_MEM>,
7326 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7327 (ins GR64:$src1, GR64:$src2),
7328 "crc32{q}\t{$src2, $src1|$src1, $src2}",
7330 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))],
7335 //===----------------------------------------------------------------------===//
7336 // SHA-NI Instructions
7337 //===----------------------------------------------------------------------===//
7339 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7341 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7342 (ins VR128:$src1, VR128:$src2),
7343 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7345 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7346 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7348 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7349 (ins VR128:$src1, i128mem:$src2),
7350 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7352 (set VR128:$dst, (IntId VR128:$src1,
7353 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7354 (set VR128:$dst, (IntId VR128:$src1,
7355 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7358 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7359 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7360 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7361 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7363 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7364 (i8 imm:$src3)))]>, TA;
7365 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7366 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7367 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7369 (int_x86_sha1rnds4 VR128:$src1,
7370 (bc_v4i32 (memopv2i64 addr:$src2)),
7371 (i8 imm:$src3)))]>, TA;
7373 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7374 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7375 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7378 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7380 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7381 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7384 // Aliases with explicit %xmm0
7385 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7386 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7387 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7388 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7390 //===----------------------------------------------------------------------===//
7391 // AES-NI Instructions
7392 //===----------------------------------------------------------------------===//
7394 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7395 Intrinsic IntId128, bit Is2Addr = 1> {
7396 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7397 (ins VR128:$src1, VR128:$src2),
7399 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7400 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7401 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7403 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7404 (ins VR128:$src1, i128mem:$src2),
7406 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7407 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7409 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7412 // Perform One Round of an AES Encryption/Decryption Flow
7413 let Predicates = [HasAVX, HasAES] in {
7414 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7415 int_x86_aesni_aesenc, 0>, VEX_4V;
7416 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7417 int_x86_aesni_aesenclast, 0>, VEX_4V;
7418 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7419 int_x86_aesni_aesdec, 0>, VEX_4V;
7420 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7421 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7424 let Constraints = "$src1 = $dst" in {
7425 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7426 int_x86_aesni_aesenc>;
7427 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7428 int_x86_aesni_aesenclast>;
7429 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7430 int_x86_aesni_aesdec>;
7431 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7432 int_x86_aesni_aesdeclast>;
7435 // Perform the AES InvMixColumn Transformation
7436 let Predicates = [HasAVX, HasAES] in {
7437 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7439 "vaesimc\t{$src1, $dst|$dst, $src1}",
7441 (int_x86_aesni_aesimc VR128:$src1))]>,
7443 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7444 (ins i128mem:$src1),
7445 "vaesimc\t{$src1, $dst|$dst, $src1}",
7446 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7449 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7451 "aesimc\t{$src1, $dst|$dst, $src1}",
7453 (int_x86_aesni_aesimc VR128:$src1))]>,
7455 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7456 (ins i128mem:$src1),
7457 "aesimc\t{$src1, $dst|$dst, $src1}",
7458 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7461 // AES Round Key Generation Assist
7462 let Predicates = [HasAVX, HasAES] in {
7463 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7464 (ins VR128:$src1, i8imm:$src2),
7465 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7467 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7469 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7470 (ins i128mem:$src1, i8imm:$src2),
7471 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7473 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7476 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7477 (ins VR128:$src1, i8imm:$src2),
7478 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7480 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7482 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7483 (ins i128mem:$src1, i8imm:$src2),
7484 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7486 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7489 //===----------------------------------------------------------------------===//
7490 // PCLMUL Instructions
7491 //===----------------------------------------------------------------------===//
7493 // AVX carry-less Multiplication instructions
7494 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7495 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7496 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7498 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7500 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7501 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7502 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7503 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7504 (memopv2i64 addr:$src2), imm:$src3))]>;
7506 // Carry-less Multiplication instructions
7507 let Constraints = "$src1 = $dst" in {
7508 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7509 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7510 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7512 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7513 IIC_SSE_PCLMULQDQ_RR>;
7515 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7516 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7517 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7518 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7519 (memopv2i64 addr:$src2), imm:$src3))],
7520 IIC_SSE_PCLMULQDQ_RM>;
7521 } // Constraints = "$src1 = $dst"
7524 multiclass pclmul_alias<string asm, int immop> {
7525 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7526 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7528 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7529 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7531 def : InstAlias<!strconcat("vpclmul", asm,
7532 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7533 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7535 def : InstAlias<!strconcat("vpclmul", asm,
7536 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7537 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7539 defm : pclmul_alias<"hqhq", 0x11>;
7540 defm : pclmul_alias<"hqlq", 0x01>;
7541 defm : pclmul_alias<"lqhq", 0x10>;
7542 defm : pclmul_alias<"lqlq", 0x00>;
7544 //===----------------------------------------------------------------------===//
7545 // SSE4A Instructions
7546 //===----------------------------------------------------------------------===//
7548 let Predicates = [HasSSE4A] in {
7550 let Constraints = "$src = $dst" in {
7551 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7552 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7553 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7554 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7555 imm:$idx))]>, TB, OpSize;
7556 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7557 (ins VR128:$src, VR128:$mask),
7558 "extrq\t{$mask, $src|$src, $mask}",
7559 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7560 VR128:$mask))]>, TB, OpSize;
7562 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7563 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7564 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7565 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7566 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7567 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7568 (ins VR128:$src, VR128:$mask),
7569 "insertq\t{$mask, $src|$src, $mask}",
7570 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7571 VR128:$mask))]>, XD;
7574 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7575 "movntss\t{$src, $dst|$dst, $src}",
7576 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7578 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7579 "movntsd\t{$src, $dst|$dst, $src}",
7580 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7583 //===----------------------------------------------------------------------===//
7585 //===----------------------------------------------------------------------===//
7587 //===----------------------------------------------------------------------===//
7588 // VBROADCAST - Load from memory and broadcast to all elements of the
7589 // destination operand
7591 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7592 X86MemOperand x86memop, Intrinsic Int> :
7593 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7595 [(set RC:$dst, (Int addr:$src))]>, VEX;
7597 // AVX2 adds register forms
7598 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7600 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7601 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7602 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7604 let ExeDomain = SSEPackedSingle in {
7605 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7606 int_x86_avx_vbroadcast_ss>;
7607 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7608 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7610 let ExeDomain = SSEPackedDouble in
7611 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7612 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7613 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7614 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7616 let ExeDomain = SSEPackedSingle in {
7617 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7618 int_x86_avx2_vbroadcast_ss_ps>;
7619 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7620 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7622 let ExeDomain = SSEPackedDouble in
7623 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7624 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7626 let Predicates = [HasAVX2] in
7627 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7628 int_x86_avx2_vbroadcasti128>, VEX_L;
7630 let Predicates = [HasAVX] in
7631 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7632 (VBROADCASTF128 addr:$src)>;
7635 //===----------------------------------------------------------------------===//
7636 // VINSERTF128 - Insert packed floating-point values
7638 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7639 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7640 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7641 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7644 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7645 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7646 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7650 let Predicates = [HasAVX] in {
7651 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7653 (VINSERTF128rr VR256:$src1, VR128:$src2,
7654 (INSERT_get_vinsert128_imm VR256:$ins))>;
7655 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7657 (VINSERTF128rr VR256:$src1, VR128:$src2,
7658 (INSERT_get_vinsert128_imm VR256:$ins))>;
7660 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7662 (VINSERTF128rm VR256:$src1, addr:$src2,
7663 (INSERT_get_vinsert128_imm VR256:$ins))>;
7664 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7666 (VINSERTF128rm VR256:$src1, addr:$src2,
7667 (INSERT_get_vinsert128_imm VR256:$ins))>;
7670 let Predicates = [HasAVX1Only] in {
7671 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7673 (VINSERTF128rr VR256:$src1, VR128:$src2,
7674 (INSERT_get_vinsert128_imm VR256:$ins))>;
7675 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7677 (VINSERTF128rr VR256:$src1, VR128:$src2,
7678 (INSERT_get_vinsert128_imm VR256:$ins))>;
7679 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7681 (VINSERTF128rr VR256:$src1, VR128:$src2,
7682 (INSERT_get_vinsert128_imm VR256:$ins))>;
7683 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7685 (VINSERTF128rr VR256:$src1, VR128:$src2,
7686 (INSERT_get_vinsert128_imm VR256:$ins))>;
7688 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7690 (VINSERTF128rm VR256:$src1, addr:$src2,
7691 (INSERT_get_vinsert128_imm VR256:$ins))>;
7692 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7693 (bc_v4i32 (loadv2i64 addr:$src2)),
7695 (VINSERTF128rm VR256:$src1, addr:$src2,
7696 (INSERT_get_vinsert128_imm VR256:$ins))>;
7697 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7698 (bc_v16i8 (loadv2i64 addr:$src2)),
7700 (VINSERTF128rm VR256:$src1, addr:$src2,
7701 (INSERT_get_vinsert128_imm VR256:$ins))>;
7702 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7703 (bc_v8i16 (loadv2i64 addr:$src2)),
7705 (VINSERTF128rm VR256:$src1, addr:$src2,
7706 (INSERT_get_vinsert128_imm VR256:$ins))>;
7709 //===----------------------------------------------------------------------===//
7710 // VEXTRACTF128 - Extract packed floating-point values
7712 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7713 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7714 (ins VR256:$src1, i8imm:$src2),
7715 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7718 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7719 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7720 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7725 let Predicates = [HasAVX] in {
7726 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7727 (v4f32 (VEXTRACTF128rr
7728 (v8f32 VR256:$src1),
7729 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7730 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7731 (v2f64 (VEXTRACTF128rr
7732 (v4f64 VR256:$src1),
7733 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7735 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7736 (iPTR imm))), addr:$dst),
7737 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7738 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7739 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7740 (iPTR imm))), addr:$dst),
7741 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7742 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7745 let Predicates = [HasAVX1Only] in {
7746 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7747 (v2i64 (VEXTRACTF128rr
7748 (v4i64 VR256:$src1),
7749 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7750 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7751 (v4i32 (VEXTRACTF128rr
7752 (v8i32 VR256:$src1),
7753 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7754 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7755 (v8i16 (VEXTRACTF128rr
7756 (v16i16 VR256:$src1),
7757 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7758 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7759 (v16i8 (VEXTRACTF128rr
7760 (v32i8 VR256:$src1),
7761 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7763 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7764 (iPTR imm))), addr:$dst),
7765 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7766 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7767 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7768 (iPTR imm))), addr:$dst),
7769 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7770 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7771 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7772 (iPTR imm))), addr:$dst),
7773 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7774 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7775 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7776 (iPTR imm))), addr:$dst),
7777 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7778 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7781 //===----------------------------------------------------------------------===//
7782 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7784 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7785 Intrinsic IntLd, Intrinsic IntLd256,
7786 Intrinsic IntSt, Intrinsic IntSt256> {
7787 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7788 (ins VR128:$src1, f128mem:$src2),
7789 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7790 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7792 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7793 (ins VR256:$src1, f256mem:$src2),
7794 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7795 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7797 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7798 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7799 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7800 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7801 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7802 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7803 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7804 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7807 let ExeDomain = SSEPackedSingle in
7808 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7809 int_x86_avx_maskload_ps,
7810 int_x86_avx_maskload_ps_256,
7811 int_x86_avx_maskstore_ps,
7812 int_x86_avx_maskstore_ps_256>;
7813 let ExeDomain = SSEPackedDouble in
7814 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7815 int_x86_avx_maskload_pd,
7816 int_x86_avx_maskload_pd_256,
7817 int_x86_avx_maskstore_pd,
7818 int_x86_avx_maskstore_pd_256>;
7820 //===----------------------------------------------------------------------===//
7821 // VPERMIL - Permute Single and Double Floating-Point Values
7823 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7824 RegisterClass RC, X86MemOperand x86memop_f,
7825 X86MemOperand x86memop_i, PatFrag i_frag,
7826 Intrinsic IntVar, ValueType vt> {
7827 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7828 (ins RC:$src1, RC:$src2),
7829 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7830 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7831 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7832 (ins RC:$src1, x86memop_i:$src2),
7833 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7834 [(set RC:$dst, (IntVar RC:$src1,
7835 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7837 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7838 (ins RC:$src1, i8imm:$src2),
7839 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7840 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7841 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7842 (ins x86memop_f:$src1, i8imm:$src2),
7843 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7845 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7848 let ExeDomain = SSEPackedSingle in {
7849 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7850 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7851 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7852 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7854 let ExeDomain = SSEPackedDouble in {
7855 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7856 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7857 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7858 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7861 let Predicates = [HasAVX] in {
7862 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7863 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7864 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7865 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7866 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7868 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7869 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7870 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7872 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7873 (VPERMILPDri VR128:$src1, imm:$imm)>;
7874 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7875 (VPERMILPDmi addr:$src1, imm:$imm)>;
7878 //===----------------------------------------------------------------------===//
7879 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7881 let ExeDomain = SSEPackedSingle in {
7882 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7883 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7884 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7885 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7886 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7887 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7888 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7889 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7890 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7891 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7894 let Predicates = [HasAVX] in {
7895 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7896 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7897 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7898 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7899 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7902 let Predicates = [HasAVX1Only] in {
7903 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7904 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7905 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7906 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7907 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7908 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7909 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7910 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7912 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7913 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7914 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7915 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7916 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7917 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7918 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7919 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7920 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7921 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7922 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7923 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7926 //===----------------------------------------------------------------------===//
7927 // VZERO - Zero YMM registers
7929 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7930 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7931 // Zero All YMM registers
7932 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7933 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7935 // Zero Upper bits of YMM registers
7936 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7937 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7940 //===----------------------------------------------------------------------===//
7941 // Half precision conversion instructions
7942 //===----------------------------------------------------------------------===//
7943 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7944 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7945 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7946 [(set RC:$dst, (Int VR128:$src))]>,
7948 let neverHasSideEffects = 1, mayLoad = 1 in
7949 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7950 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7953 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7954 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7955 (ins RC:$src1, i32i8imm:$src2),
7956 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7957 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7959 let neverHasSideEffects = 1, mayStore = 1 in
7960 def mr : Ii8<0x1D, MRMDestMem, (outs),
7961 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7962 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7966 let Predicates = [HasF16C] in {
7967 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7968 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7969 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7970 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7973 //===----------------------------------------------------------------------===//
7974 // AVX2 Instructions
7975 //===----------------------------------------------------------------------===//
7977 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7978 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7979 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7980 X86MemOperand x86memop> {
7981 let isCommutable = 1 in
7982 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7983 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7984 !strconcat(OpcodeStr,
7985 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7986 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7988 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7989 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7990 !strconcat(OpcodeStr,
7991 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7994 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7998 let isCommutable = 0 in {
7999 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8000 VR128, memopv2i64, i128mem>;
8001 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8002 VR256, memopv4i64, i256mem>, VEX_L;
8005 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8007 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8008 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8010 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8012 //===----------------------------------------------------------------------===//
8013 // VPBROADCAST - Load from memory and broadcast to all elements of the
8014 // destination operand
8016 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8017 X86MemOperand x86memop, PatFrag ld_frag,
8018 Intrinsic Int128, Intrinsic Int256> {
8019 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8020 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8021 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
8022 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8023 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8025 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
8026 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8027 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8028 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
8029 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8030 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8032 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8036 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8037 int_x86_avx2_pbroadcastb_128,
8038 int_x86_avx2_pbroadcastb_256>;
8039 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8040 int_x86_avx2_pbroadcastw_128,
8041 int_x86_avx2_pbroadcastw_256>;
8042 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8043 int_x86_avx2_pbroadcastd_128,
8044 int_x86_avx2_pbroadcastd_256>;
8045 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8046 int_x86_avx2_pbroadcastq_128,
8047 int_x86_avx2_pbroadcastq_256>;
8049 let Predicates = [HasAVX2] in {
8050 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8051 (VPBROADCASTBrm addr:$src)>;
8052 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8053 (VPBROADCASTBYrm addr:$src)>;
8054 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8055 (VPBROADCASTWrm addr:$src)>;
8056 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8057 (VPBROADCASTWYrm addr:$src)>;
8058 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8059 (VPBROADCASTDrm addr:$src)>;
8060 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8061 (VPBROADCASTDYrm addr:$src)>;
8062 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8063 (VPBROADCASTQrm addr:$src)>;
8064 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8065 (VPBROADCASTQYrm addr:$src)>;
8067 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8068 (VPBROADCASTBrr VR128:$src)>;
8069 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8070 (VPBROADCASTBYrr VR128:$src)>;
8071 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8072 (VPBROADCASTWrr VR128:$src)>;
8073 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8074 (VPBROADCASTWYrr VR128:$src)>;
8075 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8076 (VPBROADCASTDrr VR128:$src)>;
8077 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8078 (VPBROADCASTDYrr VR128:$src)>;
8079 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8080 (VPBROADCASTQrr VR128:$src)>;
8081 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8082 (VPBROADCASTQYrr VR128:$src)>;
8083 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8084 (VBROADCASTSSrr VR128:$src)>;
8085 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8086 (VBROADCASTSSYrr VR128:$src)>;
8087 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8088 (VPBROADCASTQrr VR128:$src)>;
8089 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8090 (VBROADCASTSDYrr VR128:$src)>;
8092 // Provide fallback in case the load node that is used in the patterns above
8093 // is used by additional users, which prevents the pattern selection.
8094 let AddedComplexity = 20 in {
8095 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8096 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8097 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8098 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8099 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8100 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8102 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8103 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8104 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8105 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8106 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8107 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8111 // AVX1 broadcast patterns
8112 let Predicates = [HasAVX1Only] in {
8113 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8114 (VBROADCASTSSYrm addr:$src)>;
8115 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8116 (VBROADCASTSDYrm addr:$src)>;
8117 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8118 (VBROADCASTSSrm addr:$src)>;
8121 let Predicates = [HasAVX] in {
8122 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8123 (VBROADCASTSSYrm addr:$src)>;
8124 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8125 (VBROADCASTSDYrm addr:$src)>;
8126 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8127 (VBROADCASTSSrm addr:$src)>;
8129 // Provide fallback in case the load node that is used in the patterns above
8130 // is used by additional users, which prevents the pattern selection.
8131 let AddedComplexity = 20 in {
8132 // 128bit broadcasts:
8133 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8134 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8135 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8136 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8137 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8138 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8139 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8140 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8141 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8142 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8144 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8145 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8146 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8147 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8148 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8149 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8150 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8151 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8152 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8153 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8157 //===----------------------------------------------------------------------===//
8158 // VPERM - Permute instructions
8161 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8163 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8164 (ins VR256:$src1, VR256:$src2),
8165 !strconcat(OpcodeStr,
8166 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8168 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8170 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8171 (ins VR256:$src1, i256mem:$src2),
8172 !strconcat(OpcodeStr,
8173 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8175 (OpVT (X86VPermv VR256:$src1,
8176 (bitconvert (mem_frag addr:$src2)))))]>,
8180 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
8181 let ExeDomain = SSEPackedSingle in
8182 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
8184 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8186 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8187 (ins VR256:$src1, i8imm:$src2),
8188 !strconcat(OpcodeStr,
8189 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8191 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8193 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8194 (ins i256mem:$src1, i8imm:$src2),
8195 !strconcat(OpcodeStr,
8196 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8198 (OpVT (X86VPermi (mem_frag addr:$src1),
8199 (i8 imm:$src2))))]>, VEX, VEX_L;
8202 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
8203 let ExeDomain = SSEPackedDouble in
8204 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
8206 //===----------------------------------------------------------------------===//
8207 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8209 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8210 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8211 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8212 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8213 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8214 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8215 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8216 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8217 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
8218 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8220 let Predicates = [HasAVX2] in {
8221 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8222 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8223 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8224 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8225 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8226 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8228 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
8230 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8231 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8232 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
8233 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8234 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
8236 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8240 //===----------------------------------------------------------------------===//
8241 // VINSERTI128 - Insert packed integer values
8243 let neverHasSideEffects = 1 in {
8244 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8245 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8246 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8249 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8250 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8251 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8255 let Predicates = [HasAVX2] in {
8256 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8258 (VINSERTI128rr VR256:$src1, VR128:$src2,
8259 (INSERT_get_vinsert128_imm VR256:$ins))>;
8260 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8262 (VINSERTI128rr VR256:$src1, VR128:$src2,
8263 (INSERT_get_vinsert128_imm VR256:$ins))>;
8264 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8266 (VINSERTI128rr VR256:$src1, VR128:$src2,
8267 (INSERT_get_vinsert128_imm VR256:$ins))>;
8268 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8270 (VINSERTI128rr VR256:$src1, VR128:$src2,
8271 (INSERT_get_vinsert128_imm VR256:$ins))>;
8273 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8275 (VINSERTI128rm VR256:$src1, addr:$src2,
8276 (INSERT_get_vinsert128_imm VR256:$ins))>;
8277 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8278 (bc_v4i32 (loadv2i64 addr:$src2)),
8280 (VINSERTI128rm VR256:$src1, addr:$src2,
8281 (INSERT_get_vinsert128_imm VR256:$ins))>;
8282 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8283 (bc_v16i8 (loadv2i64 addr:$src2)),
8285 (VINSERTI128rm VR256:$src1, addr:$src2,
8286 (INSERT_get_vinsert128_imm VR256:$ins))>;
8287 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8288 (bc_v8i16 (loadv2i64 addr:$src2)),
8290 (VINSERTI128rm VR256:$src1, addr:$src2,
8291 (INSERT_get_vinsert128_imm VR256:$ins))>;
8294 //===----------------------------------------------------------------------===//
8295 // VEXTRACTI128 - Extract packed integer values
8297 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8298 (ins VR256:$src1, i8imm:$src2),
8299 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8301 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8303 let neverHasSideEffects = 1, mayStore = 1 in
8304 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8305 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8306 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8309 let Predicates = [HasAVX2] in {
8310 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8311 (v2i64 (VEXTRACTI128rr
8312 (v4i64 VR256:$src1),
8313 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8314 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8315 (v4i32 (VEXTRACTI128rr
8316 (v8i32 VR256:$src1),
8317 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8318 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8319 (v8i16 (VEXTRACTI128rr
8320 (v16i16 VR256:$src1),
8321 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8322 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8323 (v16i8 (VEXTRACTI128rr
8324 (v32i8 VR256:$src1),
8325 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8327 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8328 (iPTR imm))), addr:$dst),
8329 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8330 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8331 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8332 (iPTR imm))), addr:$dst),
8333 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8334 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8335 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8336 (iPTR imm))), addr:$dst),
8337 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8338 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8339 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8340 (iPTR imm))), addr:$dst),
8341 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8342 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8345 //===----------------------------------------------------------------------===//
8346 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8348 multiclass avx2_pmovmask<string OpcodeStr,
8349 Intrinsic IntLd128, Intrinsic IntLd256,
8350 Intrinsic IntSt128, Intrinsic IntSt256> {
8351 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8352 (ins VR128:$src1, i128mem:$src2),
8353 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8354 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8355 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8356 (ins VR256:$src1, i256mem:$src2),
8357 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8358 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8360 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8361 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8362 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8363 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8364 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8365 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8367 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8370 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8371 int_x86_avx2_maskload_d,
8372 int_x86_avx2_maskload_d_256,
8373 int_x86_avx2_maskstore_d,
8374 int_x86_avx2_maskstore_d_256>;
8375 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8376 int_x86_avx2_maskload_q,
8377 int_x86_avx2_maskload_q_256,
8378 int_x86_avx2_maskstore_q,
8379 int_x86_avx2_maskstore_q_256>, VEX_W;
8382 //===----------------------------------------------------------------------===//
8383 // Variable Bit Shifts
8385 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8386 ValueType vt128, ValueType vt256> {
8387 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8388 (ins VR128:$src1, VR128:$src2),
8389 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8391 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8393 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8394 (ins VR128:$src1, i128mem:$src2),
8395 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8397 (vt128 (OpNode VR128:$src1,
8398 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8400 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8401 (ins VR256:$src1, VR256:$src2),
8402 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8404 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8406 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8407 (ins VR256:$src1, i256mem:$src2),
8408 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8410 (vt256 (OpNode VR256:$src1,
8411 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8415 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8416 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8417 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8418 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8419 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8421 //===----------------------------------------------------------------------===//
8422 // VGATHER - GATHER Operations
8423 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8424 X86MemOperand memop128, X86MemOperand memop256> {
8425 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8426 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8427 !strconcat(OpcodeStr,
8428 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8430 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8431 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8432 !strconcat(OpcodeStr,
8433 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8434 []>, VEX_4VOp3, VEX_L;
8437 let mayLoad = 1, Constraints
8438 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8440 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8441 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8442 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8443 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8444 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8445 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8446 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8447 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;