1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 def SSE_BIT_ITINS_P : OpndItins<
124 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
127 let Sched = WriteVecALU in {
128 def SSE_INTALU_ITINS_P : OpndItins<
129 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
132 def SSE_INTALUQ_ITINS_P : OpndItins<
133 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
137 let Sched = WriteVecIMul in
138 def SSE_INTMUL_ITINS_P : OpndItins<
139 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
142 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
143 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
146 def SSE_MOVA_ITINS : OpndItins<
147 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
150 def SSE_MOVU_ITINS : OpndItins<
151 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
154 def SSE_DPPD_ITINS : OpndItins<
155 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
158 def SSE_DPPS_ITINS : OpndItins<
159 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
162 def DEFAULT_ITINS : OpndItins<
163 IIC_ALU_NONMEM, IIC_ALU_MEM
166 def SSE_EXTRACT_ITINS : OpndItins<
167 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
170 def SSE_INSERT_ITINS : OpndItins<
171 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
174 def SSE_MPSADBW_ITINS : OpndItins<
175 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
178 def SSE_PMULLD_ITINS : OpndItins<
179 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
182 //===----------------------------------------------------------------------===//
183 // SSE 1 & 2 Instructions Classes
184 //===----------------------------------------------------------------------===//
186 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
187 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
188 RegisterClass RC, X86MemOperand x86memop,
191 let isCommutable = 1 in {
192 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
194 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
196 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
197 Sched<[itins.Sched]>;
199 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
201 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
203 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
204 Sched<[itins.Sched.Folded, ReadAfterLd]>;
207 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
208 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
209 string asm, string SSEVer, string FPSizeStr,
210 Operand memopr, ComplexPattern mem_cpat,
213 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
215 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
216 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
217 [(set RC:$dst, (!cast<Intrinsic>(
218 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
219 RC:$src1, RC:$src2))], itins.rr>,
220 Sched<[itins.Sched]>;
221 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
223 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
224 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
225 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
226 SSEVer, "_", OpcodeStr, FPSizeStr))
227 RC:$src1, mem_cpat:$src2))], itins.rm>,
228 Sched<[itins.Sched.Folded, ReadAfterLd]>;
231 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
232 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
233 RegisterClass RC, ValueType vt,
234 X86MemOperand x86memop, PatFrag mem_frag,
235 Domain d, OpndItins itins, bit Is2Addr = 1> {
236 let isCommutable = 1 in
237 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
241 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
242 Sched<[itins.Sched]>;
244 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
246 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
247 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
248 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
250 Sched<[itins.Sched.Folded, ReadAfterLd]>;
253 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
254 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
255 string OpcodeStr, X86MemOperand x86memop,
256 list<dag> pat_rr, list<dag> pat_rm,
258 let isCommutable = 1, hasSideEffects = 0 in
259 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
261 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
262 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
263 pat_rr, NoItinerary, d>,
264 Sched<[WriteVecLogic]>;
265 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
267 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
269 pat_rm, NoItinerary, d>,
270 Sched<[WriteVecLogicLd, ReadAfterLd]>;
273 //===----------------------------------------------------------------------===//
274 // Non-instruction patterns
275 //===----------------------------------------------------------------------===//
277 // A vector extract of the first f32/f64 position is a subregister copy
278 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
279 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
280 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
281 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
283 // A 128-bit subvector extract from the first 256-bit vector position
284 // is a subregister copy that needs no instruction.
285 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
286 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
287 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
288 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
290 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
291 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
292 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
293 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
295 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
296 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
297 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
298 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
300 // A 128-bit subvector insert to the first 256-bit vector position
301 // is a subregister copy that needs no instruction.
302 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
303 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
304 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
305 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
306 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
307 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
308 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
309 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
310 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
311 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
312 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
313 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
314 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
317 // Implicitly promote a 32-bit scalar to a vector.
318 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
319 (COPY_TO_REGCLASS FR32:$src, VR128)>;
320 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
321 (COPY_TO_REGCLASS FR32:$src, VR128)>;
322 // Implicitly promote a 64-bit scalar to a vector.
323 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
324 (COPY_TO_REGCLASS FR64:$src, VR128)>;
325 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
326 (COPY_TO_REGCLASS FR64:$src, VR128)>;
328 // Bitcasts between 128-bit vector types. Return the original type since
329 // no instruction is needed for the conversion
330 let Predicates = [HasSSE2] in {
331 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
332 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
333 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
334 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
335 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
336 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
337 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
338 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
339 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
340 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
341 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
342 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
343 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
344 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
345 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
346 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
347 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
348 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
349 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
350 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
351 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
352 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
353 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
354 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
355 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
356 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
357 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
358 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
359 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
360 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
363 // Bitcasts between 256-bit vector types. Return the original type since
364 // no instruction is needed for the conversion
365 let Predicates = [HasAVX] in {
366 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
367 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
368 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
369 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
370 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
371 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
372 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
373 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
374 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
375 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
376 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
377 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
378 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
379 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
380 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
381 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
382 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
383 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
384 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
385 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
386 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
387 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
388 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
389 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
390 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
391 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
392 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
393 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
394 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
395 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
398 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
399 // This is expanded by ExpandPostRAPseudos.
400 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
401 isPseudo = 1, SchedRW = [WriteZero] in {
402 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
403 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
404 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
405 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
408 //===----------------------------------------------------------------------===//
409 // AVX & SSE - Zero/One Vectors
410 //===----------------------------------------------------------------------===//
412 // Alias instruction that maps zero vector to pxor / xorp* for sse.
413 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
414 // swizzled by ExecutionDepsFix to pxor.
415 // We set canFoldAsLoad because this can be converted to a constant-pool
416 // load of an all-zeros value if folding it would be beneficial.
417 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
418 isPseudo = 1, SchedRW = [WriteZero] in {
419 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
420 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
423 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
424 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
425 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
426 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
427 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
430 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
431 // and doesn't need it because on sandy bridge the register is set to zero
432 // at the rename stage without using any execution unit, so SET0PSY
433 // and SET0PDY can be used for vector int instructions without penalty
434 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
435 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
436 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
437 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
440 let Predicates = [HasAVX] in
441 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
443 let Predicates = [HasAVX2] in {
444 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
445 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
446 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
447 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
450 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
451 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
452 let Predicates = [HasAVX1Only] in {
453 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
454 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
455 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
457 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
458 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
459 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
461 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
462 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
463 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
465 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
466 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
467 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-ones value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
476 let Predicates = [HasAVX2] in
477 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
478 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
482 //===----------------------------------------------------------------------===//
483 // SSE 1 & 2 - Move FP Scalar Instructions
485 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
486 // register copies because it's a partial register update; Register-to-register
487 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
488 // that the insert be implementable in terms of a copy, and just mentioned, we
489 // don't use movss/movsd for copies.
490 //===----------------------------------------------------------------------===//
492 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
493 X86MemOperand x86memop, string base_opc,
495 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
496 (ins VR128:$src1, RC:$src2),
497 !strconcat(base_opc, asm_opr),
498 [(set VR128:$dst, (vt (OpNode VR128:$src1,
499 (scalar_to_vector RC:$src2))))],
500 IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
502 // For the disassembler
503 let isCodeGenOnly = 1, hasSideEffects = 0 in
504 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
505 (ins VR128:$src1, RC:$src2),
506 !strconcat(base_opc, asm_opr),
507 [], IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
510 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
511 X86MemOperand x86memop, string OpcodeStr> {
513 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
514 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
517 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
519 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
520 VEX, VEX_LIG, Sched<[WriteStore]>;
522 let Constraints = "$src1 = $dst" in {
523 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
524 "\t{$src2, $dst|$dst, $src2}">;
527 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
528 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
529 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
533 // Loading from memory automatically zeroing upper bits.
534 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
535 PatFrag mem_pat, string OpcodeStr> {
536 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
538 [(set RC:$dst, (mem_pat addr:$src))],
539 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
540 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
541 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
542 [(set RC:$dst, (mem_pat addr:$src))],
543 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
546 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
547 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
549 let canFoldAsLoad = 1, isReMaterializable = 1 in {
550 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
552 let AddedComplexity = 20 in
553 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
557 let Predicates = [UseAVX] in {
558 let AddedComplexity = 15 in {
559 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
560 // MOVS{S,D} to the lower bits.
561 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
562 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
563 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
564 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
565 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
566 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
567 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
568 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
570 // Move low f32 and clear high bits.
571 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
572 (SUBREG_TO_REG (i32 0),
573 (VMOVSSrr (v4f32 (V_SET0)),
574 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
575 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
576 (SUBREG_TO_REG (i32 0),
577 (VMOVSSrr (v4i32 (V_SET0)),
578 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
581 let AddedComplexity = 20 in {
582 // MOVSSrm zeros the high parts of the register; represent this
583 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
584 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
585 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
586 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
587 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
588 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
589 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
591 // MOVSDrm zeros the high parts of the register; represent this
592 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
593 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
594 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
595 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
596 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
597 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
598 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
599 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
600 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
601 def : Pat<(v2f64 (X86vzload addr:$src)),
602 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
604 // Represent the same patterns above but in the form they appear for
606 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
607 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
608 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
609 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
610 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
612 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
613 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
616 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
617 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
618 (SUBREG_TO_REG (i32 0),
619 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
621 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
622 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
623 (SUBREG_TO_REG (i64 0),
624 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
626 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
627 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
628 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
630 // Move low f64 and clear high bits.
631 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
632 (SUBREG_TO_REG (i32 0),
633 (VMOVSDrr (v2f64 (V_SET0)),
634 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
636 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
637 (SUBREG_TO_REG (i32 0),
638 (VMOVSDrr (v2i64 (V_SET0)),
639 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
641 // Extract and store.
642 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
644 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
645 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
647 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
649 // Shuffle with VMOVSS
650 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
651 (VMOVSSrr (v4i32 VR128:$src1),
652 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
653 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
654 (VMOVSSrr (v4f32 VR128:$src1),
655 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
658 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
659 (SUBREG_TO_REG (i32 0),
660 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
661 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
663 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
666 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
669 // Shuffle with VMOVSD
670 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
671 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
674 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
675 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
676 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
680 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
681 (SUBREG_TO_REG (i32 0),
682 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
683 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
685 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
686 (SUBREG_TO_REG (i32 0),
687 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
688 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
692 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
693 // is during lowering, where it's not possible to recognize the fold cause
694 // it has two uses through a bitcast. One use disappears at isel time and the
695 // fold opportunity reappears.
696 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
697 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
698 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
699 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
700 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
701 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
702 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
703 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
706 let Predicates = [UseSSE1] in {
707 let AddedComplexity = 15 in {
708 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
709 // MOVSS to the lower bits.
710 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
711 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
712 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
713 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
714 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
715 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
718 let AddedComplexity = 20 in {
719 // MOVSSrm already zeros the high parts of the register.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
721 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
722 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
723 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
724 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
728 // Extract and store.
729 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
731 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
733 // Shuffle with MOVSS
734 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
735 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
736 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
737 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
740 let Predicates = [UseSSE2] in {
741 let AddedComplexity = 15 in {
742 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
743 // MOVSD to the lower bits.
744 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
745 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
748 let AddedComplexity = 20 in {
749 // MOVSDrm already zeros the high parts of the register.
750 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
751 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
752 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
753 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
754 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
755 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
756 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
757 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
758 def : Pat<(v2f64 (X86vzload addr:$src)),
759 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 // Extract and store.
763 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
765 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
767 // Shuffle with MOVSD
768 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
769 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
770 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
771 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
772 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
773 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
774 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
775 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
777 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
778 // is during lowering, where it's not possible to recognize the fold cause
779 // it has two uses through a bitcast. One use disappears at isel time and the
780 // fold opportunity reappears.
781 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
782 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
783 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
784 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
785 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
786 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
788 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
791 //===----------------------------------------------------------------------===//
792 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
793 //===----------------------------------------------------------------------===//
795 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
796 X86MemOperand x86memop, PatFrag ld_frag,
797 string asm, Domain d,
799 bit IsReMaterializable = 1> {
800 let neverHasSideEffects = 1 in
801 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
802 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
804 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
805 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
806 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
807 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
811 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
812 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
814 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
815 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
817 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
818 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
820 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
821 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
824 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
829 TB, OpSize, VEX, VEX_L;
830 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 TB, OpSize, VEX, VEX_L;
836 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
837 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
839 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
840 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
842 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
843 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
845 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
846 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let SchedRW = [WriteStore] in {
850 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
851 "movaps\t{$src, $dst|$dst, $src}",
852 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
853 IIC_SSE_MOVA_P_MR>, VEX;
854 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
855 "movapd\t{$src, $dst|$dst, $src}",
856 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
857 IIC_SSE_MOVA_P_MR>, VEX;
858 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
859 "movups\t{$src, $dst|$dst, $src}",
860 [(store (v4f32 VR128:$src), addr:$dst)],
861 IIC_SSE_MOVU_P_MR>, VEX;
862 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
863 "movupd\t{$src, $dst|$dst, $src}",
864 [(store (v2f64 VR128:$src), addr:$dst)],
865 IIC_SSE_MOVU_P_MR>, VEX;
866 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
870 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
874 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v8f32 VR256:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
878 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v4f64 VR256:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
885 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
886 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
888 "movaps\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVA_P_RR>, VEX;
890 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
892 "movapd\t{$src, $dst|$dst, $src}", [],
893 IIC_SSE_MOVA_P_RR>, VEX;
894 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
896 "movups\t{$src, $dst|$dst, $src}", [],
897 IIC_SSE_MOVU_P_RR>, VEX;
898 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
900 "movupd\t{$src, $dst|$dst, $src}", [],
901 IIC_SSE_MOVU_P_RR>, VEX;
902 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
904 "movaps\t{$src, $dst|$dst, $src}", [],
905 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
906 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
908 "movapd\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
910 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
912 "movups\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
914 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
916 "movupd\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
920 let Predicates = [HasAVX] in {
921 def : Pat<(v8i32 (X86vzmovl
922 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
923 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
924 def : Pat<(v4i64 (X86vzmovl
925 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
926 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
927 def : Pat<(v8f32 (X86vzmovl
928 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
929 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
930 def : Pat<(v4f64 (X86vzmovl
931 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
932 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
936 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
937 (VMOVUPSYmr addr:$dst, VR256:$src)>;
938 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
939 (VMOVUPDYmr addr:$dst, VR256:$src)>;
941 let SchedRW = [WriteStore] in {
942 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
943 "movaps\t{$src, $dst|$dst, $src}",
944 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
946 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
947 "movapd\t{$src, $dst|$dst, $src}",
948 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
950 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
951 "movups\t{$src, $dst|$dst, $src}",
952 [(store (v4f32 VR128:$src), addr:$dst)],
954 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
955 "movupd\t{$src, $dst|$dst, $src}",
956 [(store (v2f64 VR128:$src), addr:$dst)],
961 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
962 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
963 "movaps\t{$src, $dst|$dst, $src}", [],
965 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
966 "movapd\t{$src, $dst|$dst, $src}", [],
968 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}", [],
971 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
972 "movupd\t{$src, $dst|$dst, $src}", [],
976 let Predicates = [HasAVX] in {
977 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
978 (VMOVUPSmr addr:$dst, VR128:$src)>;
979 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
980 (VMOVUPDmr addr:$dst, VR128:$src)>;
983 let Predicates = [UseSSE1] in
984 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
985 (MOVUPSmr addr:$dst, VR128:$src)>;
986 let Predicates = [UseSSE2] in
987 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
988 (MOVUPDmr addr:$dst, VR128:$src)>;
990 // Use vmovaps/vmovups for AVX integer load/store.
991 let Predicates = [HasAVX] in {
992 // 128-bit load/store
993 def : Pat<(alignedloadv2i64 addr:$src),
994 (VMOVAPSrm addr:$src)>;
995 def : Pat<(loadv2i64 addr:$src),
996 (VMOVUPSrm addr:$src)>;
998 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
999 (VMOVAPSmr addr:$dst, VR128:$src)>;
1000 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1001 (VMOVAPSmr addr:$dst, VR128:$src)>;
1002 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1003 (VMOVAPSmr addr:$dst, VR128:$src)>;
1004 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1005 (VMOVAPSmr addr:$dst, VR128:$src)>;
1006 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1007 (VMOVUPSmr addr:$dst, VR128:$src)>;
1008 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1009 (VMOVUPSmr addr:$dst, VR128:$src)>;
1010 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1011 (VMOVUPSmr addr:$dst, VR128:$src)>;
1012 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1013 (VMOVUPSmr addr:$dst, VR128:$src)>;
1015 // 256-bit load/store
1016 def : Pat<(alignedloadv4i64 addr:$src),
1017 (VMOVAPSYrm addr:$src)>;
1018 def : Pat<(loadv4i64 addr:$src),
1019 (VMOVUPSYrm addr:$src)>;
1020 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1021 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1022 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1023 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1024 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1025 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1026 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1027 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1028 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1029 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1030 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1031 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1032 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1033 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1034 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1035 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1037 // Special patterns for storing subvector extracts of lower 128-bits
1038 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1039 def : Pat<(alignedstore (v2f64 (extract_subvector
1040 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1041 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1042 def : Pat<(alignedstore (v4f32 (extract_subvector
1043 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1044 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1045 def : Pat<(alignedstore (v2i64 (extract_subvector
1046 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1047 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1048 def : Pat<(alignedstore (v4i32 (extract_subvector
1049 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1050 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1051 def : Pat<(alignedstore (v8i16 (extract_subvector
1052 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1053 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1054 def : Pat<(alignedstore (v16i8 (extract_subvector
1055 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1056 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1058 def : Pat<(store (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(store (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(store (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(store (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(store (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(store (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1078 // Use movaps / movups for SSE integer load / store (one byte shorter).
1079 // The instructions selected below are then converted to MOVDQA/MOVDQU
1080 // during the SSE domain pass.
1081 let Predicates = [UseSSE1] in {
1082 def : Pat<(alignedloadv2i64 addr:$src),
1083 (MOVAPSrm addr:$src)>;
1084 def : Pat<(loadv2i64 addr:$src),
1085 (MOVUPSrm addr:$src)>;
1087 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1088 (MOVAPSmr addr:$dst, VR128:$src)>;
1089 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1090 (MOVAPSmr addr:$dst, VR128:$src)>;
1091 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1092 (MOVAPSmr addr:$dst, VR128:$src)>;
1093 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1094 (MOVAPSmr addr:$dst, VR128:$src)>;
1095 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1096 (MOVUPSmr addr:$dst, VR128:$src)>;
1097 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1098 (MOVUPSmr addr:$dst, VR128:$src)>;
1099 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1100 (MOVUPSmr addr:$dst, VR128:$src)>;
1101 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1102 (MOVUPSmr addr:$dst, VR128:$src)>;
1105 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1106 // bits are disregarded. FIXME: Set encoding to pseudo!
1107 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1108 let isCodeGenOnly = 1 in {
1109 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1110 "movaps\t{$src, $dst|$dst, $src}",
1111 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 IIC_SSE_MOVA_P_RM>, VEX;
1113 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1114 "movapd\t{$src, $dst|$dst, $src}",
1115 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1116 IIC_SSE_MOVA_P_RM>, VEX;
1117 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1118 "movaps\t{$src, $dst|$dst, $src}",
1119 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1121 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1122 "movapd\t{$src, $dst|$dst, $src}",
1123 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1128 //===----------------------------------------------------------------------===//
1129 // SSE 1 & 2 - Move Low packed FP Instructions
1130 //===----------------------------------------------------------------------===//
1132 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1133 string base_opc, string asm_opr,
1134 InstrItinClass itin> {
1135 def PSrm : PI<opc, MRMSrcMem,
1136 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1137 !strconcat(base_opc, "s", asm_opr),
1139 (psnode VR128:$src1,
1140 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1141 itin, SSEPackedSingle>, TB,
1142 Sched<[WriteShuffleLd, ReadAfterLd]>;
1144 def PDrm : PI<opc, MRMSrcMem,
1145 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1146 !strconcat(base_opc, "d", asm_opr),
1147 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1148 (scalar_to_vector (loadf64 addr:$src2)))))],
1149 itin, SSEPackedDouble>, TB, OpSize,
1150 Sched<[WriteShuffleLd, ReadAfterLd]>;
1154 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1155 string base_opc, InstrItinClass itin> {
1156 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1157 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1160 let Constraints = "$src1 = $dst" in
1161 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1162 "\t{$src2, $dst|$dst, $src2}",
1166 let AddedComplexity = 20 in {
1167 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1171 let SchedRW = [WriteStore] in {
1172 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1173 "movlps\t{$src, $dst|$dst, $src}",
1174 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1175 (iPTR 0))), addr:$dst)],
1176 IIC_SSE_MOV_LH>, VEX;
1177 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1178 "movlpd\t{$src, $dst|$dst, $src}",
1179 [(store (f64 (vector_extract (v2f64 VR128:$src),
1180 (iPTR 0))), addr:$dst)],
1181 IIC_SSE_MOV_LH>, VEX;
1182 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1183 "movlps\t{$src, $dst|$dst, $src}",
1184 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1185 (iPTR 0))), addr:$dst)],
1187 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1188 "movlpd\t{$src, $dst|$dst, $src}",
1189 [(store (f64 (vector_extract (v2f64 VR128:$src),
1190 (iPTR 0))), addr:$dst)],
1194 let Predicates = [HasAVX] in {
1195 // Shuffle with VMOVLPS
1196 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1197 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1198 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1199 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1201 // Shuffle with VMOVLPD
1202 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1203 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1204 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1205 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1208 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1210 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1211 def : Pat<(store (v4i32 (X86Movlps
1212 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1213 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1214 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1216 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1217 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1219 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1222 let Predicates = [UseSSE1] in {
1223 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1224 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1225 (iPTR 0))), addr:$src1),
1226 (MOVLPSmr addr:$src1, VR128:$src2)>;
1228 // Shuffle with MOVLPS
1229 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1230 (MOVLPSrm VR128:$src1, addr:$src2)>;
1231 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1232 (MOVLPSrm VR128:$src1, addr:$src2)>;
1233 def : Pat<(X86Movlps VR128:$src1,
1234 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1235 (MOVLPSrm VR128:$src1, addr:$src2)>;
1238 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1240 (MOVLPSmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v4i32 (X86Movlps
1242 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1244 (MOVLPSmr addr:$src1, VR128:$src2)>;
1247 let Predicates = [UseSSE2] in {
1248 // Shuffle with MOVLPD
1249 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1250 (MOVLPDrm VR128:$src1, addr:$src2)>;
1251 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1252 (MOVLPDrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1257 (MOVLPDmr addr:$src1, VR128:$src2)>;
1258 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1260 (MOVLPDmr addr:$src1, VR128:$src2)>;
1263 //===----------------------------------------------------------------------===//
1264 // SSE 1 & 2 - Move Hi packed FP Instructions
1265 //===----------------------------------------------------------------------===//
1267 let AddedComplexity = 20 in {
1268 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1272 let SchedRW = [WriteStore] in {
1273 // v2f64 extract element 1 is always custom lowered to unpack high to low
1274 // and extract element 0 so the non-store version isn't too horrible.
1275 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1276 "movhps\t{$src, $dst|$dst, $src}",
1277 [(store (f64 (vector_extract
1278 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1279 (bc_v2f64 (v4f32 VR128:$src))),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1281 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1282 "movhpd\t{$src, $dst|$dst, $src}",
1283 [(store (f64 (vector_extract
1284 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1285 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1286 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1287 "movhps\t{$src, $dst|$dst, $src}",
1288 [(store (f64 (vector_extract
1289 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1290 (bc_v2f64 (v4f32 VR128:$src))),
1291 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1292 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1293 "movhpd\t{$src, $dst|$dst, $src}",
1294 [(store (f64 (vector_extract
1295 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1296 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1299 let Predicates = [HasAVX] in {
1301 def : Pat<(X86Movlhps VR128:$src1,
1302 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1303 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1304 def : Pat<(X86Movlhps VR128:$src1,
1305 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1306 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1308 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1309 // is during lowering, where it's not possible to recognize the load fold
1310 // cause it has two uses through a bitcast. One use disappears at isel time
1311 // and the fold opportunity reappears.
1312 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1313 (scalar_to_vector (loadf64 addr:$src2)))),
1314 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1317 let Predicates = [UseSSE1] in {
1319 def : Pat<(X86Movlhps VR128:$src1,
1320 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1321 (MOVHPSrm VR128:$src1, addr:$src2)>;
1322 def : Pat<(X86Movlhps VR128:$src1,
1323 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1324 (MOVHPSrm VR128:$src1, addr:$src2)>;
1327 let Predicates = [UseSSE2] in {
1328 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1329 // is during lowering, where it's not possible to recognize the load fold
1330 // cause it has two uses through a bitcast. One use disappears at isel time
1331 // and the fold opportunity reappears.
1332 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1333 (scalar_to_vector (loadf64 addr:$src2)))),
1334 (MOVHPDrm VR128:$src1, addr:$src2)>;
1337 //===----------------------------------------------------------------------===//
1338 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1339 //===----------------------------------------------------------------------===//
1341 let AddedComplexity = 20, Predicates = [UseAVX] in {
1342 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1343 (ins VR128:$src1, VR128:$src2),
1344 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1346 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1348 VEX_4V, Sched<[WriteShuffle]>;
1349 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1350 (ins VR128:$src1, VR128:$src2),
1351 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1353 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 VEX_4V, Sched<[WriteShuffle]>;
1357 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1358 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1359 (ins VR128:$src1, VR128:$src2),
1360 "movlhps\t{$src2, $dst|$dst, $src2}",
1362 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1363 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1364 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1365 (ins VR128:$src1, VR128:$src2),
1366 "movhlps\t{$src2, $dst|$dst, $src2}",
1368 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1369 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1372 let Predicates = [UseAVX] in {
1374 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1375 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1376 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1377 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1380 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1381 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1384 let Predicates = [UseSSE1] in {
1386 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1387 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1388 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1389 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1392 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1393 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1396 //===----------------------------------------------------------------------===//
1397 // SSE 1 & 2 - Conversion Instructions
1398 //===----------------------------------------------------------------------===//
1400 def SSE_CVT_PD : OpndItins<
1401 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1404 let Sched = WriteCvtI2F in
1405 def SSE_CVT_PS : OpndItins<
1406 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1409 let Sched = WriteCvtI2F in
1410 def SSE_CVT_Scalar : OpndItins<
1411 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1414 let Sched = WriteCvtF2I in
1415 def SSE_CVT_SS2SI_32 : OpndItins<
1416 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1419 let Sched = WriteCvtF2I in
1420 def SSE_CVT_SS2SI_64 : OpndItins<
1421 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1424 let Sched = WriteCvtF2I in
1425 def SSE_CVT_SD2SI : OpndItins<
1426 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1429 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1431 string asm, OpndItins itins> {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1433 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1434 itins.rr>, Sched<[itins.Sched]>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1436 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1437 itins.rm>, Sched<[itins.Sched.Folded]>;
1440 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1441 X86MemOperand x86memop, string asm, Domain d,
1443 let neverHasSideEffects = 1 in {
1444 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1445 [], itins.rr, d>, Sched<[itins.Sched]>;
1447 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1448 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1452 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1453 X86MemOperand x86memop, string asm> {
1454 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1455 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1456 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1457 Sched<[WriteCvtI2F]>;
1459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1460 (ins DstRC:$src1, x86memop:$src),
1461 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1462 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1463 } // neverHasSideEffects = 1
1466 let Predicates = [UseAVX] in {
1467 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1468 "cvttss2si\t{$src, $dst|$dst, $src}",
1471 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1472 "cvttss2si\t{$src, $dst|$dst, $src}",
1474 XS, VEX, VEX_W, VEX_LIG;
1475 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1476 "cvttsd2si\t{$src, $dst|$dst, $src}",
1479 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1480 "cvttsd2si\t{$src, $dst|$dst, $src}",
1482 XD, VEX, VEX_W, VEX_LIG;
1484 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1485 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1486 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1487 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1488 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1489 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1490 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1491 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1492 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1493 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1494 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1495 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1496 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1497 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1498 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1499 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1501 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1502 // register, but the same isn't true when only using memory operands,
1503 // provide other assembly "l" and "q" forms to address this explicitly
1504 // where appropriate to do so.
1505 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1506 XS, VEX_4V, VEX_LIG;
1507 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1508 XS, VEX_4V, VEX_W, VEX_LIG;
1509 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1510 XD, VEX_4V, VEX_LIG;
1511 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1512 XD, VEX_4V, VEX_W, VEX_LIG;
1514 let Predicates = [UseAVX] in {
1515 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1516 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1517 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1518 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1520 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1521 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1522 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1523 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1524 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1525 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1526 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1527 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1529 def : Pat<(f32 (sint_to_fp GR32:$src)),
1530 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1531 def : Pat<(f32 (sint_to_fp GR64:$src)),
1532 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1533 def : Pat<(f64 (sint_to_fp GR32:$src)),
1534 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1535 def : Pat<(f64 (sint_to_fp GR64:$src)),
1536 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1539 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1540 "cvttss2si\t{$src, $dst|$dst, $src}",
1541 SSE_CVT_SS2SI_32>, XS;
1542 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1543 "cvttss2si\t{$src, $dst|$dst, $src}",
1544 SSE_CVT_SS2SI_64>, XS, REX_W;
1545 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1546 "cvttsd2si\t{$src, $dst|$dst, $src}",
1548 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1549 "cvttsd2si\t{$src, $dst|$dst, $src}",
1550 SSE_CVT_SD2SI>, XD, REX_W;
1551 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1552 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1553 SSE_CVT_Scalar>, XS;
1554 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1555 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1556 SSE_CVT_Scalar>, XS, REX_W;
1557 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1558 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1559 SSE_CVT_Scalar>, XD;
1560 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1561 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1562 SSE_CVT_Scalar>, XD, REX_W;
1564 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1565 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1566 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1567 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1568 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1569 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1570 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1571 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1572 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1573 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1574 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1575 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1576 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1577 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1578 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1579 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1581 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1582 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1583 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1584 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1586 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1587 // and/or XMM operand(s).
1589 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1590 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1591 string asm, OpndItins itins> {
1592 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1593 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1594 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1595 Sched<[itins.Sched]>;
1596 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1597 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1598 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1599 Sched<[itins.Sched.Folded]>;
1602 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1603 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1604 PatFrag ld_frag, string asm, OpndItins itins,
1606 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1608 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1609 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1610 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1611 itins.rr>, Sched<[itins.Sched]>;
1612 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1613 (ins DstRC:$src1, x86memop:$src2),
1615 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1616 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1617 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1618 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1621 let Predicates = [UseAVX] in {
1622 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1623 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1624 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1625 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1626 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1627 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1629 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1630 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1631 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1632 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1635 let Predicates = [UseAVX] in {
1636 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1637 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1638 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1639 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1640 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1641 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1643 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1644 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1645 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1646 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1647 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1648 SSE_CVT_Scalar, 0>, XD,
1651 let Constraints = "$src1 = $dst" in {
1652 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1653 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1654 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1655 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1656 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1657 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1658 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1659 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1660 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1661 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1662 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1663 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1668 // Aliases for intrinsics
1669 let Predicates = [UseAVX] in {
1670 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1671 ssmem, sse_load_f32, "cvttss2si",
1672 SSE_CVT_SS2SI_32>, XS, VEX;
1673 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1674 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1675 "cvttss2si", SSE_CVT_SS2SI_64>,
1677 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1678 sdmem, sse_load_f64, "cvttsd2si",
1679 SSE_CVT_SD2SI>, XD, VEX;
1680 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1681 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1682 "cvttsd2si", SSE_CVT_SD2SI>,
1685 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1686 ssmem, sse_load_f32, "cvttss2si",
1687 SSE_CVT_SS2SI_32>, XS;
1688 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1689 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1690 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1691 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1692 sdmem, sse_load_f64, "cvttsd2si",
1694 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1695 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1696 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1698 let Predicates = [UseAVX] in {
1699 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1700 ssmem, sse_load_f32, "cvtss2si",
1701 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1702 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1703 ssmem, sse_load_f32, "cvtss2si",
1704 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1706 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1707 ssmem, sse_load_f32, "cvtss2si",
1708 SSE_CVT_SS2SI_32>, XS;
1709 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1710 ssmem, sse_load_f32, "cvtss2si",
1711 SSE_CVT_SS2SI_64>, XS, REX_W;
1713 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1714 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1715 SSEPackedSingle, SSE_CVT_PS>,
1716 TB, VEX, Requires<[HasAVX]>;
1717 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1718 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1719 SSEPackedSingle, SSE_CVT_PS>,
1720 TB, VEX, VEX_L, Requires<[HasAVX]>;
1722 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1723 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1724 SSEPackedSingle, SSE_CVT_PS>,
1725 TB, Requires<[UseSSE2]>;
1727 let Predicates = [UseAVX] in {
1728 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1729 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1730 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1731 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1732 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1733 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1734 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1735 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1736 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1737 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1738 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1739 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1740 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1741 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1742 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1743 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1746 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1747 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1748 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1749 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1750 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1751 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1752 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1753 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1754 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1755 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1756 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1757 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1758 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1759 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1760 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1761 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1765 // Convert scalar double to scalar single
1766 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1767 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1768 (ins FR64:$src1, FR64:$src2),
1769 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1770 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1771 Sched<[WriteCvtF2F]>;
1773 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1774 (ins FR64:$src1, f64mem:$src2),
1775 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1776 [], IIC_SSE_CVT_Scalar_RM>,
1777 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1778 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1781 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1784 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1785 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1786 [(set FR32:$dst, (fround FR64:$src))],
1787 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1788 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1789 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1790 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1791 IIC_SSE_CVT_Scalar_RM>,
1793 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1795 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1796 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1797 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1799 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1800 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1801 Sched<[WriteCvtF2F]>;
1802 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1803 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1804 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1805 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1806 VR128:$src1, sse_load_f64:$src2))],
1807 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1808 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1810 let Constraints = "$src1 = $dst" in {
1811 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1812 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1813 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1815 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1816 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1817 Sched<[WriteCvtF2F]>;
1818 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1819 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1820 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1821 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1822 VR128:$src1, sse_load_f64:$src2))],
1823 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1824 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1827 // Convert scalar single to scalar double
1828 // SSE2 instructions with XS prefix
1829 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1830 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1831 (ins FR32:$src1, FR32:$src2),
1832 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1833 [], IIC_SSE_CVT_Scalar_RR>,
1834 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1835 Sched<[WriteCvtF2F]>;
1837 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1838 (ins FR32:$src1, f32mem:$src2),
1839 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1840 [], IIC_SSE_CVT_Scalar_RM>,
1841 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1842 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1845 def : Pat<(f64 (fextend FR32:$src)),
1846 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1847 def : Pat<(fextend (loadf32 addr:$src)),
1848 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1850 def : Pat<(extloadf32 addr:$src),
1851 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1852 Requires<[UseAVX, OptForSize]>;
1853 def : Pat<(extloadf32 addr:$src),
1854 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1855 Requires<[UseAVX, OptForSpeed]>;
1857 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1858 "cvtss2sd\t{$src, $dst|$dst, $src}",
1859 [(set FR64:$dst, (fextend FR32:$src))],
1860 IIC_SSE_CVT_Scalar_RR>, XS,
1861 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1862 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1863 "cvtss2sd\t{$src, $dst|$dst, $src}",
1864 [(set FR64:$dst, (extloadf32 addr:$src))],
1865 IIC_SSE_CVT_Scalar_RM>, XS,
1866 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1868 // extload f32 -> f64. This matches load+fextend because we have a hack in
1869 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1871 // Since these loads aren't folded into the fextend, we have to match it
1873 def : Pat<(fextend (loadf32 addr:$src)),
1874 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1875 def : Pat<(extloadf32 addr:$src),
1876 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1878 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1879 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1880 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1882 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1883 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1884 Sched<[WriteCvtF2F]>;
1885 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1886 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1889 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1890 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1891 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1892 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1893 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1894 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1895 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1897 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1898 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1899 Sched<[WriteCvtF2F]>;
1900 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1901 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1902 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1904 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1905 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1906 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1909 // Convert packed single/double fp to doubleword
1910 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvtps2dq\t{$src, $dst|$dst, $src}",
1912 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1913 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1914 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1915 "cvtps2dq\t{$src, $dst|$dst, $src}",
1917 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1918 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1919 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1920 "cvtps2dq\t{$src, $dst|$dst, $src}",
1922 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1923 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1924 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1925 "cvtps2dq\t{$src, $dst|$dst, $src}",
1927 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1928 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1929 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1930 "cvtps2dq\t{$src, $dst|$dst, $src}",
1931 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1932 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1933 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1934 "cvtps2dq\t{$src, $dst|$dst, $src}",
1936 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1937 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1940 // Convert Packed Double FP to Packed DW Integers
1941 let Predicates = [HasAVX] in {
1942 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1943 // register, but the same isn't true when using memory operands instead.
1944 // Provide other assembly rr and rm forms to address this explicitly.
1945 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1946 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1947 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1948 VEX, Sched<[WriteCvtF2I]>;
1951 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1952 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1953 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1954 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1956 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
1957 Sched<[WriteCvtF2ILd]>;
1960 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1961 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1963 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
1964 Sched<[WriteCvtF2I]>;
1965 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1966 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1968 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
1969 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1970 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1971 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1974 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1975 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1977 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1978 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
1979 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1980 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1981 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1982 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
1984 // Convert with truncation packed single/double fp to doubleword
1985 // SSE2 packed instructions with XS prefix
1986 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvttps2dq\t{$src, $dst|$dst, $src}",
1989 (int_x86_sse2_cvttps2dq VR128:$src))],
1990 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1991 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1992 "cvttps2dq\t{$src, $dst|$dst, $src}",
1993 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1994 (loadv4f32 addr:$src)))],
1995 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1996 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1997 "cvttps2dq\t{$src, $dst|$dst, $src}",
1999 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2000 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2001 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2002 "cvttps2dq\t{$src, $dst|$dst, $src}",
2003 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2004 (loadv8f32 addr:$src)))],
2005 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2006 Sched<[WriteCvtF2ILd]>;
2008 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2009 "cvttps2dq\t{$src, $dst|$dst, $src}",
2010 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2011 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2012 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2013 "cvttps2dq\t{$src, $dst|$dst, $src}",
2015 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2016 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2018 let Predicates = [HasAVX] in {
2019 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2020 (VCVTDQ2PSrr VR128:$src)>;
2021 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2022 (VCVTDQ2PSrm addr:$src)>;
2024 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2025 (VCVTDQ2PSrr VR128:$src)>;
2026 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2027 (VCVTDQ2PSrm addr:$src)>;
2029 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2030 (VCVTTPS2DQrr VR128:$src)>;
2031 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2032 (VCVTTPS2DQrm addr:$src)>;
2034 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2035 (VCVTDQ2PSYrr VR256:$src)>;
2036 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2037 (VCVTDQ2PSYrm addr:$src)>;
2039 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2040 (VCVTTPS2DQYrr VR256:$src)>;
2041 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2042 (VCVTTPS2DQYrm addr:$src)>;
2045 let Predicates = [UseSSE2] in {
2046 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2047 (CVTDQ2PSrr VR128:$src)>;
2048 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2049 (CVTDQ2PSrm addr:$src)>;
2051 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2052 (CVTDQ2PSrr VR128:$src)>;
2053 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2054 (CVTDQ2PSrm addr:$src)>;
2056 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2057 (CVTTPS2DQrr VR128:$src)>;
2058 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2059 (CVTTPS2DQrm addr:$src)>;
2062 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2063 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2065 (int_x86_sse2_cvttpd2dq VR128:$src))],
2066 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2068 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2069 // register, but the same isn't true when using memory operands instead.
2070 // Provide other assembly rr and rm forms to address this explicitly.
2073 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2074 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
2075 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2076 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2077 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2078 (loadv2f64 addr:$src)))],
2079 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2082 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2083 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2085 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2086 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2087 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2088 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2090 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2091 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2092 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2093 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2095 let Predicates = [HasAVX] in {
2096 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2097 (VCVTTPD2DQYrr VR256:$src)>;
2098 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2099 (VCVTTPD2DQYrm addr:$src)>;
2100 } // Predicates = [HasAVX]
2102 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2103 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2104 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2105 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2106 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2107 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2108 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2109 (memopv2f64 addr:$src)))],
2111 Sched<[WriteCvtF2ILd]>;
2113 // Convert packed single to packed double
2114 let Predicates = [HasAVX] in {
2115 // SSE2 instructions without OpSize prefix
2116 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2117 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2118 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2119 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2120 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2121 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2122 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2123 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2124 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2125 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2127 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2128 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2129 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2130 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2132 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2133 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2136 let Predicates = [UseSSE2] in {
2137 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2138 "cvtps2pd\t{$src, $dst|$dst, $src}",
2139 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2140 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2141 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2142 "cvtps2pd\t{$src, $dst|$dst, $src}",
2143 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2144 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2147 // Convert Packed DW Integers to Packed Double FP
2148 let Predicates = [HasAVX] in {
2149 let neverHasSideEffects = 1, mayLoad = 1 in
2150 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2151 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2152 []>, VEX, Sched<[WriteCvtI2FLd]>;
2153 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2154 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2156 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2157 Sched<[WriteCvtI2F]>;
2158 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2159 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2161 (int_x86_avx_cvtdq2_pd_256
2162 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2163 Sched<[WriteCvtI2FLd]>;
2164 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2165 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2167 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2168 Sched<[WriteCvtI2F]>;
2171 let neverHasSideEffects = 1, mayLoad = 1 in
2172 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2173 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2174 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2175 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2180 // AVX 256-bit register conversion intrinsics
2181 let Predicates = [HasAVX] in {
2182 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2183 (VCVTDQ2PDYrr VR128:$src)>;
2184 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2185 (VCVTDQ2PDYrm addr:$src)>;
2186 } // Predicates = [HasAVX]
2188 // Convert packed double to packed single
2189 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2190 // register, but the same isn't true when using memory operands instead.
2191 // Provide other assembly rr and rm forms to address this explicitly.
2192 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2193 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2194 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2195 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2198 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2199 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2200 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2201 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2203 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2204 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2207 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2208 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2210 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2211 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2212 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2213 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2215 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2216 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2217 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2218 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2220 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2221 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2222 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2223 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2224 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2225 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2227 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2228 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2231 // AVX 256-bit register conversion intrinsics
2232 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2233 // whenever possible to avoid declaring two versions of each one.
2234 let Predicates = [HasAVX] in {
2235 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2236 (VCVTDQ2PSYrr VR256:$src)>;
2237 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2238 (VCVTDQ2PSYrm addr:$src)>;
2240 // Match fround and fextend for 128/256-bit conversions
2241 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2242 (VCVTPD2PSrr VR128:$src)>;
2243 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2244 (VCVTPD2PSXrm addr:$src)>;
2245 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2246 (VCVTPD2PSYrr VR256:$src)>;
2247 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2248 (VCVTPD2PSYrm addr:$src)>;
2250 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2251 (VCVTPS2PDrr VR128:$src)>;
2252 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2253 (VCVTPS2PDYrr VR128:$src)>;
2254 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2255 (VCVTPS2PDYrm addr:$src)>;
2258 let Predicates = [UseSSE2] in {
2259 // Match fround and fextend for 128 conversions
2260 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2261 (CVTPD2PSrr VR128:$src)>;
2262 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2263 (CVTPD2PSrm addr:$src)>;
2265 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2266 (CVTPS2PDrr VR128:$src)>;
2269 //===----------------------------------------------------------------------===//
2270 // SSE 1 & 2 - Compare Instructions
2271 //===----------------------------------------------------------------------===//
2273 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2274 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2275 Operand CC, SDNode OpNode, ValueType VT,
2276 PatFrag ld_frag, string asm, string asm_alt,
2278 def rr : SIi8<0xC2, MRMSrcReg,
2279 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2280 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2281 itins.rr>, Sched<[itins.Sched]>;
2282 def rm : SIi8<0xC2, MRMSrcMem,
2283 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2284 [(set RC:$dst, (OpNode (VT RC:$src1),
2285 (ld_frag addr:$src2), imm:$cc))],
2287 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2289 // Accept explicit immediate argument form instead of comparison code.
2290 let neverHasSideEffects = 1 in {
2291 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2292 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2293 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2295 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2296 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2297 IIC_SSE_ALU_F32S_RM>,
2298 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2302 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2303 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2304 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2306 XS, VEX_4V, VEX_LIG;
2307 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2308 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2309 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2310 SSE_ALU_F32S>, // same latency as 32 bit compare
2311 XD, VEX_4V, VEX_LIG;
2313 let Constraints = "$src1 = $dst" in {
2314 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2315 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2316 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2318 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2319 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2320 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2325 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2326 Intrinsic Int, string asm, OpndItins itins> {
2327 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2328 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2329 [(set VR128:$dst, (Int VR128:$src1,
2330 VR128:$src, imm:$cc))],
2332 Sched<[itins.Sched]>;
2333 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2334 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2335 [(set VR128:$dst, (Int VR128:$src1,
2336 (load addr:$src), imm:$cc))],
2338 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2341 // Aliases to match intrinsics which expect XMM operand(s).
2342 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2343 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2346 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2347 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2348 SSE_ALU_F32S>, // same latency as f32
2350 let Constraints = "$src1 = $dst" in {
2351 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2352 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2354 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2355 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2361 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2362 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2363 ValueType vt, X86MemOperand x86memop,
2364 PatFrag ld_frag, string OpcodeStr> {
2365 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2366 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2367 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2370 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2371 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2372 [(set EFLAGS, (OpNode (vt RC:$src1),
2373 (ld_frag addr:$src2)))],
2375 Sched<[WriteFAddLd, ReadAfterLd]>;
2378 let Defs = [EFLAGS] in {
2379 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2380 "ucomiss">, TB, VEX, VEX_LIG;
2381 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2382 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2383 let Pattern = []<dag> in {
2384 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2385 "comiss">, TB, VEX, VEX_LIG;
2386 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2387 "comisd">, TB, OpSize, VEX, VEX_LIG;
2390 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2391 load, "ucomiss">, TB, VEX;
2392 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2393 load, "ucomisd">, TB, OpSize, VEX;
2395 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2396 load, "comiss">, TB, VEX;
2397 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2398 load, "comisd">, TB, OpSize, VEX;
2399 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2401 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2402 "ucomisd">, TB, OpSize;
2404 let Pattern = []<dag> in {
2405 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2407 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2408 "comisd">, TB, OpSize;
2411 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2412 load, "ucomiss">, TB;
2413 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2414 load, "ucomisd">, TB, OpSize;
2416 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2418 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2419 "comisd">, TB, OpSize;
2420 } // Defs = [EFLAGS]
2422 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2423 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2424 Operand CC, Intrinsic Int, string asm,
2425 string asm_alt, Domain d,
2426 OpndItins itins = SSE_ALU_F32P> {
2427 def rri : PIi8<0xC2, MRMSrcReg,
2428 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2429 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2432 def rmi : PIi8<0xC2, MRMSrcMem,
2433 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2434 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2436 Sched<[WriteFAddLd, ReadAfterLd]>;
2438 // Accept explicit immediate argument form instead of comparison code.
2439 let neverHasSideEffects = 1 in {
2440 def rri_alt : PIi8<0xC2, MRMSrcReg,
2441 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2442 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2443 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2444 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2445 asm_alt, [], itins.rm, d>,
2446 Sched<[WriteFAddLd, ReadAfterLd]>;
2450 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2451 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2452 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2453 SSEPackedSingle>, TB, VEX_4V;
2454 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2455 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2456 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2457 SSEPackedDouble>, TB, OpSize, VEX_4V;
2458 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2459 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2460 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2461 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2462 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2463 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2464 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2465 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2466 let Constraints = "$src1 = $dst" in {
2467 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2468 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2469 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2470 SSEPackedSingle, SSE_ALU_F32P>, TB;
2471 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2472 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2473 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2474 SSEPackedDouble, SSE_ALU_F64P>, TB, OpSize;
2477 let Predicates = [HasAVX] in {
2478 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2479 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2480 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2481 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2482 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2483 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2484 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2485 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2487 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2488 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2489 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2490 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2491 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2492 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2493 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2494 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2497 let Predicates = [UseSSE1] in {
2498 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2499 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2500 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2501 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2504 let Predicates = [UseSSE2] in {
2505 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2506 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2507 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2508 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2511 //===----------------------------------------------------------------------===//
2512 // SSE 1 & 2 - Shuffle Instructions
2513 //===----------------------------------------------------------------------===//
2515 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2516 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2517 ValueType vt, string asm, PatFrag mem_frag,
2518 Domain d, bit IsConvertibleToThreeAddress = 0> {
2519 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2520 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2521 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2522 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2523 Sched<[WriteShuffleLd, ReadAfterLd]>;
2524 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2525 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2526 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2527 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2528 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2529 Sched<[WriteShuffle]>;
2532 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2533 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2534 loadv4f32, SSEPackedSingle>, TB, VEX_4V;
2535 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2536 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2537 loadv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2538 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2539 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2540 loadv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2541 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2542 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2543 loadv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2545 let Constraints = "$src1 = $dst" in {
2546 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2547 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2548 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2550 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2551 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2552 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2556 let Predicates = [HasAVX] in {
2557 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2558 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2559 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2560 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2561 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2563 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2564 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2565 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2566 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2567 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2570 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2571 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2572 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2573 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2574 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2576 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2577 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2578 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2579 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2580 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2583 let Predicates = [UseSSE1] in {
2584 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2585 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2586 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2587 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2588 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2591 let Predicates = [UseSSE2] in {
2592 // Generic SHUFPD patterns
2593 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2594 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2595 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2596 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2597 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2600 //===----------------------------------------------------------------------===//
2601 // SSE 1 & 2 - Unpack Instructions
2602 //===----------------------------------------------------------------------===//
2604 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2605 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2606 PatFrag mem_frag, RegisterClass RC,
2607 X86MemOperand x86memop, string asm,
2609 def rr : PI<opc, MRMSrcReg,
2610 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2612 (vt (OpNode RC:$src1, RC:$src2)))],
2613 IIC_SSE_UNPCK, d>, Sched<[WriteShuffle]>;
2614 def rm : PI<opc, MRMSrcMem,
2615 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2617 (vt (OpNode RC:$src1,
2618 (mem_frag addr:$src2))))],
2620 Sched<[WriteShuffleLd, ReadAfterLd]>;
2623 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2624 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2625 SSEPackedSingle>, TB, VEX_4V;
2626 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2627 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2628 SSEPackedDouble>, TB, OpSize, VEX_4V;
2629 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2630 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2631 SSEPackedSingle>, TB, VEX_4V;
2632 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2633 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2634 SSEPackedDouble>, TB, OpSize, VEX_4V;
2636 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2637 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2638 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2639 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2640 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2641 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2642 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2643 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2644 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2645 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2646 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2647 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2649 let Constraints = "$src1 = $dst" in {
2650 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2651 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2652 SSEPackedSingle>, TB;
2653 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2654 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2655 SSEPackedDouble>, TB, OpSize;
2656 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2657 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2658 SSEPackedSingle>, TB;
2659 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2660 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2661 SSEPackedDouble>, TB, OpSize;
2662 } // Constraints = "$src1 = $dst"
2664 let Predicates = [HasAVX1Only] in {
2665 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2666 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2667 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2668 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2669 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2670 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2671 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2672 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2674 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2675 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2676 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2677 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2678 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2679 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2680 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2681 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2684 let Predicates = [HasAVX] in {
2685 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2686 // problem is during lowering, where it's not possible to recognize the load
2687 // fold cause it has two uses through a bitcast. One use disappears at isel
2688 // time and the fold opportunity reappears.
2689 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2690 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2693 let Predicates = [UseSSE2] in {
2694 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2695 // problem is during lowering, where it's not possible to recognize the load
2696 // fold cause it has two uses through a bitcast. One use disappears at isel
2697 // time and the fold opportunity reappears.
2698 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2699 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2702 //===----------------------------------------------------------------------===//
2703 // SSE 1 & 2 - Extract Floating-Point Sign mask
2704 //===----------------------------------------------------------------------===//
2706 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2707 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2709 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2710 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2711 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2712 Sched<[WriteVecLogic]>;
2715 let Predicates = [HasAVX] in {
2716 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2717 "movmskps", SSEPackedSingle>, TB, VEX;
2718 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2719 "movmskpd", SSEPackedDouble>, TB,
2721 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2722 "movmskps", SSEPackedSingle>, TB,
2724 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2725 "movmskpd", SSEPackedDouble>, TB,
2728 def : Pat<(i32 (X86fgetsign FR32:$src)),
2729 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2730 def : Pat<(i64 (X86fgetsign FR32:$src)),
2731 (SUBREG_TO_REG (i64 0),
2732 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2733 def : Pat<(i32 (X86fgetsign FR64:$src)),
2734 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2735 def : Pat<(i64 (X86fgetsign FR64:$src)),
2736 (SUBREG_TO_REG (i64 0),
2737 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2740 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2741 SSEPackedSingle>, TB;
2742 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2743 SSEPackedDouble>, TB, OpSize;
2745 def : Pat<(i32 (X86fgetsign FR32:$src)),
2746 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2747 Requires<[UseSSE1]>;
2748 def : Pat<(i64 (X86fgetsign FR32:$src)),
2749 (SUBREG_TO_REG (i64 0),
2750 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2751 Requires<[UseSSE1]>;
2752 def : Pat<(i32 (X86fgetsign FR64:$src)),
2753 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2754 Requires<[UseSSE2]>;
2755 def : Pat<(i64 (X86fgetsign FR64:$src)),
2756 (SUBREG_TO_REG (i64 0),
2757 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2758 Requires<[UseSSE2]>;
2760 //===---------------------------------------------------------------------===//
2761 // SSE2 - Packed Integer Logical Instructions
2762 //===---------------------------------------------------------------------===//
2764 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2766 /// PDI_binop_rm - Simple SSE2 binary operator.
2767 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2768 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2769 X86MemOperand x86memop, OpndItins itins,
2770 bit IsCommutable, bit Is2Addr> {
2771 let isCommutable = IsCommutable in
2772 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2773 (ins RC:$src1, RC:$src2),
2775 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2776 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2777 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2778 Sched<[itins.Sched]>;
2779 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2780 (ins RC:$src1, x86memop:$src2),
2782 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2783 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2784 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2785 (bitconvert (memop_frag addr:$src2)))))],
2787 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2789 } // ExeDomain = SSEPackedInt
2791 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2792 ValueType OpVT128, ValueType OpVT256,
2793 OpndItins itins, bit IsCommutable = 0> {
2794 let Predicates = [HasAVX] in
2795 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2796 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2798 let Constraints = "$src1 = $dst" in
2799 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2800 memopv2i64, i128mem, itins, IsCommutable, 1>;
2802 let Predicates = [HasAVX2] in
2803 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2804 OpVT256, VR256, loadv4i64, i256mem, itins,
2805 IsCommutable, 0>, VEX_4V, VEX_L;
2808 // These are ordered here for pattern ordering requirements with the fp versions
2810 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2811 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2812 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2813 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2814 SSE_BIT_ITINS_P, 0>;
2816 //===----------------------------------------------------------------------===//
2817 // SSE 1 & 2 - Logical Instructions
2818 //===----------------------------------------------------------------------===//
2820 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2822 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2823 SDNode OpNode, OpndItins itins> {
2824 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2825 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2828 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2829 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2832 let Constraints = "$src1 = $dst" in {
2833 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2834 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2837 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2838 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2843 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2844 let isCodeGenOnly = 1 in {
2845 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2847 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2849 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2852 let isCommutable = 0 in
2853 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2857 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2859 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2861 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2862 !strconcat(OpcodeStr, "ps"), f256mem,
2863 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2864 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2865 (loadv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2867 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2868 !strconcat(OpcodeStr, "pd"), f256mem,
2869 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2870 (bc_v4i64 (v4f64 VR256:$src2))))],
2871 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2872 (loadv4i64 addr:$src2)))], 0>,
2873 TB, OpSize, VEX_4V, VEX_L;
2875 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2876 // are all promoted to v2i64, and the patterns are covered by the int
2877 // version. This is needed in SSE only, because v2i64 isn't supported on
2878 // SSE1, but only on SSE2.
2879 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2880 !strconcat(OpcodeStr, "ps"), f128mem, [],
2881 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2882 (loadv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2884 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2885 !strconcat(OpcodeStr, "pd"), f128mem,
2886 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2887 (bc_v2i64 (v2f64 VR128:$src2))))],
2888 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2889 (loadv2i64 addr:$src2)))], 0>,
2892 let Constraints = "$src1 = $dst" in {
2893 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2894 !strconcat(OpcodeStr, "ps"), f128mem,
2895 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2896 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2897 (memopv2i64 addr:$src2)))]>, TB;
2899 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2900 !strconcat(OpcodeStr, "pd"), f128mem,
2901 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2902 (bc_v2i64 (v2f64 VR128:$src2))))],
2903 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2904 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2908 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2909 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2910 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2911 let isCommutable = 0 in
2912 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2914 //===----------------------------------------------------------------------===//
2915 // SSE 1 & 2 - Arithmetic Instructions
2916 //===----------------------------------------------------------------------===//
2918 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2921 /// In addition, we also have a special variant of the scalar form here to
2922 /// represent the associated intrinsic operation. This form is unlike the
2923 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2924 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2926 /// These three forms can each be reg+reg or reg+mem.
2929 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2931 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2932 SDNode OpNode, SizeItins itins> {
2933 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2934 VR128, v4f32, f128mem, loadv4f32,
2935 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2936 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2937 VR128, v2f64, f128mem, loadv2f64,
2938 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2940 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2941 OpNode, VR256, v8f32, f256mem, loadv8f32,
2942 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2943 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2944 OpNode, VR256, v4f64, f256mem, loadv4f64,
2945 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2947 let Constraints = "$src1 = $dst" in {
2948 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2949 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2951 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2952 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2953 itins.d>, TB, OpSize;
2957 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2959 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2960 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
2961 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2962 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
2964 let Constraints = "$src1 = $dst" in {
2965 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2966 OpNode, FR32, f32mem, itins.s>, XS;
2967 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2968 OpNode, FR64, f64mem, itins.d>, XD;
2972 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2974 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2975 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2976 itins.s, 0>, XS, VEX_4V, VEX_LIG;
2977 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2978 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2979 itins.d, 0>, XD, VEX_4V, VEX_LIG;
2981 let Constraints = "$src1 = $dst" in {
2982 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2983 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2985 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2986 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2991 // Binary Arithmetic instructions
2992 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2993 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2994 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2995 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2996 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2997 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2998 let isCommutable = 0 in {
2999 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3000 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3001 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3002 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3003 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3004 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3005 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3006 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3007 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3008 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3009 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3010 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3013 let isCodeGenOnly = 1 in {
3014 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3015 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3016 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3017 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3020 // Patterns used to select SSE scalar fp arithmetic instructions from
3021 // a scalar fp operation followed by a blend.
3023 // These patterns know, for example, how to select an ADDSS from a
3024 // float add plus vector insert.
3026 // The effect is that the backend no longer emits unnecessary vector
3027 // insert instructions immediately after SSE scalar fp instructions
3028 // like addss or mulss.
3030 // For example, given the following code:
3031 // __m128 foo(__m128 A, __m128 B) {
3036 // previously we generated:
3037 // addss %xmm0, %xmm1
3038 // movss %xmm1, %xmm0
3041 // addss %xmm1, %xmm0
3043 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3044 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3046 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3047 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3048 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3050 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3051 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3052 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3054 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3055 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3056 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3058 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3060 let Predicates = [HasSSE2] in {
3061 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3063 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3064 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3066 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3067 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3068 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3070 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3071 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3072 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3074 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3075 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3076 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3078 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3081 let Predicates = [UseSSE41] in {
3082 // If the subtarget has SSE4.1 but not AVX, the vector insert
3083 // instruction is lowered into a X86insrtps rather than a X86Movss.
3084 // When selecting SSE scalar single-precision fp arithmetic instructions,
3085 // make sure that we correctly match the X86insrtps.
3087 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3088 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3089 FR32:$src))), (iPTR 0))),
3090 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3091 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3092 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3093 FR32:$src))), (iPTR 0))),
3094 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3095 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3096 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3097 FR32:$src))), (iPTR 0))),
3098 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3099 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3100 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3101 FR32:$src))), (iPTR 0))),
3102 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3105 let AddedComplexity = 20, Predicates = [HasAVX] in {
3106 // The following patterns select AVX Scalar single/double precision fp
3107 // arithmetic instructions.
3108 // The 'AddedComplexity' is required to give them higher priority over
3109 // the equivalent SSE/SSE2 patterns.
3111 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3112 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3114 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3115 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3116 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3118 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3119 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3120 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3122 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3123 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3124 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3126 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3127 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3128 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3129 FR32:$src))), (iPTR 0))),
3130 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3131 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3132 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3133 FR32:$src))), (iPTR 0))),
3134 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3135 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3136 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3137 FR32:$src))), (iPTR 0))),
3138 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3139 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3140 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3141 FR32:$src))), (iPTR 0))),
3142 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3145 // Patterns used to select SSE scalar fp arithmetic instructions from
3146 // a vector packed single/double fp operation followed by a vector insert.
3148 // The effect is that the backend converts the packed fp instruction
3149 // followed by a vector insert into a single SSE scalar fp instruction.
3151 // For example, given the following code:
3152 // __m128 foo(__m128 A, __m128 B) {
3153 // __m128 C = A + B;
3154 // return (__m128) {c[0], a[1], a[2], a[3]};
3157 // previously we generated:
3158 // addps %xmm0, %xmm1
3159 // movss %xmm1, %xmm0
3162 // addss %xmm1, %xmm0
3164 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3165 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3166 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3167 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3168 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3169 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3170 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3171 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3172 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3173 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3174 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3175 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3177 let Predicates = [HasSSE2] in {
3178 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3179 // from a packed double-precision fp instruction plus movsd.
3181 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3182 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3183 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3184 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3185 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3186 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3187 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3188 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3189 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3190 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3191 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3192 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3195 let AddedComplexity = 20, Predicates = [HasAVX] in {
3196 // The following patterns select AVX Scalar single/double precision fp
3197 // arithmetic instructions from a packed single precision fp instruction
3198 // plus movss/movsd.
3199 // The 'AddedComplexity' is required to give them higher priority over
3200 // the equivalent SSE/SSE2 patterns.
3202 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3203 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3204 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3205 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3206 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3207 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3208 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3209 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3210 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3211 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3212 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3213 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3214 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3215 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3216 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3217 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3218 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3219 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3220 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3221 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3222 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3223 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3224 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3225 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3229 /// In addition, we also have a special variant of the scalar form here to
3230 /// represent the associated intrinsic operation. This form is unlike the
3231 /// plain scalar form, in that it takes an entire vector (instead of a
3232 /// scalar) and leaves the top elements undefined.
3234 /// And, we have a special variant form for a full-vector intrinsic form.
3236 let Sched = WriteFSqrt in {
3237 def SSE_SQRTPS : OpndItins<
3238 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3241 def SSE_SQRTSS : OpndItins<
3242 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3245 def SSE_SQRTPD : OpndItins<
3246 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3249 def SSE_SQRTSD : OpndItins<
3250 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3254 let Sched = WriteFRcp in {
3255 def SSE_RCPP : OpndItins<
3256 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3259 def SSE_RCPS : OpndItins<
3260 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3264 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3265 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3266 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3267 let Predicates = [HasAVX], hasSideEffects = 0 in {
3268 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3269 (ins FR32:$src1, FR32:$src2),
3270 !strconcat("v", OpcodeStr,
3271 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3272 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3273 let mayLoad = 1 in {
3274 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3275 (ins FR32:$src1,f32mem:$src2),
3276 !strconcat("v", OpcodeStr,
3277 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3278 []>, VEX_4V, VEX_LIG,
3279 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3280 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3281 (ins VR128:$src1, ssmem:$src2),
3282 !strconcat("v", OpcodeStr,
3283 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3284 []>, VEX_4V, VEX_LIG,
3285 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3289 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3290 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3291 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3292 // For scalar unary operations, fold a load into the operation
3293 // only in OptForSize mode. It eliminates an instruction, but it also
3294 // eliminates a whole-register clobber (the load), so it introduces a
3295 // partial register update condition.
3296 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3297 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3298 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3299 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3300 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3301 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3302 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3303 Sched<[itins.Sched]>;
3304 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3305 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3306 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3307 Sched<[itins.Sched.Folded]>;
3310 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3311 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3313 let Predicates = [HasAVX], hasSideEffects = 0 in {
3314 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3315 (ins FR32:$src1, FR32:$src2),
3316 !strconcat("v", OpcodeStr,
3317 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3318 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3319 let mayLoad = 1 in {
3320 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3321 (ins FR32:$src1,f32mem:$src2),
3322 !strconcat("v", OpcodeStr,
3323 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3324 []>, VEX_4V, VEX_LIG,
3325 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3326 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3327 (ins VR128:$src1, ssmem:$src2),
3328 !strconcat("v", OpcodeStr,
3329 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3330 []>, VEX_4V, VEX_LIG,
3331 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3335 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3336 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3337 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3338 // For scalar unary operations, fold a load into the operation
3339 // only in OptForSize mode. It eliminates an instruction, but it also
3340 // eliminates a whole-register clobber (the load), so it introduces a
3341 // partial register update condition.
3342 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3343 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3344 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3345 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3346 let Constraints = "$src1 = $dst" in {
3347 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3348 (ins VR128:$src1, VR128:$src2),
3349 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3350 [], itins.rr>, Sched<[itins.Sched]>;
3351 let mayLoad = 1, hasSideEffects = 0 in
3352 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3353 (ins VR128:$src1, ssmem:$src2),
3354 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3355 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3359 /// sse1_fp_unop_p - SSE1 unops in packed form.
3360 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3362 let Predicates = [HasAVX] in {
3363 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3364 !strconcat("v", OpcodeStr,
3365 "ps\t{$src, $dst|$dst, $src}"),
3366 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3367 itins.rr>, VEX, Sched<[itins.Sched]>;
3368 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3369 !strconcat("v", OpcodeStr,
3370 "ps\t{$src, $dst|$dst, $src}"),
3371 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3372 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3373 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3374 !strconcat("v", OpcodeStr,
3375 "ps\t{$src, $dst|$dst, $src}"),
3376 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3377 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3378 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3379 !strconcat("v", OpcodeStr,
3380 "ps\t{$src, $dst|$dst, $src}"),
3381 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3382 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3385 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3386 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3387 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3388 Sched<[itins.Sched]>;
3389 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3390 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3391 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3392 Sched<[itins.Sched.Folded]>;
3395 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3396 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3397 Intrinsic V4F32Int, Intrinsic V8F32Int,
3399 let Predicates = [HasAVX] in {
3400 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3401 !strconcat("v", OpcodeStr,
3402 "ps\t{$src, $dst|$dst, $src}"),
3403 [(set VR128:$dst, (V4F32Int VR128:$src))],
3404 itins.rr>, VEX, Sched<[itins.Sched]>;
3405 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3406 !strconcat("v", OpcodeStr,
3407 "ps\t{$src, $dst|$dst, $src}"),
3408 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3409 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3410 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3411 !strconcat("v", OpcodeStr,
3412 "ps\t{$src, $dst|$dst, $src}"),
3413 [(set VR256:$dst, (V8F32Int VR256:$src))],
3414 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3415 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3417 !strconcat("v", OpcodeStr,
3418 "ps\t{$src, $dst|$dst, $src}"),
3419 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3420 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3423 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3424 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3425 [(set VR128:$dst, (V4F32Int VR128:$src))],
3426 itins.rr>, Sched<[itins.Sched]>;
3427 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3428 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3429 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3430 itins.rm>, Sched<[itins.Sched.Folded]>;
3433 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3434 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3435 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3436 let Predicates = [HasAVX], hasSideEffects = 0 in {
3437 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3438 (ins FR64:$src1, FR64:$src2),
3439 !strconcat("v", OpcodeStr,
3440 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3441 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3442 let mayLoad = 1 in {
3443 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3444 (ins FR64:$src1,f64mem:$src2),
3445 !strconcat("v", OpcodeStr,
3446 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3447 []>, VEX_4V, VEX_LIG,
3448 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3449 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3450 (ins VR128:$src1, sdmem:$src2),
3451 !strconcat("v", OpcodeStr,
3452 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3453 []>, VEX_4V, VEX_LIG,
3454 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3458 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3459 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3460 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3461 Sched<[itins.Sched]>;
3462 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3463 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3464 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3465 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3466 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3467 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3468 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3469 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3470 Sched<[itins.Sched]>;
3471 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3472 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3473 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3474 Sched<[itins.Sched.Folded]>;
3477 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3478 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3479 SDNode OpNode, OpndItins itins> {
3480 let Predicates = [HasAVX] in {
3481 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3482 !strconcat("v", OpcodeStr,
3483 "pd\t{$src, $dst|$dst, $src}"),
3484 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3485 itins.rr>, VEX, Sched<[itins.Sched]>;
3486 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3487 !strconcat("v", OpcodeStr,
3488 "pd\t{$src, $dst|$dst, $src}"),
3489 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3490 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3491 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3492 !strconcat("v", OpcodeStr,
3493 "pd\t{$src, $dst|$dst, $src}"),
3494 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3495 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3496 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3497 !strconcat("v", OpcodeStr,
3498 "pd\t{$src, $dst|$dst, $src}"),
3499 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3500 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3503 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3504 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3505 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3506 Sched<[itins.Sched]>;
3507 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3508 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3509 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3510 Sched<[itins.Sched.Folded]>;
3514 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3516 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3517 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3519 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3521 // Reciprocal approximations. Note that these typically require refinement
3522 // in order to obtain suitable precision.
3523 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3524 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3525 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3526 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3527 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3528 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3529 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3530 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3532 let Predicates = [UseAVX] in {
3533 def : Pat<(f32 (fsqrt FR32:$src)),
3534 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3535 def : Pat<(f32 (fsqrt (load addr:$src))),
3536 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3537 Requires<[HasAVX, OptForSize]>;
3538 def : Pat<(f64 (fsqrt FR64:$src)),
3539 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3540 def : Pat<(f64 (fsqrt (load addr:$src))),
3541 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3542 Requires<[HasAVX, OptForSize]>;
3544 def : Pat<(f32 (X86frsqrt FR32:$src)),
3545 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3546 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3547 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3548 Requires<[HasAVX, OptForSize]>;
3550 def : Pat<(f32 (X86frcp FR32:$src)),
3551 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3552 def : Pat<(f32 (X86frcp (load addr:$src))),
3553 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3554 Requires<[HasAVX, OptForSize]>;
3556 let Predicates = [UseAVX] in {
3557 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3558 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3559 (COPY_TO_REGCLASS VR128:$src, FR32)),
3561 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3562 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3564 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3565 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3566 (COPY_TO_REGCLASS VR128:$src, FR64)),
3568 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3569 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3572 let Predicates = [HasAVX] in {
3573 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3574 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3575 (COPY_TO_REGCLASS VR128:$src, FR32)),
3577 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3578 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3580 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3581 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3582 (COPY_TO_REGCLASS VR128:$src, FR32)),
3584 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3585 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3588 // Reciprocal approximations. Note that these typically require refinement
3589 // in order to obtain suitable precision.
3590 let Predicates = [UseSSE1] in {
3591 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3592 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3593 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3594 (RCPSSr_Int VR128:$src, VR128:$src)>;
3597 // There is no f64 version of the reciprocal approximation instructions.
3599 //===----------------------------------------------------------------------===//
3600 // SSE 1 & 2 - Non-temporal stores
3601 //===----------------------------------------------------------------------===//
3603 let AddedComplexity = 400 in { // Prefer non-temporal versions
3604 let SchedRW = [WriteStore] in {
3605 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3606 (ins f128mem:$dst, VR128:$src),
3607 "movntps\t{$src, $dst|$dst, $src}",
3608 [(alignednontemporalstore (v4f32 VR128:$src),
3610 IIC_SSE_MOVNT>, VEX;
3611 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3612 (ins f128mem:$dst, VR128:$src),
3613 "movntpd\t{$src, $dst|$dst, $src}",
3614 [(alignednontemporalstore (v2f64 VR128:$src),
3616 IIC_SSE_MOVNT>, VEX;
3618 let ExeDomain = SSEPackedInt in
3619 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3620 (ins f128mem:$dst, VR128:$src),
3621 "movntdq\t{$src, $dst|$dst, $src}",
3622 [(alignednontemporalstore (v2i64 VR128:$src),
3624 IIC_SSE_MOVNT>, VEX;
3626 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3627 (ins f256mem:$dst, VR256:$src),
3628 "movntps\t{$src, $dst|$dst, $src}",
3629 [(alignednontemporalstore (v8f32 VR256:$src),
3631 IIC_SSE_MOVNT>, VEX, VEX_L;
3632 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3633 (ins f256mem:$dst, VR256:$src),
3634 "movntpd\t{$src, $dst|$dst, $src}",
3635 [(alignednontemporalstore (v4f64 VR256:$src),
3637 IIC_SSE_MOVNT>, VEX, VEX_L;
3638 let ExeDomain = SSEPackedInt in
3639 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3640 (ins f256mem:$dst, VR256:$src),
3641 "movntdq\t{$src, $dst|$dst, $src}",
3642 [(alignednontemporalstore (v4i64 VR256:$src),
3644 IIC_SSE_MOVNT>, VEX, VEX_L;
3646 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3647 "movntps\t{$src, $dst|$dst, $src}",
3648 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3650 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3651 "movntpd\t{$src, $dst|$dst, $src}",
3652 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3655 let ExeDomain = SSEPackedInt in
3656 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3657 "movntdq\t{$src, $dst|$dst, $src}",
3658 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3661 // There is no AVX form for instructions below this point
3662 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3663 "movnti{l}\t{$src, $dst|$dst, $src}",
3664 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3666 TB, Requires<[HasSSE2]>;
3667 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3668 "movnti{q}\t{$src, $dst|$dst, $src}",
3669 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3671 TB, Requires<[HasSSE2]>;
3672 } // SchedRW = [WriteStore]
3674 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3675 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3677 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3678 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3679 } // AddedComplexity
3681 //===----------------------------------------------------------------------===//
3682 // SSE 1 & 2 - Prefetch and memory fence
3683 //===----------------------------------------------------------------------===//
3685 // Prefetch intrinsic.
3686 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3687 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3688 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3689 IIC_SSE_PREFETCH>, TB;
3690 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3691 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3692 IIC_SSE_PREFETCH>, TB;
3693 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3694 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3695 IIC_SSE_PREFETCH>, TB;
3696 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3697 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3698 IIC_SSE_PREFETCH>, TB;
3701 // FIXME: How should these memory instructions be modeled?
3702 let SchedRW = [WriteLoad] in {
3704 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3705 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3706 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3708 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3709 // was introduced with SSE2, it's backward compatible.
3710 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3711 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3712 REP, Requires<[HasSSE2]>;
3714 // Load, store, and memory fence
3715 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3716 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3717 TB, Requires<[HasSSE1]>;
3718 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3719 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3720 TB, Requires<[HasSSE2]>;
3721 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3722 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3723 TB, Requires<[HasSSE2]>;
3726 def : Pat<(X86SFence), (SFENCE)>;
3727 def : Pat<(X86LFence), (LFENCE)>;
3728 def : Pat<(X86MFence), (MFENCE)>;
3730 //===----------------------------------------------------------------------===//
3731 // SSE 1 & 2 - Load/Store XCSR register
3732 //===----------------------------------------------------------------------===//
3734 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3735 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3736 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3737 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3738 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3739 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3741 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3742 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3743 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3744 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3745 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3746 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3748 //===---------------------------------------------------------------------===//
3749 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3750 //===---------------------------------------------------------------------===//
3752 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3754 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3755 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3756 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3758 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3759 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3761 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3762 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3764 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3765 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3770 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
3771 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3772 "movdqa\t{$src, $dst|$dst, $src}", [],
3775 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3776 "movdqa\t{$src, $dst|$dst, $src}", [],
3777 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3778 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3779 "movdqu\t{$src, $dst|$dst, $src}", [],
3782 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3783 "movdqu\t{$src, $dst|$dst, $src}", [],
3784 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3787 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3788 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3789 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3790 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3792 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3793 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3795 let Predicates = [HasAVX] in {
3796 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3797 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3799 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3800 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3805 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3806 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3807 (ins i128mem:$dst, VR128:$src),
3808 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3810 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3811 (ins i256mem:$dst, VR256:$src),
3812 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3814 let Predicates = [HasAVX] in {
3815 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3816 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3818 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3819 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3824 let SchedRW = [WriteMove] in {
3825 let neverHasSideEffects = 1 in
3826 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3827 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3829 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3830 "movdqu\t{$src, $dst|$dst, $src}",
3831 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3834 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3835 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3836 "movdqa\t{$src, $dst|$dst, $src}", [],
3839 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3840 "movdqu\t{$src, $dst|$dst, $src}",
3841 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3845 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3846 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3847 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3848 "movdqa\t{$src, $dst|$dst, $src}",
3849 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3851 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3852 "movdqu\t{$src, $dst|$dst, $src}",
3853 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3855 XS, Requires<[UseSSE2]>;
3858 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3859 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3860 "movdqa\t{$src, $dst|$dst, $src}",
3861 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3863 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3864 "movdqu\t{$src, $dst|$dst, $src}",
3865 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3867 XS, Requires<[UseSSE2]>;
3870 } // ExeDomain = SSEPackedInt
3872 let Predicates = [HasAVX] in {
3873 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3874 (VMOVDQUmr addr:$dst, VR128:$src)>;
3875 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3876 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3878 let Predicates = [UseSSE2] in
3879 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3880 (MOVDQUmr addr:$dst, VR128:$src)>;
3882 //===---------------------------------------------------------------------===//
3883 // SSE2 - Packed Integer Arithmetic Instructions
3884 //===---------------------------------------------------------------------===//
3886 let Sched = WriteVecIMul in
3887 def SSE_PMADD : OpndItins<
3888 IIC_SSE_PMADD, IIC_SSE_PMADD
3891 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3893 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3894 RegisterClass RC, PatFrag memop_frag,
3895 X86MemOperand x86memop,
3897 bit IsCommutable = 0,
3899 let isCommutable = IsCommutable in
3900 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3901 (ins RC:$src1, RC:$src2),
3903 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3904 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3905 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3906 Sched<[itins.Sched]>;
3907 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3908 (ins RC:$src1, x86memop:$src2),
3910 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3911 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3912 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3913 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3916 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3917 Intrinsic IntId256, OpndItins itins,
3918 bit IsCommutable = 0> {
3919 let Predicates = [HasAVX] in
3920 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3921 VR128, loadv2i64, i128mem, itins,
3922 IsCommutable, 0>, VEX_4V;
3924 let Constraints = "$src1 = $dst" in
3925 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3926 i128mem, itins, IsCommutable, 1>;
3928 let Predicates = [HasAVX2] in
3929 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3930 VR256, loadv4i64, i256mem, itins,
3931 IsCommutable, 0>, VEX_4V, VEX_L;
3934 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3935 string OpcodeStr, SDNode OpNode,
3936 SDNode OpNode2, RegisterClass RC,
3937 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3938 ShiftOpndItins itins,
3940 // src2 is always 128-bit
3941 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3942 (ins RC:$src1, VR128:$src2),
3944 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3945 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3946 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3947 itins.rr>, Sched<[WriteVecShift]>;
3948 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3949 (ins RC:$src1, i128mem:$src2),
3951 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3952 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3953 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3954 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
3955 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3956 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3957 (ins RC:$src1, i8imm:$src2),
3959 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3960 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3961 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3962 Sched<[WriteVecShift]>;
3965 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3966 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3967 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3968 PatFrag memop_frag, X86MemOperand x86memop,
3970 bit IsCommutable = 0, bit Is2Addr = 1> {
3971 let isCommutable = IsCommutable in
3972 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3973 (ins RC:$src1, RC:$src2),
3975 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3976 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3977 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3978 Sched<[itins.Sched]>;
3979 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3980 (ins RC:$src1, x86memop:$src2),
3982 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3983 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3984 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3985 (bitconvert (memop_frag addr:$src2)))))]>,
3986 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3988 } // ExeDomain = SSEPackedInt
3990 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3991 SSE_INTALU_ITINS_P, 1>;
3992 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3993 SSE_INTALU_ITINS_P, 1>;
3994 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3995 SSE_INTALU_ITINS_P, 1>;
3996 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3997 SSE_INTALUQ_ITINS_P, 1>;
3998 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3999 SSE_INTMUL_ITINS_P, 1>;
4000 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4001 SSE_INTALU_ITINS_P, 0>;
4002 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4003 SSE_INTALU_ITINS_P, 0>;
4004 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4005 SSE_INTALU_ITINS_P, 0>;
4006 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4007 SSE_INTALUQ_ITINS_P, 0>;
4008 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4009 SSE_INTALU_ITINS_P, 0>;
4010 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4011 SSE_INTALU_ITINS_P, 0>;
4012 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4013 SSE_INTALU_ITINS_P, 1>;
4014 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4015 SSE_INTALU_ITINS_P, 1>;
4016 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4017 SSE_INTALU_ITINS_P, 1>;
4018 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4019 SSE_INTALU_ITINS_P, 1>;
4022 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4023 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4024 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4025 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4026 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4027 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4028 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4029 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4030 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4031 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4032 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4033 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4034 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
4035 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
4036 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
4037 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
4038 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4039 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4040 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4041 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4042 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4043 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4044 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4045 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4047 let Predicates = [HasAVX] in
4048 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4049 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4051 let Predicates = [HasAVX2] in
4052 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4053 VR256, loadv4i64, i256mem,
4054 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4055 let Constraints = "$src1 = $dst" in
4056 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4057 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4059 //===---------------------------------------------------------------------===//
4060 // SSE2 - Packed Integer Logical Instructions
4061 //===---------------------------------------------------------------------===//
4063 let Predicates = [HasAVX] in {
4064 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4065 VR128, v8i16, v8i16, bc_v8i16,
4066 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4067 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4068 VR128, v4i32, v4i32, bc_v4i32,
4069 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4070 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4071 VR128, v2i64, v2i64, bc_v2i64,
4072 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4074 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4075 VR128, v8i16, v8i16, bc_v8i16,
4076 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4077 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4078 VR128, v4i32, v4i32, bc_v4i32,
4079 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4080 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4081 VR128, v2i64, v2i64, bc_v2i64,
4082 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4084 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4085 VR128, v8i16, v8i16, bc_v8i16,
4086 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4087 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4088 VR128, v4i32, v4i32, bc_v4i32,
4089 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4091 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4092 // 128-bit logical shifts.
4093 def VPSLLDQri : PDIi8<0x73, MRM7r,
4094 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4095 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4097 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4099 def VPSRLDQri : PDIi8<0x73, MRM3r,
4100 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4101 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4103 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4105 // PSRADQri doesn't exist in SSE[1-3].
4107 } // Predicates = [HasAVX]
4109 let Predicates = [HasAVX2] in {
4110 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4111 VR256, v16i16, v8i16, bc_v8i16,
4112 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4113 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4114 VR256, v8i32, v4i32, bc_v4i32,
4115 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4116 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4117 VR256, v4i64, v2i64, bc_v2i64,
4118 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4120 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4121 VR256, v16i16, v8i16, bc_v8i16,
4122 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4123 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4124 VR256, v8i32, v4i32, bc_v4i32,
4125 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4126 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4127 VR256, v4i64, v2i64, bc_v2i64,
4128 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4130 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4131 VR256, v16i16, v8i16, bc_v8i16,
4132 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4133 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4134 VR256, v8i32, v4i32, bc_v4i32,
4135 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4137 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4138 // 256-bit logical shifts.
4139 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4140 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4141 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4143 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4145 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4146 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4147 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4149 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4151 // PSRADQYri doesn't exist in SSE[1-3].
4153 } // Predicates = [HasAVX2]
4155 let Constraints = "$src1 = $dst" in {
4156 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4157 VR128, v8i16, v8i16, bc_v8i16,
4158 SSE_INTSHIFT_ITINS_P>;
4159 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4160 VR128, v4i32, v4i32, bc_v4i32,
4161 SSE_INTSHIFT_ITINS_P>;
4162 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4163 VR128, v2i64, v2i64, bc_v2i64,
4164 SSE_INTSHIFT_ITINS_P>;
4166 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4167 VR128, v8i16, v8i16, bc_v8i16,
4168 SSE_INTSHIFT_ITINS_P>;
4169 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4170 VR128, v4i32, v4i32, bc_v4i32,
4171 SSE_INTSHIFT_ITINS_P>;
4172 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4173 VR128, v2i64, v2i64, bc_v2i64,
4174 SSE_INTSHIFT_ITINS_P>;
4176 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4177 VR128, v8i16, v8i16, bc_v8i16,
4178 SSE_INTSHIFT_ITINS_P>;
4179 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4180 VR128, v4i32, v4i32, bc_v4i32,
4181 SSE_INTSHIFT_ITINS_P>;
4183 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4184 // 128-bit logical shifts.
4185 def PSLLDQri : PDIi8<0x73, MRM7r,
4186 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4187 "pslldq\t{$src2, $dst|$dst, $src2}",
4189 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4190 IIC_SSE_INTSHDQ_P_RI>;
4191 def PSRLDQri : PDIi8<0x73, MRM3r,
4192 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4193 "psrldq\t{$src2, $dst|$dst, $src2}",
4195 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4196 IIC_SSE_INTSHDQ_P_RI>;
4197 // PSRADQri doesn't exist in SSE[1-3].
4199 } // Constraints = "$src1 = $dst"
4201 let Predicates = [HasAVX] in {
4202 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4203 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4204 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4205 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4206 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4207 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4209 // Shift up / down and insert zero's.
4210 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4211 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4212 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4213 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4216 let Predicates = [HasAVX2] in {
4217 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4218 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4219 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4220 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4223 let Predicates = [UseSSE2] in {
4224 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4225 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4226 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4227 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4228 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4229 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4231 // Shift up / down and insert zero's.
4232 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4233 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4234 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4235 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4238 //===---------------------------------------------------------------------===//
4239 // SSE2 - Packed Integer Comparison Instructions
4240 //===---------------------------------------------------------------------===//
4242 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4243 SSE_INTALU_ITINS_P, 1>;
4244 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4245 SSE_INTALU_ITINS_P, 1>;
4246 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4247 SSE_INTALU_ITINS_P, 1>;
4248 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4249 SSE_INTALU_ITINS_P, 0>;
4250 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4251 SSE_INTALU_ITINS_P, 0>;
4252 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4253 SSE_INTALU_ITINS_P, 0>;
4255 //===---------------------------------------------------------------------===//
4256 // SSE2 - Packed Integer Pack Instructions
4257 //===---------------------------------------------------------------------===//
4259 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4260 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
4261 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4262 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
4263 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4264 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
4266 //===---------------------------------------------------------------------===//
4267 // SSE2 - Packed Integer Shuffle Instructions
4268 //===---------------------------------------------------------------------===//
4270 let ExeDomain = SSEPackedInt in {
4271 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4273 let Predicates = [HasAVX] in {
4274 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4275 (ins VR128:$src1, i8imm:$src2),
4276 !strconcat("v", OpcodeStr,
4277 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4279 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4280 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4281 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4282 (ins i128mem:$src1, i8imm:$src2),
4283 !strconcat("v", OpcodeStr,
4284 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4286 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4287 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4288 Sched<[WriteShuffleLd]>;
4291 let Predicates = [HasAVX2] in {
4292 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4293 (ins VR256:$src1, i8imm:$src2),
4294 !strconcat("v", OpcodeStr,
4295 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4297 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4298 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4299 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4300 (ins i256mem:$src1, i8imm:$src2),
4301 !strconcat("v", OpcodeStr,
4302 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4304 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4305 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4306 Sched<[WriteShuffleLd]>;
4309 let Predicates = [UseSSE2] in {
4310 def ri : Ii8<0x70, MRMSrcReg,
4311 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4312 !strconcat(OpcodeStr,
4313 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4315 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4316 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4317 def mi : Ii8<0x70, MRMSrcMem,
4318 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4319 !strconcat(OpcodeStr,
4320 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4322 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4323 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4324 Sched<[WriteShuffleLd]>;
4327 } // ExeDomain = SSEPackedInt
4329 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4330 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4331 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4333 let Predicates = [HasAVX] in {
4334 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4335 (VPSHUFDmi addr:$src1, imm:$imm)>;
4336 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4337 (VPSHUFDri VR128:$src1, imm:$imm)>;
4340 let Predicates = [UseSSE2] in {
4341 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4342 (PSHUFDmi addr:$src1, imm:$imm)>;
4343 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4344 (PSHUFDri VR128:$src1, imm:$imm)>;
4347 //===---------------------------------------------------------------------===//
4348 // SSE2 - Packed Integer Unpack Instructions
4349 //===---------------------------------------------------------------------===//
4351 let ExeDomain = SSEPackedInt in {
4352 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4353 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4354 def rr : PDI<opc, MRMSrcReg,
4355 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4357 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4358 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4359 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4360 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4361 def rm : PDI<opc, MRMSrcMem,
4362 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4364 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4365 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4366 [(set VR128:$dst, (OpNode VR128:$src1,
4367 (bc_frag (memopv2i64
4370 Sched<[WriteShuffleLd, ReadAfterLd]>;
4373 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4374 SDNode OpNode, PatFrag bc_frag> {
4375 def Yrr : PDI<opc, MRMSrcReg,
4376 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4377 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4378 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4379 Sched<[WriteShuffle]>;
4380 def Yrm : PDI<opc, MRMSrcMem,
4381 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4382 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4383 [(set VR256:$dst, (OpNode VR256:$src1,
4384 (bc_frag (memopv4i64 addr:$src2))))]>,
4385 Sched<[WriteShuffleLd, ReadAfterLd]>;
4388 let Predicates = [HasAVX] in {
4389 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4390 bc_v16i8, 0>, VEX_4V;
4391 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4392 bc_v8i16, 0>, VEX_4V;
4393 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4394 bc_v4i32, 0>, VEX_4V;
4395 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4396 bc_v2i64, 0>, VEX_4V;
4398 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4399 bc_v16i8, 0>, VEX_4V;
4400 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4401 bc_v8i16, 0>, VEX_4V;
4402 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4403 bc_v4i32, 0>, VEX_4V;
4404 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4405 bc_v2i64, 0>, VEX_4V;
4408 let Predicates = [HasAVX2] in {
4409 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4410 bc_v32i8>, VEX_4V, VEX_L;
4411 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4412 bc_v16i16>, VEX_4V, VEX_L;
4413 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4414 bc_v8i32>, VEX_4V, VEX_L;
4415 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4416 bc_v4i64>, VEX_4V, VEX_L;
4418 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4419 bc_v32i8>, VEX_4V, VEX_L;
4420 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4421 bc_v16i16>, VEX_4V, VEX_L;
4422 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4423 bc_v8i32>, VEX_4V, VEX_L;
4424 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4425 bc_v4i64>, VEX_4V, VEX_L;
4428 let Constraints = "$src1 = $dst" in {
4429 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4431 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4433 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4435 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4438 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4440 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4442 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4444 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4447 } // ExeDomain = SSEPackedInt
4449 //===---------------------------------------------------------------------===//
4450 // SSE2 - Packed Integer Extract and Insert
4451 //===---------------------------------------------------------------------===//
4453 let ExeDomain = SSEPackedInt in {
4454 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4455 def rri : Ii8<0xC4, MRMSrcReg,
4456 (outs VR128:$dst), (ins VR128:$src1,
4457 GR32orGR64:$src2, i32i8imm:$src3),
4459 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4460 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4462 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4463 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4464 def rmi : Ii8<0xC4, MRMSrcMem,
4465 (outs VR128:$dst), (ins VR128:$src1,
4466 i16mem:$src2, i32i8imm:$src3),
4468 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4469 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4471 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4472 imm:$src3))], IIC_SSE_PINSRW>,
4473 Sched<[WriteShuffleLd, ReadAfterLd]>;
4477 let Predicates = [HasAVX] in
4478 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4479 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4480 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4481 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4482 imm:$src2))]>, TB, OpSize, VEX,
4483 Sched<[WriteShuffle]>;
4484 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4485 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4486 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4487 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4488 imm:$src2))], IIC_SSE_PEXTRW>,
4489 Sched<[WriteShuffleLd, ReadAfterLd]>;
4492 let Predicates = [HasAVX] in
4493 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4495 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4496 defm PINSRW : sse2_pinsrw, TB, OpSize;
4498 } // ExeDomain = SSEPackedInt
4500 //===---------------------------------------------------------------------===//
4501 // SSE2 - Packed Mask Creation
4502 //===---------------------------------------------------------------------===//
4504 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4506 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4508 "pmovmskb\t{$src, $dst|$dst, $src}",
4509 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4510 IIC_SSE_MOVMSK>, VEX;
4512 let Predicates = [HasAVX2] in {
4513 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4515 "pmovmskb\t{$src, $dst|$dst, $src}",
4516 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4520 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4521 "pmovmskb\t{$src, $dst|$dst, $src}",
4522 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4525 } // ExeDomain = SSEPackedInt
4527 //===---------------------------------------------------------------------===//
4528 // SSE2 - Conditional Store
4529 //===---------------------------------------------------------------------===//
4531 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4533 let Uses = [EDI], Predicates = [HasAVX,In32BitMode] in
4534 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4535 (ins VR128:$src, VR128:$mask),
4536 "maskmovdqu\t{$mask, $src|$src, $mask}",
4537 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4538 IIC_SSE_MASKMOV>, VEX;
4539 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4540 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4541 (ins VR128:$src, VR128:$mask),
4542 "maskmovdqu\t{$mask, $src|$src, $mask}",
4543 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4544 IIC_SSE_MASKMOV>, VEX;
4546 let Uses = [EDI], Predicates = [UseSSE2,In32BitMode] in
4547 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4548 "maskmovdqu\t{$mask, $src|$src, $mask}",
4549 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4551 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4552 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4553 "maskmovdqu\t{$mask, $src|$src, $mask}",
4554 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4557 } // ExeDomain = SSEPackedInt
4559 //===---------------------------------------------------------------------===//
4560 // SSE2 - Move Doubleword
4561 //===---------------------------------------------------------------------===//
4563 //===---------------------------------------------------------------------===//
4564 // Move Int Doubleword to Packed Double Int
4566 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4567 "movd\t{$src, $dst|$dst, $src}",
4569 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4570 VEX, Sched<[WriteMove]>;
4571 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4572 "movd\t{$src, $dst|$dst, $src}",
4574 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4576 VEX, Sched<[WriteLoad]>;
4577 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4578 "movq\t{$src, $dst|$dst, $src}",
4580 (v2i64 (scalar_to_vector GR64:$src)))],
4581 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4582 let isCodeGenOnly = 1 in
4583 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4584 "movq\t{$src, $dst|$dst, $src}",
4585 [(set FR64:$dst, (bitconvert GR64:$src))],
4586 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4588 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4589 "movd\t{$src, $dst|$dst, $src}",
4591 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4593 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4594 "movd\t{$src, $dst|$dst, $src}",
4596 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4597 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4598 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4599 "mov{d|q}\t{$src, $dst|$dst, $src}",
4601 (v2i64 (scalar_to_vector GR64:$src)))],
4602 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4603 let isCodeGenOnly = 1 in
4604 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4605 "mov{d|q}\t{$src, $dst|$dst, $src}",
4606 [(set FR64:$dst, (bitconvert GR64:$src))],
4607 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4609 //===---------------------------------------------------------------------===//
4610 // Move Int Doubleword to Single Scalar
4612 let isCodeGenOnly = 1 in {
4613 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4614 "movd\t{$src, $dst|$dst, $src}",
4615 [(set FR32:$dst, (bitconvert GR32:$src))],
4616 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4618 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4619 "movd\t{$src, $dst|$dst, $src}",
4620 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4622 VEX, Sched<[WriteLoad]>;
4623 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4624 "movd\t{$src, $dst|$dst, $src}",
4625 [(set FR32:$dst, (bitconvert GR32:$src))],
4626 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4628 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4629 "movd\t{$src, $dst|$dst, $src}",
4630 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4631 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4634 //===---------------------------------------------------------------------===//
4635 // Move Packed Doubleword Int to Packed Double Int
4637 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4638 "movd\t{$src, $dst|$dst, $src}",
4639 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4640 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4642 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4643 (ins i32mem:$dst, VR128:$src),
4644 "movd\t{$src, $dst|$dst, $src}",
4645 [(store (i32 (vector_extract (v4i32 VR128:$src),
4646 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4647 VEX, Sched<[WriteLoad]>;
4648 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4649 "movd\t{$src, $dst|$dst, $src}",
4650 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4651 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4653 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4654 "movd\t{$src, $dst|$dst, $src}",
4655 [(store (i32 (vector_extract (v4i32 VR128:$src),
4656 (iPTR 0))), addr:$dst)],
4657 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4659 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4660 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4662 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4663 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4665 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4666 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4668 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4669 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4671 //===---------------------------------------------------------------------===//
4672 // Move Packed Doubleword Int first element to Doubleword Int
4674 let SchedRW = [WriteMove] in {
4675 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4676 "movq\t{$src, $dst|$dst, $src}",
4677 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4682 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4683 "mov{d|q}\t{$src, $dst|$dst, $src}",
4684 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4689 //===---------------------------------------------------------------------===//
4690 // Bitcast FR64 <-> GR64
4692 let isCodeGenOnly = 1 in {
4693 let Predicates = [UseAVX] in
4694 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4695 "movq\t{$src, $dst|$dst, $src}",
4696 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4697 VEX, Sched<[WriteLoad]>;
4698 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4699 "movq\t{$src, $dst|$dst, $src}",
4700 [(set GR64:$dst, (bitconvert FR64:$src))],
4701 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4702 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4703 "movq\t{$src, $dst|$dst, $src}",
4704 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4705 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4707 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4708 "movq\t{$src, $dst|$dst, $src}",
4709 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4710 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4711 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4712 "mov{d|q}\t{$src, $dst|$dst, $src}",
4713 [(set GR64:$dst, (bitconvert FR64:$src))],
4714 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4715 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4716 "movq\t{$src, $dst|$dst, $src}",
4717 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4718 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4721 //===---------------------------------------------------------------------===//
4722 // Move Scalar Single to Double Int
4724 let isCodeGenOnly = 1 in {
4725 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4726 "movd\t{$src, $dst|$dst, $src}",
4727 [(set GR32:$dst, (bitconvert FR32:$src))],
4728 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4729 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4730 "movd\t{$src, $dst|$dst, $src}",
4731 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4732 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4733 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4734 "movd\t{$src, $dst|$dst, $src}",
4735 [(set GR32:$dst, (bitconvert FR32:$src))],
4736 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4737 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4738 "movd\t{$src, $dst|$dst, $src}",
4739 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4740 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4743 //===---------------------------------------------------------------------===//
4744 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4746 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4747 let AddedComplexity = 15 in {
4748 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4749 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4750 [(set VR128:$dst, (v2i64 (X86vzmovl
4751 (v2i64 (scalar_to_vector GR64:$src)))))],
4754 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4755 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4756 [(set VR128:$dst, (v2i64 (X86vzmovl
4757 (v2i64 (scalar_to_vector GR64:$src)))))],
4760 } // isCodeGenOnly, SchedRW
4762 let Predicates = [UseAVX] in {
4763 let AddedComplexity = 15 in
4764 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4765 (VMOVDI2PDIrr GR32:$src)>;
4767 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4768 let AddedComplexity = 20 in {
4769 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4770 (VMOVDI2PDIrm addr:$src)>;
4771 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4772 (VMOVDI2PDIrm addr:$src)>;
4773 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4774 (VMOVDI2PDIrm addr:$src)>;
4776 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4777 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4778 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4779 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4780 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4781 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4782 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4785 let Predicates = [UseSSE2] in {
4786 let AddedComplexity = 15 in
4787 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4788 (MOVDI2PDIrr GR32:$src)>;
4790 let AddedComplexity = 20 in {
4791 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4792 (MOVDI2PDIrm addr:$src)>;
4793 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4794 (MOVDI2PDIrm addr:$src)>;
4795 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4796 (MOVDI2PDIrm addr:$src)>;
4800 // These are the correct encodings of the instructions so that we know how to
4801 // read correct assembly, even though we continue to emit the wrong ones for
4802 // compatibility with Darwin's buggy assembler.
4803 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4804 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4805 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4806 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4807 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4808 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4809 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4810 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4811 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4813 //===---------------------------------------------------------------------===//
4814 // SSE2 - Move Quadword
4815 //===---------------------------------------------------------------------===//
4817 //===---------------------------------------------------------------------===//
4818 // Move Quadword Int to Packed Quadword Int
4821 let SchedRW = [WriteLoad] in {
4822 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4823 "vmovq\t{$src, $dst|$dst, $src}",
4825 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4826 VEX, Requires<[UseAVX]>;
4827 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4828 "movq\t{$src, $dst|$dst, $src}",
4830 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4832 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4835 //===---------------------------------------------------------------------===//
4836 // Move Packed Quadword Int to Quadword Int
4838 let SchedRW = [WriteStore] in {
4839 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4840 "movq\t{$src, $dst|$dst, $src}",
4841 [(store (i64 (vector_extract (v2i64 VR128:$src),
4842 (iPTR 0))), addr:$dst)],
4843 IIC_SSE_MOVDQ>, VEX;
4844 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4845 "movq\t{$src, $dst|$dst, $src}",
4846 [(store (i64 (vector_extract (v2i64 VR128:$src),
4847 (iPTR 0))), addr:$dst)],
4851 //===---------------------------------------------------------------------===//
4852 // Store / copy lower 64-bits of a XMM register.
4854 def VMOVLQ128mr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4855 "movq\t{$src, $dst|$dst, $src}",
4856 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX,
4857 Sched<[WriteStore]>;
4858 def MOVLQ128mr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4859 "movq\t{$src, $dst|$dst, $src}",
4860 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4861 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4863 let isCodeGenOnly = 1, AddedComplexity = 20 in {
4864 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4865 "vmovq\t{$src, $dst|$dst, $src}",
4867 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4868 (loadi64 addr:$src))))))],
4870 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
4872 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4873 "movq\t{$src, $dst|$dst, $src}",
4875 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4876 (loadi64 addr:$src))))))],
4878 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4881 let Predicates = [UseAVX], AddedComplexity = 20 in {
4882 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4883 (VMOVZQI2PQIrm addr:$src)>;
4884 def : Pat<(v2i64 (X86vzload addr:$src)),
4885 (VMOVZQI2PQIrm addr:$src)>;
4888 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4889 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4890 (MOVZQI2PQIrm addr:$src)>;
4891 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4894 let Predicates = [HasAVX] in {
4895 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4896 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4897 def : Pat<(v4i64 (X86vzload addr:$src)),
4898 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4901 //===---------------------------------------------------------------------===//
4902 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4903 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4905 let SchedRW = [WriteVecLogic] in {
4906 let AddedComplexity = 15 in
4907 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4908 "vmovq\t{$src, $dst|$dst, $src}",
4909 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4911 XS, VEX, Requires<[UseAVX]>;
4912 let AddedComplexity = 15 in
4913 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4914 "movq\t{$src, $dst|$dst, $src}",
4915 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4917 XS, Requires<[UseSSE2]>;
4920 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
4921 let AddedComplexity = 20 in
4922 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4923 "vmovq\t{$src, $dst|$dst, $src}",
4924 [(set VR128:$dst, (v2i64 (X86vzmovl
4925 (loadv2i64 addr:$src))))],
4927 XS, VEX, Requires<[UseAVX]>;
4928 let AddedComplexity = 20 in {
4929 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4930 "movq\t{$src, $dst|$dst, $src}",
4931 [(set VR128:$dst, (v2i64 (X86vzmovl
4932 (loadv2i64 addr:$src))))],
4934 XS, Requires<[UseSSE2]>;
4936 } // isCodeGenOnly, SchedRW
4938 let AddedComplexity = 20 in {
4939 let Predicates = [UseAVX] in {
4940 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4941 (VMOVZPQILo2PQIrr VR128:$src)>;
4943 let Predicates = [UseSSE2] in {
4944 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4945 (MOVZPQILo2PQIrr VR128:$src)>;
4949 //===---------------------------------------------------------------------===//
4950 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4951 //===---------------------------------------------------------------------===//
4952 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4953 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4954 X86MemOperand x86memop> {
4955 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4956 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4957 [(set RC:$dst, (vt (OpNode RC:$src)))],
4958 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4959 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4960 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4961 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4962 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4965 let Predicates = [HasAVX] in {
4966 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4967 v4f32, VR128, loadv4f32, f128mem>, VEX;
4968 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4969 v4f32, VR128, loadv4f32, f128mem>, VEX;
4970 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4971 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
4972 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4973 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
4975 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4976 memopv4f32, f128mem>;
4977 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4978 memopv4f32, f128mem>;
4980 let Predicates = [HasAVX] in {
4981 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4982 (VMOVSHDUPrr VR128:$src)>;
4983 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
4984 (VMOVSHDUPrm addr:$src)>;
4985 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4986 (VMOVSLDUPrr VR128:$src)>;
4987 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
4988 (VMOVSLDUPrm addr:$src)>;
4989 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4990 (VMOVSHDUPYrr VR256:$src)>;
4991 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
4992 (VMOVSHDUPYrm addr:$src)>;
4993 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4994 (VMOVSLDUPYrr VR256:$src)>;
4995 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
4996 (VMOVSLDUPYrm addr:$src)>;
4999 let Predicates = [UseSSE3] in {
5000 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5001 (MOVSHDUPrr VR128:$src)>;
5002 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5003 (MOVSHDUPrm addr:$src)>;
5004 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5005 (MOVSLDUPrr VR128:$src)>;
5006 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5007 (MOVSLDUPrm addr:$src)>;
5010 //===---------------------------------------------------------------------===//
5011 // SSE3 - Replicate Double FP - MOVDDUP
5012 //===---------------------------------------------------------------------===//
5014 multiclass sse3_replicate_dfp<string OpcodeStr> {
5015 let neverHasSideEffects = 1 in
5016 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5017 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5018 [], IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
5019 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5020 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5023 (scalar_to_vector (loadf64 addr:$src)))))],
5024 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
5027 // FIXME: Merge with above classe when there're patterns for the ymm version
5028 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5029 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5030 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5031 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5032 Sched<[WriteShuffle]>;
5033 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5034 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5037 (scalar_to_vector (loadf64 addr:$src)))))]>,
5038 Sched<[WriteShuffleLd]>;
5041 let Predicates = [HasAVX] in {
5042 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5043 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5046 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5048 let Predicates = [HasAVX] in {
5049 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5050 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5051 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5052 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5053 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5054 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5055 def : Pat<(X86Movddup (bc_v2f64
5056 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5057 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5060 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5061 (VMOVDDUPYrm addr:$src)>;
5062 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5063 (VMOVDDUPYrm addr:$src)>;
5064 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5065 (VMOVDDUPYrm addr:$src)>;
5066 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5067 (VMOVDDUPYrr VR256:$src)>;
5070 let Predicates = [UseSSE3] in {
5071 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5072 (MOVDDUPrm addr:$src)>;
5073 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5074 (MOVDDUPrm addr:$src)>;
5075 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5076 (MOVDDUPrm addr:$src)>;
5077 def : Pat<(X86Movddup (bc_v2f64
5078 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5079 (MOVDDUPrm addr:$src)>;
5082 //===---------------------------------------------------------------------===//
5083 // SSE3 - Move Unaligned Integer
5084 //===---------------------------------------------------------------------===//
5086 let SchedRW = [WriteLoad] in {
5087 let Predicates = [HasAVX] in {
5088 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5089 "vlddqu\t{$src, $dst|$dst, $src}",
5090 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5091 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5092 "vlddqu\t{$src, $dst|$dst, $src}",
5093 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5096 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5097 "lddqu\t{$src, $dst|$dst, $src}",
5098 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5102 //===---------------------------------------------------------------------===//
5103 // SSE3 - Arithmetic
5104 //===---------------------------------------------------------------------===//
5106 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5107 X86MemOperand x86memop, OpndItins itins,
5109 def rr : I<0xD0, MRMSrcReg,
5110 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5112 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5113 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5114 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5115 Sched<[itins.Sched]>;
5116 def rm : I<0xD0, MRMSrcMem,
5117 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5119 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5120 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5121 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5122 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5125 let Predicates = [HasAVX] in {
5126 let ExeDomain = SSEPackedSingle in {
5127 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5128 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5129 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5130 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
5132 let ExeDomain = SSEPackedDouble in {
5133 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5134 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5135 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5136 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
5139 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5140 let ExeDomain = SSEPackedSingle in
5141 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5142 f128mem, SSE_ALU_F32P>, TB, XD;
5143 let ExeDomain = SSEPackedDouble in
5144 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5145 f128mem, SSE_ALU_F64P>, TB, OpSize;
5148 //===---------------------------------------------------------------------===//
5149 // SSE3 Instructions
5150 //===---------------------------------------------------------------------===//
5153 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5154 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5155 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5157 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5158 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5159 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5162 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5164 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5165 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5166 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5167 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5169 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5170 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5171 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5173 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5174 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5175 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5178 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5180 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5181 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5182 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5183 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5186 let Predicates = [HasAVX] in {
5187 let ExeDomain = SSEPackedSingle in {
5188 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5189 X86fhadd, 0>, VEX_4V;
5190 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5191 X86fhsub, 0>, VEX_4V;
5192 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5193 X86fhadd, 0>, VEX_4V, VEX_L;
5194 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5195 X86fhsub, 0>, VEX_4V, VEX_L;
5197 let ExeDomain = SSEPackedDouble in {
5198 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5199 X86fhadd, 0>, VEX_4V;
5200 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5201 X86fhsub, 0>, VEX_4V;
5202 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5203 X86fhadd, 0>, VEX_4V, VEX_L;
5204 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5205 X86fhsub, 0>, VEX_4V, VEX_L;
5209 let Constraints = "$src1 = $dst" in {
5210 let ExeDomain = SSEPackedSingle in {
5211 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5212 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5214 let ExeDomain = SSEPackedDouble in {
5215 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5216 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5220 //===---------------------------------------------------------------------===//
5221 // SSSE3 - Packed Absolute Instructions
5222 //===---------------------------------------------------------------------===//
5225 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5226 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5227 Intrinsic IntId128> {
5228 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5230 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5231 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5232 OpSize, Sched<[WriteVecALU]>;
5234 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5236 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5239 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5240 OpSize, Sched<[WriteVecALULd]>;
5243 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5244 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5245 Intrinsic IntId256> {
5246 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5248 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5249 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5250 OpSize, Sched<[WriteVecALU]>;
5252 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5254 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5257 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5258 Sched<[WriteVecALULd]>;
5261 // Helper fragments to match sext vXi1 to vXiY.
5262 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5264 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5265 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5266 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5268 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5269 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5271 let Predicates = [HasAVX] in {
5272 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5273 int_x86_ssse3_pabs_b_128>, VEX;
5274 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5275 int_x86_ssse3_pabs_w_128>, VEX;
5276 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5277 int_x86_ssse3_pabs_d_128>, VEX;
5280 (bc_v2i64 (v16i1sextv16i8)),
5281 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5282 (VPABSBrr128 VR128:$src)>;
5284 (bc_v2i64 (v8i1sextv8i16)),
5285 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5286 (VPABSWrr128 VR128:$src)>;
5288 (bc_v2i64 (v4i1sextv4i32)),
5289 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5290 (VPABSDrr128 VR128:$src)>;
5293 let Predicates = [HasAVX2] in {
5294 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5295 int_x86_avx2_pabs_b>, VEX, VEX_L;
5296 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5297 int_x86_avx2_pabs_w>, VEX, VEX_L;
5298 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5299 int_x86_avx2_pabs_d>, VEX, VEX_L;
5302 (bc_v4i64 (v32i1sextv32i8)),
5303 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5304 (VPABSBrr256 VR256:$src)>;
5306 (bc_v4i64 (v16i1sextv16i16)),
5307 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5308 (VPABSWrr256 VR256:$src)>;
5310 (bc_v4i64 (v8i1sextv8i32)),
5311 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5312 (VPABSDrr256 VR256:$src)>;
5315 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5316 int_x86_ssse3_pabs_b_128>;
5317 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5318 int_x86_ssse3_pabs_w_128>;
5319 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5320 int_x86_ssse3_pabs_d_128>;
5322 let Predicates = [HasSSSE3] in {
5324 (bc_v2i64 (v16i1sextv16i8)),
5325 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5326 (PABSBrr128 VR128:$src)>;
5328 (bc_v2i64 (v8i1sextv8i16)),
5329 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5330 (PABSWrr128 VR128:$src)>;
5332 (bc_v2i64 (v4i1sextv4i32)),
5333 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5334 (PABSDrr128 VR128:$src)>;
5337 //===---------------------------------------------------------------------===//
5338 // SSSE3 - Packed Binary Operator Instructions
5339 //===---------------------------------------------------------------------===//
5341 let Sched = WriteVecALU in {
5342 def SSE_PHADDSUBD : OpndItins<
5343 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5345 def SSE_PHADDSUBSW : OpndItins<
5346 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5348 def SSE_PHADDSUBW : OpndItins<
5349 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5352 let Sched = WriteShuffle in
5353 def SSE_PSHUFB : OpndItins<
5354 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5356 let Sched = WriteVecALU in
5357 def SSE_PSIGN : OpndItins<
5358 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5360 let Sched = WriteVecIMul in
5361 def SSE_PMULHRSW : OpndItins<
5362 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5365 /// SS3I_binop_rm - Simple SSSE3 bin op
5366 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5367 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5368 X86MemOperand x86memop, OpndItins itins,
5370 let isCommutable = 1 in
5371 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5372 (ins RC:$src1, RC:$src2),
5374 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5375 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5376 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5377 OpSize, Sched<[itins.Sched]>;
5378 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5379 (ins RC:$src1, x86memop:$src2),
5381 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5382 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5384 (OpVT (OpNode RC:$src1,
5385 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5386 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5389 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5390 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5391 Intrinsic IntId128, OpndItins itins,
5393 let isCommutable = 1 in
5394 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5395 (ins VR128:$src1, VR128:$src2),
5397 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5398 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5399 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5400 OpSize, Sched<[itins.Sched]>;
5401 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5402 (ins VR128:$src1, i128mem:$src2),
5404 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5405 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5407 (IntId128 VR128:$src1,
5408 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5409 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5412 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5413 Intrinsic IntId256> {
5414 let isCommutable = 1 in
5415 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5416 (ins VR256:$src1, VR256:$src2),
5417 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5418 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5420 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5421 (ins VR256:$src1, i256mem:$src2),
5422 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5424 (IntId256 VR256:$src1,
5425 (bitconvert (loadv4i64 addr:$src2))))]>, OpSize;
5428 let ImmT = NoImm, Predicates = [HasAVX] in {
5429 let isCommutable = 0 in {
5430 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5432 SSE_PHADDSUBW, 0>, VEX_4V;
5433 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5435 SSE_PHADDSUBD, 0>, VEX_4V;
5436 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5438 SSE_PHADDSUBW, 0>, VEX_4V;
5439 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5441 SSE_PHADDSUBD, 0>, VEX_4V;
5442 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5444 SSE_PSIGN, 0>, VEX_4V;
5445 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5447 SSE_PSIGN, 0>, VEX_4V;
5448 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5450 SSE_PSIGN, 0>, VEX_4V;
5451 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5453 SSE_PSHUFB, 0>, VEX_4V;
5454 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5455 int_x86_ssse3_phadd_sw_128,
5456 SSE_PHADDSUBSW, 0>, VEX_4V;
5457 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5458 int_x86_ssse3_phsub_sw_128,
5459 SSE_PHADDSUBSW, 0>, VEX_4V;
5460 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5461 int_x86_ssse3_pmadd_ub_sw_128,
5462 SSE_PMADD, 0>, VEX_4V;
5464 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5465 int_x86_ssse3_pmul_hr_sw_128,
5466 SSE_PMULHRSW, 0>, VEX_4V;
5469 let ImmT = NoImm, Predicates = [HasAVX2] in {
5470 let isCommutable = 0 in {
5471 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5473 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5474 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5476 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5477 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5479 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5480 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5482 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5483 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5485 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5486 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5488 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5489 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5491 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5492 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5494 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5495 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5496 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5497 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5498 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5499 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5500 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5502 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5503 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5506 // None of these have i8 immediate fields.
5507 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5508 let isCommutable = 0 in {
5509 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5510 memopv2i64, i128mem, SSE_PHADDSUBW>;
5511 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5512 memopv2i64, i128mem, SSE_PHADDSUBD>;
5513 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5514 memopv2i64, i128mem, SSE_PHADDSUBW>;
5515 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5516 memopv2i64, i128mem, SSE_PHADDSUBD>;
5517 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5518 memopv2i64, i128mem, SSE_PSIGN>;
5519 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5520 memopv2i64, i128mem, SSE_PSIGN>;
5521 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5522 memopv2i64, i128mem, SSE_PSIGN>;
5523 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5524 memopv2i64, i128mem, SSE_PSHUFB>;
5525 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5526 int_x86_ssse3_phadd_sw_128,
5528 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5529 int_x86_ssse3_phsub_sw_128,
5531 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5532 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5534 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5535 int_x86_ssse3_pmul_hr_sw_128,
5539 //===---------------------------------------------------------------------===//
5540 // SSSE3 - Packed Align Instruction Patterns
5541 //===---------------------------------------------------------------------===//
5543 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5544 let neverHasSideEffects = 1 in {
5545 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5546 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5548 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5550 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5551 [], IIC_SSE_PALIGNRR>, OpSize, Sched<[WriteShuffle]>;
5553 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5554 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5556 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5558 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5559 [], IIC_SSE_PALIGNRM>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5563 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5564 let neverHasSideEffects = 1 in {
5565 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5566 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5568 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5569 []>, OpSize, Sched<[WriteShuffle]>;
5571 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5572 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5574 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5575 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5579 let Predicates = [HasAVX] in
5580 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5581 let Predicates = [HasAVX2] in
5582 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5583 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5584 defm PALIGN : ssse3_palignr<"palignr">;
5586 let Predicates = [HasAVX2] in {
5587 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5588 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5589 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5590 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5591 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5592 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5593 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5594 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5597 let Predicates = [HasAVX] in {
5598 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5599 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5600 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5601 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5602 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5603 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5604 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5605 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5608 let Predicates = [UseSSSE3] in {
5609 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5610 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5611 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5612 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5613 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5614 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5615 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5616 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5619 //===---------------------------------------------------------------------===//
5620 // SSSE3 - Thread synchronization
5621 //===---------------------------------------------------------------------===//
5623 let SchedRW = [WriteSystem] in {
5624 let usesCustomInserter = 1 in {
5625 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5626 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5627 Requires<[HasSSE3]>;
5630 let Uses = [EAX, ECX, EDX] in
5631 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5632 TB, Requires<[HasSSE3]>;
5633 let Uses = [ECX, EAX] in
5634 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5635 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5636 TB, Requires<[HasSSE3]>;
5639 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[In32BitMode]>;
5640 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5642 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5643 Requires<[In32BitMode]>;
5644 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5645 Requires<[In64BitMode]>;
5647 //===----------------------------------------------------------------------===//
5648 // SSE4.1 - Packed Move with Sign/Zero Extend
5649 //===----------------------------------------------------------------------===//
5651 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5652 OpndItins itins = DEFAULT_ITINS> {
5653 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5654 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5655 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5657 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5658 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5660 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5664 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5666 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5667 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5668 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5670 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5671 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5672 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5676 let Predicates = [HasAVX] in {
5677 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5678 int_x86_sse41_pmovsxbw>, VEX;
5679 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5680 int_x86_sse41_pmovsxwd>, VEX;
5681 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5682 int_x86_sse41_pmovsxdq>, VEX;
5683 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5684 int_x86_sse41_pmovzxbw>, VEX;
5685 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5686 int_x86_sse41_pmovzxwd>, VEX;
5687 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5688 int_x86_sse41_pmovzxdq>, VEX;
5691 let Predicates = [HasAVX2] in {
5692 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5693 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5694 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5695 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5696 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5697 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5698 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5699 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5700 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5701 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5702 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5703 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5706 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw, SSE_INTALU_ITINS_P>;
5707 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd, SSE_INTALU_ITINS_P>;
5708 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq, SSE_INTALU_ITINS_P>;
5709 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw, SSE_INTALU_ITINS_P>;
5710 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd, SSE_INTALU_ITINS_P>;
5711 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq, SSE_INTALU_ITINS_P>;
5713 let Predicates = [HasAVX] in {
5714 // Common patterns involving scalar load.
5715 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5716 (VPMOVSXBWrm addr:$src)>;
5717 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5718 (VPMOVSXBWrm addr:$src)>;
5719 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5720 (VPMOVSXBWrm addr:$src)>;
5722 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5723 (VPMOVSXWDrm addr:$src)>;
5724 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5725 (VPMOVSXWDrm addr:$src)>;
5726 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5727 (VPMOVSXWDrm addr:$src)>;
5729 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5730 (VPMOVSXDQrm addr:$src)>;
5731 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5732 (VPMOVSXDQrm addr:$src)>;
5733 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5734 (VPMOVSXDQrm addr:$src)>;
5736 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5737 (VPMOVZXBWrm addr:$src)>;
5738 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5739 (VPMOVZXBWrm addr:$src)>;
5740 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5741 (VPMOVZXBWrm addr:$src)>;
5743 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5744 (VPMOVZXWDrm addr:$src)>;
5745 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5746 (VPMOVZXWDrm addr:$src)>;
5747 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5748 (VPMOVZXWDrm addr:$src)>;
5750 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5751 (VPMOVZXDQrm addr:$src)>;
5752 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5753 (VPMOVZXDQrm addr:$src)>;
5754 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5755 (VPMOVZXDQrm addr:$src)>;
5758 let Predicates = [UseSSE41] in {
5759 // Common patterns involving scalar load.
5760 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5761 (PMOVSXBWrm addr:$src)>;
5762 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5763 (PMOVSXBWrm addr:$src)>;
5764 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5765 (PMOVSXBWrm addr:$src)>;
5767 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5768 (PMOVSXWDrm addr:$src)>;
5769 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5770 (PMOVSXWDrm addr:$src)>;
5771 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5772 (PMOVSXWDrm addr:$src)>;
5774 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5775 (PMOVSXDQrm addr:$src)>;
5776 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5777 (PMOVSXDQrm addr:$src)>;
5778 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5779 (PMOVSXDQrm addr:$src)>;
5781 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5782 (PMOVZXBWrm addr:$src)>;
5783 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5784 (PMOVZXBWrm addr:$src)>;
5785 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5786 (PMOVZXBWrm addr:$src)>;
5788 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5789 (PMOVZXWDrm addr:$src)>;
5790 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5791 (PMOVZXWDrm addr:$src)>;
5792 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5793 (PMOVZXWDrm addr:$src)>;
5795 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5796 (PMOVZXDQrm addr:$src)>;
5797 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5798 (PMOVZXDQrm addr:$src)>;
5799 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5800 (PMOVZXDQrm addr:$src)>;
5803 let Predicates = [HasAVX2] in {
5804 let AddedComplexity = 15 in {
5805 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5806 (VPMOVZXDQYrr VR128:$src)>;
5807 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5808 (VPMOVZXWDYrr VR128:$src)>;
5809 def : Pat<(v16i16 (X86vzmovly (v16i8 VR128:$src))),
5810 (VPMOVZXBWYrr VR128:$src)>;
5813 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5814 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5815 def : Pat<(v16i16 (X86vsmovl (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5818 let Predicates = [HasAVX] in {
5819 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5820 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5821 def : Pat<(v8i16 (X86vsmovl (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5824 let Predicates = [UseSSE41] in {
5825 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5826 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5827 def : Pat<(v8i16 (X86vsmovl (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5831 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5832 OpndItins itins = DEFAULT_ITINS> {
5833 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5834 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5835 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5837 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5838 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5840 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
5845 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5847 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5848 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5849 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5851 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5852 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5854 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5858 let Predicates = [HasAVX] in {
5859 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5861 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5863 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5865 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5869 let Predicates = [HasAVX2] in {
5870 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5871 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5872 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5873 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5874 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5875 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5876 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5877 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5880 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
5881 SSE_INTALU_ITINS_P>;
5882 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
5883 SSE_INTALU_ITINS_P>;
5884 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
5885 SSE_INTALU_ITINS_P>;
5886 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
5887 SSE_INTALU_ITINS_P>;
5889 let Predicates = [HasAVX] in {
5890 // Common patterns involving scalar load
5891 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5892 (VPMOVSXBDrm addr:$src)>;
5893 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5894 (VPMOVSXWQrm addr:$src)>;
5896 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5897 (VPMOVZXBDrm addr:$src)>;
5898 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5899 (VPMOVZXWQrm addr:$src)>;
5902 let Predicates = [UseSSE41] in {
5903 // Common patterns involving scalar load
5904 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5905 (PMOVSXBDrm addr:$src)>;
5906 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5907 (PMOVSXWQrm addr:$src)>;
5909 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5910 (PMOVZXBDrm addr:$src)>;
5911 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5912 (PMOVZXWQrm addr:$src)>;
5915 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5916 OpndItins itins = DEFAULT_ITINS> {
5917 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5918 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5919 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5921 // Expecting a i16 load any extended to i32 value.
5922 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5923 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5924 [(set VR128:$dst, (IntId (bitconvert
5925 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5929 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5931 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5932 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5933 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5935 // Expecting a i16 load any extended to i32 value.
5936 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5937 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5938 [(set VR256:$dst, (IntId (bitconvert
5939 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5943 let Predicates = [HasAVX] in {
5944 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5946 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5949 let Predicates = [HasAVX2] in {
5950 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5951 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5952 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5953 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5955 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
5956 SSE_INTALU_ITINS_P>;
5957 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
5958 SSE_INTALU_ITINS_P>;
5960 let Predicates = [HasAVX2] in {
5961 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5962 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5963 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
5965 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5966 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
5968 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5970 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
5971 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5972 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
5973 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5974 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
5975 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5977 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
5978 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5979 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
5980 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5982 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
5983 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5985 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5986 (VPMOVSXWDYrm addr:$src)>;
5987 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5988 (VPMOVSXDQYrm addr:$src)>;
5990 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5991 (scalar_to_vector (loadi64 addr:$src))))))),
5992 (VPMOVSXBDYrm addr:$src)>;
5993 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5994 (scalar_to_vector (loadf64 addr:$src))))))),
5995 (VPMOVSXBDYrm addr:$src)>;
5997 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5998 (scalar_to_vector (loadi64 addr:$src))))))),
5999 (VPMOVSXWQYrm addr:$src)>;
6000 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
6001 (scalar_to_vector (loadf64 addr:$src))))))),
6002 (VPMOVSXWQYrm addr:$src)>;
6004 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
6005 (scalar_to_vector (loadi32 addr:$src))))))),
6006 (VPMOVSXBQYrm addr:$src)>;
6009 let Predicates = [HasAVX] in {
6010 // Common patterns involving scalar load
6011 def : Pat<(int_x86_sse41_pmovsxbq
6012 (bitconvert (v4i32 (X86vzmovl
6013 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6014 (VPMOVSXBQrm addr:$src)>;
6016 def : Pat<(int_x86_sse41_pmovzxbq
6017 (bitconvert (v4i32 (X86vzmovl
6018 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6019 (VPMOVZXBQrm addr:$src)>;
6022 let Predicates = [UseSSE41] in {
6023 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
6024 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
6025 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
6027 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
6028 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
6030 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
6032 // Common patterns involving scalar load
6033 def : Pat<(int_x86_sse41_pmovsxbq
6034 (bitconvert (v4i32 (X86vzmovl
6035 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6036 (PMOVSXBQrm addr:$src)>;
6038 def : Pat<(int_x86_sse41_pmovzxbq
6039 (bitconvert (v4i32 (X86vzmovl
6040 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6041 (PMOVZXBQrm addr:$src)>;
6043 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6044 (scalar_to_vector (loadi64 addr:$src))))))),
6045 (PMOVSXWDrm addr:$src)>;
6046 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6047 (scalar_to_vector (loadf64 addr:$src))))))),
6048 (PMOVSXWDrm addr:$src)>;
6049 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6050 (scalar_to_vector (loadi32 addr:$src))))))),
6051 (PMOVSXBDrm addr:$src)>;
6052 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6053 (scalar_to_vector (loadi32 addr:$src))))))),
6054 (PMOVSXWQrm addr:$src)>;
6055 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6056 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6057 (PMOVSXBQrm addr:$src)>;
6058 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6059 (scalar_to_vector (loadi64 addr:$src))))))),
6060 (PMOVSXDQrm addr:$src)>;
6061 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6062 (scalar_to_vector (loadf64 addr:$src))))))),
6063 (PMOVSXDQrm addr:$src)>;
6064 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6065 (scalar_to_vector (loadi64 addr:$src))))))),
6066 (PMOVSXBWrm addr:$src)>;
6067 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6068 (scalar_to_vector (loadf64 addr:$src))))))),
6069 (PMOVSXBWrm addr:$src)>;
6072 let Predicates = [HasAVX2] in {
6073 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
6074 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
6075 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
6077 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
6078 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
6080 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
6082 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
6083 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6084 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
6085 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6086 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
6087 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6089 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
6090 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6091 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
6092 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6094 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
6095 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6098 let Predicates = [HasAVX] in {
6099 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
6100 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
6101 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
6103 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
6104 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
6106 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
6108 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6109 (VPMOVZXBWrm addr:$src)>;
6110 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6111 (VPMOVZXBWrm addr:$src)>;
6112 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6113 (VPMOVZXBDrm addr:$src)>;
6114 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6115 (VPMOVZXBQrm addr:$src)>;
6117 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6118 (VPMOVZXWDrm addr:$src)>;
6119 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6120 (VPMOVZXWDrm addr:$src)>;
6121 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6122 (VPMOVZXWQrm addr:$src)>;
6124 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6125 (VPMOVZXDQrm addr:$src)>;
6126 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6127 (VPMOVZXDQrm addr:$src)>;
6128 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6129 (VPMOVZXDQrm addr:$src)>;
6131 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
6132 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
6133 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
6135 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
6136 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
6138 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
6140 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6141 (scalar_to_vector (loadi64 addr:$src))))))),
6142 (VPMOVSXWDrm addr:$src)>;
6143 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6144 (scalar_to_vector (loadi64 addr:$src))))))),
6145 (VPMOVSXDQrm addr:$src)>;
6146 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6147 (scalar_to_vector (loadf64 addr:$src))))))),
6148 (VPMOVSXWDrm addr:$src)>;
6149 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6150 (scalar_to_vector (loadf64 addr:$src))))))),
6151 (VPMOVSXDQrm addr:$src)>;
6152 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6153 (scalar_to_vector (loadi64 addr:$src))))))),
6154 (VPMOVSXBWrm addr:$src)>;
6155 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6156 (scalar_to_vector (loadf64 addr:$src))))))),
6157 (VPMOVSXBWrm addr:$src)>;
6159 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6160 (scalar_to_vector (loadi32 addr:$src))))))),
6161 (VPMOVSXBDrm addr:$src)>;
6162 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6163 (scalar_to_vector (loadi32 addr:$src))))))),
6164 (VPMOVSXWQrm addr:$src)>;
6165 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6166 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6167 (VPMOVSXBQrm addr:$src)>;
6170 let Predicates = [UseSSE41] in {
6171 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6172 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6173 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6175 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6176 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6178 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6180 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6181 (PMOVZXBWrm addr:$src)>;
6182 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6183 (PMOVZXBWrm addr:$src)>;
6184 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6185 (PMOVZXBDrm addr:$src)>;
6186 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6187 (PMOVZXBQrm addr:$src)>;
6189 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6190 (PMOVZXWDrm addr:$src)>;
6191 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6192 (PMOVZXWDrm addr:$src)>;
6193 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6194 (PMOVZXWQrm addr:$src)>;
6196 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6197 (PMOVZXDQrm addr:$src)>;
6198 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6199 (PMOVZXDQrm addr:$src)>;
6200 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6201 (PMOVZXDQrm addr:$src)>;
6204 //===----------------------------------------------------------------------===//
6205 // SSE4.1 - Extract Instructions
6206 //===----------------------------------------------------------------------===//
6208 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6209 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6210 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6211 (ins VR128:$src1, i32i8imm:$src2),
6212 !strconcat(OpcodeStr,
6213 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6214 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6217 let neverHasSideEffects = 1, mayStore = 1 in
6218 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6219 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6220 !strconcat(OpcodeStr,
6221 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6224 // There's an AssertZext in the way of writing the store pattern
6225 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6228 let Predicates = [HasAVX] in
6229 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6231 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6234 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6235 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6236 let isCodeGenOnly = 1, hasSideEffects = 0 in
6237 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6238 (ins VR128:$src1, i32i8imm:$src2),
6239 !strconcat(OpcodeStr,
6240 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6243 let neverHasSideEffects = 1, mayStore = 1 in
6244 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6245 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6246 !strconcat(OpcodeStr,
6247 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6250 // There's an AssertZext in the way of writing the store pattern
6251 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6254 let Predicates = [HasAVX] in
6255 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6257 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6260 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6261 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6262 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6263 (ins VR128:$src1, i32i8imm:$src2),
6264 !strconcat(OpcodeStr,
6265 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6267 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6268 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6269 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6270 !strconcat(OpcodeStr,
6271 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6272 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6273 addr:$dst)]>, OpSize;
6276 let Predicates = [HasAVX] in
6277 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6279 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6281 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6282 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6283 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6284 (ins VR128:$src1, i32i8imm:$src2),
6285 !strconcat(OpcodeStr,
6286 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6288 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6289 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6290 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6291 !strconcat(OpcodeStr,
6292 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6293 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6294 addr:$dst)]>, OpSize, REX_W;
6297 let Predicates = [HasAVX] in
6298 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6300 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6302 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6304 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6305 OpndItins itins = DEFAULT_ITINS> {
6306 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6307 (ins VR128:$src1, i32i8imm:$src2),
6308 !strconcat(OpcodeStr,
6309 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6310 [(set GR32orGR64:$dst,
6311 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6314 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6315 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6316 !strconcat(OpcodeStr,
6317 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6318 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6319 addr:$dst)], itins.rm>, OpSize;
6322 let ExeDomain = SSEPackedSingle in {
6323 let Predicates = [UseAVX] in
6324 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6325 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6328 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6329 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6332 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6334 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6337 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6338 Requires<[UseSSE41]>;
6340 //===----------------------------------------------------------------------===//
6341 // SSE4.1 - Insert Instructions
6342 //===----------------------------------------------------------------------===//
6344 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6345 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6346 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6348 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6350 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6352 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>, OpSize;
6353 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6354 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6356 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6358 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6360 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6361 imm:$src3))]>, OpSize;
6364 let Predicates = [HasAVX] in
6365 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6366 let Constraints = "$src1 = $dst" in
6367 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6369 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6370 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6371 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6373 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6375 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6377 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6379 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6380 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6382 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6384 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6386 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6387 imm:$src3)))]>, OpSize;
6390 let Predicates = [HasAVX] in
6391 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6392 let Constraints = "$src1 = $dst" in
6393 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6395 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6396 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6397 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6399 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6401 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6403 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6405 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6406 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6408 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6410 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6412 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6413 imm:$src3)))]>, OpSize;
6416 let Predicates = [HasAVX] in
6417 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6418 let Constraints = "$src1 = $dst" in
6419 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6421 // insertps has a few different modes, there's the first two here below which
6422 // are optimized inserts that won't zero arbitrary elements in the destination
6423 // vector. The next one matches the intrinsic and could zero arbitrary elements
6424 // in the target vector.
6425 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6426 OpndItins itins = DEFAULT_ITINS> {
6427 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6428 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6430 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6432 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6434 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6436 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6437 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6439 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6441 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6443 (X86insrtps VR128:$src1,
6444 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6445 imm:$src3))], itins.rm>, OpSize;
6448 let ExeDomain = SSEPackedSingle in {
6449 let Predicates = [UseAVX] in
6450 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6451 let Constraints = "$src1 = $dst" in
6452 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6455 //===----------------------------------------------------------------------===//
6456 // SSE4.1 - Round Instructions
6457 //===----------------------------------------------------------------------===//
6459 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6460 X86MemOperand x86memop, RegisterClass RC,
6461 PatFrag mem_frag32, PatFrag mem_frag64,
6462 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6463 let ExeDomain = SSEPackedSingle in {
6464 // Intrinsic operation, reg.
6465 // Vector intrinsic operation, reg
6466 def PSr : SS4AIi8<opcps, MRMSrcReg,
6467 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6468 !strconcat(OpcodeStr,
6469 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6470 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6471 IIC_SSE_ROUNDPS_REG>,
6474 // Vector intrinsic operation, mem
6475 def PSm : SS4AIi8<opcps, MRMSrcMem,
6476 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6477 !strconcat(OpcodeStr,
6478 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6480 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6481 IIC_SSE_ROUNDPS_MEM>,
6483 } // ExeDomain = SSEPackedSingle
6485 let ExeDomain = SSEPackedDouble in {
6486 // Vector intrinsic operation, reg
6487 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6488 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6489 !strconcat(OpcodeStr,
6490 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6491 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6492 IIC_SSE_ROUNDPS_REG>,
6495 // Vector intrinsic operation, mem
6496 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6497 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6498 !strconcat(OpcodeStr,
6499 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6501 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6502 IIC_SSE_ROUNDPS_REG>,
6504 } // ExeDomain = SSEPackedDouble
6507 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6510 Intrinsic F64Int, bit Is2Addr = 1> {
6511 let ExeDomain = GenericDomain in {
6513 let hasSideEffects = 0 in
6514 def SSr : SS4AIi8<opcss, MRMSrcReg,
6515 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6517 !strconcat(OpcodeStr,
6518 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6519 !strconcat(OpcodeStr,
6520 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6523 // Intrinsic operation, reg.
6524 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6525 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6527 !strconcat(OpcodeStr,
6528 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6529 !strconcat(OpcodeStr,
6530 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6531 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6534 // Intrinsic operation, mem.
6535 def SSm : SS4AIi8<opcss, MRMSrcMem,
6536 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6538 !strconcat(OpcodeStr,
6539 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6540 !strconcat(OpcodeStr,
6541 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6543 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6547 let hasSideEffects = 0 in
6548 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6549 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6551 !strconcat(OpcodeStr,
6552 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6553 !strconcat(OpcodeStr,
6554 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6557 // Intrinsic operation, reg.
6558 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6559 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6561 !strconcat(OpcodeStr,
6562 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6563 !strconcat(OpcodeStr,
6564 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6565 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6568 // Intrinsic operation, mem.
6569 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6570 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6572 !strconcat(OpcodeStr,
6573 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6574 !strconcat(OpcodeStr,
6575 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6577 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6579 } // ExeDomain = GenericDomain
6582 // FP round - roundss, roundps, roundsd, roundpd
6583 let Predicates = [HasAVX] in {
6585 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6586 loadv4f32, loadv2f64,
6587 int_x86_sse41_round_ps,
6588 int_x86_sse41_round_pd>, VEX;
6589 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6590 loadv8f32, loadv4f64,
6591 int_x86_avx_round_ps_256,
6592 int_x86_avx_round_pd_256>, VEX, VEX_L;
6593 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6594 int_x86_sse41_round_ss,
6595 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6597 def : Pat<(ffloor FR32:$src),
6598 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6599 def : Pat<(f64 (ffloor FR64:$src)),
6600 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6601 def : Pat<(f32 (fnearbyint FR32:$src)),
6602 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6603 def : Pat<(f64 (fnearbyint FR64:$src)),
6604 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6605 def : Pat<(f32 (fceil FR32:$src)),
6606 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6607 def : Pat<(f64 (fceil FR64:$src)),
6608 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6609 def : Pat<(f32 (frint FR32:$src)),
6610 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6611 def : Pat<(f64 (frint FR64:$src)),
6612 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6613 def : Pat<(f32 (ftrunc FR32:$src)),
6614 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6615 def : Pat<(f64 (ftrunc FR64:$src)),
6616 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6618 def : Pat<(v4f32 (ffloor VR128:$src)),
6619 (VROUNDPSr VR128:$src, (i32 0x1))>;
6620 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6621 (VROUNDPSr VR128:$src, (i32 0xC))>;
6622 def : Pat<(v4f32 (fceil VR128:$src)),
6623 (VROUNDPSr VR128:$src, (i32 0x2))>;
6624 def : Pat<(v4f32 (frint VR128:$src)),
6625 (VROUNDPSr VR128:$src, (i32 0x4))>;
6626 def : Pat<(v4f32 (ftrunc VR128:$src)),
6627 (VROUNDPSr VR128:$src, (i32 0x3))>;
6629 def : Pat<(v2f64 (ffloor VR128:$src)),
6630 (VROUNDPDr VR128:$src, (i32 0x1))>;
6631 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6632 (VROUNDPDr VR128:$src, (i32 0xC))>;
6633 def : Pat<(v2f64 (fceil VR128:$src)),
6634 (VROUNDPDr VR128:$src, (i32 0x2))>;
6635 def : Pat<(v2f64 (frint VR128:$src)),
6636 (VROUNDPDr VR128:$src, (i32 0x4))>;
6637 def : Pat<(v2f64 (ftrunc VR128:$src)),
6638 (VROUNDPDr VR128:$src, (i32 0x3))>;
6640 def : Pat<(v8f32 (ffloor VR256:$src)),
6641 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6642 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6643 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6644 def : Pat<(v8f32 (fceil VR256:$src)),
6645 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6646 def : Pat<(v8f32 (frint VR256:$src)),
6647 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6648 def : Pat<(v8f32 (ftrunc VR256:$src)),
6649 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6651 def : Pat<(v4f64 (ffloor VR256:$src)),
6652 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6653 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6654 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6655 def : Pat<(v4f64 (fceil VR256:$src)),
6656 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6657 def : Pat<(v4f64 (frint VR256:$src)),
6658 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6659 def : Pat<(v4f64 (ftrunc VR256:$src)),
6660 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6663 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6664 memopv4f32, memopv2f64,
6665 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6666 let Constraints = "$src1 = $dst" in
6667 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6668 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6670 let Predicates = [UseSSE41] in {
6671 def : Pat<(ffloor FR32:$src),
6672 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6673 def : Pat<(f64 (ffloor FR64:$src)),
6674 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6675 def : Pat<(f32 (fnearbyint FR32:$src)),
6676 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6677 def : Pat<(f64 (fnearbyint FR64:$src)),
6678 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6679 def : Pat<(f32 (fceil FR32:$src)),
6680 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6681 def : Pat<(f64 (fceil FR64:$src)),
6682 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6683 def : Pat<(f32 (frint FR32:$src)),
6684 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6685 def : Pat<(f64 (frint FR64:$src)),
6686 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6687 def : Pat<(f32 (ftrunc FR32:$src)),
6688 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6689 def : Pat<(f64 (ftrunc FR64:$src)),
6690 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6692 def : Pat<(v4f32 (ffloor VR128:$src)),
6693 (ROUNDPSr VR128:$src, (i32 0x1))>;
6694 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6695 (ROUNDPSr VR128:$src, (i32 0xC))>;
6696 def : Pat<(v4f32 (fceil VR128:$src)),
6697 (ROUNDPSr VR128:$src, (i32 0x2))>;
6698 def : Pat<(v4f32 (frint VR128:$src)),
6699 (ROUNDPSr VR128:$src, (i32 0x4))>;
6700 def : Pat<(v4f32 (ftrunc VR128:$src)),
6701 (ROUNDPSr VR128:$src, (i32 0x3))>;
6703 def : Pat<(v2f64 (ffloor VR128:$src)),
6704 (ROUNDPDr VR128:$src, (i32 0x1))>;
6705 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6706 (ROUNDPDr VR128:$src, (i32 0xC))>;
6707 def : Pat<(v2f64 (fceil VR128:$src)),
6708 (ROUNDPDr VR128:$src, (i32 0x2))>;
6709 def : Pat<(v2f64 (frint VR128:$src)),
6710 (ROUNDPDr VR128:$src, (i32 0x4))>;
6711 def : Pat<(v2f64 (ftrunc VR128:$src)),
6712 (ROUNDPDr VR128:$src, (i32 0x3))>;
6715 //===----------------------------------------------------------------------===//
6716 // SSE4.1 - Packed Bit Test
6717 //===----------------------------------------------------------------------===//
6719 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6720 // the intel intrinsic that corresponds to this.
6721 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6722 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6723 "vptest\t{$src2, $src1|$src1, $src2}",
6724 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6726 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6727 "vptest\t{$src2, $src1|$src1, $src2}",
6728 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6731 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6732 "vptest\t{$src2, $src1|$src1, $src2}",
6733 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6735 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6736 "vptest\t{$src2, $src1|$src1, $src2}",
6737 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6741 let Defs = [EFLAGS] in {
6742 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6743 "ptest\t{$src2, $src1|$src1, $src2}",
6744 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6746 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6747 "ptest\t{$src2, $src1|$src1, $src2}",
6748 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6752 // The bit test instructions below are AVX only
6753 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6754 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6755 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6756 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6757 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6758 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6759 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6760 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6764 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6765 let ExeDomain = SSEPackedSingle in {
6766 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6767 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6770 let ExeDomain = SSEPackedDouble in {
6771 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6772 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6777 //===----------------------------------------------------------------------===//
6778 // SSE4.1 - Misc Instructions
6779 //===----------------------------------------------------------------------===//
6781 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6782 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6783 "popcnt{w}\t{$src, $dst|$dst, $src}",
6784 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6787 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6788 "popcnt{w}\t{$src, $dst|$dst, $src}",
6789 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6790 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize, XS;
6792 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6793 "popcnt{l}\t{$src, $dst|$dst, $src}",
6794 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6797 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6798 "popcnt{l}\t{$src, $dst|$dst, $src}",
6799 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6800 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6802 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6803 "popcnt{q}\t{$src, $dst|$dst, $src}",
6804 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6807 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6808 "popcnt{q}\t{$src, $dst|$dst, $src}",
6809 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6810 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6815 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6816 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6817 Intrinsic IntId128> {
6818 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6820 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6821 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6822 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6824 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6827 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6830 let Predicates = [HasAVX] in
6831 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6832 int_x86_sse41_phminposuw>, VEX;
6833 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6834 int_x86_sse41_phminposuw>;
6836 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6837 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6838 Intrinsic IntId128, bit Is2Addr = 1,
6839 OpndItins itins = DEFAULT_ITINS> {
6840 let isCommutable = 1 in
6841 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6842 (ins VR128:$src1, VR128:$src2),
6844 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6845 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6846 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
6848 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6849 (ins VR128:$src1, i128mem:$src2),
6851 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6852 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6854 (IntId128 VR128:$src1,
6855 (bitconvert (memopv2i64 addr:$src2))))],
6859 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6860 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6861 Intrinsic IntId256> {
6862 let isCommutable = 1 in
6863 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6864 (ins VR256:$src1, VR256:$src2),
6865 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6866 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6867 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6868 (ins VR256:$src1, i256mem:$src2),
6869 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6871 (IntId256 VR256:$src1,
6872 (bitconvert (loadv4i64 addr:$src2))))]>, OpSize;
6876 /// SS48I_binop_rm - Simple SSE41 binary operator.
6877 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6878 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6879 X86MemOperand x86memop, bit Is2Addr = 1,
6880 OpndItins itins = DEFAULT_ITINS> {
6881 let isCommutable = 1 in
6882 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6883 (ins RC:$src1, RC:$src2),
6885 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6886 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6887 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6888 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6889 (ins RC:$src1, x86memop:$src2),
6891 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6892 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6894 (OpVT (OpNode RC:$src1,
6895 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6898 let Predicates = [HasAVX] in {
6899 let isCommutable = 0 in
6900 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6902 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6903 loadv2i64, i128mem, 0>, VEX_4V;
6904 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6905 loadv2i64, i128mem, 0>, VEX_4V;
6906 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6907 loadv2i64, i128mem, 0>, VEX_4V;
6908 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6909 loadv2i64, i128mem, 0>, VEX_4V;
6910 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6911 loadv2i64, i128mem, 0>, VEX_4V;
6912 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6913 loadv2i64, i128mem, 0>, VEX_4V;
6914 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6915 loadv2i64, i128mem, 0>, VEX_4V;
6916 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6917 loadv2i64, i128mem, 0>, VEX_4V;
6918 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6922 let Predicates = [HasAVX2] in {
6923 let isCommutable = 0 in
6924 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6925 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6926 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6927 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6928 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6929 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6930 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6931 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6932 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6933 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6934 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6935 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6936 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6937 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6938 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6939 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6940 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6941 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6942 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6943 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6946 let Constraints = "$src1 = $dst" in {
6947 let isCommutable = 0 in
6948 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6949 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6950 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6951 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6952 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6953 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6954 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6955 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6956 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6957 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6958 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6959 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6960 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6961 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6962 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6963 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6964 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6965 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq,
6966 1, SSE_INTMUL_ITINS_P>;
6969 let Predicates = [HasAVX] in {
6970 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6971 memopv2i64, i128mem, 0>, VEX_4V;
6972 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6973 memopv2i64, i128mem, 0>, VEX_4V;
6975 let Predicates = [HasAVX2] in {
6976 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6977 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6978 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6979 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6982 let Constraints = "$src1 = $dst" in {
6983 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6984 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6985 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6986 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6989 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6990 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6991 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6992 X86MemOperand x86memop, bit Is2Addr = 1,
6993 OpndItins itins = DEFAULT_ITINS> {
6994 let isCommutable = 1 in
6995 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6996 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6998 !strconcat(OpcodeStr,
6999 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7000 !strconcat(OpcodeStr,
7001 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7002 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7004 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7005 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7007 !strconcat(OpcodeStr,
7008 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7009 !strconcat(OpcodeStr,
7010 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7013 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7017 let Predicates = [HasAVX] in {
7018 let isCommutable = 0 in {
7019 let ExeDomain = SSEPackedSingle in {
7020 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7021 VR128, loadv4f32, f128mem, 0>, VEX_4V;
7022 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7023 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7024 f256mem, 0>, VEX_4V, VEX_L;
7026 let ExeDomain = SSEPackedDouble in {
7027 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7028 VR128, loadv2f64, f128mem, 0>, VEX_4V;
7029 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7030 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7031 f256mem, 0>, VEX_4V, VEX_L;
7033 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7034 VR128, loadv2i64, i128mem, 0>, VEX_4V;
7035 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7036 VR128, loadv2i64, i128mem, 0>, VEX_4V;
7038 let ExeDomain = SSEPackedSingle in
7039 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7040 VR128, loadv4f32, f128mem, 0>, VEX_4V;
7041 let ExeDomain = SSEPackedDouble in
7042 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7043 VR128, loadv2f64, f128mem, 0>, VEX_4V;
7044 let ExeDomain = SSEPackedSingle in
7045 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7046 VR256, loadv8f32, i256mem, 0>, VEX_4V, VEX_L;
7049 let Predicates = [HasAVX2] in {
7050 let isCommutable = 0 in {
7051 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7052 VR256, loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7053 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7054 VR256, loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7058 let Constraints = "$src1 = $dst" in {
7059 let isCommutable = 0 in {
7060 let ExeDomain = SSEPackedSingle in
7061 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7062 VR128, memopv4f32, f128mem,
7063 1, SSE_INTALU_ITINS_P>;
7064 let ExeDomain = SSEPackedDouble in
7065 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7066 VR128, memopv2f64, f128mem,
7067 1, SSE_INTALU_ITINS_P>;
7068 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7069 VR128, memopv2i64, i128mem,
7070 1, SSE_INTALU_ITINS_P>;
7071 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7072 VR128, memopv2i64, i128mem,
7073 1, SSE_INTMUL_ITINS_P>;
7075 let ExeDomain = SSEPackedSingle in
7076 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7077 VR128, memopv4f32, f128mem, 1,
7079 let ExeDomain = SSEPackedDouble in
7080 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7081 VR128, memopv2f64, f128mem, 1,
7085 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7086 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7087 RegisterClass RC, X86MemOperand x86memop,
7088 PatFrag mem_frag, Intrinsic IntId> {
7089 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7090 (ins RC:$src1, RC:$src2, RC:$src3),
7091 !strconcat(OpcodeStr,
7092 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7093 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7094 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
7096 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7097 (ins RC:$src1, x86memop:$src2, RC:$src3),
7098 !strconcat(OpcodeStr,
7099 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7101 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7103 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
7106 let Predicates = [HasAVX] in {
7107 let ExeDomain = SSEPackedDouble in {
7108 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7109 loadv2f64, int_x86_sse41_blendvpd>;
7110 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7111 loadv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
7112 } // ExeDomain = SSEPackedDouble
7113 let ExeDomain = SSEPackedSingle in {
7114 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7115 loadv4f32, int_x86_sse41_blendvps>;
7116 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7117 loadv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
7118 } // ExeDomain = SSEPackedSingle
7119 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7120 loadv2i64, int_x86_sse41_pblendvb>;
7123 let Predicates = [HasAVX2] in {
7124 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7125 loadv4i64, int_x86_avx2_pblendvb>, VEX_L;
7128 let Predicates = [HasAVX] in {
7129 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7130 (v16i8 VR128:$src2))),
7131 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7132 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7133 (v4i32 VR128:$src2))),
7134 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7135 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7136 (v4f32 VR128:$src2))),
7137 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7138 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7139 (v2i64 VR128:$src2))),
7140 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7141 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7142 (v2f64 VR128:$src2))),
7143 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7144 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7145 (v8i32 VR256:$src2))),
7146 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7147 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7148 (v8f32 VR256:$src2))),
7149 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7150 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7151 (v4i64 VR256:$src2))),
7152 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7153 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7154 (v4f64 VR256:$src2))),
7155 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7157 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7159 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7160 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7162 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7164 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7166 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7167 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7169 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7170 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7172 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7175 let Predicates = [HasAVX2] in {
7176 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7177 (v32i8 VR256:$src2))),
7178 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7179 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7181 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7184 /// SS41I_ternary_int - SSE 4.1 ternary operator
7185 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7186 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7187 X86MemOperand x86memop, Intrinsic IntId,
7188 OpndItins itins = DEFAULT_ITINS> {
7189 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7190 (ins VR128:$src1, VR128:$src2),
7191 !strconcat(OpcodeStr,
7192 "\t{$src2, $dst|$dst, $src2}"),
7193 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7196 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7197 (ins VR128:$src1, x86memop:$src2),
7198 !strconcat(OpcodeStr,
7199 "\t{$src2, $dst|$dst, $src2}"),
7202 (bitconvert (mem_frag addr:$src2)), XMM0))],
7207 let ExeDomain = SSEPackedDouble in
7208 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7209 int_x86_sse41_blendvpd>;
7210 let ExeDomain = SSEPackedSingle in
7211 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7212 int_x86_sse41_blendvps>;
7213 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7214 int_x86_sse41_pblendvb>;
7216 // Aliases with the implicit xmm0 argument
7217 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7218 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7219 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7220 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7221 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7222 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7223 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7224 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7225 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7226 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7227 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7228 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7230 let Predicates = [UseSSE41] in {
7231 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7232 (v16i8 VR128:$src2))),
7233 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7234 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7235 (v4i32 VR128:$src2))),
7236 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7237 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7238 (v4f32 VR128:$src2))),
7239 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7240 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7241 (v2i64 VR128:$src2))),
7242 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7243 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7244 (v2f64 VR128:$src2))),
7245 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7247 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7249 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7250 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7252 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7253 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7255 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7259 let Predicates = [HasAVX] in
7260 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7261 "vmovntdqa\t{$src, $dst|$dst, $src}",
7262 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7264 let Predicates = [HasAVX2] in
7265 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7266 "vmovntdqa\t{$src, $dst|$dst, $src}",
7267 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7269 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7270 "movntdqa\t{$src, $dst|$dst, $src}",
7271 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7274 //===----------------------------------------------------------------------===//
7275 // SSE4.2 - Compare Instructions
7276 //===----------------------------------------------------------------------===//
7278 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7279 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7280 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7281 X86MemOperand x86memop, bit Is2Addr = 1> {
7282 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7283 (ins RC:$src1, RC:$src2),
7285 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7286 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7287 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7289 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7290 (ins RC:$src1, x86memop:$src2),
7292 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7293 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7295 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7298 let Predicates = [HasAVX] in
7299 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7300 loadv2i64, i128mem, 0>, VEX_4V;
7302 let Predicates = [HasAVX2] in
7303 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7304 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7306 let Constraints = "$src1 = $dst" in
7307 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7308 memopv2i64, i128mem>;
7310 //===----------------------------------------------------------------------===//
7311 // SSE4.2 - String/text Processing Instructions
7312 //===----------------------------------------------------------------------===//
7314 // Packed Compare Implicit Length Strings, Return Mask
7315 multiclass pseudo_pcmpistrm<string asm> {
7316 def REG : PseudoI<(outs VR128:$dst),
7317 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7318 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7320 def MEM : PseudoI<(outs VR128:$dst),
7321 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7322 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7323 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7326 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7327 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7328 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7331 multiclass pcmpistrm_SS42AI<string asm> {
7332 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7333 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7334 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7337 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7338 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7339 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7343 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7344 let Predicates = [HasAVX] in
7345 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7346 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7349 // Packed Compare Explicit Length Strings, Return Mask
7350 multiclass pseudo_pcmpestrm<string asm> {
7351 def REG : PseudoI<(outs VR128:$dst),
7352 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7353 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7354 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7355 def MEM : PseudoI<(outs VR128:$dst),
7356 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7357 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7358 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7361 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7362 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7363 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7366 multiclass SS42AI_pcmpestrm<string asm> {
7367 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7368 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7369 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7372 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7373 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7374 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7378 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7379 let Predicates = [HasAVX] in
7380 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7381 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7384 // Packed Compare Implicit Length Strings, Return Index
7385 multiclass pseudo_pcmpistri<string asm> {
7386 def REG : PseudoI<(outs GR32:$dst),
7387 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7388 [(set GR32:$dst, EFLAGS,
7389 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7390 def MEM : PseudoI<(outs GR32:$dst),
7391 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7392 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7393 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7396 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7397 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7398 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7401 multiclass SS42AI_pcmpistri<string asm> {
7402 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7403 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7404 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7407 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7408 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7409 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7413 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7414 let Predicates = [HasAVX] in
7415 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7416 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7419 // Packed Compare Explicit Length Strings, Return Index
7420 multiclass pseudo_pcmpestri<string asm> {
7421 def REG : PseudoI<(outs GR32:$dst),
7422 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7423 [(set GR32:$dst, EFLAGS,
7424 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7425 def MEM : PseudoI<(outs GR32:$dst),
7426 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7427 [(set GR32:$dst, EFLAGS,
7428 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7432 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7433 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7434 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7437 multiclass SS42AI_pcmpestri<string asm> {
7438 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7439 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7440 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7443 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7444 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7445 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7449 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7450 let Predicates = [HasAVX] in
7451 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7452 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7455 //===----------------------------------------------------------------------===//
7456 // SSE4.2 - CRC Instructions
7457 //===----------------------------------------------------------------------===//
7459 // No CRC instructions have AVX equivalents
7461 // crc intrinsic instruction
7462 // This set of instructions are only rm, the only difference is the size
7464 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7465 RegisterClass RCIn, SDPatternOperator Int> :
7466 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7467 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7468 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>;
7470 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7471 X86MemOperand x86memop, SDPatternOperator Int> :
7472 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7473 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7474 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7477 let Constraints = "$src1 = $dst" in {
7478 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7479 int_x86_sse42_crc32_32_8>;
7480 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7481 int_x86_sse42_crc32_32_8>;
7482 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7483 int_x86_sse42_crc32_32_16>, OpSize;
7484 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7485 int_x86_sse42_crc32_32_16>, OpSize;
7486 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7487 int_x86_sse42_crc32_32_32>;
7488 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7489 int_x86_sse42_crc32_32_32>;
7490 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7491 int_x86_sse42_crc32_64_64>, REX_W;
7492 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7493 int_x86_sse42_crc32_64_64>, REX_W;
7494 let hasSideEffects = 0 in {
7496 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7498 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7503 //===----------------------------------------------------------------------===//
7504 // SHA-NI Instructions
7505 //===----------------------------------------------------------------------===//
7507 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7509 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7510 (ins VR128:$src1, VR128:$src2),
7511 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7513 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7514 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7516 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7517 (ins VR128:$src1, i128mem:$src2),
7518 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7520 (set VR128:$dst, (IntId VR128:$src1,
7521 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7522 (set VR128:$dst, (IntId VR128:$src1,
7523 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7526 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7527 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7528 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7529 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7531 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7532 (i8 imm:$src3)))]>, TA;
7533 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7534 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7535 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7537 (int_x86_sha1rnds4 VR128:$src1,
7538 (bc_v4i32 (memopv2i64 addr:$src2)),
7539 (i8 imm:$src3)))]>, TA;
7541 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7542 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7543 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7546 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7548 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7549 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7552 // Aliases with explicit %xmm0
7553 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7554 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7555 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7556 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7558 //===----------------------------------------------------------------------===//
7559 // AES-NI Instructions
7560 //===----------------------------------------------------------------------===//
7562 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7563 Intrinsic IntId128, bit Is2Addr = 1> {
7564 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7565 (ins VR128:$src1, VR128:$src2),
7567 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7568 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7569 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7571 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7572 (ins VR128:$src1, i128mem:$src2),
7574 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7575 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7577 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7580 // Perform One Round of an AES Encryption/Decryption Flow
7581 let Predicates = [HasAVX, HasAES] in {
7582 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7583 int_x86_aesni_aesenc, 0>, VEX_4V;
7584 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7585 int_x86_aesni_aesenclast, 0>, VEX_4V;
7586 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7587 int_x86_aesni_aesdec, 0>, VEX_4V;
7588 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7589 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7592 let Constraints = "$src1 = $dst" in {
7593 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7594 int_x86_aesni_aesenc>;
7595 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7596 int_x86_aesni_aesenclast>;
7597 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7598 int_x86_aesni_aesdec>;
7599 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7600 int_x86_aesni_aesdeclast>;
7603 // Perform the AES InvMixColumn Transformation
7604 let Predicates = [HasAVX, HasAES] in {
7605 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7607 "vaesimc\t{$src1, $dst|$dst, $src1}",
7609 (int_x86_aesni_aesimc VR128:$src1))]>,
7611 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7612 (ins i128mem:$src1),
7613 "vaesimc\t{$src1, $dst|$dst, $src1}",
7614 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7617 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7619 "aesimc\t{$src1, $dst|$dst, $src1}",
7621 (int_x86_aesni_aesimc VR128:$src1))]>,
7623 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7624 (ins i128mem:$src1),
7625 "aesimc\t{$src1, $dst|$dst, $src1}",
7626 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7629 // AES Round Key Generation Assist
7630 let Predicates = [HasAVX, HasAES] in {
7631 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7632 (ins VR128:$src1, i8imm:$src2),
7633 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7635 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7637 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7638 (ins i128mem:$src1, i8imm:$src2),
7639 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7641 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7644 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7645 (ins VR128:$src1, i8imm:$src2),
7646 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7648 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7650 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7651 (ins i128mem:$src1, i8imm:$src2),
7652 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7654 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7657 //===----------------------------------------------------------------------===//
7658 // PCLMUL Instructions
7659 //===----------------------------------------------------------------------===//
7661 // AVX carry-less Multiplication instructions
7662 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7663 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7664 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7666 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7668 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7669 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7670 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7671 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7672 (loadv2i64 addr:$src2), imm:$src3))]>;
7674 // Carry-less Multiplication instructions
7675 let Constraints = "$src1 = $dst" in {
7676 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7677 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7678 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7680 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7681 IIC_SSE_PCLMULQDQ_RR>;
7683 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7684 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7685 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7686 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7687 (memopv2i64 addr:$src2), imm:$src3))],
7688 IIC_SSE_PCLMULQDQ_RM>;
7689 } // Constraints = "$src1 = $dst"
7692 multiclass pclmul_alias<string asm, int immop> {
7693 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7694 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7696 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7697 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7699 def : InstAlias<!strconcat("vpclmul", asm,
7700 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7701 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7703 def : InstAlias<!strconcat("vpclmul", asm,
7704 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7705 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7707 defm : pclmul_alias<"hqhq", 0x11>;
7708 defm : pclmul_alias<"hqlq", 0x01>;
7709 defm : pclmul_alias<"lqhq", 0x10>;
7710 defm : pclmul_alias<"lqlq", 0x00>;
7712 //===----------------------------------------------------------------------===//
7713 // SSE4A Instructions
7714 //===----------------------------------------------------------------------===//
7716 let Predicates = [HasSSE4A] in {
7718 let Constraints = "$src = $dst" in {
7719 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7720 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7721 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7722 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7723 imm:$idx))]>, TB, OpSize;
7724 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7725 (ins VR128:$src, VR128:$mask),
7726 "extrq\t{$mask, $src|$src, $mask}",
7727 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7728 VR128:$mask))]>, TB, OpSize;
7730 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7731 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7732 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7733 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7734 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7735 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7736 (ins VR128:$src, VR128:$mask),
7737 "insertq\t{$mask, $src|$src, $mask}",
7738 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7739 VR128:$mask))]>, XD;
7742 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7743 "movntss\t{$src, $dst|$dst, $src}",
7744 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7746 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7747 "movntsd\t{$src, $dst|$dst, $src}",
7748 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7751 //===----------------------------------------------------------------------===//
7753 //===----------------------------------------------------------------------===//
7755 //===----------------------------------------------------------------------===//
7756 // VBROADCAST - Load from memory and broadcast to all elements of the
7757 // destination operand
7759 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7760 X86MemOperand x86memop, Intrinsic Int> :
7761 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7763 [(set RC:$dst, (Int addr:$src))]>, VEX;
7765 // AVX2 adds register forms
7766 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7768 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7769 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7770 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7772 let ExeDomain = SSEPackedSingle in {
7773 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7774 int_x86_avx_vbroadcast_ss>;
7775 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7776 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7778 let ExeDomain = SSEPackedDouble in
7779 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7780 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7781 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7782 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7784 let ExeDomain = SSEPackedSingle in {
7785 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7786 int_x86_avx2_vbroadcast_ss_ps>;
7787 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7788 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7790 let ExeDomain = SSEPackedDouble in
7791 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7792 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7794 let Predicates = [HasAVX2] in
7795 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7796 int_x86_avx2_vbroadcasti128>, VEX_L;
7798 let Predicates = [HasAVX] in
7799 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7800 (VBROADCASTF128 addr:$src)>;
7803 //===----------------------------------------------------------------------===//
7804 // VINSERTF128 - Insert packed floating-point values
7806 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7807 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7808 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7809 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7812 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7813 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7814 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7818 let Predicates = [HasAVX] in {
7819 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7821 (VINSERTF128rr VR256:$src1, VR128:$src2,
7822 (INSERT_get_vinsert128_imm VR256:$ins))>;
7823 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7825 (VINSERTF128rr VR256:$src1, VR128:$src2,
7826 (INSERT_get_vinsert128_imm VR256:$ins))>;
7828 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7830 (VINSERTF128rm VR256:$src1, addr:$src2,
7831 (INSERT_get_vinsert128_imm VR256:$ins))>;
7832 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7834 (VINSERTF128rm VR256:$src1, addr:$src2,
7835 (INSERT_get_vinsert128_imm VR256:$ins))>;
7838 let Predicates = [HasAVX1Only] in {
7839 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7841 (VINSERTF128rr VR256:$src1, VR128:$src2,
7842 (INSERT_get_vinsert128_imm VR256:$ins))>;
7843 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7845 (VINSERTF128rr VR256:$src1, VR128:$src2,
7846 (INSERT_get_vinsert128_imm VR256:$ins))>;
7847 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7849 (VINSERTF128rr VR256:$src1, VR128:$src2,
7850 (INSERT_get_vinsert128_imm VR256:$ins))>;
7851 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7853 (VINSERTF128rr VR256:$src1, VR128:$src2,
7854 (INSERT_get_vinsert128_imm VR256:$ins))>;
7856 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7858 (VINSERTF128rm VR256:$src1, addr:$src2,
7859 (INSERT_get_vinsert128_imm VR256:$ins))>;
7860 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7861 (bc_v4i32 (loadv2i64 addr:$src2)),
7863 (VINSERTF128rm VR256:$src1, addr:$src2,
7864 (INSERT_get_vinsert128_imm VR256:$ins))>;
7865 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7866 (bc_v16i8 (loadv2i64 addr:$src2)),
7868 (VINSERTF128rm VR256:$src1, addr:$src2,
7869 (INSERT_get_vinsert128_imm VR256:$ins))>;
7870 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7871 (bc_v8i16 (loadv2i64 addr:$src2)),
7873 (VINSERTF128rm VR256:$src1, addr:$src2,
7874 (INSERT_get_vinsert128_imm VR256:$ins))>;
7877 //===----------------------------------------------------------------------===//
7878 // VEXTRACTF128 - Extract packed floating-point values
7880 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7881 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7882 (ins VR256:$src1, i8imm:$src2),
7883 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7886 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7887 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7888 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7893 let Predicates = [HasAVX] in {
7894 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7895 (v4f32 (VEXTRACTF128rr
7896 (v8f32 VR256:$src1),
7897 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7898 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7899 (v2f64 (VEXTRACTF128rr
7900 (v4f64 VR256:$src1),
7901 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7903 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7904 (iPTR imm))), addr:$dst),
7905 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7906 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7907 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7908 (iPTR imm))), addr:$dst),
7909 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7910 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7913 let Predicates = [HasAVX1Only] in {
7914 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7915 (v2i64 (VEXTRACTF128rr
7916 (v4i64 VR256:$src1),
7917 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7918 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7919 (v4i32 (VEXTRACTF128rr
7920 (v8i32 VR256:$src1),
7921 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7922 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7923 (v8i16 (VEXTRACTF128rr
7924 (v16i16 VR256:$src1),
7925 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7926 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7927 (v16i8 (VEXTRACTF128rr
7928 (v32i8 VR256:$src1),
7929 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7931 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7932 (iPTR imm))), addr:$dst),
7933 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7934 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7935 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7936 (iPTR imm))), addr:$dst),
7937 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7938 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7939 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7940 (iPTR imm))), addr:$dst),
7941 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7942 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7943 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7944 (iPTR imm))), addr:$dst),
7945 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7946 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7949 //===----------------------------------------------------------------------===//
7950 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7952 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7953 Intrinsic IntLd, Intrinsic IntLd256,
7954 Intrinsic IntSt, Intrinsic IntSt256> {
7955 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7956 (ins VR128:$src1, f128mem:$src2),
7957 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7958 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7960 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7961 (ins VR256:$src1, f256mem:$src2),
7962 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7963 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7965 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7966 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7967 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7968 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7969 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7970 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7971 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7972 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7975 let ExeDomain = SSEPackedSingle in
7976 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7977 int_x86_avx_maskload_ps,
7978 int_x86_avx_maskload_ps_256,
7979 int_x86_avx_maskstore_ps,
7980 int_x86_avx_maskstore_ps_256>;
7981 let ExeDomain = SSEPackedDouble in
7982 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7983 int_x86_avx_maskload_pd,
7984 int_x86_avx_maskload_pd_256,
7985 int_x86_avx_maskstore_pd,
7986 int_x86_avx_maskstore_pd_256>;
7988 //===----------------------------------------------------------------------===//
7989 // VPERMIL - Permute Single and Double Floating-Point Values
7991 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7992 RegisterClass RC, X86MemOperand x86memop_f,
7993 X86MemOperand x86memop_i, PatFrag i_frag,
7994 Intrinsic IntVar, ValueType vt> {
7995 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7996 (ins RC:$src1, RC:$src2),
7997 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7998 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7999 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8000 (ins RC:$src1, x86memop_i:$src2),
8001 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8002 [(set RC:$dst, (IntVar RC:$src1,
8003 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
8005 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8006 (ins RC:$src1, i8imm:$src2),
8007 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8008 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
8009 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8010 (ins x86memop_f:$src1, i8imm:$src2),
8011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8013 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
8016 let ExeDomain = SSEPackedSingle in {
8017 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8018 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8019 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8020 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8022 let ExeDomain = SSEPackedDouble in {
8023 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8024 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8025 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8026 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8029 let Predicates = [HasAVX] in {
8030 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
8031 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8032 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
8033 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8034 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (loadv4i64 addr:$src1)),
8036 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8037 def : Pat<(v4i64 (X86VPermilp (loadv4i64 addr:$src1), (i8 imm:$imm))),
8038 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8040 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
8041 (VPERMILPDri VR128:$src1, imm:$imm)>;
8042 def : Pat<(v2i64 (X86VPermilp (loadv2i64 addr:$src1), (i8 imm:$imm))),
8043 (VPERMILPDmi addr:$src1, imm:$imm)>;
8046 //===----------------------------------------------------------------------===//
8047 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8049 let ExeDomain = SSEPackedSingle in {
8050 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8051 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8052 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8053 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8054 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8055 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8056 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8057 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8058 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8059 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8062 let Predicates = [HasAVX] in {
8063 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8064 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8065 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8066 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8067 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8070 let Predicates = [HasAVX1Only] in {
8071 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8072 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8073 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8074 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8075 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8076 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8077 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8078 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8080 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8081 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8082 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8083 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8084 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8085 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8086 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8087 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8088 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8089 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8090 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8091 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8094 //===----------------------------------------------------------------------===//
8095 // VZERO - Zero YMM registers
8097 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8098 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8099 // Zero All YMM registers
8100 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8101 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
8103 // Zero Upper bits of YMM registers
8104 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8105 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
8108 //===----------------------------------------------------------------------===//
8109 // Half precision conversion instructions
8110 //===----------------------------------------------------------------------===//
8111 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8112 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8113 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8114 [(set RC:$dst, (Int VR128:$src))]>,
8116 let neverHasSideEffects = 1, mayLoad = 1 in
8117 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8118 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
8121 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8122 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8123 (ins RC:$src1, i32i8imm:$src2),
8124 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8125 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8127 let neverHasSideEffects = 1, mayStore = 1 in
8128 def mr : Ii8<0x1D, MRMDestMem, (outs),
8129 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8130 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8134 let Predicates = [HasF16C] in {
8135 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8136 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8137 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8138 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8141 //===----------------------------------------------------------------------===//
8142 // AVX2 Instructions
8143 //===----------------------------------------------------------------------===//
8145 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8146 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8147 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8148 X86MemOperand x86memop> {
8149 let isCommutable = 1 in
8150 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8151 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
8152 !strconcat(OpcodeStr,
8153 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8154 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8156 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8157 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
8158 !strconcat(OpcodeStr,
8159 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8162 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8166 let isCommutable = 0 in {
8167 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8168 VR128, loadv2i64, i128mem>;
8169 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8170 VR256, loadv4i64, i256mem>, VEX_L;
8173 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8175 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8176 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8178 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8180 //===----------------------------------------------------------------------===//
8181 // VPBROADCAST - Load from memory and broadcast to all elements of the
8182 // destination operand
8184 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8185 X86MemOperand x86memop, PatFrag ld_frag,
8186 Intrinsic Int128, Intrinsic Int256> {
8187 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8188 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8189 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
8190 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8191 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8193 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
8194 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8195 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8196 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
8197 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8198 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8200 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8204 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8205 int_x86_avx2_pbroadcastb_128,
8206 int_x86_avx2_pbroadcastb_256>;
8207 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8208 int_x86_avx2_pbroadcastw_128,
8209 int_x86_avx2_pbroadcastw_256>;
8210 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8211 int_x86_avx2_pbroadcastd_128,
8212 int_x86_avx2_pbroadcastd_256>;
8213 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8214 int_x86_avx2_pbroadcastq_128,
8215 int_x86_avx2_pbroadcastq_256>;
8217 let Predicates = [HasAVX2] in {
8218 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8219 (VPBROADCASTBrm addr:$src)>;
8220 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8221 (VPBROADCASTBYrm addr:$src)>;
8222 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8223 (VPBROADCASTWrm addr:$src)>;
8224 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8225 (VPBROADCASTWYrm addr:$src)>;
8226 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8227 (VPBROADCASTDrm addr:$src)>;
8228 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8229 (VPBROADCASTDYrm addr:$src)>;
8230 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8231 (VPBROADCASTQrm addr:$src)>;
8232 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8233 (VPBROADCASTQYrm addr:$src)>;
8235 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8236 (VPBROADCASTBrr VR128:$src)>;
8237 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8238 (VPBROADCASTBYrr VR128:$src)>;
8239 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8240 (VPBROADCASTWrr VR128:$src)>;
8241 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8242 (VPBROADCASTWYrr VR128:$src)>;
8243 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8244 (VPBROADCASTDrr VR128:$src)>;
8245 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8246 (VPBROADCASTDYrr VR128:$src)>;
8247 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8248 (VPBROADCASTQrr VR128:$src)>;
8249 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8250 (VPBROADCASTQYrr VR128:$src)>;
8251 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8252 (VBROADCASTSSrr VR128:$src)>;
8253 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8254 (VBROADCASTSSYrr VR128:$src)>;
8255 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8256 (VPBROADCASTQrr VR128:$src)>;
8257 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8258 (VBROADCASTSDYrr VR128:$src)>;
8260 // Provide fallback in case the load node that is used in the patterns above
8261 // is used by additional users, which prevents the pattern selection.
8262 let AddedComplexity = 20 in {
8263 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8264 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8265 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8266 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8267 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8268 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8270 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8271 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8272 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8273 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8274 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8275 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8279 // AVX1 broadcast patterns
8280 let Predicates = [HasAVX1Only] in {
8281 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8282 (VBROADCASTSSYrm addr:$src)>;
8283 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8284 (VBROADCASTSDYrm addr:$src)>;
8285 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8286 (VBROADCASTSSrm addr:$src)>;
8289 let Predicates = [HasAVX] in {
8290 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8291 (VBROADCASTSSYrm addr:$src)>;
8292 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8293 (VBROADCASTSDYrm addr:$src)>;
8294 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8295 (VBROADCASTSSrm addr:$src)>;
8297 // Provide fallback in case the load node that is used in the patterns above
8298 // is used by additional users, which prevents the pattern selection.
8299 let AddedComplexity = 20 in {
8300 // 128bit broadcasts:
8301 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8302 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8303 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8304 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8305 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8306 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8307 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8308 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8309 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8310 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8312 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8313 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8314 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8315 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8316 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8317 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8318 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8319 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8320 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8321 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8325 //===----------------------------------------------------------------------===//
8326 // VPERM - Permute instructions
8329 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8331 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8332 (ins VR256:$src1, VR256:$src2),
8333 !strconcat(OpcodeStr,
8334 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8336 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8338 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8339 (ins VR256:$src1, i256mem:$src2),
8340 !strconcat(OpcodeStr,
8341 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8343 (OpVT (X86VPermv VR256:$src1,
8344 (bitconvert (mem_frag addr:$src2)))))]>,
8348 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32>;
8349 let ExeDomain = SSEPackedSingle in
8350 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32>;
8352 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8354 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8355 (ins VR256:$src1, i8imm:$src2),
8356 !strconcat(OpcodeStr,
8357 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8359 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8361 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8362 (ins i256mem:$src1, i8imm:$src2),
8363 !strconcat(OpcodeStr,
8364 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8366 (OpVT (X86VPermi (mem_frag addr:$src1),
8367 (i8 imm:$src2))))]>, VEX, VEX_L;
8370 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64>, VEX_W;
8371 let ExeDomain = SSEPackedDouble in
8372 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64>, VEX_W;
8374 //===----------------------------------------------------------------------===//
8375 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8377 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8378 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8379 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8380 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8381 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8382 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8383 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8384 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8385 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8386 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8388 let Predicates = [HasAVX2] in {
8389 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8390 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8391 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8392 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8393 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8394 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8396 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8398 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8399 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8400 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8401 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8402 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8404 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8408 //===----------------------------------------------------------------------===//
8409 // VINSERTI128 - Insert packed integer values
8411 let neverHasSideEffects = 1 in {
8412 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8413 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8414 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8417 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8418 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8419 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8423 let Predicates = [HasAVX2] in {
8424 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8426 (VINSERTI128rr VR256:$src1, VR128:$src2,
8427 (INSERT_get_vinsert128_imm VR256:$ins))>;
8428 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8430 (VINSERTI128rr VR256:$src1, VR128:$src2,
8431 (INSERT_get_vinsert128_imm VR256:$ins))>;
8432 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8434 (VINSERTI128rr VR256:$src1, VR128:$src2,
8435 (INSERT_get_vinsert128_imm VR256:$ins))>;
8436 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8438 (VINSERTI128rr VR256:$src1, VR128:$src2,
8439 (INSERT_get_vinsert128_imm VR256:$ins))>;
8441 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8443 (VINSERTI128rm VR256:$src1, addr:$src2,
8444 (INSERT_get_vinsert128_imm VR256:$ins))>;
8445 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8446 (bc_v4i32 (loadv2i64 addr:$src2)),
8448 (VINSERTI128rm VR256:$src1, addr:$src2,
8449 (INSERT_get_vinsert128_imm VR256:$ins))>;
8450 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8451 (bc_v16i8 (loadv2i64 addr:$src2)),
8453 (VINSERTI128rm VR256:$src1, addr:$src2,
8454 (INSERT_get_vinsert128_imm VR256:$ins))>;
8455 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8456 (bc_v8i16 (loadv2i64 addr:$src2)),
8458 (VINSERTI128rm VR256:$src1, addr:$src2,
8459 (INSERT_get_vinsert128_imm VR256:$ins))>;
8462 //===----------------------------------------------------------------------===//
8463 // VEXTRACTI128 - Extract packed integer values
8465 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8466 (ins VR256:$src1, i8imm:$src2),
8467 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8469 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8471 let neverHasSideEffects = 1, mayStore = 1 in
8472 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8473 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8474 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8477 let Predicates = [HasAVX2] in {
8478 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8479 (v2i64 (VEXTRACTI128rr
8480 (v4i64 VR256:$src1),
8481 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8482 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8483 (v4i32 (VEXTRACTI128rr
8484 (v8i32 VR256:$src1),
8485 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8486 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8487 (v8i16 (VEXTRACTI128rr
8488 (v16i16 VR256:$src1),
8489 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8490 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8491 (v16i8 (VEXTRACTI128rr
8492 (v32i8 VR256:$src1),
8493 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8495 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8496 (iPTR imm))), addr:$dst),
8497 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8498 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8499 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8500 (iPTR imm))), addr:$dst),
8501 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8502 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8503 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8504 (iPTR imm))), addr:$dst),
8505 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8506 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8507 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8508 (iPTR imm))), addr:$dst),
8509 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8510 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8513 //===----------------------------------------------------------------------===//
8514 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8516 multiclass avx2_pmovmask<string OpcodeStr,
8517 Intrinsic IntLd128, Intrinsic IntLd256,
8518 Intrinsic IntSt128, Intrinsic IntSt256> {
8519 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8520 (ins VR128:$src1, i128mem:$src2),
8521 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8522 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8523 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8524 (ins VR256:$src1, i256mem:$src2),
8525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8526 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8528 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8529 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8530 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8531 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8532 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8533 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8534 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8535 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8538 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8539 int_x86_avx2_maskload_d,
8540 int_x86_avx2_maskload_d_256,
8541 int_x86_avx2_maskstore_d,
8542 int_x86_avx2_maskstore_d_256>;
8543 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8544 int_x86_avx2_maskload_q,
8545 int_x86_avx2_maskload_q_256,
8546 int_x86_avx2_maskstore_q,
8547 int_x86_avx2_maskstore_q_256>, VEX_W;
8550 //===----------------------------------------------------------------------===//
8551 // Variable Bit Shifts
8553 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8554 ValueType vt128, ValueType vt256> {
8555 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8556 (ins VR128:$src1, VR128:$src2),
8557 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8559 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8561 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8562 (ins VR128:$src1, i128mem:$src2),
8563 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8565 (vt128 (OpNode VR128:$src1,
8566 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8568 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8569 (ins VR256:$src1, VR256:$src2),
8570 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8572 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8574 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8575 (ins VR256:$src1, i256mem:$src2),
8576 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8578 (vt256 (OpNode VR256:$src1,
8579 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8583 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8584 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8585 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8586 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8587 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8589 //===----------------------------------------------------------------------===//
8590 // VGATHER - GATHER Operations
8591 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8592 X86MemOperand memop128, X86MemOperand memop256> {
8593 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8594 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8595 !strconcat(OpcodeStr,
8596 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8598 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8599 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8600 !strconcat(OpcodeStr,
8601 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8602 []>, VEX_4VOp3, VEX_L;
8605 let mayLoad = 1, Constraints
8606 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8608 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8609 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8610 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8611 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8612 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8613 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8614 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8615 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;