1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 let isCommutable = 1, hasSideEffects = 0 in
208 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
210 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
211 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
212 pat_rr, IIC_DEFAULT, d>;
213 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
215 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
216 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
217 pat_rm, IIC_DEFAULT, d>;
220 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
221 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
222 string asm, string SSEVer, string FPSizeStr,
223 X86MemOperand x86memop, PatFrag mem_frag,
224 Domain d, OpndItins itins, bit Is2Addr = 1> {
225 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
227 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
228 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
229 [(set RC:$dst, (!cast<Intrinsic>(
230 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
231 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
232 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
234 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
235 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
236 [(set RC:$dst, (!cast<Intrinsic>(
237 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
238 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
241 //===----------------------------------------------------------------------===//
242 // Non-instruction patterns
243 //===----------------------------------------------------------------------===//
245 // A vector extract of the first f32/f64 position is a subregister copy
246 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
247 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
248 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
249 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
251 // A 128-bit subvector extract from the first 256-bit vector position
252 // is a subregister copy that needs no instruction.
253 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
254 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
255 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
256 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
258 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
259 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
260 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
261 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
263 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
264 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
265 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
266 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
268 // A 128-bit subvector insert to the first 256-bit vector position
269 // is a subregister copy that needs no instruction.
270 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
285 // Implicitly promote a 32-bit scalar to a vector.
286 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
287 (COPY_TO_REGCLASS FR32:$src, VR128)>;
288 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
289 (COPY_TO_REGCLASS FR32:$src, VR128)>;
290 // Implicitly promote a 64-bit scalar to a vector.
291 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
292 (COPY_TO_REGCLASS FR64:$src, VR128)>;
293 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
294 (COPY_TO_REGCLASS FR64:$src, VR128)>;
296 // Bitcasts between 128-bit vector types. Return the original type since
297 // no instruction is needed for the conversion
298 let Predicates = [HasSSE2] in {
299 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
328 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
331 // Bitcasts between 256-bit vector types. Return the original type since
332 // no instruction is needed for the conversion
333 let Predicates = [HasAVX] in {
334 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
363 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
366 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
367 // This is expanded by ExpandPostRAPseudos.
368 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
370 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
371 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
372 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
373 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
376 //===----------------------------------------------------------------------===//
377 // AVX & SSE - Zero/One Vectors
378 //===----------------------------------------------------------------------===//
380 // Alias instruction that maps zero vector to pxor / xorp* for sse.
381 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
382 // swizzled by ExecutionDepsFix to pxor.
383 // We set canFoldAsLoad because this can be converted to a constant-pool
384 // load of an all-zeros value if folding it would be beneficial.
385 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
387 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
388 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
391 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
392 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
393 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
394 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
395 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
398 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
399 // and doesn't need it because on sandy bridge the register is set to zero
400 // at the rename stage without using any execution unit, so SET0PSY
401 // and SET0PDY can be used for vector int instructions without penalty
402 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
403 isPseudo = 1, Predicates = [HasAVX] in {
404 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
405 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
408 let Predicates = [HasAVX] in
409 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
411 let Predicates = [HasAVX2] in {
412 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
413 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
414 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
415 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
418 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
419 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
420 let Predicates = [HasAVX1Only] in {
421 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
422 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
423 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
425 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
426 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
427 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
429 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
430 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
431 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
433 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
434 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
435 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
438 // We set canFoldAsLoad because this can be converted to a constant-pool
439 // load of an all-ones value if folding it would be beneficial.
440 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
442 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
443 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
444 let Predicates = [HasAVX2] in
445 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
446 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
450 //===----------------------------------------------------------------------===//
451 // SSE 1 & 2 - Move FP Scalar Instructions
453 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
454 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
455 // is used instead. Register-to-register movss/movsd is not modeled as an
456 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
457 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
458 //===----------------------------------------------------------------------===//
460 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
461 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
462 [(set VR128:$dst, (vt (OpNode VR128:$src1,
463 (scalar_to_vector RC:$src2))))],
466 // Loading from memory automatically zeroing upper bits.
467 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
468 PatFrag mem_pat, string OpcodeStr> :
469 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
470 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
471 [(set RC:$dst, (mem_pat addr:$src))],
475 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
476 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
478 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
479 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
482 // For the disassembler
483 let isCodeGenOnly = 1, hasSideEffects = 0 in {
484 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
485 (ins VR128:$src1, FR32:$src2),
486 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
489 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
490 (ins VR128:$src1, FR64:$src2),
491 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
496 let canFoldAsLoad = 1, isReMaterializable = 1 in {
497 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
499 let AddedComplexity = 20 in
500 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
504 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
505 "movss\t{$src, $dst|$dst, $src}",
506 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
508 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
509 "movsd\t{$src, $dst|$dst, $src}",
510 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
514 let Constraints = "$src1 = $dst" in {
515 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
516 "movss\t{$src2, $dst|$dst, $src2}">, XS;
517 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
518 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
520 // For the disassembler
521 let isCodeGenOnly = 1, hasSideEffects = 0 in {
522 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
523 (ins VR128:$src1, FR32:$src2),
524 "movss\t{$src2, $dst|$dst, $src2}", [],
525 IIC_SSE_MOV_S_RR>, XS;
526 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
527 (ins VR128:$src1, FR64:$src2),
528 "movsd\t{$src2, $dst|$dst, $src2}", [],
529 IIC_SSE_MOV_S_RR>, XD;
533 let canFoldAsLoad = 1, isReMaterializable = 1 in {
534 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
536 let AddedComplexity = 20 in
537 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
540 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
541 "movss\t{$src, $dst|$dst, $src}",
542 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
543 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
544 "movsd\t{$src, $dst|$dst, $src}",
545 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
548 let Predicates = [HasAVX] in {
549 let AddedComplexity = 15 in {
550 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
551 // MOVS{S,D} to the lower bits.
552 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
553 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
554 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
555 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
556 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
557 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
558 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
559 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
561 // Move low f32 and clear high bits.
562 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
563 (SUBREG_TO_REG (i32 0),
564 (VMOVSSrr (v4f32 (V_SET0)),
565 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
566 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
567 (SUBREG_TO_REG (i32 0),
568 (VMOVSSrr (v4i32 (V_SET0)),
569 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
572 let AddedComplexity = 20 in {
573 // MOVSSrm zeros the high parts of the register; represent this
574 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
575 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
576 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
577 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
578 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
579 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
580 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
582 // MOVSDrm zeros the high parts of the register; represent this
583 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
584 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
585 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
586 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
587 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
588 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
589 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
590 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
591 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
592 def : Pat<(v2f64 (X86vzload addr:$src)),
593 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
595 // Represent the same patterns above but in the form they appear for
597 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
598 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
599 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
600 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
601 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
602 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
603 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
604 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
605 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
607 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
608 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
609 (SUBREG_TO_REG (i32 0),
610 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
612 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
613 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
614 (SUBREG_TO_REG (i64 0),
615 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
617 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
618 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
619 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
621 // Move low f64 and clear high bits.
622 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
623 (SUBREG_TO_REG (i32 0),
624 (VMOVSDrr (v2f64 (V_SET0)),
625 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
627 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
628 (SUBREG_TO_REG (i32 0),
629 (VMOVSDrr (v2i64 (V_SET0)),
630 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
632 // Extract and store.
633 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
635 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
636 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
638 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
640 // Shuffle with VMOVSS
641 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
642 (VMOVSSrr (v4i32 VR128:$src1),
643 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
644 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
645 (VMOVSSrr (v4f32 VR128:$src1),
646 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
649 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
650 (SUBREG_TO_REG (i32 0),
651 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
652 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
654 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
655 (SUBREG_TO_REG (i32 0),
656 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
657 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
660 // Shuffle with VMOVSD
661 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
662 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
663 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
664 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
665 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
666 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
667 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
668 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
671 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
672 (SUBREG_TO_REG (i32 0),
673 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
674 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
676 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
677 (SUBREG_TO_REG (i32 0),
678 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
679 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
683 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
684 // is during lowering, where it's not possible to recognize the fold cause
685 // it has two uses through a bitcast. One use disappears at isel time and the
686 // fold opportunity reappears.
687 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
689 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
690 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
692 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
693 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
694 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
697 let Predicates = [UseSSE1] in {
698 let AddedComplexity = 15 in {
699 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
700 // MOVSS to the lower bits.
701 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
702 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
703 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
704 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
705 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
706 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
709 let AddedComplexity = 20 in {
710 // MOVSSrm already zeros the high parts of the register.
711 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
712 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
713 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
714 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
715 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
716 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
719 // Extract and store.
720 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
722 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
724 // Shuffle with MOVSS
725 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
726 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
727 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
728 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
731 let Predicates = [UseSSE2] in {
732 let AddedComplexity = 15 in {
733 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
734 // MOVSD to the lower bits.
735 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
736 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
739 let AddedComplexity = 20 in {
740 // MOVSDrm already zeros the high parts of the register.
741 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
742 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
743 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
744 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
745 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
746 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
747 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
748 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
749 def : Pat<(v2f64 (X86vzload addr:$src)),
750 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
753 // Extract and store.
754 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
756 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
758 // Shuffle with MOVSD
759 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
760 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
761 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
762 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
763 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
764 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
765 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
766 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
768 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
769 // is during lowering, where it's not possible to recognize the fold cause
770 // it has two uses through a bitcast. One use disappears at isel time and the
771 // fold opportunity reappears.
772 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
773 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
774 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
775 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
776 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
777 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
778 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
779 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 //===----------------------------------------------------------------------===//
783 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
784 //===----------------------------------------------------------------------===//
786 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
787 X86MemOperand x86memop, PatFrag ld_frag,
788 string asm, Domain d,
790 bit IsReMaterializable = 1> {
791 let neverHasSideEffects = 1 in
792 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
793 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
794 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
795 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
796 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
797 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
800 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
801 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
803 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
804 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
806 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
807 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
809 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
810 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
813 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
814 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
816 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
817 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
818 TB, OpSize, VEX, VEX_L;
819 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
820 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
822 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
823 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
824 TB, OpSize, VEX, VEX_L;
825 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
826 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
828 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
829 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
831 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
832 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
834 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
835 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
838 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
839 "movaps\t{$src, $dst|$dst, $src}",
840 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
841 IIC_SSE_MOVA_P_MR>, VEX;
842 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
843 "movapd\t{$src, $dst|$dst, $src}",
844 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
845 IIC_SSE_MOVA_P_MR>, VEX;
846 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
847 "movups\t{$src, $dst|$dst, $src}",
848 [(store (v4f32 VR128:$src), addr:$dst)],
849 IIC_SSE_MOVU_P_MR>, VEX;
850 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
851 "movupd\t{$src, $dst|$dst, $src}",
852 [(store (v2f64 VR128:$src), addr:$dst)],
853 IIC_SSE_MOVU_P_MR>, VEX;
854 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
855 "movaps\t{$src, $dst|$dst, $src}",
856 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
857 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
858 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
859 "movapd\t{$src, $dst|$dst, $src}",
860 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
861 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
862 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
863 "movups\t{$src, $dst|$dst, $src}",
864 [(store (v8f32 VR256:$src), addr:$dst)],
865 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
866 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
867 "movupd\t{$src, $dst|$dst, $src}",
868 [(store (v4f64 VR256:$src), addr:$dst)],
869 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
872 let isCodeGenOnly = 1, hasSideEffects = 0 in {
873 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
875 "movaps\t{$src, $dst|$dst, $src}", [],
876 IIC_SSE_MOVA_P_RR>, VEX;
877 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
879 "movapd\t{$src, $dst|$dst, $src}", [],
880 IIC_SSE_MOVA_P_RR>, VEX;
881 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
883 "movups\t{$src, $dst|$dst, $src}", [],
884 IIC_SSE_MOVU_P_RR>, VEX;
885 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
887 "movupd\t{$src, $dst|$dst, $src}", [],
888 IIC_SSE_MOVU_P_RR>, VEX;
889 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
891 "movaps\t{$src, $dst|$dst, $src}", [],
892 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
893 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
895 "movapd\t{$src, $dst|$dst, $src}", [],
896 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
897 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
899 "movups\t{$src, $dst|$dst, $src}", [],
900 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
901 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
903 "movupd\t{$src, $dst|$dst, $src}", [],
904 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
907 let Predicates = [HasAVX] in {
908 def : Pat<(v8i32 (X86vzmovl
909 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
910 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
911 def : Pat<(v4i64 (X86vzmovl
912 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
913 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
914 def : Pat<(v8f32 (X86vzmovl
915 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
916 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
917 def : Pat<(v4f64 (X86vzmovl
918 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
919 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
923 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
924 (VMOVUPSYmr addr:$dst, VR256:$src)>;
925 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
926 (VMOVUPDYmr addr:$dst, VR256:$src)>;
928 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
929 "movaps\t{$src, $dst|$dst, $src}",
930 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
932 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
933 "movapd\t{$src, $dst|$dst, $src}",
934 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
936 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
937 "movups\t{$src, $dst|$dst, $src}",
938 [(store (v4f32 VR128:$src), addr:$dst)],
940 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
941 "movupd\t{$src, $dst|$dst, $src}",
942 [(store (v2f64 VR128:$src), addr:$dst)],
946 let isCodeGenOnly = 1, hasSideEffects = 0 in {
947 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
948 "movaps\t{$src, $dst|$dst, $src}", [],
950 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
951 "movapd\t{$src, $dst|$dst, $src}", [],
953 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
954 "movups\t{$src, $dst|$dst, $src}", [],
956 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
957 "movupd\t{$src, $dst|$dst, $src}", [],
961 let Predicates = [HasAVX] in {
962 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
963 (VMOVUPSmr addr:$dst, VR128:$src)>;
964 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
965 (VMOVUPDmr addr:$dst, VR128:$src)>;
968 let Predicates = [UseSSE1] in
969 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
970 (MOVUPSmr addr:$dst, VR128:$src)>;
971 let Predicates = [UseSSE2] in
972 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
973 (MOVUPDmr addr:$dst, VR128:$src)>;
975 // Use vmovaps/vmovups for AVX integer load/store.
976 let Predicates = [HasAVX] in {
977 // 128-bit load/store
978 def : Pat<(alignedloadv2i64 addr:$src),
979 (VMOVAPSrm addr:$src)>;
980 def : Pat<(loadv2i64 addr:$src),
981 (VMOVUPSrm addr:$src)>;
983 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
984 (VMOVAPSmr addr:$dst, VR128:$src)>;
985 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
986 (VMOVAPSmr addr:$dst, VR128:$src)>;
987 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
988 (VMOVAPSmr addr:$dst, VR128:$src)>;
989 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
990 (VMOVAPSmr addr:$dst, VR128:$src)>;
991 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
992 (VMOVUPSmr addr:$dst, VR128:$src)>;
993 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
994 (VMOVUPSmr addr:$dst, VR128:$src)>;
995 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
996 (VMOVUPSmr addr:$dst, VR128:$src)>;
997 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
998 (VMOVUPSmr addr:$dst, VR128:$src)>;
1000 // 256-bit load/store
1001 def : Pat<(alignedloadv4i64 addr:$src),
1002 (VMOVAPSYrm addr:$src)>;
1003 def : Pat<(loadv4i64 addr:$src),
1004 (VMOVUPSYrm addr:$src)>;
1005 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1006 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1007 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1008 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1009 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1010 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1011 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1012 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1013 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1014 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1015 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1016 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1017 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1018 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1019 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1020 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1022 // Special patterns for storing subvector extracts of lower 128-bits
1023 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1024 def : Pat<(alignedstore (v2f64 (extract_subvector
1025 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1026 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1027 def : Pat<(alignedstore (v4f32 (extract_subvector
1028 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1029 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1030 def : Pat<(alignedstore (v2i64 (extract_subvector
1031 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1032 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1033 def : Pat<(alignedstore (v4i32 (extract_subvector
1034 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1035 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1036 def : Pat<(alignedstore (v8i16 (extract_subvector
1037 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1038 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1039 def : Pat<(alignedstore (v16i8 (extract_subvector
1040 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1041 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1043 def : Pat<(store (v2f64 (extract_subvector
1044 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1045 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1046 def : Pat<(store (v4f32 (extract_subvector
1047 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1048 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1049 def : Pat<(store (v2i64 (extract_subvector
1050 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1051 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1052 def : Pat<(store (v4i32 (extract_subvector
1053 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1054 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1055 def : Pat<(store (v8i16 (extract_subvector
1056 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1057 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1058 def : Pat<(store (v16i8 (extract_subvector
1059 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1063 // Use movaps / movups for SSE integer load / store (one byte shorter).
1064 // The instructions selected below are then converted to MOVDQA/MOVDQU
1065 // during the SSE domain pass.
1066 let Predicates = [UseSSE1] in {
1067 def : Pat<(alignedloadv2i64 addr:$src),
1068 (MOVAPSrm addr:$src)>;
1069 def : Pat<(loadv2i64 addr:$src),
1070 (MOVUPSrm addr:$src)>;
1072 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1073 (MOVAPSmr addr:$dst, VR128:$src)>;
1074 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1075 (MOVAPSmr addr:$dst, VR128:$src)>;
1076 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1077 (MOVAPSmr addr:$dst, VR128:$src)>;
1078 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1079 (MOVAPSmr addr:$dst, VR128:$src)>;
1080 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1081 (MOVUPSmr addr:$dst, VR128:$src)>;
1082 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1083 (MOVUPSmr addr:$dst, VR128:$src)>;
1084 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1085 (MOVUPSmr addr:$dst, VR128:$src)>;
1086 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1087 (MOVUPSmr addr:$dst, VR128:$src)>;
1090 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1091 // bits are disregarded. FIXME: Set encoding to pseudo!
1092 let neverHasSideEffects = 1 in {
1093 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1094 "movaps\t{$src, $dst|$dst, $src}", [],
1095 IIC_SSE_MOVA_P_RR>, VEX;
1096 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1097 "movapd\t{$src, $dst|$dst, $src}", [],
1098 IIC_SSE_MOVA_P_RR>, VEX;
1099 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1100 "movaps\t{$src, $dst|$dst, $src}", [],
1102 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1103 "movapd\t{$src, $dst|$dst, $src}", [],
1107 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1108 // bits are disregarded. FIXME: Set encoding to pseudo!
1109 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1110 let isCodeGenOnly = 1 in {
1111 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1112 "movaps\t{$src, $dst|$dst, $src}",
1113 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1114 IIC_SSE_MOVA_P_RM>, VEX;
1115 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1116 "movapd\t{$src, $dst|$dst, $src}",
1117 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1118 IIC_SSE_MOVA_P_RM>, VEX;
1120 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1121 "movaps\t{$src, $dst|$dst, $src}",
1122 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1124 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1125 "movapd\t{$src, $dst|$dst, $src}",
1126 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1130 //===----------------------------------------------------------------------===//
1131 // SSE 1 & 2 - Move Low packed FP Instructions
1132 //===----------------------------------------------------------------------===//
1134 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1135 SDNode psnode, SDNode pdnode, string base_opc,
1136 string asm_opr, InstrItinClass itin> {
1137 def PSrm : PI<opc, MRMSrcMem,
1138 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1139 !strconcat(base_opc, "s", asm_opr),
1142 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1143 itin, SSEPackedSingle>, TB;
1145 def PDrm : PI<opc, MRMSrcMem,
1146 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1147 !strconcat(base_opc, "d", asm_opr),
1148 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1149 (scalar_to_vector (loadf64 addr:$src2)))))],
1150 itin, SSEPackedDouble>, TB, OpSize;
1153 let AddedComplexity = 20 in {
1154 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1155 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1156 IIC_SSE_MOV_LH>, VEX_4V;
1158 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1159 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1160 "\t{$src2, $dst|$dst, $src2}",
1164 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1165 "movlps\t{$src, $dst|$dst, $src}",
1166 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1167 (iPTR 0))), addr:$dst)],
1168 IIC_SSE_MOV_LH>, VEX;
1169 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1170 "movlpd\t{$src, $dst|$dst, $src}",
1171 [(store (f64 (vector_extract (v2f64 VR128:$src),
1172 (iPTR 0))), addr:$dst)],
1173 IIC_SSE_MOV_LH>, VEX;
1174 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1175 "movlps\t{$src, $dst|$dst, $src}",
1176 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1177 (iPTR 0))), addr:$dst)],
1179 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1180 "movlpd\t{$src, $dst|$dst, $src}",
1181 [(store (f64 (vector_extract (v2f64 VR128:$src),
1182 (iPTR 0))), addr:$dst)],
1185 let Predicates = [HasAVX] in {
1186 // Shuffle with VMOVLPS
1187 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1188 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1189 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1190 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1192 // Shuffle with VMOVLPD
1193 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1194 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1195 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1196 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1199 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1201 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1202 def : Pat<(store (v4i32 (X86Movlps
1203 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1204 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1205 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1207 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1208 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1210 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1213 let Predicates = [UseSSE1] in {
1214 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1215 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1216 (iPTR 0))), addr:$src1),
1217 (MOVLPSmr addr:$src1, VR128:$src2)>;
1219 // Shuffle with MOVLPS
1220 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1221 (MOVLPSrm VR128:$src1, addr:$src2)>;
1222 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1223 (MOVLPSrm VR128:$src1, addr:$src2)>;
1224 def : Pat<(X86Movlps VR128:$src1,
1225 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1226 (MOVLPSrm VR128:$src1, addr:$src2)>;
1229 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1231 (MOVLPSmr addr:$src1, VR128:$src2)>;
1232 def : Pat<(store (v4i32 (X86Movlps
1233 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1235 (MOVLPSmr addr:$src1, VR128:$src2)>;
1238 let Predicates = [UseSSE2] in {
1239 // Shuffle with MOVLPD
1240 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1241 (MOVLPDrm VR128:$src1, addr:$src2)>;
1242 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1243 (MOVLPDrm VR128:$src1, addr:$src2)>;
1246 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1248 (MOVLPDmr addr:$src1, VR128:$src2)>;
1249 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1251 (MOVLPDmr addr:$src1, VR128:$src2)>;
1254 //===----------------------------------------------------------------------===//
1255 // SSE 1 & 2 - Move Hi packed FP Instructions
1256 //===----------------------------------------------------------------------===//
1258 let AddedComplexity = 20 in {
1259 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1260 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1261 IIC_SSE_MOV_LH>, VEX_4V;
1263 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1264 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1265 "\t{$src2, $dst|$dst, $src2}",
1269 // v2f64 extract element 1 is always custom lowered to unpack high to low
1270 // and extract element 0 so the non-store version isn't too horrible.
1271 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1272 "movhps\t{$src, $dst|$dst, $src}",
1273 [(store (f64 (vector_extract
1274 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1275 (bc_v2f64 (v4f32 VR128:$src))),
1276 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1277 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1278 "movhpd\t{$src, $dst|$dst, $src}",
1279 [(store (f64 (vector_extract
1280 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1281 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1282 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1283 "movhps\t{$src, $dst|$dst, $src}",
1284 [(store (f64 (vector_extract
1285 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1286 (bc_v2f64 (v4f32 VR128:$src))),
1287 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1288 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1289 "movhpd\t{$src, $dst|$dst, $src}",
1290 [(store (f64 (vector_extract
1291 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1292 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1294 let Predicates = [HasAVX] in {
1296 def : Pat<(X86Movlhps VR128:$src1,
1297 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1298 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1299 def : Pat<(X86Movlhps VR128:$src1,
1300 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1301 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1303 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1304 // is during lowering, where it's not possible to recognize the load fold
1305 // cause it has two uses through a bitcast. One use disappears at isel time
1306 // and the fold opportunity reappears.
1307 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1308 (scalar_to_vector (loadf64 addr:$src2)))),
1309 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1312 let Predicates = [UseSSE1] in {
1314 def : Pat<(X86Movlhps VR128:$src1,
1315 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1316 (MOVHPSrm VR128:$src1, addr:$src2)>;
1317 def : Pat<(X86Movlhps VR128:$src1,
1318 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1319 (MOVHPSrm VR128:$src1, addr:$src2)>;
1322 let Predicates = [UseSSE2] in {
1323 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1324 // is during lowering, where it's not possible to recognize the load fold
1325 // cause it has two uses through a bitcast. One use disappears at isel time
1326 // and the fold opportunity reappears.
1327 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1328 (scalar_to_vector (loadf64 addr:$src2)))),
1329 (MOVHPDrm VR128:$src1, addr:$src2)>;
1332 //===----------------------------------------------------------------------===//
1333 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1334 //===----------------------------------------------------------------------===//
1336 let AddedComplexity = 20 in {
1337 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1338 (ins VR128:$src1, VR128:$src2),
1339 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1341 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1344 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1345 (ins VR128:$src1, VR128:$src2),
1346 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1348 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1352 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1353 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1354 (ins VR128:$src1, VR128:$src2),
1355 "movlhps\t{$src2, $dst|$dst, $src2}",
1357 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1359 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1360 (ins VR128:$src1, VR128:$src2),
1361 "movhlps\t{$src2, $dst|$dst, $src2}",
1363 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1367 let Predicates = [HasAVX] in {
1369 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1370 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1371 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1372 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1375 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1376 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1379 let Predicates = [UseSSE1] in {
1381 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1382 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1383 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1384 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1387 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1388 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1391 //===----------------------------------------------------------------------===//
1392 // SSE 1 & 2 - Conversion Instructions
1393 //===----------------------------------------------------------------------===//
1395 def SSE_CVT_PD : OpndItins<
1396 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1399 def SSE_CVT_PS : OpndItins<
1400 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1403 def SSE_CVT_Scalar : OpndItins<
1404 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1407 def SSE_CVT_SS2SI_32 : OpndItins<
1408 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1411 def SSE_CVT_SS2SI_64 : OpndItins<
1412 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1415 def SSE_CVT_SD2SI : OpndItins<
1416 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1419 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1420 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1421 string asm, OpndItins itins> {
1422 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1423 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1425 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1426 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1430 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1431 X86MemOperand x86memop, string asm, Domain d,
1433 let neverHasSideEffects = 1 in {
1434 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1437 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1442 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1443 X86MemOperand x86memop, string asm> {
1444 let neverHasSideEffects = 1 in {
1445 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1446 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1448 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1449 (ins DstRC:$src1, x86memop:$src),
1450 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1451 } // neverHasSideEffects = 1
1454 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1455 "cvttss2si\t{$src, $dst|$dst, $src}",
1458 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1459 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1461 XS, VEX, VEX_W, VEX_LIG;
1462 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1463 "cvttsd2si\t{$src, $dst|$dst, $src}",
1466 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1467 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1469 XD, VEX, VEX_W, VEX_LIG;
1471 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1472 // register, but the same isn't true when only using memory operands,
1473 // provide other assembly "l" and "q" forms to address this explicitly
1474 // where appropriate to do so.
1475 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1476 XS, VEX_4V, VEX_LIG;
1477 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1478 XS, VEX_4V, VEX_W, VEX_LIG;
1479 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1480 XD, VEX_4V, VEX_LIG;
1481 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1482 XD, VEX_4V, VEX_W, VEX_LIG;
1484 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1485 (VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
1486 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1487 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1489 let Predicates = [HasAVX] in {
1490 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1491 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1492 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1493 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1494 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1495 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1496 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1497 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1499 def : Pat<(f32 (sint_to_fp GR32:$src)),
1500 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1501 def : Pat<(f32 (sint_to_fp GR64:$src)),
1502 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1503 def : Pat<(f64 (sint_to_fp GR32:$src)),
1504 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1505 def : Pat<(f64 (sint_to_fp GR64:$src)),
1506 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1509 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1510 "cvttss2si\t{$src, $dst|$dst, $src}",
1511 SSE_CVT_SS2SI_32>, XS;
1512 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1513 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1514 SSE_CVT_SS2SI_64>, XS, REX_W;
1515 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1516 "cvttsd2si\t{$src, $dst|$dst, $src}",
1518 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1519 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1520 SSE_CVT_SD2SI>, XD, REX_W;
1521 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1522 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1523 SSE_CVT_Scalar>, XS;
1524 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1525 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1526 SSE_CVT_Scalar>, XS, REX_W;
1527 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1528 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1529 SSE_CVT_Scalar>, XD;
1530 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1531 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1532 SSE_CVT_Scalar>, XD, REX_W;
1534 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1535 // and/or XMM operand(s).
1537 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1538 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1539 string asm, OpndItins itins> {
1540 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1541 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1542 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1543 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1544 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1545 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>;
1548 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1549 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1550 PatFrag ld_frag, string asm, OpndItins itins,
1552 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1554 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1555 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1556 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1558 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1559 (ins DstRC:$src1, x86memop:$src2),
1561 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1562 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1563 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1567 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1568 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si{l}",
1569 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1570 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1571 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si{q}",
1572 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1574 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1575 sdmem, sse_load_f64, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1576 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1577 sdmem, sse_load_f64, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1580 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1581 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1582 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1583 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1584 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1585 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1587 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1588 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1589 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1590 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1591 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1592 SSE_CVT_Scalar, 0>, XD,
1595 let Constraints = "$src1 = $dst" in {
1596 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1597 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1598 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1599 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1600 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1601 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1602 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1603 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1604 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1605 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1606 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1607 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1612 // Aliases for intrinsics
1613 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1614 ssmem, sse_load_f32, "cvttss2si",
1615 SSE_CVT_SS2SI_32>, XS, VEX;
1616 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1617 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1618 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1620 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1621 sdmem, sse_load_f64, "cvttsd2si",
1622 SSE_CVT_SD2SI>, XD, VEX;
1623 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1624 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1625 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1627 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1628 ssmem, sse_load_f32, "cvttss2si",
1629 SSE_CVT_SS2SI_32>, XS;
1630 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1631 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1632 "cvttss2si{q}", SSE_CVT_SS2SI_64>, XS, REX_W;
1633 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1634 sdmem, sse_load_f64, "cvttsd2si",
1636 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1637 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1638 "cvttsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1640 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1641 ssmem, sse_load_f32, "cvtss2si{l}",
1642 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1643 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1644 ssmem, sse_load_f32, "cvtss2si{q}",
1645 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1647 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1648 ssmem, sse_load_f32, "cvtss2si{l}",
1649 SSE_CVT_SS2SI_32>, XS;
1650 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1651 ssmem, sse_load_f32, "cvtss2si{q}",
1652 SSE_CVT_SS2SI_64>, XS, REX_W;
1654 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1655 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1656 SSEPackedSingle, SSE_CVT_PS>,
1657 TB, VEX, Requires<[HasAVX]>;
1658 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1659 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1660 SSEPackedSingle, SSE_CVT_PS>,
1661 TB, VEX, VEX_L, Requires<[HasAVX]>;
1663 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1664 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1665 SSEPackedSingle, SSE_CVT_PS>,
1666 TB, Requires<[UseSSE2]>;
1670 // Convert scalar double to scalar single
1671 let neverHasSideEffects = 1 in {
1672 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1673 (ins FR64:$src1, FR64:$src2),
1674 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1675 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1677 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1678 (ins FR64:$src1, f64mem:$src2),
1679 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1680 [], IIC_SSE_CVT_Scalar_RM>,
1681 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1684 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1687 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1688 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1689 [(set FR32:$dst, (fround FR64:$src))],
1690 IIC_SSE_CVT_Scalar_RR>;
1691 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1692 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1693 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1694 IIC_SSE_CVT_Scalar_RM>,
1696 Requires<[UseSSE2, OptForSize]>;
1698 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1699 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1700 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1702 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1703 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
1704 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1705 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1706 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1707 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1708 VR128:$src1, sse_load_f64:$src2))],
1709 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
1711 let Constraints = "$src1 = $dst" in {
1712 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1713 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1714 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1716 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1717 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>;
1718 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1719 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1720 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1721 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1722 VR128:$src1, sse_load_f64:$src2))],
1723 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>;
1726 // Convert scalar single to scalar double
1727 // SSE2 instructions with XS prefix
1728 let neverHasSideEffects = 1 in {
1729 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1730 (ins FR32:$src1, FR32:$src2),
1731 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1732 [], IIC_SSE_CVT_Scalar_RR>,
1733 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1735 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1736 (ins FR32:$src1, f32mem:$src2),
1737 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1738 [], IIC_SSE_CVT_Scalar_RM>,
1739 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1742 def : Pat<(f64 (fextend FR32:$src)),
1743 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1744 def : Pat<(fextend (loadf32 addr:$src)),
1745 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1747 def : Pat<(extloadf32 addr:$src),
1748 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1749 Requires<[HasAVX, OptForSize]>;
1750 def : Pat<(extloadf32 addr:$src),
1751 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1752 Requires<[HasAVX, OptForSpeed]>;
1754 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1755 "cvtss2sd\t{$src, $dst|$dst, $src}",
1756 [(set FR64:$dst, (fextend FR32:$src))],
1757 IIC_SSE_CVT_Scalar_RR>, XS,
1758 Requires<[UseSSE2]>;
1759 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1760 "cvtss2sd\t{$src, $dst|$dst, $src}",
1761 [(set FR64:$dst, (extloadf32 addr:$src))],
1762 IIC_SSE_CVT_Scalar_RM>, XS,
1763 Requires<[UseSSE2, OptForSize]>;
1765 // extload f32 -> f64. This matches load+fextend because we have a hack in
1766 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1768 // Since these loads aren't folded into the fextend, we have to match it
1770 def : Pat<(fextend (loadf32 addr:$src)),
1771 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1772 def : Pat<(extloadf32 addr:$src),
1773 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1775 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1776 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1777 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1779 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1780 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
1781 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1782 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1783 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1785 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1786 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
1787 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1788 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1789 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1790 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1792 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1793 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>;
1794 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1795 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1796 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1798 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1799 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>;
1802 // Convert packed single/double fp to doubleword
1803 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1804 "cvtps2dq\t{$src, $dst|$dst, $src}",
1805 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1806 IIC_SSE_CVT_PS_RR>, VEX;
1807 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1808 "cvtps2dq\t{$src, $dst|$dst, $src}",
1810 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1811 IIC_SSE_CVT_PS_RM>, VEX;
1812 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1813 "cvtps2dq\t{$src, $dst|$dst, $src}",
1815 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1816 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1817 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1818 "cvtps2dq\t{$src, $dst|$dst, $src}",
1820 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1821 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1822 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1823 "cvtps2dq\t{$src, $dst|$dst, $src}",
1824 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1826 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1827 "cvtps2dq\t{$src, $dst|$dst, $src}",
1829 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1833 // Convert Packed Double FP to Packed DW Integers
1834 let Predicates = [HasAVX] in {
1835 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1836 // register, but the same isn't true when using memory operands instead.
1837 // Provide other assembly rr and rm forms to address this explicitly.
1838 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1839 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1840 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1844 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1845 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1846 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1847 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1849 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
1852 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1853 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1855 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L;
1856 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1857 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1859 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1861 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1862 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1865 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1866 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1868 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1870 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1871 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1872 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1875 // Convert with truncation packed single/double fp to doubleword
1876 // SSE2 packed instructions with XS prefix
1877 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1878 "cvttps2dq\t{$src, $dst|$dst, $src}",
1880 (int_x86_sse2_cvttps2dq VR128:$src))],
1881 IIC_SSE_CVT_PS_RR>, VEX;
1882 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1883 "cvttps2dq\t{$src, $dst|$dst, $src}",
1884 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1885 (memopv4f32 addr:$src)))],
1886 IIC_SSE_CVT_PS_RM>, VEX;
1887 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1888 "cvttps2dq\t{$src, $dst|$dst, $src}",
1890 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1891 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1892 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1893 "cvttps2dq\t{$src, $dst|$dst, $src}",
1894 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1895 (memopv8f32 addr:$src)))],
1896 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1898 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1899 "cvttps2dq\t{$src, $dst|$dst, $src}",
1900 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1902 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1903 "cvttps2dq\t{$src, $dst|$dst, $src}",
1905 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1908 let Predicates = [HasAVX] in {
1909 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1910 (VCVTDQ2PSrr VR128:$src)>;
1911 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1912 (VCVTDQ2PSrm addr:$src)>;
1914 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1915 (VCVTDQ2PSrr VR128:$src)>;
1916 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1917 (VCVTDQ2PSrm addr:$src)>;
1919 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1920 (VCVTTPS2DQrr VR128:$src)>;
1921 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1922 (VCVTTPS2DQrm addr:$src)>;
1924 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1925 (VCVTDQ2PSYrr VR256:$src)>;
1926 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1927 (VCVTDQ2PSYrm addr:$src)>;
1929 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1930 (VCVTTPS2DQYrr VR256:$src)>;
1931 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1932 (VCVTTPS2DQYrm addr:$src)>;
1935 let Predicates = [UseSSE2] in {
1936 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1937 (CVTDQ2PSrr VR128:$src)>;
1938 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1939 (CVTDQ2PSrm addr:$src)>;
1941 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1942 (CVTDQ2PSrr VR128:$src)>;
1943 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1944 (CVTDQ2PSrm addr:$src)>;
1946 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1947 (CVTTPS2DQrr VR128:$src)>;
1948 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1949 (CVTTPS2DQrm addr:$src)>;
1952 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1953 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1955 (int_x86_sse2_cvttpd2dq VR128:$src))],
1956 IIC_SSE_CVT_PD_RR>, VEX;
1958 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1959 // register, but the same isn't true when using memory operands instead.
1960 // Provide other assembly rr and rm forms to address this explicitly.
1963 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
1964 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
1965 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1966 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
1967 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1968 (memopv2f64 addr:$src)))],
1969 IIC_SSE_CVT_PD_RM>, VEX;
1972 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1973 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1975 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
1976 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
1977 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1978 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1980 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
1981 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1982 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
1983 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
1985 let Predicates = [HasAVX] in {
1986 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
1987 (VCVTTPD2DQYrr VR256:$src)>;
1988 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
1989 (VCVTTPD2DQYrm addr:$src)>;
1990 } // Predicates = [HasAVX]
1992 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1993 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1994 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1996 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1997 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1998 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1999 (memopv2f64 addr:$src)))],
2002 // Convert packed single to packed double
2003 let Predicates = [HasAVX] in {
2004 // SSE2 instructions without OpSize prefix
2005 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2006 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2007 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2008 IIC_SSE_CVT_PD_RR>, TB, VEX;
2009 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2010 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2011 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2012 IIC_SSE_CVT_PD_RM>, TB, VEX;
2013 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2014 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2016 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2017 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L;
2018 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2019 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2021 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2022 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L;
2025 let Predicates = [UseSSE2] in {
2026 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2027 "cvtps2pd\t{$src, $dst|$dst, $src}",
2028 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2029 IIC_SSE_CVT_PD_RR>, TB;
2030 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2031 "cvtps2pd\t{$src, $dst|$dst, $src}",
2032 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2033 IIC_SSE_CVT_PD_RM>, TB;
2036 // Convert Packed DW Integers to Packed Double FP
2037 let Predicates = [HasAVX] in {
2038 let neverHasSideEffects = 1, mayLoad = 1 in
2039 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2040 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2042 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2043 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2045 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
2046 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2047 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2049 (int_x86_avx_cvtdq2_pd_256
2050 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L;
2051 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2052 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2054 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L;
2057 let neverHasSideEffects = 1, mayLoad = 1 in
2058 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2059 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2061 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2062 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2063 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2066 // AVX 256-bit register conversion intrinsics
2067 let Predicates = [HasAVX] in {
2068 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2069 (VCVTDQ2PDYrr VR128:$src)>;
2070 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2071 (VCVTDQ2PDYrm addr:$src)>;
2072 } // Predicates = [HasAVX]
2074 // Convert packed double to packed single
2075 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2076 // register, but the same isn't true when using memory operands instead.
2077 // Provide other assembly rr and rm forms to address this explicitly.
2078 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2079 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2080 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2081 IIC_SSE_CVT_PD_RR>, VEX;
2084 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2085 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2086 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2087 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2089 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2090 IIC_SSE_CVT_PD_RM>, VEX;
2093 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2094 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2096 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2097 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
2098 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2099 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2101 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2102 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2103 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2104 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2106 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2107 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2108 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2110 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2111 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2113 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2117 // AVX 256-bit register conversion intrinsics
2118 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2119 // whenever possible to avoid declaring two versions of each one.
2120 let Predicates = [HasAVX] in {
2121 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2122 (VCVTDQ2PSYrr VR256:$src)>;
2123 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2124 (VCVTDQ2PSYrm addr:$src)>;
2126 // Match fround and fextend for 128/256-bit conversions
2127 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2128 (VCVTPD2PSrr VR128:$src)>;
2129 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2130 (VCVTPD2PSXrm addr:$src)>;
2131 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2132 (VCVTPD2PSYrr VR256:$src)>;
2133 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2134 (VCVTPD2PSYrm addr:$src)>;
2136 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2137 (VCVTPS2PDrr VR128:$src)>;
2138 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2139 (VCVTPS2PDYrr VR128:$src)>;
2140 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2141 (VCVTPS2PDYrm addr:$src)>;
2144 let Predicates = [UseSSE2] in {
2145 // Match fround and fextend for 128 conversions
2146 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2147 (CVTPD2PSrr VR128:$src)>;
2148 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2149 (CVTPD2PSrm addr:$src)>;
2151 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2152 (CVTPS2PDrr VR128:$src)>;
2155 //===----------------------------------------------------------------------===//
2156 // SSE 1 & 2 - Compare Instructions
2157 //===----------------------------------------------------------------------===//
2159 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2160 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2161 Operand CC, SDNode OpNode, ValueType VT,
2162 PatFrag ld_frag, string asm, string asm_alt,
2164 def rr : SIi8<0xC2, MRMSrcReg,
2165 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2166 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2168 def rm : SIi8<0xC2, MRMSrcMem,
2169 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2170 [(set RC:$dst, (OpNode (VT RC:$src1),
2171 (ld_frag addr:$src2), imm:$cc))],
2174 // Accept explicit immediate argument form instead of comparison code.
2175 let neverHasSideEffects = 1 in {
2176 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2177 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2178 IIC_SSE_ALU_F32S_RR>;
2180 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2181 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2182 IIC_SSE_ALU_F32S_RM>;
2186 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2187 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2188 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2190 XS, VEX_4V, VEX_LIG;
2191 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2192 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2193 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2194 SSE_ALU_F32S>, // same latency as 32 bit compare
2195 XD, VEX_4V, VEX_LIG;
2197 let Constraints = "$src1 = $dst" in {
2198 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2199 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2200 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2202 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2203 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2204 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2205 SSE_ALU_F32S>, // same latency as 32 bit compare
2209 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2210 Intrinsic Int, string asm, OpndItins itins> {
2211 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2212 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2213 [(set VR128:$dst, (Int VR128:$src1,
2214 VR128:$src, imm:$cc))],
2216 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2217 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2218 [(set VR128:$dst, (Int VR128:$src1,
2219 (load addr:$src), imm:$cc))],
2223 // Aliases to match intrinsics which expect XMM operand(s).
2224 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2225 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2228 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2229 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2230 SSE_ALU_F32S>, // same latency as f32
2232 let Constraints = "$src1 = $dst" in {
2233 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2234 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2236 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2237 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2238 SSE_ALU_F32S>, // same latency as f32
2243 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2244 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2245 ValueType vt, X86MemOperand x86memop,
2246 PatFrag ld_frag, string OpcodeStr, Domain d> {
2247 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2248 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2249 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2250 IIC_SSE_COMIS_RR, d>;
2251 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2252 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2253 [(set EFLAGS, (OpNode (vt RC:$src1),
2254 (ld_frag addr:$src2)))],
2255 IIC_SSE_COMIS_RM, d>;
2258 let Defs = [EFLAGS] in {
2259 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2260 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2261 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2262 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2264 let Pattern = []<dag> in {
2265 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2266 "comiss", SSEPackedSingle>, TB, VEX,
2268 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2269 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2273 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2274 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2275 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2276 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2278 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2279 load, "comiss", SSEPackedSingle>, TB, VEX;
2280 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2281 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2282 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2283 "ucomiss", SSEPackedSingle>, TB;
2284 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2285 "ucomisd", SSEPackedDouble>, TB, OpSize;
2287 let Pattern = []<dag> in {
2288 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2289 "comiss", SSEPackedSingle>, TB;
2290 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2291 "comisd", SSEPackedDouble>, TB, OpSize;
2294 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2295 load, "ucomiss", SSEPackedSingle>, TB;
2296 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2297 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2299 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2300 "comiss", SSEPackedSingle>, TB;
2301 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2302 "comisd", SSEPackedDouble>, TB, OpSize;
2303 } // Defs = [EFLAGS]
2305 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2306 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2307 Operand CC, Intrinsic Int, string asm,
2308 string asm_alt, Domain d> {
2309 def rri : PIi8<0xC2, MRMSrcReg,
2310 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2311 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2312 IIC_SSE_CMPP_RR, d>;
2313 def rmi : PIi8<0xC2, MRMSrcMem,
2314 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2315 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2316 IIC_SSE_CMPP_RM, d>;
2318 // Accept explicit immediate argument form instead of comparison code.
2319 let neverHasSideEffects = 1 in {
2320 def rri_alt : PIi8<0xC2, MRMSrcReg,
2321 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2322 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2323 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2324 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2325 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2329 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2330 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2331 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2332 SSEPackedSingle>, TB, VEX_4V;
2333 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2334 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2335 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2336 SSEPackedDouble>, TB, OpSize, VEX_4V;
2337 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2338 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2339 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2340 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2341 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2342 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2343 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2344 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2345 let Constraints = "$src1 = $dst" in {
2346 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2347 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2348 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2349 SSEPackedSingle>, TB;
2350 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2351 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2352 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2353 SSEPackedDouble>, TB, OpSize;
2356 let Predicates = [HasAVX] in {
2357 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2358 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2359 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2360 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2361 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2362 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2363 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2364 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2366 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2367 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2368 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2369 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2370 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2371 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2372 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2373 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2376 let Predicates = [UseSSE1] in {
2377 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2378 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2379 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2380 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2383 let Predicates = [UseSSE2] in {
2384 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2385 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2386 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2387 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2390 //===----------------------------------------------------------------------===//
2391 // SSE 1 & 2 - Shuffle Instructions
2392 //===----------------------------------------------------------------------===//
2394 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2395 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2396 ValueType vt, string asm, PatFrag mem_frag,
2397 Domain d, bit IsConvertibleToThreeAddress = 0> {
2398 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2399 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2400 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2401 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2402 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2403 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2404 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2405 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2406 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2409 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2410 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2411 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2412 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2413 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2414 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2415 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2416 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2417 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2418 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2419 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2420 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2422 let Constraints = "$src1 = $dst" in {
2423 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2424 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2425 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2427 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2428 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2429 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2433 let Predicates = [HasAVX] in {
2434 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2435 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2436 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2437 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2438 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2440 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2441 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2442 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2443 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2444 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2447 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2448 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2449 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2450 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2451 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2453 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2454 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2455 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2456 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2457 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2460 let Predicates = [UseSSE1] in {
2461 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2462 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2463 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2464 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2465 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2468 let Predicates = [UseSSE2] in {
2469 // Generic SHUFPD patterns
2470 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2471 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2472 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2473 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2474 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2477 //===----------------------------------------------------------------------===//
2478 // SSE 1 & 2 - Unpack Instructions
2479 //===----------------------------------------------------------------------===//
2481 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2482 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2483 PatFrag mem_frag, RegisterClass RC,
2484 X86MemOperand x86memop, string asm,
2486 def rr : PI<opc, MRMSrcReg,
2487 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2489 (vt (OpNode RC:$src1, RC:$src2)))],
2491 def rm : PI<opc, MRMSrcMem,
2492 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2494 (vt (OpNode RC:$src1,
2495 (mem_frag addr:$src2))))],
2499 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2500 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2501 SSEPackedSingle>, TB, VEX_4V;
2502 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2503 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2504 SSEPackedDouble>, TB, OpSize, VEX_4V;
2505 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2506 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2507 SSEPackedSingle>, TB, VEX_4V;
2508 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2509 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2510 SSEPackedDouble>, TB, OpSize, VEX_4V;
2512 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2513 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2514 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2515 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2516 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2517 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2518 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2519 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2520 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2521 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2522 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2523 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2525 let Constraints = "$src1 = $dst" in {
2526 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2527 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2528 SSEPackedSingle>, TB;
2529 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2530 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2531 SSEPackedDouble>, TB, OpSize;
2532 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2533 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2534 SSEPackedSingle>, TB;
2535 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2536 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2537 SSEPackedDouble>, TB, OpSize;
2538 } // Constraints = "$src1 = $dst"
2540 let Predicates = [HasAVX1Only] in {
2541 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2542 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2543 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2544 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2545 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2546 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2547 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2548 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2550 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2551 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2552 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2553 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2554 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2555 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2556 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2557 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2560 let Predicates = [HasAVX] in {
2561 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2562 // problem is during lowering, where it's not possible to recognize the load
2563 // fold cause it has two uses through a bitcast. One use disappears at isel
2564 // time and the fold opportunity reappears.
2565 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2566 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2569 let Predicates = [UseSSE2] in {
2570 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2571 // problem is during lowering, where it's not possible to recognize the load
2572 // fold cause it has two uses through a bitcast. One use disappears at isel
2573 // time and the fold opportunity reappears.
2574 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2575 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2578 //===----------------------------------------------------------------------===//
2579 // SSE 1 & 2 - Extract Floating-Point Sign mask
2580 //===----------------------------------------------------------------------===//
2582 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2583 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2585 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2586 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2587 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2588 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2589 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2590 IIC_SSE_MOVMSK, d>, REX_W;
2593 let Predicates = [HasAVX] in {
2594 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2595 "movmskps", SSEPackedSingle>, TB, VEX;
2596 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2597 "movmskpd", SSEPackedDouble>, TB,
2599 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2600 "movmskps", SSEPackedSingle>, TB,
2602 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2603 "movmskpd", SSEPackedDouble>, TB,
2606 def : Pat<(i32 (X86fgetsign FR32:$src)),
2607 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2608 def : Pat<(i64 (X86fgetsign FR32:$src)),
2609 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2610 def : Pat<(i32 (X86fgetsign FR64:$src)),
2611 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2612 def : Pat<(i64 (X86fgetsign FR64:$src)),
2613 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2616 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2617 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2618 SSEPackedSingle>, TB, VEX;
2619 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2620 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2621 SSEPackedDouble>, TB,
2623 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2624 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2625 SSEPackedSingle>, TB, VEX, VEX_L;
2626 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2627 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2628 SSEPackedDouble>, TB,
2632 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2633 SSEPackedSingle>, TB;
2634 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2635 SSEPackedDouble>, TB, OpSize;
2637 def : Pat<(i32 (X86fgetsign FR32:$src)),
2638 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2639 Requires<[UseSSE1]>;
2640 def : Pat<(i64 (X86fgetsign FR32:$src)),
2641 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2642 Requires<[UseSSE1]>;
2643 def : Pat<(i32 (X86fgetsign FR64:$src)),
2644 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2645 Requires<[UseSSE2]>;
2646 def : Pat<(i64 (X86fgetsign FR64:$src)),
2647 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2648 Requires<[UseSSE2]>;
2650 //===---------------------------------------------------------------------===//
2651 // SSE2 - Packed Integer Logical Instructions
2652 //===---------------------------------------------------------------------===//
2654 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2656 /// PDI_binop_rm - Simple SSE2 binary operator.
2657 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2658 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2659 X86MemOperand x86memop, OpndItins itins,
2660 bit IsCommutable, bit Is2Addr> {
2661 let isCommutable = IsCommutable in
2662 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2663 (ins RC:$src1, RC:$src2),
2665 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2666 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2667 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2668 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2669 (ins RC:$src1, x86memop:$src2),
2671 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2672 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2673 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2674 (bitconvert (memop_frag addr:$src2)))))],
2677 } // ExeDomain = SSEPackedInt
2679 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2680 ValueType OpVT128, ValueType OpVT256,
2681 OpndItins itins, bit IsCommutable = 0> {
2682 let Predicates = [HasAVX] in
2683 defm VP#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2684 VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2686 let Constraints = "$src1 = $dst" in
2687 defm P#NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2688 memopv2i64, i128mem, itins, IsCommutable, 1>;
2690 let Predicates = [HasAVX2] in
2691 defm VP#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2692 OpVT256, VR256, memopv4i64, i256mem, itins,
2693 IsCommutable, 0>, VEX_4V, VEX_L;
2696 // These are ordered here for pattern ordering requirements with the fp versions
2698 defm AND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2699 defm OR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2700 defm XOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2701 defm ANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2702 SSE_BIT_ITINS_P, 0>;
2704 //===----------------------------------------------------------------------===//
2705 // SSE 1 & 2 - Logical Instructions
2706 //===----------------------------------------------------------------------===//
2708 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2710 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2711 SDNode OpNode, OpndItins itins> {
2712 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2713 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2716 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2717 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2720 let Constraints = "$src1 = $dst" in {
2721 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2722 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2725 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2726 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2731 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2732 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2734 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2736 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2739 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2740 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2743 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2745 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2747 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2748 !strconcat(OpcodeStr, "ps"), f256mem,
2749 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2750 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2751 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2753 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2754 !strconcat(OpcodeStr, "pd"), f256mem,
2755 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2756 (bc_v4i64 (v4f64 VR256:$src2))))],
2757 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2758 (memopv4i64 addr:$src2)))], 0>,
2759 TB, OpSize, VEX_4V, VEX_L;
2761 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2762 // are all promoted to v2i64, and the patterns are covered by the int
2763 // version. This is needed in SSE only, because v2i64 isn't supported on
2764 // SSE1, but only on SSE2.
2765 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2766 !strconcat(OpcodeStr, "ps"), f128mem, [],
2767 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2768 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2770 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2771 !strconcat(OpcodeStr, "pd"), f128mem,
2772 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2773 (bc_v2i64 (v2f64 VR128:$src2))))],
2774 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2775 (memopv2i64 addr:$src2)))], 0>,
2778 let Constraints = "$src1 = $dst" in {
2779 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2780 !strconcat(OpcodeStr, "ps"), f128mem,
2781 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2782 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2783 (memopv2i64 addr:$src2)))]>, TB;
2785 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2786 !strconcat(OpcodeStr, "pd"), f128mem,
2787 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2788 (bc_v2i64 (v2f64 VR128:$src2))))],
2789 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2790 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2794 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2795 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2796 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2797 let isCommutable = 0 in
2798 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2800 //===----------------------------------------------------------------------===//
2801 // SSE 1 & 2 - Arithmetic Instructions
2802 //===----------------------------------------------------------------------===//
2804 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2807 /// In addition, we also have a special variant of the scalar form here to
2808 /// represent the associated intrinsic operation. This form is unlike the
2809 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2810 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2812 /// These three forms can each be reg+reg or reg+mem.
2815 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2817 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2820 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2821 OpNode, FR32, f32mem,
2822 itins.s, Is2Addr>, XS;
2823 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2824 OpNode, FR64, f64mem,
2825 itins.d, Is2Addr>, XD;
2828 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2831 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2832 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2834 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2835 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2839 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2842 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2843 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2845 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2846 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2850 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2853 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2854 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2855 itins.s, Is2Addr>, XS;
2856 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2857 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2858 itins.d, Is2Addr>, XD;
2861 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2864 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2865 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2866 SSEPackedSingle, itins.s, Is2Addr>,
2869 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2870 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2871 SSEPackedDouble, itins.d, Is2Addr>,
2875 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2877 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2878 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2879 SSEPackedSingle, itins.s, 0>, TB, VEX_L;
2881 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2882 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2883 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_L;
2886 // Binary Arithmetic instructions
2887 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2888 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2890 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2891 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2893 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2894 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2896 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2897 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2900 let isCommutable = 0 in {
2901 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2902 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2904 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2905 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2907 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2908 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2910 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2911 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2913 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2914 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2916 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2917 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2918 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2919 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2921 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2922 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2924 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2925 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2926 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2927 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2931 let Constraints = "$src1 = $dst" in {
2932 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2933 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2934 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2935 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2936 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2937 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2939 let isCommutable = 0 in {
2940 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2941 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2942 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2943 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2944 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2945 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2946 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2947 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2948 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2949 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2950 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2951 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2952 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2953 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2957 let isCodeGenOnly = 1 in {
2958 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
2960 defm VMAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P, 0>,
2961 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>, VEX_4V;
2962 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
2964 defm VMINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P, 0>,
2965 basic_sse12_fp_binop_p_y<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>, VEX_4V;
2966 let Constraints = "$src1 = $dst" in {
2967 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>,
2968 basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2969 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>,
2970 basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2975 /// In addition, we also have a special variant of the scalar form here to
2976 /// represent the associated intrinsic operation. This form is unlike the
2977 /// plain scalar form, in that it takes an entire vector (instead of a
2978 /// scalar) and leaves the top elements undefined.
2980 /// And, we have a special variant form for a full-vector intrinsic form.
2982 def SSE_SQRTP : OpndItins<
2983 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2986 def SSE_SQRTS : OpndItins<
2987 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2990 def SSE_RCPP : OpndItins<
2991 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
2994 def SSE_RCPS : OpndItins<
2995 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
2998 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2999 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3000 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3001 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3002 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3003 [(set FR32:$dst, (OpNode FR32:$src))]>;
3004 // For scalar unary operations, fold a load into the operation
3005 // only in OptForSize mode. It eliminates an instruction, but it also
3006 // eliminates a whole-register clobber (the load), so it introduces a
3007 // partial register update condition.
3008 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3009 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3010 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3011 Requires<[UseSSE1, OptForSize]>;
3012 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3013 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3014 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3015 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3016 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3017 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3020 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3021 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3022 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3023 !strconcat(OpcodeStr,
3024 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3025 let mayLoad = 1 in {
3026 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3027 !strconcat(OpcodeStr,
3028 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3029 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3030 (ins VR128:$src1, ssmem:$src2),
3031 !strconcat(OpcodeStr,
3032 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3036 /// sse1_fp_unop_p - SSE1 unops in packed form.
3037 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3039 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3040 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3041 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3042 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3043 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3044 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3047 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3048 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3050 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3051 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3052 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3054 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3055 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3056 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3060 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3061 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3062 Intrinsic V4F32Int, OpndItins itins> {
3063 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3064 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3065 [(set VR128:$dst, (V4F32Int VR128:$src))],
3067 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3068 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3069 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3073 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3074 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3075 Intrinsic V4F32Int, OpndItins itins> {
3076 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3077 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3078 [(set VR256:$dst, (V4F32Int VR256:$src))],
3080 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3081 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3082 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3086 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3087 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3088 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3089 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3090 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3091 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3092 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3093 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3094 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3095 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3096 Requires<[UseSSE2, OptForSize]>;
3097 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3098 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3099 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3100 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3101 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3102 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3105 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3106 let hasSideEffects = 0 in
3107 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3108 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3109 !strconcat(OpcodeStr,
3110 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3111 let mayLoad = 1 in {
3112 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3113 !strconcat(OpcodeStr,
3114 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3115 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3116 (ins VR128:$src1, sdmem:$src2),
3117 !strconcat(OpcodeStr,
3118 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3122 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3123 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3124 SDNode OpNode, OpndItins itins> {
3125 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3126 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3127 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3128 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3129 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3130 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3133 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3134 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3136 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3137 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3138 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3140 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3141 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3142 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3146 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3147 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3148 Intrinsic V2F64Int, OpndItins itins> {
3149 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3150 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3151 [(set VR128:$dst, (V2F64Int VR128:$src))],
3153 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3154 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3155 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3159 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3160 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3161 Intrinsic V2F64Int, OpndItins itins> {
3162 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3163 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3164 [(set VR256:$dst, (V2F64Int VR256:$src))],
3166 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3167 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3168 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3172 let Predicates = [HasAVX] in {
3174 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3175 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3177 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3178 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3179 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3180 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3181 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3183 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3185 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3187 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3191 // Reciprocal approximations. Note that these typically require refinement
3192 // in order to obtain suitable precision.
3193 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3194 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3195 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3196 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3198 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3201 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3202 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3203 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3204 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3206 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3210 def : Pat<(f32 (fsqrt FR32:$src)),
3211 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3212 def : Pat<(f32 (fsqrt (load addr:$src))),
3213 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3214 Requires<[HasAVX, OptForSize]>;
3215 def : Pat<(f64 (fsqrt FR64:$src)),
3216 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3217 def : Pat<(f64 (fsqrt (load addr:$src))),
3218 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3219 Requires<[HasAVX, OptForSize]>;
3221 def : Pat<(f32 (X86frsqrt FR32:$src)),
3222 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3223 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3224 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3225 Requires<[HasAVX, OptForSize]>;
3227 def : Pat<(f32 (X86frcp FR32:$src)),
3228 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3229 def : Pat<(f32 (X86frcp (load addr:$src))),
3230 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3231 Requires<[HasAVX, OptForSize]>;
3233 let Predicates = [HasAVX] in {
3234 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3235 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3236 (COPY_TO_REGCLASS VR128:$src, FR32)),
3238 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3239 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3241 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3242 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3243 (COPY_TO_REGCLASS VR128:$src, FR64)),
3245 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3246 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3248 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3249 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3250 (COPY_TO_REGCLASS VR128:$src, FR32)),
3252 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3253 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3255 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3256 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3257 (COPY_TO_REGCLASS VR128:$src, FR32)),
3259 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3260 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3264 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3266 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3267 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3268 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3270 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3271 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3273 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3274 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3275 Intrinsic F32Int, OpndItins itins> {
3276 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3277 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3278 [(set FR32:$dst, (OpNode FR32:$src))]>;
3279 // For scalar unary operations, fold a load into the operation
3280 // only in OptForSize mode. It eliminates an instruction, but it also
3281 // eliminates a whole-register clobber (the load), so it introduces a
3282 // partial register update condition.
3283 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3284 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3285 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3286 Requires<[UseSSE1, OptForSize]>;
3287 let Constraints = "$src1 = $dst" in {
3288 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3289 (ins VR128:$src1, VR128:$src2),
3290 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3292 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3293 (ins VR128:$src1, ssmem:$src2),
3294 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3299 // Reciprocal approximations. Note that these typically require refinement
3300 // in order to obtain suitable precision.
3301 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3303 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3304 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3306 let Predicates = [UseSSE1] in {
3307 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3308 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3311 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3313 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3314 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3315 let Predicates = [UseSSE1] in {
3316 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3317 (RCPSSr_Int VR128:$src, VR128:$src)>;
3320 // There is no f64 version of the reciprocal approximation instructions.
3322 //===----------------------------------------------------------------------===//
3323 // SSE 1 & 2 - Non-temporal stores
3324 //===----------------------------------------------------------------------===//
3326 let AddedComplexity = 400 in { // Prefer non-temporal versions
3327 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3328 (ins f128mem:$dst, VR128:$src),
3329 "movntps\t{$src, $dst|$dst, $src}",
3330 [(alignednontemporalstore (v4f32 VR128:$src),
3332 IIC_SSE_MOVNT>, VEX;
3333 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3334 (ins f128mem:$dst, VR128:$src),
3335 "movntpd\t{$src, $dst|$dst, $src}",
3336 [(alignednontemporalstore (v2f64 VR128:$src),
3338 IIC_SSE_MOVNT>, VEX;
3340 let ExeDomain = SSEPackedInt in
3341 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3342 (ins f128mem:$dst, VR128:$src),
3343 "movntdq\t{$src, $dst|$dst, $src}",
3344 [(alignednontemporalstore (v2i64 VR128:$src),
3346 IIC_SSE_MOVNT>, VEX;
3348 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3349 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3351 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3352 (ins f256mem:$dst, VR256:$src),
3353 "movntps\t{$src, $dst|$dst, $src}",
3354 [(alignednontemporalstore (v8f32 VR256:$src),
3356 IIC_SSE_MOVNT>, VEX, VEX_L;
3357 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3358 (ins f256mem:$dst, VR256:$src),
3359 "movntpd\t{$src, $dst|$dst, $src}",
3360 [(alignednontemporalstore (v4f64 VR256:$src),
3362 IIC_SSE_MOVNT>, VEX, VEX_L;
3363 let ExeDomain = SSEPackedInt in
3364 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3365 (ins f256mem:$dst, VR256:$src),
3366 "movntdq\t{$src, $dst|$dst, $src}",
3367 [(alignednontemporalstore (v4i64 VR256:$src),
3369 IIC_SSE_MOVNT>, VEX, VEX_L;
3372 let AddedComplexity = 400 in { // Prefer non-temporal versions
3373 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3374 "movntps\t{$src, $dst|$dst, $src}",
3375 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3377 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3378 "movntpd\t{$src, $dst|$dst, $src}",
3379 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3382 let ExeDomain = SSEPackedInt in
3383 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3384 "movntdq\t{$src, $dst|$dst, $src}",
3385 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3388 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3389 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3391 // There is no AVX form for instructions below this point
3392 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3393 "movnti{l}\t{$src, $dst|$dst, $src}",
3394 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3396 TB, Requires<[HasSSE2]>;
3397 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3398 "movnti{q}\t{$src, $dst|$dst, $src}",
3399 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3401 TB, Requires<[HasSSE2]>;
3404 //===----------------------------------------------------------------------===//
3405 // SSE 1 & 2 - Prefetch and memory fence
3406 //===----------------------------------------------------------------------===//
3408 // Prefetch intrinsic.
3409 let Predicates = [HasSSE1] in {
3410 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3411 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3412 IIC_SSE_PREFETCH>, TB;
3413 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3414 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3415 IIC_SSE_PREFETCH>, TB;
3416 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3417 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3418 IIC_SSE_PREFETCH>, TB;
3419 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3420 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3421 IIC_SSE_PREFETCH>, TB;
3425 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3426 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3427 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3429 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3430 // was introduced with SSE2, it's backward compatible.
3431 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3433 // Load, store, and memory fence
3434 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3435 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3436 TB, Requires<[HasSSE1]>;
3437 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3438 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3439 TB, Requires<[HasSSE2]>;
3440 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3441 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3442 TB, Requires<[HasSSE2]>;
3444 def : Pat<(X86SFence), (SFENCE)>;
3445 def : Pat<(X86LFence), (LFENCE)>;
3446 def : Pat<(X86MFence), (MFENCE)>;
3448 //===----------------------------------------------------------------------===//
3449 // SSE 1 & 2 - Load/Store XCSR register
3450 //===----------------------------------------------------------------------===//
3452 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3453 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3454 IIC_SSE_LDMXCSR>, VEX;
3455 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3456 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3457 IIC_SSE_STMXCSR>, VEX;
3459 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3460 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3462 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3463 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3466 //===---------------------------------------------------------------------===//
3467 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3468 //===---------------------------------------------------------------------===//
3470 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3472 let neverHasSideEffects = 1 in {
3473 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3474 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3476 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3477 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3479 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3480 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3482 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3483 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3488 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3489 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3490 "movdqa\t{$src, $dst|$dst, $src}", [],
3493 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3494 "movdqa\t{$src, $dst|$dst, $src}", [],
3495 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3496 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3497 "movdqu\t{$src, $dst|$dst, $src}", [],
3500 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3501 "movdqu\t{$src, $dst|$dst, $src}", [],
3502 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3505 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3506 neverHasSideEffects = 1 in {
3507 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3508 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3510 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3511 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3513 let Predicates = [HasAVX] in {
3514 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3515 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3517 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3518 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3523 let mayStore = 1, neverHasSideEffects = 1 in {
3524 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3525 (ins i128mem:$dst, VR128:$src),
3526 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3528 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3529 (ins i256mem:$dst, VR256:$src),
3530 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3532 let Predicates = [HasAVX] in {
3533 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3534 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3536 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3537 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3542 let neverHasSideEffects = 1 in
3543 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3544 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3546 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3547 "movdqu\t{$src, $dst|$dst, $src}",
3548 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3551 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3552 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3553 "movdqa\t{$src, $dst|$dst, $src}", [],
3556 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3557 "movdqu\t{$src, $dst|$dst, $src}",
3558 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3561 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3562 neverHasSideEffects = 1 in {
3563 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3564 "movdqa\t{$src, $dst|$dst, $src}",
3565 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3567 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3568 "movdqu\t{$src, $dst|$dst, $src}",
3569 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3571 XS, Requires<[UseSSE2]>;
3574 let mayStore = 1 in {
3575 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3576 "movdqa\t{$src, $dst|$dst, $src}",
3577 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3579 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3580 "movdqu\t{$src, $dst|$dst, $src}",
3581 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3583 XS, Requires<[UseSSE2]>;
3586 } // ExeDomain = SSEPackedInt
3588 let Predicates = [HasAVX] in {
3589 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3590 (VMOVDQUmr addr:$dst, VR128:$src)>;
3591 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3592 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3594 let Predicates = [UseSSE2] in
3595 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3596 (MOVDQUmr addr:$dst, VR128:$src)>;
3598 //===---------------------------------------------------------------------===//
3599 // SSE2 - Packed Integer Arithmetic Instructions
3600 //===---------------------------------------------------------------------===//
3602 def SSE_PMADD : OpndItins<
3603 IIC_SSE_PMADD, IIC_SSE_PMADD
3606 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3608 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3609 RegisterClass RC, PatFrag memop_frag,
3610 X86MemOperand x86memop,
3612 bit IsCommutable = 0,
3614 let isCommutable = IsCommutable in
3615 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3616 (ins RC:$src1, RC:$src2),
3618 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3619 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3620 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3621 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3622 (ins RC:$src1, x86memop:$src2),
3624 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3625 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3626 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3630 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3631 Intrinsic IntId256, OpndItins itins,
3632 bit IsCommutable = 0> {
3633 let Predicates = [HasAVX] in
3634 defm VP#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3635 VR128, memopv2i64, i128mem, itins,
3636 IsCommutable, 0>, VEX_4V;
3638 let Constraints = "$src1 = $dst" in
3639 defm P#NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3640 i128mem, itins, IsCommutable, 1>;
3642 let Predicates = [HasAVX2] in
3643 defm VP#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3644 VR256, memopv4i64, i256mem, itins,
3645 IsCommutable, 0>, VEX_4V, VEX_L;
3648 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3649 string OpcodeStr, SDNode OpNode,
3650 SDNode OpNode2, RegisterClass RC,
3651 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3652 ShiftOpndItins itins,
3654 // src2 is always 128-bit
3655 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3656 (ins RC:$src1, VR128:$src2),
3658 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3659 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3660 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3662 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3663 (ins RC:$src1, i128mem:$src2),
3665 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3666 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3667 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3668 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3669 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3670 (ins RC:$src1, i32i8imm:$src2),
3672 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3673 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3674 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3677 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3678 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3679 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3680 PatFrag memop_frag, X86MemOperand x86memop,
3682 bit IsCommutable = 0, bit Is2Addr = 1> {
3683 let isCommutable = IsCommutable in
3684 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3685 (ins RC:$src1, RC:$src2),
3687 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3688 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3689 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3690 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3691 (ins RC:$src1, x86memop:$src2),
3693 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3694 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3695 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3696 (bitconvert (memop_frag addr:$src2)))))]>;
3698 } // ExeDomain = SSEPackedInt
3700 defm ADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3701 SSE_INTALU_ITINS_P, 1>;
3702 defm ADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3703 SSE_INTALU_ITINS_P, 1>;
3704 defm ADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3705 SSE_INTALU_ITINS_P, 1>;
3706 defm ADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3707 SSE_INTALUQ_ITINS_P, 1>;
3708 defm MULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3709 SSE_INTMUL_ITINS_P, 1>;
3710 defm SUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3711 SSE_INTALU_ITINS_P, 0>;
3712 defm SUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3713 SSE_INTALU_ITINS_P, 0>;
3714 defm SUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3715 SSE_INTALU_ITINS_P, 0>;
3716 defm SUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3717 SSE_INTALUQ_ITINS_P, 0>;
3718 defm SUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3719 SSE_INTALU_ITINS_P, 0>;
3720 defm SUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3721 SSE_INTALU_ITINS_P, 0>;
3722 defm MINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3723 SSE_INTALU_ITINS_P, 1>;
3724 defm MINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3725 SSE_INTALU_ITINS_P, 1>;
3726 defm MAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3727 SSE_INTALU_ITINS_P, 1>;
3728 defm MAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3729 SSE_INTALU_ITINS_P, 1>;
3732 defm SUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
3733 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
3734 defm SUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3735 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
3736 defm ADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3737 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
3738 defm ADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3739 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
3740 defm ADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3741 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
3742 defm ADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3743 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
3744 defm MULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3745 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
3746 defm MULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3747 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
3748 defm MADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3749 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
3750 defm AVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3751 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
3752 defm AVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3753 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
3754 defm SADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3755 int_x86_avx2_psad_bw, SSE_INTALU_ITINS_P, 1>;
3757 let Predicates = [HasAVX] in
3758 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3759 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3761 let Predicates = [HasAVX2] in
3762 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3763 VR256, memopv4i64, i256mem,
3764 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3765 let Constraints = "$src1 = $dst" in
3766 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3767 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3769 //===---------------------------------------------------------------------===//
3770 // SSE2 - Packed Integer Logical Instructions
3771 //===---------------------------------------------------------------------===//
3773 let Predicates = [HasAVX] in {
3774 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3775 VR128, v8i16, v8i16, bc_v8i16,
3776 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3777 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3778 VR128, v4i32, v4i32, bc_v4i32,
3779 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3780 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3781 VR128, v2i64, v2i64, bc_v2i64,
3782 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3784 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3785 VR128, v8i16, v8i16, bc_v8i16,
3786 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3787 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3788 VR128, v4i32, v4i32, bc_v4i32,
3789 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3790 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3791 VR128, v2i64, v2i64, bc_v2i64,
3792 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3794 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3795 VR128, v8i16, v8i16, bc_v8i16,
3796 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3797 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3798 VR128, v4i32, v4i32, bc_v4i32,
3799 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3801 let ExeDomain = SSEPackedInt in {
3802 // 128-bit logical shifts.
3803 def VPSLLDQri : PDIi8<0x73, MRM7r,
3804 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3805 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3807 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3809 def VPSRLDQri : PDIi8<0x73, MRM3r,
3810 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3811 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3813 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3815 // PSRADQri doesn't exist in SSE[1-3].
3817 } // Predicates = [HasAVX]
3819 let Predicates = [HasAVX2] in {
3820 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3821 VR256, v16i16, v8i16, bc_v8i16,
3822 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3823 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3824 VR256, v8i32, v4i32, bc_v4i32,
3825 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3826 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3827 VR256, v4i64, v2i64, bc_v2i64,
3828 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3830 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3831 VR256, v16i16, v8i16, bc_v8i16,
3832 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3833 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3834 VR256, v8i32, v4i32, bc_v4i32,
3835 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3836 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3837 VR256, v4i64, v2i64, bc_v2i64,
3838 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3840 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3841 VR256, v16i16, v8i16, bc_v8i16,
3842 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3843 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3844 VR256, v8i32, v4i32, bc_v4i32,
3845 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3847 let ExeDomain = SSEPackedInt in {
3848 // 256-bit logical shifts.
3849 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3850 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3851 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3853 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3855 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3856 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3857 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3859 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3861 // PSRADQYri doesn't exist in SSE[1-3].
3863 } // Predicates = [HasAVX2]
3865 let Constraints = "$src1 = $dst" in {
3866 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3867 VR128, v8i16, v8i16, bc_v8i16,
3868 SSE_INTSHIFT_ITINS_P>;
3869 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3870 VR128, v4i32, v4i32, bc_v4i32,
3871 SSE_INTSHIFT_ITINS_P>;
3872 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3873 VR128, v2i64, v2i64, bc_v2i64,
3874 SSE_INTSHIFT_ITINS_P>;
3876 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3877 VR128, v8i16, v8i16, bc_v8i16,
3878 SSE_INTSHIFT_ITINS_P>;
3879 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3880 VR128, v4i32, v4i32, bc_v4i32,
3881 SSE_INTSHIFT_ITINS_P>;
3882 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3883 VR128, v2i64, v2i64, bc_v2i64,
3884 SSE_INTSHIFT_ITINS_P>;
3886 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3887 VR128, v8i16, v8i16, bc_v8i16,
3888 SSE_INTSHIFT_ITINS_P>;
3889 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3890 VR128, v4i32, v4i32, bc_v4i32,
3891 SSE_INTSHIFT_ITINS_P>;
3893 let ExeDomain = SSEPackedInt in {
3894 // 128-bit logical shifts.
3895 def PSLLDQri : PDIi8<0x73, MRM7r,
3896 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3897 "pslldq\t{$src2, $dst|$dst, $src2}",
3899 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
3900 def PSRLDQri : PDIi8<0x73, MRM3r,
3901 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3902 "psrldq\t{$src2, $dst|$dst, $src2}",
3904 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
3905 // PSRADQri doesn't exist in SSE[1-3].
3907 } // Constraints = "$src1 = $dst"
3909 let Predicates = [HasAVX] in {
3910 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3911 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3912 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3913 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3914 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3915 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3917 // Shift up / down and insert zero's.
3918 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3919 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3920 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3921 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3924 let Predicates = [HasAVX2] in {
3925 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
3926 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3927 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
3928 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3931 let Predicates = [UseSSE2] in {
3932 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3933 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3934 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3935 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3936 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3937 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3939 // Shift up / down and insert zero's.
3940 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3941 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3942 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3943 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3946 //===---------------------------------------------------------------------===//
3947 // SSE2 - Packed Integer Comparison Instructions
3948 //===---------------------------------------------------------------------===//
3950 defm CMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
3951 SSE_INTALU_ITINS_P, 1>;
3952 defm CMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
3953 SSE_INTALU_ITINS_P, 1>;
3954 defm CMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
3955 SSE_INTALU_ITINS_P, 1>;
3956 defm CMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
3957 SSE_INTALU_ITINS_P, 0>;
3958 defm CMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
3959 SSE_INTALU_ITINS_P, 0>;
3960 defm CMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
3961 SSE_INTALU_ITINS_P, 0>;
3963 //===---------------------------------------------------------------------===//
3964 // SSE2 - Packed Integer Pack Instructions
3965 //===---------------------------------------------------------------------===//
3967 // FIXME: Names are bad due to the need to have a 'P' prefix in the multiclass.
3968 defm ACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
3969 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
3970 defm ACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
3971 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
3972 defm ACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
3973 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
3975 //===---------------------------------------------------------------------===//
3976 // SSE2 - Packed Integer Shuffle Instructions
3977 //===---------------------------------------------------------------------===//
3979 let ExeDomain = SSEPackedInt in {
3980 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
3981 def ri : Ii8<0x70, MRMSrcReg,
3982 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3983 !strconcat(OpcodeStr,
3984 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3985 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
3987 def mi : Ii8<0x70, MRMSrcMem,
3988 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3989 !strconcat(OpcodeStr,
3990 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3992 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
3997 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
3998 def Yri : Ii8<0x70, MRMSrcReg,
3999 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4000 !strconcat(OpcodeStr,
4001 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4002 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4003 def Ymi : Ii8<0x70, MRMSrcMem,
4004 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4005 !strconcat(OpcodeStr,
4006 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4008 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4009 (i8 imm:$src2))))]>;
4011 } // ExeDomain = SSEPackedInt
4013 let Predicates = [HasAVX] in {
4014 let AddedComplexity = 5 in
4015 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4017 // SSE2 with ImmT == Imm8 and XS prefix.
4018 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4020 // SSE2 with ImmT == Imm8 and XD prefix.
4021 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4023 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4024 (VPSHUFDmi addr:$src1, imm:$imm)>;
4025 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4026 (VPSHUFDri VR128:$src1, imm:$imm)>;
4029 let Predicates = [HasAVX2] in {
4030 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>,
4031 TB, OpSize, VEX,VEX_L;
4032 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>,
4034 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>,
4038 let Predicates = [UseSSE2] in {
4039 let AddedComplexity = 5 in
4040 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4042 // SSE2 with ImmT == Imm8 and XS prefix.
4043 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4045 // SSE2 with ImmT == Imm8 and XD prefix.
4046 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4048 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4049 (PSHUFDmi addr:$src1, imm:$imm)>;
4050 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4051 (PSHUFDri VR128:$src1, imm:$imm)>;
4054 //===---------------------------------------------------------------------===//
4055 // SSE2 - Packed Integer Unpack Instructions
4056 //===---------------------------------------------------------------------===//
4058 let ExeDomain = SSEPackedInt in {
4059 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4060 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4061 def rr : PDI<opc, MRMSrcReg,
4062 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4064 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4065 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4066 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4068 def rm : PDI<opc, MRMSrcMem,
4069 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4071 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4072 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4073 [(set VR128:$dst, (OpNode VR128:$src1,
4074 (bc_frag (memopv2i64
4079 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4080 SDNode OpNode, PatFrag bc_frag> {
4081 def Yrr : PDI<opc, MRMSrcReg,
4082 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4083 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4084 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4085 def Yrm : PDI<opc, MRMSrcMem,
4086 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4087 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4088 [(set VR256:$dst, (OpNode VR256:$src1,
4089 (bc_frag (memopv4i64 addr:$src2))))]>;
4092 let Predicates = [HasAVX] in {
4093 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4094 bc_v16i8, 0>, VEX_4V;
4095 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4096 bc_v8i16, 0>, VEX_4V;
4097 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4098 bc_v4i32, 0>, VEX_4V;
4099 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4100 bc_v2i64, 0>, VEX_4V;
4102 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4103 bc_v16i8, 0>, VEX_4V;
4104 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4105 bc_v8i16, 0>, VEX_4V;
4106 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4107 bc_v4i32, 0>, VEX_4V;
4108 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4109 bc_v2i64, 0>, VEX_4V;
4112 let Predicates = [HasAVX2] in {
4113 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4114 bc_v32i8>, VEX_4V, VEX_L;
4115 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4116 bc_v16i16>, VEX_4V, VEX_L;
4117 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4118 bc_v8i32>, VEX_4V, VEX_L;
4119 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4120 bc_v4i64>, VEX_4V, VEX_L;
4122 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4123 bc_v32i8>, VEX_4V, VEX_L;
4124 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4125 bc_v16i16>, VEX_4V, VEX_L;
4126 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4127 bc_v8i32>, VEX_4V, VEX_L;
4128 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4129 bc_v4i64>, VEX_4V, VEX_L;
4132 let Constraints = "$src1 = $dst" in {
4133 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4135 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4137 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4139 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4142 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4144 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4146 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4148 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4151 } // ExeDomain = SSEPackedInt
4153 //===---------------------------------------------------------------------===//
4154 // SSE2 - Packed Integer Extract and Insert
4155 //===---------------------------------------------------------------------===//
4157 let ExeDomain = SSEPackedInt in {
4158 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4159 def rri : Ii8<0xC4, MRMSrcReg,
4160 (outs VR128:$dst), (ins VR128:$src1,
4161 GR32:$src2, i32i8imm:$src3),
4163 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4164 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4166 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4167 def rmi : Ii8<0xC4, MRMSrcMem,
4168 (outs VR128:$dst), (ins VR128:$src1,
4169 i16mem:$src2, i32i8imm:$src3),
4171 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4172 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4174 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4175 imm:$src3))], IIC_SSE_PINSRW>;
4179 let Predicates = [HasAVX] in
4180 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4181 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4182 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4183 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4184 imm:$src2))]>, TB, OpSize, VEX;
4185 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4186 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4187 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4188 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4189 imm:$src2))], IIC_SSE_PEXTRW>;
4192 let Predicates = [HasAVX] in {
4193 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4194 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4195 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4196 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4197 []>, TB, OpSize, VEX_4V;
4200 let Constraints = "$src1 = $dst" in
4201 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4203 } // ExeDomain = SSEPackedInt
4205 //===---------------------------------------------------------------------===//
4206 // SSE2 - Packed Mask Creation
4207 //===---------------------------------------------------------------------===//
4209 let ExeDomain = SSEPackedInt in {
4211 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4212 "pmovmskb\t{$src, $dst|$dst, $src}",
4213 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4214 IIC_SSE_MOVMSK>, VEX;
4215 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4216 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4218 let Predicates = [HasAVX2] in {
4219 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4220 "pmovmskb\t{$src, $dst|$dst, $src}",
4221 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4222 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4223 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4226 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4227 "pmovmskb\t{$src, $dst|$dst, $src}",
4228 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4231 } // ExeDomain = SSEPackedInt
4233 //===---------------------------------------------------------------------===//
4234 // SSE2 - Conditional Store
4235 //===---------------------------------------------------------------------===//
4237 let ExeDomain = SSEPackedInt in {
4240 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4241 (ins VR128:$src, VR128:$mask),
4242 "maskmovdqu\t{$mask, $src|$src, $mask}",
4243 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4244 IIC_SSE_MASKMOV>, VEX;
4246 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4247 (ins VR128:$src, VR128:$mask),
4248 "maskmovdqu\t{$mask, $src|$src, $mask}",
4249 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4250 IIC_SSE_MASKMOV>, VEX;
4253 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4254 "maskmovdqu\t{$mask, $src|$src, $mask}",
4255 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4258 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4259 "maskmovdqu\t{$mask, $src|$src, $mask}",
4260 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4263 } // ExeDomain = SSEPackedInt
4265 //===---------------------------------------------------------------------===//
4266 // SSE2 - Move Doubleword
4267 //===---------------------------------------------------------------------===//
4269 //===---------------------------------------------------------------------===//
4270 // Move Int Doubleword to Packed Double Int
4272 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4273 "movd\t{$src, $dst|$dst, $src}",
4275 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4277 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4278 "movd\t{$src, $dst|$dst, $src}",
4280 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4283 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4284 "mov{d|q}\t{$src, $dst|$dst, $src}",
4286 (v2i64 (scalar_to_vector GR64:$src)))],
4287 IIC_SSE_MOVDQ>, VEX;
4288 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4289 "mov{d|q}\t{$src, $dst|$dst, $src}",
4290 [(set FR64:$dst, (bitconvert GR64:$src))],
4291 IIC_SSE_MOVDQ>, VEX;
4293 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4294 "movd\t{$src, $dst|$dst, $src}",
4296 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4297 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4298 "movd\t{$src, $dst|$dst, $src}",
4300 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4302 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4303 "mov{d|q}\t{$src, $dst|$dst, $src}",
4305 (v2i64 (scalar_to_vector GR64:$src)))],
4307 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4308 "mov{d|q}\t{$src, $dst|$dst, $src}",
4309 [(set FR64:$dst, (bitconvert GR64:$src))],
4312 //===---------------------------------------------------------------------===//
4313 // Move Int Doubleword to Single Scalar
4315 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4316 "movd\t{$src, $dst|$dst, $src}",
4317 [(set FR32:$dst, (bitconvert GR32:$src))],
4318 IIC_SSE_MOVDQ>, VEX;
4320 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4321 "movd\t{$src, $dst|$dst, $src}",
4322 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4325 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4326 "movd\t{$src, $dst|$dst, $src}",
4327 [(set FR32:$dst, (bitconvert GR32:$src))],
4330 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4331 "movd\t{$src, $dst|$dst, $src}",
4332 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4335 //===---------------------------------------------------------------------===//
4336 // Move Packed Doubleword Int to Packed Double Int
4338 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4339 "movd\t{$src, $dst|$dst, $src}",
4340 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4341 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4342 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4343 (ins i32mem:$dst, VR128:$src),
4344 "movd\t{$src, $dst|$dst, $src}",
4345 [(store (i32 (vector_extract (v4i32 VR128:$src),
4346 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4348 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4349 "movd\t{$src, $dst|$dst, $src}",
4350 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4351 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4352 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4353 "movd\t{$src, $dst|$dst, $src}",
4354 [(store (i32 (vector_extract (v4i32 VR128:$src),
4355 (iPTR 0))), addr:$dst)],
4358 //===---------------------------------------------------------------------===//
4359 // Move Packed Doubleword Int first element to Doubleword Int
4361 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4362 "vmov{d|q}\t{$src, $dst|$dst, $src}",
4363 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4366 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4368 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4369 "mov{d|q}\t{$src, $dst|$dst, $src}",
4370 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4374 //===---------------------------------------------------------------------===//
4375 // Bitcast FR64 <-> GR64
4377 let Predicates = [HasAVX] in
4378 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4379 "vmovq\t{$src, $dst|$dst, $src}",
4380 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4382 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4383 "mov{d|q}\t{$src, $dst|$dst, $src}",
4384 [(set GR64:$dst, (bitconvert FR64:$src))],
4385 IIC_SSE_MOVDQ>, VEX;
4386 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4387 "movq\t{$src, $dst|$dst, $src}",
4388 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4389 IIC_SSE_MOVDQ>, VEX;
4391 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4392 "movq\t{$src, $dst|$dst, $src}",
4393 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4395 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4396 "mov{d|q}\t{$src, $dst|$dst, $src}",
4397 [(set GR64:$dst, (bitconvert FR64:$src))],
4399 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4400 "movq\t{$src, $dst|$dst, $src}",
4401 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4404 //===---------------------------------------------------------------------===//
4405 // Move Scalar Single to Double Int
4407 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4408 "movd\t{$src, $dst|$dst, $src}",
4409 [(set GR32:$dst, (bitconvert FR32:$src))],
4410 IIC_SSE_MOVD_ToGP>, VEX;
4411 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4412 "movd\t{$src, $dst|$dst, $src}",
4413 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4414 IIC_SSE_MOVDQ>, VEX;
4415 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4416 "movd\t{$src, $dst|$dst, $src}",
4417 [(set GR32:$dst, (bitconvert FR32:$src))],
4419 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4420 "movd\t{$src, $dst|$dst, $src}",
4421 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4424 //===---------------------------------------------------------------------===//
4425 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4427 let AddedComplexity = 15 in {
4428 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4429 "movd\t{$src, $dst|$dst, $src}",
4430 [(set VR128:$dst, (v4i32 (X86vzmovl
4431 (v4i32 (scalar_to_vector GR32:$src)))))],
4432 IIC_SSE_MOVDQ>, VEX;
4433 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4434 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4435 [(set VR128:$dst, (v2i64 (X86vzmovl
4436 (v2i64 (scalar_to_vector GR64:$src)))))],
4440 let AddedComplexity = 15 in {
4441 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4442 "movd\t{$src, $dst|$dst, $src}",
4443 [(set VR128:$dst, (v4i32 (X86vzmovl
4444 (v4i32 (scalar_to_vector GR32:$src)))))],
4446 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4447 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4448 [(set VR128:$dst, (v2i64 (X86vzmovl
4449 (v2i64 (scalar_to_vector GR64:$src)))))],
4453 let AddedComplexity = 20 in {
4454 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4455 "movd\t{$src, $dst|$dst, $src}",
4457 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4458 (loadi32 addr:$src))))))],
4459 IIC_SSE_MOVDQ>, VEX;
4460 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4461 "movd\t{$src, $dst|$dst, $src}",
4463 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4464 (loadi32 addr:$src))))))],
4468 let Predicates = [HasAVX] in {
4469 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4470 let AddedComplexity = 20 in {
4471 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4472 (VMOVZDI2PDIrm addr:$src)>;
4473 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4474 (VMOVZDI2PDIrm addr:$src)>;
4476 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4477 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4478 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4479 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4480 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4481 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4482 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4485 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4486 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4487 (MOVZDI2PDIrm addr:$src)>;
4488 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4489 (MOVZDI2PDIrm addr:$src)>;
4492 // These are the correct encodings of the instructions so that we know how to
4493 // read correct assembly, even though we continue to emit the wrong ones for
4494 // compatibility with Darwin's buggy assembler.
4495 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4496 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4497 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4498 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4499 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4500 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4501 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4502 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4503 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4504 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4505 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4506 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4508 //===---------------------------------------------------------------------===//
4509 // SSE2 - Move Quadword
4510 //===---------------------------------------------------------------------===//
4512 //===---------------------------------------------------------------------===//
4513 // Move Quadword Int to Packed Quadword Int
4515 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4516 "vmovq\t{$src, $dst|$dst, $src}",
4518 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4519 VEX, Requires<[HasAVX]>;
4520 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4521 "movq\t{$src, $dst|$dst, $src}",
4523 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4525 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4527 //===---------------------------------------------------------------------===//
4528 // Move Packed Quadword Int to Quadword Int
4530 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4531 "movq\t{$src, $dst|$dst, $src}",
4532 [(store (i64 (vector_extract (v2i64 VR128:$src),
4533 (iPTR 0))), addr:$dst)],
4534 IIC_SSE_MOVDQ>, VEX;
4535 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4536 "movq\t{$src, $dst|$dst, $src}",
4537 [(store (i64 (vector_extract (v2i64 VR128:$src),
4538 (iPTR 0))), addr:$dst)],
4541 //===---------------------------------------------------------------------===//
4542 // Store / copy lower 64-bits of a XMM register.
4544 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4545 "movq\t{$src, $dst|$dst, $src}",
4546 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4547 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4548 "movq\t{$src, $dst|$dst, $src}",
4549 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4552 let AddedComplexity = 20 in
4553 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4554 "vmovq\t{$src, $dst|$dst, $src}",
4556 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4557 (loadi64 addr:$src))))))],
4559 XS, VEX, Requires<[HasAVX]>;
4561 let AddedComplexity = 20 in
4562 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4563 "movq\t{$src, $dst|$dst, $src}",
4565 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4566 (loadi64 addr:$src))))))],
4568 XS, Requires<[UseSSE2]>;
4570 let Predicates = [HasAVX], AddedComplexity = 20 in {
4571 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4572 (VMOVZQI2PQIrm addr:$src)>;
4573 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4574 (VMOVZQI2PQIrm addr:$src)>;
4575 def : Pat<(v2i64 (X86vzload addr:$src)),
4576 (VMOVZQI2PQIrm addr:$src)>;
4579 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4580 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4581 (MOVZQI2PQIrm addr:$src)>;
4582 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4583 (MOVZQI2PQIrm addr:$src)>;
4584 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4587 let Predicates = [HasAVX] in {
4588 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4589 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4590 def : Pat<(v4i64 (X86vzload addr:$src)),
4591 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4594 //===---------------------------------------------------------------------===//
4595 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4596 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4598 let AddedComplexity = 15 in
4599 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4600 "vmovq\t{$src, $dst|$dst, $src}",
4601 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4603 XS, VEX, Requires<[HasAVX]>;
4604 let AddedComplexity = 15 in
4605 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4606 "movq\t{$src, $dst|$dst, $src}",
4607 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4609 XS, Requires<[UseSSE2]>;
4611 let AddedComplexity = 20 in
4612 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4613 "vmovq\t{$src, $dst|$dst, $src}",
4614 [(set VR128:$dst, (v2i64 (X86vzmovl
4615 (loadv2i64 addr:$src))))],
4617 XS, VEX, Requires<[HasAVX]>;
4618 let AddedComplexity = 20 in {
4619 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4620 "movq\t{$src, $dst|$dst, $src}",
4621 [(set VR128:$dst, (v2i64 (X86vzmovl
4622 (loadv2i64 addr:$src))))],
4624 XS, Requires<[UseSSE2]>;
4627 let AddedComplexity = 20 in {
4628 let Predicates = [HasAVX] in {
4629 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4630 (VMOVZPQILo2PQIrm addr:$src)>;
4631 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4632 (VMOVZPQILo2PQIrr VR128:$src)>;
4634 let Predicates = [UseSSE2] in {
4635 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4636 (MOVZPQILo2PQIrm addr:$src)>;
4637 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4638 (MOVZPQILo2PQIrr VR128:$src)>;
4642 // Instructions to match in the assembler
4643 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4644 "movq\t{$src, $dst|$dst, $src}", [],
4645 IIC_SSE_MOVDQ>, VEX, VEX_W;
4646 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4647 "movq\t{$src, $dst|$dst, $src}", [],
4648 IIC_SSE_MOVDQ>, VEX, VEX_W;
4649 // Recognize "movd" with GR64 destination, but encode as a "movq"
4650 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4651 "movd\t{$src, $dst|$dst, $src}", [],
4652 IIC_SSE_MOVDQ>, VEX, VEX_W;
4654 // Instructions for the disassembler
4655 // xr = XMM register
4658 let Predicates = [HasAVX] in
4659 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4660 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4661 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4662 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4664 //===---------------------------------------------------------------------===//
4665 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4666 //===---------------------------------------------------------------------===//
4667 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4668 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4669 X86MemOperand x86memop> {
4670 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4671 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4672 [(set RC:$dst, (vt (OpNode RC:$src)))],
4674 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4675 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4676 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4680 let Predicates = [HasAVX] in {
4681 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4682 v4f32, VR128, memopv4f32, f128mem>, VEX;
4683 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4684 v4f32, VR128, memopv4f32, f128mem>, VEX;
4685 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4686 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4687 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4688 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4690 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4691 memopv4f32, f128mem>;
4692 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4693 memopv4f32, f128mem>;
4695 let Predicates = [HasAVX] in {
4696 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4697 (VMOVSHDUPrr VR128:$src)>;
4698 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4699 (VMOVSHDUPrm addr:$src)>;
4700 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4701 (VMOVSLDUPrr VR128:$src)>;
4702 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4703 (VMOVSLDUPrm addr:$src)>;
4704 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4705 (VMOVSHDUPYrr VR256:$src)>;
4706 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4707 (VMOVSHDUPYrm addr:$src)>;
4708 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4709 (VMOVSLDUPYrr VR256:$src)>;
4710 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4711 (VMOVSLDUPYrm addr:$src)>;
4714 let Predicates = [UseSSE3] in {
4715 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4716 (MOVSHDUPrr VR128:$src)>;
4717 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4718 (MOVSHDUPrm addr:$src)>;
4719 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4720 (MOVSLDUPrr VR128:$src)>;
4721 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4722 (MOVSLDUPrm addr:$src)>;
4725 //===---------------------------------------------------------------------===//
4726 // SSE3 - Replicate Double FP - MOVDDUP
4727 //===---------------------------------------------------------------------===//
4729 multiclass sse3_replicate_dfp<string OpcodeStr> {
4730 let neverHasSideEffects = 1 in
4731 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4732 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4733 [], IIC_SSE_MOV_LH>;
4734 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4735 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4738 (scalar_to_vector (loadf64 addr:$src)))))],
4742 // FIXME: Merge with above classe when there're patterns for the ymm version
4743 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4744 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4745 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4746 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4747 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4748 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4751 (scalar_to_vector (loadf64 addr:$src)))))]>;
4754 let Predicates = [HasAVX] in {
4755 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4756 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4759 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4761 let Predicates = [HasAVX] in {
4762 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4763 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4764 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4765 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4766 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4767 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4768 def : Pat<(X86Movddup (bc_v2f64
4769 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4770 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4773 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4774 (VMOVDDUPYrm addr:$src)>;
4775 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4776 (VMOVDDUPYrm addr:$src)>;
4777 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4778 (VMOVDDUPYrm addr:$src)>;
4779 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4780 (VMOVDDUPYrr VR256:$src)>;
4783 let Predicates = [UseSSE3] in {
4784 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4785 (MOVDDUPrm addr:$src)>;
4786 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4787 (MOVDDUPrm addr:$src)>;
4788 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4789 (MOVDDUPrm addr:$src)>;
4790 def : Pat<(X86Movddup (bc_v2f64
4791 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4792 (MOVDDUPrm addr:$src)>;
4795 //===---------------------------------------------------------------------===//
4796 // SSE3 - Move Unaligned Integer
4797 //===---------------------------------------------------------------------===//
4799 let Predicates = [HasAVX] in {
4800 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4801 "vlddqu\t{$src, $dst|$dst, $src}",
4802 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4803 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4804 "vlddqu\t{$src, $dst|$dst, $src}",
4805 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
4808 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4809 "lddqu\t{$src, $dst|$dst, $src}",
4810 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4813 //===---------------------------------------------------------------------===//
4814 // SSE3 - Arithmetic
4815 //===---------------------------------------------------------------------===//
4817 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4818 X86MemOperand x86memop, OpndItins itins,
4820 def rr : I<0xD0, MRMSrcReg,
4821 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4823 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4824 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4825 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
4826 def rm : I<0xD0, MRMSrcMem,
4827 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4829 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4830 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4831 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
4834 let Predicates = [HasAVX] in {
4835 let ExeDomain = SSEPackedSingle in {
4836 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4837 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
4838 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4839 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
4841 let ExeDomain = SSEPackedDouble in {
4842 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4843 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
4844 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4845 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
4848 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
4849 let ExeDomain = SSEPackedSingle in
4850 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4851 f128mem, SSE_ALU_F32P>, TB, XD;
4852 let ExeDomain = SSEPackedDouble in
4853 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4854 f128mem, SSE_ALU_F64P>, TB, OpSize;
4857 //===---------------------------------------------------------------------===//
4858 // SSE3 Instructions
4859 //===---------------------------------------------------------------------===//
4862 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4863 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4864 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4866 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4867 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4868 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
4870 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4872 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4873 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4874 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4875 IIC_SSE_HADDSUB_RM>;
4877 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4878 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4879 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4881 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4882 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4883 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
4885 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4887 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4888 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4889 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
4890 IIC_SSE_HADDSUB_RM>;
4893 let Predicates = [HasAVX] in {
4894 let ExeDomain = SSEPackedSingle in {
4895 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4896 X86fhadd, 0>, VEX_4V;
4897 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4898 X86fhsub, 0>, VEX_4V;
4899 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4900 X86fhadd, 0>, VEX_4V, VEX_L;
4901 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4902 X86fhsub, 0>, VEX_4V, VEX_L;
4904 let ExeDomain = SSEPackedDouble in {
4905 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4906 X86fhadd, 0>, VEX_4V;
4907 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4908 X86fhsub, 0>, VEX_4V;
4909 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4910 X86fhadd, 0>, VEX_4V, VEX_L;
4911 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4912 X86fhsub, 0>, VEX_4V, VEX_L;
4916 let Constraints = "$src1 = $dst" in {
4917 let ExeDomain = SSEPackedSingle in {
4918 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
4919 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
4921 let ExeDomain = SSEPackedDouble in {
4922 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
4923 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
4927 //===---------------------------------------------------------------------===//
4928 // SSSE3 - Packed Absolute Instructions
4929 //===---------------------------------------------------------------------===//
4932 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4933 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4934 Intrinsic IntId128> {
4935 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4937 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4938 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
4941 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4943 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4946 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
4950 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4951 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
4952 Intrinsic IntId256> {
4953 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4956 [(set VR256:$dst, (IntId256 VR256:$src))]>,
4959 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
4961 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4964 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
4967 let Predicates = [HasAVX] in {
4968 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
4969 int_x86_ssse3_pabs_b_128>, VEX;
4970 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
4971 int_x86_ssse3_pabs_w_128>, VEX;
4972 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
4973 int_x86_ssse3_pabs_d_128>, VEX;
4976 let Predicates = [HasAVX2] in {
4977 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
4978 int_x86_avx2_pabs_b>, VEX, VEX_L;
4979 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
4980 int_x86_avx2_pabs_w>, VEX, VEX_L;
4981 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
4982 int_x86_avx2_pabs_d>, VEX, VEX_L;
4985 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
4986 int_x86_ssse3_pabs_b_128>;
4987 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
4988 int_x86_ssse3_pabs_w_128>;
4989 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
4990 int_x86_ssse3_pabs_d_128>;
4992 //===---------------------------------------------------------------------===//
4993 // SSSE3 - Packed Binary Operator Instructions
4994 //===---------------------------------------------------------------------===//
4996 def SSE_PHADDSUBD : OpndItins<
4997 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
4999 def SSE_PHADDSUBSW : OpndItins<
5000 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5002 def SSE_PHADDSUBW : OpndItins<
5003 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5005 def SSE_PSHUFB : OpndItins<
5006 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5008 def SSE_PSIGN : OpndItins<
5009 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5011 def SSE_PMULHRSW : OpndItins<
5012 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5015 /// SS3I_binop_rm - Simple SSSE3 bin op
5016 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5017 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5018 X86MemOperand x86memop, OpndItins itins,
5020 let isCommutable = 1 in
5021 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5022 (ins RC:$src1, RC:$src2),
5024 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5025 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5026 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5028 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5029 (ins RC:$src1, x86memop:$src2),
5031 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5032 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5034 (OpVT (OpNode RC:$src1,
5035 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5038 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5039 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5040 Intrinsic IntId128, OpndItins itins,
5042 let isCommutable = 1 in
5043 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5044 (ins VR128:$src1, VR128:$src2),
5046 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5047 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5048 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5050 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5051 (ins VR128:$src1, i128mem:$src2),
5053 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5054 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5056 (IntId128 VR128:$src1,
5057 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5060 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5061 Intrinsic IntId256> {
5062 let isCommutable = 1 in
5063 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5064 (ins VR256:$src1, VR256:$src2),
5065 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5066 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5068 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5069 (ins VR256:$src1, i256mem:$src2),
5070 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5072 (IntId256 VR256:$src1,
5073 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5076 let ImmT = NoImm, Predicates = [HasAVX] in {
5077 let isCommutable = 0 in {
5078 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5079 memopv2i64, i128mem,
5080 SSE_PHADDSUBW, 0>, VEX_4V;
5081 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5082 memopv2i64, i128mem,
5083 SSE_PHADDSUBD, 0>, VEX_4V;
5084 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5085 memopv2i64, i128mem,
5086 SSE_PHADDSUBW, 0>, VEX_4V;
5087 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5088 memopv2i64, i128mem,
5089 SSE_PHADDSUBD, 0>, VEX_4V;
5090 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5091 memopv2i64, i128mem,
5092 SSE_PSIGN, 0>, VEX_4V;
5093 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5094 memopv2i64, i128mem,
5095 SSE_PSIGN, 0>, VEX_4V;
5096 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5097 memopv2i64, i128mem,
5098 SSE_PSIGN, 0>, VEX_4V;
5099 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5100 memopv2i64, i128mem,
5101 SSE_PSHUFB, 0>, VEX_4V;
5102 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5103 int_x86_ssse3_phadd_sw_128,
5104 SSE_PHADDSUBSW, 0>, VEX_4V;
5105 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5106 int_x86_ssse3_phsub_sw_128,
5107 SSE_PHADDSUBSW, 0>, VEX_4V;
5108 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5109 int_x86_ssse3_pmadd_ub_sw_128,
5110 SSE_PMADD, 0>, VEX_4V;
5112 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5113 int_x86_ssse3_pmul_hr_sw_128,
5114 SSE_PMULHRSW, 0>, VEX_4V;
5117 let ImmT = NoImm, Predicates = [HasAVX2] in {
5118 let isCommutable = 0 in {
5119 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5120 memopv4i64, i256mem,
5121 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5122 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5123 memopv4i64, i256mem,
5124 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5125 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5126 memopv4i64, i256mem,
5127 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5128 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5129 memopv4i64, i256mem,
5130 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5131 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5132 memopv4i64, i256mem,
5133 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5134 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5135 memopv4i64, i256mem,
5136 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5137 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5138 memopv4i64, i256mem,
5139 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5140 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5141 memopv4i64, i256mem,
5142 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5143 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5144 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5145 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5146 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5147 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5148 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5150 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5151 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5154 // None of these have i8 immediate fields.
5155 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5156 let isCommutable = 0 in {
5157 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5158 memopv2i64, i128mem, SSE_PHADDSUBW>;
5159 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5160 memopv2i64, i128mem, SSE_PHADDSUBD>;
5161 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5162 memopv2i64, i128mem, SSE_PHADDSUBW>;
5163 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5164 memopv2i64, i128mem, SSE_PHADDSUBD>;
5165 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5166 memopv2i64, i128mem, SSE_PSIGN>;
5167 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5168 memopv2i64, i128mem, SSE_PSIGN>;
5169 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5170 memopv2i64, i128mem, SSE_PSIGN>;
5171 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5172 memopv2i64, i128mem, SSE_PSHUFB>;
5173 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5174 int_x86_ssse3_phadd_sw_128,
5176 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5177 int_x86_ssse3_phsub_sw_128,
5179 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5180 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5182 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5183 int_x86_ssse3_pmul_hr_sw_128,
5187 //===---------------------------------------------------------------------===//
5188 // SSSE3 - Packed Align Instruction Patterns
5189 //===---------------------------------------------------------------------===//
5191 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5192 let neverHasSideEffects = 1 in {
5193 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5194 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5196 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5198 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5199 [], IIC_SSE_PALIGNR>, OpSize;
5201 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5202 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5204 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5206 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5207 [], IIC_SSE_PALIGNR>, OpSize;
5211 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5212 let neverHasSideEffects = 1 in {
5213 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5214 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5216 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5219 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5220 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5222 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5227 let Predicates = [HasAVX] in
5228 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5229 let Predicates = [HasAVX2] in
5230 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V, VEX_L;
5231 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5232 defm PALIGN : ssse3_palign<"palignr">;
5234 let Predicates = [HasAVX2] in {
5235 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5236 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5237 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5238 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5239 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5240 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5241 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5242 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5245 let Predicates = [HasAVX] in {
5246 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5247 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5248 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5249 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5250 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5251 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5252 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5253 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5256 let Predicates = [UseSSSE3] in {
5257 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5258 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5259 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5260 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5261 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5262 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5263 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5264 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5267 //===---------------------------------------------------------------------===//
5268 // SSSE3 - Thread synchronization
5269 //===---------------------------------------------------------------------===//
5271 let usesCustomInserter = 1 in {
5272 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5273 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5274 Requires<[HasSSE3]>;
5277 let Uses = [EAX, ECX, EDX] in
5278 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5279 TB, Requires<[HasSSE3]>;
5280 let Uses = [ECX, EAX] in
5281 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5282 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5283 TB, Requires<[HasSSE3]>;
5285 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5286 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5288 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5289 Requires<[In32BitMode]>;
5290 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5291 Requires<[In64BitMode]>;
5293 //===----------------------------------------------------------------------===//
5294 // SSE4.1 - Packed Move with Sign/Zero Extend
5295 //===----------------------------------------------------------------------===//
5297 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5298 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5299 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5300 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5302 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5303 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5305 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5309 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5311 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5312 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5313 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5315 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5316 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5317 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5320 let Predicates = [HasAVX] in {
5321 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5323 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5325 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5327 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5329 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5331 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5335 let Predicates = [HasAVX2] in {
5336 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5337 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5338 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5339 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5340 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5341 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5342 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5343 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5344 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5345 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5346 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5347 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5350 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5351 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5352 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5353 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5354 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5355 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5357 let Predicates = [HasAVX] in {
5358 // Common patterns involving scalar load.
5359 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5360 (VPMOVSXBWrm addr:$src)>;
5361 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5362 (VPMOVSXBWrm addr:$src)>;
5363 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5364 (VPMOVSXBWrm addr:$src)>;
5366 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5367 (VPMOVSXWDrm addr:$src)>;
5368 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5369 (VPMOVSXWDrm addr:$src)>;
5370 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5371 (VPMOVSXWDrm addr:$src)>;
5373 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5374 (VPMOVSXDQrm addr:$src)>;
5375 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5376 (VPMOVSXDQrm addr:$src)>;
5377 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5378 (VPMOVSXDQrm addr:$src)>;
5380 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5381 (VPMOVZXBWrm addr:$src)>;
5382 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5383 (VPMOVZXBWrm addr:$src)>;
5384 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5385 (VPMOVZXBWrm addr:$src)>;
5387 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5388 (VPMOVZXWDrm addr:$src)>;
5389 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5390 (VPMOVZXWDrm addr:$src)>;
5391 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5392 (VPMOVZXWDrm addr:$src)>;
5394 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5395 (VPMOVZXDQrm addr:$src)>;
5396 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5397 (VPMOVZXDQrm addr:$src)>;
5398 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5399 (VPMOVZXDQrm addr:$src)>;
5402 let Predicates = [UseSSE41] in {
5403 // Common patterns involving scalar load.
5404 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5405 (PMOVSXBWrm addr:$src)>;
5406 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5407 (PMOVSXBWrm addr:$src)>;
5408 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5409 (PMOVSXBWrm addr:$src)>;
5411 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5412 (PMOVSXWDrm addr:$src)>;
5413 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5414 (PMOVSXWDrm addr:$src)>;
5415 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5416 (PMOVSXWDrm addr:$src)>;
5418 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5419 (PMOVSXDQrm addr:$src)>;
5420 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5421 (PMOVSXDQrm addr:$src)>;
5422 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5423 (PMOVSXDQrm addr:$src)>;
5425 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5426 (PMOVZXBWrm addr:$src)>;
5427 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5428 (PMOVZXBWrm addr:$src)>;
5429 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5430 (PMOVZXBWrm addr:$src)>;
5432 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5433 (PMOVZXWDrm addr:$src)>;
5434 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5435 (PMOVZXWDrm addr:$src)>;
5436 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5437 (PMOVZXWDrm addr:$src)>;
5439 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5440 (PMOVZXDQrm addr:$src)>;
5441 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5442 (PMOVZXDQrm addr:$src)>;
5443 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5444 (PMOVZXDQrm addr:$src)>;
5447 let Predicates = [HasAVX2] in {
5448 let AddedComplexity = 15 in {
5449 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5450 (VPMOVZXDQYrr VR128:$src)>;
5451 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5452 (VPMOVZXWDYrr VR128:$src)>;
5455 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5456 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5459 let Predicates = [HasAVX] in {
5460 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5461 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5464 let Predicates = [UseSSE41] in {
5465 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5466 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5470 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5471 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5472 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5473 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5475 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5476 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5478 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5482 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5484 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5485 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5486 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5488 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5489 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5491 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5495 let Predicates = [HasAVX] in {
5496 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5498 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5500 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5502 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5506 let Predicates = [HasAVX2] in {
5507 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5508 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5509 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5510 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5511 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5512 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5513 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5514 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5517 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5518 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5519 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5520 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5522 let Predicates = [HasAVX] in {
5523 // Common patterns involving scalar load
5524 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5525 (VPMOVSXBDrm addr:$src)>;
5526 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5527 (VPMOVSXWQrm addr:$src)>;
5529 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5530 (VPMOVZXBDrm addr:$src)>;
5531 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5532 (VPMOVZXWQrm addr:$src)>;
5535 let Predicates = [UseSSE41] in {
5536 // Common patterns involving scalar load
5537 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5538 (PMOVSXBDrm addr:$src)>;
5539 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5540 (PMOVSXWQrm addr:$src)>;
5542 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5543 (PMOVZXBDrm addr:$src)>;
5544 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5545 (PMOVZXWQrm addr:$src)>;
5548 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5549 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5550 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5551 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5553 // Expecting a i16 load any extended to i32 value.
5554 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5555 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5556 [(set VR128:$dst, (IntId (bitconvert
5557 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5561 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5563 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5564 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5565 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5567 // Expecting a i16 load any extended to i32 value.
5568 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5569 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5570 [(set VR256:$dst, (IntId (bitconvert
5571 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5575 let Predicates = [HasAVX] in {
5576 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5578 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5581 let Predicates = [HasAVX2] in {
5582 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5583 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5584 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5585 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5587 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5588 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5590 let Predicates = [HasAVX2] in {
5591 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5592 (VPMOVSXWDYrm addr:$src)>;
5593 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5594 (VPMOVSXDQYrm addr:$src)>;
5596 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5597 (scalar_to_vector (loadi64 addr:$src))))))),
5598 (VPMOVSXBDYrm addr:$src)>;
5599 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5600 (scalar_to_vector (loadf64 addr:$src))))))),
5601 (VPMOVSXBDYrm addr:$src)>;
5603 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5604 (scalar_to_vector (loadi64 addr:$src))))))),
5605 (VPMOVSXWQYrm addr:$src)>;
5606 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5607 (scalar_to_vector (loadf64 addr:$src))))))),
5608 (VPMOVSXWQYrm addr:$src)>;
5610 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5611 (scalar_to_vector (loadi32 addr:$src))))))),
5612 (VPMOVSXBQYrm addr:$src)>;
5615 let Predicates = [HasAVX] in {
5616 // Common patterns involving scalar load
5617 def : Pat<(int_x86_sse41_pmovsxbq
5618 (bitconvert (v4i32 (X86vzmovl
5619 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5620 (VPMOVSXBQrm addr:$src)>;
5622 def : Pat<(int_x86_sse41_pmovzxbq
5623 (bitconvert (v4i32 (X86vzmovl
5624 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5625 (VPMOVZXBQrm addr:$src)>;
5628 let Predicates = [UseSSE41] in {
5629 // Common patterns involving scalar load
5630 def : Pat<(int_x86_sse41_pmovsxbq
5631 (bitconvert (v4i32 (X86vzmovl
5632 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5633 (PMOVSXBQrm addr:$src)>;
5635 def : Pat<(int_x86_sse41_pmovzxbq
5636 (bitconvert (v4i32 (X86vzmovl
5637 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5638 (PMOVZXBQrm addr:$src)>;
5640 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5641 (scalar_to_vector (loadi64 addr:$src))))))),
5642 (PMOVSXWDrm addr:$src)>;
5643 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5644 (scalar_to_vector (loadf64 addr:$src))))))),
5645 (PMOVSXWDrm addr:$src)>;
5646 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5647 (scalar_to_vector (loadi32 addr:$src))))))),
5648 (PMOVSXBDrm addr:$src)>;
5649 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5650 (scalar_to_vector (loadi32 addr:$src))))))),
5651 (PMOVSXWQrm addr:$src)>;
5652 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5653 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5654 (PMOVSXBQrm addr:$src)>;
5655 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5656 (scalar_to_vector (loadi64 addr:$src))))))),
5657 (PMOVSXDQrm addr:$src)>;
5658 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5659 (scalar_to_vector (loadf64 addr:$src))))))),
5660 (PMOVSXDQrm addr:$src)>;
5661 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5662 (scalar_to_vector (loadi64 addr:$src))))))),
5663 (PMOVSXBWrm addr:$src)>;
5664 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5665 (scalar_to_vector (loadf64 addr:$src))))))),
5666 (PMOVSXBWrm addr:$src)>;
5669 let Predicates = [HasAVX2] in {
5670 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5671 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5672 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5674 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5675 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5677 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5679 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5680 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5681 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5682 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5683 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5684 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5686 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5687 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5688 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5689 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5691 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5692 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5695 let Predicates = [HasAVX] in {
5696 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5697 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5698 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5700 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5701 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5703 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5705 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5706 (VPMOVZXBWrm addr:$src)>;
5707 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5708 (VPMOVZXBWrm addr:$src)>;
5709 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5710 (VPMOVZXBDrm addr:$src)>;
5711 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5712 (VPMOVZXBQrm addr:$src)>;
5714 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5715 (VPMOVZXWDrm addr:$src)>;
5716 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5717 (VPMOVZXWDrm addr:$src)>;
5718 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5719 (VPMOVZXWQrm addr:$src)>;
5721 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5722 (VPMOVZXDQrm addr:$src)>;
5723 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5724 (VPMOVZXDQrm addr:$src)>;
5725 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5726 (VPMOVZXDQrm addr:$src)>;
5728 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5729 (scalar_to_vector (loadi64 addr:$src))))))),
5730 (VPMOVSXWDrm addr:$src)>;
5731 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5732 (scalar_to_vector (loadi64 addr:$src))))))),
5733 (VPMOVSXDQrm addr:$src)>;
5734 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5735 (scalar_to_vector (loadf64 addr:$src))))))),
5736 (VPMOVSXWDrm addr:$src)>;
5737 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5738 (scalar_to_vector (loadf64 addr:$src))))))),
5739 (VPMOVSXDQrm addr:$src)>;
5740 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5741 (scalar_to_vector (loadi64 addr:$src))))))),
5742 (VPMOVSXBWrm addr:$src)>;
5743 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5744 (scalar_to_vector (loadf64 addr:$src))))))),
5745 (VPMOVSXBWrm addr:$src)>;
5747 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5748 (scalar_to_vector (loadi32 addr:$src))))))),
5749 (VPMOVSXBDrm addr:$src)>;
5750 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5751 (scalar_to_vector (loadi32 addr:$src))))))),
5752 (VPMOVSXWQrm addr:$src)>;
5753 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5754 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5755 (VPMOVSXBQrm addr:$src)>;
5758 let Predicates = [UseSSE41] in {
5759 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
5760 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
5761 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
5763 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
5764 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
5766 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
5768 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5769 (PMOVZXBWrm addr:$src)>;
5770 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5771 (PMOVZXBWrm addr:$src)>;
5772 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5773 (PMOVZXBDrm addr:$src)>;
5774 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5775 (PMOVZXBQrm addr:$src)>;
5777 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5778 (PMOVZXWDrm addr:$src)>;
5779 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5780 (PMOVZXWDrm addr:$src)>;
5781 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5782 (PMOVZXWQrm addr:$src)>;
5784 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5785 (PMOVZXDQrm addr:$src)>;
5786 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5787 (PMOVZXDQrm addr:$src)>;
5788 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5789 (PMOVZXDQrm addr:$src)>;
5792 //===----------------------------------------------------------------------===//
5793 // SSE4.1 - Extract Instructions
5794 //===----------------------------------------------------------------------===//
5796 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5797 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5798 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5799 (ins VR128:$src1, i32i8imm:$src2),
5800 !strconcat(OpcodeStr,
5801 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5802 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5804 let neverHasSideEffects = 1, mayStore = 1 in
5805 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5806 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5807 !strconcat(OpcodeStr,
5808 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5811 // There's an AssertZext in the way of writing the store pattern
5812 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5815 let Predicates = [HasAVX] in {
5816 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5817 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5818 (ins VR128:$src1, i32i8imm:$src2),
5819 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5822 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5825 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5826 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5827 let neverHasSideEffects = 1, mayStore = 1 in
5828 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5829 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5830 !strconcat(OpcodeStr,
5831 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5834 // There's an AssertZext in the way of writing the store pattern
5835 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5838 let Predicates = [HasAVX] in
5839 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5841 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5844 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5845 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5846 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5847 (ins VR128:$src1, i32i8imm:$src2),
5848 !strconcat(OpcodeStr,
5849 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5851 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5852 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5853 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5854 !strconcat(OpcodeStr,
5855 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5856 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5857 addr:$dst)]>, OpSize;
5860 let Predicates = [HasAVX] in
5861 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5863 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5865 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5866 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5867 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5868 (ins VR128:$src1, i32i8imm:$src2),
5869 !strconcat(OpcodeStr,
5870 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5872 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5873 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5874 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5875 !strconcat(OpcodeStr,
5876 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5877 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5878 addr:$dst)]>, OpSize, REX_W;
5881 let Predicates = [HasAVX] in
5882 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5884 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5886 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5888 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5889 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5890 (ins VR128:$src1, i32i8imm:$src2),
5891 !strconcat(OpcodeStr,
5892 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5894 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5896 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5897 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5898 !strconcat(OpcodeStr,
5899 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5900 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5901 addr:$dst)]>, OpSize;
5904 let ExeDomain = SSEPackedSingle in {
5905 let Predicates = [HasAVX] in {
5906 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5907 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5908 (ins VR128:$src1, i32i8imm:$src2),
5909 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5912 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5915 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5916 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5919 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5921 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5924 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5925 Requires<[UseSSE41]>;
5927 //===----------------------------------------------------------------------===//
5928 // SSE4.1 - Insert Instructions
5929 //===----------------------------------------------------------------------===//
5931 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5932 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5933 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5935 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5937 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5939 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5940 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5941 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5943 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5945 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5947 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5948 imm:$src3))]>, OpSize;
5951 let Predicates = [HasAVX] in
5952 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5953 let Constraints = "$src1 = $dst" in
5954 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5956 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5957 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5958 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5960 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5962 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5964 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5966 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5967 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5969 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5971 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5973 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5974 imm:$src3)))]>, OpSize;
5977 let Predicates = [HasAVX] in
5978 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5979 let Constraints = "$src1 = $dst" in
5980 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5982 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5983 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5984 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5986 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5988 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5990 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5992 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5993 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5995 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5997 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5999 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6000 imm:$src3)))]>, OpSize;
6003 let Predicates = [HasAVX] in
6004 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6005 let Constraints = "$src1 = $dst" in
6006 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6008 // insertps has a few different modes, there's the first two here below which
6009 // are optimized inserts that won't zero arbitrary elements in the destination
6010 // vector. The next one matches the intrinsic and could zero arbitrary elements
6011 // in the target vector.
6012 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6013 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6014 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6016 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6018 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6020 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6022 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6023 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6025 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6027 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6029 (X86insrtps VR128:$src1,
6030 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6031 imm:$src3))]>, OpSize;
6034 let ExeDomain = SSEPackedSingle in {
6035 let Predicates = [HasAVX] in
6036 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6037 let Constraints = "$src1 = $dst" in
6038 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6041 //===----------------------------------------------------------------------===//
6042 // SSE4.1 - Round Instructions
6043 //===----------------------------------------------------------------------===//
6045 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6046 X86MemOperand x86memop, RegisterClass RC,
6047 PatFrag mem_frag32, PatFrag mem_frag64,
6048 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6049 let ExeDomain = SSEPackedSingle in {
6050 // Intrinsic operation, reg.
6051 // Vector intrinsic operation, reg
6052 def PSr : SS4AIi8<opcps, MRMSrcReg,
6053 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6054 !strconcat(OpcodeStr,
6055 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6056 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6059 // Vector intrinsic operation, mem
6060 def PSm : SS4AIi8<opcps, MRMSrcMem,
6061 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6062 !strconcat(OpcodeStr,
6063 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6065 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6067 } // ExeDomain = SSEPackedSingle
6069 let ExeDomain = SSEPackedDouble in {
6070 // Vector intrinsic operation, reg
6071 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6072 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6073 !strconcat(OpcodeStr,
6074 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6075 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6078 // Vector intrinsic operation, mem
6079 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6080 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6081 !strconcat(OpcodeStr,
6082 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6084 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6086 } // ExeDomain = SSEPackedDouble
6089 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6092 Intrinsic F64Int, bit Is2Addr = 1> {
6093 let ExeDomain = GenericDomain in {
6095 def SSr : SS4AIi8<opcss, MRMSrcReg,
6096 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6098 !strconcat(OpcodeStr,
6099 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6100 !strconcat(OpcodeStr,
6101 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6104 // Intrinsic operation, reg.
6105 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6106 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6108 !strconcat(OpcodeStr,
6109 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6110 !strconcat(OpcodeStr,
6111 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6112 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6115 // Intrinsic operation, mem.
6116 def SSm : SS4AIi8<opcss, MRMSrcMem,
6117 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6119 !strconcat(OpcodeStr,
6120 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6121 !strconcat(OpcodeStr,
6122 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6124 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6128 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6129 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6131 !strconcat(OpcodeStr,
6132 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6133 !strconcat(OpcodeStr,
6134 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6137 // Intrinsic operation, reg.
6138 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6139 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6141 !strconcat(OpcodeStr,
6142 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6143 !strconcat(OpcodeStr,
6144 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6145 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6148 // Intrinsic operation, mem.
6149 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6150 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6152 !strconcat(OpcodeStr,
6153 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6154 !strconcat(OpcodeStr,
6155 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6157 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6159 } // ExeDomain = GenericDomain
6162 // FP round - roundss, roundps, roundsd, roundpd
6163 let Predicates = [HasAVX] in {
6165 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6166 memopv4f32, memopv2f64,
6167 int_x86_sse41_round_ps,
6168 int_x86_sse41_round_pd>, VEX;
6169 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6170 memopv8f32, memopv4f64,
6171 int_x86_avx_round_ps_256,
6172 int_x86_avx_round_pd_256>, VEX, VEX_L;
6173 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6174 int_x86_sse41_round_ss,
6175 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6177 def : Pat<(ffloor FR32:$src),
6178 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6179 def : Pat<(f64 (ffloor FR64:$src)),
6180 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6181 def : Pat<(f32 (fnearbyint FR32:$src)),
6182 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6183 def : Pat<(f64 (fnearbyint FR64:$src)),
6184 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6185 def : Pat<(f32 (fceil FR32:$src)),
6186 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6187 def : Pat<(f64 (fceil FR64:$src)),
6188 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6189 def : Pat<(f32 (frint FR32:$src)),
6190 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6191 def : Pat<(f64 (frint FR64:$src)),
6192 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6193 def : Pat<(f32 (ftrunc FR32:$src)),
6194 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6195 def : Pat<(f64 (ftrunc FR64:$src)),
6196 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6198 def : Pat<(v4f32 (ffloor VR128:$src)),
6199 (VROUNDPSr VR128:$src, (i32 0x1))>;
6200 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6201 (VROUNDPSr VR128:$src, (i32 0xC))>;
6202 def : Pat<(v4f32 (fceil VR128:$src)),
6203 (VROUNDPSr VR128:$src, (i32 0x2))>;
6204 def : Pat<(v4f32 (frint VR128:$src)),
6205 (VROUNDPSr VR128:$src, (i32 0x4))>;
6206 def : Pat<(v4f32 (ftrunc VR128:$src)),
6207 (VROUNDPSr VR128:$src, (i32 0x3))>;
6209 def : Pat<(v2f64 (ffloor VR128:$src)),
6210 (VROUNDPDr VR128:$src, (i32 0x1))>;
6211 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6212 (VROUNDPDr VR128:$src, (i32 0xC))>;
6213 def : Pat<(v2f64 (fceil VR128:$src)),
6214 (VROUNDPDr VR128:$src, (i32 0x2))>;
6215 def : Pat<(v2f64 (frint VR128:$src)),
6216 (VROUNDPDr VR128:$src, (i32 0x4))>;
6217 def : Pat<(v2f64 (ftrunc VR128:$src)),
6218 (VROUNDPDr VR128:$src, (i32 0x3))>;
6220 def : Pat<(v8f32 (ffloor VR256:$src)),
6221 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6222 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6223 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6224 def : Pat<(v8f32 (fceil VR256:$src)),
6225 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6226 def : Pat<(v8f32 (frint VR256:$src)),
6227 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6228 def : Pat<(v8f32 (ftrunc VR256:$src)),
6229 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6231 def : Pat<(v4f64 (ffloor VR256:$src)),
6232 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6233 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6234 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6235 def : Pat<(v4f64 (fceil VR256:$src)),
6236 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6237 def : Pat<(v4f64 (frint VR256:$src)),
6238 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6239 def : Pat<(v4f64 (ftrunc VR256:$src)),
6240 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6243 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6244 memopv4f32, memopv2f64,
6245 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6246 let Constraints = "$src1 = $dst" in
6247 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6248 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6250 let Predicates = [UseSSE41] in {
6251 def : Pat<(ffloor FR32:$src),
6252 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6253 def : Pat<(f64 (ffloor FR64:$src)),
6254 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6255 def : Pat<(f32 (fnearbyint FR32:$src)),
6256 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6257 def : Pat<(f64 (fnearbyint FR64:$src)),
6258 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6259 def : Pat<(f32 (fceil FR32:$src)),
6260 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6261 def : Pat<(f64 (fceil FR64:$src)),
6262 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6263 def : Pat<(f32 (frint FR32:$src)),
6264 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6265 def : Pat<(f64 (frint FR64:$src)),
6266 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6267 def : Pat<(f32 (ftrunc FR32:$src)),
6268 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6269 def : Pat<(f64 (ftrunc FR64:$src)),
6270 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6272 def : Pat<(v4f32 (ffloor VR128:$src)),
6273 (ROUNDPSr VR128:$src, (i32 0x1))>;
6274 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6275 (ROUNDPSr VR128:$src, (i32 0xC))>;
6276 def : Pat<(v4f32 (fceil VR128:$src)),
6277 (ROUNDPSr VR128:$src, (i32 0x2))>;
6278 def : Pat<(v4f32 (frint VR128:$src)),
6279 (ROUNDPSr VR128:$src, (i32 0x4))>;
6280 def : Pat<(v4f32 (ftrunc VR128:$src)),
6281 (ROUNDPSr VR128:$src, (i32 0x3))>;
6283 def : Pat<(v2f64 (ffloor VR128:$src)),
6284 (ROUNDPDr VR128:$src, (i32 0x1))>;
6285 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6286 (ROUNDPDr VR128:$src, (i32 0xC))>;
6287 def : Pat<(v2f64 (fceil VR128:$src)),
6288 (ROUNDPDr VR128:$src, (i32 0x2))>;
6289 def : Pat<(v2f64 (frint VR128:$src)),
6290 (ROUNDPDr VR128:$src, (i32 0x4))>;
6291 def : Pat<(v2f64 (ftrunc VR128:$src)),
6292 (ROUNDPDr VR128:$src, (i32 0x3))>;
6295 //===----------------------------------------------------------------------===//
6296 // SSE4.1 - Packed Bit Test
6297 //===----------------------------------------------------------------------===//
6299 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6300 // the intel intrinsic that corresponds to this.
6301 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6302 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6303 "vptest\t{$src2, $src1|$src1, $src2}",
6304 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6306 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6307 "vptest\t{$src2, $src1|$src1, $src2}",
6308 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6311 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6312 "vptest\t{$src2, $src1|$src1, $src2}",
6313 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6315 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6316 "vptest\t{$src2, $src1|$src1, $src2}",
6317 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6321 let Defs = [EFLAGS] in {
6322 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6323 "ptest\t{$src2, $src1|$src1, $src2}",
6324 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6326 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6327 "ptest\t{$src2, $src1|$src1, $src2}",
6328 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6332 // The bit test instructions below are AVX only
6333 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6334 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6335 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6336 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6337 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6338 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6339 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6340 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6344 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6345 let ExeDomain = SSEPackedSingle in {
6346 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6347 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6350 let ExeDomain = SSEPackedDouble in {
6351 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6352 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6357 //===----------------------------------------------------------------------===//
6358 // SSE4.1 - Misc Instructions
6359 //===----------------------------------------------------------------------===//
6361 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6362 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6363 "popcnt{w}\t{$src, $dst|$dst, $src}",
6364 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6366 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6367 "popcnt{w}\t{$src, $dst|$dst, $src}",
6368 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6369 (implicit EFLAGS)]>, OpSize, XS;
6371 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6372 "popcnt{l}\t{$src, $dst|$dst, $src}",
6373 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6375 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6376 "popcnt{l}\t{$src, $dst|$dst, $src}",
6377 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6378 (implicit EFLAGS)]>, XS;
6380 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6381 "popcnt{q}\t{$src, $dst|$dst, $src}",
6382 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6384 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6385 "popcnt{q}\t{$src, $dst|$dst, $src}",
6386 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6387 (implicit EFLAGS)]>, XS;
6392 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6393 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6394 Intrinsic IntId128> {
6395 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6398 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6399 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6401 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6404 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6407 let Predicates = [HasAVX] in
6408 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6409 int_x86_sse41_phminposuw>, VEX;
6410 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6411 int_x86_sse41_phminposuw>;
6413 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6414 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6415 Intrinsic IntId128, bit Is2Addr = 1> {
6416 let isCommutable = 1 in
6417 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6418 (ins VR128:$src1, VR128:$src2),
6420 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6421 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6422 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6423 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6424 (ins VR128:$src1, i128mem:$src2),
6426 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6427 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6429 (IntId128 VR128:$src1,
6430 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6433 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6434 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6435 Intrinsic IntId256> {
6436 let isCommutable = 1 in
6437 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6438 (ins VR256:$src1, VR256:$src2),
6439 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6440 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6441 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6442 (ins VR256:$src1, i256mem:$src2),
6443 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6445 (IntId256 VR256:$src1,
6446 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6450 /// SS48I_binop_rm - Simple SSE41 binary operator.
6451 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6452 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6453 X86MemOperand x86memop, bit Is2Addr = 1> {
6454 let isCommutable = 1 in
6455 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6456 (ins RC:$src1, RC:$src2),
6458 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6459 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6460 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6461 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6462 (ins RC:$src1, x86memop:$src2),
6464 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6465 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6467 (OpVT (OpNode RC:$src1,
6468 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6471 let Predicates = [HasAVX] in {
6472 let isCommutable = 0 in
6473 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6475 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6476 memopv2i64, i128mem, 0>, VEX_4V;
6477 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6478 memopv2i64, i128mem, 0>, VEX_4V;
6479 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6480 memopv2i64, i128mem, 0>, VEX_4V;
6481 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6482 memopv2i64, i128mem, 0>, VEX_4V;
6483 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6484 memopv2i64, i128mem, 0>, VEX_4V;
6485 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6486 memopv2i64, i128mem, 0>, VEX_4V;
6487 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6488 memopv2i64, i128mem, 0>, VEX_4V;
6489 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6490 memopv2i64, i128mem, 0>, VEX_4V;
6491 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6495 let Predicates = [HasAVX2] in {
6496 let isCommutable = 0 in
6497 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6498 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6499 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6500 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6501 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6502 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6503 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6504 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6505 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6506 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6507 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6508 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6509 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6510 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6511 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6512 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6513 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6514 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6515 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6516 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6519 let Constraints = "$src1 = $dst" in {
6520 let isCommutable = 0 in
6521 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6522 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6523 memopv2i64, i128mem>;
6524 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6525 memopv2i64, i128mem>;
6526 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6527 memopv2i64, i128mem>;
6528 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6529 memopv2i64, i128mem>;
6530 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6531 memopv2i64, i128mem>;
6532 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6533 memopv2i64, i128mem>;
6534 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6535 memopv2i64, i128mem>;
6536 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6537 memopv2i64, i128mem>;
6538 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6541 let Predicates = [HasAVX] in {
6542 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6543 memopv2i64, i128mem, 0>, VEX_4V;
6544 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6545 memopv2i64, i128mem, 0>, VEX_4V;
6547 let Predicates = [HasAVX2] in {
6548 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6549 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6550 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6551 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6554 let Constraints = "$src1 = $dst" in {
6555 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6556 memopv2i64, i128mem>;
6557 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6558 memopv2i64, i128mem>;
6561 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6562 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6563 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6564 X86MemOperand x86memop, bit Is2Addr = 1> {
6565 let isCommutable = 1 in
6566 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6567 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6569 !strconcat(OpcodeStr,
6570 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6571 !strconcat(OpcodeStr,
6572 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6573 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6575 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6576 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6578 !strconcat(OpcodeStr,
6579 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6580 !strconcat(OpcodeStr,
6581 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6584 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6588 let Predicates = [HasAVX] in {
6589 let isCommutable = 0 in {
6590 let ExeDomain = SSEPackedSingle in {
6591 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6592 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6593 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6594 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6595 f256mem, 0>, VEX_4V, VEX_L;
6597 let ExeDomain = SSEPackedDouble in {
6598 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6599 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6600 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6601 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6602 f256mem, 0>, VEX_4V, VEX_L;
6604 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6605 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6606 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6607 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6609 let ExeDomain = SSEPackedSingle in
6610 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6611 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6612 let ExeDomain = SSEPackedDouble in
6613 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6614 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6615 let ExeDomain = SSEPackedSingle in
6616 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6617 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6620 let Predicates = [HasAVX2] in {
6621 let isCommutable = 0 in {
6622 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6623 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6624 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6625 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6629 let Constraints = "$src1 = $dst" in {
6630 let isCommutable = 0 in {
6631 let ExeDomain = SSEPackedSingle in
6632 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6633 VR128, memopv4f32, f128mem>;
6634 let ExeDomain = SSEPackedDouble in
6635 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6636 VR128, memopv2f64, f128mem>;
6637 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6638 VR128, memopv2i64, i128mem>;
6639 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6640 VR128, memopv2i64, i128mem>;
6642 let ExeDomain = SSEPackedSingle in
6643 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6644 VR128, memopv4f32, f128mem>;
6645 let ExeDomain = SSEPackedDouble in
6646 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6647 VR128, memopv2f64, f128mem>;
6650 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6651 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6652 RegisterClass RC, X86MemOperand x86memop,
6653 PatFrag mem_frag, Intrinsic IntId> {
6654 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6655 (ins RC:$src1, RC:$src2, RC:$src3),
6656 !strconcat(OpcodeStr,
6657 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6658 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6659 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6661 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6662 (ins RC:$src1, x86memop:$src2, RC:$src3),
6663 !strconcat(OpcodeStr,
6664 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6666 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6668 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6671 let Predicates = [HasAVX] in {
6672 let ExeDomain = SSEPackedDouble in {
6673 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6674 memopv2f64, int_x86_sse41_blendvpd>;
6675 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6676 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6677 } // ExeDomain = SSEPackedDouble
6678 let ExeDomain = SSEPackedSingle in {
6679 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6680 memopv4f32, int_x86_sse41_blendvps>;
6681 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6682 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6683 } // ExeDomain = SSEPackedSingle
6684 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6685 memopv2i64, int_x86_sse41_pblendvb>;
6688 let Predicates = [HasAVX2] in {
6689 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6690 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6693 let Predicates = [HasAVX] in {
6694 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6695 (v16i8 VR128:$src2))),
6696 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6697 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6698 (v4i32 VR128:$src2))),
6699 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6700 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6701 (v4f32 VR128:$src2))),
6702 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6703 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6704 (v2i64 VR128:$src2))),
6705 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6706 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6707 (v2f64 VR128:$src2))),
6708 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6709 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6710 (v8i32 VR256:$src2))),
6711 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6712 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6713 (v8f32 VR256:$src2))),
6714 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6715 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6716 (v4i64 VR256:$src2))),
6717 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6718 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6719 (v4f64 VR256:$src2))),
6720 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6722 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6724 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6725 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6727 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6729 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6731 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6732 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6734 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6735 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6737 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6740 let Predicates = [HasAVX2] in {
6741 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6742 (v32i8 VR256:$src2))),
6743 (VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
6744 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6746 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6749 /// SS41I_ternary_int - SSE 4.1 ternary operator
6750 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6751 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6752 X86MemOperand x86memop, Intrinsic IntId> {
6753 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6754 (ins VR128:$src1, VR128:$src2),
6755 !strconcat(OpcodeStr,
6756 "\t{$src2, $dst|$dst, $src2}"),
6757 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6760 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6761 (ins VR128:$src1, x86memop:$src2),
6762 !strconcat(OpcodeStr,
6763 "\t{$src2, $dst|$dst, $src2}"),
6766 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6770 let ExeDomain = SSEPackedDouble in
6771 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
6772 int_x86_sse41_blendvpd>;
6773 let ExeDomain = SSEPackedSingle in
6774 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
6775 int_x86_sse41_blendvps>;
6776 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
6777 int_x86_sse41_pblendvb>;
6779 // Aliases with the implicit xmm0 argument
6780 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6781 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
6782 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6783 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
6784 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6785 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
6786 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6787 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
6788 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6789 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
6790 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6791 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
6793 let Predicates = [UseSSE41] in {
6794 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6795 (v16i8 VR128:$src2))),
6796 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6797 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6798 (v4i32 VR128:$src2))),
6799 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6800 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6801 (v4f32 VR128:$src2))),
6802 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6803 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6804 (v2i64 VR128:$src2))),
6805 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6806 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6807 (v2f64 VR128:$src2))),
6808 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6810 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6812 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6813 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6815 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6816 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6818 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6822 let Predicates = [HasAVX] in
6823 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6824 "vmovntdqa\t{$src, $dst|$dst, $src}",
6825 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6827 let Predicates = [HasAVX2] in
6828 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6829 "vmovntdqa\t{$src, $dst|$dst, $src}",
6830 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6832 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6833 "movntdqa\t{$src, $dst|$dst, $src}",
6834 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6837 //===----------------------------------------------------------------------===//
6838 // SSE4.2 - Compare Instructions
6839 //===----------------------------------------------------------------------===//
6841 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6842 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6843 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6844 X86MemOperand x86memop, bit Is2Addr = 1> {
6845 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6846 (ins RC:$src1, RC:$src2),
6848 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6849 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6850 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6852 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6853 (ins RC:$src1, x86memop:$src2),
6855 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6856 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6858 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6861 let Predicates = [HasAVX] in
6862 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6863 memopv2i64, i128mem, 0>, VEX_4V;
6865 let Predicates = [HasAVX2] in
6866 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6867 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6869 let Constraints = "$src1 = $dst" in
6870 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6871 memopv2i64, i128mem>;
6873 //===----------------------------------------------------------------------===//
6874 // SSE4.2 - String/text Processing Instructions
6875 //===----------------------------------------------------------------------===//
6877 // Packed Compare Implicit Length Strings, Return Mask
6878 multiclass pseudo_pcmpistrm<string asm> {
6879 def REG : PseudoI<(outs VR128:$dst),
6880 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6881 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6883 def MEM : PseudoI<(outs VR128:$dst),
6884 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6885 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
6886 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
6889 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6890 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6891 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
6894 multiclass pcmpistrm_SS42AI<string asm> {
6895 def rr : SS42AI<0x62, MRMSrcReg, (outs),
6896 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6897 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6900 def rm :SS42AI<0x62, MRMSrcMem, (outs),
6901 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6902 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6906 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6907 let Predicates = [HasAVX] in
6908 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
6909 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
6912 // Packed Compare Explicit Length Strings, Return Mask
6913 multiclass pseudo_pcmpestrm<string asm> {
6914 def REG : PseudoI<(outs VR128:$dst),
6915 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6916 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6917 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6918 def MEM : PseudoI<(outs VR128:$dst),
6919 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6920 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
6921 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
6924 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6925 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6926 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
6929 multiclass SS42AI_pcmpestrm<string asm> {
6930 def rr : SS42AI<0x60, MRMSrcReg, (outs),
6931 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6932 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6935 def rm : SS42AI<0x60, MRMSrcMem, (outs),
6936 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6937 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6941 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6942 let Predicates = [HasAVX] in
6943 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
6944 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
6947 // Packed Compare Implicit Length Strings, Return Index
6948 multiclass pseudo_pcmpistri<string asm> {
6949 def REG : PseudoI<(outs GR32:$dst),
6950 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6951 [(set GR32:$dst, EFLAGS,
6952 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
6953 def MEM : PseudoI<(outs GR32:$dst),
6954 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6955 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
6956 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
6959 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6960 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
6961 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
6964 multiclass SS42AI_pcmpistri<string asm> {
6965 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6966 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6967 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6970 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6971 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6972 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6976 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
6977 let Predicates = [HasAVX] in
6978 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
6979 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
6982 // Packed Compare Explicit Length Strings, Return Index
6983 multiclass pseudo_pcmpestri<string asm> {
6984 def REG : PseudoI<(outs GR32:$dst),
6985 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6986 [(set GR32:$dst, EFLAGS,
6987 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6988 def MEM : PseudoI<(outs GR32:$dst),
6989 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6990 [(set GR32:$dst, EFLAGS,
6991 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
6995 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6996 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
6997 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7000 multiclass SS42AI_pcmpestri<string asm> {
7001 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7002 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7003 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7006 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7007 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7008 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7012 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7013 let Predicates = [HasAVX] in
7014 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7015 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7018 //===----------------------------------------------------------------------===//
7019 // SSE4.2 - CRC Instructions
7020 //===----------------------------------------------------------------------===//
7022 // No CRC instructions have AVX equivalents
7024 // crc intrinsic instruction
7025 // This set of instructions are only rm, the only difference is the size
7027 let Constraints = "$src1 = $dst" in {
7028 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7029 (ins GR32:$src1, i8mem:$src2),
7030 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7032 (int_x86_sse42_crc32_32_8 GR32:$src1,
7033 (load addr:$src2)))]>;
7034 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7035 (ins GR32:$src1, GR8:$src2),
7036 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7038 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7039 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7040 (ins GR32:$src1, i16mem:$src2),
7041 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7043 (int_x86_sse42_crc32_32_16 GR32:$src1,
7044 (load addr:$src2)))]>,
7046 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7047 (ins GR32:$src1, GR16:$src2),
7048 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7050 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7052 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7053 (ins GR32:$src1, i32mem:$src2),
7054 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7056 (int_x86_sse42_crc32_32_32 GR32:$src1,
7057 (load addr:$src2)))]>;
7058 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7059 (ins GR32:$src1, GR32:$src2),
7060 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7062 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7063 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7064 (ins GR64:$src1, i8mem:$src2),
7065 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7067 (int_x86_sse42_crc32_64_8 GR64:$src1,
7068 (load addr:$src2)))]>,
7070 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7071 (ins GR64:$src1, GR8:$src2),
7072 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7074 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7076 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7077 (ins GR64:$src1, i64mem:$src2),
7078 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7080 (int_x86_sse42_crc32_64_64 GR64:$src1,
7081 (load addr:$src2)))]>,
7083 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7084 (ins GR64:$src1, GR64:$src2),
7085 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7087 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7091 //===----------------------------------------------------------------------===//
7092 // AES-NI Instructions
7093 //===----------------------------------------------------------------------===//
7095 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7096 Intrinsic IntId128, bit Is2Addr = 1> {
7097 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7098 (ins VR128:$src1, VR128:$src2),
7100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7101 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7102 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7104 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7105 (ins VR128:$src1, i128mem:$src2),
7107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7110 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7113 // Perform One Round of an AES Encryption/Decryption Flow
7114 let Predicates = [HasAVX, HasAES] in {
7115 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7116 int_x86_aesni_aesenc, 0>, VEX_4V;
7117 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7118 int_x86_aesni_aesenclast, 0>, VEX_4V;
7119 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7120 int_x86_aesni_aesdec, 0>, VEX_4V;
7121 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7122 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7125 let Constraints = "$src1 = $dst" in {
7126 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7127 int_x86_aesni_aesenc>;
7128 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7129 int_x86_aesni_aesenclast>;
7130 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7131 int_x86_aesni_aesdec>;
7132 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7133 int_x86_aesni_aesdeclast>;
7136 // Perform the AES InvMixColumn Transformation
7137 let Predicates = [HasAVX, HasAES] in {
7138 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7140 "vaesimc\t{$src1, $dst|$dst, $src1}",
7142 (int_x86_aesni_aesimc VR128:$src1))]>,
7144 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7145 (ins i128mem:$src1),
7146 "vaesimc\t{$src1, $dst|$dst, $src1}",
7147 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7150 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7152 "aesimc\t{$src1, $dst|$dst, $src1}",
7154 (int_x86_aesni_aesimc VR128:$src1))]>,
7156 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7157 (ins i128mem:$src1),
7158 "aesimc\t{$src1, $dst|$dst, $src1}",
7159 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7162 // AES Round Key Generation Assist
7163 let Predicates = [HasAVX, HasAES] in {
7164 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7165 (ins VR128:$src1, i8imm:$src2),
7166 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7168 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7170 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7171 (ins i128mem:$src1, i8imm:$src2),
7172 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7174 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7177 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7178 (ins VR128:$src1, i8imm:$src2),
7179 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7181 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7183 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7184 (ins i128mem:$src1, i8imm:$src2),
7185 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7187 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7190 //===----------------------------------------------------------------------===//
7191 // PCLMUL Instructions
7192 //===----------------------------------------------------------------------===//
7194 // AVX carry-less Multiplication instructions
7195 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7196 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7197 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7199 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7201 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7202 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7203 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7204 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7205 (memopv2i64 addr:$src2), imm:$src3))]>;
7207 // Carry-less Multiplication instructions
7208 let Constraints = "$src1 = $dst" in {
7209 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7210 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7211 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7213 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7215 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7216 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7217 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7218 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7219 (memopv2i64 addr:$src2), imm:$src3))]>;
7220 } // Constraints = "$src1 = $dst"
7223 multiclass pclmul_alias<string asm, int immop> {
7224 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7225 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7227 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7228 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7230 def : InstAlias<!strconcat("vpclmul", asm,
7231 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7232 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7234 def : InstAlias<!strconcat("vpclmul", asm,
7235 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7236 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7238 defm : pclmul_alias<"hqhq", 0x11>;
7239 defm : pclmul_alias<"hqlq", 0x01>;
7240 defm : pclmul_alias<"lqhq", 0x10>;
7241 defm : pclmul_alias<"lqlq", 0x00>;
7243 //===----------------------------------------------------------------------===//
7244 // SSE4A Instructions
7245 //===----------------------------------------------------------------------===//
7247 let Predicates = [HasSSE4A] in {
7249 let Constraints = "$src = $dst" in {
7250 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7251 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7252 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7253 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7254 imm:$idx))]>, TB, OpSize;
7255 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7256 (ins VR128:$src, VR128:$mask),
7257 "extrq\t{$mask, $src|$src, $mask}",
7258 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7259 VR128:$mask))]>, TB, OpSize;
7261 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7262 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7263 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7264 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7265 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7266 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7267 (ins VR128:$src, VR128:$mask),
7268 "insertq\t{$mask, $src|$src, $mask}",
7269 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7270 VR128:$mask))]>, XD;
7273 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7274 "movntss\t{$src, $dst|$dst, $src}",
7275 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7277 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7278 "movntsd\t{$src, $dst|$dst, $src}",
7279 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7282 //===----------------------------------------------------------------------===//
7284 //===----------------------------------------------------------------------===//
7286 //===----------------------------------------------------------------------===//
7287 // VBROADCAST - Load from memory and broadcast to all elements of the
7288 // destination operand
7290 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7291 X86MemOperand x86memop, Intrinsic Int> :
7292 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7293 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7294 [(set RC:$dst, (Int addr:$src))]>, VEX;
7296 // AVX2 adds register forms
7297 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7299 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7300 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7301 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7303 let ExeDomain = SSEPackedSingle in {
7304 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7305 int_x86_avx_vbroadcast_ss>;
7306 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7307 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7309 let ExeDomain = SSEPackedDouble in
7310 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7311 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7312 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7313 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7315 let ExeDomain = SSEPackedSingle in {
7316 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7317 int_x86_avx2_vbroadcast_ss_ps>;
7318 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7319 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7321 let ExeDomain = SSEPackedDouble in
7322 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7323 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7325 let Predicates = [HasAVX2] in
7326 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7327 int_x86_avx2_vbroadcasti128>, VEX_L;
7329 let Predicates = [HasAVX] in
7330 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7331 (VBROADCASTF128 addr:$src)>;
7334 //===----------------------------------------------------------------------===//
7335 // VINSERTF128 - Insert packed floating-point values
7337 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7338 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7339 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7340 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7343 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7344 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7345 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7349 let Predicates = [HasAVX] in {
7350 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7352 (VINSERTF128rr VR256:$src1, VR128:$src2,
7353 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7354 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7356 (VINSERTF128rr VR256:$src1, VR128:$src2,
7357 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7359 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7361 (VINSERTF128rm VR256:$src1, addr:$src2,
7362 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7363 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7365 (VINSERTF128rm VR256:$src1, addr:$src2,
7366 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7369 let Predicates = [HasAVX1Only] in {
7370 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7372 (VINSERTF128rr VR256:$src1, VR128:$src2,
7373 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7374 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7376 (VINSERTF128rr VR256:$src1, VR128:$src2,
7377 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7378 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7380 (VINSERTF128rr VR256:$src1, VR128:$src2,
7381 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7382 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7384 (VINSERTF128rr VR256:$src1, VR128:$src2,
7385 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7387 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7389 (VINSERTF128rm VR256:$src1, addr:$src2,
7390 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7391 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7392 (bc_v4i32 (memopv2i64 addr:$src2)),
7394 (VINSERTF128rm VR256:$src1, addr:$src2,
7395 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7396 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7397 (bc_v16i8 (memopv2i64 addr:$src2)),
7399 (VINSERTF128rm VR256:$src1, addr:$src2,
7400 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7401 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7402 (bc_v8i16 (memopv2i64 addr:$src2)),
7404 (VINSERTF128rm VR256:$src1, addr:$src2,
7405 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7408 //===----------------------------------------------------------------------===//
7409 // VEXTRACTF128 - Extract packed floating-point values
7411 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7412 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7413 (ins VR256:$src1, i8imm:$src2),
7414 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7417 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7418 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7419 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7424 let Predicates = [HasAVX] in {
7425 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7426 (v4f32 (VEXTRACTF128rr
7427 (v8f32 VR256:$src1),
7428 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7429 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7430 (v2f64 (VEXTRACTF128rr
7431 (v4f64 VR256:$src1),
7432 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7434 def : Pat<(alignedstore (v4f32 (vextractf128_extract:$ext (v8f32 VR256:$src1),
7435 (iPTR imm))), addr:$dst),
7436 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7437 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7438 def : Pat<(alignedstore (v2f64 (vextractf128_extract:$ext (v4f64 VR256:$src1),
7439 (iPTR imm))), addr:$dst),
7440 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7441 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7444 let Predicates = [HasAVX1Only] in {
7445 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7446 (v2i64 (VEXTRACTF128rr
7447 (v4i64 VR256:$src1),
7448 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7449 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7450 (v4i32 (VEXTRACTF128rr
7451 (v8i32 VR256:$src1),
7452 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7453 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7454 (v8i16 (VEXTRACTF128rr
7455 (v16i16 VR256:$src1),
7456 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7457 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7458 (v16i8 (VEXTRACTF128rr
7459 (v32i8 VR256:$src1),
7460 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7462 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7463 (iPTR imm))), addr:$dst),
7464 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7465 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7466 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7467 (iPTR imm))), addr:$dst),
7468 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7469 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7470 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7471 (iPTR imm))), addr:$dst),
7472 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7473 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7474 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7475 (iPTR imm))), addr:$dst),
7476 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7477 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7480 //===----------------------------------------------------------------------===//
7481 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7483 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7484 Intrinsic IntLd, Intrinsic IntLd256,
7485 Intrinsic IntSt, Intrinsic IntSt256> {
7486 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7487 (ins VR128:$src1, f128mem:$src2),
7488 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7489 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7491 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7492 (ins VR256:$src1, f256mem:$src2),
7493 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7494 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7496 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7497 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7498 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7499 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7500 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7501 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7502 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7503 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7506 let ExeDomain = SSEPackedSingle in
7507 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7508 int_x86_avx_maskload_ps,
7509 int_x86_avx_maskload_ps_256,
7510 int_x86_avx_maskstore_ps,
7511 int_x86_avx_maskstore_ps_256>;
7512 let ExeDomain = SSEPackedDouble in
7513 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7514 int_x86_avx_maskload_pd,
7515 int_x86_avx_maskload_pd_256,
7516 int_x86_avx_maskstore_pd,
7517 int_x86_avx_maskstore_pd_256>;
7519 //===----------------------------------------------------------------------===//
7520 // VPERMIL - Permute Single and Double Floating-Point Values
7522 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7523 RegisterClass RC, X86MemOperand x86memop_f,
7524 X86MemOperand x86memop_i, PatFrag i_frag,
7525 Intrinsic IntVar, ValueType vt> {
7526 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7527 (ins RC:$src1, RC:$src2),
7528 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7529 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7530 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7531 (ins RC:$src1, x86memop_i:$src2),
7532 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7533 [(set RC:$dst, (IntVar RC:$src1,
7534 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7536 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7537 (ins RC:$src1, i8imm:$src2),
7538 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7539 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7540 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7541 (ins x86memop_f:$src1, i8imm:$src2),
7542 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7544 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7547 let ExeDomain = SSEPackedSingle in {
7548 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7549 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7550 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7551 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7553 let ExeDomain = SSEPackedDouble in {
7554 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7555 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7556 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7557 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7560 let Predicates = [HasAVX] in {
7561 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7562 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7563 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7564 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7565 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7567 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7568 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7569 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7571 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7572 (VPERMILPDri VR128:$src1, imm:$imm)>;
7573 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7574 (VPERMILPDmi addr:$src1, imm:$imm)>;
7577 //===----------------------------------------------------------------------===//
7578 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7580 let ExeDomain = SSEPackedSingle in {
7581 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7582 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7583 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7584 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7585 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7586 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7587 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7588 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7589 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7590 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7593 let Predicates = [HasAVX] in {
7594 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7595 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7596 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7597 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7598 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7601 let Predicates = [HasAVX1Only] in {
7602 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7603 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7604 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7605 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7606 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7607 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7608 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7609 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7611 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7612 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7613 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7614 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7615 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7616 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7617 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7618 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7619 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7620 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7621 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7622 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7625 //===----------------------------------------------------------------------===//
7626 // VZERO - Zero YMM registers
7628 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7629 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7630 // Zero All YMM registers
7631 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7632 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7634 // Zero Upper bits of YMM registers
7635 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7636 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7639 //===----------------------------------------------------------------------===//
7640 // Half precision conversion instructions
7641 //===----------------------------------------------------------------------===//
7642 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7643 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7644 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7645 [(set RC:$dst, (Int VR128:$src))]>,
7647 let neverHasSideEffects = 1, mayLoad = 1 in
7648 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7649 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7652 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7653 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7654 (ins RC:$src1, i32i8imm:$src2),
7655 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7656 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7658 let neverHasSideEffects = 1, mayStore = 1 in
7659 def mr : Ii8<0x1D, MRMDestMem, (outs),
7660 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7661 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7665 let Predicates = [HasAVX, HasF16C] in {
7666 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7667 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7668 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7669 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7672 //===----------------------------------------------------------------------===//
7673 // AVX2 Instructions
7674 //===----------------------------------------------------------------------===//
7676 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7677 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7678 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7679 X86MemOperand x86memop> {
7680 let isCommutable = 1 in
7681 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7682 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7683 !strconcat(OpcodeStr,
7684 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7685 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7687 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7688 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7689 !strconcat(OpcodeStr,
7690 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7693 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7697 let isCommutable = 0 in {
7698 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7699 VR128, memopv2i64, i128mem>;
7700 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7701 VR256, memopv4i64, i256mem>, VEX_L;
7704 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
7706 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7707 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
7709 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7711 //===----------------------------------------------------------------------===//
7712 // VPBROADCAST - Load from memory and broadcast to all elements of the
7713 // destination operand
7715 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7716 X86MemOperand x86memop, PatFrag ld_frag,
7717 Intrinsic Int128, Intrinsic Int256> {
7718 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7719 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7720 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7721 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7722 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7724 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7725 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7726 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7727 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
7728 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7729 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7731 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
7735 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7736 int_x86_avx2_pbroadcastb_128,
7737 int_x86_avx2_pbroadcastb_256>;
7738 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7739 int_x86_avx2_pbroadcastw_128,
7740 int_x86_avx2_pbroadcastw_256>;
7741 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7742 int_x86_avx2_pbroadcastd_128,
7743 int_x86_avx2_pbroadcastd_256>;
7744 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7745 int_x86_avx2_pbroadcastq_128,
7746 int_x86_avx2_pbroadcastq_256>;
7748 let Predicates = [HasAVX2] in {
7749 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7750 (VPBROADCASTBrm addr:$src)>;
7751 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7752 (VPBROADCASTBYrm addr:$src)>;
7753 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7754 (VPBROADCASTWrm addr:$src)>;
7755 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7756 (VPBROADCASTWYrm addr:$src)>;
7757 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7758 (VPBROADCASTDrm addr:$src)>;
7759 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7760 (VPBROADCASTDYrm addr:$src)>;
7761 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7762 (VPBROADCASTQrm addr:$src)>;
7763 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7764 (VPBROADCASTQYrm addr:$src)>;
7766 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
7767 (VPBROADCASTBrr VR128:$src)>;
7768 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
7769 (VPBROADCASTBYrr VR128:$src)>;
7770 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
7771 (VPBROADCASTWrr VR128:$src)>;
7772 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
7773 (VPBROADCASTWYrr VR128:$src)>;
7774 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
7775 (VPBROADCASTDrr VR128:$src)>;
7776 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
7777 (VPBROADCASTDYrr VR128:$src)>;
7778 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
7779 (VPBROADCASTQrr VR128:$src)>;
7780 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
7781 (VPBROADCASTQYrr VR128:$src)>;
7782 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
7783 (VBROADCASTSSrr VR128:$src)>;
7784 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
7785 (VBROADCASTSSYrr VR128:$src)>;
7786 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
7787 (VPBROADCASTQrr VR128:$src)>;
7788 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
7789 (VBROADCASTSDYrr VR128:$src)>;
7791 // Provide fallback in case the load node that is used in the patterns above
7792 // is used by additional users, which prevents the pattern selection.
7793 let AddedComplexity = 20 in {
7794 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7795 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7796 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7797 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7798 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7799 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
7801 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7802 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7803 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7804 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7805 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7806 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
7810 // AVX1 broadcast patterns
7811 let Predicates = [HasAVX1Only] in {
7812 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7813 (VBROADCASTSSYrm addr:$src)>;
7814 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7815 (VBROADCASTSDYrm addr:$src)>;
7816 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7817 (VBROADCASTSSrm addr:$src)>;
7820 let Predicates = [HasAVX] in {
7821 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7822 (VBROADCASTSSYrm addr:$src)>;
7823 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7824 (VBROADCASTSDYrm addr:$src)>;
7825 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7826 (VBROADCASTSSrm addr:$src)>;
7828 // Provide fallback in case the load node that is used in the patterns above
7829 // is used by additional users, which prevents the pattern selection.
7830 let AddedComplexity = 20 in {
7831 // 128bit broadcasts:
7832 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7833 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
7834 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7835 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7836 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
7837 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
7838 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7839 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7840 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
7841 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
7843 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7844 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
7845 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7846 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7847 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
7848 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
7849 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7850 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7851 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
7852 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
7856 //===----------------------------------------------------------------------===//
7857 // VPERM - Permute instructions
7860 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7862 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7863 (ins VR256:$src1, VR256:$src2),
7864 !strconcat(OpcodeStr,
7865 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7867 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
7869 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7870 (ins VR256:$src1, i256mem:$src2),
7871 !strconcat(OpcodeStr,
7872 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7874 (OpVT (X86VPermv VR256:$src1,
7875 (bitconvert (mem_frag addr:$src2)))))]>,
7879 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7880 let ExeDomain = SSEPackedSingle in
7881 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7883 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7885 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7886 (ins VR256:$src1, i8imm:$src2),
7887 !strconcat(OpcodeStr,
7888 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7890 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
7892 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7893 (ins i256mem:$src1, i8imm:$src2),
7894 !strconcat(OpcodeStr,
7895 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7897 (OpVT (X86VPermi (mem_frag addr:$src1),
7898 (i8 imm:$src2))))]>, VEX, VEX_L;
7901 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7902 let ExeDomain = SSEPackedDouble in
7903 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7905 //===----------------------------------------------------------------------===//
7906 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7908 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7909 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7910 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7911 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7912 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7913 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7914 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7915 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7916 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7917 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7919 let Predicates = [HasAVX2] in {
7920 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7921 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7922 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7923 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7924 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7925 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7927 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7929 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7930 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7931 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7932 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7933 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7935 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7939 //===----------------------------------------------------------------------===//
7940 // VINSERTI128 - Insert packed integer values
7942 let neverHasSideEffects = 1 in {
7943 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7944 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7945 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7948 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7949 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7950 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7954 let Predicates = [HasAVX2] in {
7955 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7957 (VINSERTI128rr VR256:$src1, VR128:$src2,
7958 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7959 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7961 (VINSERTI128rr VR256:$src1, VR128:$src2,
7962 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7963 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7965 (VINSERTI128rr VR256:$src1, VR128:$src2,
7966 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7967 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7969 (VINSERTI128rr VR256:$src1, VR128:$src2,
7970 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7972 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7974 (VINSERTI128rm VR256:$src1, addr:$src2,
7975 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7976 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7977 (bc_v4i32 (memopv2i64 addr:$src2)),
7979 (VINSERTI128rm VR256:$src1, addr:$src2,
7980 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7981 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7982 (bc_v16i8 (memopv2i64 addr:$src2)),
7984 (VINSERTI128rm VR256:$src1, addr:$src2,
7985 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7986 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7987 (bc_v8i16 (memopv2i64 addr:$src2)),
7989 (VINSERTI128rm VR256:$src1, addr:$src2,
7990 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7993 //===----------------------------------------------------------------------===//
7994 // VEXTRACTI128 - Extract packed integer values
7996 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7997 (ins VR256:$src1, i8imm:$src2),
7998 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8000 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8002 let neverHasSideEffects = 1, mayStore = 1 in
8003 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8004 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8005 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8008 let Predicates = [HasAVX2] in {
8009 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8010 (v2i64 (VEXTRACTI128rr
8011 (v4i64 VR256:$src1),
8012 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8013 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8014 (v4i32 (VEXTRACTI128rr
8015 (v8i32 VR256:$src1),
8016 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8017 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8018 (v8i16 (VEXTRACTI128rr
8019 (v16i16 VR256:$src1),
8020 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8021 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8022 (v16i8 (VEXTRACTI128rr
8023 (v32i8 VR256:$src1),
8024 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8026 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
8027 (iPTR imm))), addr:$dst),
8028 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8029 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8030 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
8031 (iPTR imm))), addr:$dst),
8032 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8033 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8034 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
8035 (iPTR imm))), addr:$dst),
8036 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8037 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8038 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
8039 (iPTR imm))), addr:$dst),
8040 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8041 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8044 //===----------------------------------------------------------------------===//
8045 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8047 multiclass avx2_pmovmask<string OpcodeStr,
8048 Intrinsic IntLd128, Intrinsic IntLd256,
8049 Intrinsic IntSt128, Intrinsic IntSt256> {
8050 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8051 (ins VR128:$src1, i128mem:$src2),
8052 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8053 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8054 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8055 (ins VR256:$src1, i256mem:$src2),
8056 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8057 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8059 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8060 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8061 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8062 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8063 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8064 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8065 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8066 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8069 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8070 int_x86_avx2_maskload_d,
8071 int_x86_avx2_maskload_d_256,
8072 int_x86_avx2_maskstore_d,
8073 int_x86_avx2_maskstore_d_256>;
8074 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8075 int_x86_avx2_maskload_q,
8076 int_x86_avx2_maskload_q_256,
8077 int_x86_avx2_maskstore_q,
8078 int_x86_avx2_maskstore_q_256>, VEX_W;
8081 //===----------------------------------------------------------------------===//
8082 // Variable Bit Shifts
8084 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8085 ValueType vt128, ValueType vt256> {
8086 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8087 (ins VR128:$src1, VR128:$src2),
8088 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8090 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8092 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8093 (ins VR128:$src1, i128mem:$src2),
8094 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8096 (vt128 (OpNode VR128:$src1,
8097 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8099 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8100 (ins VR256:$src1, VR256:$src2),
8101 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8103 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8105 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8106 (ins VR256:$src1, i256mem:$src2),
8107 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8109 (vt256 (OpNode VR256:$src1,
8110 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8114 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8115 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8116 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8117 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8118 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8120 //===----------------------------------------------------------------------===//
8121 // VGATHER - GATHER Operations
8122 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8123 X86MemOperand memop128, X86MemOperand memop256> {
8124 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8125 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8126 !strconcat(OpcodeStr,
8127 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8129 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8130 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8131 !strconcat(OpcodeStr,
8132 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8133 []>, VEX_4VOp3, VEX_L;
8136 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
8137 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8138 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8139 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8140 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8141 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8142 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8143 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8144 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;