1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
374 // Move Instructions. Register-to-register movss is not used for FR32
375 // register copies because it's a partial register update; FsMOVAPSrr is
376 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
377 // because INSERT_SUBREG requires that the insert be implementable in terms of
378 // a copy, and just mentioned, we don't use movss for copies.
379 let Constraints = "$src1 = $dst" in
380 def MOVSSrr : SSI<0x10, MRMSrcReg,
381 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
382 "movss\t{$src2, $dst|$dst, $src2}",
383 [(set (v4f32 VR128:$dst),
384 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
386 // Extract the low 32-bit value from one vector and insert it into another.
387 let AddedComplexity = 15 in
388 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
389 (MOVSSrr (v4f32 VR128:$src1),
390 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
392 // Implicitly promote a 32-bit scalar to a vector.
393 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
394 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
396 // Loading from memory automatically zeroing upper bits.
397 let canFoldAsLoad = 1, isReMaterializable = 1 in
398 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
399 "movss\t{$src, $dst|$dst, $src}",
400 [(set FR32:$dst, (loadf32 addr:$src))]>;
402 // MOVSSrm zeros the high parts of the register; represent this
403 // with SUBREG_TO_REG.
404 let AddedComplexity = 20 in {
405 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
406 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
407 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
408 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
409 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
410 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
413 // Store scalar value to memory.
414 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
415 "movss\t{$src, $dst|$dst, $src}",
416 [(store FR32:$src, addr:$dst)]>;
418 // Extract and store.
419 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
422 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
424 // Conversion instructions
425 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
426 "cvttss2si\t{$src, $dst|$dst, $src}",
427 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
428 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
429 "cvttss2si\t{$src, $dst|$dst, $src}",
430 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
431 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
432 "cvtsi2ss\t{$src, $dst|$dst, $src}",
433 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
434 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
435 "cvtsi2ss\t{$src, $dst|$dst, $src}",
436 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
438 // Match intrinsics which expect XMM operand(s).
439 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
440 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
441 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
442 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
444 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
445 "cvtss2si\t{$src, $dst|$dst, $src}",
446 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
447 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
448 "cvtss2si\t{$src, $dst|$dst, $src}",
449 [(set GR32:$dst, (int_x86_sse_cvtss2si
450 (load addr:$src)))]>;
452 // Match intrinsics which expect MM and XMM operand(s).
453 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
454 "cvtps2pi\t{$src, $dst|$dst, $src}",
455 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
456 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
457 "cvtps2pi\t{$src, $dst|$dst, $src}",
458 [(set VR64:$dst, (int_x86_sse_cvtps2pi
459 (load addr:$src)))]>;
460 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
461 "cvttps2pi\t{$src, $dst|$dst, $src}",
462 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
463 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
464 "cvttps2pi\t{$src, $dst|$dst, $src}",
465 [(set VR64:$dst, (int_x86_sse_cvttps2pi
466 (load addr:$src)))]>;
467 let Constraints = "$src1 = $dst" in {
468 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
469 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
470 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
471 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
473 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
474 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
475 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
476 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
477 (load addr:$src2)))]>;
480 // Aliases for intrinsics
481 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
482 "cvttss2si\t{$src, $dst|$dst, $src}",
484 (int_x86_sse_cvttss2si VR128:$src))]>;
485 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
486 "cvttss2si\t{$src, $dst|$dst, $src}",
488 (int_x86_sse_cvttss2si(load addr:$src)))]>;
490 let Constraints = "$src1 = $dst" in {
491 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
492 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
493 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
494 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
496 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
497 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
498 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
499 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
500 (loadi32 addr:$src2)))]>;
503 // Comparison instructions
504 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
505 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
506 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
507 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
509 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
510 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
511 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
513 // Accept explicit immediate argument form instead of comparison code.
514 let isAsmParserOnly = 1 in {
515 def CMPSSrr_alt : SSIi8<0xC2, MRMSrcReg,
516 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
517 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
519 def CMPSSrm_alt : SSIi8<0xC2, MRMSrcMem,
520 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
521 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
525 let Defs = [EFLAGS] in {
526 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
527 "ucomiss\t{$src2, $src1|$src1, $src2}",
528 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
529 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
530 "ucomiss\t{$src2, $src1|$src1, $src2}",
531 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
533 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
534 "comiss\t{$src2, $src1|$src1, $src2}", []>;
535 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
536 "comiss\t{$src2, $src1|$src1, $src2}", []>;
540 // Aliases to match intrinsics which expect XMM operand(s).
541 let Constraints = "$src1 = $dst" in {
542 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
544 (ins VR128:$src1, VR128:$src, SSECC:$cc),
545 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
546 [(set VR128:$dst, (int_x86_sse_cmp_ss
548 VR128:$src, imm:$cc))]>;
549 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
551 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
552 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
553 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
554 (load addr:$src), imm:$cc))]>;
557 let Defs = [EFLAGS] in {
558 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
559 "ucomiss\t{$src2, $src1|$src1, $src2}",
560 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
562 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
563 "ucomiss\t{$src2, $src1|$src1, $src2}",
564 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
565 (load addr:$src2)))]>;
567 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
568 "comiss\t{$src2, $src1|$src1, $src2}",
569 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
571 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
572 "comiss\t{$src2, $src1|$src1, $src2}",
573 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
574 (load addr:$src2)))]>;
577 // Aliases of packed SSE1 instructions for scalar use. These all have names
578 // that start with 'Fs'.
580 // Alias instructions that map fld0 to pxor for sse.
581 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
583 // FIXME: Set encoding to pseudo!
584 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
585 [(set FR32:$dst, fp32imm0)]>,
586 Requires<[HasSSE1]>, TB, OpSize;
588 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
590 let neverHasSideEffects = 1 in
591 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
592 "movaps\t{$src, $dst|$dst, $src}", []>;
594 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
596 let canFoldAsLoad = 1, isReMaterializable = 1 in
597 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
598 "movaps\t{$src, $dst|$dst, $src}",
599 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
601 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
603 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
604 SDNode OpNode, int NoPat = 0,
605 bit MayLoad = 0, bit Commutable = 1> {
606 def PSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
607 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
609 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))])> {
610 let isCommutable = Commutable;
613 def PDrr : PDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
614 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
616 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))])> {
617 let isCommutable = Commutable;
620 def PSrm : PSI<opc, MRMSrcMem, (outs FR32:$dst),
621 (ins FR32:$src1, f128mem:$src2),
622 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
624 [(set FR32:$dst, (OpNode FR32:$src1,
625 (memopfsf32 addr:$src2)))])> {
626 let mayLoad = MayLoad;
629 def PDrm : PDI<opc, MRMSrcMem, (outs FR64:$dst),
630 (ins FR64:$src1, f128mem:$src2),
631 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
633 [(set FR64:$dst, (OpNode FR64:$src1,
634 (memopfsf64 addr:$src2)))])> {
635 let mayLoad = MayLoad;
639 // Alias bitwise logical operations using SSE logical ops on packed FP values.
640 let Constraints = "$src1 = $dst" in {
641 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
642 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
643 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
645 let neverHasSideEffects = 1 in
646 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1, 1, 0>;
649 /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
652 /// In addition, we also have a special variant of the scalar form here to
653 /// represent the associated intrinsic operation. This form is unlike the
654 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
655 /// and leaves the top elements unmodified (therefore these cannot be commuted).
657 /// These three forms can each be reg+reg or reg+mem, so there are a total of
658 /// six "instructions".
660 let Constraints = "$src1 = $dst" in {
661 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
662 SDNode OpNode, bit Commutable = 0> {
663 // Scalar operation, reg+reg.
664 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
665 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
666 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
667 let isCommutable = Commutable;
670 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
671 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
672 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
673 let isCommutable = Commutable;
676 def V#NAME#SSrr : VSSI<opc, MRMSrcReg, (outs FR32:$dst),
677 (ins FR32:$src1, FR32:$src2),
678 !strconcat(OpcodeStr,
679 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
681 let isCommutable = Commutable;
682 let Constraints = "";
683 let isAsmParserOnly = 1;
686 def V#NAME#SDrr : VSDI<opc, MRMSrcReg, (outs FR64:$dst),
687 (ins FR64:$src1, FR64:$src2),
688 !strconcat(OpcodeStr,
689 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
691 let isCommutable = Commutable;
692 let Constraints = "";
693 let isAsmParserOnly = 1;
696 // Scalar operation, reg+mem.
697 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
698 (ins FR32:$src1, f32mem:$src2),
699 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
700 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
702 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
703 (ins FR64:$src1, f64mem:$src2),
704 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
705 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
707 // Vector operation, reg+reg.
708 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
709 (ins VR128:$src1, VR128:$src2),
710 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
711 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
712 let isCommutable = Commutable;
715 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
716 (ins VR128:$src1, VR128:$src2),
717 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
718 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
719 let isCommutable = Commutable;
722 // Vector operation, reg+mem.
723 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
724 (ins VR128:$src1, f128mem:$src2),
725 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
726 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
728 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
729 (ins VR128:$src1, f128mem:$src2),
730 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
731 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
733 // Intrinsic operation, reg+reg.
734 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
735 (ins VR128:$src1, VR128:$src2),
736 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
737 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
738 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
740 // int_x86_sse_xxx_ss
742 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
743 (ins VR128:$src1, VR128:$src2),
744 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
745 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
746 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
748 // int_x86_sse2_xxx_sd
750 // Intrinsic operation, reg+mem.
751 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
752 (ins VR128:$src1, ssmem:$src2),
753 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
754 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
755 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
756 sse_load_f32:$src2))]>;
757 // int_x86_sse_xxx_ss
759 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
760 (ins VR128:$src1, sdmem:$src2),
761 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
762 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
763 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
764 sse_load_f64:$src2))]>;
765 // int_x86_sse2_xxx_sd
769 // Arithmetic instructions
770 defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd, 1>;
771 defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul, 1>;
772 defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
773 defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
775 /// sse12_fp_binop_rm - Other SSE 1 & 2 binops
777 /// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
778 /// instructions for a full-vector intrinsic form. Operations that map
779 /// onto C operators don't use this form since they just use the plain
780 /// vector form instead of having a separate vector intrinsic form.
782 /// This provides a total of eight "instructions".
784 let Constraints = "$src1 = $dst" in {
785 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
786 SDNode OpNode, bit Commutable = 0> {
788 // Scalar operation, reg+reg.
789 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
790 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
791 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
792 let isCommutable = Commutable;
795 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
796 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
797 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
798 let isCommutable = Commutable;
801 // Scalar operation, reg+mem.
802 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
803 (ins FR32:$src1, f32mem:$src2),
804 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
805 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
807 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
808 (ins FR64:$src1, f64mem:$src2),
809 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
810 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
812 // Vector operation, reg+reg.
813 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
814 (ins VR128:$src1, VR128:$src2),
815 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
816 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
817 let isCommutable = Commutable;
820 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
821 (ins VR128:$src1, VR128:$src2),
822 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
823 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
824 let isCommutable = Commutable;
827 // Vector operation, reg+mem.
828 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
829 (ins VR128:$src1, f128mem:$src2),
830 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
831 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
833 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
834 (ins VR128:$src1, f128mem:$src2),
835 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
836 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
838 // Intrinsic operation, reg+reg.
839 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
840 (ins VR128:$src1, VR128:$src2),
841 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
842 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
843 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
845 // int_x86_sse_xxx_ss
846 let isCommutable = Commutable;
849 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
850 (ins VR128:$src1, VR128:$src2),
851 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
852 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
853 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
855 // int_x86_sse2_xxx_sd
856 let isCommutable = Commutable;
859 // Intrinsic operation, reg+mem.
860 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
861 (ins VR128:$src1, ssmem:$src2),
862 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
863 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
864 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
865 sse_load_f32:$src2))]>;
866 // int_x86_sse_xxx_ss
868 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
869 (ins VR128:$src1, sdmem:$src2),
870 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
871 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
872 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
873 sse_load_f64:$src2))]>;
874 // int_x86_sse2_xxx_sd
876 // Vector intrinsic operation, reg+reg.
877 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
878 (ins VR128:$src1, VR128:$src2),
879 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
880 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
881 !strconcat(OpcodeStr, "_ps")) VR128:$src1,
883 // int_x86_sse_xxx_ps
884 let isCommutable = Commutable;
887 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
888 (ins VR128:$src1, VR128:$src2),
889 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
890 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
891 !strconcat(OpcodeStr, "_pd")) VR128:$src1,
893 // int_x86_sse2_xxx_pd
894 let isCommutable = Commutable;
897 // Vector intrinsic operation, reg+mem.
898 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
899 (ins VR128:$src1, f128mem:$src2),
900 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
901 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
902 !strconcat(OpcodeStr, "_ps")) VR128:$src1,
903 (memopv4f32 addr:$src2)))]>;
904 // int_x86_sse_xxx_ps
906 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
907 (ins VR128:$src1, f128mem:$src2),
908 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
909 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
910 !strconcat(OpcodeStr, "_pd")) VR128:$src1,
911 (memopv2f64 addr:$src2)))]>;
912 // int_x86_sse2_xxx_pd
916 defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
917 defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
919 //===----------------------------------------------------------------------===//
920 // SSE packed FP Instructions
923 let neverHasSideEffects = 1 in
924 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
925 "movaps\t{$src, $dst|$dst, $src}", []>;
926 let canFoldAsLoad = 1, isReMaterializable = 1 in
927 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
928 "movaps\t{$src, $dst|$dst, $src}",
929 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
931 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
932 "movaps\t{$src, $dst|$dst, $src}",
933 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
935 let neverHasSideEffects = 1 in
936 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
937 "movups\t{$src, $dst|$dst, $src}", []>;
938 let canFoldAsLoad = 1, isReMaterializable = 1 in
939 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
940 "movups\t{$src, $dst|$dst, $src}",
941 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
942 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
943 "movups\t{$src, $dst|$dst, $src}",
944 [(store (v4f32 VR128:$src), addr:$dst)]>;
946 // Intrinsic forms of MOVUPS load and store
947 let canFoldAsLoad = 1, isReMaterializable = 1 in
948 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
949 "movups\t{$src, $dst|$dst, $src}",
950 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
951 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
952 "movups\t{$src, $dst|$dst, $src}",
953 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
955 let Constraints = "$src1 = $dst" in {
956 let AddedComplexity = 20 in {
957 def MOVLPSrm : PSI<0x12, MRMSrcMem,
958 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
959 "movlps\t{$src2, $dst|$dst, $src2}",
962 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
963 def MOVHPSrm : PSI<0x16, MRMSrcMem,
964 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
965 "movhps\t{$src2, $dst|$dst, $src2}",
967 (movlhps VR128:$src1,
968 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
970 } // Constraints = "$src1 = $dst"
973 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
974 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
976 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
977 "movlps\t{$src, $dst|$dst, $src}",
978 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
979 (iPTR 0))), addr:$dst)]>;
981 // v2f64 extract element 1 is always custom lowered to unpack high to low
982 // and extract element 0 so the non-store version isn't too horrible.
983 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
984 "movhps\t{$src, $dst|$dst, $src}",
985 [(store (f64 (vector_extract
986 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
987 (undef)), (iPTR 0))), addr:$dst)]>;
989 let Constraints = "$src1 = $dst" in {
990 let AddedComplexity = 20 in {
991 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
992 (ins VR128:$src1, VR128:$src2),
993 "movlhps\t{$src2, $dst|$dst, $src2}",
995 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
997 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
998 (ins VR128:$src1, VR128:$src2),
999 "movhlps\t{$src2, $dst|$dst, $src2}",
1001 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1002 } // AddedComplexity
1003 } // Constraints = "$src1 = $dst"
1005 let AddedComplexity = 20 in {
1006 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1007 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1008 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1009 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1016 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
1018 /// In addition, we also have a special variant of the scalar form here to
1019 /// represent the associated intrinsic operation. This form is unlike the
1020 /// plain scalar form, in that it takes an entire vector (instead of a
1021 /// scalar) and leaves the top elements undefined.
1023 /// And, we have a special variant form for a full-vector intrinsic form.
1025 /// These four forms can each have a reg or a mem operand, so there are a
1026 /// total of eight "instructions".
1028 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
1032 bit Commutable = 0> {
1033 // Scalar operation, reg.
1034 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1035 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1036 [(set FR32:$dst, (OpNode FR32:$src))]> {
1037 let isCommutable = Commutable;
1040 // Scalar operation, mem.
1041 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1042 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1043 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1044 Requires<[HasSSE1, OptForSize]>;
1046 // Vector operation, reg.
1047 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1048 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1049 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
1050 let isCommutable = Commutable;
1053 // Vector operation, mem.
1054 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1055 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1056 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1058 // Intrinsic operation, reg.
1059 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1060 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1061 [(set VR128:$dst, (F32Int VR128:$src))]> {
1062 let isCommutable = Commutable;
1065 // Intrinsic operation, mem.
1066 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1067 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1068 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1070 // Vector intrinsic operation, reg
1071 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1072 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1073 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
1074 let isCommutable = Commutable;
1077 // Vector intrinsic operation, mem
1078 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1079 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1080 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1084 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
1085 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
1087 // Reciprocal approximations. Note that these typically require refinement
1088 // in order to obtain suitable precision.
1089 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
1090 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
1091 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
1092 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
1094 /// sse12_fp_pack_logical - SSE 1 & 2 packed FP logical ops
1096 multiclass sse12_fp_pack_logical<bits<8> opc, string OpcodeStr,
1097 SDNode OpNode, int HasPat = 0,
1099 list<list<dag>> Pattern = []> {
1100 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
1101 (ins VR128:$src1, VR128:$src2),
1102 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
1103 !if(HasPat, Pattern[0],
1104 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1106 { let isCommutable = Commutable; }
1108 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1109 (ins VR128:$src1, VR128:$src2),
1110 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1111 !if(HasPat, Pattern[1],
1112 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1113 (bc_v2i64 (v2f64 VR128:$src2))))])>
1114 { let isCommutable = Commutable; }
1116 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
1117 (ins VR128:$src1, f128mem:$src2),
1118 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
1119 !if(HasPat, Pattern[2],
1120 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1121 (memopv2i64 addr:$src2)))])>;
1123 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1124 (ins VR128:$src1, f128mem:$src2),
1125 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1126 !if(HasPat, Pattern[3],
1127 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1128 (memopv2i64 addr:$src2)))])>;
1132 let Constraints = "$src1 = $dst" in {
1133 defm AND : sse12_fp_pack_logical<0x54, "and", and>;
1134 defm OR : sse12_fp_pack_logical<0x56, "or", or>;
1135 defm XOR : sse12_fp_pack_logical<0x57, "xor", xor>;
1136 defm ANDN : sse12_fp_pack_logical<0x55, "andn", undef /* dummy */, 1, 0, [
1138 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1139 (bc_v2i64 (v4i32 immAllOnesV))),
1142 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1143 (bc_v2i64 (v2f64 VR128:$src2))))],
1145 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1146 (bc_v2i64 (v4i32 immAllOnesV))),
1147 (memopv2i64 addr:$src2))))],
1149 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1150 (memopv2i64 addr:$src2)))]]>;
1153 let Constraints = "$src1 = $dst" in {
1154 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1155 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1156 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1157 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1158 VR128:$src, imm:$cc))]>;
1159 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1160 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1161 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1162 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1163 (memop addr:$src), imm:$cc))]>;
1165 // Accept explicit immediate argument form instead of comparison code.
1166 let isAsmParserOnly = 1 in {
1167 def CMPPSrri_alt : PSIi8<0xC2, MRMSrcReg,
1168 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1169 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1170 def CMPPSrmi_alt : PSIi8<0xC2, MRMSrcMem,
1171 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1172 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1175 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1176 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1177 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1178 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1180 // Shuffle and unpack instructions
1181 let Constraints = "$src1 = $dst" in {
1182 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1183 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1184 (outs VR128:$dst), (ins VR128:$src1,
1185 VR128:$src2, i8imm:$src3),
1186 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1188 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1189 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1190 (outs VR128:$dst), (ins VR128:$src1,
1191 f128mem:$src2, i8imm:$src3),
1192 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1195 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1197 let AddedComplexity = 10 in {
1198 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1199 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1200 "unpckhps\t{$src2, $dst|$dst, $src2}",
1202 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1203 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1204 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1205 "unpckhps\t{$src2, $dst|$dst, $src2}",
1207 (v4f32 (unpckh VR128:$src1,
1208 (memopv4f32 addr:$src2))))]>;
1210 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1211 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1212 "unpcklps\t{$src2, $dst|$dst, $src2}",
1214 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1215 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1216 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1217 "unpcklps\t{$src2, $dst|$dst, $src2}",
1219 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1220 } // AddedComplexity
1221 } // Constraints = "$src1 = $dst"
1224 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1225 "movmskps\t{$src, $dst|$dst, $src}",
1226 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1227 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1228 "movmskpd\t{$src, $dst|$dst, $src}",
1229 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1231 // Prefetch intrinsic.
1232 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1233 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1234 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1235 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1236 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1237 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1238 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1239 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1241 // Non-temporal stores
1242 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1243 "movntps\t{$src, $dst|$dst, $src}",
1244 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1246 let AddedComplexity = 400 in { // Prefer non-temporal versions
1247 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1248 "movntps\t{$src, $dst|$dst, $src}",
1249 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1251 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1252 "movntdq\t{$src, $dst|$dst, $src}",
1253 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1255 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1256 "movnti\t{$src, $dst|$dst, $src}",
1257 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1258 TB, Requires<[HasSSE2]>;
1260 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1261 "movnti\t{$src, $dst|$dst, $src}",
1262 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1263 TB, Requires<[HasSSE2]>;
1266 // Load, store, and memory fence
1267 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1268 TB, Requires<[HasSSE1]>;
1271 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1272 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1273 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1274 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1276 // Alias instructions that map zero vector to pxor / xorp* for sse.
1277 // We set canFoldAsLoad because this can be converted to a constant-pool
1278 // load of an all-zeros value if folding it would be beneficial.
1279 // FIXME: Change encoding to pseudo!
1280 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1281 isCodeGenOnly = 1 in {
1282 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1283 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1284 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1285 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1286 let ExeDomain = SSEPackedInt in
1287 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1288 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1291 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
1292 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
1293 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
1295 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1296 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1298 //===---------------------------------------------------------------------===//
1299 // SSE2 Instructions
1300 //===---------------------------------------------------------------------===//
1302 // Move Instructions. Register-to-register movsd is not used for FR64
1303 // register copies because it's a partial register update; FsMOVAPDrr is
1304 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1305 // because INSERT_SUBREG requires that the insert be implementable in terms of
1306 // a copy, and just mentioned, we don't use movsd for copies.
1307 let Constraints = "$src1 = $dst" in
1308 def MOVSDrr : SDI<0x10, MRMSrcReg,
1309 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1310 "movsd\t{$src2, $dst|$dst, $src2}",
1311 [(set (v2f64 VR128:$dst),
1312 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1314 // Extract the low 64-bit value from one vector and insert it into another.
1315 let AddedComplexity = 15 in
1316 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1317 (MOVSDrr (v2f64 VR128:$src1),
1318 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
1320 // Implicitly promote a 64-bit scalar to a vector.
1321 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1322 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
1324 // Loading from memory automatically zeroing upper bits.
1325 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1326 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1327 "movsd\t{$src, $dst|$dst, $src}",
1328 [(set FR64:$dst, (loadf64 addr:$src))]>;
1330 // MOVSDrm zeros the high parts of the register; represent this
1331 // with SUBREG_TO_REG.
1332 let AddedComplexity = 20 in {
1333 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1334 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1335 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1336 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1337 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1338 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1339 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1340 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1341 def : Pat<(v2f64 (X86vzload addr:$src)),
1342 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1345 // Store scalar value to memory.
1346 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1347 "movsd\t{$src, $dst|$dst, $src}",
1348 [(store FR64:$src, addr:$dst)]>;
1350 // Extract and store.
1351 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1354 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
1356 // Conversion instructions
1357 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1358 "cvttsd2si\t{$src, $dst|$dst, $src}",
1359 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1360 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1361 "cvttsd2si\t{$src, $dst|$dst, $src}",
1362 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1363 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1364 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1365 [(set FR32:$dst, (fround FR64:$src))]>;
1366 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1367 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1368 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1369 Requires<[HasSSE2, OptForSize]>;
1370 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1371 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1372 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1373 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1374 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1375 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1377 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1378 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1379 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1380 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1381 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1382 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1383 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1384 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1385 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1386 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1387 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1388 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1389 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1390 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1391 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1392 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1393 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1394 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1395 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1396 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1398 // SSE2 instructions with XS prefix
1399 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1400 "cvtss2sd\t{$src, $dst|$dst, $src}",
1401 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1402 Requires<[HasSSE2]>;
1403 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1404 "cvtss2sd\t{$src, $dst|$dst, $src}",
1405 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1406 Requires<[HasSSE2, OptForSize]>;
1408 def : Pat<(extloadf32 addr:$src),
1409 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1410 Requires<[HasSSE2, OptForSpeed]>;
1412 // Match intrinsics which expect XMM operand(s).
1413 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1414 "cvtsd2si\t{$src, $dst|$dst, $src}",
1415 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1416 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1417 "cvtsd2si\t{$src, $dst|$dst, $src}",
1418 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1419 (load addr:$src)))]>;
1421 // Match intrinsics which expect MM and XMM operand(s).
1422 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1423 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1424 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1425 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1426 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1427 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1428 (memop addr:$src)))]>;
1429 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1430 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1431 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1432 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1433 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1434 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1435 (memop addr:$src)))]>;
1436 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1437 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1438 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1439 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1440 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1441 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1442 (load addr:$src)))]>;
1444 // Aliases for intrinsics
1445 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1446 "cvttsd2si\t{$src, $dst|$dst, $src}",
1448 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1449 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1450 "cvttsd2si\t{$src, $dst|$dst, $src}",
1451 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1452 (load addr:$src)))]>;
1454 // Comparison instructions
1455 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1456 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1457 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1458 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1460 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1461 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1462 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1464 // Accept explicit immediate argument form instead of comparison code.
1465 let isAsmParserOnly = 1 in {
1466 def CMPSDrr_alt : SDIi8<0xC2, MRMSrcReg,
1467 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1468 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1470 def CMPSDrm_alt : SDIi8<0xC2, MRMSrcMem,
1471 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1472 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1476 let Defs = [EFLAGS] in {
1477 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1478 "ucomisd\t{$src2, $src1|$src1, $src2}",
1479 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
1480 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1481 "ucomisd\t{$src2, $src1|$src1, $src2}",
1482 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
1483 } // Defs = [EFLAGS]
1485 // Aliases to match intrinsics which expect XMM operand(s).
1486 let Constraints = "$src1 = $dst" in {
1487 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1489 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1490 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1491 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1492 VR128:$src, imm:$cc))]>;
1493 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1495 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1496 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1497 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1498 (load addr:$src), imm:$cc))]>;
1501 let Defs = [EFLAGS] in {
1502 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1503 "ucomisd\t{$src2, $src1|$src1, $src2}",
1504 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1506 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1507 "ucomisd\t{$src2, $src1|$src1, $src2}",
1508 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1509 (load addr:$src2)))]>;
1511 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1512 "comisd\t{$src2, $src1|$src1, $src2}",
1513 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1515 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1516 "comisd\t{$src2, $src1|$src1, $src2}",
1517 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1518 (load addr:$src2)))]>;
1519 } // Defs = [EFLAGS]
1521 // Aliases of packed SSE2 instructions for scalar use. These all have names
1522 // that start with 'Fs'.
1524 // Alias instructions that map fld0 to pxor for sse.
1525 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1526 canFoldAsLoad = 1 in
1527 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1528 [(set FR64:$dst, fpimm0)]>,
1529 Requires<[HasSSE2]>, TB, OpSize;
1531 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1533 let neverHasSideEffects = 1 in
1534 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1535 "movapd\t{$src, $dst|$dst, $src}", []>;
1537 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1539 let canFoldAsLoad = 1, isReMaterializable = 1 in
1540 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1541 "movapd\t{$src, $dst|$dst, $src}",
1542 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1544 //===---------------------------------------------------------------------===//
1545 // SSE packed FP Instructions
1547 // Move Instructions
1548 let neverHasSideEffects = 1 in
1549 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1550 "movapd\t{$src, $dst|$dst, $src}", []>;
1551 let canFoldAsLoad = 1, isReMaterializable = 1 in
1552 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1553 "movapd\t{$src, $dst|$dst, $src}",
1554 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1556 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1557 "movapd\t{$src, $dst|$dst, $src}",
1558 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1560 let neverHasSideEffects = 1 in
1561 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1562 "movupd\t{$src, $dst|$dst, $src}", []>;
1563 let canFoldAsLoad = 1 in
1564 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1565 "movupd\t{$src, $dst|$dst, $src}",
1566 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1567 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1568 "movupd\t{$src, $dst|$dst, $src}",
1569 [(store (v2f64 VR128:$src), addr:$dst)]>;
1571 // Intrinsic forms of MOVUPD load and store
1572 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1573 "movupd\t{$src, $dst|$dst, $src}",
1574 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1575 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1576 "movupd\t{$src, $dst|$dst, $src}",
1577 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1579 let Constraints = "$src1 = $dst" in {
1580 let AddedComplexity = 20 in {
1581 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1582 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1583 "movlpd\t{$src2, $dst|$dst, $src2}",
1585 (v2f64 (movlp VR128:$src1,
1586 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1587 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1588 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1589 "movhpd\t{$src2, $dst|$dst, $src2}",
1591 (v2f64 (movlhps VR128:$src1,
1592 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1593 } // AddedComplexity
1594 } // Constraints = "$src1 = $dst"
1596 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1597 "movlpd\t{$src, $dst|$dst, $src}",
1598 [(store (f64 (vector_extract (v2f64 VR128:$src),
1599 (iPTR 0))), addr:$dst)]>;
1601 // v2f64 extract element 1 is always custom lowered to unpack high to low
1602 // and extract element 0 so the non-store version isn't too horrible.
1603 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1604 "movhpd\t{$src, $dst|$dst, $src}",
1605 [(store (f64 (vector_extract
1606 (v2f64 (unpckh VR128:$src, (undef))),
1607 (iPTR 0))), addr:$dst)]>;
1609 // SSE2 instructions without OpSize prefix
1610 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1611 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1612 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1613 TB, Requires<[HasSSE2]>;
1614 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1615 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1616 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1617 (bitconvert (memopv2i64 addr:$src))))]>,
1618 TB, Requires<[HasSSE2]>;
1620 // SSE2 instructions with XS prefix
1621 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1622 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1623 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1624 XS, Requires<[HasSSE2]>;
1625 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1626 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1627 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1628 (bitconvert (memopv2i64 addr:$src))))]>,
1629 XS, Requires<[HasSSE2]>;
1631 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1632 "cvtps2dq\t{$src, $dst|$dst, $src}",
1633 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1634 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1635 "cvtps2dq\t{$src, $dst|$dst, $src}",
1636 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1637 (memop addr:$src)))]>;
1638 // SSE2 packed instructions with XS prefix
1639 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1640 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1641 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1642 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1644 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1645 "cvttps2dq\t{$src, $dst|$dst, $src}",
1647 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1648 XS, Requires<[HasSSE2]>;
1649 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1650 "cvttps2dq\t{$src, $dst|$dst, $src}",
1651 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1652 (memop addr:$src)))]>,
1653 XS, Requires<[HasSSE2]>;
1655 // SSE2 packed instructions with XD prefix
1656 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1657 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1658 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1659 XD, Requires<[HasSSE2]>;
1660 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1661 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1662 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1663 (memop addr:$src)))]>,
1664 XD, Requires<[HasSSE2]>;
1666 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1667 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1668 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1669 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1670 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1671 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1672 (memop addr:$src)))]>;
1674 // SSE2 instructions without OpSize prefix
1675 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1676 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1677 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1678 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1680 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1681 "cvtps2pd\t{$src, $dst|$dst, $src}",
1682 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1683 TB, Requires<[HasSSE2]>;
1684 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1685 "cvtps2pd\t{$src, $dst|$dst, $src}",
1686 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1687 (load addr:$src)))]>,
1688 TB, Requires<[HasSSE2]>;
1690 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1691 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1692 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1693 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1696 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1697 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1698 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1699 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1700 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1701 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1702 (memop addr:$src)))]>;
1704 // Match intrinsics which expect XMM operand(s).
1705 // Aliases for intrinsics
1706 let Constraints = "$src1 = $dst" in {
1707 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1708 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1709 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1710 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1712 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1713 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1714 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1715 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1716 (loadi32 addr:$src2)))]>;
1717 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1718 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1719 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1720 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1722 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1723 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1724 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1725 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1726 (load addr:$src2)))]>;
1727 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1728 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1729 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1730 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1731 VR128:$src2))]>, XS,
1732 Requires<[HasSSE2]>;
1733 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1734 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1735 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1736 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1737 (load addr:$src2)))]>, XS,
1738 Requires<[HasSSE2]>;
1743 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1745 /// In addition, we also have a special variant of the scalar form here to
1746 /// represent the associated intrinsic operation. This form is unlike the
1747 /// plain scalar form, in that it takes an entire vector (instead of a
1748 /// scalar) and leaves the top elements undefined.
1750 /// And, we have a special variant form for a full-vector intrinsic form.
1752 /// These four forms can each have a reg or a mem operand, so there are a
1753 /// total of eight "instructions".
1755 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1759 bit Commutable = 0> {
1760 // Scalar operation, reg.
1761 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1762 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1763 [(set FR64:$dst, (OpNode FR64:$src))]> {
1764 let isCommutable = Commutable;
1767 // Scalar operation, mem.
1768 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1769 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1770 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1772 // Vector operation, reg.
1773 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1774 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1775 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1776 let isCommutable = Commutable;
1779 // Vector operation, mem.
1780 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1781 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1782 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1784 // Intrinsic operation, reg.
1785 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1786 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1787 [(set VR128:$dst, (F64Int VR128:$src))]> {
1788 let isCommutable = Commutable;
1791 // Intrinsic operation, mem.
1792 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1793 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1794 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1796 // Vector intrinsic operation, reg
1797 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1798 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1799 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1800 let isCommutable = Commutable;
1803 // Vector intrinsic operation, mem
1804 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1805 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1806 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1810 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1811 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1813 // There is no f64 version of the reciprocal approximation instructions.
1815 let Constraints = "$src1 = $dst" in {
1816 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1817 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1818 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1819 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1820 VR128:$src, imm:$cc))]>;
1821 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1822 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1823 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1824 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1825 (memop addr:$src), imm:$cc))]>;
1827 // Accept explicit immediate argument form instead of comparison code.
1828 let isAsmParserOnly = 1 in {
1829 def CMPPDrri_alt : PDIi8<0xC2, MRMSrcReg,
1830 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1831 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1832 def CMPPDrmi_alt : PDIi8<0xC2, MRMSrcMem,
1833 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1834 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1837 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1838 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1839 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1840 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1842 // Shuffle and unpack instructions
1843 let Constraints = "$src1 = $dst" in {
1844 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1845 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1846 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1848 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1849 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1850 (outs VR128:$dst), (ins VR128:$src1,
1851 f128mem:$src2, i8imm:$src3),
1852 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1855 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1857 let AddedComplexity = 10 in {
1858 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1859 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1860 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1862 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1863 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1864 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1865 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1867 (v2f64 (unpckh VR128:$src1,
1868 (memopv2f64 addr:$src2))))]>;
1870 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1871 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1872 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1874 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1875 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1876 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1877 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1879 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1880 } // AddedComplexity
1881 } // Constraints = "$src1 = $dst"
1884 //===---------------------------------------------------------------------===//
1885 // SSE integer instructions
1886 let ExeDomain = SSEPackedInt in {
1888 // Move Instructions
1889 let neverHasSideEffects = 1 in
1890 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1891 "movdqa\t{$src, $dst|$dst, $src}", []>;
1892 let canFoldAsLoad = 1, mayLoad = 1 in
1893 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1894 "movdqa\t{$src, $dst|$dst, $src}",
1895 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1897 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1898 "movdqa\t{$src, $dst|$dst, $src}",
1899 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1900 let canFoldAsLoad = 1, mayLoad = 1 in
1901 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1902 "movdqu\t{$src, $dst|$dst, $src}",
1903 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1904 XS, Requires<[HasSSE2]>;
1906 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1907 "movdqu\t{$src, $dst|$dst, $src}",
1908 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1909 XS, Requires<[HasSSE2]>;
1911 // Intrinsic forms of MOVDQU load and store
1912 let canFoldAsLoad = 1 in
1913 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1914 "movdqu\t{$src, $dst|$dst, $src}",
1915 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1916 XS, Requires<[HasSSE2]>;
1917 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1918 "movdqu\t{$src, $dst|$dst, $src}",
1919 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1920 XS, Requires<[HasSSE2]>;
1922 let Constraints = "$src1 = $dst" in {
1924 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1925 bit Commutable = 0> {
1926 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1927 (ins VR128:$src1, VR128:$src2),
1928 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1929 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1930 let isCommutable = Commutable;
1932 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1933 (ins VR128:$src1, i128mem:$src2),
1934 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1935 [(set VR128:$dst, (IntId VR128:$src1,
1936 (bitconvert (memopv2i64
1940 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1942 Intrinsic IntId, Intrinsic IntId2> {
1943 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1944 (ins VR128:$src1, VR128:$src2),
1945 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1946 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1947 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1948 (ins VR128:$src1, i128mem:$src2),
1949 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1950 [(set VR128:$dst, (IntId VR128:$src1,
1951 (bitconvert (memopv2i64 addr:$src2))))]>;
1952 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
1953 (ins VR128:$src1, i32i8imm:$src2),
1954 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1955 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1958 /// PDI_binop_rm - Simple SSE2 binary operator.
1959 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1960 ValueType OpVT, bit Commutable = 0> {
1961 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1962 (ins VR128:$src1, VR128:$src2),
1963 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1964 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1965 let isCommutable = Commutable;
1967 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1968 (ins VR128:$src1, i128mem:$src2),
1969 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1970 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1971 (bitconvert (memopv2i64 addr:$src2)))))]>;
1974 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1976 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1977 /// to collapse (bitconvert VT to VT) into its operand.
1979 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1980 bit Commutable = 0> {
1981 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1982 (ins VR128:$src1, VR128:$src2),
1983 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1984 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1985 let isCommutable = Commutable;
1987 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1988 (ins VR128:$src1, i128mem:$src2),
1989 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1990 [(set VR128:$dst, (OpNode VR128:$src1,
1991 (memopv2i64 addr:$src2)))]>;
1994 } // Constraints = "$src1 = $dst"
1995 } // ExeDomain = SSEPackedInt
1997 // 128-bit Integer Arithmetic
1999 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2000 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2001 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2002 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2004 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2005 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2006 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2007 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2009 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2010 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2011 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2012 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2014 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2015 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2016 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2017 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2019 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2021 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2022 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
2023 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2025 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2027 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2028 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2031 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2032 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2033 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2034 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2035 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2038 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2039 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2040 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2041 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2042 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2043 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2045 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2046 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2047 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2048 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2049 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2050 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2052 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2053 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2054 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2055 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2057 // 128-bit logical shifts.
2058 let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
2059 ExeDomain = SSEPackedInt in {
2060 def PSLLDQri : PDIi8<0x73, MRM7r,
2061 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2062 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2063 def PSRLDQri : PDIi8<0x73, MRM3r,
2064 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2065 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2066 // PSRADQri doesn't exist in SSE[1-3].
2069 let Predicates = [HasSSE2] in {
2070 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2071 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2072 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2073 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2074 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2075 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2076 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2077 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2078 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2079 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2081 // Shift up / down and insert zero's.
2082 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2083 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2084 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2085 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2089 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2090 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2091 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2093 let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
2094 def PANDNrr : PDI<0xDF, MRMSrcReg,
2095 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2096 "pandn\t{$src2, $dst|$dst, $src2}",
2097 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2100 def PANDNrm : PDI<0xDF, MRMSrcMem,
2101 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2102 "pandn\t{$src2, $dst|$dst, $src2}",
2103 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2104 (memopv2i64 addr:$src2))))]>;
2107 // SSE2 Integer comparison
2108 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2109 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2110 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2111 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2112 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2113 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2115 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2116 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2117 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2118 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2119 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2120 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2121 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2122 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2123 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2124 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2125 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2126 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2128 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2129 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2130 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2131 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2132 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2133 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2134 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2135 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2136 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2137 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2138 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2139 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2142 // Pack instructions
2143 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2144 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2145 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2147 let ExeDomain = SSEPackedInt in {
2149 // Shuffle and unpack instructions
2150 let AddedComplexity = 5 in {
2151 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2152 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2153 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2154 [(set VR128:$dst, (v4i32 (pshufd:$src2
2155 VR128:$src1, (undef))))]>;
2156 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2157 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2158 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2159 [(set VR128:$dst, (v4i32 (pshufd:$src2
2160 (bc_v4i32 (memopv2i64 addr:$src1)),
2164 // SSE2 with ImmT == Imm8 and XS prefix.
2165 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2166 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2167 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2168 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2170 XS, Requires<[HasSSE2]>;
2171 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2172 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2173 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2174 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2175 (bc_v8i16 (memopv2i64 addr:$src1)),
2177 XS, Requires<[HasSSE2]>;
2179 // SSE2 with ImmT == Imm8 and XD prefix.
2180 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2181 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2182 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2183 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2185 XD, Requires<[HasSSE2]>;
2186 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2187 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2188 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2189 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2190 (bc_v8i16 (memopv2i64 addr:$src1)),
2192 XD, Requires<[HasSSE2]>;
2194 // Unpack instructions
2195 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2196 PatFrag unp_frag, PatFrag bc_frag> {
2197 def rr : PDI<opc, MRMSrcReg,
2198 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2199 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2200 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2201 def rm : PDI<opc, MRMSrcMem,
2202 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2203 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2204 [(set VR128:$dst, (unp_frag VR128:$src1,
2205 (bc_frag (memopv2i64
2209 let Constraints = "$src1 = $dst" in {
2210 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2211 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2212 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2214 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2215 /// knew to collapse (bitconvert VT to VT) into its operand.
2216 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2217 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2218 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2220 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2221 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2222 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2223 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2225 (v2i64 (unpckl VR128:$src1,
2226 (memopv2i64 addr:$src2))))]>;
2228 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2229 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2230 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2232 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2233 /// knew to collapse (bitconvert VT to VT) into its operand.
2234 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2235 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2236 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2238 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2239 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2240 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2241 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2243 (v2i64 (unpckh VR128:$src1,
2244 (memopv2i64 addr:$src2))))]>;
2248 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2249 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2250 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2251 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2253 let Constraints = "$src1 = $dst" in {
2254 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2255 (outs VR128:$dst), (ins VR128:$src1,
2256 GR32:$src2, i32i8imm:$src3),
2257 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2259 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2260 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2261 (outs VR128:$dst), (ins VR128:$src1,
2262 i16mem:$src2, i32i8imm:$src3),
2263 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2265 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2270 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2271 "pmovmskb\t{$src, $dst|$dst, $src}",
2272 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2274 // Conditional store
2276 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2277 "maskmovdqu\t{$mask, $src|$src, $mask}",
2278 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2281 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2282 "maskmovdqu\t{$mask, $src|$src, $mask}",
2283 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2285 } // ExeDomain = SSEPackedInt
2287 // Non-temporal stores
2288 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2289 "movntpd\t{$src, $dst|$dst, $src}",
2290 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2291 let ExeDomain = SSEPackedInt in
2292 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2293 "movntdq\t{$src, $dst|$dst, $src}",
2294 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2295 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2296 "movnti\t{$src, $dst|$dst, $src}",
2297 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2298 TB, Requires<[HasSSE2]>;
2300 let AddedComplexity = 400 in { // Prefer non-temporal versions
2301 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2302 "movntpd\t{$src, $dst|$dst, $src}",
2303 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2305 let ExeDomain = SSEPackedInt in
2306 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2307 "movntdq\t{$src, $dst|$dst, $src}",
2308 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2312 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2313 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2314 TB, Requires<[HasSSE2]>;
2316 // Load, store, and memory fence
2317 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2318 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2319 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2320 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2322 // Pause. This "instruction" is encoded as "rep; nop", so even though it
2323 // was introduced with SSE2, it's backward compatible.
2324 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
2326 //TODO: custom lower this so as to never even generate the noop
2327 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2329 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2330 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2331 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2334 // Alias instructions that map zero vector to pxor / xorp* for sse.
2335 // We set canFoldAsLoad because this can be converted to a constant-pool
2336 // load of an all-ones value if folding it would be beneficial.
2337 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2338 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2339 // FIXME: Change encoding to pseudo.
2340 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2341 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2343 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2344 "movd\t{$src, $dst|$dst, $src}",
2346 (v4i32 (scalar_to_vector GR32:$src)))]>;
2347 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2348 "movd\t{$src, $dst|$dst, $src}",
2350 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2352 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2353 "movd\t{$src, $dst|$dst, $src}",
2354 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2356 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2357 "movd\t{$src, $dst|$dst, $src}",
2358 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2360 // SSE2 instructions with XS prefix
2361 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2362 "movq\t{$src, $dst|$dst, $src}",
2364 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2365 Requires<[HasSSE2]>;
2366 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2367 "movq\t{$src, $dst|$dst, $src}",
2368 [(store (i64 (vector_extract (v2i64 VR128:$src),
2369 (iPTR 0))), addr:$dst)]>;
2371 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2372 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2374 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2375 "movd\t{$src, $dst|$dst, $src}",
2376 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2378 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2379 "movd\t{$src, $dst|$dst, $src}",
2380 [(store (i32 (vector_extract (v4i32 VR128:$src),
2381 (iPTR 0))), addr:$dst)]>;
2383 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2384 "movd\t{$src, $dst|$dst, $src}",
2385 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2386 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2387 "movd\t{$src, $dst|$dst, $src}",
2388 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2390 // Store / copy lower 64-bits of a XMM register.
2391 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2392 "movq\t{$src, $dst|$dst, $src}",
2393 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2395 // movd / movq to XMM register zero-extends
2396 let AddedComplexity = 15 in {
2397 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2398 "movd\t{$src, $dst|$dst, $src}",
2399 [(set VR128:$dst, (v4i32 (X86vzmovl
2400 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2401 // This is X86-64 only.
2402 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2403 "mov{d|q}\t{$src, $dst|$dst, $src}",
2404 [(set VR128:$dst, (v2i64 (X86vzmovl
2405 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2408 let AddedComplexity = 20 in {
2409 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2410 "movd\t{$src, $dst|$dst, $src}",
2412 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2413 (loadi32 addr:$src))))))]>;
2415 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2416 (MOVZDI2PDIrm addr:$src)>;
2417 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2418 (MOVZDI2PDIrm addr:$src)>;
2419 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2420 (MOVZDI2PDIrm addr:$src)>;
2422 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2423 "movq\t{$src, $dst|$dst, $src}",
2425 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2426 (loadi64 addr:$src))))))]>, XS,
2427 Requires<[HasSSE2]>;
2429 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2430 (MOVZQI2PQIrm addr:$src)>;
2431 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2432 (MOVZQI2PQIrm addr:$src)>;
2433 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2436 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2437 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2438 let AddedComplexity = 15 in
2439 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2440 "movq\t{$src, $dst|$dst, $src}",
2441 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2442 XS, Requires<[HasSSE2]>;
2444 let AddedComplexity = 20 in {
2445 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2446 "movq\t{$src, $dst|$dst, $src}",
2447 [(set VR128:$dst, (v2i64 (X86vzmovl
2448 (loadv2i64 addr:$src))))]>,
2449 XS, Requires<[HasSSE2]>;
2451 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2452 (MOVZPQILo2PQIrm addr:$src)>;
2455 // Instructions for the disassembler
2456 // xr = XMM register
2459 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2460 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2462 //===---------------------------------------------------------------------===//
2463 // SSE3 Instructions
2464 //===---------------------------------------------------------------------===//
2466 // Move Instructions
2467 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2468 "movshdup\t{$src, $dst|$dst, $src}",
2469 [(set VR128:$dst, (v4f32 (movshdup
2470 VR128:$src, (undef))))]>;
2471 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2472 "movshdup\t{$src, $dst|$dst, $src}",
2473 [(set VR128:$dst, (movshdup
2474 (memopv4f32 addr:$src), (undef)))]>;
2476 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2477 "movsldup\t{$src, $dst|$dst, $src}",
2478 [(set VR128:$dst, (v4f32 (movsldup
2479 VR128:$src, (undef))))]>;
2480 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2481 "movsldup\t{$src, $dst|$dst, $src}",
2482 [(set VR128:$dst, (movsldup
2483 (memopv4f32 addr:$src), (undef)))]>;
2485 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2486 "movddup\t{$src, $dst|$dst, $src}",
2487 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2488 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2489 "movddup\t{$src, $dst|$dst, $src}",
2491 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2494 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2496 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2498 let AddedComplexity = 5 in {
2499 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2500 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2501 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2502 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2503 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2504 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2505 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2506 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2510 let Constraints = "$src1 = $dst" in {
2511 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2512 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2513 "addsubps\t{$src2, $dst|$dst, $src2}",
2514 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2516 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2517 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2518 "addsubps\t{$src2, $dst|$dst, $src2}",
2519 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2520 (memop addr:$src2)))]>;
2521 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2522 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2523 "addsubpd\t{$src2, $dst|$dst, $src2}",
2524 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2526 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2527 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2528 "addsubpd\t{$src2, $dst|$dst, $src2}",
2529 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2530 (memop addr:$src2)))]>;
2533 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2534 "lddqu\t{$src, $dst|$dst, $src}",
2535 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2538 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2539 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2540 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2541 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2542 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2543 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2544 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2545 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2546 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2547 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2548 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2549 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2550 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2551 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2552 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2553 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2555 let Constraints = "$src1 = $dst" in {
2556 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2557 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2558 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2559 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2560 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2561 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2562 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2563 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2566 // Thread synchronization
2567 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2568 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2569 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2570 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2572 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2573 let AddedComplexity = 15 in
2574 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2575 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2576 let AddedComplexity = 20 in
2577 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2578 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2580 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2581 let AddedComplexity = 15 in
2582 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2583 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2584 let AddedComplexity = 20 in
2585 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2586 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2588 //===---------------------------------------------------------------------===//
2589 // SSSE3 Instructions
2590 //===---------------------------------------------------------------------===//
2592 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2593 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2594 Intrinsic IntId64, Intrinsic IntId128> {
2595 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2597 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2599 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2600 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2602 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2604 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2606 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2607 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2610 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2612 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2615 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2618 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2619 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2620 Intrinsic IntId64, Intrinsic IntId128> {
2621 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2623 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2624 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2626 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2628 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2631 (bitconvert (memopv4i16 addr:$src))))]>;
2633 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2635 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2636 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2639 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2641 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2644 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2647 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2648 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2649 Intrinsic IntId64, Intrinsic IntId128> {
2650 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2652 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2653 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2655 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2657 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2660 (bitconvert (memopv2i32 addr:$src))))]>;
2662 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2664 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2665 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2668 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2670 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2673 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2676 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2677 int_x86_ssse3_pabs_b,
2678 int_x86_ssse3_pabs_b_128>;
2679 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2680 int_x86_ssse3_pabs_w,
2681 int_x86_ssse3_pabs_w_128>;
2682 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2683 int_x86_ssse3_pabs_d,
2684 int_x86_ssse3_pabs_d_128>;
2686 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2687 let Constraints = "$src1 = $dst" in {
2688 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2689 Intrinsic IntId64, Intrinsic IntId128,
2690 bit Commutable = 0> {
2691 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2692 (ins VR64:$src1, VR64:$src2),
2693 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2694 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2695 let isCommutable = Commutable;
2697 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2698 (ins VR64:$src1, i64mem:$src2),
2699 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2701 (IntId64 VR64:$src1,
2702 (bitconvert (memopv8i8 addr:$src2))))]>;
2704 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2705 (ins VR128:$src1, VR128:$src2),
2706 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2707 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2709 let isCommutable = Commutable;
2711 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2712 (ins VR128:$src1, i128mem:$src2),
2713 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2715 (IntId128 VR128:$src1,
2716 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2720 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2721 let Constraints = "$src1 = $dst" in {
2722 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2723 Intrinsic IntId64, Intrinsic IntId128,
2724 bit Commutable = 0> {
2725 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2726 (ins VR64:$src1, VR64:$src2),
2727 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2728 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2729 let isCommutable = Commutable;
2731 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2732 (ins VR64:$src1, i64mem:$src2),
2733 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2735 (IntId64 VR64:$src1,
2736 (bitconvert (memopv4i16 addr:$src2))))]>;
2738 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2739 (ins VR128:$src1, VR128:$src2),
2740 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2741 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2743 let isCommutable = Commutable;
2745 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2746 (ins VR128:$src1, i128mem:$src2),
2747 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2749 (IntId128 VR128:$src1,
2750 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2754 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2755 let Constraints = "$src1 = $dst" in {
2756 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2757 Intrinsic IntId64, Intrinsic IntId128,
2758 bit Commutable = 0> {
2759 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2760 (ins VR64:$src1, VR64:$src2),
2761 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2762 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2763 let isCommutable = Commutable;
2765 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2766 (ins VR64:$src1, i64mem:$src2),
2767 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2769 (IntId64 VR64:$src1,
2770 (bitconvert (memopv2i32 addr:$src2))))]>;
2772 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2773 (ins VR128:$src1, VR128:$src2),
2774 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2775 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2777 let isCommutable = Commutable;
2779 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2780 (ins VR128:$src1, i128mem:$src2),
2781 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2783 (IntId128 VR128:$src1,
2784 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2788 let ImmT = NoImm in { // None of these have i8 immediate fields.
2789 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2790 int_x86_ssse3_phadd_w,
2791 int_x86_ssse3_phadd_w_128>;
2792 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2793 int_x86_ssse3_phadd_d,
2794 int_x86_ssse3_phadd_d_128>;
2795 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2796 int_x86_ssse3_phadd_sw,
2797 int_x86_ssse3_phadd_sw_128>;
2798 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2799 int_x86_ssse3_phsub_w,
2800 int_x86_ssse3_phsub_w_128>;
2801 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2802 int_x86_ssse3_phsub_d,
2803 int_x86_ssse3_phsub_d_128>;
2804 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2805 int_x86_ssse3_phsub_sw,
2806 int_x86_ssse3_phsub_sw_128>;
2807 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2808 int_x86_ssse3_pmadd_ub_sw,
2809 int_x86_ssse3_pmadd_ub_sw_128>;
2810 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2811 int_x86_ssse3_pmul_hr_sw,
2812 int_x86_ssse3_pmul_hr_sw_128, 1>;
2814 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2815 int_x86_ssse3_pshuf_b,
2816 int_x86_ssse3_pshuf_b_128>;
2817 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2818 int_x86_ssse3_psign_b,
2819 int_x86_ssse3_psign_b_128>;
2820 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2821 int_x86_ssse3_psign_w,
2822 int_x86_ssse3_psign_w_128>;
2823 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2824 int_x86_ssse3_psign_d,
2825 int_x86_ssse3_psign_d_128>;
2828 // palignr patterns.
2829 let Constraints = "$src1 = $dst" in {
2830 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2831 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2832 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2834 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2835 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2836 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2839 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2840 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2841 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2843 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2844 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2845 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2849 let AddedComplexity = 5 in {
2851 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
2852 (PALIGNR64rr VR64:$src2, VR64:$src1,
2853 (SHUFFLE_get_palign_imm VR64:$src3))>,
2854 Requires<[HasSSSE3]>;
2855 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
2856 (PALIGNR64rr VR64:$src2, VR64:$src1,
2857 (SHUFFLE_get_palign_imm VR64:$src3))>,
2858 Requires<[HasSSSE3]>;
2859 def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
2860 (PALIGNR64rr VR64:$src2, VR64:$src1,
2861 (SHUFFLE_get_palign_imm VR64:$src3))>,
2862 Requires<[HasSSSE3]>;
2863 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
2864 (PALIGNR64rr VR64:$src2, VR64:$src1,
2865 (SHUFFLE_get_palign_imm VR64:$src3))>,
2866 Requires<[HasSSSE3]>;
2867 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
2868 (PALIGNR64rr VR64:$src2, VR64:$src1,
2869 (SHUFFLE_get_palign_imm VR64:$src3))>,
2870 Requires<[HasSSSE3]>;
2872 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2873 (PALIGNR128rr VR128:$src2, VR128:$src1,
2874 (SHUFFLE_get_palign_imm VR128:$src3))>,
2875 Requires<[HasSSSE3]>;
2876 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2877 (PALIGNR128rr VR128:$src2, VR128:$src1,
2878 (SHUFFLE_get_palign_imm VR128:$src3))>,
2879 Requires<[HasSSSE3]>;
2880 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2881 (PALIGNR128rr VR128:$src2, VR128:$src1,
2882 (SHUFFLE_get_palign_imm VR128:$src3))>,
2883 Requires<[HasSSSE3]>;
2884 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2885 (PALIGNR128rr VR128:$src2, VR128:$src1,
2886 (SHUFFLE_get_palign_imm VR128:$src3))>,
2887 Requires<[HasSSSE3]>;
2890 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2891 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2892 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2893 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2895 //===---------------------------------------------------------------------===//
2896 // Non-Instruction Patterns
2897 //===---------------------------------------------------------------------===//
2899 // extload f32 -> f64. This matches load+fextend because we have a hack in
2900 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2902 // Since these loads aren't folded into the fextend, we have to match it
2904 let Predicates = [HasSSE2] in
2905 def : Pat<(fextend (loadf32 addr:$src)),
2906 (CVTSS2SDrm addr:$src)>;
2909 let Predicates = [HasSSE2] in {
2910 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2911 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2912 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2913 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2914 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2915 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2916 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2917 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2918 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2919 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2920 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2921 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2922 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2923 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2924 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2925 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2926 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2927 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2928 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2929 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2930 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2931 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2932 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2933 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2934 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2935 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2936 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2937 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2938 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2939 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2942 // Move scalar to XMM zero-extended
2943 // movd to XMM register zero-extends
2944 let AddedComplexity = 15 in {
2945 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2946 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2947 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
2948 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2949 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
2950 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2951 (MOVSSrr (v4f32 (V_SET0PS)),
2952 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
2953 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2954 (MOVSSrr (v4i32 (V_SET0PI)),
2955 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
2958 // Splat v2f64 / v2i64
2959 let AddedComplexity = 10 in {
2960 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2961 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2962 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
2963 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2964 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
2965 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2966 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
2967 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2970 // Special unary SHUFPSrri case.
2971 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2972 (SHUFPSrri VR128:$src1, VR128:$src1,
2973 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2974 let AddedComplexity = 5 in
2975 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
2976 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2977 Requires<[HasSSE2]>;
2978 // Special unary SHUFPDrri case.
2979 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2980 (SHUFPDrri VR128:$src1, VR128:$src1,
2981 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2982 Requires<[HasSSE2]>;
2983 // Special unary SHUFPDrri case.
2984 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2985 (SHUFPDrri VR128:$src1, VR128:$src1,
2986 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2987 Requires<[HasSSE2]>;
2988 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2989 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
2990 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2991 Requires<[HasSSE2]>;
2993 // Special binary v4i32 shuffle cases with SHUFPS.
2994 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2995 (SHUFPSrri VR128:$src1, VR128:$src2,
2996 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2997 Requires<[HasSSE2]>;
2998 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
2999 (SHUFPSrmi VR128:$src1, addr:$src2,
3000 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3001 Requires<[HasSSE2]>;
3002 // Special binary v2i64 shuffle cases using SHUFPDrri.
3003 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3004 (SHUFPDrri VR128:$src1, VR128:$src2,
3005 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3006 Requires<[HasSSE2]>;
3008 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3009 let AddedComplexity = 15 in {
3010 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3011 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3012 Requires<[OptForSpeed, HasSSE2]>;
3013 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3014 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3015 Requires<[OptForSpeed, HasSSE2]>;
3017 let AddedComplexity = 10 in {
3018 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3019 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3020 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3021 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3022 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3023 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3024 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3025 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3028 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3029 let AddedComplexity = 15 in {
3030 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3031 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3032 Requires<[OptForSpeed, HasSSE2]>;
3033 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3034 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3035 Requires<[OptForSpeed, HasSSE2]>;
3037 let AddedComplexity = 10 in {
3038 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3039 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3040 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3041 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3042 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3043 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3044 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3045 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3048 let AddedComplexity = 20 in {
3049 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3050 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3051 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3053 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3054 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3055 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3057 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3058 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3059 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3060 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3061 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3064 let AddedComplexity = 20 in {
3065 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3066 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3067 (MOVLPSrm VR128:$src1, addr:$src2)>;
3068 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3069 (MOVLPDrm VR128:$src1, addr:$src2)>;
3070 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3071 (MOVLPSrm VR128:$src1, addr:$src2)>;
3072 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3073 (MOVLPDrm VR128:$src1, addr:$src2)>;
3076 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3077 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3078 (MOVLPSmr addr:$src1, VR128:$src2)>;
3079 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3080 (MOVLPDmr addr:$src1, VR128:$src2)>;
3081 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3083 (MOVLPSmr addr:$src1, VR128:$src2)>;
3084 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3085 (MOVLPDmr addr:$src1, VR128:$src2)>;
3087 let AddedComplexity = 15 in {
3088 // Setting the lowest element in the vector.
3089 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3090 (MOVSSrr (v4i32 VR128:$src1),
3091 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3092 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3093 (MOVSDrr (v2i64 VR128:$src1),
3094 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3096 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3097 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3098 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3099 Requires<[HasSSE2]>;
3100 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3101 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3102 Requires<[HasSSE2]>;
3105 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3106 // fall back to this for SSE1)
3107 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3108 (SHUFPSrri VR128:$src2, VR128:$src1,
3109 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3111 // Set lowest element and zero upper elements.
3112 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3113 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3115 // Some special case pandn patterns.
3116 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3118 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3119 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3121 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3122 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3124 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3126 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3127 (memop addr:$src2))),
3128 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3129 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3130 (memop addr:$src2))),
3131 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3132 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3133 (memop addr:$src2))),
3134 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3136 // vector -> vector casts
3137 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3138 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3139 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3140 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3141 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3142 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3143 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3144 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3146 // Use movaps / movups for SSE integer load / store (one byte shorter).
3147 def : Pat<(alignedloadv4i32 addr:$src),
3148 (MOVAPSrm addr:$src)>;
3149 def : Pat<(loadv4i32 addr:$src),
3150 (MOVUPSrm addr:$src)>;
3151 def : Pat<(alignedloadv2i64 addr:$src),
3152 (MOVAPSrm addr:$src)>;
3153 def : Pat<(loadv2i64 addr:$src),
3154 (MOVUPSrm addr:$src)>;
3156 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3157 (MOVAPSmr addr:$dst, VR128:$src)>;
3158 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3159 (MOVAPSmr addr:$dst, VR128:$src)>;
3160 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3161 (MOVAPSmr addr:$dst, VR128:$src)>;
3162 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3163 (MOVAPSmr addr:$dst, VR128:$src)>;
3164 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3165 (MOVUPSmr addr:$dst, VR128:$src)>;
3166 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3167 (MOVUPSmr addr:$dst, VR128:$src)>;
3168 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3169 (MOVUPSmr addr:$dst, VR128:$src)>;
3170 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3171 (MOVUPSmr addr:$dst, VR128:$src)>;
3173 //===----------------------------------------------------------------------===//
3174 // SSE4.1 Instructions
3175 //===----------------------------------------------------------------------===//
3177 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3180 Intrinsic V2F64Int> {
3181 // Intrinsic operation, reg.
3182 // Vector intrinsic operation, reg
3183 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3184 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3185 !strconcat(OpcodeStr,
3186 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3187 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3190 // Vector intrinsic operation, mem
3191 def PSm_Int : Ii8<opcps, MRMSrcMem,
3192 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3193 !strconcat(OpcodeStr,
3194 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3196 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3198 Requires<[HasSSE41]>;
3200 // Vector intrinsic operation, reg
3201 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3202 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3203 !strconcat(OpcodeStr,
3204 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3205 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3208 // Vector intrinsic operation, mem
3209 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3210 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3211 !strconcat(OpcodeStr,
3212 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3214 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3218 let Constraints = "$src1 = $dst" in {
3219 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3223 // Intrinsic operation, reg.
3224 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3226 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3227 !strconcat(OpcodeStr,
3228 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3230 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3233 // Intrinsic operation, mem.
3234 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3236 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3237 !strconcat(OpcodeStr,
3238 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3240 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3243 // Intrinsic operation, reg.
3244 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3246 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3247 !strconcat(OpcodeStr,
3248 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3250 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3253 // Intrinsic operation, mem.
3254 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3256 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3257 !strconcat(OpcodeStr,
3258 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3260 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3265 // FP round - roundss, roundps, roundsd, roundpd
3266 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3267 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3268 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3269 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3271 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3272 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3273 Intrinsic IntId128> {
3274 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3276 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3277 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3278 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3280 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3283 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3286 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3287 int_x86_sse41_phminposuw>;
3289 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3290 let Constraints = "$src1 = $dst" in {
3291 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3292 Intrinsic IntId128, bit Commutable = 0> {
3293 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3294 (ins VR128:$src1, VR128:$src2),
3295 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3296 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3298 let isCommutable = Commutable;
3300 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3301 (ins VR128:$src1, i128mem:$src2),
3302 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3304 (IntId128 VR128:$src1,
3305 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3309 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3310 int_x86_sse41_pcmpeqq, 1>;
3311 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3312 int_x86_sse41_packusdw, 0>;
3313 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3314 int_x86_sse41_pminsb, 1>;
3315 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3316 int_x86_sse41_pminsd, 1>;
3317 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3318 int_x86_sse41_pminud, 1>;
3319 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3320 int_x86_sse41_pminuw, 1>;
3321 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3322 int_x86_sse41_pmaxsb, 1>;
3323 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3324 int_x86_sse41_pmaxsd, 1>;
3325 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3326 int_x86_sse41_pmaxud, 1>;
3327 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3328 int_x86_sse41_pmaxuw, 1>;
3330 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3332 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3333 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3334 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3335 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3337 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3338 let Constraints = "$src1 = $dst" in {
3339 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3340 SDNode OpNode, Intrinsic IntId128,
3341 bit Commutable = 0> {
3342 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3343 (ins VR128:$src1, VR128:$src2),
3344 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3345 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3346 VR128:$src2))]>, OpSize {
3347 let isCommutable = Commutable;
3349 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3350 (ins VR128:$src1, VR128:$src2),
3351 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3352 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3354 let isCommutable = Commutable;
3356 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3357 (ins VR128:$src1, i128mem:$src2),
3358 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3360 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3361 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3362 (ins VR128:$src1, i128mem:$src2),
3363 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3365 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3370 /// SS48I_binop_rm - Simple SSE41 binary operator.
3371 let Constraints = "$src1 = $dst" in {
3372 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3373 ValueType OpVT, bit Commutable = 0> {
3374 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3375 (ins VR128:$src1, VR128:$src2),
3376 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3377 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3379 let isCommutable = Commutable;
3381 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3382 (ins VR128:$src1, i128mem:$src2),
3383 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3384 [(set VR128:$dst, (OpNode VR128:$src1,
3385 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3390 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3392 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3393 let Constraints = "$src1 = $dst" in {
3394 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3395 Intrinsic IntId128, bit Commutable = 0> {
3396 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3397 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3398 !strconcat(OpcodeStr,
3399 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3401 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3403 let isCommutable = Commutable;
3405 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3406 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3407 !strconcat(OpcodeStr,
3408 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3410 (IntId128 VR128:$src1,
3411 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3416 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3417 int_x86_sse41_blendps, 0>;
3418 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3419 int_x86_sse41_blendpd, 0>;
3420 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3421 int_x86_sse41_pblendw, 0>;
3422 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3423 int_x86_sse41_dpps, 1>;
3424 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3425 int_x86_sse41_dppd, 1>;
3426 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3427 int_x86_sse41_mpsadbw, 0>;
3430 /// SS41I_ternary_int - SSE 4.1 ternary operator
3431 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3432 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3433 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3434 (ins VR128:$src1, VR128:$src2),
3435 !strconcat(OpcodeStr,
3436 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3437 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3440 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3441 (ins VR128:$src1, i128mem:$src2),
3442 !strconcat(OpcodeStr,
3443 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3446 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3450 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3451 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3452 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3455 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3456 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3457 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3458 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3460 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3461 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3463 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3467 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3468 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3469 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3470 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3471 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3472 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3474 // Common patterns involving scalar load.
3475 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3476 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3477 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3478 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3480 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3481 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3482 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3483 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3485 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3486 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3487 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3488 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3490 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3491 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3492 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3493 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3495 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3496 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3497 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3498 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3500 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3501 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3502 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3503 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3506 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3507 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3509 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3511 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3512 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3514 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3518 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3519 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3520 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3521 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3523 // Common patterns involving scalar load
3524 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3525 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3526 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3527 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3529 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3530 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3531 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3532 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3535 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3536 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3538 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3540 // Expecting a i16 load any extended to i32 value.
3541 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3542 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3543 [(set VR128:$dst, (IntId (bitconvert
3544 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3548 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3549 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3551 // Common patterns involving scalar load
3552 def : Pat<(int_x86_sse41_pmovsxbq
3553 (bitconvert (v4i32 (X86vzmovl
3554 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3555 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3557 def : Pat<(int_x86_sse41_pmovzxbq
3558 (bitconvert (v4i32 (X86vzmovl
3559 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3560 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3563 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3564 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3565 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3566 (ins VR128:$src1, i32i8imm:$src2),
3567 !strconcat(OpcodeStr,
3568 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3569 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3571 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3572 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3573 !strconcat(OpcodeStr,
3574 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3577 // There's an AssertZext in the way of writing the store pattern
3578 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3581 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3584 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3585 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3586 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3587 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3588 !strconcat(OpcodeStr,
3589 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3592 // There's an AssertZext in the way of writing the store pattern
3593 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3596 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3599 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3600 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3601 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3602 (ins VR128:$src1, i32i8imm:$src2),
3603 !strconcat(OpcodeStr,
3604 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3606 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3607 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3608 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3609 !strconcat(OpcodeStr,
3610 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3611 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3612 addr:$dst)]>, OpSize;
3615 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3618 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3620 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3621 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3622 (ins VR128:$src1, i32i8imm:$src2),
3623 !strconcat(OpcodeStr,
3624 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3626 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3628 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3629 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3630 !strconcat(OpcodeStr,
3631 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3632 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3633 addr:$dst)]>, OpSize;
3636 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3638 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3639 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3642 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3643 Requires<[HasSSE41]>;
3645 let Constraints = "$src1 = $dst" in {
3646 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3647 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3648 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3649 !strconcat(OpcodeStr,
3650 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3652 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3653 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3654 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3655 !strconcat(OpcodeStr,
3656 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3658 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3659 imm:$src3))]>, OpSize;
3663 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3665 let Constraints = "$src1 = $dst" in {
3666 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3667 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3668 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3669 !strconcat(OpcodeStr,
3670 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3672 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3674 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3675 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3676 !strconcat(OpcodeStr,
3677 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3679 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3680 imm:$src3)))]>, OpSize;
3684 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3686 // insertps has a few different modes, there's the first two here below which
3687 // are optimized inserts that won't zero arbitrary elements in the destination
3688 // vector. The next one matches the intrinsic and could zero arbitrary elements
3689 // in the target vector.
3690 let Constraints = "$src1 = $dst" in {
3691 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3692 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3693 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3694 !strconcat(OpcodeStr,
3695 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3697 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3699 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3700 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3701 !strconcat(OpcodeStr,
3702 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3704 (X86insrtps VR128:$src1,
3705 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3706 imm:$src3))]>, OpSize;
3710 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3712 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3713 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3715 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3716 // the intel intrinsic that corresponds to this.
3717 let Defs = [EFLAGS] in {
3718 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3719 "ptest \t{$src2, $src1|$src1, $src2}",
3720 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
3722 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3723 "ptest \t{$src2, $src1|$src1, $src2}",
3724 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
3728 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3729 "movntdqa\t{$src, $dst|$dst, $src}",
3730 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3734 //===----------------------------------------------------------------------===//
3735 // SSE4.2 Instructions
3736 //===----------------------------------------------------------------------===//
3738 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3739 let Constraints = "$src1 = $dst" in {
3740 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3741 Intrinsic IntId128, bit Commutable = 0> {
3742 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3743 (ins VR128:$src1, VR128:$src2),
3744 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3745 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3747 let isCommutable = Commutable;
3749 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3750 (ins VR128:$src1, i128mem:$src2),
3751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3753 (IntId128 VR128:$src1,
3754 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3758 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3760 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3761 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3762 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3763 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3765 // crc intrinsic instruction
3766 // This set of instructions are only rm, the only difference is the size
3768 let Constraints = "$src1 = $dst" in {
3769 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3770 (ins GR32:$src1, i8mem:$src2),
3771 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3773 (int_x86_sse42_crc32_8 GR32:$src1,
3774 (load addr:$src2)))]>;
3775 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3776 (ins GR32:$src1, GR8:$src2),
3777 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3779 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3780 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3781 (ins GR32:$src1, i16mem:$src2),
3782 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3784 (int_x86_sse42_crc32_16 GR32:$src1,
3785 (load addr:$src2)))]>,
3787 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3788 (ins GR32:$src1, GR16:$src2),
3789 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3791 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3793 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3794 (ins GR32:$src1, i32mem:$src2),
3795 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3797 (int_x86_sse42_crc32_32 GR32:$src1,
3798 (load addr:$src2)))]>;
3799 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3800 (ins GR32:$src1, GR32:$src2),
3801 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3803 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3804 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3805 (ins GR64:$src1, i8mem:$src2),
3806 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3808 (int_x86_sse42_crc64_8 GR64:$src1,
3809 (load addr:$src2)))]>,
3811 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3812 (ins GR64:$src1, GR8:$src2),
3813 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3815 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3817 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3818 (ins GR64:$src1, i64mem:$src2),
3819 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3821 (int_x86_sse42_crc64_64 GR64:$src1,
3822 (load addr:$src2)))]>,
3824 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3825 (ins GR64:$src1, GR64:$src2),
3826 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3828 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3832 // String/text processing instructions.
3833 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3834 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3835 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3836 "#PCMPISTRM128rr PSEUDO!",
3837 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3838 imm:$src3))]>, OpSize;
3839 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3840 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3841 "#PCMPISTRM128rm PSEUDO!",
3842 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3843 imm:$src3))]>, OpSize;
3846 let Defs = [XMM0, EFLAGS] in {
3847 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3848 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3849 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3850 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3851 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3852 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3855 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3856 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3857 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3858 "#PCMPESTRM128rr PSEUDO!",
3860 (int_x86_sse42_pcmpestrm128
3861 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3863 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3864 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3865 "#PCMPESTRM128rm PSEUDO!",
3866 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3867 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3871 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3872 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3873 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3874 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3875 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3876 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3877 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3880 let Defs = [ECX, EFLAGS] in {
3881 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3882 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3883 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3884 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3885 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3886 (implicit EFLAGS)]>, OpSize;
3887 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3888 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3889 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3890 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3891 (implicit EFLAGS)]>, OpSize;
3895 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3896 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3897 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3898 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3899 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3900 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3902 let Defs = [ECX, EFLAGS] in {
3903 let Uses = [EAX, EDX] in {
3904 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3905 def rr : SS42AI<0x61, MRMSrcReg, (outs),
3906 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3907 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3908 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
3909 (implicit EFLAGS)]>, OpSize;
3910 def rm : SS42AI<0x61, MRMSrcMem, (outs),
3911 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3912 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3914 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
3915 (implicit EFLAGS)]>, OpSize;
3920 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
3921 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
3922 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
3923 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
3924 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
3925 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
3927 //===----------------------------------------------------------------------===//
3928 // AES-NI Instructions
3929 //===----------------------------------------------------------------------===//
3931 let Constraints = "$src1 = $dst" in {
3932 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
3933 Intrinsic IntId128, bit Commutable = 0> {
3934 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
3935 (ins VR128:$src1, VR128:$src2),
3936 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3937 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3939 let isCommutable = Commutable;
3941 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
3942 (ins VR128:$src1, i128mem:$src2),
3943 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3945 (IntId128 VR128:$src1,
3946 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3950 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
3951 int_x86_aesni_aesenc>;
3952 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
3953 int_x86_aesni_aesenclast>;
3954 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
3955 int_x86_aesni_aesdec>;
3956 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
3957 int_x86_aesni_aesdeclast>;
3959 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
3960 (AESENCrr VR128:$src1, VR128:$src2)>;
3961 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
3962 (AESENCrm VR128:$src1, addr:$src2)>;
3963 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
3964 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
3965 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
3966 (AESENCLASTrm VR128:$src1, addr:$src2)>;
3967 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
3968 (AESDECrr VR128:$src1, VR128:$src2)>;
3969 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
3970 (AESDECrm VR128:$src1, addr:$src2)>;
3971 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
3972 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
3973 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
3974 (AESDECLASTrm VR128:$src1, addr:$src2)>;
3976 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
3978 "aesimc\t{$src1, $dst|$dst, $src1}",
3980 (int_x86_aesni_aesimc VR128:$src1))]>,
3983 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
3984 (ins i128mem:$src1),
3985 "aesimc\t{$src1, $dst|$dst, $src1}",
3987 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
3990 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
3991 (ins VR128:$src1, i8imm:$src2),
3992 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3994 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
3996 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
3997 (ins i128mem:$src1, i8imm:$src2),
3998 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4000 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),