1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
244 Domain d, OpndItins itins, bit Is2Addr = 1> {
245 let isCommutable = 1 in {
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
251 Sched<[itins.Sched]>;
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
258 Sched<[itins.Sched.Folded, ReadAfterLd]>;
261 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
262 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
263 string asm, string SSEVer, string FPSizeStr,
264 Operand memopr, ComplexPattern mem_cpat,
265 Domain d, OpndItins itins, bit Is2Addr = 1> {
266 let isCodeGenOnly = 1 in {
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
269 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 [(set RC:$dst, (!cast<Intrinsic>(
272 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
273 RC:$src1, RC:$src2))], itins.rr, d>,
274 Sched<[itins.Sched]>;
275 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
277 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
279 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
280 SSEVer, "_", OpcodeStr, FPSizeStr))
281 RC:$src1, mem_cpat:$src2))], itins.rm, d>,
282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
286 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
288 RegisterClass RC, ValueType vt,
289 X86MemOperand x86memop, PatFrag mem_frag,
290 Domain d, OpndItins itins, bit Is2Addr = 1> {
291 let isCommutable = 1 in
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
297 Sched<[itins.Sched]>;
299 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
305 Sched<[itins.Sched.Folded, ReadAfterLd]>;
308 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
309 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
310 string OpcodeStr, X86MemOperand x86memop,
311 list<dag> pat_rr, list<dag> pat_rm,
313 let isCommutable = 1, hasSideEffects = 0 in
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
318 pat_rr, NoItinerary, d>,
319 Sched<[WriteVecLogic]>;
320 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
324 pat_rm, NoItinerary, d>,
325 Sched<[WriteVecLogicLd, ReadAfterLd]>;
328 //===----------------------------------------------------------------------===//
329 // Non-instruction patterns
330 //===----------------------------------------------------------------------===//
332 // A vector extract of the first f32/f64 position is a subregister copy
333 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
338 // A 128-bit subvector extract from the first 256-bit vector position
339 // is a subregister copy that needs no instruction.
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
355 // A 128-bit subvector insert to the first 256-bit vector position
356 // is a subregister copy that needs no instruction.
357 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
372 // Implicitly promote a 32-bit scalar to a vector.
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 // Implicitly promote a 64-bit scalar to a vector.
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
383 // Bitcasts between 128-bit vector types. Return the original type since
384 // no instruction is needed for the conversion
385 let Predicates = [HasSSE2] in {
386 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
387 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
388 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
392 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
397 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
402 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
407 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
412 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(f128 (bitconvert (i128 FR128:$src))), (f128 FR128:$src)>;
417 def : Pat<(i128 (bitconvert (f128 FR128:$src))), (i128 FR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
551 string asm_opr, Domain d = GenericDomain> {
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr,
569 Domain d = GenericDomain> {
571 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
572 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
575 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
576 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
577 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
578 VEX, VEX_LIG, Sched<[WriteStore]>;
580 let Constraints = "$src1 = $dst" in {
581 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
582 "\t{$src2, $dst|$dst, $src2}", d>;
585 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
586 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
587 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
591 // Loading from memory automatically zeroing upper bits.
592 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
593 PatFrag mem_pat, string OpcodeStr,
594 Domain d = GenericDomain> {
595 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
597 [(set RC:$dst, (mem_pat addr:$src))],
598 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
599 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
600 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
601 [(set RC:$dst, (mem_pat addr:$src))],
602 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
605 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
606 SSEPackedSingle>, XS;
607 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
608 SSEPackedDouble>, XD;
610 let canFoldAsLoad = 1, isReMaterializable = 1 in {
611 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
612 SSEPackedSingle>, XS;
614 let AddedComplexity = 20 in
615 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
616 SSEPackedDouble>, XD;
620 let Predicates = [UseAVX] in {
621 let AddedComplexity = 20 in {
622 // MOVSSrm zeros the high parts of the register; represent this
623 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
624 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
628 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
629 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
631 // MOVSDrm zeros the high parts of the register; represent this
632 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
633 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
641 def : Pat<(v2f64 (X86vzload addr:$src)),
642 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
644 // Represent the same patterns above but in the form they appear for
646 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
647 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
648 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
649 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
650 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
651 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
654 // Extract and store.
655 def : Pat<(store (f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
657 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
658 def : Pat<(store (f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
660 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
662 // Shuffle with VMOVSS
663 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
664 (VMOVSSrr (v4i32 VR128:$src1),
665 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
666 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
667 (VMOVSSrr (v4f32 VR128:$src1),
668 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
671 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
672 (SUBREG_TO_REG (i32 0),
673 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
674 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
676 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
677 (SUBREG_TO_REG (i32 0),
678 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
679 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
682 // Shuffle with VMOVSD
683 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
689 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
690 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
693 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
694 (SUBREG_TO_REG (i32 0),
695 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
696 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
698 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
699 (SUBREG_TO_REG (i32 0),
700 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
701 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
704 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
705 // is during lowering, where it's not possible to recognize the fold cause
706 // it has two uses through a bitcast. One use disappears at isel time and the
707 // fold opportunity reappears.
708 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
714 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
715 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
718 let Predicates = [UseSSE1] in {
719 let Predicates = [NoSSE41], AddedComplexity = 15 in {
720 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
721 // MOVSS to the lower bits.
722 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
723 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
724 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
725 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
726 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
727 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
730 let AddedComplexity = 20 in {
731 // MOVSSrm already zeros the high parts of the register.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
740 // Extract and store.
741 def : Pat<(store (f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
743 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
745 // Shuffle with MOVSS
746 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
748 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
749 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
752 let Predicates = [UseSSE2] in {
753 let Predicates = [NoSSE41], AddedComplexity = 15 in {
754 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
755 // MOVSD to the lower bits.
756 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
757 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
760 let AddedComplexity = 20 in {
761 // MOVSDrm already zeros the high parts of the register.
762 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
770 def : Pat<(v2f64 (X86vzload addr:$src)),
771 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
774 // Extract and store.
775 def : Pat<(store (f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
777 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
779 // Shuffle with MOVSD
780 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
786 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
787 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
789 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
790 // is during lowering, where it's not possible to recognize the fold because
791 // it has two uses through a bitcast. One use disappears at isel time and the
792 // fold opportunity reappears.
793 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
799 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
800 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
803 //===----------------------------------------------------------------------===//
804 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
805 //===----------------------------------------------------------------------===//
807 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
808 X86MemOperand x86memop, PatFrag ld_frag,
809 string asm, Domain d,
811 bit IsReMaterializable = 1> {
812 let hasSideEffects = 0 in
813 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
814 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
815 Sched<[WriteFShuffle]>;
816 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
817 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
818 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
819 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
823 let Predicates = [HasAVX, NoVLX] in {
824 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
830 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
837 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
838 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
840 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
841 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
843 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
844 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
846 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
847 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
851 let Predicates = [UseSSE1] in {
852 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
853 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
855 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
856 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
859 let Predicates = [UseSSE2] in {
860 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
861 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
863 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
864 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
868 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
869 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
870 "movaps\t{$src, $dst|$dst, $src}",
871 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
872 IIC_SSE_MOVA_P_MR>, VEX;
873 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
874 "movapd\t{$src, $dst|$dst, $src}",
875 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
876 IIC_SSE_MOVA_P_MR>, VEX;
877 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
878 "movups\t{$src, $dst|$dst, $src}",
879 [(store (v4f32 VR128:$src), addr:$dst)],
880 IIC_SSE_MOVU_P_MR>, VEX;
881 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
882 "movupd\t{$src, $dst|$dst, $src}",
883 [(store (v2f64 VR128:$src), addr:$dst)],
884 IIC_SSE_MOVU_P_MR>, VEX;
885 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
886 "movaps\t{$src, $dst|$dst, $src}",
887 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
888 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
889 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
890 "movapd\t{$src, $dst|$dst, $src}",
891 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
892 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
893 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
894 "movups\t{$src, $dst|$dst, $src}",
895 [(store (v8f32 VR256:$src), addr:$dst)],
896 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
897 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
898 "movupd\t{$src, $dst|$dst, $src}",
899 [(store (v4f64 VR256:$src), addr:$dst)],
900 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
904 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
905 SchedRW = [WriteFShuffle] in {
906 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
908 "movaps\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX;
910 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
912 "movapd\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVA_P_RR>, VEX;
914 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
916 "movups\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX;
918 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
920 "movupd\t{$src, $dst|$dst, $src}", [],
921 IIC_SSE_MOVU_P_RR>, VEX;
922 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
924 "movaps\t{$src, $dst|$dst, $src}", [],
925 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
926 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
928 "movapd\t{$src, $dst|$dst, $src}", [],
929 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
930 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
932 "movups\t{$src, $dst|$dst, $src}", [],
933 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
934 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
936 "movupd\t{$src, $dst|$dst, $src}", [],
937 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
940 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
941 (VMOVUPSYmr addr:$dst, VR256:$src)>;
942 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
943 (VMOVUPDYmr addr:$dst, VR256:$src)>;
945 let SchedRW = [WriteStore] in {
946 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
947 "movaps\t{$src, $dst|$dst, $src}",
948 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
950 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
951 "movapd\t{$src, $dst|$dst, $src}",
952 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
954 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
955 "movups\t{$src, $dst|$dst, $src}",
956 [(store (v4f32 VR128:$src), addr:$dst)],
958 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
959 "movupd\t{$src, $dst|$dst, $src}",
960 [(store (v2f64 VR128:$src), addr:$dst)],
965 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
966 SchedRW = [WriteFShuffle] in {
967 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
968 "movaps\t{$src, $dst|$dst, $src}", [],
970 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
971 "movapd\t{$src, $dst|$dst, $src}", [],
973 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
974 "movups\t{$src, $dst|$dst, $src}", [],
976 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
977 "movupd\t{$src, $dst|$dst, $src}", [],
981 let Predicates = [HasAVX] in {
982 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
983 (VMOVUPSmr addr:$dst, VR128:$src)>;
984 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
985 (VMOVUPDmr addr:$dst, VR128:$src)>;
988 let Predicates = [UseSSE1] in
989 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
990 (MOVUPSmr addr:$dst, VR128:$src)>;
991 let Predicates = [UseSSE2] in
992 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
993 (MOVUPDmr addr:$dst, VR128:$src)>;
995 // Use vmovaps/vmovups for AVX integer load/store.
996 let Predicates = [HasAVX, NoVLX] in {
997 // 128-bit load/store
998 def : Pat<(alignedloadv2i64 addr:$src),
999 (VMOVAPSrm addr:$src)>;
1000 def : Pat<(loadv2i64 addr:$src),
1001 (VMOVUPSrm addr:$src)>;
1003 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1004 (VMOVAPSmr addr:$dst, VR128:$src)>;
1005 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1006 (VMOVAPSmr addr:$dst, VR128:$src)>;
1007 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1008 (VMOVAPSmr addr:$dst, VR128:$src)>;
1009 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1010 (VMOVAPSmr addr:$dst, VR128:$src)>;
1011 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1012 (VMOVUPSmr addr:$dst, VR128:$src)>;
1013 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1014 (VMOVUPSmr addr:$dst, VR128:$src)>;
1015 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1016 (VMOVUPSmr addr:$dst, VR128:$src)>;
1017 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1018 (VMOVUPSmr addr:$dst, VR128:$src)>;
1020 // 256-bit load/store
1021 def : Pat<(alignedloadv4i64 addr:$src),
1022 (VMOVAPSYrm addr:$src)>;
1023 def : Pat<(loadv4i64 addr:$src),
1024 (VMOVUPSYrm addr:$src)>;
1025 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1026 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1027 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1028 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1029 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1030 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1031 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1032 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1033 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1034 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1035 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1036 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1037 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1038 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1039 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1040 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1042 // Special patterns for storing subvector extracts of lower 128-bits
1043 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1044 def : Pat<(alignedstore (v2f64 (extract_subvector
1045 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1046 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1047 def : Pat<(alignedstore (v4f32 (extract_subvector
1048 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1049 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1050 def : Pat<(alignedstore (v2i64 (extract_subvector
1051 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1052 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1053 def : Pat<(alignedstore (v4i32 (extract_subvector
1054 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1055 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1056 def : Pat<(alignedstore (v8i16 (extract_subvector
1057 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1058 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1059 def : Pat<(alignedstore (v16i8 (extract_subvector
1060 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1061 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1063 def : Pat<(store (v2f64 (extract_subvector
1064 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1065 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1066 def : Pat<(store (v4f32 (extract_subvector
1067 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1068 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1069 def : Pat<(store (v2i64 (extract_subvector
1070 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1071 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1072 def : Pat<(store (v4i32 (extract_subvector
1073 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1074 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1075 def : Pat<(store (v8i16 (extract_subvector
1076 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1077 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1078 def : Pat<(store (v16i8 (extract_subvector
1079 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1080 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1083 // Use movaps / movups for SSE integer load / store (one byte shorter).
1084 // The instructions selected below are then converted to MOVDQA/MOVDQU
1085 // during the SSE domain pass.
1086 let Predicates = [UseSSE1] in {
1087 def : Pat<(alignedloadv2i64 addr:$src),
1088 (MOVAPSrm addr:$src)>;
1089 def : Pat<(loadv2i64 addr:$src),
1090 (MOVUPSrm addr:$src)>;
1092 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1093 (MOVAPSmr addr:$dst, VR128:$src)>;
1094 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1095 (MOVAPSmr addr:$dst, VR128:$src)>;
1096 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1097 (MOVAPSmr addr:$dst, VR128:$src)>;
1098 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1099 (MOVAPSmr addr:$dst, VR128:$src)>;
1100 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1101 (MOVUPSmr addr:$dst, VR128:$src)>;
1102 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1103 (MOVUPSmr addr:$dst, VR128:$src)>;
1104 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1105 (MOVUPSmr addr:$dst, VR128:$src)>;
1106 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1107 (MOVUPSmr addr:$dst, VR128:$src)>;
1110 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1111 // bits are disregarded. FIXME: Set encoding to pseudo!
1112 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1113 let isCodeGenOnly = 1 in {
1114 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1115 "movaps\t{$src, $dst|$dst, $src}",
1116 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1117 IIC_SSE_MOVA_P_RM>, VEX;
1118 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1119 "movapd\t{$src, $dst|$dst, $src}",
1120 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1121 IIC_SSE_MOVA_P_RM>, VEX;
1122 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1123 "movaps\t{$src, $dst|$dst, $src}",
1124 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1126 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1127 "movapd\t{$src, $dst|$dst, $src}",
1128 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1133 //===----------------------------------------------------------------------===//
1134 // SSE 1 & 2 - Move Low packed FP Instructions
1135 //===----------------------------------------------------------------------===//
1137 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1138 string base_opc, string asm_opr,
1139 InstrItinClass itin> {
1140 def PSrm : PI<opc, MRMSrcMem,
1141 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1142 !strconcat(base_opc, "s", asm_opr),
1144 (psnode VR128:$src1,
1145 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1146 itin, SSEPackedSingle>, PS,
1147 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1149 def PDrm : PI<opc, MRMSrcMem,
1150 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1151 !strconcat(base_opc, "d", asm_opr),
1152 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1153 (scalar_to_vector (loadf64 addr:$src2)))))],
1154 itin, SSEPackedDouble>, PD,
1155 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1159 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1160 string base_opc, InstrItinClass itin> {
1161 let Predicates = [UseAVX] in
1162 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1163 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1166 let Constraints = "$src1 = $dst" in
1167 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1168 "\t{$src2, $dst|$dst, $src2}",
1172 let AddedComplexity = 20 in {
1173 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1177 let SchedRW = [WriteStore] in {
1178 let Predicates = [UseAVX] in {
1179 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1180 "movlps\t{$src, $dst|$dst, $src}",
1181 [(store (f64 (extractelt (bc_v2f64 (v4f32 VR128:$src)),
1182 (iPTR 0))), addr:$dst)],
1183 IIC_SSE_MOV_LH>, VEX;
1184 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1185 "movlpd\t{$src, $dst|$dst, $src}",
1186 [(store (f64 (extractelt (v2f64 VR128:$src),
1187 (iPTR 0))), addr:$dst)],
1188 IIC_SSE_MOV_LH>, VEX;
1190 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1191 "movlps\t{$src, $dst|$dst, $src}",
1192 [(store (f64 (extractelt (bc_v2f64 (v4f32 VR128:$src)),
1193 (iPTR 0))), addr:$dst)],
1195 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1196 "movlpd\t{$src, $dst|$dst, $src}",
1197 [(store (f64 (extractelt (v2f64 VR128:$src),
1198 (iPTR 0))), addr:$dst)],
1202 let Predicates = [UseAVX] in {
1203 // Shuffle with VMOVLPS
1204 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1205 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1206 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1207 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1209 // Shuffle with VMOVLPD
1210 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1211 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1213 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1214 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1215 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1216 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1219 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1221 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1222 def : Pat<(store (v4i32 (X86Movlps
1223 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1224 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1225 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1227 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1228 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1230 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1233 let Predicates = [UseSSE1] in {
1234 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1235 def : Pat<(store (i64 (extractelt (bc_v2i64 (v4f32 VR128:$src2)),
1236 (iPTR 0))), addr:$src1),
1237 (MOVLPSmr addr:$src1, VR128:$src2)>;
1239 // Shuffle with MOVLPS
1240 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1241 (MOVLPSrm VR128:$src1, addr:$src2)>;
1242 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1243 (MOVLPSrm VR128:$src1, addr:$src2)>;
1244 def : Pat<(X86Movlps VR128:$src1,
1245 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1246 (MOVLPSrm VR128:$src1, addr:$src2)>;
1249 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1251 (MOVLPSmr addr:$src1, VR128:$src2)>;
1252 def : Pat<(store (v4i32 (X86Movlps
1253 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1255 (MOVLPSmr addr:$src1, VR128:$src2)>;
1258 let Predicates = [UseSSE2] in {
1259 // Shuffle with MOVLPD
1260 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1261 (MOVLPDrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1263 (MOVLPDrm VR128:$src1, addr:$src2)>;
1264 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1265 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1266 (MOVLPDrm VR128:$src1, addr:$src2)>;
1269 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1271 (MOVLPDmr addr:$src1, VR128:$src2)>;
1272 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1274 (MOVLPDmr addr:$src1, VR128:$src2)>;
1277 //===----------------------------------------------------------------------===//
1278 // SSE 1 & 2 - Move Hi packed FP Instructions
1279 //===----------------------------------------------------------------------===//
1281 let AddedComplexity = 20 in {
1282 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1286 let SchedRW = [WriteStore] in {
1287 // v2f64 extract element 1 is always custom lowered to unpack high to low
1288 // and extract element 0 so the non-store version isn't too horrible.
1289 let Predicates = [UseAVX] in {
1290 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1291 "movhps\t{$src, $dst|$dst, $src}",
1292 [(store (f64 (extractelt
1293 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1294 (bc_v2f64 (v4f32 VR128:$src))),
1295 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1296 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1297 "movhpd\t{$src, $dst|$dst, $src}",
1298 [(store (f64 (extractelt
1299 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1300 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1302 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1303 "movhps\t{$src, $dst|$dst, $src}",
1304 [(store (f64 (extractelt
1305 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1306 (bc_v2f64 (v4f32 VR128:$src))),
1307 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1308 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1309 "movhpd\t{$src, $dst|$dst, $src}",
1310 [(store (f64 (extractelt
1311 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1312 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1315 let Predicates = [UseAVX] in {
1317 def : Pat<(X86Movlhps VR128:$src1,
1318 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1319 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1320 def : Pat<(X86Movlhps VR128:$src1,
1321 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1322 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1326 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1327 // is during lowering, where it's not possible to recognize the load fold
1328 // cause it has two uses through a bitcast. One use disappears at isel time
1329 // and the fold opportunity reappears.
1330 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1331 (scalar_to_vector (loadf64 addr:$src2)))),
1332 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1333 // Also handle an i64 load because that may get selected as a faster way to
1335 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1336 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1337 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1339 def : Pat<(store (f64 (extractelt
1340 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1341 (iPTR 0))), addr:$dst),
1342 (VMOVHPDmr addr:$dst, VR128:$src)>;
1345 let Predicates = [UseSSE1] in {
1347 def : Pat<(X86Movlhps VR128:$src1,
1348 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1349 (MOVHPSrm VR128:$src1, addr:$src2)>;
1350 def : Pat<(X86Movlhps VR128:$src1,
1351 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1352 (MOVHPSrm VR128:$src1, addr:$src2)>;
1355 let Predicates = [UseSSE2] in {
1358 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1359 // is during lowering, where it's not possible to recognize the load fold
1360 // cause it has two uses through a bitcast. One use disappears at isel time
1361 // and the fold opportunity reappears.
1362 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1363 (scalar_to_vector (loadf64 addr:$src2)))),
1364 (MOVHPDrm VR128:$src1, addr:$src2)>;
1365 // Also handle an i64 load because that may get selected as a faster way to
1367 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1368 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1369 (MOVHPDrm VR128:$src1, addr:$src2)>;
1371 def : Pat<(store (f64 (extractelt
1372 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1373 (iPTR 0))), addr:$dst),
1374 (MOVHPDmr addr:$dst, VR128:$src)>;
1377 //===----------------------------------------------------------------------===//
1378 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1379 //===----------------------------------------------------------------------===//
1381 let AddedComplexity = 20, Predicates = [UseAVX] in {
1382 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1383 (ins VR128:$src1, VR128:$src2),
1384 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1386 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1388 VEX_4V, Sched<[WriteFShuffle]>;
1389 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1390 (ins VR128:$src1, VR128:$src2),
1391 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1393 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1395 VEX_4V, Sched<[WriteFShuffle]>;
1397 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1398 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1399 (ins VR128:$src1, VR128:$src2),
1400 "movlhps\t{$src2, $dst|$dst, $src2}",
1402 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1403 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1404 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1405 (ins VR128:$src1, VR128:$src2),
1406 "movhlps\t{$src2, $dst|$dst, $src2}",
1408 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1409 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1412 let Predicates = [UseAVX] in {
1414 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1415 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1416 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1417 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1420 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1421 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1424 let Predicates = [UseSSE1] in {
1426 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1427 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1428 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1429 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1432 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1433 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1436 //===----------------------------------------------------------------------===//
1437 // SSE 1 & 2 - Conversion Instructions
1438 //===----------------------------------------------------------------------===//
1440 def SSE_CVT_PD : OpndItins<
1441 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1444 let Sched = WriteCvtI2F in
1445 def SSE_CVT_PS : OpndItins<
1446 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1449 let Sched = WriteCvtI2F in
1450 def SSE_CVT_Scalar : OpndItins<
1451 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1454 let Sched = WriteCvtF2I in
1455 def SSE_CVT_SS2SI_32 : OpndItins<
1456 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1459 let Sched = WriteCvtF2I in
1460 def SSE_CVT_SS2SI_64 : OpndItins<
1461 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1464 let Sched = WriteCvtF2I in
1465 def SSE_CVT_SD2SI : OpndItins<
1466 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1469 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1470 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1471 string asm, OpndItins itins> {
1472 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1473 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1474 itins.rr>, Sched<[itins.Sched]>;
1475 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1476 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1477 itins.rm>, Sched<[itins.Sched.Folded]>;
1480 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1481 X86MemOperand x86memop, string asm, Domain d,
1483 let hasSideEffects = 0 in {
1484 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1485 [], itins.rr, d>, Sched<[itins.Sched]>;
1487 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1488 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1492 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1493 X86MemOperand x86memop, string asm> {
1494 let hasSideEffects = 0, Predicates = [UseAVX] in {
1495 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1496 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1497 Sched<[WriteCvtI2F]>;
1499 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1500 (ins DstRC:$src1, x86memop:$src),
1501 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1502 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1503 } // hasSideEffects = 0
1506 let Predicates = [UseAVX] in {
1507 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1508 "cvttss2si\t{$src, $dst|$dst, $src}",
1511 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1512 "cvttss2si\t{$src, $dst|$dst, $src}",
1514 XS, VEX, VEX_W, VEX_LIG;
1515 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1516 "cvttsd2si\t{$src, $dst|$dst, $src}",
1519 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1520 "cvttsd2si\t{$src, $dst|$dst, $src}",
1522 XD, VEX, VEX_W, VEX_LIG;
1524 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1525 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1526 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1527 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1528 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1529 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1530 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1531 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1532 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1533 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1534 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1535 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1536 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1537 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1538 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1539 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1541 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1542 // register, but the same isn't true when only using memory operands,
1543 // provide other assembly "l" and "q" forms to address this explicitly
1544 // where appropriate to do so.
1545 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1546 XS, VEX_4V, VEX_LIG;
1547 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1548 XS, VEX_4V, VEX_W, VEX_LIG;
1549 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1550 XD, VEX_4V, VEX_LIG;
1551 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1552 XD, VEX_4V, VEX_W, VEX_LIG;
1554 let Predicates = [UseAVX] in {
1555 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1556 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1557 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1558 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1560 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1561 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1562 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1563 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1564 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1565 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1566 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1567 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1569 def : Pat<(f32 (sint_to_fp GR32:$src)),
1570 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1571 def : Pat<(f32 (sint_to_fp GR64:$src)),
1572 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1573 def : Pat<(f64 (sint_to_fp GR32:$src)),
1574 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1575 def : Pat<(f64 (sint_to_fp GR64:$src)),
1576 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1579 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1580 "cvttss2si\t{$src, $dst|$dst, $src}",
1581 SSE_CVT_SS2SI_32>, XS;
1582 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1583 "cvttss2si\t{$src, $dst|$dst, $src}",
1584 SSE_CVT_SS2SI_64>, XS, REX_W;
1585 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1586 "cvttsd2si\t{$src, $dst|$dst, $src}",
1588 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1589 "cvttsd2si\t{$src, $dst|$dst, $src}",
1590 SSE_CVT_SD2SI>, XD, REX_W;
1591 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1592 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1593 SSE_CVT_Scalar>, XS;
1594 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1595 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1596 SSE_CVT_Scalar>, XS, REX_W;
1597 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1598 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1599 SSE_CVT_Scalar>, XD;
1600 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1601 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1602 SSE_CVT_Scalar>, XD, REX_W;
1604 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1605 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1606 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1607 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1608 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1609 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1610 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1611 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1612 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1613 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1614 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1615 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1616 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1617 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1618 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1619 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1621 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1622 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1623 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1624 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1626 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1627 // and/or XMM operand(s).
1629 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1630 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1631 string asm, OpndItins itins> {
1632 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1633 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1634 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1635 Sched<[itins.Sched]>;
1636 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1637 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1638 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1639 Sched<[itins.Sched.Folded]>;
1642 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1643 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1644 PatFrag ld_frag, string asm, OpndItins itins,
1646 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1648 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1649 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1650 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1651 itins.rr>, Sched<[itins.Sched]>;
1652 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1653 (ins DstRC:$src1, x86memop:$src2),
1655 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1656 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1657 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1658 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1661 let Predicates = [UseAVX] in {
1662 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1663 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1664 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1665 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1666 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1667 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1669 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1670 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1671 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1672 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1675 let isCodeGenOnly = 1 in {
1676 let Predicates = [UseAVX] in {
1677 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1678 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1679 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1680 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1681 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1682 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1684 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1685 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1686 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1687 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1688 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1689 SSE_CVT_Scalar, 0>, XD,
1692 let Constraints = "$src1 = $dst" in {
1693 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1694 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1695 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1696 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1697 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1698 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1699 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1700 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1701 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1702 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1703 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1704 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1706 } // isCodeGenOnly = 1
1710 // Aliases for intrinsics
1711 let isCodeGenOnly = 1 in {
1712 let Predicates = [UseAVX] in {
1713 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1714 ssmem, sse_load_f32, "cvttss2si",
1715 SSE_CVT_SS2SI_32>, XS, VEX;
1716 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1717 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1718 "cvttss2si", SSE_CVT_SS2SI_64>,
1720 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1721 sdmem, sse_load_f64, "cvttsd2si",
1722 SSE_CVT_SD2SI>, XD, VEX;
1723 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1724 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1725 "cvttsd2si", SSE_CVT_SD2SI>,
1728 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1729 ssmem, sse_load_f32, "cvttss2si",
1730 SSE_CVT_SS2SI_32>, XS;
1731 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1732 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1733 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1734 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1735 sdmem, sse_load_f64, "cvttsd2si",
1737 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1738 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1739 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1740 } // isCodeGenOnly = 1
1742 let Predicates = [UseAVX] in {
1743 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1744 ssmem, sse_load_f32, "cvtss2si",
1745 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1746 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1747 ssmem, sse_load_f32, "cvtss2si",
1748 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1750 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1751 ssmem, sse_load_f32, "cvtss2si",
1752 SSE_CVT_SS2SI_32>, XS;
1753 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1754 ssmem, sse_load_f32, "cvtss2si",
1755 SSE_CVT_SS2SI_64>, XS, REX_W;
1757 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1758 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1759 SSEPackedSingle, SSE_CVT_PS>,
1760 PS, VEX, Requires<[HasAVX]>;
1761 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1762 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1763 SSEPackedSingle, SSE_CVT_PS>,
1764 PS, VEX, VEX_L, Requires<[HasAVX]>;
1766 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1767 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1768 SSEPackedSingle, SSE_CVT_PS>,
1769 PS, Requires<[UseSSE2]>;
1771 let Predicates = [UseAVX] in {
1772 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1773 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1774 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1775 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1776 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1777 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1778 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1779 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1780 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1781 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1782 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1783 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1784 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1785 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1786 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1787 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1790 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1791 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1792 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1793 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1794 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1795 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1796 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1797 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1798 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1799 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1800 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1801 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1802 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1803 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1804 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1805 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1809 // Convert scalar double to scalar single
1810 let hasSideEffects = 0, Predicates = [UseAVX] in {
1811 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1812 (ins FR64:$src1, FR64:$src2),
1813 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1814 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1815 Sched<[WriteCvtF2F]>;
1817 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1818 (ins FR64:$src1, f64mem:$src2),
1819 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1820 [], IIC_SSE_CVT_Scalar_RM>,
1821 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1822 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1825 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1828 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1829 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1830 [(set FR32:$dst, (fround FR64:$src))],
1831 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1832 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1833 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1834 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1835 IIC_SSE_CVT_Scalar_RM>,
1837 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1839 let isCodeGenOnly = 1 in {
1840 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1841 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1842 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1844 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1845 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1846 Sched<[WriteCvtF2F]>;
1847 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1848 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1849 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1850 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1851 VR128:$src1, sse_load_f64:$src2))],
1852 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1853 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1855 let Constraints = "$src1 = $dst" in {
1856 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1857 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1858 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1860 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1861 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1862 Sched<[WriteCvtF2F]>;
1863 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1864 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1865 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1866 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1867 VR128:$src1, sse_load_f64:$src2))],
1868 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1869 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1871 } // isCodeGenOnly = 1
1873 // Convert scalar single to scalar double
1874 // SSE2 instructions with XS prefix
1875 let hasSideEffects = 0, Predicates = [UseAVX] in {
1876 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1877 (ins FR32:$src1, FR32:$src2),
1878 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1879 [], IIC_SSE_CVT_Scalar_RR>,
1880 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1881 Sched<[WriteCvtF2F]>;
1883 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1884 (ins FR32:$src1, f32mem:$src2),
1885 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1886 [], IIC_SSE_CVT_Scalar_RM>,
1887 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1888 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1891 def : Pat<(f64 (fextend FR32:$src)),
1892 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1893 def : Pat<(fextend (loadf32 addr:$src)),
1894 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1896 def : Pat<(extloadf32 addr:$src),
1897 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1898 Requires<[UseAVX, OptForSize]>;
1899 def : Pat<(extloadf32 addr:$src),
1900 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1901 Requires<[UseAVX, OptForSpeed]>;
1903 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1904 "cvtss2sd\t{$src, $dst|$dst, $src}",
1905 [(set FR64:$dst, (fextend FR32:$src))],
1906 IIC_SSE_CVT_Scalar_RR>, XS,
1907 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1908 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1909 "cvtss2sd\t{$src, $dst|$dst, $src}",
1910 [(set FR64:$dst, (extloadf32 addr:$src))],
1911 IIC_SSE_CVT_Scalar_RM>, XS,
1912 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1914 // extload f32 -> f64. This matches load+fextend because we have a hack in
1915 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1917 // Since these loads aren't folded into the fextend, we have to match it
1919 def : Pat<(fextend (loadf32 addr:$src)),
1920 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1921 def : Pat<(extloadf32 addr:$src),
1922 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1924 let isCodeGenOnly = 1 in {
1925 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1926 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1927 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1929 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1930 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1931 Sched<[WriteCvtF2F]>;
1932 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1933 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1934 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1936 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1937 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1938 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1939 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1940 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1941 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1942 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1944 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1945 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1946 Sched<[WriteCvtF2F]>;
1947 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1948 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1949 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1951 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1952 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1953 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1955 } // isCodeGenOnly = 1
1957 // Convert packed single/double fp to doubleword
1958 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1959 "cvtps2dq\t{$src, $dst|$dst, $src}",
1960 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1961 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1962 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1963 "cvtps2dq\t{$src, $dst|$dst, $src}",
1965 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1966 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1967 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1968 "cvtps2dq\t{$src, $dst|$dst, $src}",
1970 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1971 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1972 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1973 "cvtps2dq\t{$src, $dst|$dst, $src}",
1975 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1976 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1977 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1978 "cvtps2dq\t{$src, $dst|$dst, $src}",
1979 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1980 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1981 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1982 "cvtps2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1985 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1988 // Convert Packed Double FP to Packed DW Integers
1989 let Predicates = [HasAVX] in {
1990 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1991 // register, but the same isn't true when using memory operands instead.
1992 // Provide other assembly rr and rm forms to address this explicitly.
1993 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1994 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1995 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1996 VEX, Sched<[WriteCvtF2I]>;
1999 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2000 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2001 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2002 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2004 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2005 Sched<[WriteCvtF2ILd]>;
2008 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2009 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2011 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2012 Sched<[WriteCvtF2I]>;
2013 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2014 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2016 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2017 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2018 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2019 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2022 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2023 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2025 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2026 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2027 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2028 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2029 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2030 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2032 // Convert with truncation packed single/double fp to doubleword
2033 // SSE2 packed instructions with XS prefix
2034 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2035 "cvttps2dq\t{$src, $dst|$dst, $src}",
2037 (int_x86_sse2_cvttps2dq VR128:$src))],
2038 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2039 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2040 "cvttps2dq\t{$src, $dst|$dst, $src}",
2041 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2042 (loadv4f32 addr:$src)))],
2043 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2044 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2045 "cvttps2dq\t{$src, $dst|$dst, $src}",
2047 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2048 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2049 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2050 "cvttps2dq\t{$src, $dst|$dst, $src}",
2051 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2052 (loadv8f32 addr:$src)))],
2053 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2054 Sched<[WriteCvtF2ILd]>;
2056 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2057 "cvttps2dq\t{$src, $dst|$dst, $src}",
2058 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2059 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2060 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2061 "cvttps2dq\t{$src, $dst|$dst, $src}",
2063 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2064 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2066 let Predicates = [HasAVX] in {
2067 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2068 (VCVTDQ2PSrr VR128:$src)>;
2069 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2070 (VCVTDQ2PSrm addr:$src)>;
2073 let Predicates = [HasAVX, NoVLX] in {
2074 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2075 (VCVTDQ2PSrr VR128:$src)>;
2076 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2077 (VCVTDQ2PSrm addr:$src)>;
2079 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2080 (VCVTTPS2DQrr VR128:$src)>;
2081 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2082 (VCVTTPS2DQrm addr:$src)>;
2084 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2085 (VCVTDQ2PSYrr VR256:$src)>;
2086 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2087 (VCVTDQ2PSYrm addr:$src)>;
2089 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2090 (VCVTTPS2DQYrr VR256:$src)>;
2091 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2092 (VCVTTPS2DQYrm addr:$src)>;
2095 let Predicates = [UseSSE2] in {
2096 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2097 (CVTDQ2PSrr VR128:$src)>;
2098 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2099 (CVTDQ2PSrm addr:$src)>;
2101 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2102 (CVTDQ2PSrr VR128:$src)>;
2103 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2104 (CVTDQ2PSrm addr:$src)>;
2106 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2107 (CVTTPS2DQrr VR128:$src)>;
2108 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2109 (CVTTPS2DQrm addr:$src)>;
2112 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2113 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2115 (int_x86_sse2_cvttpd2dq VR128:$src))],
2116 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2118 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2119 // register, but the same isn't true when using memory operands instead.
2120 // Provide other assembly rr and rm forms to address this explicitly.
2123 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2124 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2125 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2126 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2127 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2128 (loadv2f64 addr:$src)))],
2129 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2132 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2133 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2135 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2136 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2137 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2138 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2140 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2141 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2142 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2143 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2145 let Predicates = [HasAVX, NoVLX] in {
2146 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2147 (VCVTTPD2DQYrr VR256:$src)>;
2148 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2149 (VCVTTPD2DQYrm addr:$src)>;
2150 } // Predicates = [HasAVX]
2152 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2153 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2154 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2155 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2156 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2157 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2158 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2159 (memopv2f64 addr:$src)))],
2161 Sched<[WriteCvtF2ILd]>;
2163 // Convert packed single to packed double
2164 let Predicates = [HasAVX] in {
2165 // SSE2 instructions without OpSize prefix
2166 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2167 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2168 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2169 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2170 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2171 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2172 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2173 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2174 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2175 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2177 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2178 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2179 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2180 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2182 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2183 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2186 let Predicates = [UseSSE2] in {
2187 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2188 "cvtps2pd\t{$src, $dst|$dst, $src}",
2189 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2190 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2191 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2192 "cvtps2pd\t{$src, $dst|$dst, $src}",
2193 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2194 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2197 // Convert Packed DW Integers to Packed Double FP
2198 let Predicates = [HasAVX] in {
2199 let hasSideEffects = 0, mayLoad = 1 in
2200 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2201 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2202 []>, VEX, Sched<[WriteCvtI2FLd]>;
2203 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2204 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2206 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2207 Sched<[WriteCvtI2F]>;
2208 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2209 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2211 (int_x86_avx_cvtdq2_pd_256
2212 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2213 Sched<[WriteCvtI2FLd]>;
2214 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2215 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2217 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2218 Sched<[WriteCvtI2F]>;
2221 let hasSideEffects = 0, mayLoad = 1 in
2222 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2223 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2224 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2225 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2226 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2227 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2228 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2230 // AVX register conversion intrinsics
2231 let Predicates = [HasAVX] in {
2232 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2233 (VCVTDQ2PDrr VR128:$src)>;
2234 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2235 (VCVTDQ2PDrm addr:$src)>;
2237 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2238 (VCVTDQ2PDYrr VR128:$src)>;
2239 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2240 (VCVTDQ2PDYrm addr:$src)>;
2241 } // Predicates = [HasAVX]
2243 // SSE2 register conversion intrinsics
2244 let Predicates = [HasSSE2] in {
2245 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2246 (CVTDQ2PDrr VR128:$src)>;
2247 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2248 (CVTDQ2PDrm addr:$src)>;
2249 } // Predicates = [HasSSE2]
2251 // Convert packed double to packed single
2252 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2253 // register, but the same isn't true when using memory operands instead.
2254 // Provide other assembly rr and rm forms to address this explicitly.
2255 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2256 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2257 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2258 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2261 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2262 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2263 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2264 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2266 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2267 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2270 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2271 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2273 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2274 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2275 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2276 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2278 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2279 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2280 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2281 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2283 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2284 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2285 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2286 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2287 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2288 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2290 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2291 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2294 // AVX 256-bit register conversion intrinsics
2295 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2296 // whenever possible to avoid declaring two versions of each one.
2297 let Predicates = [HasAVX] in {
2298 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2299 (VCVTDQ2PSYrr VR256:$src)>;
2300 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2301 (VCVTDQ2PSYrm addr:$src)>;
2304 let Predicates = [HasAVX, NoVLX] in {
2305 // Match fround and fextend for 128/256-bit conversions
2306 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2307 (VCVTPD2PSrr VR128:$src)>;
2308 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2309 (VCVTPD2PSXrm addr:$src)>;
2310 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2311 (VCVTPD2PSYrr VR256:$src)>;
2312 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2313 (VCVTPD2PSYrm addr:$src)>;
2315 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2316 (VCVTPS2PDrr VR128:$src)>;
2317 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2318 (VCVTPS2PDYrr VR128:$src)>;
2319 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2320 (VCVTPS2PDYrm addr:$src)>;
2323 let Predicates = [UseSSE2] in {
2324 // Match fround and fextend for 128 conversions
2325 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2326 (CVTPD2PSrr VR128:$src)>;
2327 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2328 (CVTPD2PSrm addr:$src)>;
2330 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2331 (CVTPS2PDrr VR128:$src)>;
2334 //===----------------------------------------------------------------------===//
2335 // SSE 1 & 2 - Compare Instructions
2336 //===----------------------------------------------------------------------===//
2338 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2339 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2340 Operand CC, SDNode OpNode, ValueType VT,
2341 PatFrag ld_frag, string asm, string asm_alt,
2342 OpndItins itins, ImmLeaf immLeaf> {
2343 def rr : SIi8<0xC2, MRMSrcReg,
2344 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2345 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2346 itins.rr>, Sched<[itins.Sched]>;
2347 def rm : SIi8<0xC2, MRMSrcMem,
2348 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2349 [(set RC:$dst, (OpNode (VT RC:$src1),
2350 (ld_frag addr:$src2), immLeaf:$cc))],
2352 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2354 // Accept explicit immediate argument form instead of comparison code.
2355 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2356 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2357 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2358 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2360 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2361 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2362 IIC_SSE_ALU_F32S_RM>,
2363 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2367 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2368 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2369 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2370 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2371 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2372 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2373 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2374 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2375 XD, VEX_4V, VEX_LIG;
2377 let Constraints = "$src1 = $dst" in {
2378 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2379 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2380 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2382 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2383 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2384 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2385 SSE_ALU_F64S, i8immZExt3>, XD;
2388 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2389 Intrinsic Int, string asm, OpndItins itins,
2391 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2392 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2393 [(set VR128:$dst, (Int VR128:$src1,
2394 VR128:$src, immLeaf:$cc))],
2396 Sched<[itins.Sched]>;
2397 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2398 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2399 [(set VR128:$dst, (Int VR128:$src1,
2400 (load addr:$src), immLeaf:$cc))],
2402 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2405 let isCodeGenOnly = 1 in {
2406 // Aliases to match intrinsics which expect XMM operand(s).
2407 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2408 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2409 SSE_ALU_F32S, i8immZExt5>,
2411 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2412 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2413 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2415 let Constraints = "$src1 = $dst" in {
2416 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2417 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2418 SSE_ALU_F32S, i8immZExt3>, XS;
2419 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2420 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2421 SSE_ALU_F64S, i8immZExt3>,
2427 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2428 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2429 ValueType vt, X86MemOperand x86memop,
2430 PatFrag ld_frag, string OpcodeStr> {
2431 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2432 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2433 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2436 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2437 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2438 [(set EFLAGS, (OpNode (vt RC:$src1),
2439 (ld_frag addr:$src2)))],
2441 Sched<[WriteFAddLd, ReadAfterLd]>;
2444 let Defs = [EFLAGS] in {
2445 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2446 "ucomiss">, PS, VEX, VEX_LIG;
2447 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2448 "ucomisd">, PD, VEX, VEX_LIG;
2449 let Pattern = []<dag> in {
2450 defm VCOMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
2451 "comiss">, PS, VEX, VEX_LIG;
2452 defm VCOMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
2453 "comisd">, PD, VEX, VEX_LIG;
2456 let isCodeGenOnly = 1 in {
2457 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2458 load, "ucomiss">, PS, VEX;
2459 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2460 load, "ucomisd">, PD, VEX;
2462 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2463 load, "comiss">, PS, VEX;
2464 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2465 load, "comisd">, PD, VEX;
2467 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2469 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2472 let Pattern = []<dag> in {
2473 defm COMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
2475 defm COMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
2479 let isCodeGenOnly = 1 in {
2480 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2481 load, "ucomiss">, PS;
2482 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2483 load, "ucomisd">, PD;
2485 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2487 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2490 } // Defs = [EFLAGS]
2492 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2493 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2494 Operand CC, Intrinsic Int, string asm,
2495 string asm_alt, Domain d, ImmLeaf immLeaf,
2496 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2497 let isCommutable = 1 in
2498 def rri : PIi8<0xC2, MRMSrcReg,
2499 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2500 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2503 def rmi : PIi8<0xC2, MRMSrcMem,
2504 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2505 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2507 Sched<[WriteFAddLd, ReadAfterLd]>;
2509 // Accept explicit immediate argument form instead of comparison code.
2510 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2511 def rri_alt : PIi8<0xC2, MRMSrcReg,
2512 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2513 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2515 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2516 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2517 asm_alt, [], itins.rm, d>,
2518 Sched<[WriteFAddLd, ReadAfterLd]>;
2522 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2523 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2524 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2525 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2526 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2527 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2528 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2529 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2530 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2531 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2532 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2533 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2534 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2535 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2536 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2537 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2538 let Constraints = "$src1 = $dst" in {
2539 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2540 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2541 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2542 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2543 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2544 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2545 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2546 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2549 let Predicates = [HasAVX] in {
2550 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2551 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2552 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2553 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2554 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2555 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2556 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2557 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2559 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2560 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2561 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2562 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2563 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2564 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2565 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2566 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2569 let Predicates = [UseSSE1] in {
2570 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2571 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2572 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2573 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2576 let Predicates = [UseSSE2] in {
2577 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2578 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2579 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2580 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2583 //===----------------------------------------------------------------------===//
2584 // SSE 1 & 2 - Shuffle Instructions
2585 //===----------------------------------------------------------------------===//
2587 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2588 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2589 ValueType vt, string asm, PatFrag mem_frag,
2591 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2592 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2593 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2594 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2595 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2596 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2597 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2598 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2599 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2600 Sched<[WriteFShuffle]>;
2603 let Predicates = [HasAVX, NoVLX] in {
2604 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2605 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2606 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2607 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2608 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2609 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2610 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2611 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2612 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2613 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2614 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2615 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2617 let Constraints = "$src1 = $dst" in {
2618 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2619 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2620 memopv4f32, SSEPackedSingle>, PS;
2621 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2622 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2623 memopv2f64, SSEPackedDouble>, PD;
2626 let Predicates = [HasAVX, NoVLX] in {
2627 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2628 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2629 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2630 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2631 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2633 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2634 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2635 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2636 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2637 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2640 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2641 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2642 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2643 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2644 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2646 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2647 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2648 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2649 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2650 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2653 let Predicates = [UseSSE1] in {
2654 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2655 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2656 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2657 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2658 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2661 let Predicates = [UseSSE2] in {
2662 // Generic SHUFPD patterns
2663 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2664 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2665 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2666 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2667 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2670 //===----------------------------------------------------------------------===//
2671 // SSE 1 & 2 - Unpack FP Instructions
2672 //===----------------------------------------------------------------------===//
2674 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2675 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2676 PatFrag mem_frag, RegisterClass RC,
2677 X86MemOperand x86memop, string asm,
2679 def rr : PI<opc, MRMSrcReg,
2680 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2682 (vt (OpNode RC:$src1, RC:$src2)))],
2683 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2684 def rm : PI<opc, MRMSrcMem,
2685 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2687 (vt (OpNode RC:$src1,
2688 (mem_frag addr:$src2))))],
2690 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2693 let Predicates = [HasAVX, NoVLX] in {
2694 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2695 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2696 SSEPackedSingle>, PS, VEX_4V;
2697 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2698 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2699 SSEPackedDouble>, PD, VEX_4V;
2700 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2701 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2702 SSEPackedSingle>, PS, VEX_4V;
2703 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2704 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2705 SSEPackedDouble>, PD, VEX_4V;
2707 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2708 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2709 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2710 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2711 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2712 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2713 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2714 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2715 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2716 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2717 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2718 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2719 }// Predicates = [HasAVX, NoVLX]
2720 let Constraints = "$src1 = $dst" in {
2721 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2722 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2723 SSEPackedSingle>, PS;
2724 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2725 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2726 SSEPackedDouble>, PD;
2727 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2728 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2729 SSEPackedSingle>, PS;
2730 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2731 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2732 SSEPackedDouble>, PD;
2733 } // Constraints = "$src1 = $dst"
2735 let Predicates = [HasAVX1Only] in {
2736 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2737 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2738 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2739 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2740 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2741 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2742 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2743 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2745 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2746 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2747 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2748 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2749 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2750 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2751 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2752 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2755 //===----------------------------------------------------------------------===//
2756 // SSE 1 & 2 - Extract Floating-Point Sign mask
2757 //===----------------------------------------------------------------------===//
2759 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2760 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2762 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2763 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2764 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2765 Sched<[WriteVecLogic]>;
2768 let Predicates = [HasAVX] in {
2769 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2770 "movmskps", SSEPackedSingle>, PS, VEX;
2771 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2772 "movmskpd", SSEPackedDouble>, PD, VEX;
2773 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2774 "movmskps", SSEPackedSingle>, PS,
2776 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2777 "movmskpd", SSEPackedDouble>, PD,
2780 def : Pat<(i32 (X86fgetsign FR32:$src)),
2781 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2782 def : Pat<(i64 (X86fgetsign FR32:$src)),
2783 (SUBREG_TO_REG (i64 0),
2784 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2785 def : Pat<(i32 (X86fgetsign FR64:$src)),
2786 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2787 def : Pat<(i64 (X86fgetsign FR64:$src)),
2788 (SUBREG_TO_REG (i64 0),
2789 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2792 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2793 SSEPackedSingle>, PS;
2794 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2795 SSEPackedDouble>, PD;
2797 def : Pat<(i32 (X86fgetsign FR32:$src)),
2798 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2799 Requires<[UseSSE1]>;
2800 def : Pat<(i64 (X86fgetsign FR32:$src)),
2801 (SUBREG_TO_REG (i64 0),
2802 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2803 Requires<[UseSSE1]>;
2804 def : Pat<(i32 (X86fgetsign FR64:$src)),
2805 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2806 Requires<[UseSSE2]>;
2807 def : Pat<(i64 (X86fgetsign FR64:$src)),
2808 (SUBREG_TO_REG (i64 0),
2809 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2810 Requires<[UseSSE2]>;
2812 //===---------------------------------------------------------------------===//
2813 // SSE2 - Packed Integer Logical Instructions
2814 //===---------------------------------------------------------------------===//
2816 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2818 /// PDI_binop_rm - Simple SSE2 binary operator.
2819 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2820 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2821 X86MemOperand x86memop, OpndItins itins,
2822 bit IsCommutable, bit Is2Addr> {
2823 let isCommutable = IsCommutable in
2824 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2825 (ins RC:$src1, RC:$src2),
2827 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2828 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2829 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2830 Sched<[itins.Sched]>;
2831 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2832 (ins RC:$src1, x86memop:$src2),
2834 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2835 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2836 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2837 (bitconvert (memop_frag addr:$src2)))))],
2839 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2841 } // ExeDomain = SSEPackedInt
2843 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2844 ValueType OpVT128, ValueType OpVT256,
2845 OpndItins itins, bit IsCommutable = 0, Predicate prd> {
2846 let Predicates = [HasAVX, prd] in
2847 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2848 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2850 let Constraints = "$src1 = $dst" in
2851 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2852 memopv2i64, i128mem, itins, IsCommutable, 1>;
2854 let Predicates = [HasAVX2, prd] in
2855 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2856 OpVT256, VR256, loadv4i64, i256mem, itins,
2857 IsCommutable, 0>, VEX_4V, VEX_L;
2860 // These are ordered here for pattern ordering requirements with the fp versions
2862 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2863 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2864 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2865 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2866 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2867 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2868 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2869 SSE_VEC_BIT_ITINS_P, 0, NoVLX>;
2871 //===----------------------------------------------------------------------===//
2872 // SSE 1 & 2 - Logical Instructions
2873 //===----------------------------------------------------------------------===//
2875 // Multiclass for scalars using the X86 logical operation aliases for FP.
2876 multiclass sse12_fp_packed_scalar_logical_alias<
2877 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2878 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2879 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2882 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2883 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2886 let Constraints = "$src1 = $dst" in {
2887 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2888 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2890 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2891 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2895 let isCodeGenOnly = 1 in {
2896 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2898 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2900 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2903 let isCommutable = 0 in
2904 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2908 // Multiclass for vectors using the X86 logical operation aliases for FP.
2909 multiclass sse12_fp_packed_vector_logical_alias<
2910 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2911 let Predicates = [HasAVX, NoVLX_Or_NoDQI] in {
2912 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2913 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2916 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2917 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2920 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2921 VR256, v8f32, f256mem, loadv8f32, SSEPackedSingle, itins, 0>,
2924 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2925 VR256, v4f64, f256mem, loadv4f64, SSEPackedDouble, itins, 0>,
2929 let Constraints = "$src1 = $dst" in {
2930 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2931 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2934 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2935 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2940 let isCodeGenOnly = 1 in {
2941 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2943 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2945 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2948 let isCommutable = 0 in
2949 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2953 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2955 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2957 let Predicates = [HasAVX, NoVLX] in {
2958 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2959 !strconcat(OpcodeStr, "ps"), f256mem,
2960 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2961 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2962 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2964 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2965 !strconcat(OpcodeStr, "pd"), f256mem,
2966 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2967 (bc_v4i64 (v4f64 VR256:$src2))))],
2968 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2969 (loadv4i64 addr:$src2)))], 0>,
2972 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2973 // are all promoted to v2i64, and the patterns are covered by the int
2974 // version. This is needed in SSE only, because v2i64 isn't supported on
2975 // SSE1, but only on SSE2.
2976 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2977 !strconcat(OpcodeStr, "ps"), f128mem, [],
2978 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2979 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2981 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2982 !strconcat(OpcodeStr, "pd"), f128mem,
2983 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2984 (bc_v2i64 (v2f64 VR128:$src2))))],
2985 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2986 (loadv2i64 addr:$src2)))], 0>,
2990 let Constraints = "$src1 = $dst" in {
2991 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2992 !strconcat(OpcodeStr, "ps"), f128mem,
2993 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2994 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2995 (memopv2i64 addr:$src2)))]>, PS;
2997 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2998 !strconcat(OpcodeStr, "pd"), f128mem,
2999 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
3000 (bc_v2i64 (v2f64 VR128:$src2))))],
3001 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
3002 (memopv2i64 addr:$src2)))]>, PD;
3006 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
3007 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
3008 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
3009 let isCommutable = 0 in
3010 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
3012 // AVX1 requires type coercions in order to fold loads directly into logical
3014 let Predicates = [HasAVX1Only] in {
3015 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3016 (VANDPSYrm VR256:$src1, addr:$src2)>;
3017 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3018 (VORPSYrm VR256:$src1, addr:$src2)>;
3019 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3020 (VXORPSYrm VR256:$src1, addr:$src2)>;
3021 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3022 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3025 //===----------------------------------------------------------------------===//
3026 // SSE 1 & 2 - Arithmetic Instructions
3027 //===----------------------------------------------------------------------===//
3029 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3032 /// In addition, we also have a special variant of the scalar form here to
3033 /// represent the associated intrinsic operation. This form is unlike the
3034 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3035 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3037 /// These three forms can each be reg+reg or reg+mem.
3040 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3042 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3043 SDNode OpNode, SizeItins itins> {
3044 let Predicates = [HasAVX, NoVLX] in {
3045 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3046 VR128, v4f32, f128mem, loadv4f32,
3047 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3048 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3049 VR128, v2f64, f128mem, loadv2f64,
3050 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3052 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3053 OpNode, VR256, v8f32, f256mem, loadv8f32,
3054 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3055 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3056 OpNode, VR256, v4f64, f256mem, loadv4f64,
3057 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3060 let Constraints = "$src1 = $dst" in {
3061 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3062 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3064 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3065 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3070 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3072 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3073 OpNode, FR32, f32mem, SSEPackedSingle, itins.s, 0>,
3074 XS, VEX_4V, VEX_LIG;
3075 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3076 OpNode, FR64, f64mem, SSEPackedDouble, itins.d, 0>,
3077 XD, VEX_4V, VEX_LIG;
3079 let Constraints = "$src1 = $dst" in {
3080 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3081 OpNode, FR32, f32mem, SSEPackedSingle,
3083 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3084 OpNode, FR64, f64mem, SSEPackedDouble,
3089 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3091 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3092 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3093 SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3094 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3095 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3096 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3098 let Constraints = "$src1 = $dst" in {
3099 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3100 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3101 SSEPackedSingle, itins.s>, XS;
3102 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3103 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3104 SSEPackedDouble, itins.d>, XD;
3108 // Binary Arithmetic instructions
3109 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3110 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3111 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3112 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3113 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3114 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3115 let isCommutable = 0 in {
3116 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3117 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3118 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3119 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3120 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3121 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3122 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3123 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3124 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3125 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3126 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3127 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3130 let isCodeGenOnly = 1 in {
3131 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3132 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3133 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3134 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3137 // Patterns used to select SSE scalar fp arithmetic instructions from
3140 // (1) a scalar fp operation followed by a blend
3142 // The effect is that the backend no longer emits unnecessary vector
3143 // insert instructions immediately after SSE scalar fp instructions
3144 // like addss or mulss.
3146 // For example, given the following code:
3147 // __m128 foo(__m128 A, __m128 B) {
3152 // Previously we generated:
3153 // addss %xmm0, %xmm1
3154 // movss %xmm1, %xmm0
3157 // addss %xmm1, %xmm0
3159 // (2) a vector packed single/double fp operation followed by a vector insert
3161 // The effect is that the backend converts the packed fp instruction
3162 // followed by a vector insert into a single SSE scalar fp instruction.
3164 // For example, given the following code:
3165 // __m128 foo(__m128 A, __m128 B) {
3166 // __m128 C = A + B;
3167 // return (__m128) {c[0], a[1], a[2], a[3]};
3170 // Previously we generated:
3171 // addps %xmm0, %xmm1
3172 // movss %xmm1, %xmm0
3175 // addss %xmm1, %xmm0
3177 // TODO: Some canonicalization in lowering would simplify the number of
3178 // patterns we have to try to match.
3179 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3180 let Predicates = [UseSSE1] in {
3181 // extracted scalar math op with insert via movss
3182 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3183 (Op (f32 (extractelt (v4f32 VR128:$dst), (iPTR 0))),
3185 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3186 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3188 // vector math op with insert via movss
3189 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3190 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3191 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3194 // With SSE 4.1, blendi is preferred to movsd, so match that too.
3195 let Predicates = [UseSSE41] in {
3196 // extracted scalar math op with insert via blend
3197 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3198 (Op (f32 (extractelt (v4f32 VR128:$dst), (iPTR 0))),
3199 FR32:$src))), (i8 1))),
3200 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3201 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3203 // vector math op with insert via blend
3204 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3205 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3206 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3210 // Repeat everything for AVX, except for the movss + scalar combo...
3211 // because that one shouldn't occur with AVX codegen?
3212 let Predicates = [HasAVX] in {
3213 // extracted scalar math op with insert via blend
3214 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3215 (Op (f32 (extractelt (v4f32 VR128:$dst), (iPTR 0))),
3216 FR32:$src))), (i8 1))),
3217 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3218 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3220 // vector math op with insert via movss
3221 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3222 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3223 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3225 // vector math op with insert via blend
3226 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3227 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3228 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3232 defm : scalar_math_f32_patterns<fadd, "ADD">;
3233 defm : scalar_math_f32_patterns<fsub, "SUB">;
3234 defm : scalar_math_f32_patterns<fmul, "MUL">;
3235 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3237 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3238 let Predicates = [UseSSE2] in {
3239 // extracted scalar math op with insert via movsd
3240 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3241 (Op (f64 (extractelt (v2f64 VR128:$dst), (iPTR 0))),
3243 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3244 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3246 // vector math op with insert via movsd
3247 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3248 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3249 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3252 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3253 let Predicates = [UseSSE41] in {
3254 // extracted scalar math op with insert via blend
3255 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3256 (Op (f64 (extractelt (v2f64 VR128:$dst), (iPTR 0))),
3257 FR64:$src))), (i8 1))),
3258 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3259 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3261 // vector math op with insert via blend
3262 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3263 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3264 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3267 // Repeat everything for AVX.
3268 let Predicates = [HasAVX] in {
3269 // extracted scalar math op with insert via movsd
3270 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3271 (Op (f64 (extractelt (v2f64 VR128:$dst), (iPTR 0))),
3273 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3274 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3276 // extracted scalar math op with insert via blend
3277 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3278 (Op (f64 (extractelt (v2f64 VR128:$dst), (iPTR 0))),
3279 FR64:$src))), (i8 1))),
3280 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3281 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3283 // vector math op with insert via movsd
3284 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3285 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3286 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3288 // vector math op with insert via blend
3289 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3290 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3291 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3295 defm : scalar_math_f64_patterns<fadd, "ADD">;
3296 defm : scalar_math_f64_patterns<fsub, "SUB">;
3297 defm : scalar_math_f64_patterns<fmul, "MUL">;
3298 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3302 /// In addition, we also have a special variant of the scalar form here to
3303 /// represent the associated intrinsic operation. This form is unlike the
3304 /// plain scalar form, in that it takes an entire vector (instead of a
3305 /// scalar) and leaves the top elements undefined.
3307 /// And, we have a special variant form for a full-vector intrinsic form.
3309 let Sched = WriteFSqrt in {
3310 def SSE_SQRTPS : OpndItins<
3311 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3314 def SSE_SQRTSS : OpndItins<
3315 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3318 def SSE_SQRTPD : OpndItins<
3319 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3322 def SSE_SQRTSD : OpndItins<
3323 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3327 let Sched = WriteFRsqrt in {
3328 def SSE_RSQRTPS : OpndItins<
3329 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3332 def SSE_RSQRTSS : OpndItins<
3333 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3337 let Sched = WriteFRcp in {
3338 def SSE_RCPP : OpndItins<
3339 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3342 def SSE_RCPS : OpndItins<
3343 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3347 /// sse_fp_unop_s - SSE1 unops in scalar form
3348 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3349 /// the HW instructions are 2 operand / destructive.
3350 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3351 ValueType vt, ValueType ScalarVT,
3352 X86MemOperand x86memop, Operand vec_memop,
3353 ComplexPattern mem_cpat, Intrinsic Intr,
3354 SDNode OpNode, Domain d, OpndItins itins,
3355 Predicate target, string Suffix> {
3356 let hasSideEffects = 0 in {
3357 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3358 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3359 [(set RC:$dst, (OpNode RC:$src1))], itins.rr, d>, Sched<[itins.Sched]>,
3362 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3363 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3364 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm, d>,
3365 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3366 Requires<[target, OptForSize]>;
3368 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3369 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3370 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3371 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3373 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3374 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3375 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3379 let Predicates = [target] in {
3380 def : Pat<(vt (OpNode mem_cpat:$src)),
3381 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3382 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3383 // These are unary operations, but they are modeled as having 2 source operands
3384 // because the high elements of the destination are unchanged in SSE.
3385 def : Pat<(Intr VR128:$src),
3386 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3387 def : Pat<(Intr (load addr:$src)),
3388 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3389 addr:$src), VR128))>;
3390 def : Pat<(Intr mem_cpat:$src),
3391 (!cast<Instruction>(NAME#Suffix##m_Int)
3392 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3396 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3397 ValueType vt, ValueType ScalarVT,
3398 X86MemOperand x86memop, Operand vec_memop,
3399 ComplexPattern mem_cpat,
3400 Intrinsic Intr, SDNode OpNode, Domain d,
3401 OpndItins itins, string Suffix> {
3402 let hasSideEffects = 0 in {
3403 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3404 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3405 [], itins.rr, d>, Sched<[itins.Sched]>;
3407 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3408 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3409 [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3410 let isCodeGenOnly = 1 in {
3411 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3412 (ins VR128:$src1, VR128:$src2),
3413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3414 []>, Sched<[itins.Sched.Folded]>;
3416 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3417 (ins VR128:$src1, vec_memop:$src2),
3418 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3419 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3423 let Predicates = [UseAVX] in {
3424 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3425 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3427 def : Pat<(vt (OpNode mem_cpat:$src)),
3428 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3432 let Predicates = [HasAVX] in {
3433 def : Pat<(Intr VR128:$src),
3434 (!cast<Instruction>("V"#NAME#Suffix##r_Int) (vt (IMPLICIT_DEF)),
3437 def : Pat<(Intr mem_cpat:$src),
3438 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3439 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3441 let Predicates = [UseAVX, OptForSize] in
3442 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3443 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3447 /// sse1_fp_unop_p - SSE1 unops in packed form.
3448 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3449 OpndItins itins, list<Predicate> prds> {
3450 let Predicates = prds in {
3451 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3452 !strconcat("v", OpcodeStr,
3453 "ps\t{$src, $dst|$dst, $src}"),
3454 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3455 itins.rr>, VEX, Sched<[itins.Sched]>;
3456 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3457 !strconcat("v", OpcodeStr,
3458 "ps\t{$src, $dst|$dst, $src}"),
3459 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3460 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3461 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3462 !strconcat("v", OpcodeStr,
3463 "ps\t{$src, $dst|$dst, $src}"),
3464 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3465 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3466 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3467 !strconcat("v", OpcodeStr,
3468 "ps\t{$src, $dst|$dst, $src}"),
3469 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3470 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3473 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3474 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3475 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3476 Sched<[itins.Sched]>;
3477 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3478 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3479 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3480 Sched<[itins.Sched.Folded]>;
3483 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3484 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3485 SDNode OpNode, OpndItins itins> {
3486 let Predicates = [HasAVX] in {
3487 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3488 !strconcat("v", OpcodeStr,
3489 "pd\t{$src, $dst|$dst, $src}"),
3490 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3491 itins.rr>, VEX, Sched<[itins.Sched]>;
3492 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3493 !strconcat("v", OpcodeStr,
3494 "pd\t{$src, $dst|$dst, $src}"),
3495 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3496 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3497 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3498 !strconcat("v", OpcodeStr,
3499 "pd\t{$src, $dst|$dst, $src}"),
3500 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3501 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3502 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3503 !strconcat("v", OpcodeStr,
3504 "pd\t{$src, $dst|$dst, $src}"),
3505 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3506 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3509 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3510 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3511 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3512 Sched<[itins.Sched]>;
3513 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3514 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3515 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3516 Sched<[itins.Sched.Folded]>;
3519 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3521 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3522 ssmem, sse_load_f32,
3523 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3524 SSEPackedSingle, itins, UseSSE1, "SS">, XS;
3525 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3526 f32mem, ssmem, sse_load_f32,
3527 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3528 SSEPackedSingle, itins, "SS">, XS, VEX_4V, VEX_LIG;
3531 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3533 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3534 sdmem, sse_load_f64,
3535 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3536 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3537 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3538 f64mem, sdmem, sse_load_f64,
3539 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3540 OpNode, SSEPackedDouble, itins, "SD">,
3541 XD, VEX_4V, VEX_LIG;
3545 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3546 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS, [HasAVX]>,
3547 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3548 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3550 // Reciprocal approximations. Note that these typically require refinement
3551 // in order to obtain suitable precision.
3552 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3553 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS, [HasAVX, NoVLX] >;
3554 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3555 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP, [HasAVX, NoVLX]>;
3557 // There is no f64 version of the reciprocal approximation instructions.
3559 // TODO: We should add *scalar* op patterns for these just like we have for
3560 // the binops above. If the binop and unop patterns could all be unified
3561 // that would be even better.
3563 multiclass scalar_unary_math_patterns<Intrinsic Intr, string OpcPrefix,
3564 SDNode Move, ValueType VT,
3565 Predicate BasePredicate> {
3566 let Predicates = [BasePredicate] in {
3567 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3568 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3571 // With SSE 4.1, blendi is preferred to movs*, so match that too.
3572 let Predicates = [UseSSE41] in {
3573 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3574 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3577 // Repeat for AVX versions of the instructions.
3578 let Predicates = [HasAVX] in {
3579 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3580 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3582 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3583 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3587 defm : scalar_unary_math_patterns<int_x86_sse_rcp_ss, "RCPSS", X86Movss,
3589 defm : scalar_unary_math_patterns<int_x86_sse_rsqrt_ss, "RSQRTSS", X86Movss,
3591 defm : scalar_unary_math_patterns<int_x86_sse_sqrt_ss, "SQRTSS", X86Movss,
3593 defm : scalar_unary_math_patterns<int_x86_sse2_sqrt_sd, "SQRTSD", X86Movsd,
3597 //===----------------------------------------------------------------------===//
3598 // SSE 1 & 2 - Non-temporal stores
3599 //===----------------------------------------------------------------------===//
3601 let AddedComplexity = 400 in { // Prefer non-temporal versions
3602 let SchedRW = [WriteStore] in {
3603 let Predicates = [HasAVX, NoVLX] in {
3604 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3605 (ins f128mem:$dst, VR128:$src),
3606 "movntps\t{$src, $dst|$dst, $src}",
3607 [(alignednontemporalstore (v4f32 VR128:$src),
3609 IIC_SSE_MOVNT>, VEX;
3610 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3611 (ins f128mem:$dst, VR128:$src),
3612 "movntpd\t{$src, $dst|$dst, $src}",
3613 [(alignednontemporalstore (v2f64 VR128:$src),
3615 IIC_SSE_MOVNT>, VEX;
3617 let ExeDomain = SSEPackedInt in
3618 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3619 (ins f128mem:$dst, VR128:$src),
3620 "movntdq\t{$src, $dst|$dst, $src}",
3621 [(alignednontemporalstore (v2i64 VR128:$src),
3623 IIC_SSE_MOVNT>, VEX;
3625 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3626 (ins f256mem:$dst, VR256:$src),
3627 "movntps\t{$src, $dst|$dst, $src}",
3628 [(alignednontemporalstore (v8f32 VR256:$src),
3630 IIC_SSE_MOVNT>, VEX, VEX_L;
3631 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3632 (ins f256mem:$dst, VR256:$src),
3633 "movntpd\t{$src, $dst|$dst, $src}",
3634 [(alignednontemporalstore (v4f64 VR256:$src),
3636 IIC_SSE_MOVNT>, VEX, VEX_L;
3637 let ExeDomain = SSEPackedInt in
3638 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3639 (ins f256mem:$dst, VR256:$src),
3640 "movntdq\t{$src, $dst|$dst, $src}",
3641 [(alignednontemporalstore (v4i64 VR256:$src),
3643 IIC_SSE_MOVNT>, VEX, VEX_L;
3646 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3647 "movntps\t{$src, $dst|$dst, $src}",
3648 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3650 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3651 "movntpd\t{$src, $dst|$dst, $src}",
3652 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3655 let ExeDomain = SSEPackedInt in
3656 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3657 "movntdq\t{$src, $dst|$dst, $src}",
3658 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3661 // There is no AVX form for instructions below this point
3662 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3663 "movnti{l}\t{$src, $dst|$dst, $src}",
3664 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3666 PS, Requires<[HasSSE2]>;
3667 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3668 "movnti{q}\t{$src, $dst|$dst, $src}",
3669 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3671 PS, Requires<[HasSSE2]>;
3672 } // SchedRW = [WriteStore]
3674 let Predicates = [HasAVX2, NoVLX] in {
3675 def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst),
3676 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3677 def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst),
3678 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3679 def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst),
3680 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3683 let Predicates = [HasAVX, NoVLX] in {
3684 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3685 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3686 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3687 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3688 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3689 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3692 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3693 (MOVNTDQmr addr:$dst, VR128:$src)>;
3694 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3695 (MOVNTDQmr addr:$dst, VR128:$src)>;
3696 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3697 (MOVNTDQmr addr:$dst, VR128:$src)>;
3699 } // AddedComplexity
3701 //===----------------------------------------------------------------------===//
3702 // SSE 1 & 2 - Prefetch and memory fence
3703 //===----------------------------------------------------------------------===//
3705 // Prefetch intrinsic.
3706 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3707 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3708 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3709 IIC_SSE_PREFETCH>, TB;
3710 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3711 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3712 IIC_SSE_PREFETCH>, TB;
3713 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3714 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3715 IIC_SSE_PREFETCH>, TB;
3716 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3717 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3718 IIC_SSE_PREFETCH>, TB;
3721 // FIXME: How should flush instruction be modeled?
3722 let SchedRW = [WriteLoad] in {
3724 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3725 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3726 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3729 let SchedRW = [WriteNop] in {
3730 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3731 // was introduced with SSE2, it's backward compatible.
3732 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3733 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3734 OBXS, Requires<[HasSSE2]>;
3737 let SchedRW = [WriteFence] in {
3738 // Load, store, and memory fence
3739 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3740 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3741 PS, Requires<[HasSSE1]>;
3742 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3743 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3744 TB, Requires<[HasSSE2]>;
3745 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3746 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3747 TB, Requires<[HasSSE2]>;
3750 def : Pat<(X86SFence), (SFENCE)>;
3751 def : Pat<(X86LFence), (LFENCE)>;
3752 def : Pat<(X86MFence), (MFENCE)>;
3754 //===----------------------------------------------------------------------===//
3755 // SSE 1 & 2 - Load/Store XCSR register
3756 //===----------------------------------------------------------------------===//
3758 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3759 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3760 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3761 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3762 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3763 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3765 let Predicates = [UseSSE1] in {
3766 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3767 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3768 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3769 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3770 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3771 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3774 //===---------------------------------------------------------------------===//
3775 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3776 //===---------------------------------------------------------------------===//
3778 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3780 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3781 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3782 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3784 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3785 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3787 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3788 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3790 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3791 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3796 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3797 SchedRW = [WriteMove] in {
3798 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3799 "movdqa\t{$src, $dst|$dst, $src}", [],
3802 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3803 "movdqa\t{$src, $dst|$dst, $src}", [],
3804 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3805 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3806 "movdqu\t{$src, $dst|$dst, $src}", [],
3809 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3810 "movdqu\t{$src, $dst|$dst, $src}", [],
3811 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3814 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3815 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3816 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3817 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3819 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3820 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3822 let Predicates = [HasAVX] in {
3823 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3824 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3826 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3827 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3832 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3833 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3834 (ins i128mem:$dst, VR128:$src),
3835 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3837 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3838 (ins i256mem:$dst, VR256:$src),
3839 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3841 let Predicates = [HasAVX] in {
3842 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3843 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3845 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3846 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3851 let SchedRW = [WriteMove] in {
3852 let hasSideEffects = 0 in
3853 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3854 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3856 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3857 "movdqu\t{$src, $dst|$dst, $src}",
3858 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3861 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3862 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3863 "movdqa\t{$src, $dst|$dst, $src}", [],
3866 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3867 "movdqu\t{$src, $dst|$dst, $src}",
3868 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3872 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3873 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3874 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3875 "movdqa\t{$src, $dst|$dst, $src}",
3876 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3878 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3879 "movdqu\t{$src, $dst|$dst, $src}",
3880 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3882 XS, Requires<[UseSSE2]>;
3885 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3886 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3887 "movdqa\t{$src, $dst|$dst, $src}",
3888 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3890 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3891 "movdqu\t{$src, $dst|$dst, $src}",
3892 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3894 XS, Requires<[UseSSE2]>;
3897 } // ExeDomain = SSEPackedInt
3899 let Predicates = [HasAVX] in {
3900 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3901 (VMOVDQUmr addr:$dst, VR128:$src)>;
3902 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3903 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3905 let Predicates = [UseSSE2] in
3906 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3907 (MOVDQUmr addr:$dst, VR128:$src)>;
3909 //===---------------------------------------------------------------------===//
3910 // SSE2 - Packed Integer Arithmetic Instructions
3911 //===---------------------------------------------------------------------===//
3913 let Sched = WriteVecIMul in
3914 def SSE_PMADD : OpndItins<
3915 IIC_SSE_PMADD, IIC_SSE_PMADD
3918 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3920 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3921 RegisterClass RC, PatFrag memop_frag,
3922 X86MemOperand x86memop,
3924 bit IsCommutable = 0,
3926 let isCommutable = IsCommutable in
3927 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3928 (ins RC:$src1, RC:$src2),
3930 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3931 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3932 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3933 Sched<[itins.Sched]>;
3934 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3935 (ins RC:$src1, x86memop:$src2),
3937 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3938 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3939 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3940 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3943 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3944 Intrinsic IntId256, OpndItins itins,
3945 bit IsCommutable = 0> {
3946 let Predicates = [HasAVX] in
3947 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3948 VR128, loadv2i64, i128mem, itins,
3949 IsCommutable, 0>, VEX_4V;
3951 let Constraints = "$src1 = $dst" in
3952 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3953 i128mem, itins, IsCommutable, 1>;
3955 let Predicates = [HasAVX2] in
3956 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3957 VR256, loadv4i64, i256mem, itins,
3958 IsCommutable, 0>, VEX_4V, VEX_L;
3961 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3962 string OpcodeStr, SDNode OpNode,
3963 SDNode OpNode2, RegisterClass RC,
3964 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3965 PatFrag ld_frag, ShiftOpndItins itins,
3967 // src2 is always 128-bit
3968 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3969 (ins RC:$src1, VR128:$src2),
3971 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3972 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3973 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3974 itins.rr>, Sched<[WriteVecShift]>;
3975 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3976 (ins RC:$src1, i128mem:$src2),
3978 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3979 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3980 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3981 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3982 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3983 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3984 (ins RC:$src1, u8imm:$src2),
3986 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3987 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3988 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3989 Sched<[WriteVecShift]>;
3992 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3993 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3994 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3995 PatFrag memop_frag, X86MemOperand x86memop,
3997 bit IsCommutable = 0, bit Is2Addr = 1> {
3998 let isCommutable = IsCommutable in
3999 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4000 (ins RC:$src1, RC:$src2),
4002 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4003 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4004 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4005 Sched<[itins.Sched]>;
4006 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4007 (ins RC:$src1, x86memop:$src2),
4009 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4010 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4011 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4012 (bitconvert (memop_frag addr:$src2)))))]>,
4013 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4015 } // ExeDomain = SSEPackedInt
4017 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4018 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4019 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4020 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4021 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4022 SSE_INTALU_ITINS_P, 1, NoVLX>;
4023 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4024 SSE_INTALUQ_ITINS_P, 1, NoVLX>;
4025 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4026 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4027 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4028 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4029 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4030 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4031 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4032 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4033 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4034 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4035 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4036 SSE_INTALU_ITINS_P, 0, NoVLX>;
4037 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4038 SSE_INTALUQ_ITINS_P, 0, NoVLX>;
4039 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4040 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4041 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4042 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4043 defm PMINUB : PDI_binop_all<0xDA, "pminub", umin, v16i8, v32i8,
4044 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4045 defm PMINSW : PDI_binop_all<0xEA, "pminsw", smin, v8i16, v16i16,
4046 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4047 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", umax, v16i8, v32i8,
4048 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4049 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", smax, v8i16, v16i16,
4050 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4051 defm PAVGB : PDI_binop_all<0xE0, "pavgb", X86avg, v16i8, v32i8,
4052 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4053 defm PAVGW : PDI_binop_all<0xE3, "pavgw", X86avg, v8i16, v16i16,
4054 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4057 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4058 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4059 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4060 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4061 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4062 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4063 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4064 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4065 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4066 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4067 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4068 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4069 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4070 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4072 let Predicates = [HasAVX] in
4073 defm VPSADBW : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v2i64, v16i8, VR128,
4074 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4076 let Predicates = [HasAVX2] in
4077 defm VPSADBWY : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v4i64, v32i8, VR256,
4078 loadv4i64, i256mem, SSE_INTMUL_ITINS_P, 1, 0>,
4080 let Constraints = "$src1 = $dst" in
4081 defm PSADBW : PDI_binop_rm2<0xF6, "psadbw", X86psadbw, v2i64, v16i8, VR128,
4082 memopv2i64, i128mem, SSE_INTALU_ITINS_P, 1>;
4084 let Predicates = [HasAVX] in
4085 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4086 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4088 let Predicates = [HasAVX2] in
4089 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4090 VR256, loadv4i64, i256mem,
4091 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4092 let Constraints = "$src1 = $dst" in
4093 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4094 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4096 //===---------------------------------------------------------------------===//
4097 // SSE2 - Packed Integer Logical Instructions
4098 //===---------------------------------------------------------------------===//
4100 let Predicates = [HasAVX, NoVLX] in {
4101 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4102 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4103 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4104 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4105 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4106 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4107 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4108 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4109 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4111 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4112 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4113 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4114 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4115 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4116 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4117 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4118 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4119 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4121 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4122 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4123 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4124 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4125 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4126 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4127 } // Predicates = [HasAVX]
4129 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] ,
4130 Predicates = [HasAVX, NoVLX_Or_NoBWI]in {
4131 // 128-bit logical shifts.
4132 def VPSLLDQri : PDIi8<0x73, MRM7r,
4133 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4134 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4136 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4138 def VPSRLDQri : PDIi8<0x73, MRM3r,
4139 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4140 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4142 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4144 // PSRADQri doesn't exist in SSE[1-3].
4145 } // Predicates = [HasAVX, NoVLX_Or_NoBWI]
4147 let Predicates = [HasAVX2, NoVLX] in {
4148 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4149 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4150 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4151 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4152 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4153 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4154 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4155 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4156 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4158 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4159 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4160 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4161 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4162 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4163 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4164 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4165 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4166 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4168 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4169 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4170 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4171 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4172 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4173 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4174 }// Predicates = [HasAVX2]
4176 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 ,
4177 Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
4178 // 256-bit logical shifts.
4179 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4180 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4181 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4183 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4185 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4186 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4187 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4189 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4191 // PSRADQYri doesn't exist in SSE[1-3].
4192 } // Predicates = [HasAVX2, NoVLX_Or_NoBWI]
4194 let Constraints = "$src1 = $dst" in {
4195 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4196 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4197 SSE_INTSHIFT_ITINS_P>;
4198 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4199 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4200 SSE_INTSHIFT_ITINS_P>;
4201 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4202 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4203 SSE_INTSHIFT_ITINS_P>;
4205 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4206 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4207 SSE_INTSHIFT_ITINS_P>;
4208 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4209 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4210 SSE_INTSHIFT_ITINS_P>;
4211 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4212 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4213 SSE_INTSHIFT_ITINS_P>;
4215 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4216 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4217 SSE_INTSHIFT_ITINS_P>;
4218 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4219 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4220 SSE_INTSHIFT_ITINS_P>;
4222 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4223 // 128-bit logical shifts.
4224 def PSLLDQri : PDIi8<0x73, MRM7r,
4225 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4226 "pslldq\t{$src2, $dst|$dst, $src2}",
4228 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4229 IIC_SSE_INTSHDQ_P_RI>;
4230 def PSRLDQri : PDIi8<0x73, MRM3r,
4231 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4232 "psrldq\t{$src2, $dst|$dst, $src2}",
4234 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4235 IIC_SSE_INTSHDQ_P_RI>;
4236 // PSRADQri doesn't exist in SSE[1-3].
4238 } // Constraints = "$src1 = $dst"
4240 //===---------------------------------------------------------------------===//
4241 // SSE2 - Packed Integer Comparison Instructions
4242 //===---------------------------------------------------------------------===//
4244 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4245 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4246 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4247 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4248 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4249 SSE_INTALU_ITINS_P, 1, NoVLX>;
4250 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4251 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4252 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4253 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4254 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4255 SSE_INTALU_ITINS_P, 0, NoVLX>;
4257 //===---------------------------------------------------------------------===//
4258 // SSE2 - Packed Integer Shuffle Instructions
4259 //===---------------------------------------------------------------------===//
4261 let ExeDomain = SSEPackedInt in {
4262 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4264 let Predicates = [HasAVX] in {
4265 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4266 (ins VR128:$src1, u8imm:$src2),
4267 !strconcat("v", OpcodeStr,
4268 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4270 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4271 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4272 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4273 (ins i128mem:$src1, u8imm:$src2),
4274 !strconcat("v", OpcodeStr,
4275 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4277 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4278 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4279 Sched<[WriteShuffleLd]>;
4282 let Predicates = [HasAVX2] in {
4283 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4284 (ins VR256:$src1, u8imm:$src2),
4285 !strconcat("v", OpcodeStr,
4286 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4288 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4289 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4290 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4291 (ins i256mem:$src1, u8imm:$src2),
4292 !strconcat("v", OpcodeStr,
4293 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4295 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4296 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4297 Sched<[WriteShuffleLd]>;
4300 let Predicates = [UseSSE2] in {
4301 def ri : Ii8<0x70, MRMSrcReg,
4302 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4303 !strconcat(OpcodeStr,
4304 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4306 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4307 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4308 def mi : Ii8<0x70, MRMSrcMem,
4309 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4310 !strconcat(OpcodeStr,
4311 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4313 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4314 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4315 Sched<[WriteShuffleLd, ReadAfterLd]>;
4318 } // ExeDomain = SSEPackedInt
4320 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4321 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4322 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4324 let Predicates = [HasAVX] in {
4325 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4326 (VPSHUFDmi addr:$src1, imm:$imm)>;
4327 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4328 (VPSHUFDri VR128:$src1, imm:$imm)>;
4331 let Predicates = [UseSSE2] in {
4332 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4333 (PSHUFDmi addr:$src1, imm:$imm)>;
4334 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4335 (PSHUFDri VR128:$src1, imm:$imm)>;
4338 //===---------------------------------------------------------------------===//
4339 // Packed Integer Pack Instructions (SSE & AVX)
4340 //===---------------------------------------------------------------------===//
4342 let ExeDomain = SSEPackedInt in {
4343 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4344 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4345 PatFrag ld_frag, bit Is2Addr = 1> {
4346 def rr : PDI<opc, MRMSrcReg,
4347 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4349 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4350 !strconcat(OpcodeStr,
4351 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4353 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4354 Sched<[WriteShuffle]>;
4355 def rm : PDI<opc, MRMSrcMem,
4356 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4358 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4359 !strconcat(OpcodeStr,
4360 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4362 (OutVT (OpNode VR128:$src1,
4363 (bc_frag (ld_frag addr:$src2)))))]>,
4364 Sched<[WriteShuffleLd, ReadAfterLd]>;
4367 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4368 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4369 def Yrr : PDI<opc, MRMSrcReg,
4370 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4371 !strconcat(OpcodeStr,
4372 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4374 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4375 Sched<[WriteShuffle]>;
4376 def Yrm : PDI<opc, MRMSrcMem,
4377 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4378 !strconcat(OpcodeStr,
4379 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4381 (OutVT (OpNode VR256:$src1,
4382 (bc_frag (loadv4i64 addr:$src2)))))]>,
4383 Sched<[WriteShuffleLd, ReadAfterLd]>;
4386 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4387 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4388 PatFrag ld_frag, bit Is2Addr = 1> {
4389 def rr : SS48I<opc, MRMSrcReg,
4390 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4392 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4393 !strconcat(OpcodeStr,
4394 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4396 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4397 Sched<[WriteShuffle]>;
4398 def rm : SS48I<opc, MRMSrcMem,
4399 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4401 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4402 !strconcat(OpcodeStr,
4403 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4405 (OutVT (OpNode VR128:$src1,
4406 (bc_frag (ld_frag addr:$src2)))))]>,
4407 Sched<[WriteShuffleLd, ReadAfterLd]>;
4410 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4411 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4412 def Yrr : SS48I<opc, MRMSrcReg,
4413 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4414 !strconcat(OpcodeStr,
4415 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4417 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4418 Sched<[WriteShuffle]>;
4419 def Yrm : SS48I<opc, MRMSrcMem,
4420 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4421 !strconcat(OpcodeStr,
4422 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4424 (OutVT (OpNode VR256:$src1,
4425 (bc_frag (loadv4i64 addr:$src2)))))]>,
4426 Sched<[WriteShuffleLd, ReadAfterLd]>;
4429 let Predicates = [HasAVX] in {
4430 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4431 bc_v8i16, loadv2i64, 0>, VEX_4V;
4432 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4433 bc_v4i32, loadv2i64, 0>, VEX_4V;
4435 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4436 bc_v8i16, loadv2i64, 0>, VEX_4V;
4437 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4438 bc_v4i32, loadv2i64, 0>, VEX_4V;
4441 let Predicates = [HasAVX2] in {
4442 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4443 bc_v16i16>, VEX_4V, VEX_L;
4444 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4445 bc_v8i32>, VEX_4V, VEX_L;
4447 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4448 bc_v16i16>, VEX_4V, VEX_L;
4449 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4450 bc_v8i32>, VEX_4V, VEX_L;
4453 let Constraints = "$src1 = $dst" in {
4454 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4455 bc_v8i16, memopv2i64>;
4456 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4457 bc_v4i32, memopv2i64>;
4459 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4460 bc_v8i16, memopv2i64>;
4462 let Predicates = [HasSSE41] in
4463 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4464 bc_v4i32, memopv2i64>;
4466 } // ExeDomain = SSEPackedInt
4468 //===---------------------------------------------------------------------===//
4469 // SSE2 - Packed Integer Unpack Instructions
4470 //===---------------------------------------------------------------------===//
4472 let ExeDomain = SSEPackedInt in {
4473 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4474 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4476 def rr : PDI<opc, MRMSrcReg,
4477 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4479 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4480 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4481 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4482 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4483 def rm : PDI<opc, MRMSrcMem,
4484 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4486 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4487 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4488 [(set VR128:$dst, (OpNode VR128:$src1,
4489 (bc_frag (ld_frag addr:$src2))))],
4491 Sched<[WriteShuffleLd, ReadAfterLd]>;
4494 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4495 SDNode OpNode, PatFrag bc_frag> {
4496 def Yrr : PDI<opc, MRMSrcReg,
4497 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4498 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4499 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4500 Sched<[WriteShuffle]>;
4501 def Yrm : PDI<opc, MRMSrcMem,
4502 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4503 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4504 [(set VR256:$dst, (OpNode VR256:$src1,
4505 (bc_frag (loadv4i64 addr:$src2))))]>,
4506 Sched<[WriteShuffleLd, ReadAfterLd]>;
4510 let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
4511 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4512 bc_v16i8, loadv2i64, 0>, VEX_4V;
4513 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4514 bc_v8i16, loadv2i64, 0>, VEX_4V;
4515 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4516 bc_v16i8, loadv2i64, 0>, VEX_4V;
4517 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4518 bc_v8i16, loadv2i64, 0>, VEX_4V;
4520 let Predicates = [HasAVX, NoVLX] in {
4521 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4522 bc_v4i32, loadv2i64, 0>, VEX_4V;
4523 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4524 bc_v2i64, loadv2i64, 0>, VEX_4V;
4525 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4526 bc_v4i32, loadv2i64, 0>, VEX_4V;
4527 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4528 bc_v2i64, loadv2i64, 0>, VEX_4V;
4531 let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
4532 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4533 bc_v32i8>, VEX_4V, VEX_L;
4534 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4535 bc_v16i16>, VEX_4V, VEX_L;
4536 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4537 bc_v32i8>, VEX_4V, VEX_L;
4538 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4539 bc_v16i16>, VEX_4V, VEX_L;
4541 let Predicates = [HasAVX2, NoVLX] in {
4542 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4543 bc_v8i32>, VEX_4V, VEX_L;
4544 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4545 bc_v4i64>, VEX_4V, VEX_L;
4546 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4547 bc_v8i32>, VEX_4V, VEX_L;
4548 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4549 bc_v4i64>, VEX_4V, VEX_L;
4552 let Constraints = "$src1 = $dst" in {
4553 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4554 bc_v16i8, memopv2i64>;
4555 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4556 bc_v8i16, memopv2i64>;
4557 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4558 bc_v4i32, memopv2i64>;
4559 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4560 bc_v2i64, memopv2i64>;
4562 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4563 bc_v16i8, memopv2i64>;
4564 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4565 bc_v8i16, memopv2i64>;
4566 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4567 bc_v4i32, memopv2i64>;
4568 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4569 bc_v2i64, memopv2i64>;
4571 } // ExeDomain = SSEPackedInt
4573 //===---------------------------------------------------------------------===//
4574 // SSE2 - Packed Integer Extract and Insert
4575 //===---------------------------------------------------------------------===//
4577 let ExeDomain = SSEPackedInt in {
4578 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4579 def rri : Ii8<0xC4, MRMSrcReg,
4580 (outs VR128:$dst), (ins VR128:$src1,
4581 GR32orGR64:$src2, u8imm:$src3),
4583 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4584 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4586 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4587 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4588 def rmi : Ii8<0xC4, MRMSrcMem,
4589 (outs VR128:$dst), (ins VR128:$src1,
4590 i16mem:$src2, u8imm:$src3),
4592 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4593 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4595 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4596 imm:$src3))], IIC_SSE_PINSRW>,
4597 Sched<[WriteShuffleLd, ReadAfterLd]>;
4601 let Predicates = [HasAVX, NoBWI] in
4602 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4603 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4604 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4605 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4606 imm:$src2))]>, PD, VEX,
4607 Sched<[WriteShuffle]>;
4608 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4609 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4610 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4611 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4612 imm:$src2))], IIC_SSE_PEXTRW>,
4613 Sched<[WriteShuffleLd, ReadAfterLd]>;
4616 let Predicates = [HasAVX, NoBWI] in
4617 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4619 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4620 defm PINSRW : sse2_pinsrw, PD;
4622 } // ExeDomain = SSEPackedInt
4624 //===---------------------------------------------------------------------===//
4625 // SSE2 - Packed Mask Creation
4626 //===---------------------------------------------------------------------===//
4628 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4630 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4632 "pmovmskb\t{$src, $dst|$dst, $src}",
4633 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4634 IIC_SSE_MOVMSK>, VEX;
4636 let Predicates = [HasAVX2] in {
4637 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4639 "pmovmskb\t{$src, $dst|$dst, $src}",
4640 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4644 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4645 "pmovmskb\t{$src, $dst|$dst, $src}",
4646 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4649 } // ExeDomain = SSEPackedInt
4651 //===---------------------------------------------------------------------===//
4652 // SSE2 - Conditional Store
4653 //===---------------------------------------------------------------------===//
4655 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4657 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4658 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4659 (ins VR128:$src, VR128:$mask),
4660 "maskmovdqu\t{$mask, $src|$src, $mask}",
4661 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4662 IIC_SSE_MASKMOV>, VEX;
4663 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4664 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4665 (ins VR128:$src, VR128:$mask),
4666 "maskmovdqu\t{$mask, $src|$src, $mask}",
4667 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4668 IIC_SSE_MASKMOV>, VEX;
4670 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4671 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4672 "maskmovdqu\t{$mask, $src|$src, $mask}",
4673 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4675 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4676 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4677 "maskmovdqu\t{$mask, $src|$src, $mask}",
4678 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4681 } // ExeDomain = SSEPackedInt
4683 //===---------------------------------------------------------------------===//
4684 // SSE2 - Move Doubleword/Quadword
4685 //===---------------------------------------------------------------------===//
4687 //===---------------------------------------------------------------------===//
4688 // Move Int Doubleword to Packed Double Int
4690 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4691 "movd\t{$src, $dst|$dst, $src}",
4693 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4694 VEX, Sched<[WriteMove]>;
4695 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4696 "movd\t{$src, $dst|$dst, $src}",
4698 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4700 VEX, Sched<[WriteLoad]>;
4701 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4702 "movq\t{$src, $dst|$dst, $src}",
4704 (v2i64 (scalar_to_vector GR64:$src)))],
4705 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4706 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4707 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4708 "movq\t{$src, $dst|$dst, $src}",
4709 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4710 let isCodeGenOnly = 1 in
4711 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4712 "movq\t{$src, $dst|$dst, $src}",
4713 [(set FR64:$dst, (bitconvert GR64:$src))],
4714 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4716 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4717 "movd\t{$src, $dst|$dst, $src}",
4719 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4721 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4722 "movd\t{$src, $dst|$dst, $src}",
4724 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4725 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4726 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4727 "mov{d|q}\t{$src, $dst|$dst, $src}",
4729 (v2i64 (scalar_to_vector GR64:$src)))],
4730 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4731 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4732 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4733 "mov{d|q}\t{$src, $dst|$dst, $src}",
4734 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4735 let isCodeGenOnly = 1 in
4736 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4737 "mov{d|q}\t{$src, $dst|$dst, $src}",
4738 [(set FR64:$dst, (bitconvert GR64:$src))],
4739 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4741 //===---------------------------------------------------------------------===//
4742 // Move Int Doubleword to Single Scalar
4744 let isCodeGenOnly = 1 in {
4745 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4746 "movd\t{$src, $dst|$dst, $src}",
4747 [(set FR32:$dst, (bitconvert GR32:$src))],
4748 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4750 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4751 "movd\t{$src, $dst|$dst, $src}",
4752 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4754 VEX, Sched<[WriteLoad]>;
4755 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4756 "movd\t{$src, $dst|$dst, $src}",
4757 [(set FR32:$dst, (bitconvert GR32:$src))],
4758 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4760 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4761 "movd\t{$src, $dst|$dst, $src}",
4762 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4763 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4766 //===---------------------------------------------------------------------===//
4767 // Move Packed Doubleword Int to Packed Double Int
4769 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4770 "movd\t{$src, $dst|$dst, $src}",
4771 [(set GR32:$dst, (extractelt (v4i32 VR128:$src),
4772 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4774 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4775 (ins i32mem:$dst, VR128:$src),
4776 "movd\t{$src, $dst|$dst, $src}",
4777 [(store (i32 (extractelt (v4i32 VR128:$src),
4778 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4779 VEX, Sched<[WriteStore]>;
4780 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4781 "movd\t{$src, $dst|$dst, $src}",
4782 [(set GR32:$dst, (extractelt (v4i32 VR128:$src),
4783 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4785 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4786 "movd\t{$src, $dst|$dst, $src}",
4787 [(store (i32 (extractelt (v4i32 VR128:$src),
4788 (iPTR 0))), addr:$dst)],
4789 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4791 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4792 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4794 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4795 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4797 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4798 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4800 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4801 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4803 //===---------------------------------------------------------------------===//
4804 // Move Packed Doubleword Int first element to Doubleword Int
4806 let SchedRW = [WriteMove] in {
4807 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4808 "movq\t{$src, $dst|$dst, $src}",
4809 [(set GR64:$dst, (extractelt (v2i64 VR128:$src),
4814 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4815 "mov{d|q}\t{$src, $dst|$dst, $src}",
4816 [(set GR64:$dst, (extractelt (v2i64 VR128:$src),
4821 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4822 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4823 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4824 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4825 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4826 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4827 "mov{d|q}\t{$src, $dst|$dst, $src}",
4828 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4830 //===---------------------------------------------------------------------===//
4831 // Bitcast FR64 <-> GR64
4833 let isCodeGenOnly = 1 in {
4834 let Predicates = [UseAVX] in
4835 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4836 "movq\t{$src, $dst|$dst, $src}",
4837 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4838 VEX, Sched<[WriteLoad]>;
4839 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4840 "movq\t{$src, $dst|$dst, $src}",
4841 [(set GR64:$dst, (bitconvert FR64:$src))],
4842 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4843 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4844 "movq\t{$src, $dst|$dst, $src}",
4845 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4846 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4848 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4849 "movq\t{$src, $dst|$dst, $src}",
4850 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4851 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4852 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4853 "mov{d|q}\t{$src, $dst|$dst, $src}",
4854 [(set GR64:$dst, (bitconvert FR64:$src))],
4855 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4856 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4857 "movq\t{$src, $dst|$dst, $src}",
4858 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4859 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4862 //===---------------------------------------------------------------------===//
4863 // Move Scalar Single to Double Int
4865 let isCodeGenOnly = 1 in {
4866 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4867 "movd\t{$src, $dst|$dst, $src}",
4868 [(set GR32:$dst, (bitconvert FR32:$src))],
4869 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4870 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4871 "movd\t{$src, $dst|$dst, $src}",
4872 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4873 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4874 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4875 "movd\t{$src, $dst|$dst, $src}",
4876 [(set GR32:$dst, (bitconvert FR32:$src))],
4877 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4878 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4879 "movd\t{$src, $dst|$dst, $src}",
4880 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4881 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4884 let Predicates = [UseAVX] in {
4885 let AddedComplexity = 15 in {
4886 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4887 (VMOVDI2PDIrr GR32:$src)>;
4889 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
4890 (VMOV64toPQIrr GR64:$src)>;
4892 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4893 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4894 (SUBREG_TO_REG (i64 0), (VMOV64toPQIrr GR64:$src), sub_xmm)>;
4896 // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part.
4897 // These instructions also write zeros in the high part of a 256-bit register.
4898 let AddedComplexity = 20 in {
4899 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4900 (VMOVDI2PDIrm addr:$src)>;
4901 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4902 (VMOVDI2PDIrm addr:$src)>;
4903 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4904 (VMOVDI2PDIrm addr:$src)>;
4905 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4906 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
4907 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrm addr:$src), sub_xmm)>;
4909 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4910 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4911 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4912 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4915 let Predicates = [UseSSE2] in {
4916 let AddedComplexity = 15 in {
4917 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4918 (MOVDI2PDIrr GR32:$src)>;
4920 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
4921 (MOV64toPQIrr GR64:$src)>;
4923 let AddedComplexity = 20 in {
4924 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4925 (MOVDI2PDIrm addr:$src)>;
4926 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4927 (MOVDI2PDIrm addr:$src)>;
4928 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4929 (MOVDI2PDIrm addr:$src)>;
4933 // These are the correct encodings of the instructions so that we know how to
4934 // read correct assembly, even though we continue to emit the wrong ones for
4935 // compatibility with Darwin's buggy assembler.
4936 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4937 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4938 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4939 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4940 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4941 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4942 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4943 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4944 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4946 //===---------------------------------------------------------------------===//
4947 // SSE2 - Move Quadword
4948 //===---------------------------------------------------------------------===//
4950 //===---------------------------------------------------------------------===//
4951 // Move Quadword Int to Packed Quadword Int
4954 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4955 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4956 "vmovq\t{$src, $dst|$dst, $src}",
4958 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4959 VEX, Requires<[UseAVX]>;
4960 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4961 "movq\t{$src, $dst|$dst, $src}",
4963 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4965 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4966 } // ExeDomain, SchedRW
4968 //===---------------------------------------------------------------------===//
4969 // Move Packed Quadword Int to Quadword Int
4971 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4972 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4973 "movq\t{$src, $dst|$dst, $src}",
4974 [(store (i64 (extractelt (v2i64 VR128:$src),
4975 (iPTR 0))), addr:$dst)],
4976 IIC_SSE_MOVDQ>, VEX;
4977 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4978 "movq\t{$src, $dst|$dst, $src}",
4979 [(store (i64 (extractelt (v2i64 VR128:$src),
4980 (iPTR 0))), addr:$dst)],
4982 } // ExeDomain, SchedRW
4984 // For disassembler only
4985 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4986 SchedRW = [WriteVecLogic] in {
4987 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4988 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
4989 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4990 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
4993 //===---------------------------------------------------------------------===//
4994 // Store / copy lower 64-bits of a XMM register.
4996 let Predicates = [HasAVX] in
4997 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4998 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
4999 let Predicates = [UseSSE2] in
5000 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5001 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5003 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
5004 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5005 "vmovq\t{$src, $dst|$dst, $src}",
5007 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5008 (loadi64 addr:$src))))))],
5010 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5012 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5013 "movq\t{$src, $dst|$dst, $src}",
5015 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5016 (loadi64 addr:$src))))))],
5018 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5019 } // ExeDomain, isCodeGenOnly, AddedComplexity
5021 let Predicates = [UseAVX], AddedComplexity = 20 in {
5022 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5023 (VMOVZQI2PQIrm addr:$src)>;
5024 def : Pat<(v2i64 (X86vzload addr:$src)),
5025 (VMOVZQI2PQIrm addr:$src)>;
5026 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5027 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
5028 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
5031 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5032 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5033 (MOVZQI2PQIrm addr:$src)>;
5034 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5037 let Predicates = [HasAVX] in {
5038 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5039 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5040 def : Pat<(v4i64 (X86vzload addr:$src)),
5041 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5044 //===---------------------------------------------------------------------===//
5045 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5046 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5048 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5049 let AddedComplexity = 15 in
5050 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5051 "vmovq\t{$src, $dst|$dst, $src}",
5052 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5054 XS, VEX, Requires<[UseAVX]>;
5055 let AddedComplexity = 15 in
5056 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5057 "movq\t{$src, $dst|$dst, $src}",
5058 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5060 XS, Requires<[UseSSE2]>;
5061 } // ExeDomain, SchedRW
5063 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5064 let AddedComplexity = 20 in
5065 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5066 "vmovq\t{$src, $dst|$dst, $src}",
5067 [(set VR128:$dst, (v2i64 (X86vzmovl
5068 (loadv2i64 addr:$src))))],
5070 XS, VEX, Requires<[UseAVX]>;
5071 let AddedComplexity = 20 in {
5072 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5073 "movq\t{$src, $dst|$dst, $src}",
5074 [(set VR128:$dst, (v2i64 (X86vzmovl
5075 (loadv2i64 addr:$src))))],
5077 XS, Requires<[UseSSE2]>;
5079 } // ExeDomain, isCodeGenOnly, SchedRW
5081 let AddedComplexity = 20 in {
5082 let Predicates = [UseAVX] in {
5083 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5084 (VMOVZPQILo2PQIrr VR128:$src)>;
5086 let Predicates = [UseSSE2] in {
5087 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5088 (MOVZPQILo2PQIrr VR128:$src)>;
5092 //===---------------------------------------------------------------------===//
5093 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5094 //===---------------------------------------------------------------------===//
5095 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5096 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5097 X86MemOperand x86memop> {
5098 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5099 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5100 [(set RC:$dst, (vt (OpNode RC:$src)))],
5101 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5102 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5103 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5104 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5105 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5108 let Predicates = [HasAVX, NoVLX] in {
5109 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5110 v4f32, VR128, loadv4f32, f128mem>, VEX;
5111 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5112 v4f32, VR128, loadv4f32, f128mem>, VEX;
5113 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5114 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5115 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5116 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5118 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5119 memopv4f32, f128mem>;
5120 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5121 memopv4f32, f128mem>;
5123 let Predicates = [HasAVX, NoVLX] in {
5124 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5125 (VMOVSHDUPrr VR128:$src)>;
5126 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5127 (VMOVSHDUPrm addr:$src)>;
5128 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5129 (VMOVSLDUPrr VR128:$src)>;
5130 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5131 (VMOVSLDUPrm addr:$src)>;
5132 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5133 (VMOVSHDUPYrr VR256:$src)>;
5134 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5135 (VMOVSHDUPYrm addr:$src)>;
5136 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5137 (VMOVSLDUPYrr VR256:$src)>;
5138 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5139 (VMOVSLDUPYrm addr:$src)>;
5142 let Predicates = [UseSSE3] in {
5143 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5144 (MOVSHDUPrr VR128:$src)>;
5145 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5146 (MOVSHDUPrm addr:$src)>;
5147 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5148 (MOVSLDUPrr VR128:$src)>;
5149 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5150 (MOVSLDUPrm addr:$src)>;
5153 //===---------------------------------------------------------------------===//
5154 // SSE3 - Replicate Double FP - MOVDDUP
5155 //===---------------------------------------------------------------------===//
5157 multiclass sse3_replicate_dfp<string OpcodeStr> {
5158 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5159 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5160 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5161 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5162 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5163 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5166 (scalar_to_vector (loadf64 addr:$src)))))],
5167 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5170 // FIXME: Merge with above classe when there're patterns for the ymm version
5171 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5172 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5173 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5174 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5175 Sched<[WriteFShuffle]>;
5176 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5177 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5179 (v4f64 (X86Movddup (loadv4f64 addr:$src))))]>,
5183 let Predicates = [HasAVX, NoVLX] in {
5184 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5185 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5188 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5191 let Predicates = [HasAVX, NoVLX] in {
5192 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5193 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5196 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5197 (VMOVDDUPYrm addr:$src)>;
5198 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5199 (VMOVDDUPYrr VR256:$src)>;
5202 let Predicates = [HasAVX] in {
5203 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5204 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5205 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5206 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5207 def : Pat<(X86Movddup (bc_v2f64
5208 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5209 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5212 let Predicates = [UseAVX, OptForSize] in {
5213 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5214 (VMOVDDUPrm addr:$src)>;
5215 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5216 (VMOVDDUPrm addr:$src)>;
5219 let Predicates = [UseSSE3] in {
5220 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5221 (MOVDDUPrm addr:$src)>;
5222 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5223 (MOVDDUPrm addr:$src)>;
5224 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5225 (MOVDDUPrm addr:$src)>;
5226 def : Pat<(X86Movddup (bc_v2f64
5227 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5228 (MOVDDUPrm addr:$src)>;
5231 //===---------------------------------------------------------------------===//
5232 // SSE3 - Move Unaligned Integer
5233 //===---------------------------------------------------------------------===//
5235 let SchedRW = [WriteLoad] in {
5236 let Predicates = [HasAVX] in {
5237 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5238 "vlddqu\t{$src, $dst|$dst, $src}",
5239 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5240 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5241 "vlddqu\t{$src, $dst|$dst, $src}",
5242 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5245 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5246 "lddqu\t{$src, $dst|$dst, $src}",
5247 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5251 //===---------------------------------------------------------------------===//
5252 // SSE3 - Arithmetic
5253 //===---------------------------------------------------------------------===//
5255 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5256 X86MemOperand x86memop, OpndItins itins,
5257 PatFrag ld_frag, bit Is2Addr = 1> {
5258 def rr : I<0xD0, MRMSrcReg,
5259 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5261 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5262 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5263 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5264 Sched<[itins.Sched]>;
5265 def rm : I<0xD0, MRMSrcMem,
5266 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5268 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5269 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5270 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5271 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5274 let Predicates = [HasAVX] in {
5275 let ExeDomain = SSEPackedSingle in {
5276 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5277 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5278 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5279 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5281 let ExeDomain = SSEPackedDouble in {
5282 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5283 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5284 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5285 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5288 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5289 let ExeDomain = SSEPackedSingle in
5290 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5291 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5292 let ExeDomain = SSEPackedDouble in
5293 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5294 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5297 // Patterns used to select 'addsub' instructions.
5298 let Predicates = [HasAVX] in {
5299 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5300 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5301 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5302 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5303 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5304 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5305 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5306 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5308 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5309 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5310 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5311 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5312 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5313 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5314 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5315 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5318 let Predicates = [UseSSE3] in {
5319 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5320 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5321 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5322 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5323 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5324 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5325 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5326 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5329 //===---------------------------------------------------------------------===//
5330 // SSE3 Instructions
5331 //===---------------------------------------------------------------------===//
5334 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5335 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5337 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5339 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5340 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5341 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5344 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5348 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5349 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5351 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5352 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5354 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5356 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5357 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5358 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5361 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5363 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5364 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5365 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5366 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5369 let Predicates = [HasAVX] in {
5370 let ExeDomain = SSEPackedSingle in {
5371 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5372 X86fhadd, loadv4f32, 0>, VEX_4V;
5373 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5374 X86fhsub, loadv4f32, 0>, VEX_4V;
5375 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5376 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5377 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5378 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5380 let ExeDomain = SSEPackedDouble in {
5381 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5382 X86fhadd, loadv2f64, 0>, VEX_4V;
5383 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5384 X86fhsub, loadv2f64, 0>, VEX_4V;
5385 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5386 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5387 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5388 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5392 let Constraints = "$src1 = $dst" in {
5393 let ExeDomain = SSEPackedSingle in {
5394 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5396 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5399 let ExeDomain = SSEPackedDouble in {
5400 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5402 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5407 //===---------------------------------------------------------------------===//
5408 // SSSE3 - Packed Absolute Instructions
5409 //===---------------------------------------------------------------------===//
5412 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5413 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5415 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5417 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5418 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5419 Sched<[WriteVecALU]>;
5421 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5423 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5426 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5427 Sched<[WriteVecALULd]>;
5430 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5431 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5432 Intrinsic IntId256> {
5433 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5435 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5436 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5437 Sched<[WriteVecALU]>;
5439 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5441 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5444 (bitconvert (loadv4i64 addr:$src))))]>,
5445 Sched<[WriteVecALULd]>;
5448 // Helper fragments to match sext vXi1 to vXiY.
5449 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5451 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5452 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5453 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5455 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5456 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5458 let Predicates = [HasAVX] in {
5459 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5461 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5463 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5467 (bc_v2i64 (v16i1sextv16i8)),
5468 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5469 (VPABSBrr128 VR128:$src)>;
5471 (bc_v2i64 (v8i1sextv8i16)),
5472 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5473 (VPABSWrr128 VR128:$src)>;
5475 (bc_v2i64 (v4i1sextv4i32)),
5476 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5477 (VPABSDrr128 VR128:$src)>;
5480 let Predicates = [HasAVX2] in {
5481 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5482 int_x86_avx2_pabs_b>, VEX, VEX_L;
5483 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5484 int_x86_avx2_pabs_w>, VEX, VEX_L;
5485 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5486 int_x86_avx2_pabs_d>, VEX, VEX_L;
5489 (bc_v4i64 (v32i1sextv32i8)),
5490 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5491 (VPABSBrr256 VR256:$src)>;
5493 (bc_v4i64 (v16i1sextv16i16)),
5494 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5495 (VPABSWrr256 VR256:$src)>;
5497 (bc_v4i64 (v8i1sextv8i32)),
5498 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5499 (VPABSDrr256 VR256:$src)>;
5502 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5504 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5506 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5509 let Predicates = [HasSSSE3] in {
5511 (bc_v2i64 (v16i1sextv16i8)),
5512 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5513 (PABSBrr128 VR128:$src)>;
5515 (bc_v2i64 (v8i1sextv8i16)),
5516 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5517 (PABSWrr128 VR128:$src)>;
5519 (bc_v2i64 (v4i1sextv4i32)),
5520 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5521 (PABSDrr128 VR128:$src)>;
5524 //===---------------------------------------------------------------------===//
5525 // SSSE3 - Packed Binary Operator Instructions
5526 //===---------------------------------------------------------------------===//
5528 let Sched = WriteVecALU in {
5529 def SSE_PHADDSUBD : OpndItins<
5530 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5532 def SSE_PHADDSUBSW : OpndItins<
5533 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5535 def SSE_PHADDSUBW : OpndItins<
5536 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5539 let Sched = WriteShuffle in
5540 def SSE_PSHUFB : OpndItins<
5541 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5543 let Sched = WriteVecALU in
5544 def SSE_PSIGN : OpndItins<
5545 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5547 let Sched = WriteVecIMul in
5548 def SSE_PMULHRSW : OpndItins<
5549 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5552 /// SS3I_binop_rm - Simple SSSE3 bin op
5553 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5554 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5555 X86MemOperand x86memop, OpndItins itins,
5557 let isCommutable = 1 in
5558 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5559 (ins RC:$src1, RC:$src2),
5561 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5562 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5563 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5564 Sched<[itins.Sched]>;
5565 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5566 (ins RC:$src1, x86memop:$src2),
5568 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5569 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5571 (OpVT (OpNode RC:$src1,
5572 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5573 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5576 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5577 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5578 Intrinsic IntId128, OpndItins itins,
5579 PatFrag ld_frag, bit Is2Addr = 1> {
5580 let isCommutable = 1 in
5581 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5582 (ins VR128:$src1, VR128:$src2),
5584 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5585 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5586 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5587 Sched<[itins.Sched]>;
5588 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5589 (ins VR128:$src1, i128mem:$src2),
5591 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5592 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5594 (IntId128 VR128:$src1,
5595 (bitconvert (ld_frag addr:$src2))))]>,
5596 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5599 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5601 X86FoldableSchedWrite Sched> {
5602 let isCommutable = 1 in
5603 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5604 (ins VR256:$src1, VR256:$src2),
5605 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5606 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5608 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5609 (ins VR256:$src1, i256mem:$src2),
5610 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5612 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5613 Sched<[Sched.Folded, ReadAfterLd]>;
5616 let ImmT = NoImm, Predicates = [HasAVX] in {
5617 let isCommutable = 0 in {
5618 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5620 SSE_PHADDSUBW, 0>, VEX_4V;
5621 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5623 SSE_PHADDSUBD, 0>, VEX_4V;
5624 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5626 SSE_PHADDSUBW, 0>, VEX_4V;
5627 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5629 SSE_PHADDSUBD, 0>, VEX_4V;
5630 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5632 SSE_PSIGN, 0>, VEX_4V;
5633 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5635 SSE_PSIGN, 0>, VEX_4V;
5636 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5638 SSE_PSIGN, 0>, VEX_4V;
5639 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5641 SSE_PSHUFB, 0>, VEX_4V;
5642 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5643 int_x86_ssse3_phadd_sw_128,
5644 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5645 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5646 int_x86_ssse3_phsub_sw_128,
5647 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5648 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5649 int_x86_ssse3_pmadd_ub_sw_128,
5650 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5652 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5653 int_x86_ssse3_pmul_hr_sw_128,
5654 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5657 let ImmT = NoImm, Predicates = [HasAVX2] in {
5658 let isCommutable = 0 in {
5659 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5661 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5662 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5664 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5665 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5667 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5668 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5670 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5671 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5673 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5674 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5676 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5677 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5679 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5680 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5682 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5683 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5684 int_x86_avx2_phadd_sw,
5685 WriteVecALU>, VEX_4V, VEX_L;
5686 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5687 int_x86_avx2_phsub_sw,
5688 WriteVecALU>, VEX_4V, VEX_L;
5689 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5690 int_x86_avx2_pmadd_ub_sw,
5691 WriteVecIMul>, VEX_4V, VEX_L;
5693 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5694 int_x86_avx2_pmul_hr_sw,
5695 WriteVecIMul>, VEX_4V, VEX_L;
5698 // None of these have i8 immediate fields.
5699 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5700 let isCommutable = 0 in {
5701 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5702 memopv2i64, i128mem, SSE_PHADDSUBW>;
5703 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5704 memopv2i64, i128mem, SSE_PHADDSUBD>;
5705 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5706 memopv2i64, i128mem, SSE_PHADDSUBW>;
5707 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5708 memopv2i64, i128mem, SSE_PHADDSUBD>;
5709 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5710 memopv2i64, i128mem, SSE_PSIGN>;
5711 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5712 memopv2i64, i128mem, SSE_PSIGN>;
5713 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5714 memopv2i64, i128mem, SSE_PSIGN>;
5715 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5716 memopv2i64, i128mem, SSE_PSHUFB>;
5717 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5718 int_x86_ssse3_phadd_sw_128,
5719 SSE_PHADDSUBSW, memopv2i64>;
5720 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5721 int_x86_ssse3_phsub_sw_128,
5722 SSE_PHADDSUBSW, memopv2i64>;
5723 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5724 int_x86_ssse3_pmadd_ub_sw_128,
5725 SSE_PMADD, memopv2i64>;
5727 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5728 int_x86_ssse3_pmul_hr_sw_128,
5729 SSE_PMULHRSW, memopv2i64>;
5732 //===---------------------------------------------------------------------===//
5733 // SSSE3 - Packed Align Instruction Patterns
5734 //===---------------------------------------------------------------------===//
5736 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5737 let hasSideEffects = 0 in {
5738 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5739 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5741 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5743 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5744 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5746 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5747 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5749 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5751 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5752 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5756 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5757 let hasSideEffects = 0 in {
5758 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5759 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5761 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5762 []>, Sched<[WriteShuffle]>;
5764 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5765 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5767 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5768 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5772 let Predicates = [HasAVX] in
5773 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5774 let Predicates = [HasAVX2] in
5775 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5776 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5777 defm PALIGN : ssse3_palignr<"palignr">;
5779 let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
5780 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5781 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5782 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5783 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5784 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5785 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5786 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5787 (VPALIGNR256rr VR256:$src1, VR256:$src2, imm:$imm)>;
5790 let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
5791 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5792 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5793 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5794 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5795 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5796 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5797 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5798 (VPALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5801 let Predicates = [UseSSSE3] in {
5802 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5803 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5804 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5805 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5806 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5807 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5808 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5809 (PALIGNR128rr VR128:$src1, VR128:$src2, imm:$imm)>;
5812 //===---------------------------------------------------------------------===//
5813 // SSSE3 - Thread synchronization
5814 //===---------------------------------------------------------------------===//
5816 let SchedRW = [WriteSystem] in {
5817 let usesCustomInserter = 1 in {
5818 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5819 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5820 Requires<[HasSSE3]>;
5823 let Uses = [EAX, ECX, EDX] in
5824 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5825 TB, Requires<[HasSSE3]>;
5826 let Uses = [ECX, EAX] in
5827 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5828 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5829 TB, Requires<[HasSSE3]>;
5832 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5833 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5835 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5836 Requires<[Not64BitMode]>;
5837 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5838 Requires<[In64BitMode]>;
5840 //===----------------------------------------------------------------------===//
5841 // SSE4.1 - Packed Move with Sign/Zero Extend
5842 //===----------------------------------------------------------------------===//
5844 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5845 RegisterClass OutRC, RegisterClass InRC,
5847 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5848 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5850 Sched<[itins.Sched]>;
5852 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5853 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5855 itins.rm>, Sched<[itins.Sched.Folded]>;
5858 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5859 X86MemOperand MemOp, X86MemOperand MemYOp,
5860 OpndItins SSEItins, OpndItins AVXItins,
5861 OpndItins AVX2Itins> {
5862 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5863 let Predicates = [HasAVX, NoVLX] in
5864 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5865 VR128, VR128, AVXItins>, VEX;
5866 let Predicates = [HasAVX2, NoVLX] in
5867 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5868 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5871 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5872 X86MemOperand MemOp, X86MemOperand MemYOp> {
5873 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5875 SSE_INTALU_ITINS_SHUFF_P,
5876 DEFAULT_ITINS_SHUFFLESCHED,
5877 DEFAULT_ITINS_SHUFFLESCHED>;
5878 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5879 !strconcat("pmovzx", OpcodeStr),
5881 SSE_INTALU_ITINS_SHUFF_P,
5882 DEFAULT_ITINS_SHUFFLESCHED,
5883 DEFAULT_ITINS_SHUFFLESCHED>;
5886 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5887 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5888 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5890 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5891 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5893 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5896 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5897 // Register-Register patterns
5898 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5899 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5900 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5901 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5902 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5903 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5905 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5906 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5907 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5908 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5910 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5911 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5913 // On AVX2, we also support 256bit inputs.
5914 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5915 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5916 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5917 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5918 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5919 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5921 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5922 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5923 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5924 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5926 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5927 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5929 // Simple Register-Memory patterns
5930 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5931 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5932 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5933 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5934 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5935 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5937 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5938 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5939 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5940 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5942 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5943 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5945 // AVX2 Register-Memory patterns
5946 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5947 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5948 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5949 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5950 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5951 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5952 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5953 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5955 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5956 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5957 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5958 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5959 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5960 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5961 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5962 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5964 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5965 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5966 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5967 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5968 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5969 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5970 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5971 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5973 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5974 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5975 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5976 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5977 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5978 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5979 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5980 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5982 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5983 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5984 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5985 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5986 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5987 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5988 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5989 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5991 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5992 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5993 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
5994 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5995 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
5996 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5997 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5998 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6001 let Predicates = [HasAVX2, NoVLX] in {
6002 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6003 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6006 // SSE4.1/AVX patterns.
6007 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6008 SDNode ExtOp, PatFrag ExtLoad16> {
6009 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6010 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6011 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6012 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6013 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6014 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6016 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6017 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6018 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6019 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6021 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6022 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6024 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6025 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6026 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6027 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6028 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6029 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6031 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6032 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6033 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6034 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6036 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6037 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6039 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6040 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6041 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6042 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6043 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6044 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6045 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6046 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6047 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6048 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6050 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6051 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6052 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6053 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6054 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6055 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6056 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6057 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6059 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6060 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6061 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6062 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6063 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6064 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6065 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6066 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6068 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6069 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6070 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6071 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6072 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6073 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6074 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6075 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6076 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6077 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6079 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6080 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6081 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6082 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6083 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6084 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6085 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6086 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6088 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6089 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6090 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6091 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6092 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6093 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6094 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6095 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6096 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6097 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6100 let Predicates = [HasAVX, NoVLX] in {
6101 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6102 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6105 let Predicates = [UseSSE41] in {
6106 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6107 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6110 //===----------------------------------------------------------------------===//
6111 // SSE4.1 - Extract Instructions
6112 //===----------------------------------------------------------------------===//
6114 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6115 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6116 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6117 (ins VR128:$src1, u8imm:$src2),
6118 !strconcat(OpcodeStr,
6119 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6120 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6122 Sched<[WriteShuffle]>;
6123 let hasSideEffects = 0, mayStore = 1,
6124 SchedRW = [WriteShuffleLd, WriteRMW] in
6125 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6126 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6127 !strconcat(OpcodeStr,
6128 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6129 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6130 imm:$src2)))), addr:$dst)]>;
6133 let Predicates = [HasAVX, NoBWI] in
6134 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6136 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6139 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6140 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6141 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6142 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6143 (ins VR128:$src1, u8imm:$src2),
6144 !strconcat(OpcodeStr,
6145 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6146 []>, Sched<[WriteShuffle]>;
6148 let hasSideEffects = 0, mayStore = 1,
6149 SchedRW = [WriteShuffleLd, WriteRMW] in
6150 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6151 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6152 !strconcat(OpcodeStr,
6153 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6154 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6155 imm:$src2)))), addr:$dst)]>;
6158 let Predicates = [HasAVX, NoBWI] in
6159 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6161 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6164 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6165 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6166 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6167 (ins VR128:$src1, u8imm:$src2),
6168 !strconcat(OpcodeStr,
6169 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6171 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6172 Sched<[WriteShuffle]>;
6173 let SchedRW = [WriteShuffleLd, WriteRMW] in
6174 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6175 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6176 !strconcat(OpcodeStr,
6177 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6178 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6182 let Predicates = [HasAVX, NoDQI] in
6183 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6185 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6187 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6188 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6189 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6190 (ins VR128:$src1, u8imm:$src2),
6191 !strconcat(OpcodeStr,
6192 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6194 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6195 Sched<[WriteShuffle]>, REX_W;
6196 let SchedRW = [WriteShuffleLd, WriteRMW] in
6197 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6198 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6199 !strconcat(OpcodeStr,
6200 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6201 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6202 addr:$dst)]>, REX_W;
6205 let Predicates = [HasAVX, NoDQI] in
6206 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6208 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6210 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6212 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6213 OpndItins itins = DEFAULT_ITINS> {
6214 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6215 (ins VR128:$src1, u8imm:$src2),
6216 !strconcat(OpcodeStr,
6217 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6218 [(set GR32orGR64:$dst,
6219 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6220 itins.rr>, Sched<[WriteFBlend]>;
6221 let SchedRW = [WriteFBlendLd, WriteRMW] in
6222 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6223 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6224 !strconcat(OpcodeStr,
6225 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6226 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6227 addr:$dst)], itins.rm>;
6230 let ExeDomain = SSEPackedSingle in {
6231 let Predicates = [UseAVX] in
6232 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6233 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6236 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6237 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6240 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6242 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6245 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6246 Requires<[UseSSE41]>;
6248 //===----------------------------------------------------------------------===//
6249 // SSE4.1 - Insert Instructions
6250 //===----------------------------------------------------------------------===//
6252 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6253 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6254 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6256 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6258 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6260 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6261 Sched<[WriteShuffle]>;
6262 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6263 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6265 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6267 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6269 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6270 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6273 let Predicates = [HasAVX, NoBWI] in
6274 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6275 let Constraints = "$src1 = $dst" in
6276 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6278 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6279 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6280 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6282 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6284 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6286 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6287 Sched<[WriteShuffle]>;
6288 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6289 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6291 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6293 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6295 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6296 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6299 let Predicates = [HasAVX, NoDQI] in
6300 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6301 let Constraints = "$src1 = $dst" in
6302 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6304 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6305 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6306 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6308 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6310 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6312 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6313 Sched<[WriteShuffle]>;
6314 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6315 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6317 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6319 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6321 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6322 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6325 let Predicates = [HasAVX, NoDQI] in
6326 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6327 let Constraints = "$src1 = $dst" in
6328 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6330 // insertps has a few different modes, there's the first two here below which
6331 // are optimized inserts that won't zero arbitrary elements in the destination
6332 // vector. The next one matches the intrinsic and could zero arbitrary elements
6333 // in the target vector.
6334 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6335 OpndItins itins = DEFAULT_ITINS> {
6336 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6337 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6339 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6341 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6343 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6344 Sched<[WriteFShuffle]>;
6345 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6346 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6348 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6350 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6352 (X86insertps VR128:$src1,
6353 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6354 imm:$src3))], itins.rm>,
6355 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6358 let ExeDomain = SSEPackedSingle in {
6359 let Predicates = [UseAVX] in
6360 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6361 let Constraints = "$src1 = $dst" in
6362 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6365 let Predicates = [UseSSE41] in {
6366 // If we're inserting an element from a load or a null pshuf of a load,
6367 // fold the load into the insertps instruction.
6368 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6369 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6371 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6372 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6373 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6374 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6377 let Predicates = [UseAVX] in {
6378 // If we're inserting an element from a vbroadcast of a load, fold the
6379 // load into the X86insertps instruction.
6380 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6381 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6382 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6383 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6384 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6385 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6388 //===----------------------------------------------------------------------===//
6389 // SSE4.1 - Round Instructions
6390 //===----------------------------------------------------------------------===//
6392 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6393 X86MemOperand x86memop, RegisterClass RC,
6394 PatFrag mem_frag32, PatFrag mem_frag64,
6395 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6396 let ExeDomain = SSEPackedSingle in {
6397 // Intrinsic operation, reg.
6398 // Vector intrinsic operation, reg
6399 def PSr : SS4AIi8<opcps, MRMSrcReg,
6400 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6401 !strconcat(OpcodeStr,
6402 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6403 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6404 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6406 // Vector intrinsic operation, mem
6407 def PSm : SS4AIi8<opcps, MRMSrcMem,
6408 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6409 !strconcat(OpcodeStr,
6410 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6412 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6413 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6414 } // ExeDomain = SSEPackedSingle
6416 let ExeDomain = SSEPackedDouble in {
6417 // Vector intrinsic operation, reg
6418 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6419 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6420 !strconcat(OpcodeStr,
6421 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6422 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6423 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6425 // Vector intrinsic operation, mem
6426 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6427 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6428 !strconcat(OpcodeStr,
6429 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6431 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6432 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6433 } // ExeDomain = SSEPackedDouble
6436 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6439 Intrinsic F64Int, bit Is2Addr = 1> {
6440 let ExeDomain = GenericDomain in {
6442 let hasSideEffects = 0 in
6443 def SSr : SS4AIi8<opcss, MRMSrcReg,
6444 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6446 !strconcat(OpcodeStr,
6447 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6448 !strconcat(OpcodeStr,
6449 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6450 []>, Sched<[WriteFAdd]>;
6452 // Intrinsic operation, reg.
6453 let isCodeGenOnly = 1 in
6454 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6455 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6457 !strconcat(OpcodeStr,
6458 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6459 !strconcat(OpcodeStr,
6460 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6461 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6464 // Intrinsic operation, mem.
6465 def SSm : SS4AIi8<opcss, MRMSrcMem,
6466 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6468 !strconcat(OpcodeStr,
6469 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6470 !strconcat(OpcodeStr,
6471 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6473 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6474 Sched<[WriteFAddLd, ReadAfterLd]>;
6477 let hasSideEffects = 0 in
6478 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6479 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6481 !strconcat(OpcodeStr,
6482 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6483 !strconcat(OpcodeStr,
6484 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6485 []>, Sched<[WriteFAdd]>;
6487 // Intrinsic operation, reg.
6488 let isCodeGenOnly = 1 in
6489 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6490 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6492 !strconcat(OpcodeStr,
6493 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6494 !strconcat(OpcodeStr,
6495 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6496 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6499 // Intrinsic operation, mem.
6500 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6501 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6503 !strconcat(OpcodeStr,
6504 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6505 !strconcat(OpcodeStr,
6506 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6508 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6509 Sched<[WriteFAddLd, ReadAfterLd]>;
6510 } // ExeDomain = GenericDomain
6513 // FP round - roundss, roundps, roundsd, roundpd
6514 let Predicates = [HasAVX] in {
6516 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6517 loadv4f32, loadv2f64,
6518 int_x86_sse41_round_ps,
6519 int_x86_sse41_round_pd>, VEX;
6520 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6521 loadv8f32, loadv4f64,
6522 int_x86_avx_round_ps_256,
6523 int_x86_avx_round_pd_256>, VEX, VEX_L;
6524 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6525 int_x86_sse41_round_ss,
6526 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6529 let Predicates = [UseAVX] in {
6530 def : Pat<(ffloor FR32:$src),
6531 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>;
6532 def : Pat<(f64 (ffloor FR64:$src)),
6533 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>;
6534 def : Pat<(f32 (fnearbyint FR32:$src)),
6535 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6536 def : Pat<(f64 (fnearbyint FR64:$src)),
6537 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6538 def : Pat<(f32 (fceil FR32:$src)),
6539 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>;
6540 def : Pat<(f64 (fceil FR64:$src)),
6541 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>;
6542 def : Pat<(f32 (frint FR32:$src)),
6543 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6544 def : Pat<(f64 (frint FR64:$src)),
6545 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6546 def : Pat<(f32 (ftrunc FR32:$src)),
6547 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>;
6548 def : Pat<(f64 (ftrunc FR64:$src)),
6549 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>;
6552 let Predicates = [HasAVX] in {
6553 def : Pat<(v4f32 (ffloor VR128:$src)),
6554 (VROUNDPSr VR128:$src, (i32 0x9))>;
6555 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6556 (VROUNDPSr VR128:$src, (i32 0xC))>;
6557 def : Pat<(v4f32 (fceil VR128:$src)),
6558 (VROUNDPSr VR128:$src, (i32 0xA))>;
6559 def : Pat<(v4f32 (frint VR128:$src)),
6560 (VROUNDPSr VR128:$src, (i32 0x4))>;
6561 def : Pat<(v4f32 (ftrunc VR128:$src)),
6562 (VROUNDPSr VR128:$src, (i32 0xB))>;
6564 def : Pat<(v2f64 (ffloor VR128:$src)),
6565 (VROUNDPDr VR128:$src, (i32 0x9))>;
6566 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6567 (VROUNDPDr VR128:$src, (i32 0xC))>;
6568 def : Pat<(v2f64 (fceil VR128:$src)),
6569 (VROUNDPDr VR128:$src, (i32 0xA))>;
6570 def : Pat<(v2f64 (frint VR128:$src)),
6571 (VROUNDPDr VR128:$src, (i32 0x4))>;
6572 def : Pat<(v2f64 (ftrunc VR128:$src)),
6573 (VROUNDPDr VR128:$src, (i32 0xB))>;
6575 def : Pat<(v8f32 (ffloor VR256:$src)),
6576 (VROUNDYPSr VR256:$src, (i32 0x9))>;
6577 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6578 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6579 def : Pat<(v8f32 (fceil VR256:$src)),
6580 (VROUNDYPSr VR256:$src, (i32 0xA))>;
6581 def : Pat<(v8f32 (frint VR256:$src)),
6582 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6583 def : Pat<(v8f32 (ftrunc VR256:$src)),
6584 (VROUNDYPSr VR256:$src, (i32 0xB))>;
6586 def : Pat<(v4f64 (ffloor VR256:$src)),
6587 (VROUNDYPDr VR256:$src, (i32 0x9))>;
6588 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6589 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6590 def : Pat<(v4f64 (fceil VR256:$src)),
6591 (VROUNDYPDr VR256:$src, (i32 0xA))>;
6592 def : Pat<(v4f64 (frint VR256:$src)),
6593 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6594 def : Pat<(v4f64 (ftrunc VR256:$src)),
6595 (VROUNDYPDr VR256:$src, (i32 0xB))>;
6598 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6599 memopv4f32, memopv2f64,
6600 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6601 let Constraints = "$src1 = $dst" in
6602 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6603 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6605 let Predicates = [UseSSE41] in {
6606 def : Pat<(ffloor FR32:$src),
6607 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x9))>;
6608 def : Pat<(f64 (ffloor FR64:$src)),
6609 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x9))>;
6610 def : Pat<(f32 (fnearbyint FR32:$src)),
6611 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6612 def : Pat<(f64 (fnearbyint FR64:$src)),
6613 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6614 def : Pat<(f32 (fceil FR32:$src)),
6615 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xA))>;
6616 def : Pat<(f64 (fceil FR64:$src)),
6617 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xA))>;
6618 def : Pat<(f32 (frint FR32:$src)),
6619 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6620 def : Pat<(f64 (frint FR64:$src)),
6621 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6622 def : Pat<(f32 (ftrunc FR32:$src)),
6623 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xB))>;
6624 def : Pat<(f64 (ftrunc FR64:$src)),
6625 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xB))>;
6627 def : Pat<(v4f32 (ffloor VR128:$src)),
6628 (ROUNDPSr VR128:$src, (i32 0x9))>;
6629 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6630 (ROUNDPSr VR128:$src, (i32 0xC))>;
6631 def : Pat<(v4f32 (fceil VR128:$src)),
6632 (ROUNDPSr VR128:$src, (i32 0xA))>;
6633 def : Pat<(v4f32 (frint VR128:$src)),
6634 (ROUNDPSr VR128:$src, (i32 0x4))>;
6635 def : Pat<(v4f32 (ftrunc VR128:$src)),
6636 (ROUNDPSr VR128:$src, (i32 0xB))>;
6638 def : Pat<(v2f64 (ffloor VR128:$src)),
6639 (ROUNDPDr VR128:$src, (i32 0x9))>;
6640 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6641 (ROUNDPDr VR128:$src, (i32 0xC))>;
6642 def : Pat<(v2f64 (fceil VR128:$src)),
6643 (ROUNDPDr VR128:$src, (i32 0xA))>;
6644 def : Pat<(v2f64 (frint VR128:$src)),
6645 (ROUNDPDr VR128:$src, (i32 0x4))>;
6646 def : Pat<(v2f64 (ftrunc VR128:$src)),
6647 (ROUNDPDr VR128:$src, (i32 0xB))>;
6650 //===----------------------------------------------------------------------===//
6651 // SSE4.1 - Packed Bit Test
6652 //===----------------------------------------------------------------------===//
6654 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6655 // the intel intrinsic that corresponds to this.
6656 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6657 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6658 "vptest\t{$src2, $src1|$src1, $src2}",
6659 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6660 Sched<[WriteVecLogic]>, VEX;
6661 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6662 "vptest\t{$src2, $src1|$src1, $src2}",
6663 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6664 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6666 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6667 "vptest\t{$src2, $src1|$src1, $src2}",
6668 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6669 Sched<[WriteVecLogic]>, VEX, VEX_L;
6670 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6671 "vptest\t{$src2, $src1|$src1, $src2}",
6672 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6673 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6676 let Defs = [EFLAGS] in {
6677 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6678 "ptest\t{$src2, $src1|$src1, $src2}",
6679 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6680 Sched<[WriteVecLogic]>;
6681 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6682 "ptest\t{$src2, $src1|$src1, $src2}",
6683 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6684 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6687 // The bit test instructions below are AVX only
6688 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6689 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6690 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6691 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6692 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6693 Sched<[WriteVecLogic]>, VEX;
6694 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6695 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6696 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6697 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6700 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6701 let ExeDomain = SSEPackedSingle in {
6702 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6703 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6706 let ExeDomain = SSEPackedDouble in {
6707 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6708 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6713 //===----------------------------------------------------------------------===//
6714 // SSE4.1 - Misc Instructions
6715 //===----------------------------------------------------------------------===//
6717 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6718 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6719 "popcnt{w}\t{$src, $dst|$dst, $src}",
6720 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6721 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6723 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6724 "popcnt{w}\t{$src, $dst|$dst, $src}",
6725 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6726 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6727 Sched<[WriteFAddLd]>, OpSize16, XS;
6729 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6730 "popcnt{l}\t{$src, $dst|$dst, $src}",
6731 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6732 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6735 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6736 "popcnt{l}\t{$src, $dst|$dst, $src}",
6737 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6738 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6739 Sched<[WriteFAddLd]>, OpSize32, XS;
6741 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6742 "popcnt{q}\t{$src, $dst|$dst, $src}",
6743 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6744 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6745 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6746 "popcnt{q}\t{$src, $dst|$dst, $src}",
6747 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6748 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6749 Sched<[WriteFAddLd]>, XS;
6754 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6755 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6756 Intrinsic IntId128, PatFrag ld_frag,
6757 X86FoldableSchedWrite Sched> {
6758 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6760 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6761 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6763 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6765 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6767 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6768 Sched<[Sched.Folded]>;
6771 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6772 // model, although the naming is misleading.
6773 let Predicates = [HasAVX] in
6774 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6775 int_x86_sse41_phminposuw, loadv2i64,
6777 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6778 int_x86_sse41_phminposuw, memopv2i64,
6781 /// SS48I_binop_rm - Simple SSE41 binary operator.
6782 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6783 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6784 X86MemOperand x86memop, bit Is2Addr = 1,
6785 OpndItins itins = SSE_INTALU_ITINS_P> {
6786 let isCommutable = 1 in
6787 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6788 (ins RC:$src1, RC:$src2),
6790 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6791 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6792 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6793 Sched<[itins.Sched]>;
6794 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6795 (ins RC:$src1, x86memop:$src2),
6797 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6798 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6800 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6801 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6804 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6806 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6807 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6808 PatFrag memop_frag, X86MemOperand x86memop,
6810 bit IsCommutable = 0, bit Is2Addr = 1> {
6811 let isCommutable = IsCommutable in
6812 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6813 (ins RC:$src1, RC:$src2),
6815 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6816 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6817 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6818 Sched<[itins.Sched]>;
6819 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6820 (ins RC:$src1, x86memop:$src2),
6822 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6823 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6824 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6825 (bitconvert (memop_frag addr:$src2)))))]>,
6826 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6829 let Predicates = [HasAVX, NoVLX] in {
6830 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", smin, v16i8, VR128,
6831 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6833 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", smin, v4i32, VR128,
6834 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6836 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", umin, v4i32, VR128,
6837 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6839 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", umin, v8i16, VR128,
6840 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6842 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v16i8, VR128,
6843 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6845 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v4i32, VR128,
6846 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6848 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", umax, v4i32, VR128,
6849 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6851 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v8i16, VR128,
6852 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6854 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6855 VR128, loadv2i64, i128mem,
6856 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6859 let Predicates = [HasAVX2, NoVLX] in {
6860 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", smin, v32i8, VR256,
6861 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6863 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", smin, v8i32, VR256,
6864 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6866 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", umin, v8i32, VR256,
6867 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6869 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", umin, v16i16, VR256,
6870 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6872 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v32i8, VR256,
6873 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6875 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v8i32, VR256,
6876 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6878 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", umax, v8i32, VR256,
6879 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6881 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v16i16, VR256,
6882 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6884 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6885 VR256, loadv4i64, i256mem,
6886 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6889 let Constraints = "$src1 = $dst" in {
6890 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", smin, v16i8, VR128,
6891 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6892 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", smin, v4i32, VR128,
6893 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6894 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", umin, v4i32, VR128,
6895 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6896 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", umin, v8i16, VR128,
6897 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6898 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", smax, v16i8, VR128,
6899 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6900 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", smax, v4i32, VR128,
6901 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6902 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", umax, v4i32, VR128,
6903 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6904 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", umax, v8i16, VR128,
6905 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6906 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6907 VR128, memopv2i64, i128mem,
6908 SSE_INTMUL_ITINS_P, 1>;
6911 let Predicates = [HasAVX, NoVLX] in {
6912 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6913 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6915 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6916 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6919 let Predicates = [HasAVX2] in {
6920 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6921 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6923 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6924 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6928 let Constraints = "$src1 = $dst" in {
6929 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6930 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6931 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6932 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6935 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6936 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6937 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6938 X86MemOperand x86memop, bit Is2Addr = 1,
6939 OpndItins itins = DEFAULT_ITINS> {
6940 let isCommutable = 1 in
6941 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6942 (ins RC:$src1, RC:$src2, u8imm:$src3),
6944 !strconcat(OpcodeStr,
6945 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6946 !strconcat(OpcodeStr,
6947 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6948 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6949 Sched<[itins.Sched]>;
6950 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6951 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6953 !strconcat(OpcodeStr,
6954 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6955 !strconcat(OpcodeStr,
6956 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6959 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6960 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6963 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6964 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6965 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6966 X86MemOperand x86memop, bit Is2Addr = 1,
6967 OpndItins itins = DEFAULT_ITINS> {
6968 let isCommutable = 1 in
6969 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6970 (ins RC:$src1, RC:$src2, u8imm:$src3),
6972 !strconcat(OpcodeStr,
6973 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6974 !strconcat(OpcodeStr,
6975 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6976 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
6977 itins.rr>, Sched<[itins.Sched]>;
6978 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6979 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6981 !strconcat(OpcodeStr,
6982 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6983 !strconcat(OpcodeStr,
6984 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6986 (OpVT (OpNode RC:$src1,
6987 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
6988 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6991 let Predicates = [HasAVX] in {
6992 let isCommutable = 0 in {
6993 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6994 VR128, loadv2i64, i128mem, 0,
6995 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
6998 let ExeDomain = SSEPackedSingle in {
6999 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
7000 VR128, loadv4f32, f128mem, 0,
7001 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7002 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
7003 VR256, loadv8f32, f256mem, 0,
7004 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7006 let ExeDomain = SSEPackedDouble in {
7007 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
7008 VR128, loadv2f64, f128mem, 0,
7009 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7010 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
7011 VR256, loadv4f64, f256mem, 0,
7012 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7014 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
7015 VR128, loadv2i64, i128mem, 0,
7016 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7018 let ExeDomain = SSEPackedSingle in
7019 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7020 VR128, loadv4f32, f128mem, 0,
7021 SSE_DPPS_ITINS>, VEX_4V;
7022 let ExeDomain = SSEPackedDouble in
7023 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7024 VR128, loadv2f64, f128mem, 0,
7025 SSE_DPPS_ITINS>, VEX_4V;
7026 let ExeDomain = SSEPackedSingle in
7027 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7028 VR256, loadv8f32, i256mem, 0,
7029 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7032 let Predicates = [HasAVX2] in {
7033 let isCommutable = 0 in {
7034 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7035 VR256, loadv4i64, i256mem, 0,
7036 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7038 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
7039 VR256, loadv4i64, i256mem, 0,
7040 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7043 let Constraints = "$src1 = $dst" in {
7044 let isCommutable = 0 in {
7045 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7046 VR128, memopv2i64, i128mem,
7047 1, SSE_MPSADBW_ITINS>;
7049 let ExeDomain = SSEPackedSingle in
7050 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7051 VR128, memopv4f32, f128mem,
7052 1, SSE_INTALU_ITINS_FBLEND_P>;
7053 let ExeDomain = SSEPackedDouble in
7054 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7055 VR128, memopv2f64, f128mem,
7056 1, SSE_INTALU_ITINS_FBLEND_P>;
7057 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7058 VR128, memopv2i64, i128mem,
7059 1, SSE_INTALU_ITINS_BLEND_P>;
7060 let ExeDomain = SSEPackedSingle in
7061 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7062 VR128, memopv4f32, f128mem, 1,
7064 let ExeDomain = SSEPackedDouble in
7065 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7066 VR128, memopv2f64, f128mem, 1,
7070 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7071 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7072 RegisterClass RC, X86MemOperand x86memop,
7073 PatFrag mem_frag, Intrinsic IntId,
7074 X86FoldableSchedWrite Sched> {
7075 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7076 (ins RC:$src1, RC:$src2, RC:$src3),
7077 !strconcat(OpcodeStr,
7078 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7079 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7080 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7083 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7084 (ins RC:$src1, x86memop:$src2, RC:$src3),
7085 !strconcat(OpcodeStr,
7086 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7088 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7090 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7091 Sched<[Sched.Folded, ReadAfterLd]>;
7094 let Predicates = [HasAVX] in {
7095 let ExeDomain = SSEPackedDouble in {
7096 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7097 loadv2f64, int_x86_sse41_blendvpd,
7099 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7100 loadv4f64, int_x86_avx_blendv_pd_256,
7101 WriteFVarBlend>, VEX_L;
7102 } // ExeDomain = SSEPackedDouble
7103 let ExeDomain = SSEPackedSingle in {
7104 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7105 loadv4f32, int_x86_sse41_blendvps,
7107 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7108 loadv8f32, int_x86_avx_blendv_ps_256,
7109 WriteFVarBlend>, VEX_L;
7110 } // ExeDomain = SSEPackedSingle
7111 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7112 loadv2i64, int_x86_sse41_pblendvb,
7116 let Predicates = [HasAVX2] in {
7117 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7118 loadv4i64, int_x86_avx2_pblendvb,
7119 WriteVarBlend>, VEX_L;
7122 let Predicates = [HasAVX] in {
7123 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7124 (v16i8 VR128:$src2))),
7125 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7126 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7127 (v4i32 VR128:$src2))),
7128 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7129 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7130 (v4f32 VR128:$src2))),
7131 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7132 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7133 (v2i64 VR128:$src2))),
7134 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7135 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7136 (v2f64 VR128:$src2))),
7137 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7138 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7139 (v8i32 VR256:$src2))),
7140 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7141 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7142 (v8f32 VR256:$src2))),
7143 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7144 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7145 (v4i64 VR256:$src2))),
7146 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7147 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7148 (v4f64 VR256:$src2))),
7149 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7152 let Predicates = [HasAVX2] in {
7153 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7154 (v32i8 VR256:$src2))),
7155 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7159 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7160 // on targets where they have equal performance. These were changed to use
7161 // blends because blends have better throughput on SandyBridge and Haswell, but
7162 // movs[s/d] are 1-2 byte shorter instructions.
7163 let Predicates = [UseAVX] in {
7164 let AddedComplexity = 15 in {
7165 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7166 // MOVS{S,D} to the lower bits.
7167 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7168 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7169 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7170 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7171 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7172 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7173 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7174 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7176 // Move low f32 and clear high bits.
7177 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7178 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7180 // Move low f64 and clear high bits.
7181 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7182 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7185 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7186 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7187 (SUBREG_TO_REG (i32 0),
7188 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7190 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7191 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7192 (SUBREG_TO_REG (i64 0),
7193 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7196 // These will incur an FP/int domain crossing penalty, but it may be the only
7197 // way without AVX2. Do not add any complexity because we may be able to match
7198 // more optimal patterns defined earlier in this file.
7199 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7200 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7201 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7202 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7205 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7206 // on targets where they have equal performance. These were changed to use
7207 // blends because blends have better throughput on SandyBridge and Haswell, but
7208 // movs[s/d] are 1-2 byte shorter instructions.
7209 let Predicates = [UseSSE41] in {
7210 // With SSE41 we can use blends for these patterns.
7211 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7212 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7213 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7214 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7215 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7216 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7220 /// SS41I_ternary_int - SSE 4.1 ternary operator
7221 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7222 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7223 X86MemOperand x86memop, Intrinsic IntId,
7224 OpndItins itins = DEFAULT_ITINS> {
7225 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7226 (ins VR128:$src1, VR128:$src2),
7227 !strconcat(OpcodeStr,
7228 "\t{$src2, $dst|$dst, $src2}"),
7229 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7230 itins.rr>, Sched<[itins.Sched]>;
7232 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7233 (ins VR128:$src1, x86memop:$src2),
7234 !strconcat(OpcodeStr,
7235 "\t{$src2, $dst|$dst, $src2}"),
7238 (bitconvert (mem_frag addr:$src2)), XMM0))],
7239 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7243 let ExeDomain = SSEPackedDouble in
7244 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7245 int_x86_sse41_blendvpd,
7246 DEFAULT_ITINS_FBLENDSCHED>;
7247 let ExeDomain = SSEPackedSingle in
7248 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7249 int_x86_sse41_blendvps,
7250 DEFAULT_ITINS_FBLENDSCHED>;
7251 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7252 int_x86_sse41_pblendvb,
7253 DEFAULT_ITINS_VARBLENDSCHED>;
7255 // Aliases with the implicit xmm0 argument
7256 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7257 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7258 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7259 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7260 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7261 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7262 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7263 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7264 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7265 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7266 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7267 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7269 let Predicates = [UseSSE41] in {
7270 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7271 (v16i8 VR128:$src2))),
7272 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7273 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7274 (v4i32 VR128:$src2))),
7275 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7276 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7277 (v4f32 VR128:$src2))),
7278 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7279 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7280 (v2i64 VR128:$src2))),
7281 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7282 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7283 (v2f64 VR128:$src2))),
7284 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7287 let SchedRW = [WriteLoad] in {
7288 let Predicates = [HasAVX] in
7289 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7290 "vmovntdqa\t{$src, $dst|$dst, $src}",
7291 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7293 let Predicates = [HasAVX2] in
7294 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7295 "vmovntdqa\t{$src, $dst|$dst, $src}",
7296 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7298 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7299 "movntdqa\t{$src, $dst|$dst, $src}",
7300 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7303 //===----------------------------------------------------------------------===//
7304 // SSE4.2 - Compare Instructions
7305 //===----------------------------------------------------------------------===//
7307 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7308 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7309 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7310 X86MemOperand x86memop, bit Is2Addr = 1> {
7311 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7312 (ins RC:$src1, RC:$src2),
7314 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7315 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7316 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7317 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7318 (ins RC:$src1, x86memop:$src2),
7320 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7323 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7326 let Predicates = [HasAVX] in
7327 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7328 loadv2i64, i128mem, 0>, VEX_4V;
7330 let Predicates = [HasAVX2] in
7331 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7332 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7334 let Constraints = "$src1 = $dst" in
7335 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7336 memopv2i64, i128mem>;
7338 //===----------------------------------------------------------------------===//
7339 // SSE4.2 - String/text Processing Instructions
7340 //===----------------------------------------------------------------------===//
7342 // Packed Compare Implicit Length Strings, Return Mask
7343 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7344 def REG : PseudoI<(outs VR128:$dst),
7345 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7346 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7348 def MEM : PseudoI<(outs VR128:$dst),
7349 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7350 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7351 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7354 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7355 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7357 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7358 Requires<[UseSSE42]>;
7361 multiclass pcmpistrm_SS42AI<string asm> {
7362 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7363 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7364 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7365 []>, Sched<[WritePCmpIStrM]>;
7367 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7368 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7369 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7370 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7373 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7374 let Predicates = [HasAVX] in
7375 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7376 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7379 // Packed Compare Explicit Length Strings, Return Mask
7380 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7381 def REG : PseudoI<(outs VR128:$dst),
7382 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7383 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7384 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7385 def MEM : PseudoI<(outs VR128:$dst),
7386 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7387 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7388 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7391 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7392 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7394 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7395 Requires<[UseSSE42]>;
7398 multiclass SS42AI_pcmpestrm<string asm> {
7399 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7400 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7401 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7402 []>, Sched<[WritePCmpEStrM]>;
7404 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7405 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7406 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7407 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7410 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7411 let Predicates = [HasAVX] in
7412 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7413 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7416 // Packed Compare Implicit Length Strings, Return Index
7417 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7418 def REG : PseudoI<(outs GR32:$dst),
7419 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7420 [(set GR32:$dst, EFLAGS,
7421 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7422 def MEM : PseudoI<(outs GR32:$dst),
7423 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7424 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7425 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7428 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7429 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7431 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7432 Requires<[UseSSE42]>;
7435 multiclass SS42AI_pcmpistri<string asm> {
7436 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7437 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7438 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7439 []>, Sched<[WritePCmpIStrI]>;
7441 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7442 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7443 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7444 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7447 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7448 let Predicates = [HasAVX] in
7449 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7450 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7453 // Packed Compare Explicit Length Strings, Return Index
7454 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7455 def REG : PseudoI<(outs GR32:$dst),
7456 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7457 [(set GR32:$dst, EFLAGS,
7458 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7459 def MEM : PseudoI<(outs GR32:$dst),
7460 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7461 [(set GR32:$dst, EFLAGS,
7462 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7466 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7467 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7469 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7470 Requires<[UseSSE42]>;
7473 multiclass SS42AI_pcmpestri<string asm> {
7474 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7475 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7476 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7477 []>, Sched<[WritePCmpEStrI]>;
7479 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7480 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7481 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7482 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7485 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7486 let Predicates = [HasAVX] in
7487 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7488 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7491 //===----------------------------------------------------------------------===//
7492 // SSE4.2 - CRC Instructions
7493 //===----------------------------------------------------------------------===//
7495 // No CRC instructions have AVX equivalents
7497 // crc intrinsic instruction
7498 // This set of instructions are only rm, the only difference is the size
7500 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7501 RegisterClass RCIn, SDPatternOperator Int> :
7502 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7503 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7504 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7507 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7508 X86MemOperand x86memop, SDPatternOperator Int> :
7509 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7510 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7511 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7512 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7514 let Constraints = "$src1 = $dst" in {
7515 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7516 int_x86_sse42_crc32_32_8>;
7517 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7518 int_x86_sse42_crc32_32_8>;
7519 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7520 int_x86_sse42_crc32_32_16>, OpSize16;
7521 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7522 int_x86_sse42_crc32_32_16>, OpSize16;
7523 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7524 int_x86_sse42_crc32_32_32>, OpSize32;
7525 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7526 int_x86_sse42_crc32_32_32>, OpSize32;
7527 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7528 int_x86_sse42_crc32_64_64>, REX_W;
7529 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7530 int_x86_sse42_crc32_64_64>, REX_W;
7531 let hasSideEffects = 0 in {
7533 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7535 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7540 //===----------------------------------------------------------------------===//
7541 // SHA-NI Instructions
7542 //===----------------------------------------------------------------------===//
7544 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7546 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7547 (ins VR128:$src1, VR128:$src2),
7548 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7550 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7551 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7553 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7554 (ins VR128:$src1, i128mem:$src2),
7555 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7557 (set VR128:$dst, (IntId VR128:$src1,
7558 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7559 (set VR128:$dst, (IntId VR128:$src1,
7560 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7563 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7564 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7565 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7566 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7568 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7569 (i8 imm:$src3)))]>, TA;
7570 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7571 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7572 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7574 (int_x86_sha1rnds4 VR128:$src1,
7575 (bc_v4i32 (memopv2i64 addr:$src2)),
7576 (i8 imm:$src3)))]>, TA;
7578 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7579 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7580 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7583 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7585 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7586 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7589 // Aliases with explicit %xmm0
7590 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7591 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7592 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7593 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7595 //===----------------------------------------------------------------------===//
7596 // AES-NI Instructions
7597 //===----------------------------------------------------------------------===//
7599 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7600 PatFrag ld_frag, bit Is2Addr = 1> {
7601 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7602 (ins VR128:$src1, VR128:$src2),
7604 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7605 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7606 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7607 Sched<[WriteAESDecEnc]>;
7608 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7609 (ins VR128:$src1, i128mem:$src2),
7611 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7612 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7614 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7615 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7618 // Perform One Round of an AES Encryption/Decryption Flow
7619 let Predicates = [HasAVX, HasAES] in {
7620 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7621 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7622 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7623 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7624 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7625 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7626 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7627 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7630 let Constraints = "$src1 = $dst" in {
7631 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7632 int_x86_aesni_aesenc, memopv2i64>;
7633 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7634 int_x86_aesni_aesenclast, memopv2i64>;
7635 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7636 int_x86_aesni_aesdec, memopv2i64>;
7637 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7638 int_x86_aesni_aesdeclast, memopv2i64>;
7641 // Perform the AES InvMixColumn Transformation
7642 let Predicates = [HasAVX, HasAES] in {
7643 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7645 "vaesimc\t{$src1, $dst|$dst, $src1}",
7647 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7649 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7650 (ins i128mem:$src1),
7651 "vaesimc\t{$src1, $dst|$dst, $src1}",
7652 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7653 Sched<[WriteAESIMCLd]>, VEX;
7655 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7657 "aesimc\t{$src1, $dst|$dst, $src1}",
7659 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7660 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7661 (ins i128mem:$src1),
7662 "aesimc\t{$src1, $dst|$dst, $src1}",
7663 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7664 Sched<[WriteAESIMCLd]>;
7666 // AES Round Key Generation Assist
7667 let Predicates = [HasAVX, HasAES] in {
7668 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7669 (ins VR128:$src1, u8imm:$src2),
7670 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7672 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7673 Sched<[WriteAESKeyGen]>, VEX;
7674 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7675 (ins i128mem:$src1, u8imm:$src2),
7676 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7678 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7679 Sched<[WriteAESKeyGenLd]>, VEX;
7681 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7682 (ins VR128:$src1, u8imm:$src2),
7683 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7685 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7686 Sched<[WriteAESKeyGen]>;
7687 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7688 (ins i128mem:$src1, u8imm:$src2),
7689 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7691 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7692 Sched<[WriteAESKeyGenLd]>;
7694 //===----------------------------------------------------------------------===//
7695 // PCLMUL Instructions
7696 //===----------------------------------------------------------------------===//
7698 // AVX carry-less Multiplication instructions
7699 let isCommutable = 1 in
7700 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7701 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7702 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7704 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7705 Sched<[WriteCLMul]>;
7707 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7708 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7709 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7710 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7711 (loadv2i64 addr:$src2), imm:$src3))]>,
7712 Sched<[WriteCLMulLd, ReadAfterLd]>;
7714 // Carry-less Multiplication instructions
7715 let Constraints = "$src1 = $dst" in {
7716 let isCommutable = 1 in
7717 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7718 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7719 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7721 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7722 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7724 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7725 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7726 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7727 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7728 (memopv2i64 addr:$src2), imm:$src3))],
7729 IIC_SSE_PCLMULQDQ_RM>,
7730 Sched<[WriteCLMulLd, ReadAfterLd]>;
7731 } // Constraints = "$src1 = $dst"
7734 multiclass pclmul_alias<string asm, int immop> {
7735 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7736 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7738 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7739 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7741 def : InstAlias<!strconcat("vpclmul", asm,
7742 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7743 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7746 def : InstAlias<!strconcat("vpclmul", asm,
7747 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7748 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7751 defm : pclmul_alias<"hqhq", 0x11>;
7752 defm : pclmul_alias<"hqlq", 0x01>;
7753 defm : pclmul_alias<"lqhq", 0x10>;
7754 defm : pclmul_alias<"lqlq", 0x00>;
7756 //===----------------------------------------------------------------------===//
7757 // SSE4A Instructions
7758 //===----------------------------------------------------------------------===//
7760 let Predicates = [HasSSE4A] in {
7762 let Constraints = "$src = $dst" in {
7763 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7764 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7765 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7766 [(set VR128:$dst, (X86extrqi VR128:$src, imm:$len,
7768 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7769 (ins VR128:$src, VR128:$mask),
7770 "extrq\t{$mask, $src|$src, $mask}",
7771 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7772 VR128:$mask))]>, PD;
7774 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7775 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7776 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7777 [(set VR128:$dst, (X86insertqi VR128:$src, VR128:$src2,
7778 imm:$len, imm:$idx))]>, XD;
7779 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7780 (ins VR128:$src, VR128:$mask),
7781 "insertq\t{$mask, $src|$src, $mask}",
7782 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7783 VR128:$mask))]>, XD;
7786 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7787 "movntss\t{$src, $dst|$dst, $src}",
7788 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7790 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7791 "movntsd\t{$src, $dst|$dst, $src}",
7792 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7795 //===----------------------------------------------------------------------===//
7797 //===----------------------------------------------------------------------===//
7799 //===----------------------------------------------------------------------===//
7800 // VBROADCAST - Load from memory and broadcast to all elements of the
7801 // destination operand
7803 class avx_broadcast_rm<bits<8> opc, string OpcodeStr, RegisterClass RC,
7804 X86MemOperand x86memop, ValueType VT,
7805 PatFrag ld_frag, SchedWrite Sched> :
7806 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7807 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7808 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7809 Sched<[Sched]>, VEX {
7813 // AVX2 adds register forms
7814 class avx2_broadcast_rr<bits<8> opc, string OpcodeStr, RegisterClass RC,
7815 ValueType ResVT, ValueType OpVT, SchedWrite Sched> :
7816 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7817 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7818 [(set RC:$dst, (ResVT (X86VBroadcast (OpVT VR128:$src))))]>,
7819 Sched<[Sched]>, VEX;
7821 let ExeDomain = SSEPackedSingle in {
7822 def VBROADCASTSSrm : avx_broadcast_rm<0x18, "vbroadcastss", VR128,
7823 f32mem, v4f32, loadf32, WriteLoad>;
7824 def VBROADCASTSSYrm : avx_broadcast_rm<0x18, "vbroadcastss", VR256,
7825 f32mem, v8f32, loadf32,
7826 WriteFShuffleLd>, VEX_L;
7828 let ExeDomain = SSEPackedDouble in
7829 def VBROADCASTSDYrm : avx_broadcast_rm<0x19, "vbroadcastsd", VR256, f64mem,
7830 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7832 let ExeDomain = SSEPackedSingle in {
7833 def VBROADCASTSSrr : avx2_broadcast_rr<0x18, "vbroadcastss", VR128,
7834 v4f32, v4f32, WriteFShuffle>;
7835 def VBROADCASTSSYrr : avx2_broadcast_rr<0x18, "vbroadcastss", VR256,
7836 v8f32, v4f32, WriteFShuffle256>, VEX_L;
7838 let ExeDomain = SSEPackedDouble in
7839 def VBROADCASTSDYrr : avx2_broadcast_rr<0x19, "vbroadcastsd", VR256,
7840 v4f64, v2f64, WriteFShuffle256>, VEX_L;
7842 let mayLoad = 1, Predicates = [HasAVX2] in
7843 def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
7845 "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
7846 Sched<[WriteLoad]>, VEX, VEX_L;
7848 def VBROADCASTF128 : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
7850 "vbroadcastf128\t{$src, $dst|$dst, $src}",
7852 (int_x86_avx_vbroadcastf128_pd_256 addr:$src))]>,
7853 Sched<[WriteFShuffleLd]>, VEX, VEX_L;
7855 let Predicates = [HasAVX] in
7856 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7857 (VBROADCASTF128 addr:$src)>;
7860 //===----------------------------------------------------------------------===//
7861 // VINSERTF128 - Insert packed floating-point values
7863 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7864 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7865 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7866 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7867 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7869 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7870 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7871 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7872 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7875 let Predicates = [HasAVX, NoVLX] in {
7876 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7878 (VINSERTF128rr VR256:$src1, VR128:$src2,
7879 (INSERT_get_vinsert128_imm VR256:$ins))>;
7880 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7882 (VINSERTF128rr VR256:$src1, VR128:$src2,
7883 (INSERT_get_vinsert128_imm VR256:$ins))>;
7885 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7887 (VINSERTF128rm VR256:$src1, addr:$src2,
7888 (INSERT_get_vinsert128_imm VR256:$ins))>;
7889 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7891 (VINSERTF128rm VR256:$src1, addr:$src2,
7892 (INSERT_get_vinsert128_imm VR256:$ins))>;
7895 let Predicates = [HasAVX1Only] in {
7896 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7898 (VINSERTF128rr VR256:$src1, VR128:$src2,
7899 (INSERT_get_vinsert128_imm VR256:$ins))>;
7900 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7902 (VINSERTF128rr VR256:$src1, VR128:$src2,
7903 (INSERT_get_vinsert128_imm VR256:$ins))>;
7904 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7906 (VINSERTF128rr VR256:$src1, VR128:$src2,
7907 (INSERT_get_vinsert128_imm VR256:$ins))>;
7908 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7910 (VINSERTF128rr VR256:$src1, VR128:$src2,
7911 (INSERT_get_vinsert128_imm VR256:$ins))>;
7913 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7915 (VINSERTF128rm VR256:$src1, addr:$src2,
7916 (INSERT_get_vinsert128_imm VR256:$ins))>;
7917 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7918 (bc_v4i32 (loadv2i64 addr:$src2)),
7920 (VINSERTF128rm VR256:$src1, addr:$src2,
7921 (INSERT_get_vinsert128_imm VR256:$ins))>;
7922 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7923 (bc_v16i8 (loadv2i64 addr:$src2)),
7925 (VINSERTF128rm VR256:$src1, addr:$src2,
7926 (INSERT_get_vinsert128_imm VR256:$ins))>;
7927 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7928 (bc_v8i16 (loadv2i64 addr:$src2)),
7930 (VINSERTF128rm VR256:$src1, addr:$src2,
7931 (INSERT_get_vinsert128_imm VR256:$ins))>;
7934 //===----------------------------------------------------------------------===//
7935 // VEXTRACTF128 - Extract packed floating-point values
7937 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7938 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7939 (ins VR256:$src1, u8imm:$src2),
7940 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7941 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7943 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7944 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7945 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7946 []>, Sched<[WriteStore]>, VEX, VEX_L;
7950 let Predicates = [HasAVX] in {
7951 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7952 (v4f32 (VEXTRACTF128rr
7953 (v8f32 VR256:$src1),
7954 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7955 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7956 (v2f64 (VEXTRACTF128rr
7957 (v4f64 VR256:$src1),
7958 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7960 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7961 (iPTR imm))), addr:$dst),
7962 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7963 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7964 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7965 (iPTR imm))), addr:$dst),
7966 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7967 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7970 let Predicates = [HasAVX1Only] in {
7971 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7972 (v2i64 (VEXTRACTF128rr
7973 (v4i64 VR256:$src1),
7974 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7975 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7976 (v4i32 (VEXTRACTF128rr
7977 (v8i32 VR256:$src1),
7978 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7979 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7980 (v8i16 (VEXTRACTF128rr
7981 (v16i16 VR256:$src1),
7982 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7983 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7984 (v16i8 (VEXTRACTF128rr
7985 (v32i8 VR256:$src1),
7986 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7988 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7989 (iPTR imm))), addr:$dst),
7990 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7991 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7992 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7993 (iPTR imm))), addr:$dst),
7994 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7995 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7996 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7997 (iPTR imm))), addr:$dst),
7998 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7999 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8000 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8001 (iPTR imm))), addr:$dst),
8002 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8003 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8006 //===----------------------------------------------------------------------===//
8007 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8009 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8010 Intrinsic IntLd, Intrinsic IntLd256,
8011 Intrinsic IntSt, Intrinsic IntSt256> {
8012 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8013 (ins VR128:$src1, f128mem:$src2),
8014 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8015 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8017 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8018 (ins VR256:$src1, f256mem:$src2),
8019 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8020 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8022 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8023 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8024 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8025 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8026 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8027 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8028 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8029 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8032 let ExeDomain = SSEPackedSingle in
8033 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8034 int_x86_avx_maskload_ps,
8035 int_x86_avx_maskload_ps_256,
8036 int_x86_avx_maskstore_ps,
8037 int_x86_avx_maskstore_ps_256>;
8038 let ExeDomain = SSEPackedDouble in
8039 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8040 int_x86_avx_maskload_pd,
8041 int_x86_avx_maskload_pd_256,
8042 int_x86_avx_maskstore_pd,
8043 int_x86_avx_maskstore_pd_256>;
8045 //===----------------------------------------------------------------------===//
8046 // VPERMIL - Permute Single and Double Floating-Point Values
8048 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8049 RegisterClass RC, X86MemOperand x86memop_f,
8050 X86MemOperand x86memop_i, PatFrag i_frag,
8051 Intrinsic IntVar, ValueType vt> {
8052 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8053 (ins RC:$src1, RC:$src2),
8054 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8055 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8056 Sched<[WriteFShuffle]>;
8057 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8058 (ins RC:$src1, x86memop_i:$src2),
8059 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8060 [(set RC:$dst, (IntVar RC:$src1,
8061 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8062 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8064 let Predicates = [HasAVX, NoVLX] in {
8065 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8066 (ins RC:$src1, u8imm:$src2),
8067 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8068 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8069 Sched<[WriteFShuffle]>;
8070 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8071 (ins x86memop_f:$src1, u8imm:$src2),
8072 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8074 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8075 Sched<[WriteFShuffleLd]>;
8076 }// Predicates = [HasAVX, NoVLX]
8079 let ExeDomain = SSEPackedSingle in {
8080 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8081 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8082 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8083 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8085 let ExeDomain = SSEPackedDouble in {
8086 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8087 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8088 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8089 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8092 let Predicates = [HasAVX, NoVLX] in {
8093 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8094 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8095 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8096 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8097 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8098 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8099 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8100 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8102 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8103 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8104 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8105 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8106 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8108 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8109 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8110 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8112 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8113 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8114 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8115 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8116 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8117 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8118 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8119 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8121 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8122 (VPERMILPDri VR128:$src1, imm:$imm)>;
8123 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8124 (VPERMILPDmi addr:$src1, imm:$imm)>;
8127 //===----------------------------------------------------------------------===//
8128 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8130 let ExeDomain = SSEPackedSingle in {
8131 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8132 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8133 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8134 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8135 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8136 Sched<[WriteFShuffle]>;
8137 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8138 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8139 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8140 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8141 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8142 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8145 let Predicates = [HasAVX] in {
8146 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8147 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8148 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8149 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8150 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8153 let Predicates = [HasAVX1Only] in {
8154 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8155 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8156 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8157 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8158 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8159 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8160 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8161 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8163 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8164 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8165 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8166 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8167 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8168 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8169 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8170 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8171 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8172 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8173 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8174 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8177 //===----------------------------------------------------------------------===//
8178 // VZERO - Zero YMM registers
8180 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8181 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8182 // Zero All YMM registers
8183 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8184 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8186 // Zero Upper bits of YMM registers
8187 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8188 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8191 //===----------------------------------------------------------------------===//
8192 // Half precision conversion instructions
8193 //===----------------------------------------------------------------------===//
8194 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8195 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8196 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8197 [(set RC:$dst, (Int VR128:$src))]>,
8198 T8PD, VEX, Sched<[WriteCvtF2F]>;
8199 let hasSideEffects = 0, mayLoad = 1 in
8200 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8201 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8202 Sched<[WriteCvtF2FLd]>;
8205 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8206 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8207 (ins RC:$src1, i32u8imm:$src2),
8208 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8209 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8210 TAPD, VEX, Sched<[WriteCvtF2F]>;
8211 let hasSideEffects = 0, mayStore = 1,
8212 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8213 def mr : Ii8<0x1D, MRMDestMem, (outs),
8214 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8215 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8219 let Predicates = [HasF16C] in {
8220 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8221 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8222 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8223 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8225 // Pattern match vcvtph2ps of a scalar i64 load.
8226 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8227 (VCVTPH2PSrm addr:$src)>;
8228 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8229 (VCVTPH2PSrm addr:$src)>;
8231 def : Pat<(store (f64 (extractelt (bc_v2f64 (v8i16
8232 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8234 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8235 def : Pat<(store (i64 (extractelt (bc_v2i64 (v8i16
8236 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8238 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8239 def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
8241 (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
8244 // Patterns for matching conversions from float to half-float and vice versa.
8245 let Predicates = [HasF16C] in {
8246 def : Pat<(fp_to_f16 FR32:$src),
8247 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8248 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8250 def : Pat<(f16_to_fp GR16:$src),
8251 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8252 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8254 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8255 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8256 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8259 //===----------------------------------------------------------------------===//
8260 // AVX2 Instructions
8261 //===----------------------------------------------------------------------===//
8263 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8264 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8265 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8266 X86MemOperand x86memop> {
8267 let isCommutable = 1 in
8268 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8269 (ins RC:$src1, RC:$src2, u8imm:$src3),
8270 !strconcat(OpcodeStr,
8271 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8272 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8273 Sched<[WriteBlend]>, VEX_4V;
8274 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8275 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8276 !strconcat(OpcodeStr,
8277 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8279 (OpVT (OpNode RC:$src1,
8280 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8281 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8284 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8285 VR128, loadv2i64, i128mem>;
8286 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8287 VR256, loadv4i64, i256mem>, VEX_L;
8289 //===----------------------------------------------------------------------===//
8290 // VPBROADCAST - Load from memory and broadcast to all elements of the
8291 // destination operand
8293 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8294 X86MemOperand x86memop, PatFrag ld_frag,
8295 ValueType OpVT128, ValueType OpVT256, Predicate prd> {
8296 let Predicates = [HasAVX2, prd] in {
8297 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8298 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8300 (OpVT128 (X86VBroadcast (OpVT128 VR128:$src))))]>,
8301 Sched<[WriteShuffle]>, VEX;
8302 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8303 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8305 (OpVT128 (X86VBroadcast (ld_frag addr:$src))))]>,
8306 Sched<[WriteLoad]>, VEX;
8307 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8308 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8310 (OpVT256 (X86VBroadcast (OpVT128 VR128:$src))))]>,
8311 Sched<[WriteShuffle256]>, VEX, VEX_L;
8312 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8313 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8315 (OpVT256 (X86VBroadcast (ld_frag addr:$src))))]>,
8316 Sched<[WriteLoad]>, VEX, VEX_L;
8318 // Provide aliases for broadcast from the same register class that
8319 // automatically does the extract.
8320 def : Pat<(OpVT256 (X86VBroadcast (OpVT256 VR256:$src))),
8321 (!cast<Instruction>(NAME#"Yrr")
8322 (OpVT128 (EXTRACT_SUBREG (OpVT256 VR256:$src),sub_xmm)))>;
8326 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8327 v16i8, v32i8, NoVLX_Or_NoBWI>;
8328 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8329 v8i16, v16i16, NoVLX_Or_NoBWI>;
8330 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8331 v4i32, v8i32, NoVLX>;
8332 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8333 v2i64, v4i64, NoVLX>;
8335 let Predicates = [HasAVX2] in {
8336 // loadi16 is tricky to fold, because !isTypeDesirableForOp, justifiably.
8337 // This means we'll encounter truncated i32 loads; match that here.
8338 def : Pat<(v8i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))),
8339 (VPBROADCASTWrm addr:$src)>;
8340 def : Pat<(v16i16 (X86VBroadcast (i16 (trunc (i32 (load addr:$src)))))),
8341 (VPBROADCASTWYrm addr:$src)>;
8342 def : Pat<(v8i16 (X86VBroadcast
8343 (i16 (trunc (i32 (zextloadi16 addr:$src)))))),
8344 (VPBROADCASTWrm addr:$src)>;
8345 def : Pat<(v16i16 (X86VBroadcast
8346 (i16 (trunc (i32 (zextloadi16 addr:$src)))))),
8347 (VPBROADCASTWYrm addr:$src)>;
8349 // Provide aliases for broadcast from the same register class that
8350 // automatically does the extract.
8351 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8352 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8354 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8355 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8358 // Provide fallback in case the load node that is used in the patterns above
8359 // is used by additional users, which prevents the pattern selection.
8360 let AddedComplexity = 20 in {
8361 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8362 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8363 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8364 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8365 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8366 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8368 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8369 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8370 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8371 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8372 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8373 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8375 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8376 (VPBROADCASTBrr (COPY_TO_REGCLASS
8377 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8379 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8380 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8381 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8384 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8385 (VPBROADCASTWrr (COPY_TO_REGCLASS
8386 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8388 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8389 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8390 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8393 // The patterns for VPBROADCASTD are not needed because they would match
8394 // the exact same thing as VBROADCASTSS patterns.
8396 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8397 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8398 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8402 // AVX1 broadcast patterns
8403 let Predicates = [HasAVX1Only] in {
8404 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8405 (VBROADCASTSSYrm addr:$src)>;
8406 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8407 (VBROADCASTSDYrm addr:$src)>;
8408 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8409 (VBROADCASTSSrm addr:$src)>;
8412 let Predicates = [HasAVX] in {
8413 // Provide fallback in case the load node that is used in the patterns above
8414 // is used by additional users, which prevents the pattern selection.
8415 let AddedComplexity = 20 in {
8416 // 128bit broadcasts:
8417 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8418 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8419 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8420 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8421 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8422 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8423 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8424 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8425 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8426 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8428 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8429 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8430 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8431 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8432 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8433 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8434 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8435 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8436 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8437 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8440 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8441 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8442 def : Pat<(v2i64 (X86VBroadcast i64:$src)),
8443 (VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8446 //===----------------------------------------------------------------------===//
8447 // VPERM - Permute instructions
8450 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8451 ValueType OpVT, X86FoldableSchedWrite Sched> {
8452 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8453 (ins VR256:$src1, VR256:$src2),
8454 !strconcat(OpcodeStr,
8455 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8457 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8458 Sched<[Sched]>, VEX_4V, VEX_L;
8459 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8460 (ins VR256:$src1, i256mem:$src2),
8461 !strconcat(OpcodeStr,
8462 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8464 (OpVT (X86VPermv VR256:$src1,
8465 (bitconvert (mem_frag addr:$src2)))))]>,
8466 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8469 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8470 let ExeDomain = SSEPackedSingle in
8471 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8473 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8474 ValueType OpVT, X86FoldableSchedWrite Sched> {
8475 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8476 (ins VR256:$src1, u8imm:$src2),
8477 !strconcat(OpcodeStr,
8478 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8480 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8481 Sched<[Sched]>, VEX, VEX_L;
8482 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8483 (ins i256mem:$src1, u8imm:$src2),
8484 !strconcat(OpcodeStr,
8485 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8487 (OpVT (X86VPermi (mem_frag addr:$src1),
8488 (i8 imm:$src2))))]>,
8489 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8492 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8493 WriteShuffle256>, VEX_W;
8494 let ExeDomain = SSEPackedDouble in
8495 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8496 WriteFShuffle256>, VEX_W;
8498 //===----------------------------------------------------------------------===//
8499 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8501 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8502 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8503 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8504 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8505 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8507 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8508 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8509 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8510 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8512 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8514 let Predicates = [HasAVX2] in {
8515 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8516 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8517 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8518 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8519 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8520 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8522 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8524 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8525 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8526 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8527 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8528 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8530 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8534 //===----------------------------------------------------------------------===//
8535 // VINSERTI128 - Insert packed integer values
8537 let hasSideEffects = 0 in {
8538 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8539 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8540 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8541 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8543 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8544 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8545 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8546 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8549 let Predicates = [HasAVX2, NoVLX] in {
8550 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8552 (VINSERTI128rr VR256:$src1, VR128:$src2,
8553 (INSERT_get_vinsert128_imm VR256:$ins))>;
8554 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8556 (VINSERTI128rr VR256:$src1, VR128:$src2,
8557 (INSERT_get_vinsert128_imm VR256:$ins))>;
8558 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8560 (VINSERTI128rr VR256:$src1, VR128:$src2,
8561 (INSERT_get_vinsert128_imm VR256:$ins))>;
8562 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8564 (VINSERTI128rr VR256:$src1, VR128:$src2,
8565 (INSERT_get_vinsert128_imm VR256:$ins))>;
8567 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8569 (VINSERTI128rm VR256:$src1, addr:$src2,
8570 (INSERT_get_vinsert128_imm VR256:$ins))>;
8571 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8572 (bc_v4i32 (loadv2i64 addr:$src2)),
8574 (VINSERTI128rm VR256:$src1, addr:$src2,
8575 (INSERT_get_vinsert128_imm VR256:$ins))>;
8576 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8577 (bc_v16i8 (loadv2i64 addr:$src2)),
8579 (VINSERTI128rm VR256:$src1, addr:$src2,
8580 (INSERT_get_vinsert128_imm VR256:$ins))>;
8581 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8582 (bc_v8i16 (loadv2i64 addr:$src2)),
8584 (VINSERTI128rm VR256:$src1, addr:$src2,
8585 (INSERT_get_vinsert128_imm VR256:$ins))>;
8588 //===----------------------------------------------------------------------===//
8589 // VEXTRACTI128 - Extract packed integer values
8591 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8592 (ins VR256:$src1, u8imm:$src2),
8593 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8594 Sched<[WriteShuffle256]>, VEX, VEX_L;
8595 let hasSideEffects = 0, mayStore = 1 in
8596 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8597 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8598 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8599 Sched<[WriteStore]>, VEX, VEX_L;
8601 let Predicates = [HasAVX2] in {
8602 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8603 (v2i64 (VEXTRACTI128rr
8604 (v4i64 VR256:$src1),
8605 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8606 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8607 (v4i32 (VEXTRACTI128rr
8608 (v8i32 VR256:$src1),
8609 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8610 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8611 (v8i16 (VEXTRACTI128rr
8612 (v16i16 VR256:$src1),
8613 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8614 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8615 (v16i8 (VEXTRACTI128rr
8616 (v32i8 VR256:$src1),
8617 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8619 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8620 (iPTR imm))), addr:$dst),
8621 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8622 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8623 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8624 (iPTR imm))), addr:$dst),
8625 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8626 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8627 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8628 (iPTR imm))), addr:$dst),
8629 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8630 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8631 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8632 (iPTR imm))), addr:$dst),
8633 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8634 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8637 //===----------------------------------------------------------------------===//
8638 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8640 multiclass avx2_pmovmask<string OpcodeStr,
8641 Intrinsic IntLd128, Intrinsic IntLd256,
8642 Intrinsic IntSt128, Intrinsic IntSt256> {
8643 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8644 (ins VR128:$src1, i128mem:$src2),
8645 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8646 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8647 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8648 (ins VR256:$src1, i256mem:$src2),
8649 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8650 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8652 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8653 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8654 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8655 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8656 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8657 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8658 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8659 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8662 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8663 int_x86_avx2_maskload_d,
8664 int_x86_avx2_maskload_d_256,
8665 int_x86_avx2_maskstore_d,
8666 int_x86_avx2_maskstore_d_256>;
8667 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8668 int_x86_avx2_maskload_q,
8669 int_x86_avx2_maskload_q_256,
8670 int_x86_avx2_maskstore_q,
8671 int_x86_avx2_maskstore_q_256>, VEX_W;
8673 def: Pat<(X86mstore addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8674 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8676 def: Pat<(X86mstore addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8677 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8679 def: Pat<(X86mstore addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8680 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8682 def: Pat<(X86mstore addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8683 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8685 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8686 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8688 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8689 (bc_v8f32 (v8i32 immAllZerosV)))),
8690 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8692 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8693 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8696 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8697 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8699 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8700 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8702 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8703 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8706 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8707 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8709 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8710 (bc_v4f32 (v4i32 immAllZerosV)))),
8711 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8713 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8714 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8717 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8718 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8720 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8721 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8723 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8724 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8727 def: Pat<(X86mstore addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8728 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8730 def: Pat<(X86mstore addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8731 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8733 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8734 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8736 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8737 (v4f64 immAllZerosV))),
8738 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8740 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8741 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8744 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8745 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8747 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8748 (bc_v4i64 (v8i32 immAllZerosV)))),
8749 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8751 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8752 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8755 def: Pat<(X86mstore addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8756 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8758 def: Pat<(X86mstore addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8759 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8761 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8762 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8764 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8765 (v2f64 immAllZerosV))),
8766 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8768 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8769 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8772 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8773 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8775 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8776 (bc_v2i64 (v4i32 immAllZerosV)))),
8777 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8779 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8780 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8783 //===----------------------------------------------------------------------===//
8784 // Variable Bit Shifts
8786 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8787 ValueType vt128, ValueType vt256> {
8788 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8789 (ins VR128:$src1, VR128:$src2),
8790 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8792 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8793 VEX_4V, Sched<[WriteVarVecShift]>;
8794 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8795 (ins VR128:$src1, i128mem:$src2),
8796 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8798 (vt128 (OpNode VR128:$src1,
8799 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8800 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8801 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8802 (ins VR256:$src1, VR256:$src2),
8803 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8805 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8806 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8807 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8808 (ins VR256:$src1, i256mem:$src2),
8809 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8811 (vt256 (OpNode VR256:$src1,
8812 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8813 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8816 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8817 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8818 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8819 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8820 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8822 //===----------------------------------------------------------------------===//
8823 // VGATHER - GATHER Operations
8824 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8825 X86MemOperand memop128, X86MemOperand memop256> {
8826 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8827 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8828 !strconcat(OpcodeStr,
8829 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8831 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8832 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8833 !strconcat(OpcodeStr,
8834 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8835 []>, VEX_4VOp3, VEX_L;
8838 let mayLoad = 1, Constraints
8839 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8841 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8842 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8843 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8844 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8846 let ExeDomain = SSEPackedDouble in {
8847 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8848 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8851 let ExeDomain = SSEPackedSingle in {
8852 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8853 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8857 //===----------------------------------------------------------------------===//
8858 // Extra selection patterns for FR128, f128, f128mem
8860 // movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2.
8861 def : Pat<(store (f128 FR128:$src), addr:$dst),
8862 (MOVAPSmr addr:$dst, (COPY_TO_REGCLASS (f128 FR128:$src), VR128))>;
8864 def : Pat<(loadf128 addr:$src),
8865 (COPY_TO_REGCLASS (MOVAPSrm addr:$src), FR128)>;
8867 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
8868 def : Pat<(X86fand FR128:$src1, (loadf128 addr:$src2)),
8870 (ANDPSrm (COPY_TO_REGCLASS FR128:$src1, VR128), f128mem:$src2),
8873 def : Pat<(X86fand FR128:$src1, FR128:$src2),
8875 (ANDPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
8876 (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
8878 def : Pat<(and FR128:$src1, FR128:$src2),
8880 (ANDPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
8881 (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
8883 def : Pat<(X86for FR128:$src1, (loadf128 addr:$src2)),
8885 (ORPSrm (COPY_TO_REGCLASS FR128:$src1, VR128), f128mem:$src2),
8888 def : Pat<(X86for FR128:$src1, FR128:$src2),
8890 (ORPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
8891 (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
8893 def : Pat<(or FR128:$src1, FR128:$src2),
8895 (ORPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
8896 (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
8898 def : Pat<(X86fxor FR128:$src1, (loadf128 addr:$src2)),
8900 (XORPSrm (COPY_TO_REGCLASS FR128:$src1, VR128), f128mem:$src2),
8903 def : Pat<(X86fxor FR128:$src1, FR128:$src2),
8905 (XORPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
8906 (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;
8908 def : Pat<(xor FR128:$src1, FR128:$src2),
8910 (XORPSrr (COPY_TO_REGCLASS FR128:$src1, VR128),
8911 (COPY_TO_REGCLASS FR128:$src2, VR128)), FR128)>;