1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_DEFAULT, d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
80 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
81 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
82 string OpcodeStr, X86MemOperand x86memop,
83 list<dag> pat_rr, list<dag> pat_rm,
85 bit rr_hasSideEffects = 0> {
86 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
87 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
89 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
90 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
91 pat_rr, IIC_DEFAULT, d>;
92 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
94 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
95 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
96 pat_rm, IIC_DEFAULT, d>;
99 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
100 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
101 string asm, string SSEVer, string FPSizeStr,
102 X86MemOperand x86memop, PatFrag mem_frag,
103 Domain d, bit Is2Addr = 1> {
104 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
106 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
107 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
108 [(set RC:$dst, (!cast<Intrinsic>(
109 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
110 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
111 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
113 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
114 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
115 [(set RC:$dst, (!cast<Intrinsic>(
116 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
117 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
120 //===----------------------------------------------------------------------===//
121 // Non-instruction patterns
122 //===----------------------------------------------------------------------===//
124 // A vector extract of the first f32/f64 position is a subregister copy
125 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
126 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
127 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
128 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
130 // A 128-bit subvector extract from the first 256-bit vector position
131 // is a subregister copy that needs no instruction.
132 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
133 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
134 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
135 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
137 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
138 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
139 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
140 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
142 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
143 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
144 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
145 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
147 // A 128-bit subvector insert to the first 256-bit vector position
148 // is a subregister copy that needs no instruction.
149 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
157 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
158 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
159 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
160 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
162 // Implicitly promote a 32-bit scalar to a vector.
163 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
164 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
165 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
166 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
167 // Implicitly promote a 64-bit scalar to a vector.
168 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
169 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
170 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
171 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
173 // Bitcasts between 128-bit vector types. Return the original type since
174 // no instruction is needed for the conversion
175 let Predicates = [HasSSE2] in {
176 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
180 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
185 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
190 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
195 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
200 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
204 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
205 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
208 // Bitcasts between 256-bit vector types. Return the original type since
209 // no instruction is needed for the conversion
210 let Predicates = [HasAVX] in {
211 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
215 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
220 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
225 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
230 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
235 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
239 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
240 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
243 // Alias instructions that map fld0 to pxor for sse.
244 // This is expanded by ExpandPostRAPseudos.
245 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
247 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
248 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
249 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
250 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
253 //===----------------------------------------------------------------------===//
254 // AVX & SSE - Zero/One Vectors
255 //===----------------------------------------------------------------------===//
257 // Alias instruction that maps zero vector to pxor / xorp* for sse.
258 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
259 // swizzled by ExecutionDepsFix to pxor.
260 // We set canFoldAsLoad because this can be converted to a constant-pool
261 // load of an all-zeros value if folding it would be beneficial.
262 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
263 isPseudo = 1, neverHasSideEffects = 1 in {
264 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
267 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
268 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
269 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
270 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
271 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
272 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
275 // The same as done above but for AVX. The 256-bit ISA does not support PI,
276 // and doesn't need it because on sandy bridge the register is set to zero
277 // at the rename stage without using any execution unit, so SET0PSY
278 // and SET0PDY can be used for vector int instructions without penalty
279 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
280 // JIT implementatioan, it does not expand the instructions below like
281 // X86MCInstLower does.
282 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
283 isCodeGenOnly = 1 in {
284 let Predicates = [HasAVX] in {
285 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
286 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
287 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
288 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
290 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
291 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
295 let Predicates = [HasAVX2], AddedComplexity = 5 in {
296 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
297 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
298 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
299 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
302 // AVX has no support for 256-bit integer instructions, but since the 128-bit
303 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
304 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
305 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
306 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
308 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
309 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
310 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
312 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
313 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
314 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
316 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
317 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
318 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
320 // We set canFoldAsLoad because this can be converted to a constant-pool
321 // load of an all-ones value if folding it would be beneficial.
322 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
323 // JIT implementation, it does not expand the instructions below like
324 // X86MCInstLower does.
325 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
326 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
327 let Predicates = [HasAVX] in
328 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
329 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
330 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
331 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
332 let Predicates = [HasAVX2] in
333 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
334 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
338 //===----------------------------------------------------------------------===//
339 // SSE 1 & 2 - Move FP Scalar Instructions
341 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
342 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
343 // is used instead. Register-to-register movss/movsd is not modeled as an
344 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
345 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
346 //===----------------------------------------------------------------------===//
348 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
349 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
350 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
352 // Loading from memory automatically zeroing upper bits.
353 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
354 PatFrag mem_pat, string OpcodeStr> :
355 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
356 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
357 [(set RC:$dst, (mem_pat addr:$src))]>;
360 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
361 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
363 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
364 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
367 // For the disassembler
368 let isCodeGenOnly = 1 in {
369 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
370 (ins VR128:$src1, FR32:$src2),
371 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
373 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
374 (ins VR128:$src1, FR64:$src2),
375 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
379 let canFoldAsLoad = 1, isReMaterializable = 1 in {
380 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
382 let AddedComplexity = 20 in
383 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
387 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
388 "movss\t{$src, $dst|$dst, $src}",
389 [(store FR32:$src, addr:$dst)]>, XS, VEX, VEX_LIG;
390 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
391 "movsd\t{$src, $dst|$dst, $src}",
392 [(store FR64:$src, addr:$dst)]>, XD, VEX, VEX_LIG;
395 let Constraints = "$src1 = $dst" in {
396 def MOVSSrr : sse12_move_rr<FR32, v4f32,
397 "movss\t{$src2, $dst|$dst, $src2}">, XS;
398 def MOVSDrr : sse12_move_rr<FR64, v2f64,
399 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
401 // For the disassembler
402 let isCodeGenOnly = 1 in {
403 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
404 (ins VR128:$src1, FR32:$src2),
405 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
406 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
407 (ins VR128:$src1, FR64:$src2),
408 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
412 let canFoldAsLoad = 1, isReMaterializable = 1 in {
413 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
415 let AddedComplexity = 20 in
416 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
419 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
420 "movss\t{$src, $dst|$dst, $src}",
421 [(store FR32:$src, addr:$dst)]>;
422 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
423 "movsd\t{$src, $dst|$dst, $src}",
424 [(store FR64:$src, addr:$dst)]>;
427 let Predicates = [HasAVX] in {
428 let AddedComplexity = 15 in {
429 // Extract the low 32-bit value from one vector and insert it into another.
430 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
431 (VMOVSSrr (v4f32 VR128:$src1),
432 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
433 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
434 (VMOVSSrr (v4i32 VR128:$src1),
435 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
437 // Extract the low 64-bit value from one vector and insert it into another.
438 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
439 (VMOVSDrr (v2f64 VR128:$src1),
440 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
441 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
442 (VMOVSDrr (v2i64 VR128:$src1),
443 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
445 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
446 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
447 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
448 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
449 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
451 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
452 // MOVS{S,D} to the lower bits.
453 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
454 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
455 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
456 (VMOVSSrr (v4f32 (V_SET0)),
457 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
458 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
459 (VMOVSSrr (v4i32 (V_SET0)),
460 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
461 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
462 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
464 // Move low f32 and clear high bits.
465 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
466 (SUBREG_TO_REG (i32 0),
467 (VMOVSSrr (v4f32 (V_SET0)),
468 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
469 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
470 (SUBREG_TO_REG (i32 0),
471 (VMOVSSrr (v4i32 (V_SET0)),
472 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
475 let AddedComplexity = 20 in {
476 // MOVSSrm zeros the high parts of the register; represent this
477 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
478 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
479 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
480 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
481 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
482 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
483 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
485 // MOVSDrm zeros the high parts of the register; represent this
486 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
487 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
488 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
489 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
490 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
491 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
492 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
493 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
494 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
495 def : Pat<(v2f64 (X86vzload addr:$src)),
496 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
498 // Represent the same patterns above but in the form they appear for
500 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
501 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
502 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
503 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
504 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
505 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
506 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
507 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
508 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
510 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
511 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
512 (SUBREG_TO_REG (i32 0),
513 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
515 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
516 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
517 (SUBREG_TO_REG (i64 0),
518 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
520 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
521 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
522 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
524 // Move low f64 and clear high bits.
525 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
526 (SUBREG_TO_REG (i32 0),
527 (VMOVSDrr (v2f64 (V_SET0)),
528 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
530 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
531 (SUBREG_TO_REG (i32 0),
532 (VMOVSDrr (v2i64 (V_SET0)),
533 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
535 // Extract and store.
536 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
539 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
540 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
543 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
545 // Shuffle with VMOVSS
546 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
547 (VMOVSSrr VR128:$src1, FR32:$src2)>;
548 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
549 (VMOVSSrr (v4i32 VR128:$src1),
550 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
551 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
552 (VMOVSSrr (v4f32 VR128:$src1),
553 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
556 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
557 (SUBREG_TO_REG (i32 0),
558 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
559 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
560 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
561 (SUBREG_TO_REG (i32 0),
562 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
563 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
565 // Shuffle with VMOVSD
566 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
567 (VMOVSDrr VR128:$src1, FR64:$src2)>;
568 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
569 (VMOVSDrr (v2i64 VR128:$src1),
570 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
571 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
572 (VMOVSDrr (v2f64 VR128:$src1),
573 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
574 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
575 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
577 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
578 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
582 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
583 (SUBREG_TO_REG (i32 0),
584 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
585 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
586 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
587 (SUBREG_TO_REG (i32 0),
588 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
589 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
592 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
593 // is during lowering, where it's not possible to recognize the fold cause
594 // it has two uses through a bitcast. One use disappears at isel time and the
595 // fold opportunity reappears.
596 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
597 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
599 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
600 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
602 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
603 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
605 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
606 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
610 let Predicates = [HasSSE1] in {
611 let AddedComplexity = 15 in {
612 // Extract the low 32-bit value from one vector and insert it into another.
613 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
614 (MOVSSrr (v4f32 VR128:$src1),
615 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
616 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
617 (MOVSSrr (v4i32 VR128:$src1),
618 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
620 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
621 // MOVSS to the lower bits.
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
623 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
624 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
625 (MOVSSrr (v4f32 (V_SET0)),
626 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
627 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
628 (MOVSSrr (v4i32 (V_SET0)),
629 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
632 let AddedComplexity = 20 in {
633 // MOVSSrm zeros the high parts of the register; represent this
634 // with SUBREG_TO_REG.
635 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
636 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
637 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
638 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
639 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
640 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
643 // Extract and store.
644 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
647 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
649 // Shuffle with MOVSS
650 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
651 (MOVSSrr VR128:$src1, FR32:$src2)>;
652 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
653 (MOVSSrr (v4i32 VR128:$src1),
654 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
655 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
656 (MOVSSrr (v4f32 VR128:$src1),
657 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
660 let Predicates = [HasSSE2] in {
661 let AddedComplexity = 15 in {
662 // Extract the low 64-bit value from one vector and insert it into another.
663 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
664 (MOVSDrr (v2f64 VR128:$src1),
665 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
666 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
667 (MOVSDrr (v2i64 VR128:$src1),
668 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
670 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
671 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
672 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
673 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
674 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
676 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
677 // MOVSD to the lower bits.
678 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
679 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
682 let AddedComplexity = 20 in {
683 // MOVSDrm zeros the high parts of the register; represent this
684 // with SUBREG_TO_REG.
685 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
686 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
687 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
688 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
689 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
690 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
691 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
692 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
693 def : Pat<(v2f64 (X86vzload addr:$src)),
694 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
697 // Extract and store.
698 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
701 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
703 // Shuffle with MOVSD
704 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
705 (MOVSDrr VR128:$src1, FR64:$src2)>;
706 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
707 (MOVSDrr (v2i64 VR128:$src1),
708 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
709 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
710 (MOVSDrr (v2f64 VR128:$src1),
711 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
712 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
713 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
714 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
715 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
717 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
718 // is during lowering, where it's not possible to recognize the fold cause
719 // it has two uses through a bitcast. One use disappears at isel time and the
720 // fold opportunity reappears.
721 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
722 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
723 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
724 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
725 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
726 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
727 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
728 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
731 //===----------------------------------------------------------------------===//
732 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
733 //===----------------------------------------------------------------------===//
735 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
736 X86MemOperand x86memop, PatFrag ld_frag,
737 string asm, Domain d,
738 bit IsReMaterializable = 1> {
739 let neverHasSideEffects = 1 in
740 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
741 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], IIC_DEFAULT, d>;
742 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
743 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
744 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
745 [(set RC:$dst, (ld_frag addr:$src))], IIC_DEFAULT, d>;
748 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
749 "movaps", SSEPackedSingle>, TB, VEX;
750 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
751 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
752 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
753 "movups", SSEPackedSingle>, TB, VEX;
754 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
755 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
757 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
758 "movaps", SSEPackedSingle>, TB, VEX;
759 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
760 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
761 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
762 "movups", SSEPackedSingle>, TB, VEX;
763 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
764 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
765 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
766 "movaps", SSEPackedSingle>, TB;
767 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
768 "movapd", SSEPackedDouble>, TB, OpSize;
769 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
770 "movups", SSEPackedSingle>, TB;
771 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
772 "movupd", SSEPackedDouble, 0>, TB, OpSize;
774 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
775 "movaps\t{$src, $dst|$dst, $src}",
776 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
777 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
778 "movapd\t{$src, $dst|$dst, $src}",
779 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
780 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
781 "movups\t{$src, $dst|$dst, $src}",
782 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
783 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
784 "movupd\t{$src, $dst|$dst, $src}",
785 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
786 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
787 "movaps\t{$src, $dst|$dst, $src}",
788 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
789 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
790 "movapd\t{$src, $dst|$dst, $src}",
791 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
792 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
793 "movups\t{$src, $dst|$dst, $src}",
794 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
795 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
796 "movupd\t{$src, $dst|$dst, $src}",
797 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
800 let isCodeGenOnly = 1 in {
801 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
803 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
804 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
806 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
807 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
809 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
810 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
812 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
813 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
815 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
816 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
818 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
819 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
821 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
822 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
824 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
827 let Predicates = [HasAVX] in {
828 def : Pat<(v8i32 (X86vzmovl
829 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
830 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
831 def : Pat<(v4i64 (X86vzmovl
832 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
833 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
834 def : Pat<(v8f32 (X86vzmovl
835 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
836 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
837 def : Pat<(v4f64 (X86vzmovl
838 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
839 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
843 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
844 (VMOVUPSYmr addr:$dst, VR256:$src)>;
845 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
846 (VMOVUPDYmr addr:$dst, VR256:$src)>;
848 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
849 "movaps\t{$src, $dst|$dst, $src}",
850 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
851 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
852 "movapd\t{$src, $dst|$dst, $src}",
853 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
854 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
855 "movups\t{$src, $dst|$dst, $src}",
856 [(store (v4f32 VR128:$src), addr:$dst)]>;
857 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
858 "movupd\t{$src, $dst|$dst, $src}",
859 [(store (v2f64 VR128:$src), addr:$dst)]>;
862 let isCodeGenOnly = 1 in {
863 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
864 "movaps\t{$src, $dst|$dst, $src}", []>;
865 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
866 "movapd\t{$src, $dst|$dst, $src}", []>;
867 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
868 "movups\t{$src, $dst|$dst, $src}", []>;
869 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
870 "movupd\t{$src, $dst|$dst, $src}", []>;
873 let Predicates = [HasAVX] in {
874 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
875 (VMOVUPSmr addr:$dst, VR128:$src)>;
876 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
877 (VMOVUPDmr addr:$dst, VR128:$src)>;
880 let Predicates = [HasSSE1] in
881 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
882 (MOVUPSmr addr:$dst, VR128:$src)>;
883 let Predicates = [HasSSE2] in
884 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
885 (MOVUPDmr addr:$dst, VR128:$src)>;
887 // Use vmovaps/vmovups for AVX integer load/store.
888 let Predicates = [HasAVX] in {
889 // 128-bit load/store
890 def : Pat<(alignedloadv2i64 addr:$src),
891 (VMOVAPSrm addr:$src)>;
892 def : Pat<(loadv2i64 addr:$src),
893 (VMOVUPSrm addr:$src)>;
895 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
896 (VMOVAPSmr addr:$dst, VR128:$src)>;
897 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
898 (VMOVAPSmr addr:$dst, VR128:$src)>;
899 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
900 (VMOVAPSmr addr:$dst, VR128:$src)>;
901 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
902 (VMOVAPSmr addr:$dst, VR128:$src)>;
903 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
904 (VMOVUPSmr addr:$dst, VR128:$src)>;
905 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
906 (VMOVUPSmr addr:$dst, VR128:$src)>;
907 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
908 (VMOVUPSmr addr:$dst, VR128:$src)>;
909 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
910 (VMOVUPSmr addr:$dst, VR128:$src)>;
912 // 256-bit load/store
913 def : Pat<(alignedloadv4i64 addr:$src),
914 (VMOVAPSYrm addr:$src)>;
915 def : Pat<(loadv4i64 addr:$src),
916 (VMOVUPSYrm addr:$src)>;
917 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
918 (VMOVAPSYmr addr:$dst, VR256:$src)>;
919 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
920 (VMOVAPSYmr addr:$dst, VR256:$src)>;
921 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
922 (VMOVAPSYmr addr:$dst, VR256:$src)>;
923 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
924 (VMOVAPSYmr addr:$dst, VR256:$src)>;
925 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
926 (VMOVUPSYmr addr:$dst, VR256:$src)>;
927 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
928 (VMOVUPSYmr addr:$dst, VR256:$src)>;
929 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
930 (VMOVUPSYmr addr:$dst, VR256:$src)>;
931 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
932 (VMOVUPSYmr addr:$dst, VR256:$src)>;
935 // Use movaps / movups for SSE integer load / store (one byte shorter).
936 // The instructions selected below are then converted to MOVDQA/MOVDQU
937 // during the SSE domain pass.
938 let Predicates = [HasSSE1] in {
939 def : Pat<(alignedloadv2i64 addr:$src),
940 (MOVAPSrm addr:$src)>;
941 def : Pat<(loadv2i64 addr:$src),
942 (MOVUPSrm addr:$src)>;
944 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
945 (MOVAPSmr addr:$dst, VR128:$src)>;
946 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
947 (MOVAPSmr addr:$dst, VR128:$src)>;
948 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
949 (MOVAPSmr addr:$dst, VR128:$src)>;
950 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
951 (MOVAPSmr addr:$dst, VR128:$src)>;
952 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
953 (MOVUPSmr addr:$dst, VR128:$src)>;
954 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
955 (MOVUPSmr addr:$dst, VR128:$src)>;
956 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
957 (MOVUPSmr addr:$dst, VR128:$src)>;
958 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
959 (MOVUPSmr addr:$dst, VR128:$src)>;
962 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
963 // bits are disregarded. FIXME: Set encoding to pseudo!
964 let neverHasSideEffects = 1 in {
965 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
966 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
967 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
968 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
969 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
970 "movaps\t{$src, $dst|$dst, $src}", []>;
971 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
972 "movapd\t{$src, $dst|$dst, $src}", []>;
975 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
976 // bits are disregarded. FIXME: Set encoding to pseudo!
977 let canFoldAsLoad = 1, isReMaterializable = 1 in {
978 let isCodeGenOnly = 1 in {
979 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
980 "movaps\t{$src, $dst|$dst, $src}",
981 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
982 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
983 "movapd\t{$src, $dst|$dst, $src}",
984 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
986 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
987 "movaps\t{$src, $dst|$dst, $src}",
988 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
989 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
990 "movapd\t{$src, $dst|$dst, $src}",
991 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
994 //===----------------------------------------------------------------------===//
995 // SSE 1 & 2 - Move Low packed FP Instructions
996 //===----------------------------------------------------------------------===//
998 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
999 PatFrag mov_frag, string base_opc,
1001 def PSrm : PI<opc, MRMSrcMem,
1002 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1003 !strconcat(base_opc, "s", asm_opr),
1006 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1007 IIC_DEFAULT, SSEPackedSingle>, TB;
1009 def PDrm : PI<opc, MRMSrcMem,
1010 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1011 !strconcat(base_opc, "d", asm_opr),
1012 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
1013 (scalar_to_vector (loadf64 addr:$src2)))))],
1014 IIC_DEFAULT, SSEPackedDouble>, TB, OpSize;
1017 let AddedComplexity = 20 in {
1018 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
1019 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1021 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1022 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
1023 "\t{$src2, $dst|$dst, $src2}">;
1026 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1027 "movlps\t{$src, $dst|$dst, $src}",
1028 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1029 (iPTR 0))), addr:$dst)]>, VEX;
1030 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1031 "movlpd\t{$src, $dst|$dst, $src}",
1032 [(store (f64 (vector_extract (v2f64 VR128:$src),
1033 (iPTR 0))), addr:$dst)]>, VEX;
1034 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1035 "movlps\t{$src, $dst|$dst, $src}",
1036 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1037 (iPTR 0))), addr:$dst)]>;
1038 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1039 "movlpd\t{$src, $dst|$dst, $src}",
1040 [(store (f64 (vector_extract (v2f64 VR128:$src),
1041 (iPTR 0))), addr:$dst)]>;
1043 let Predicates = [HasAVX] in {
1044 let AddedComplexity = 20 in {
1045 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1046 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1047 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1048 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1049 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1050 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1051 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1052 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1053 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1054 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1057 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1058 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1059 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1060 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1061 VR128:$src2)), addr:$src1),
1062 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1064 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1065 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1066 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1067 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1068 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1070 // Shuffle with VMOVLPS
1071 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1072 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1073 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1074 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1075 def : Pat<(X86Movlps VR128:$src1,
1076 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1077 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1079 // Shuffle with VMOVLPD
1080 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1081 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1082 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1083 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1084 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1085 (scalar_to_vector (loadf64 addr:$src2)))),
1086 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1089 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1091 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1092 def : Pat<(store (v4i32 (X86Movlps
1093 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1094 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1095 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1097 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1098 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1100 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1103 let Predicates = [HasSSE1] in {
1104 let AddedComplexity = 20 in {
1105 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1106 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1107 (MOVLPSrm VR128:$src1, addr:$src2)>;
1108 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1109 (MOVLPSrm VR128:$src1, addr:$src2)>;
1112 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1113 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1114 (iPTR 0))), addr:$src1),
1115 (MOVLPSmr addr:$src1, VR128:$src2)>;
1116 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1117 (MOVLPSmr addr:$src1, VR128:$src2)>;
1118 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1119 VR128:$src2)), addr:$src1),
1120 (MOVLPSmr addr:$src1, VR128:$src2)>;
1122 // Shuffle with MOVLPS
1123 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1124 (MOVLPSrm VR128:$src1, addr:$src2)>;
1125 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1126 (MOVLPSrm VR128:$src1, addr:$src2)>;
1127 def : Pat<(X86Movlps VR128:$src1,
1128 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1129 (MOVLPSrm VR128:$src1, addr:$src2)>;
1130 def : Pat<(X86Movlps VR128:$src1,
1131 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1132 (MOVLPSrm VR128:$src1, addr:$src2)>;
1135 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1137 (MOVLPSmr addr:$src1, VR128:$src2)>;
1138 def : Pat<(store (v4i32 (X86Movlps
1139 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1141 (MOVLPSmr addr:$src1, VR128:$src2)>;
1144 let Predicates = [HasSSE2] in {
1145 let AddedComplexity = 20 in {
1146 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1147 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1148 (MOVLPDrm VR128:$src1, addr:$src2)>;
1149 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1150 (MOVLPDrm VR128:$src1, addr:$src2)>;
1153 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1154 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1155 (MOVLPDmr addr:$src1, VR128:$src2)>;
1156 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1157 (MOVLPDmr addr:$src1, VR128:$src2)>;
1159 // Shuffle with MOVLPD
1160 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1161 (MOVLPDrm VR128:$src1, addr:$src2)>;
1162 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1163 (MOVLPDrm VR128:$src1, addr:$src2)>;
1164 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1165 (scalar_to_vector (loadf64 addr:$src2)))),
1166 (MOVLPDrm VR128:$src1, addr:$src2)>;
1169 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1171 (MOVLPDmr addr:$src1, VR128:$src2)>;
1172 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1174 (MOVLPDmr addr:$src1, VR128:$src2)>;
1177 //===----------------------------------------------------------------------===//
1178 // SSE 1 & 2 - Move Hi packed FP Instructions
1179 //===----------------------------------------------------------------------===//
1181 let AddedComplexity = 20 in {
1182 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1183 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1185 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1186 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1187 "\t{$src2, $dst|$dst, $src2}">;
1190 // v2f64 extract element 1 is always custom lowered to unpack high to low
1191 // and extract element 0 so the non-store version isn't too horrible.
1192 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1193 "movhps\t{$src, $dst|$dst, $src}",
1194 [(store (f64 (vector_extract
1195 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1196 (undef)), (iPTR 0))), addr:$dst)]>,
1198 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1199 "movhpd\t{$src, $dst|$dst, $src}",
1200 [(store (f64 (vector_extract
1201 (v2f64 (unpckh VR128:$src, (undef))),
1202 (iPTR 0))), addr:$dst)]>,
1204 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1205 "movhps\t{$src, $dst|$dst, $src}",
1206 [(store (f64 (vector_extract
1207 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1208 (undef)), (iPTR 0))), addr:$dst)]>;
1209 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1210 "movhpd\t{$src, $dst|$dst, $src}",
1211 [(store (f64 (vector_extract
1212 (v2f64 (unpckh VR128:$src, (undef))),
1213 (iPTR 0))), addr:$dst)]>;
1215 let Predicates = [HasAVX] in {
1217 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1218 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1219 def : Pat<(X86Movlhps VR128:$src1,
1220 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1221 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1222 def : Pat<(X86Movlhps VR128:$src1,
1223 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1224 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(X86Movlhps VR128:$src1,
1226 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1227 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1229 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1230 // is during lowering, where it's not possible to recognize the load fold
1231 // cause it has two uses through a bitcast. One use disappears at isel time
1232 // and the fold opportunity reappears.
1233 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1234 (scalar_to_vector (loadf64 addr:$src2)))),
1235 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1237 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1238 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1239 (scalar_to_vector (loadf64 addr:$src2)))),
1240 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1243 def : Pat<(store (f64 (vector_extract
1244 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1245 (bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
1246 (VMOVHPSmr addr:$dst, VR128:$src)>;
1247 def : Pat<(store (f64 (vector_extract
1248 (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))), addr:$dst),
1249 (VMOVHPDmr addr:$dst, VR128:$src)>;
1252 let Predicates = [HasSSE1] in {
1254 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1255 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1256 def : Pat<(X86Movlhps VR128:$src1,
1257 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1258 (MOVHPSrm VR128:$src1, addr:$src2)>;
1259 def : Pat<(X86Movlhps VR128:$src1,
1260 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1261 (MOVHPSrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(X86Movlhps VR128:$src1,
1263 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1264 (MOVHPSrm VR128:$src1, addr:$src2)>;
1267 def : Pat<(store (f64 (vector_extract
1268 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1269 (bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
1270 (MOVHPSmr addr:$dst, VR128:$src)>;
1273 let Predicates = [HasSSE2] in {
1274 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1275 // is during lowering, where it's not possible to recognize the load fold
1276 // cause it has two uses through a bitcast. One use disappears at isel time
1277 // and the fold opportunity reappears.
1278 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1279 (scalar_to_vector (loadf64 addr:$src2)))),
1280 (MOVHPDrm VR128:$src1, addr:$src2)>;
1282 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1283 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1284 (scalar_to_vector (loadf64 addr:$src2)))),
1285 (MOVHPDrm VR128:$src1, addr:$src2)>;
1288 def : Pat<(store (f64 (vector_extract
1289 (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))),addr:$dst),
1290 (MOVHPDmr addr:$dst, VR128:$src)>;
1293 //===----------------------------------------------------------------------===//
1294 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1295 //===----------------------------------------------------------------------===//
1297 let AddedComplexity = 20 in {
1298 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1299 (ins VR128:$src1, VR128:$src2),
1300 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1302 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))]>,
1304 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1305 (ins VR128:$src1, VR128:$src2),
1306 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1308 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))]>,
1311 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1312 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1313 (ins VR128:$src1, VR128:$src2),
1314 "movlhps\t{$src2, $dst|$dst, $src2}",
1316 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))]>;
1317 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1318 (ins VR128:$src1, VR128:$src2),
1319 "movhlps\t{$src2, $dst|$dst, $src2}",
1321 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))]>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1327 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1328 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1329 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1332 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1333 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1336 let Predicates = [HasSSE1] in {
1338 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1339 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1340 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1341 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1344 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1345 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1348 //===----------------------------------------------------------------------===//
1349 // SSE 1 & 2 - Conversion Instructions
1350 //===----------------------------------------------------------------------===//
1352 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1353 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1355 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1356 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1357 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1358 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1361 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1362 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1363 string asm, Domain d> {
1364 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1365 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1367 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1368 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1372 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1373 X86MemOperand x86memop, string asm> {
1374 let neverHasSideEffects = 1 in {
1375 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1376 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1378 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1379 (ins DstRC:$src1, x86memop:$src),
1380 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1381 } // neverHasSideEffects = 1
1384 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1385 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1387 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1388 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1390 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1391 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX,
1393 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1394 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1395 VEX, VEX_W, VEX_LIG;
1397 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1398 // register, but the same isn't true when only using memory operands,
1399 // provide other assembly "l" and "q" forms to address this explicitly
1400 // where appropriate to do so.
1401 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1403 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1404 VEX_4V, VEX_W, VEX_LIG;
1405 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1407 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1409 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1410 VEX_4V, VEX_W, VEX_LIG;
1412 let Predicates = [HasAVX], AddedComplexity = 1 in {
1413 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1414 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1415 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1416 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1417 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1418 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1419 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1420 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1422 def : Pat<(f32 (sint_to_fp GR32:$src)),
1423 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1424 def : Pat<(f32 (sint_to_fp GR64:$src)),
1425 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1426 def : Pat<(f64 (sint_to_fp GR32:$src)),
1427 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1428 def : Pat<(f64 (sint_to_fp GR64:$src)),
1429 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1432 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1433 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1434 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1435 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1436 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1437 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1438 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1439 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1440 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1441 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1442 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1443 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1444 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1445 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1446 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1447 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1449 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1450 // and/or XMM operand(s).
1452 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1453 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1455 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1456 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1457 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1458 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1459 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1460 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1463 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1464 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1465 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1466 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1468 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1469 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1470 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1471 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1472 (ins DstRC:$src1, x86memop:$src2),
1474 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1475 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1476 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1479 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1480 f128mem, load, "cvtsd2si">, XD, VEX, VEX_LIG;
1481 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1482 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1483 XD, VEX, VEX_W, VEX_LIG;
1485 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1486 f128mem, load, "cvtsd2si{l}">, XD;
1487 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1488 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1491 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1492 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1493 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1494 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1496 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1497 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1498 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1499 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1502 let Constraints = "$src1 = $dst" in {
1503 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1504 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1506 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1507 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1508 "cvtsi2ss{q}">, XS, REX_W;
1509 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1510 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1512 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1513 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1514 "cvtsi2sd">, XD, REX_W;
1519 // Aliases for intrinsics
1520 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1521 f32mem, load, "cvttss2si">, XS, VEX;
1522 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1523 int_x86_sse_cvttss2si64, f32mem, load,
1524 "cvttss2si">, XS, VEX, VEX_W;
1525 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1526 f128mem, load, "cvttsd2si">, XD, VEX;
1527 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1528 int_x86_sse2_cvttsd2si64, f128mem, load,
1529 "cvttsd2si">, XD, VEX, VEX_W;
1530 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1531 f32mem, load, "cvttss2si">, XS;
1532 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1533 int_x86_sse_cvttss2si64, f32mem, load,
1534 "cvttss2si{q}">, XS, REX_W;
1535 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1536 f128mem, load, "cvttsd2si">, XD;
1537 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1538 int_x86_sse2_cvttsd2si64, f128mem, load,
1539 "cvttsd2si{q}">, XD, REX_W;
1541 let Pattern = []<dag> in {
1542 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1543 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS,
1545 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1546 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1548 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1549 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1550 SSEPackedSingle>, TB, VEX;
1551 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1552 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1553 SSEPackedSingle>, TB, VEX;
1556 let Pattern = []<dag> in {
1557 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1558 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1559 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1560 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1561 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1562 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1563 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1566 let Predicates = [HasAVX] in {
1567 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1568 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1569 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1570 (VCVTSS2SIrm addr:$src)>;
1571 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1572 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1573 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1574 (VCVTSS2SI64rm addr:$src)>;
1577 let Predicates = [HasSSE1] in {
1578 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1579 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1580 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1581 (CVTSS2SIrm addr:$src)>;
1582 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1583 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1584 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1585 (CVTSS2SI64rm addr:$src)>;
1590 // Convert scalar double to scalar single
1591 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1592 (ins FR64:$src1, FR64:$src2),
1593 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1596 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1597 (ins FR64:$src1, f64mem:$src2),
1598 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1599 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1601 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1604 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1605 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1606 [(set FR32:$dst, (fround FR64:$src))]>;
1607 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1608 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1609 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1610 Requires<[HasSSE2, OptForSize]>;
1612 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1613 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1615 let Constraints = "$src1 = $dst" in
1616 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1617 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1619 // Convert scalar single to scalar double
1620 // SSE2 instructions with XS prefix
1621 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1622 (ins FR32:$src1, FR32:$src2),
1623 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1624 []>, XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1626 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1627 (ins FR32:$src1, f32mem:$src2),
1628 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1629 []>, XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1631 let Predicates = [HasAVX] in {
1632 def : Pat<(f64 (fextend FR32:$src)),
1633 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1634 def : Pat<(fextend (loadf32 addr:$src)),
1635 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1636 def : Pat<(extloadf32 addr:$src),
1637 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1640 def : Pat<(extloadf32 addr:$src),
1641 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1642 Requires<[HasAVX, OptForSpeed]>;
1644 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1645 "cvtss2sd\t{$src, $dst|$dst, $src}",
1646 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1647 Requires<[HasSSE2]>;
1648 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1649 "cvtss2sd\t{$src, $dst|$dst, $src}",
1650 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1651 Requires<[HasSSE2, OptForSize]>;
1653 // extload f32 -> f64. This matches load+fextend because we have a hack in
1654 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1656 // Since these loads aren't folded into the fextend, we have to match it
1658 def : Pat<(fextend (loadf32 addr:$src)),
1659 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1660 def : Pat<(extloadf32 addr:$src),
1661 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1663 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1664 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1665 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1666 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1667 VR128:$src2))]>, XS, VEX_4V,
1669 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1670 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1671 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1672 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1673 (load addr:$src2)))]>, XS, VEX_4V,
1675 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1676 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1677 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1678 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1679 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1680 VR128:$src2))]>, XS,
1681 Requires<[HasSSE2]>;
1682 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1683 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1684 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1685 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1686 (load addr:$src2)))]>, XS,
1687 Requires<[HasSSE2]>;
1690 // Convert doubleword to packed single/double fp
1691 // SSE2 instructions without OpSize prefix
1692 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1693 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1694 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1695 TB, VEX, Requires<[HasAVX]>;
1696 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1697 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1698 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1699 (bitconvert (memopv2i64 addr:$src))))]>,
1700 TB, VEX, Requires<[HasAVX]>;
1701 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1702 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1703 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1704 TB, Requires<[HasSSE2]>;
1705 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1706 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1707 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1708 (bitconvert (memopv2i64 addr:$src))))]>,
1709 TB, Requires<[HasSSE2]>;
1711 // FIXME: why the non-intrinsic version is described as SSE3?
1712 // SSE2 instructions with XS prefix
1713 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1714 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1715 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1716 XS, VEX, Requires<[HasAVX]>;
1717 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1718 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1719 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1720 (bitconvert (memopv2i64 addr:$src))))]>,
1721 XS, VEX, Requires<[HasAVX]>;
1722 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1723 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1724 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1725 XS, Requires<[HasSSE2]>;
1726 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1727 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1728 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1729 (bitconvert (memopv2i64 addr:$src))))]>,
1730 XS, Requires<[HasSSE2]>;
1733 // Convert packed single/double fp to doubleword
1734 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1735 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1736 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1737 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1738 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1739 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1740 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1741 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1742 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1743 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1744 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1745 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1747 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1748 "cvtps2dq\t{$src, $dst|$dst, $src}",
1749 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1751 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1753 "cvtps2dq\t{$src, $dst|$dst, $src}",
1754 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1755 (memop addr:$src)))]>, VEX;
1756 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1757 "cvtps2dq\t{$src, $dst|$dst, $src}",
1758 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1759 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1760 "cvtps2dq\t{$src, $dst|$dst, $src}",
1761 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1762 (memop addr:$src)))]>;
1764 // SSE2 packed instructions with XD prefix
1765 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1766 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1767 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1768 XD, VEX, Requires<[HasAVX]>;
1769 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1770 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1771 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1772 (memop addr:$src)))]>,
1773 XD, VEX, Requires<[HasAVX]>;
1774 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1775 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1776 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1777 XD, Requires<[HasSSE2]>;
1778 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1779 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1780 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1781 (memop addr:$src)))]>,
1782 XD, Requires<[HasSSE2]>;
1785 // Convert with truncation packed single/double fp to doubleword
1786 // SSE2 packed instructions with XS prefix
1787 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1788 "cvttps2dq\t{$src, $dst|$dst, $src}",
1790 (int_x86_sse2_cvttps2dq VR128:$src))]>, VEX;
1791 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1792 "cvttps2dq\t{$src, $dst|$dst, $src}",
1793 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1794 (memop addr:$src)))]>, VEX;
1795 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1796 "cvttps2dq\t{$src, $dst|$dst, $src}",
1798 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))]>, VEX;
1799 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1800 "cvttps2dq\t{$src, $dst|$dst, $src}",
1801 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1802 (memopv8f32 addr:$src)))]>, VEX;
1804 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvttps2dq\t{$src, $dst|$dst, $src}",
1807 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1808 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1809 "cvttps2dq\t{$src, $dst|$dst, $src}",
1811 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1813 let Predicates = [HasAVX] in {
1814 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1815 (Int_VCVTDQ2PSrr VR128:$src)>;
1816 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1817 (Int_VCVTDQ2PSrm addr:$src)>;
1819 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1820 (VCVTTPS2DQrr VR128:$src)>;
1821 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1822 (VCVTTPS2DQrm addr:$src)>;
1824 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1825 (VCVTDQ2PSYrr VR256:$src)>;
1826 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1827 (VCVTDQ2PSYrm addr:$src)>;
1829 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1830 (VCVTTPS2DQYrr VR256:$src)>;
1831 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1832 (VCVTTPS2DQYrm addr:$src)>;
1835 let Predicates = [HasSSE2] in {
1836 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1837 (Int_CVTDQ2PSrr VR128:$src)>;
1838 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1839 (Int_CVTDQ2PSrm addr:$src)>;
1841 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1842 (CVTTPS2DQrr VR128:$src)>;
1843 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1844 (CVTTPS2DQrm addr:$src)>;
1847 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1848 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1850 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1851 let isCodeGenOnly = 1 in
1852 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1853 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1854 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1855 (memop addr:$src)))]>, VEX;
1856 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1857 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1858 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1859 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1860 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1861 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1862 (memop addr:$src)))]>;
1864 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1865 // register, but the same isn't true when using memory operands instead.
1866 // Provide other assembly rr and rm forms to address this explicitly.
1867 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1868 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1871 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1872 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1873 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1874 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1877 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1878 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1879 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1880 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1882 // Convert packed single to packed double
1883 let Predicates = [HasAVX] in {
1884 // SSE2 instructions without OpSize prefix
1885 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1886 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1887 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1888 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1889 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1890 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1891 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1892 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1894 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1895 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1896 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1897 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1899 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1902 TB, VEX, Requires<[HasAVX]>;
1903 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1904 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1905 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1906 (load addr:$src)))]>,
1907 TB, VEX, Requires<[HasAVX]>;
1908 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1909 "cvtps2pd\t{$src, $dst|$dst, $src}",
1910 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1911 TB, Requires<[HasSSE2]>;
1912 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1913 "cvtps2pd\t{$src, $dst|$dst, $src}",
1914 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1915 (load addr:$src)))]>,
1916 TB, Requires<[HasSSE2]>;
1918 // Convert packed double to packed single
1919 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1920 // register, but the same isn't true when using memory operands instead.
1921 // Provide other assembly rr and rm forms to address this explicitly.
1922 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1923 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1924 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1925 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1928 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1929 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1930 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1931 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1934 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1935 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1936 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1937 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1938 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1939 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1940 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1941 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1944 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1945 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1946 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1947 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1949 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1950 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1951 (memop addr:$src)))]>;
1952 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1953 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1954 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1955 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1956 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1957 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1958 (memop addr:$src)))]>;
1960 // AVX 256-bit register conversion intrinsics
1961 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1962 // whenever possible to avoid declaring two versions of each one.
1963 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1964 (VCVTDQ2PSYrr VR256:$src)>;
1965 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
1966 (VCVTDQ2PSYrm addr:$src)>;
1968 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1969 (VCVTPD2PSYrr VR256:$src)>;
1970 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1971 (VCVTPD2PSYrm addr:$src)>;
1973 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1974 (VCVTPS2DQYrr VR256:$src)>;
1975 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1976 (VCVTPS2DQYrm addr:$src)>;
1978 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1979 (VCVTPS2PDYrr VR128:$src)>;
1980 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1981 (VCVTPS2PDYrm addr:$src)>;
1983 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1984 (VCVTTPD2DQYrr VR256:$src)>;
1985 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1986 (VCVTTPD2DQYrm addr:$src)>;
1988 // Match fround and fextend for 128/256-bit conversions
1989 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1990 (VCVTPD2PSYrr VR256:$src)>;
1991 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1992 (VCVTPD2PSYrm addr:$src)>;
1994 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1995 (VCVTPS2PDYrr VR128:$src)>;
1996 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1997 (VCVTPS2PDYrm addr:$src)>;
1999 //===----------------------------------------------------------------------===//
2000 // SSE 1 & 2 - Compare Instructions
2001 //===----------------------------------------------------------------------===//
2003 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2004 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2005 SDNode OpNode, ValueType VT, PatFrag ld_frag,
2006 string asm, string asm_alt> {
2007 def rr : SIi8<0xC2, MRMSrcReg,
2008 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2009 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
2010 def rm : SIi8<0xC2, MRMSrcMem,
2011 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
2012 [(set RC:$dst, (OpNode (VT RC:$src1),
2013 (ld_frag addr:$src2), imm:$cc))]>;
2015 // Accept explicit immediate argument form instead of comparison code.
2016 let neverHasSideEffects = 1 in {
2017 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2018 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
2020 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2021 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
2025 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2026 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2027 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2028 XS, VEX_4V, VEX_LIG;
2029 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2030 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2031 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2032 XD, VEX_4V, VEX_LIG;
2034 let Constraints = "$src1 = $dst" in {
2035 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2036 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2037 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2039 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2040 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2041 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2045 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2046 Intrinsic Int, string asm> {
2047 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2048 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2049 [(set VR128:$dst, (Int VR128:$src1,
2050 VR128:$src, imm:$cc))]>;
2051 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2052 (ins VR128:$src1, x86memop:$src, SSECC:$cc), asm,
2053 [(set VR128:$dst, (Int VR128:$src1,
2054 (load addr:$src), imm:$cc))]>;
2057 // Aliases to match intrinsics which expect XMM operand(s).
2058 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2059 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2061 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2062 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2064 let Constraints = "$src1 = $dst" in {
2065 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2066 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2067 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2068 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2072 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2073 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2074 ValueType vt, X86MemOperand x86memop,
2075 PatFrag ld_frag, string OpcodeStr, Domain d> {
2076 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2077 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2078 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2080 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2081 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2082 [(set EFLAGS, (OpNode (vt RC:$src1),
2083 (ld_frag addr:$src2)))],
2087 let Defs = [EFLAGS] in {
2088 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2089 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2090 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2091 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2093 let Pattern = []<dag> in {
2094 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2095 "comiss", SSEPackedSingle>, TB, VEX,
2097 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2098 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2102 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2103 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2104 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2105 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2107 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2108 load, "comiss", SSEPackedSingle>, TB, VEX;
2109 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2110 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2111 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2112 "ucomiss", SSEPackedSingle>, TB;
2113 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2114 "ucomisd", SSEPackedDouble>, TB, OpSize;
2116 let Pattern = []<dag> in {
2117 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2118 "comiss", SSEPackedSingle>, TB;
2119 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2120 "comisd", SSEPackedDouble>, TB, OpSize;
2123 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2124 load, "ucomiss", SSEPackedSingle>, TB;
2125 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2126 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2128 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2129 "comiss", SSEPackedSingle>, TB;
2130 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2131 "comisd", SSEPackedDouble>, TB, OpSize;
2132 } // Defs = [EFLAGS]
2134 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2135 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2136 Intrinsic Int, string asm, string asm_alt,
2138 let isAsmParserOnly = 1 in {
2139 def rri : PIi8<0xC2, MRMSrcReg,
2140 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2141 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2143 def rmi : PIi8<0xC2, MRMSrcMem,
2144 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
2145 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2149 // Accept explicit immediate argument form instead of comparison code.
2150 def rri_alt : PIi8<0xC2, MRMSrcReg,
2151 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2152 asm_alt, [], IIC_DEFAULT, d>;
2153 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2154 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2155 asm_alt, [], IIC_DEFAULT, d>;
2158 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2159 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2160 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2161 SSEPackedSingle>, TB, VEX_4V;
2162 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2163 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2164 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2165 SSEPackedDouble>, TB, OpSize, VEX_4V;
2166 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2167 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2168 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2169 SSEPackedSingle>, TB, VEX_4V;
2170 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2171 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2172 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2173 SSEPackedDouble>, TB, OpSize, VEX_4V;
2174 let Constraints = "$src1 = $dst" in {
2175 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2176 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2177 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2178 SSEPackedSingle>, TB;
2179 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2180 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2181 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2182 SSEPackedDouble>, TB, OpSize;
2185 let Predicates = [HasAVX] in {
2186 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2187 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2188 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2189 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2190 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2191 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2192 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2193 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2195 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2196 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2197 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2198 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2199 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2200 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2201 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2202 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2205 let Predicates = [HasSSE1] in {
2206 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2207 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2208 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2209 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2212 let Predicates = [HasSSE2] in {
2213 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2214 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2215 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2216 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2219 //===----------------------------------------------------------------------===//
2220 // SSE 1 & 2 - Shuffle Instructions
2221 //===----------------------------------------------------------------------===//
2223 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2224 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2225 ValueType vt, string asm, PatFrag mem_frag,
2226 Domain d, bit IsConvertibleToThreeAddress = 0> {
2227 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2228 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2229 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2230 (i8 imm:$src3))))], IIC_DEFAULT, d>;
2231 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2232 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2233 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2234 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2235 (i8 imm:$src3))))], IIC_DEFAULT, d>;
2238 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2239 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2240 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2241 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2242 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2243 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2244 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2245 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2246 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2247 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2248 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2249 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2251 let Constraints = "$src1 = $dst" in {
2252 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2253 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2254 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2256 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2257 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2258 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2262 let Predicates = [HasAVX] in {
2263 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2264 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2265 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2266 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2267 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2269 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2270 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2271 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2272 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2273 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2276 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2277 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2278 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2279 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2280 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2282 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2283 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2284 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2285 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2286 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2289 let Predicates = [HasSSE1] in {
2290 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2291 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2292 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2293 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2294 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2297 let Predicates = [HasSSE2] in {
2298 // Generic SHUFPD patterns
2299 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2300 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2301 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2302 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2303 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2306 //===----------------------------------------------------------------------===//
2307 // SSE 1 & 2 - Unpack Instructions
2308 //===----------------------------------------------------------------------===//
2310 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2311 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2312 PatFrag mem_frag, RegisterClass RC,
2313 X86MemOperand x86memop, string asm,
2315 def rr : PI<opc, MRMSrcReg,
2316 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2318 (vt (OpNode RC:$src1, RC:$src2)))],
2320 def rm : PI<opc, MRMSrcMem,
2321 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2323 (vt (OpNode RC:$src1,
2324 (mem_frag addr:$src2))))],
2328 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2329 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2330 SSEPackedSingle>, TB, VEX_4V;
2331 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2332 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2333 SSEPackedDouble>, TB, OpSize, VEX_4V;
2334 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2335 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2336 SSEPackedSingle>, TB, VEX_4V;
2337 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2338 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2339 SSEPackedDouble>, TB, OpSize, VEX_4V;
2341 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2342 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2343 SSEPackedSingle>, TB, VEX_4V;
2344 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2345 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2346 SSEPackedDouble>, TB, OpSize, VEX_4V;
2347 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2348 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2349 SSEPackedSingle>, TB, VEX_4V;
2350 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2351 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2352 SSEPackedDouble>, TB, OpSize, VEX_4V;
2354 let Constraints = "$src1 = $dst" in {
2355 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2356 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2357 SSEPackedSingle>, TB;
2358 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2359 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2360 SSEPackedDouble>, TB, OpSize;
2361 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2362 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2363 SSEPackedSingle>, TB;
2364 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2365 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2366 SSEPackedDouble>, TB, OpSize;
2367 } // Constraints = "$src1 = $dst"
2369 let Predicates = [HasAVX], AddedComplexity = 1 in {
2370 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2371 // problem is during lowering, where it's not possible to recognize the load
2372 // fold cause it has two uses through a bitcast. One use disappears at isel
2373 // time and the fold opportunity reappears.
2374 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2375 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2378 let Predicates = [HasSSE2] in {
2379 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2380 // problem is during lowering, where it's not possible to recognize the load
2381 // fold cause it has two uses through a bitcast. One use disappears at isel
2382 // time and the fold opportunity reappears.
2383 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2384 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2387 //===----------------------------------------------------------------------===//
2388 // SSE 1 & 2 - Extract Floating-Point Sign mask
2389 //===----------------------------------------------------------------------===//
2391 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2392 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2394 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2395 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2396 [(set GR32:$dst, (Int RC:$src))], IIC_DEFAULT, d>;
2397 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2398 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2399 IIC_DEFAULT, d>, REX_W;
2402 let Predicates = [HasAVX] in {
2403 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2404 "movmskps", SSEPackedSingle>, TB, VEX;
2405 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2406 "movmskpd", SSEPackedDouble>, TB,
2408 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2409 "movmskps", SSEPackedSingle>, TB, VEX;
2410 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2411 "movmskpd", SSEPackedDouble>, TB,
2414 def : Pat<(i32 (X86fgetsign FR32:$src)),
2415 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2417 def : Pat<(i64 (X86fgetsign FR32:$src)),
2418 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2420 def : Pat<(i32 (X86fgetsign FR64:$src)),
2421 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2423 def : Pat<(i64 (X86fgetsign FR64:$src)),
2424 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2428 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2429 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2430 SSEPackedSingle>, TB, VEX;
2431 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2432 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2433 SSEPackedDouble>, TB,
2435 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2436 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2437 SSEPackedSingle>, TB, VEX;
2438 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2439 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2440 SSEPackedDouble>, TB,
2444 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2445 SSEPackedSingle>, TB;
2446 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2447 SSEPackedDouble>, TB, OpSize;
2449 def : Pat<(i32 (X86fgetsign FR32:$src)),
2450 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2451 sub_ss))>, Requires<[HasSSE1]>;
2452 def : Pat<(i64 (X86fgetsign FR32:$src)),
2453 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2454 sub_ss))>, Requires<[HasSSE1]>;
2455 def : Pat<(i32 (X86fgetsign FR64:$src)),
2456 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2457 sub_sd))>, Requires<[HasSSE2]>;
2458 def : Pat<(i64 (X86fgetsign FR64:$src)),
2459 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2460 sub_sd))>, Requires<[HasSSE2]>;
2462 //===---------------------------------------------------------------------===//
2463 // SSE2 - Packed Integer Logical Instructions
2464 //===---------------------------------------------------------------------===//
2466 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2468 /// PDI_binop_rm - Simple SSE2 binary operator.
2469 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2470 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2471 X86MemOperand x86memop, bit IsCommutable = 0,
2473 let isCommutable = IsCommutable in
2474 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2475 (ins RC:$src1, RC:$src2),
2477 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2478 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2479 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
2480 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2481 (ins RC:$src1, x86memop:$src2),
2483 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2484 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2485 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2486 (bitconvert (memop_frag addr:$src2)))))]>;
2488 } // ExeDomain = SSEPackedInt
2490 // These are ordered here for pattern ordering requirements with the fp versions
2492 let Predicates = [HasAVX] in {
2493 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2494 i128mem, 1, 0>, VEX_4V;
2495 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2496 i128mem, 1, 0>, VEX_4V;
2497 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2498 i128mem, 1, 0>, VEX_4V;
2499 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2500 i128mem, 0, 0>, VEX_4V;
2503 let Constraints = "$src1 = $dst" in {
2504 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2506 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2508 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2510 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2512 } // Constraints = "$src1 = $dst"
2514 let Predicates = [HasAVX2] in {
2515 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2516 i256mem, 1, 0>, VEX_4V;
2517 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2518 i256mem, 1, 0>, VEX_4V;
2519 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2520 i256mem, 1, 0>, VEX_4V;
2521 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2522 i256mem, 0, 0>, VEX_4V;
2525 //===----------------------------------------------------------------------===//
2526 // SSE 1 & 2 - Logical Instructions
2527 //===----------------------------------------------------------------------===//
2529 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2531 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2533 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2534 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2536 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2537 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2539 let Constraints = "$src1 = $dst" in {
2540 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2541 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2543 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2544 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2548 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2549 let mayLoad = 0 in {
2550 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2551 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2552 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2555 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2556 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2558 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2560 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2562 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2563 // are all promoted to v2i64, and the patterns are covered by the int
2564 // version. This is needed in SSE only, because v2i64 isn't supported on
2565 // SSE1, but only on SSE2.
2566 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2567 !strconcat(OpcodeStr, "ps"), f128mem, [],
2568 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2569 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2571 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2572 !strconcat(OpcodeStr, "pd"), f128mem,
2573 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2574 (bc_v2i64 (v2f64 VR128:$src2))))],
2575 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2576 (memopv2i64 addr:$src2)))], 0>,
2578 let Constraints = "$src1 = $dst" in {
2579 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2580 !strconcat(OpcodeStr, "ps"), f128mem,
2581 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2582 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2583 (memopv2i64 addr:$src2)))]>, TB;
2585 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2586 !strconcat(OpcodeStr, "pd"), f128mem,
2587 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2588 (bc_v2i64 (v2f64 VR128:$src2))))],
2589 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2590 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2594 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2596 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2598 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2599 !strconcat(OpcodeStr, "ps"), f256mem,
2600 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2601 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2602 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2604 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2605 !strconcat(OpcodeStr, "pd"), f256mem,
2606 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2607 (bc_v4i64 (v4f64 VR256:$src2))))],
2608 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2609 (memopv4i64 addr:$src2)))], 0>,
2613 // AVX 256-bit packed logical ops forms
2614 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2615 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2616 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2617 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2619 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2620 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2621 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2622 let isCommutable = 0 in
2623 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2625 //===----------------------------------------------------------------------===//
2626 // SSE 1 & 2 - Arithmetic Instructions
2627 //===----------------------------------------------------------------------===//
2629 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2632 /// In addition, we also have a special variant of the scalar form here to
2633 /// represent the associated intrinsic operation. This form is unlike the
2634 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2635 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2637 /// These three forms can each be reg+reg or reg+mem.
2640 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2642 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2644 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2645 OpNode, FR32, f32mem, Is2Addr>, XS;
2646 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2647 OpNode, FR64, f64mem, Is2Addr>, XD;
2650 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2652 let mayLoad = 0 in {
2653 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2654 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2655 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2656 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2660 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2662 let mayLoad = 0 in {
2663 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2664 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2665 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2666 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2670 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2672 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2673 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2674 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2675 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2678 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2680 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2681 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2682 SSEPackedSingle, Is2Addr>, TB;
2684 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2685 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2686 SSEPackedDouble, Is2Addr>, TB, OpSize;
2689 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2690 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2691 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2692 SSEPackedSingle, 0>, TB;
2694 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2695 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2696 SSEPackedDouble, 0>, TB, OpSize;
2699 // Binary Arithmetic instructions
2700 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2701 basic_sse12_fp_binop_s_int<0x58, "add", 0>, VEX_4V, VEX_LIG;
2702 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2703 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2704 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2705 basic_sse12_fp_binop_s_int<0x59, "mul", 0>, VEX_4V, VEX_LIG;
2706 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2707 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2709 let isCommutable = 0 in {
2710 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2711 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>, VEX_4V, VEX_LIG;
2712 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2713 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2714 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2715 basic_sse12_fp_binop_s_int<0x5E, "div", 0>, VEX_4V, VEX_LIG;
2716 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2717 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2718 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2719 basic_sse12_fp_binop_s_int<0x5F, "max", 0>, VEX_4V, VEX_LIG;
2720 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2721 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2722 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2723 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2724 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2725 basic_sse12_fp_binop_s_int<0x5D, "min", 0>, VEX_4V, VEX_LIG;
2726 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2727 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2728 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2729 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2732 let Constraints = "$src1 = $dst" in {
2733 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2734 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2735 basic_sse12_fp_binop_s_int<0x58, "add">;
2736 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2737 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2738 basic_sse12_fp_binop_s_int<0x59, "mul">;
2740 let isCommutable = 0 in {
2741 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2742 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2743 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2744 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2745 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2746 basic_sse12_fp_binop_s_int<0x5E, "div">;
2747 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2748 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2749 basic_sse12_fp_binop_s_int<0x5F, "max">,
2750 basic_sse12_fp_binop_p_int<0x5F, "max">;
2751 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2752 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2753 basic_sse12_fp_binop_s_int<0x5D, "min">,
2754 basic_sse12_fp_binop_p_int<0x5D, "min">;
2759 /// In addition, we also have a special variant of the scalar form here to
2760 /// represent the associated intrinsic operation. This form is unlike the
2761 /// plain scalar form, in that it takes an entire vector (instead of a
2762 /// scalar) and leaves the top elements undefined.
2764 /// And, we have a special variant form for a full-vector intrinsic form.
2766 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2767 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2768 SDNode OpNode, Intrinsic F32Int> {
2769 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2770 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2771 [(set FR32:$dst, (OpNode FR32:$src))]>;
2772 // For scalar unary operations, fold a load into the operation
2773 // only in OptForSize mode. It eliminates an instruction, but it also
2774 // eliminates a whole-register clobber (the load), so it introduces a
2775 // partial register update condition.
2776 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2777 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2778 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2779 Requires<[HasSSE1, OptForSize]>;
2780 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2781 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2782 [(set VR128:$dst, (F32Int VR128:$src))]>;
2783 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2784 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2785 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2788 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2789 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2790 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2791 !strconcat(OpcodeStr,
2792 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2794 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2795 !strconcat(OpcodeStr,
2796 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2797 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2798 (ins VR128:$src1, ssmem:$src2),
2799 !strconcat(OpcodeStr,
2800 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2803 /// sse1_fp_unop_p - SSE1 unops in packed form.
2804 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2805 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2806 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2807 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2808 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2809 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2810 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2813 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2814 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2815 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2816 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2817 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2818 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2819 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2820 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2823 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2824 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2825 Intrinsic V4F32Int> {
2826 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2827 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2828 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2829 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2830 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2831 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2834 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2835 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2836 Intrinsic V4F32Int> {
2837 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2838 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2839 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2840 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2841 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2842 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2845 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2846 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2847 SDNode OpNode, Intrinsic F64Int> {
2848 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2849 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2850 [(set FR64:$dst, (OpNode FR64:$src))]>;
2851 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2852 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2853 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2854 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2855 Requires<[HasSSE2, OptForSize]>;
2856 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2857 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2858 [(set VR128:$dst, (F64Int VR128:$src))]>;
2859 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2860 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2861 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2864 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2865 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2866 let neverHasSideEffects = 1 in {
2867 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2868 !strconcat(OpcodeStr,
2869 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2871 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2872 !strconcat(OpcodeStr,
2873 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2875 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2876 (ins VR128:$src1, sdmem:$src2),
2877 !strconcat(OpcodeStr,
2878 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2881 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2882 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2884 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2885 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2886 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2887 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2888 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2889 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2892 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2893 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2894 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2895 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2896 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2897 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2898 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2899 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2902 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2903 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2904 Intrinsic V2F64Int> {
2905 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2906 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2907 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2908 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2909 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2910 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2913 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2914 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2915 Intrinsic V2F64Int> {
2916 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2917 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2918 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2919 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2920 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2921 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2924 let Predicates = [HasAVX] in {
2926 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2927 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
2929 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2930 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2931 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2932 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2933 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2934 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2935 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2936 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
2939 // Reciprocal approximations. Note that these typically require refinement
2940 // in order to obtain suitable precision.
2941 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
2942 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2943 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2944 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2945 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
2947 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
2948 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
2949 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
2950 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
2951 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
2954 let AddedComplexity = 1 in {
2955 def : Pat<(f32 (fsqrt FR32:$src)),
2956 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2957 def : Pat<(f32 (fsqrt (load addr:$src))),
2958 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2959 Requires<[HasAVX, OptForSize]>;
2960 def : Pat<(f64 (fsqrt FR64:$src)),
2961 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
2962 def : Pat<(f64 (fsqrt (load addr:$src))),
2963 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
2964 Requires<[HasAVX, OptForSize]>;
2966 def : Pat<(f32 (X86frsqrt FR32:$src)),
2967 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2968 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2969 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2970 Requires<[HasAVX, OptForSize]>;
2972 def : Pat<(f32 (X86frcp FR32:$src)),
2973 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2974 def : Pat<(f32 (X86frcp (load addr:$src))),
2975 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2976 Requires<[HasAVX, OptForSize]>;
2979 let Predicates = [HasAVX], AddedComplexity = 1 in {
2980 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
2981 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2982 (VSQRTSSr (f32 (IMPLICIT_DEF)),
2983 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2985 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2986 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2988 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
2989 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
2990 (VSQRTSDr (f64 (IMPLICIT_DEF)),
2991 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
2993 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2994 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2996 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
2997 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2998 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
2999 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3001 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3002 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3004 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3005 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3006 (VRCPSSr (f32 (IMPLICIT_DEF)),
3007 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3009 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3010 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3014 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3015 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3016 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3017 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3018 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3019 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3021 // Reciprocal approximations. Note that these typically require refinement
3022 // in order to obtain suitable precision.
3023 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3024 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3025 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3026 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3027 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3028 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3030 // There is no f64 version of the reciprocal approximation instructions.
3032 //===----------------------------------------------------------------------===//
3033 // SSE 1 & 2 - Non-temporal stores
3034 //===----------------------------------------------------------------------===//
3036 let AddedComplexity = 400 in { // Prefer non-temporal versions
3037 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3038 (ins f128mem:$dst, VR128:$src),
3039 "movntps\t{$src, $dst|$dst, $src}",
3040 [(alignednontemporalstore (v4f32 VR128:$src),
3042 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3043 (ins f128mem:$dst, VR128:$src),
3044 "movntpd\t{$src, $dst|$dst, $src}",
3045 [(alignednontemporalstore (v2f64 VR128:$src),
3048 let ExeDomain = SSEPackedInt in
3049 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3050 (ins f128mem:$dst, VR128:$src),
3051 "movntdq\t{$src, $dst|$dst, $src}",
3052 [(alignednontemporalstore (v2i64 VR128:$src),
3055 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3056 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3058 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3059 (ins f256mem:$dst, VR256:$src),
3060 "movntps\t{$src, $dst|$dst, $src}",
3061 [(alignednontemporalstore (v8f32 VR256:$src),
3063 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3064 (ins f256mem:$dst, VR256:$src),
3065 "movntpd\t{$src, $dst|$dst, $src}",
3066 [(alignednontemporalstore (v4f64 VR256:$src),
3068 let ExeDomain = SSEPackedInt in
3069 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3070 (ins f256mem:$dst, VR256:$src),
3071 "movntdq\t{$src, $dst|$dst, $src}",
3072 [(alignednontemporalstore (v4i64 VR256:$src),
3076 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3077 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3078 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3079 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3080 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3081 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3083 let AddedComplexity = 400 in { // Prefer non-temporal versions
3084 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3085 "movntps\t{$src, $dst|$dst, $src}",
3086 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3087 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3088 "movntpd\t{$src, $dst|$dst, $src}",
3089 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3091 let ExeDomain = SSEPackedInt in
3092 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3093 "movntdq\t{$src, $dst|$dst, $src}",
3094 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)]>;
3096 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3097 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3099 // There is no AVX form for instructions below this point
3100 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3101 "movnti{l}\t{$src, $dst|$dst, $src}",
3102 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3103 TB, Requires<[HasSSE2]>;
3104 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3105 "movnti{q}\t{$src, $dst|$dst, $src}",
3106 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3107 TB, Requires<[HasSSE2]>;
3110 //===----------------------------------------------------------------------===//
3111 // SSE 1 & 2 - Prefetch and memory fence
3112 //===----------------------------------------------------------------------===//
3114 // Prefetch intrinsic.
3115 let Predicates = [HasSSE1] in {
3116 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3117 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>, TB;
3118 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3119 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>, TB;
3120 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3121 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>, TB;
3122 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3123 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>, TB;
3127 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3128 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3129 TB, Requires<[HasSSE2]>;
3131 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3132 // was introduced with SSE2, it's backward compatible.
3133 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3135 // Load, store, and memory fence
3136 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3137 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3138 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3139 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3140 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3141 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3143 def : Pat<(X86SFence), (SFENCE)>;
3144 def : Pat<(X86LFence), (LFENCE)>;
3145 def : Pat<(X86MFence), (MFENCE)>;
3147 //===----------------------------------------------------------------------===//
3148 // SSE 1 & 2 - Load/Store XCSR register
3149 //===----------------------------------------------------------------------===//
3151 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3152 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3153 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3154 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3156 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3157 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3158 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3159 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3161 //===---------------------------------------------------------------------===//
3162 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3163 //===---------------------------------------------------------------------===//
3165 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3167 let neverHasSideEffects = 1 in {
3168 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3169 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3170 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3171 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3173 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3174 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3175 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3176 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3179 let isCodeGenOnly = 1 in {
3180 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3181 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3182 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3183 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3184 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3185 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3186 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3187 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3190 let canFoldAsLoad = 1, mayLoad = 1 in {
3191 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3192 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3193 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3194 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3195 let Predicates = [HasAVX] in {
3196 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3197 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3198 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3199 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3203 let mayStore = 1 in {
3204 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3205 (ins i128mem:$dst, VR128:$src),
3206 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3207 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3208 (ins i256mem:$dst, VR256:$src),
3209 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3210 let Predicates = [HasAVX] in {
3211 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3212 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3213 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3214 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3218 let neverHasSideEffects = 1 in
3219 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3220 "movdqa\t{$src, $dst|$dst, $src}", []>;
3222 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3223 "movdqu\t{$src, $dst|$dst, $src}",
3224 []>, XS, Requires<[HasSSE2]>;
3227 let isCodeGenOnly = 1 in {
3228 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3229 "movdqa\t{$src, $dst|$dst, $src}", []>;
3231 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3232 "movdqu\t{$src, $dst|$dst, $src}",
3233 []>, XS, Requires<[HasSSE2]>;
3236 let canFoldAsLoad = 1, mayLoad = 1 in {
3237 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3238 "movdqa\t{$src, $dst|$dst, $src}",
3239 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3240 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3241 "movdqu\t{$src, $dst|$dst, $src}",
3242 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3243 XS, Requires<[HasSSE2]>;
3246 let mayStore = 1 in {
3247 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3248 "movdqa\t{$src, $dst|$dst, $src}",
3249 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3250 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3251 "movdqu\t{$src, $dst|$dst, $src}",
3252 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3253 XS, Requires<[HasSSE2]>;
3256 // Intrinsic forms of MOVDQU load and store
3257 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3258 "vmovdqu\t{$src, $dst|$dst, $src}",
3259 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3260 XS, VEX, Requires<[HasAVX]>;
3262 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3263 "movdqu\t{$src, $dst|$dst, $src}",
3264 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3265 XS, Requires<[HasSSE2]>;
3267 } // ExeDomain = SSEPackedInt
3269 let Predicates = [HasAVX] in {
3270 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3271 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3274 //===---------------------------------------------------------------------===//
3275 // SSE2 - Packed Integer Arithmetic Instructions
3276 //===---------------------------------------------------------------------===//
3278 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3280 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3281 RegisterClass RC, PatFrag memop_frag,
3282 X86MemOperand x86memop, bit IsCommutable = 0,
3284 let isCommutable = IsCommutable in
3285 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3286 (ins RC:$src1, RC:$src2),
3288 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3289 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3290 [(set RC:$dst, (IntId RC:$src1, RC:$src2))]>;
3291 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3292 (ins RC:$src1, x86memop:$src2),
3294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3296 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))]>;
3299 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3300 string OpcodeStr, SDNode OpNode,
3301 SDNode OpNode2, RegisterClass RC,
3302 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3304 // src2 is always 128-bit
3305 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3306 (ins RC:$src1, VR128:$src2),
3308 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3310 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))]>;
3311 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3312 (ins RC:$src1, i128mem:$src2),
3314 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3315 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3316 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3317 (bc_frag (memopv2i64 addr:$src2)))))]>;
3318 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3319 (ins RC:$src1, i32i8imm:$src2),
3321 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3322 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3323 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))]>;
3326 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3327 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3328 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3329 PatFrag memop_frag, X86MemOperand x86memop,
3330 bit IsCommutable = 0, bit Is2Addr = 1> {
3331 let isCommutable = IsCommutable in
3332 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3333 (ins RC:$src1, RC:$src2),
3335 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3336 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3337 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3338 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3339 (ins RC:$src1, x86memop:$src2),
3341 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3342 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3343 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3344 (bitconvert (memop_frag addr:$src2)))))]>;
3346 } // ExeDomain = SSEPackedInt
3348 // 128-bit Integer Arithmetic
3350 let Predicates = [HasAVX] in {
3351 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3352 i128mem, 1, 0 /*3addr*/>, VEX_4V;
3353 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3354 i128mem, 1, 0>, VEX_4V;
3355 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3356 i128mem, 1, 0>, VEX_4V;
3357 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3358 i128mem, 1, 0>, VEX_4V;
3359 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3360 i128mem, 1, 0>, VEX_4V;
3361 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3362 i128mem, 0, 0>, VEX_4V;
3363 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3364 i128mem, 0, 0>, VEX_4V;
3365 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3366 i128mem, 0, 0>, VEX_4V;
3367 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3368 i128mem, 0, 0>, VEX_4V;
3369 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3370 memopv2i64, i128mem, 1, 0>, VEX_4V;
3373 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3374 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3375 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3376 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3377 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3378 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3379 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3380 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3381 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3382 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3383 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3384 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3385 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3386 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3387 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3388 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3389 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3390 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3391 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3392 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3393 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3394 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3395 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3396 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3397 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3398 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3399 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3400 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3401 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3402 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3403 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3404 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3405 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3406 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3407 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3408 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3411 let Predicates = [HasAVX2] in {
3412 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3413 i256mem, 1, 0>, VEX_4V;
3414 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3415 i256mem, 1, 0>, VEX_4V;
3416 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3417 i256mem, 1, 0>, VEX_4V;
3418 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3419 i256mem, 1, 0>, VEX_4V;
3420 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3421 i256mem, 1, 0>, VEX_4V;
3422 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3423 i256mem, 0, 0>, VEX_4V;
3424 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3425 i256mem, 0, 0>, VEX_4V;
3426 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3427 i256mem, 0, 0>, VEX_4V;
3428 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3429 i256mem, 0, 0>, VEX_4V;
3430 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3431 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3434 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3435 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3436 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3437 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3438 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3439 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3440 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3441 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3442 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3443 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3444 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3445 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3446 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3447 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3448 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3449 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3450 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3451 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3452 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3453 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3454 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3455 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3456 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3457 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3458 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3459 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3460 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3461 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3462 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3463 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3464 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3465 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3466 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3467 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3468 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3469 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3472 let Constraints = "$src1 = $dst" in {
3473 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3475 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3477 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3479 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3481 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3483 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3485 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3487 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3489 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3491 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3492 memopv2i64, i128mem, 1>;
3495 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3496 VR128, memopv2i64, i128mem>;
3497 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3498 VR128, memopv2i64, i128mem>;
3499 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3500 VR128, memopv2i64, i128mem>;
3501 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3502 VR128, memopv2i64, i128mem>;
3503 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3504 VR128, memopv2i64, i128mem, 1>;
3505 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3506 VR128, memopv2i64, i128mem, 1>;
3507 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3508 VR128, memopv2i64, i128mem, 1>;
3509 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3510 VR128, memopv2i64, i128mem, 1>;
3511 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3512 VR128, memopv2i64, i128mem, 1>;
3513 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3514 VR128, memopv2i64, i128mem, 1>;
3515 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3516 VR128, memopv2i64, i128mem, 1>;
3517 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3518 VR128, memopv2i64, i128mem, 1>;
3519 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3520 VR128, memopv2i64, i128mem, 1>;
3521 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3522 VR128, memopv2i64, i128mem, 1>;
3523 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3524 VR128, memopv2i64, i128mem, 1>;
3525 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3526 VR128, memopv2i64, i128mem, 1>;
3527 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3528 VR128, memopv2i64, i128mem, 1>;
3529 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3530 VR128, memopv2i64, i128mem, 1>;
3532 } // Constraints = "$src1 = $dst"
3534 //===---------------------------------------------------------------------===//
3535 // SSE2 - Packed Integer Logical Instructions
3536 //===---------------------------------------------------------------------===//
3538 let Predicates = [HasAVX] in {
3539 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3540 VR128, v8i16, v8i16, bc_v8i16, 0>, VEX_4V;
3541 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3542 VR128, v4i32, v4i32, bc_v4i32, 0>, VEX_4V;
3543 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3544 VR128, v2i64, v2i64, bc_v2i64, 0>, VEX_4V;
3546 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3547 VR128, v8i16, v8i16, bc_v8i16, 0>, VEX_4V;
3548 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3549 VR128, v4i32, v4i32, bc_v4i32, 0>, VEX_4V;
3550 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3551 VR128, v2i64, v2i64, bc_v2i64, 0>, VEX_4V;
3553 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3554 VR128, v8i16, v8i16, bc_v8i16, 0>, VEX_4V;
3555 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3556 VR128, v4i32, v4i32, bc_v4i32, 0>, VEX_4V;
3558 let ExeDomain = SSEPackedInt in {
3559 // 128-bit logical shifts.
3560 def VPSLLDQri : PDIi8<0x73, MRM7r,
3561 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3562 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3564 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3566 def VPSRLDQri : PDIi8<0x73, MRM3r,
3567 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3568 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3570 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3572 // PSRADQri doesn't exist in SSE[1-3].
3574 } // Predicates = [HasAVX]
3576 let Predicates = [HasAVX2] in {
3577 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3578 VR256, v16i16, v8i16, bc_v8i16, 0>, VEX_4V;
3579 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3580 VR256, v8i32, v4i32, bc_v4i32, 0>, VEX_4V;
3581 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3582 VR256, v4i64, v2i64, bc_v2i64, 0>, VEX_4V;
3584 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3585 VR256, v16i16, v8i16, bc_v8i16, 0>, VEX_4V;
3586 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3587 VR256, v8i32, v4i32, bc_v4i32, 0>, VEX_4V;
3588 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3589 VR256, v4i64, v2i64, bc_v2i64, 0>, VEX_4V;
3591 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3592 VR256, v16i16, v8i16, bc_v8i16, 0>, VEX_4V;
3593 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3594 VR256, v8i32, v4i32, bc_v4i32, 0>, VEX_4V;
3596 let ExeDomain = SSEPackedInt in {
3597 // 256-bit logical shifts.
3598 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3599 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3600 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3602 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3604 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3605 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3606 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3608 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3610 // PSRADQYri doesn't exist in SSE[1-3].
3612 } // Predicates = [HasAVX2]
3614 let Constraints = "$src1 = $dst" in {
3615 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3616 VR128, v8i16, v8i16, bc_v8i16>;
3617 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3618 VR128, v4i32, v4i32, bc_v4i32>;
3619 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3620 VR128, v2i64, v2i64, bc_v2i64>;
3622 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3623 VR128, v8i16, v8i16, bc_v8i16>;
3624 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3625 VR128, v4i32, v4i32, bc_v4i32>;
3626 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3627 VR128, v2i64, v2i64, bc_v2i64>;
3629 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3630 VR128, v8i16, v8i16, bc_v8i16>;
3631 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3632 VR128, v4i32, v4i32, bc_v4i32>;
3634 let ExeDomain = SSEPackedInt in {
3635 // 128-bit logical shifts.
3636 def PSLLDQri : PDIi8<0x73, MRM7r,
3637 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3638 "pslldq\t{$src2, $dst|$dst, $src2}",
3640 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
3641 def PSRLDQri : PDIi8<0x73, MRM3r,
3642 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3643 "psrldq\t{$src2, $dst|$dst, $src2}",
3645 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
3646 // PSRADQri doesn't exist in SSE[1-3].
3648 } // Constraints = "$src1 = $dst"
3650 let Predicates = [HasAVX] in {
3651 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3652 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3653 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3654 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3655 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3656 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3658 // Shift up / down and insert zero's.
3659 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3660 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3661 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3662 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3665 let Predicates = [HasAVX2] in {
3666 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
3667 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3668 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
3669 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3672 let Predicates = [HasSSE2] in {
3673 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3674 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3675 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3676 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3677 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3678 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3680 // Shift up / down and insert zero's.
3681 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3682 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3683 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3684 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3687 //===---------------------------------------------------------------------===//
3688 // SSE2 - Packed Integer Comparison Instructions
3689 //===---------------------------------------------------------------------===//
3691 let Predicates = [HasAVX] in {
3692 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
3693 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3694 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
3695 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3696 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
3697 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3698 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
3699 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3700 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
3701 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3702 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
3703 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3706 let Predicates = [HasAVX2] in {
3707 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
3708 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3709 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
3710 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3711 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
3712 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3713 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
3714 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3715 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
3716 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3717 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
3718 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3721 let Constraints = "$src1 = $dst" in {
3722 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
3723 VR128, memopv2i64, i128mem, 1>;
3724 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
3725 VR128, memopv2i64, i128mem, 1>;
3726 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
3727 VR128, memopv2i64, i128mem, 1>;
3728 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
3729 VR128, memopv2i64, i128mem>;
3730 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
3731 VR128, memopv2i64, i128mem>;
3732 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
3733 VR128, memopv2i64, i128mem>;
3734 } // Constraints = "$src1 = $dst"
3736 //===---------------------------------------------------------------------===//
3737 // SSE2 - Packed Integer Pack Instructions
3738 //===---------------------------------------------------------------------===//
3740 let Predicates = [HasAVX] in {
3741 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3742 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3743 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3744 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3745 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3746 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3749 let Predicates = [HasAVX2] in {
3750 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
3751 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3752 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
3753 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3754 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
3755 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3758 let Constraints = "$src1 = $dst" in {
3759 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
3760 VR128, memopv2i64, i128mem>;
3761 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
3762 VR128, memopv2i64, i128mem>;
3763 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
3764 VR128, memopv2i64, i128mem>;
3765 } // Constraints = "$src1 = $dst"
3767 //===---------------------------------------------------------------------===//
3768 // SSE2 - Packed Integer Shuffle Instructions
3769 //===---------------------------------------------------------------------===//
3771 let ExeDomain = SSEPackedInt in {
3772 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
3773 def ri : Ii8<0x70, MRMSrcReg,
3774 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3775 !strconcat(OpcodeStr,
3776 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3777 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))]>;
3778 def mi : Ii8<0x70, MRMSrcMem,
3779 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3780 !strconcat(OpcodeStr,
3781 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3783 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
3784 (i8 imm:$src2))))]>;
3787 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
3788 def Yri : Ii8<0x70, MRMSrcReg,
3789 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
3790 !strconcat(OpcodeStr,
3791 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3792 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
3793 def Ymi : Ii8<0x70, MRMSrcMem,
3794 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
3795 !strconcat(OpcodeStr,
3796 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3798 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
3799 (i8 imm:$src2))))]>;
3801 } // ExeDomain = SSEPackedInt
3803 let Predicates = [HasAVX] in {
3804 let AddedComplexity = 5 in
3805 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
3807 // SSE2 with ImmT == Imm8 and XS prefix.
3808 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
3810 // SSE2 with ImmT == Imm8 and XD prefix.
3811 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
3813 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
3814 (VPSHUFDmi addr:$src1, imm:$imm)>;
3815 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3816 (VPSHUFDri VR128:$src1, imm:$imm)>;
3819 let Predicates = [HasAVX2] in {
3820 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
3821 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
3822 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
3825 let Predicates = [HasSSE2] in {
3826 let AddedComplexity = 5 in
3827 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
3829 // SSE2 with ImmT == Imm8 and XS prefix.
3830 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
3832 // SSE2 with ImmT == Imm8 and XD prefix.
3833 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
3835 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
3836 (PSHUFDmi addr:$src1, imm:$imm)>;
3837 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3838 (PSHUFDri VR128:$src1, imm:$imm)>;
3841 //===---------------------------------------------------------------------===//
3842 // SSE2 - Packed Integer Unpack Instructions
3843 //===---------------------------------------------------------------------===//
3845 let ExeDomain = SSEPackedInt in {
3846 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3847 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3848 def rr : PDI<opc, MRMSrcReg,
3849 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3851 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3852 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3853 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3854 def rm : PDI<opc, MRMSrcMem,
3855 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3857 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3858 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3859 [(set VR128:$dst, (OpNode VR128:$src1,
3860 (bc_frag (memopv2i64
3864 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
3865 SDNode OpNode, PatFrag bc_frag> {
3866 def Yrr : PDI<opc, MRMSrcReg,
3867 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
3868 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3869 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
3870 def Yrm : PDI<opc, MRMSrcMem,
3871 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
3872 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3873 [(set VR256:$dst, (OpNode VR256:$src1,
3874 (bc_frag (memopv4i64 addr:$src2))))]>;
3877 let Predicates = [HasAVX] in {
3878 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
3879 bc_v16i8, 0>, VEX_4V;
3880 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
3881 bc_v8i16, 0>, VEX_4V;
3882 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
3883 bc_v4i32, 0>, VEX_4V;
3884 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
3885 bc_v2i64, 0>, VEX_4V;
3887 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
3888 bc_v16i8, 0>, VEX_4V;
3889 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
3890 bc_v8i16, 0>, VEX_4V;
3891 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
3892 bc_v4i32, 0>, VEX_4V;
3893 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
3894 bc_v2i64, 0>, VEX_4V;
3897 let Predicates = [HasAVX2] in {
3898 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
3900 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
3902 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
3904 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
3907 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
3909 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
3911 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
3913 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
3917 let Constraints = "$src1 = $dst" in {
3918 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
3920 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
3922 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
3924 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
3927 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
3929 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
3931 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
3933 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
3936 } // ExeDomain = SSEPackedInt
3938 // Patterns for using AVX1 instructions with integer vectors
3939 // Here to give AVX2 priority
3940 let Predicates = [HasAVX] in {
3941 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
3942 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
3943 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
3944 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
3945 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
3946 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
3947 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
3948 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
3950 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
3951 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
3952 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
3953 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
3954 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
3955 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
3956 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
3957 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
3960 //===---------------------------------------------------------------------===//
3961 // SSE2 - Packed Integer Extract and Insert
3962 //===---------------------------------------------------------------------===//
3964 let ExeDomain = SSEPackedInt in {
3965 multiclass sse2_pinsrw<bit Is2Addr = 1> {
3966 def rri : Ii8<0xC4, MRMSrcReg,
3967 (outs VR128:$dst), (ins VR128:$src1,
3968 GR32:$src2, i32i8imm:$src3),
3970 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3971 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3973 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
3974 def rmi : Ii8<0xC4, MRMSrcMem,
3975 (outs VR128:$dst), (ins VR128:$src1,
3976 i16mem:$src2, i32i8imm:$src3),
3978 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3979 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3981 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
3986 let Predicates = [HasAVX] in
3987 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
3988 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3989 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3990 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3991 imm:$src2))]>, TB, OpSize, VEX;
3992 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
3993 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3994 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3995 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3999 let Predicates = [HasAVX] in {
4000 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4001 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4002 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4003 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4004 []>, TB, OpSize, VEX_4V;
4007 let Constraints = "$src1 = $dst" in
4008 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4010 } // ExeDomain = SSEPackedInt
4012 //===---------------------------------------------------------------------===//
4013 // SSE2 - Packed Mask Creation
4014 //===---------------------------------------------------------------------===//
4016 let ExeDomain = SSEPackedInt in {
4018 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4019 "pmovmskb\t{$src, $dst|$dst, $src}",
4020 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4021 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4022 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4024 let Predicates = [HasAVX2] in {
4025 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4026 "pmovmskb\t{$src, $dst|$dst, $src}",
4027 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4028 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4029 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4032 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4033 "pmovmskb\t{$src, $dst|$dst, $src}",
4034 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4036 } // ExeDomain = SSEPackedInt
4038 //===---------------------------------------------------------------------===//
4039 // SSE2 - Conditional Store
4040 //===---------------------------------------------------------------------===//
4042 let ExeDomain = SSEPackedInt in {
4045 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4046 (ins VR128:$src, VR128:$mask),
4047 "maskmovdqu\t{$mask, $src|$src, $mask}",
4048 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4050 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4051 (ins VR128:$src, VR128:$mask),
4052 "maskmovdqu\t{$mask, $src|$src, $mask}",
4053 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4056 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4057 "maskmovdqu\t{$mask, $src|$src, $mask}",
4058 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4060 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4061 "maskmovdqu\t{$mask, $src|$src, $mask}",
4062 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4064 } // ExeDomain = SSEPackedInt
4066 //===---------------------------------------------------------------------===//
4067 // SSE2 - Move Doubleword
4068 //===---------------------------------------------------------------------===//
4070 //===---------------------------------------------------------------------===//
4071 // Move Int Doubleword to Packed Double Int
4073 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4074 "movd\t{$src, $dst|$dst, $src}",
4076 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4077 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4078 "movd\t{$src, $dst|$dst, $src}",
4080 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4082 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4083 "mov{d|q}\t{$src, $dst|$dst, $src}",
4085 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4086 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4087 "mov{d|q}\t{$src, $dst|$dst, $src}",
4088 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4090 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4091 "movd\t{$src, $dst|$dst, $src}",
4093 (v4i32 (scalar_to_vector GR32:$src)))]>;
4094 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4095 "movd\t{$src, $dst|$dst, $src}",
4097 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4098 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4099 "mov{d|q}\t{$src, $dst|$dst, $src}",
4101 (v2i64 (scalar_to_vector GR64:$src)))]>;
4102 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4103 "mov{d|q}\t{$src, $dst|$dst, $src}",
4104 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4106 //===---------------------------------------------------------------------===//
4107 // Move Int Doubleword to Single Scalar
4109 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4110 "movd\t{$src, $dst|$dst, $src}",
4111 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4113 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4114 "movd\t{$src, $dst|$dst, $src}",
4115 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4117 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4118 "movd\t{$src, $dst|$dst, $src}",
4119 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4121 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4122 "movd\t{$src, $dst|$dst, $src}",
4123 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4125 //===---------------------------------------------------------------------===//
4126 // Move Packed Doubleword Int to Packed Double Int
4128 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4129 "movd\t{$src, $dst|$dst, $src}",
4130 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4132 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4133 (ins i32mem:$dst, VR128:$src),
4134 "movd\t{$src, $dst|$dst, $src}",
4135 [(store (i32 (vector_extract (v4i32 VR128:$src),
4136 (iPTR 0))), addr:$dst)]>, VEX;
4137 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4138 "movd\t{$src, $dst|$dst, $src}",
4139 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4141 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4142 "movd\t{$src, $dst|$dst, $src}",
4143 [(store (i32 (vector_extract (v4i32 VR128:$src),
4144 (iPTR 0))), addr:$dst)]>;
4146 //===---------------------------------------------------------------------===//
4147 // Move Packed Doubleword Int first element to Doubleword Int
4149 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4150 "mov{d|q}\t{$src, $dst|$dst, $src}",
4151 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4153 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4155 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4156 "mov{d|q}\t{$src, $dst|$dst, $src}",
4157 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4160 //===---------------------------------------------------------------------===//
4161 // Bitcast FR64 <-> GR64
4163 let Predicates = [HasAVX] in
4164 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4165 "vmovq\t{$src, $dst|$dst, $src}",
4166 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4168 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4169 "mov{d|q}\t{$src, $dst|$dst, $src}",
4170 [(set GR64:$dst, (bitconvert FR64:$src))]>, VEX;
4171 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4172 "movq\t{$src, $dst|$dst, $src}",
4173 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>,
4176 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4177 "movq\t{$src, $dst|$dst, $src}",
4178 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4179 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4180 "mov{d|q}\t{$src, $dst|$dst, $src}",
4181 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4182 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4183 "movq\t{$src, $dst|$dst, $src}",
4184 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4186 //===---------------------------------------------------------------------===//
4187 // Move Scalar Single to Double Int
4189 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4190 "movd\t{$src, $dst|$dst, $src}",
4191 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4192 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4193 "movd\t{$src, $dst|$dst, $src}",
4194 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4195 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4196 "movd\t{$src, $dst|$dst, $src}",
4197 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4198 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4199 "movd\t{$src, $dst|$dst, $src}",
4200 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4202 //===---------------------------------------------------------------------===//
4203 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4205 let AddedComplexity = 15 in {
4206 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4207 "movd\t{$src, $dst|$dst, $src}",
4208 [(set VR128:$dst, (v4i32 (X86vzmovl
4209 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4211 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4212 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4213 [(set VR128:$dst, (v2i64 (X86vzmovl
4214 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4217 let AddedComplexity = 15 in {
4218 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4219 "movd\t{$src, $dst|$dst, $src}",
4220 [(set VR128:$dst, (v4i32 (X86vzmovl
4221 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4222 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4223 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4224 [(set VR128:$dst, (v2i64 (X86vzmovl
4225 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4228 let AddedComplexity = 20 in {
4229 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4230 "movd\t{$src, $dst|$dst, $src}",
4232 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4233 (loadi32 addr:$src))))))]>,
4235 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4236 "movd\t{$src, $dst|$dst, $src}",
4238 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4239 (loadi32 addr:$src))))))]>;
4242 let Predicates = [HasAVX] in {
4243 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4244 let AddedComplexity = 20 in {
4245 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4246 (VMOVZDI2PDIrm addr:$src)>;
4247 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4248 (VMOVZDI2PDIrm addr:$src)>;
4250 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4251 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4252 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4253 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4254 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4255 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4256 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4259 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4260 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4261 (MOVZDI2PDIrm addr:$src)>;
4262 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4263 (MOVZDI2PDIrm addr:$src)>;
4266 // These are the correct encodings of the instructions so that we know how to
4267 // read correct assembly, even though we continue to emit the wrong ones for
4268 // compatibility with Darwin's buggy assembler.
4269 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4270 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4271 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4272 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4273 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4274 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4275 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4276 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4277 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4278 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4279 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4280 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4282 //===---------------------------------------------------------------------===//
4283 // SSE2 - Move Quadword
4284 //===---------------------------------------------------------------------===//
4286 //===---------------------------------------------------------------------===//
4287 // Move Quadword Int to Packed Quadword Int
4289 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4290 "vmovq\t{$src, $dst|$dst, $src}",
4292 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4293 VEX, Requires<[HasAVX]>;
4294 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4295 "movq\t{$src, $dst|$dst, $src}",
4297 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4298 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4300 //===---------------------------------------------------------------------===//
4301 // Move Packed Quadword Int to Quadword Int
4303 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4304 "movq\t{$src, $dst|$dst, $src}",
4305 [(store (i64 (vector_extract (v2i64 VR128:$src),
4306 (iPTR 0))), addr:$dst)]>, VEX;
4307 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4308 "movq\t{$src, $dst|$dst, $src}",
4309 [(store (i64 (vector_extract (v2i64 VR128:$src),
4310 (iPTR 0))), addr:$dst)]>;
4312 //===---------------------------------------------------------------------===//
4313 // Store / copy lower 64-bits of a XMM register.
4315 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4316 "movq\t{$src, $dst|$dst, $src}",
4317 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4318 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4319 "movq\t{$src, $dst|$dst, $src}",
4320 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4322 let AddedComplexity = 20 in
4323 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4324 "vmovq\t{$src, $dst|$dst, $src}",
4326 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4327 (loadi64 addr:$src))))))]>,
4328 XS, VEX, Requires<[HasAVX]>;
4330 let AddedComplexity = 20 in
4331 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4332 "movq\t{$src, $dst|$dst, $src}",
4334 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4335 (loadi64 addr:$src))))))]>,
4336 XS, Requires<[HasSSE2]>;
4338 let Predicates = [HasAVX], AddedComplexity = 20 in {
4339 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4340 (VMOVZQI2PQIrm addr:$src)>;
4341 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4342 (VMOVZQI2PQIrm addr:$src)>;
4343 def : Pat<(v2i64 (X86vzload addr:$src)),
4344 (VMOVZQI2PQIrm addr:$src)>;
4347 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4348 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4349 (MOVZQI2PQIrm addr:$src)>;
4350 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4351 (MOVZQI2PQIrm addr:$src)>;
4352 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4355 let Predicates = [HasAVX] in {
4356 def : Pat<(v4i64 (X86vzload addr:$src)),
4357 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4360 //===---------------------------------------------------------------------===//
4361 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4362 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4364 let AddedComplexity = 15 in
4365 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4366 "vmovq\t{$src, $dst|$dst, $src}",
4367 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4368 XS, VEX, Requires<[HasAVX]>;
4369 let AddedComplexity = 15 in
4370 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4371 "movq\t{$src, $dst|$dst, $src}",
4372 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4373 XS, Requires<[HasSSE2]>;
4375 let AddedComplexity = 20 in
4376 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4377 "vmovq\t{$src, $dst|$dst, $src}",
4378 [(set VR128:$dst, (v2i64 (X86vzmovl
4379 (loadv2i64 addr:$src))))]>,
4380 XS, VEX, Requires<[HasAVX]>;
4381 let AddedComplexity = 20 in {
4382 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4383 "movq\t{$src, $dst|$dst, $src}",
4384 [(set VR128:$dst, (v2i64 (X86vzmovl
4385 (loadv2i64 addr:$src))))]>,
4386 XS, Requires<[HasSSE2]>;
4389 let AddedComplexity = 20 in {
4390 let Predicates = [HasAVX] in {
4391 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4392 (VMOVZPQILo2PQIrm addr:$src)>;
4393 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4394 (VMOVZPQILo2PQIrr VR128:$src)>;
4396 let Predicates = [HasSSE2] in {
4397 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4398 (MOVZPQILo2PQIrm addr:$src)>;
4399 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4400 (MOVZPQILo2PQIrr VR128:$src)>;
4404 // Instructions to match in the assembler
4405 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4406 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4407 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4408 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4409 // Recognize "movd" with GR64 destination, but encode as a "movq"
4410 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4411 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4413 // Instructions for the disassembler
4414 // xr = XMM register
4417 let Predicates = [HasAVX] in
4418 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4419 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4420 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4421 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4423 //===---------------------------------------------------------------------===//
4424 // SSE3 - Conversion Instructions
4425 //===---------------------------------------------------------------------===//
4427 // Convert Packed Double FP to Packed DW Integers
4428 let Predicates = [HasAVX] in {
4429 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4430 // register, but the same isn't true when using memory operands instead.
4431 // Provide other assembly rr and rm forms to address this explicitly.
4432 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4433 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4434 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4435 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4438 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4439 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4440 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4441 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4444 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4445 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4446 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4447 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4450 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4451 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4452 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4453 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4455 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4456 (VCVTTPD2DQYrr VR256:$src)>;
4457 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4458 (VCVTTPD2DQYrm addr:$src)>;
4460 // Convert Packed DW Integers to Packed Double FP
4461 let Predicates = [HasAVX] in {
4462 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4463 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4464 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4465 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4466 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4467 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4468 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4469 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4472 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4473 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4474 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4475 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4477 // AVX 256-bit register conversion intrinsics
4478 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4479 (VCVTDQ2PDYrr VR128:$src)>;
4480 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
4481 (VCVTDQ2PDYrm addr:$src)>;
4483 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4484 (VCVTPD2DQYrr VR256:$src)>;
4485 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4486 (VCVTPD2DQYrm addr:$src)>;
4488 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4489 (VCVTDQ2PDYrr VR128:$src)>;
4490 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
4491 (VCVTDQ2PDYrm addr:$src)>;
4493 //===---------------------------------------------------------------------===//
4494 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4495 //===---------------------------------------------------------------------===//
4496 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4497 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4498 X86MemOperand x86memop> {
4499 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4500 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4501 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4502 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4503 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4504 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4507 let Predicates = [HasAVX] in {
4508 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4509 v4f32, VR128, memopv4f32, f128mem>, VEX;
4510 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4511 v4f32, VR128, memopv4f32, f128mem>, VEX;
4512 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4513 v8f32, VR256, memopv8f32, f256mem>, VEX;
4514 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4515 v8f32, VR256, memopv8f32, f256mem>, VEX;
4517 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4518 memopv4f32, f128mem>;
4519 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4520 memopv4f32, f128mem>;
4522 let Predicates = [HasAVX] in {
4523 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4524 (VMOVSHDUPrr VR128:$src)>;
4525 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4526 (VMOVSHDUPrm addr:$src)>;
4527 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4528 (VMOVSLDUPrr VR128:$src)>;
4529 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4530 (VMOVSLDUPrm addr:$src)>;
4531 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4532 (VMOVSHDUPYrr VR256:$src)>;
4533 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4534 (VMOVSHDUPYrm addr:$src)>;
4535 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4536 (VMOVSLDUPYrr VR256:$src)>;
4537 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4538 (VMOVSLDUPYrm addr:$src)>;
4541 let Predicates = [HasSSE3] in {
4542 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4543 (MOVSHDUPrr VR128:$src)>;
4544 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4545 (MOVSHDUPrm addr:$src)>;
4546 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4547 (MOVSLDUPrr VR128:$src)>;
4548 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4549 (MOVSLDUPrm addr:$src)>;
4552 //===---------------------------------------------------------------------===//
4553 // SSE3 - Replicate Double FP - MOVDDUP
4554 //===---------------------------------------------------------------------===//
4556 multiclass sse3_replicate_dfp<string OpcodeStr> {
4557 let neverHasSideEffects = 1 in
4558 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4559 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4561 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4562 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4565 (scalar_to_vector (loadf64 addr:$src)))))]>;
4568 // FIXME: Merge with above classe when there're patterns for the ymm version
4569 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4570 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4571 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4572 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4573 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4577 (scalar_to_vector (loadf64 addr:$src)))))]>;
4580 let Predicates = [HasAVX] in {
4581 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4582 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4585 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4587 let Predicates = [HasAVX] in {
4588 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4589 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4590 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4591 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4592 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4593 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4594 def : Pat<(X86Movddup (bc_v2f64
4595 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4596 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4599 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4600 (VMOVDDUPYrm addr:$src)>;
4601 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4602 (VMOVDDUPYrm addr:$src)>;
4603 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4604 (VMOVDDUPYrm addr:$src)>;
4605 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4606 (VMOVDDUPYrr VR256:$src)>;
4609 let Predicates = [HasSSE3] in {
4610 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4611 (MOVDDUPrm addr:$src)>;
4612 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4613 (MOVDDUPrm addr:$src)>;
4614 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4615 (MOVDDUPrm addr:$src)>;
4616 def : Pat<(X86Movddup (bc_v2f64
4617 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4618 (MOVDDUPrm addr:$src)>;
4621 //===---------------------------------------------------------------------===//
4622 // SSE3 - Move Unaligned Integer
4623 //===---------------------------------------------------------------------===//
4625 let Predicates = [HasAVX] in {
4626 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4627 "vlddqu\t{$src, $dst|$dst, $src}",
4628 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4629 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4630 "vlddqu\t{$src, $dst|$dst, $src}",
4631 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4633 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4634 "lddqu\t{$src, $dst|$dst, $src}",
4635 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4637 //===---------------------------------------------------------------------===//
4638 // SSE3 - Arithmetic
4639 //===---------------------------------------------------------------------===//
4641 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4642 X86MemOperand x86memop, bit Is2Addr = 1> {
4643 def rr : I<0xD0, MRMSrcReg,
4644 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4646 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4647 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4648 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4649 def rm : I<0xD0, MRMSrcMem,
4650 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4652 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4653 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4654 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4657 let Predicates = [HasAVX] in {
4658 let ExeDomain = SSEPackedSingle in {
4659 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4660 f128mem, 0>, TB, XD, VEX_4V;
4661 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4662 f256mem, 0>, TB, XD, VEX_4V;
4664 let ExeDomain = SSEPackedDouble in {
4665 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4666 f128mem, 0>, TB, OpSize, VEX_4V;
4667 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4668 f256mem, 0>, TB, OpSize, VEX_4V;
4671 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
4672 let ExeDomain = SSEPackedSingle in
4673 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4675 let ExeDomain = SSEPackedDouble in
4676 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4677 f128mem>, TB, OpSize;
4680 //===---------------------------------------------------------------------===//
4681 // SSE3 Instructions
4682 //===---------------------------------------------------------------------===//
4685 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4686 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4687 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4689 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4690 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4691 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4693 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4695 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4696 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4697 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4699 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4700 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4701 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4703 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4704 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4705 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4707 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4709 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4710 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4711 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4714 let Predicates = [HasAVX] in {
4715 let ExeDomain = SSEPackedSingle in {
4716 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4717 X86fhadd, 0>, VEX_4V;
4718 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4719 X86fhsub, 0>, VEX_4V;
4720 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4721 X86fhadd, 0>, VEX_4V;
4722 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4723 X86fhsub, 0>, VEX_4V;
4725 let ExeDomain = SSEPackedDouble in {
4726 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4727 X86fhadd, 0>, VEX_4V;
4728 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4729 X86fhsub, 0>, VEX_4V;
4730 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4731 X86fhadd, 0>, VEX_4V;
4732 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4733 X86fhsub, 0>, VEX_4V;
4737 let Constraints = "$src1 = $dst" in {
4738 let ExeDomain = SSEPackedSingle in {
4739 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
4740 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
4742 let ExeDomain = SSEPackedDouble in {
4743 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
4744 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
4748 //===---------------------------------------------------------------------===//
4749 // SSSE3 - Packed Absolute Instructions
4750 //===---------------------------------------------------------------------===//
4753 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4754 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4755 Intrinsic IntId128> {
4756 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4758 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4759 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4762 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4764 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4767 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
4770 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4771 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
4772 Intrinsic IntId256> {
4773 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4775 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4776 [(set VR256:$dst, (IntId256 VR256:$src))]>,
4779 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
4781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4784 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
4787 let Predicates = [HasAVX] in {
4788 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
4789 int_x86_ssse3_pabs_b_128>, VEX;
4790 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
4791 int_x86_ssse3_pabs_w_128>, VEX;
4792 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
4793 int_x86_ssse3_pabs_d_128>, VEX;
4796 let Predicates = [HasAVX2] in {
4797 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
4798 int_x86_avx2_pabs_b>, VEX;
4799 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
4800 int_x86_avx2_pabs_w>, VEX;
4801 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
4802 int_x86_avx2_pabs_d>, VEX;
4805 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
4806 int_x86_ssse3_pabs_b_128>;
4807 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
4808 int_x86_ssse3_pabs_w_128>;
4809 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
4810 int_x86_ssse3_pabs_d_128>;
4812 //===---------------------------------------------------------------------===//
4813 // SSSE3 - Packed Binary Operator Instructions
4814 //===---------------------------------------------------------------------===//
4816 /// SS3I_binop_rm - Simple SSSE3 bin op
4817 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4818 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
4819 X86MemOperand x86memop, bit Is2Addr = 1> {
4820 let isCommutable = 1 in
4821 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
4822 (ins RC:$src1, RC:$src2),
4824 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4826 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
4828 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
4829 (ins RC:$src1, x86memop:$src2),
4831 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4832 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4834 (OpVT (OpNode RC:$src1,
4835 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
4838 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4839 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4840 Intrinsic IntId128, bit Is2Addr = 1> {
4841 let isCommutable = 1 in
4842 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4843 (ins VR128:$src1, VR128:$src2),
4845 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4847 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4849 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4850 (ins VR128:$src1, i128mem:$src2),
4852 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4853 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4855 (IntId128 VR128:$src1,
4856 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
4859 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
4860 Intrinsic IntId256> {
4861 let isCommutable = 1 in
4862 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4863 (ins VR256:$src1, VR256:$src2),
4864 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4865 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
4867 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
4868 (ins VR256:$src1, i256mem:$src2),
4869 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4871 (IntId256 VR256:$src1,
4872 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
4875 let ImmT = NoImm, Predicates = [HasAVX] in {
4876 let isCommutable = 0 in {
4877 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
4878 memopv2i64, i128mem, 0>, VEX_4V;
4879 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
4880 memopv2i64, i128mem, 0>, VEX_4V;
4881 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
4882 memopv2i64, i128mem, 0>, VEX_4V;
4883 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
4884 memopv2i64, i128mem, 0>, VEX_4V;
4885 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
4886 memopv2i64, i128mem, 0>, VEX_4V;
4887 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
4888 memopv2i64, i128mem, 0>, VEX_4V;
4889 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
4890 memopv2i64, i128mem, 0>, VEX_4V;
4891 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
4892 memopv2i64, i128mem, 0>, VEX_4V;
4893 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
4894 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4895 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
4896 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4897 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
4898 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4900 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
4901 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4904 let ImmT = NoImm, Predicates = [HasAVX2] in {
4905 let isCommutable = 0 in {
4906 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
4907 memopv4i64, i256mem, 0>, VEX_4V;
4908 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
4909 memopv4i64, i256mem, 0>, VEX_4V;
4910 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
4911 memopv4i64, i256mem, 0>, VEX_4V;
4912 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
4913 memopv4i64, i256mem, 0>, VEX_4V;
4914 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
4915 memopv4i64, i256mem, 0>, VEX_4V;
4916 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
4917 memopv4i64, i256mem, 0>, VEX_4V;
4918 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
4919 memopv4i64, i256mem, 0>, VEX_4V;
4920 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
4921 memopv4i64, i256mem, 0>, VEX_4V;
4922 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
4923 int_x86_avx2_phadd_sw>, VEX_4V;
4924 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
4925 int_x86_avx2_phsub_sw>, VEX_4V;
4926 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
4927 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
4929 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
4930 int_x86_avx2_pmul_hr_sw>, VEX_4V;
4933 // None of these have i8 immediate fields.
4934 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
4935 let isCommutable = 0 in {
4936 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
4937 memopv2i64, i128mem>;
4938 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
4939 memopv2i64, i128mem>;
4940 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
4941 memopv2i64, i128mem>;
4942 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
4943 memopv2i64, i128mem>;
4944 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
4945 memopv2i64, i128mem>;
4946 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
4947 memopv2i64, i128mem>;
4948 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
4949 memopv2i64, i128mem>;
4950 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
4951 memopv2i64, i128mem>;
4952 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
4953 int_x86_ssse3_phadd_sw_128>;
4954 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
4955 int_x86_ssse3_phsub_sw_128>;
4956 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
4957 int_x86_ssse3_pmadd_ub_sw_128>;
4959 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
4960 int_x86_ssse3_pmul_hr_sw_128>;
4963 //===---------------------------------------------------------------------===//
4964 // SSSE3 - Packed Align Instruction Patterns
4965 //===---------------------------------------------------------------------===//
4967 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
4968 let neverHasSideEffects = 1 in {
4969 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
4970 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4972 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4974 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4977 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
4978 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4980 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4982 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4987 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
4988 let neverHasSideEffects = 1 in {
4989 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
4990 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
4992 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4995 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
4996 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
4998 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5003 let Predicates = [HasAVX] in
5004 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5005 let Predicates = [HasAVX2] in
5006 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5007 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5008 defm PALIGN : ssse3_palign<"palignr">;
5010 let Predicates = [HasAVX2] in {
5011 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5012 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5013 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5014 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5015 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5016 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5017 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5018 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5021 let Predicates = [HasAVX] in {
5022 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5023 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5024 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5025 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5026 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5027 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5028 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5029 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5032 let Predicates = [HasSSSE3] in {
5033 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5034 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5035 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5036 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5037 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5038 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5039 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5040 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5043 //===---------------------------------------------------------------------===//
5044 // SSSE3 - Thread synchronization
5045 //===---------------------------------------------------------------------===//
5047 let usesCustomInserter = 1 in {
5048 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5049 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5050 Requires<[HasSSE3]>;
5051 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5052 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5053 Requires<[HasSSE3]>;
5056 let Uses = [EAX, ECX, EDX] in
5057 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
5058 Requires<[HasSSE3]>;
5059 let Uses = [ECX, EAX] in
5060 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
5061 Requires<[HasSSE3]>;
5063 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5064 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5066 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5067 Requires<[In32BitMode]>;
5068 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5069 Requires<[In64BitMode]>;
5071 //===----------------------------------------------------------------------===//
5072 // SSE4.1 - Packed Move with Sign/Zero Extend
5073 //===----------------------------------------------------------------------===//
5075 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5076 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5077 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5078 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5080 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5081 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5083 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5087 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5089 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5090 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5091 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5093 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5094 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5095 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5098 let Predicates = [HasAVX] in {
5099 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5101 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5103 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5105 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5107 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5109 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5113 let Predicates = [HasAVX2] in {
5114 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5115 int_x86_avx2_pmovsxbw>, VEX;
5116 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5117 int_x86_avx2_pmovsxwd>, VEX;
5118 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5119 int_x86_avx2_pmovsxdq>, VEX;
5120 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5121 int_x86_avx2_pmovzxbw>, VEX;
5122 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5123 int_x86_avx2_pmovzxwd>, VEX;
5124 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5125 int_x86_avx2_pmovzxdq>, VEX;
5128 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5129 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5130 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5131 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5132 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5133 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5135 let Predicates = [HasAVX] in {
5136 // Common patterns involving scalar load.
5137 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5138 (VPMOVSXBWrm addr:$src)>;
5139 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5140 (VPMOVSXBWrm addr:$src)>;
5142 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5143 (VPMOVSXWDrm addr:$src)>;
5144 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5145 (VPMOVSXWDrm addr:$src)>;
5147 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5148 (VPMOVSXDQrm addr:$src)>;
5149 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5150 (VPMOVSXDQrm addr:$src)>;
5152 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5153 (VPMOVZXBWrm addr:$src)>;
5154 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5155 (VPMOVZXBWrm addr:$src)>;
5157 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5158 (VPMOVZXWDrm addr:$src)>;
5159 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5160 (VPMOVZXWDrm addr:$src)>;
5162 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5163 (VPMOVZXDQrm addr:$src)>;
5164 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5165 (VPMOVZXDQrm addr:$src)>;
5168 let Predicates = [HasSSE41] in {
5169 // Common patterns involving scalar load.
5170 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5171 (PMOVSXBWrm addr:$src)>;
5172 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5173 (PMOVSXBWrm addr:$src)>;
5175 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5176 (PMOVSXWDrm addr:$src)>;
5177 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5178 (PMOVSXWDrm addr:$src)>;
5180 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5181 (PMOVSXDQrm addr:$src)>;
5182 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5183 (PMOVSXDQrm addr:$src)>;
5185 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5186 (PMOVZXBWrm addr:$src)>;
5187 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5188 (PMOVZXBWrm addr:$src)>;
5190 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5191 (PMOVZXWDrm addr:$src)>;
5192 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5193 (PMOVZXWDrm addr:$src)>;
5195 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5196 (PMOVZXDQrm addr:$src)>;
5197 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5198 (PMOVZXDQrm addr:$src)>;
5201 let Predicates = [HasAVX] in {
5202 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5203 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5206 let Predicates = [HasSSE41] in {
5207 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5208 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5212 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5213 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5214 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5215 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5217 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5218 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5220 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5224 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5226 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5227 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5228 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5230 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5231 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5233 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5237 let Predicates = [HasAVX] in {
5238 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5240 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5242 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5244 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5248 let Predicates = [HasAVX2] in {
5249 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5250 int_x86_avx2_pmovsxbd>, VEX;
5251 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5252 int_x86_avx2_pmovsxwq>, VEX;
5253 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5254 int_x86_avx2_pmovzxbd>, VEX;
5255 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5256 int_x86_avx2_pmovzxwq>, VEX;
5259 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5260 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5261 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5262 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5264 let Predicates = [HasAVX] in {
5265 // Common patterns involving scalar load
5266 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5267 (VPMOVSXBDrm addr:$src)>;
5268 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5269 (VPMOVSXWQrm addr:$src)>;
5271 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5272 (VPMOVZXBDrm addr:$src)>;
5273 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5274 (VPMOVZXWQrm addr:$src)>;
5277 let Predicates = [HasSSE41] in {
5278 // Common patterns involving scalar load
5279 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5280 (PMOVSXBDrm addr:$src)>;
5281 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5282 (PMOVSXWQrm addr:$src)>;
5284 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5285 (PMOVZXBDrm addr:$src)>;
5286 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5287 (PMOVZXWQrm addr:$src)>;
5290 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5291 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5292 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5293 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5295 // Expecting a i16 load any extended to i32 value.
5296 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5297 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5298 [(set VR128:$dst, (IntId (bitconvert
5299 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5303 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5305 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5306 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5307 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5309 // Expecting a i16 load any extended to i32 value.
5310 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5311 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5312 [(set VR256:$dst, (IntId (bitconvert
5313 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5317 let Predicates = [HasAVX] in {
5318 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5320 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5323 let Predicates = [HasAVX2] in {
5324 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5325 int_x86_avx2_pmovsxbq>, VEX;
5326 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5327 int_x86_avx2_pmovzxbq>, VEX;
5329 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5330 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5332 let Predicates = [HasAVX] in {
5333 // Common patterns involving scalar load
5334 def : Pat<(int_x86_sse41_pmovsxbq
5335 (bitconvert (v4i32 (X86vzmovl
5336 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5337 (VPMOVSXBQrm addr:$src)>;
5339 def : Pat<(int_x86_sse41_pmovzxbq
5340 (bitconvert (v4i32 (X86vzmovl
5341 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5342 (VPMOVZXBQrm addr:$src)>;
5345 let Predicates = [HasSSE41] in {
5346 // Common patterns involving scalar load
5347 def : Pat<(int_x86_sse41_pmovsxbq
5348 (bitconvert (v4i32 (X86vzmovl
5349 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5350 (PMOVSXBQrm addr:$src)>;
5352 def : Pat<(int_x86_sse41_pmovzxbq
5353 (bitconvert (v4i32 (X86vzmovl
5354 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5355 (PMOVZXBQrm addr:$src)>;
5358 //===----------------------------------------------------------------------===//
5359 // SSE4.1 - Extract Instructions
5360 //===----------------------------------------------------------------------===//
5362 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5363 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5364 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5365 (ins VR128:$src1, i32i8imm:$src2),
5366 !strconcat(OpcodeStr,
5367 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5368 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5370 let neverHasSideEffects = 1, mayStore = 1 in
5371 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5372 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5373 !strconcat(OpcodeStr,
5374 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5377 // There's an AssertZext in the way of writing the store pattern
5378 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5381 let Predicates = [HasAVX] in {
5382 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5383 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5384 (ins VR128:$src1, i32i8imm:$src2),
5385 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5388 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5391 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5392 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5393 let neverHasSideEffects = 1, mayStore = 1 in
5394 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5395 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5396 !strconcat(OpcodeStr,
5397 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5400 // There's an AssertZext in the way of writing the store pattern
5401 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5404 let Predicates = [HasAVX] in
5405 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5407 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5410 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5411 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5412 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5413 (ins VR128:$src1, i32i8imm:$src2),
5414 !strconcat(OpcodeStr,
5415 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5417 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5418 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5419 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5420 !strconcat(OpcodeStr,
5421 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5422 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5423 addr:$dst)]>, OpSize;
5426 let Predicates = [HasAVX] in
5427 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5429 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5431 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5432 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5433 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5434 (ins VR128:$src1, i32i8imm:$src2),
5435 !strconcat(OpcodeStr,
5436 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5438 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5439 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5440 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5441 !strconcat(OpcodeStr,
5442 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5443 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5444 addr:$dst)]>, OpSize, REX_W;
5447 let Predicates = [HasAVX] in
5448 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5450 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5452 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5454 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5455 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5456 (ins VR128:$src1, i32i8imm:$src2),
5457 !strconcat(OpcodeStr,
5458 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5460 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5462 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5463 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5464 !strconcat(OpcodeStr,
5465 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5466 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5467 addr:$dst)]>, OpSize;
5470 let ExeDomain = SSEPackedSingle in {
5471 let Predicates = [HasAVX] in {
5472 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5473 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5474 (ins VR128:$src1, i32i8imm:$src2),
5475 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5478 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5481 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5482 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5485 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5487 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5490 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5491 Requires<[HasSSE41]>;
5493 //===----------------------------------------------------------------------===//
5494 // SSE4.1 - Insert Instructions
5495 //===----------------------------------------------------------------------===//
5497 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5498 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5499 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5501 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5503 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5505 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5506 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5507 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5509 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5511 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5513 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5514 imm:$src3))]>, OpSize;
5517 let Predicates = [HasAVX] in
5518 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5519 let Constraints = "$src1 = $dst" in
5520 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5522 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5523 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5524 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5526 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5528 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5530 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5532 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5533 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5535 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5537 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5539 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5540 imm:$src3)))]>, OpSize;
5543 let Predicates = [HasAVX] in
5544 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5545 let Constraints = "$src1 = $dst" in
5546 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5548 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5549 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5550 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5552 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5554 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5556 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5558 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5559 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5561 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5563 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5565 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5566 imm:$src3)))]>, OpSize;
5569 let Predicates = [HasAVX] in
5570 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5571 let Constraints = "$src1 = $dst" in
5572 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5574 // insertps has a few different modes, there's the first two here below which
5575 // are optimized inserts that won't zero arbitrary elements in the destination
5576 // vector. The next one matches the intrinsic and could zero arbitrary elements
5577 // in the target vector.
5578 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5579 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5580 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5582 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5584 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5586 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5588 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5589 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5591 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5593 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5595 (X86insrtps VR128:$src1,
5596 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5597 imm:$src3))]>, OpSize;
5600 let ExeDomain = SSEPackedSingle in {
5601 let Predicates = [HasAVX] in
5602 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5603 let Constraints = "$src1 = $dst" in
5604 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5607 //===----------------------------------------------------------------------===//
5608 // SSE4.1 - Round Instructions
5609 //===----------------------------------------------------------------------===//
5611 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5612 X86MemOperand x86memop, RegisterClass RC,
5613 PatFrag mem_frag32, PatFrag mem_frag64,
5614 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5615 let ExeDomain = SSEPackedSingle in {
5616 // Intrinsic operation, reg.
5617 // Vector intrinsic operation, reg
5618 def PSr : SS4AIi8<opcps, MRMSrcReg,
5619 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5620 !strconcat(OpcodeStr,
5621 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5622 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5625 // Vector intrinsic operation, mem
5626 def PSm : SS4AIi8<opcps, MRMSrcMem,
5627 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5628 !strconcat(OpcodeStr,
5629 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5631 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5633 } // ExeDomain = SSEPackedSingle
5635 let ExeDomain = SSEPackedDouble in {
5636 // Vector intrinsic operation, reg
5637 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5638 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5639 !strconcat(OpcodeStr,
5640 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5641 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5644 // Vector intrinsic operation, mem
5645 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5646 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5647 !strconcat(OpcodeStr,
5648 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5650 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5652 } // ExeDomain = SSEPackedDouble
5655 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5658 Intrinsic F64Int, bit Is2Addr = 1> {
5659 let ExeDomain = GenericDomain in {
5661 def SSr : SS4AIi8<opcss, MRMSrcReg,
5662 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
5664 !strconcat(OpcodeStr,
5665 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5666 !strconcat(OpcodeStr,
5667 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5670 // Intrinsic operation, reg.
5671 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
5672 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5674 !strconcat(OpcodeStr,
5675 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5676 !strconcat(OpcodeStr,
5677 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5678 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5681 // Intrinsic operation, mem.
5682 def SSm : SS4AIi8<opcss, MRMSrcMem,
5683 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5685 !strconcat(OpcodeStr,
5686 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5687 !strconcat(OpcodeStr,
5688 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5690 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5694 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5695 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
5697 !strconcat(OpcodeStr,
5698 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5699 !strconcat(OpcodeStr,
5700 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5703 // Intrinsic operation, reg.
5704 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
5705 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5707 !strconcat(OpcodeStr,
5708 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5709 !strconcat(OpcodeStr,
5710 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5711 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5714 // Intrinsic operation, mem.
5715 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5716 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5718 !strconcat(OpcodeStr,
5719 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5720 !strconcat(OpcodeStr,
5721 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5723 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5725 } // ExeDomain = GenericDomain
5728 // FP round - roundss, roundps, roundsd, roundpd
5729 let Predicates = [HasAVX] in {
5731 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5732 memopv4f32, memopv2f64,
5733 int_x86_sse41_round_ps,
5734 int_x86_sse41_round_pd>, VEX;
5735 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5736 memopv8f32, memopv4f64,
5737 int_x86_avx_round_ps_256,
5738 int_x86_avx_round_pd_256>, VEX;
5739 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5740 int_x86_sse41_round_ss,
5741 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
5743 def : Pat<(ffloor FR32:$src),
5744 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
5745 def : Pat<(f64 (ffloor FR64:$src)),
5746 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
5747 def : Pat<(f32 (fnearbyint FR32:$src)),
5748 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
5749 def : Pat<(f64 (fnearbyint FR64:$src)),
5750 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
5751 def : Pat<(f32 (fceil FR32:$src)),
5752 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
5753 def : Pat<(f64 (fceil FR64:$src)),
5754 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
5755 def : Pat<(f32 (frint FR32:$src)),
5756 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
5757 def : Pat<(f64 (frint FR64:$src)),
5758 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
5759 def : Pat<(f32 (ftrunc FR32:$src)),
5760 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
5761 def : Pat<(f64 (ftrunc FR64:$src)),
5762 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
5765 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5766 memopv4f32, memopv2f64,
5767 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5768 let Constraints = "$src1 = $dst" in
5769 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5770 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5772 def : Pat<(ffloor FR32:$src),
5773 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
5774 def : Pat<(f64 (ffloor FR64:$src)),
5775 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
5776 def : Pat<(f32 (fnearbyint FR32:$src)),
5777 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
5778 def : Pat<(f64 (fnearbyint FR64:$src)),
5779 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
5780 def : Pat<(f32 (fceil FR32:$src)),
5781 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
5782 def : Pat<(f64 (fceil FR64:$src)),
5783 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
5784 def : Pat<(f32 (frint FR32:$src)),
5785 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
5786 def : Pat<(f64 (frint FR64:$src)),
5787 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
5788 def : Pat<(f32 (ftrunc FR32:$src)),
5789 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
5790 def : Pat<(f64 (ftrunc FR64:$src)),
5791 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
5793 //===----------------------------------------------------------------------===//
5794 // SSE4.1 - Packed Bit Test
5795 //===----------------------------------------------------------------------===//
5797 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5798 // the intel intrinsic that corresponds to this.
5799 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5800 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5801 "vptest\t{$src2, $src1|$src1, $src2}",
5802 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5804 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5805 "vptest\t{$src2, $src1|$src1, $src2}",
5806 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5809 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5810 "vptest\t{$src2, $src1|$src1, $src2}",
5811 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5813 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5814 "vptest\t{$src2, $src1|$src1, $src2}",
5815 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5819 let Defs = [EFLAGS] in {
5820 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5821 "ptest\t{$src2, $src1|$src1, $src2}",
5822 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5824 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5825 "ptest\t{$src2, $src1|$src1, $src2}",
5826 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5830 // The bit test instructions below are AVX only
5831 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5832 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5833 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5834 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5835 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5836 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5837 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5838 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5842 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5843 let ExeDomain = SSEPackedSingle in {
5844 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5845 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5847 let ExeDomain = SSEPackedDouble in {
5848 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5849 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5853 //===----------------------------------------------------------------------===//
5854 // SSE4.1 - Misc Instructions
5855 //===----------------------------------------------------------------------===//
5857 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
5858 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5859 "popcnt{w}\t{$src, $dst|$dst, $src}",
5860 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
5862 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5863 "popcnt{w}\t{$src, $dst|$dst, $src}",
5864 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
5865 (implicit EFLAGS)]>, OpSize, XS;
5867 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5868 "popcnt{l}\t{$src, $dst|$dst, $src}",
5869 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
5871 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5872 "popcnt{l}\t{$src, $dst|$dst, $src}",
5873 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
5874 (implicit EFLAGS)]>, XS;
5876 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5877 "popcnt{q}\t{$src, $dst|$dst, $src}",
5878 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
5880 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5881 "popcnt{q}\t{$src, $dst|$dst, $src}",
5882 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
5883 (implicit EFLAGS)]>, XS;
5888 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5889 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5890 Intrinsic IntId128> {
5891 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5893 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5894 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5895 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5897 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5900 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
5903 let Predicates = [HasAVX] in
5904 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5905 int_x86_sse41_phminposuw>, VEX;
5906 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5907 int_x86_sse41_phminposuw>;
5909 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5910 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5911 Intrinsic IntId128, bit Is2Addr = 1> {
5912 let isCommutable = 1 in
5913 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5914 (ins VR128:$src1, VR128:$src2),
5916 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5917 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5918 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5919 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5920 (ins VR128:$src1, i128mem:$src2),
5922 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5923 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5925 (IntId128 VR128:$src1,
5926 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5929 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5930 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5931 Intrinsic IntId256> {
5932 let isCommutable = 1 in
5933 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
5934 (ins VR256:$src1, VR256:$src2),
5935 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5936 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
5937 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
5938 (ins VR256:$src1, i256mem:$src2),
5939 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5941 (IntId256 VR256:$src1,
5942 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5945 let Predicates = [HasAVX] in {
5946 let isCommutable = 0 in
5947 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
5949 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
5951 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
5953 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
5955 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
5957 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
5959 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
5961 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
5963 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
5965 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
5969 let Predicates = [HasAVX2] in {
5970 let isCommutable = 0 in
5971 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
5972 int_x86_avx2_packusdw>, VEX_4V;
5973 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
5974 int_x86_avx2_pmins_b>, VEX_4V;
5975 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
5976 int_x86_avx2_pmins_d>, VEX_4V;
5977 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
5978 int_x86_avx2_pminu_d>, VEX_4V;
5979 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
5980 int_x86_avx2_pminu_w>, VEX_4V;
5981 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
5982 int_x86_avx2_pmaxs_b>, VEX_4V;
5983 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
5984 int_x86_avx2_pmaxs_d>, VEX_4V;
5985 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
5986 int_x86_avx2_pmaxu_d>, VEX_4V;
5987 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
5988 int_x86_avx2_pmaxu_w>, VEX_4V;
5989 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
5990 int_x86_avx2_pmul_dq>, VEX_4V;
5993 let Constraints = "$src1 = $dst" in {
5994 let isCommutable = 0 in
5995 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
5996 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
5997 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
5998 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
5999 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6000 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6001 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6002 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6003 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6004 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6007 /// SS48I_binop_rm - Simple SSE41 binary operator.
6008 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6009 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6010 X86MemOperand x86memop, bit Is2Addr = 1> {
6011 let isCommutable = 1 in
6012 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6013 (ins RC:$src1, RC:$src2),
6015 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6016 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6017 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6018 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6019 (ins RC:$src1, x86memop:$src2),
6021 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6022 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6024 (OpVT (OpNode RC:$src1,
6025 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6028 let Predicates = [HasAVX] in {
6029 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6030 memopv2i64, i128mem, 0>, VEX_4V;
6031 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6032 memopv2i64, i128mem, 0>, VEX_4V;
6034 let Predicates = [HasAVX2] in {
6035 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6036 memopv4i64, i256mem, 0>, VEX_4V;
6037 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6038 memopv4i64, i256mem, 0>, VEX_4V;
6041 let Constraints = "$src1 = $dst" in {
6042 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6043 memopv2i64, i128mem>;
6044 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6045 memopv2i64, i128mem>;
6048 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6049 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6050 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6051 X86MemOperand x86memop, bit Is2Addr = 1> {
6052 let isCommutable = 1 in
6053 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6054 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6056 !strconcat(OpcodeStr,
6057 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6058 !strconcat(OpcodeStr,
6059 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6060 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6062 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6063 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6065 !strconcat(OpcodeStr,
6066 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6067 !strconcat(OpcodeStr,
6068 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6071 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6075 let Predicates = [HasAVX] in {
6076 let isCommutable = 0 in {
6077 let ExeDomain = SSEPackedSingle in {
6078 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6079 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6080 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6081 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6083 let ExeDomain = SSEPackedDouble in {
6084 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6085 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6086 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6087 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6089 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6090 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6091 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6092 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6094 let ExeDomain = SSEPackedSingle in
6095 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6096 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6097 let ExeDomain = SSEPackedDouble in
6098 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6099 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6100 let ExeDomain = SSEPackedSingle in
6101 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6102 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6105 let Predicates = [HasAVX2] in {
6106 let isCommutable = 0 in {
6107 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6108 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6109 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6110 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6114 let Constraints = "$src1 = $dst" in {
6115 let isCommutable = 0 in {
6116 let ExeDomain = SSEPackedSingle in
6117 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6118 VR128, memopv4f32, i128mem>;
6119 let ExeDomain = SSEPackedDouble in
6120 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6121 VR128, memopv2f64, i128mem>;
6122 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6123 VR128, memopv2i64, i128mem>;
6124 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6125 VR128, memopv2i64, i128mem>;
6127 let ExeDomain = SSEPackedSingle in
6128 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6129 VR128, memopv4f32, i128mem>;
6130 let ExeDomain = SSEPackedDouble in
6131 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6132 VR128, memopv2f64, i128mem>;
6135 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6136 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6137 RegisterClass RC, X86MemOperand x86memop,
6138 PatFrag mem_frag, Intrinsic IntId> {
6139 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6140 (ins RC:$src1, RC:$src2, RC:$src3),
6141 !strconcat(OpcodeStr,
6142 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6143 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6144 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6146 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6147 (ins RC:$src1, x86memop:$src2, RC:$src3),
6148 !strconcat(OpcodeStr,
6149 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6151 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6153 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6156 let Predicates = [HasAVX] in {
6157 let ExeDomain = SSEPackedDouble in {
6158 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6159 memopv2f64, int_x86_sse41_blendvpd>;
6160 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6161 memopv4f64, int_x86_avx_blendv_pd_256>;
6162 } // ExeDomain = SSEPackedDouble
6163 let ExeDomain = SSEPackedSingle in {
6164 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6165 memopv4f32, int_x86_sse41_blendvps>;
6166 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6167 memopv8f32, int_x86_avx_blendv_ps_256>;
6168 } // ExeDomain = SSEPackedSingle
6169 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6170 memopv2i64, int_x86_sse41_pblendvb>;
6173 let Predicates = [HasAVX2] in {
6174 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6175 memopv4i64, int_x86_avx2_pblendvb>;
6178 let Predicates = [HasAVX] in {
6179 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6180 (v16i8 VR128:$src2))),
6181 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6182 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6183 (v4i32 VR128:$src2))),
6184 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6185 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6186 (v4f32 VR128:$src2))),
6187 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6188 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6189 (v2i64 VR128:$src2))),
6190 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6191 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6192 (v2f64 VR128:$src2))),
6193 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6194 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6195 (v8i32 VR256:$src2))),
6196 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6197 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6198 (v8f32 VR256:$src2))),
6199 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6200 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6201 (v4i64 VR256:$src2))),
6202 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6203 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6204 (v4f64 VR256:$src2))),
6205 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6208 let Predicates = [HasAVX2] in {
6209 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6210 (v32i8 VR256:$src2))),
6211 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6214 /// SS41I_ternary_int - SSE 4.1 ternary operator
6215 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6216 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6218 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6219 (ins VR128:$src1, VR128:$src2),
6220 !strconcat(OpcodeStr,
6221 "\t{$src2, $dst|$dst, $src2}"),
6222 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6225 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6226 (ins VR128:$src1, i128mem:$src2),
6227 !strconcat(OpcodeStr,
6228 "\t{$src2, $dst|$dst, $src2}"),
6231 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6235 let ExeDomain = SSEPackedDouble in
6236 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6237 int_x86_sse41_blendvpd>;
6238 let ExeDomain = SSEPackedSingle in
6239 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6240 int_x86_sse41_blendvps>;
6241 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6242 int_x86_sse41_pblendvb>;
6244 let Predicates = [HasSSE41] in {
6245 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6246 (v16i8 VR128:$src2))),
6247 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6248 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6249 (v4i32 VR128:$src2))),
6250 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6251 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6252 (v4f32 VR128:$src2))),
6253 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6254 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6255 (v2i64 VR128:$src2))),
6256 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6257 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6258 (v2f64 VR128:$src2))),
6259 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6262 let Predicates = [HasAVX] in
6263 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6264 "vmovntdqa\t{$src, $dst|$dst, $src}",
6265 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6267 let Predicates = [HasAVX2] in
6268 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6269 "vmovntdqa\t{$src, $dst|$dst, $src}",
6270 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6272 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6273 "movntdqa\t{$src, $dst|$dst, $src}",
6274 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6277 //===----------------------------------------------------------------------===//
6278 // SSE4.2 - Compare Instructions
6279 //===----------------------------------------------------------------------===//
6281 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6282 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6283 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6284 X86MemOperand x86memop, bit Is2Addr = 1> {
6285 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6286 (ins RC:$src1, RC:$src2),
6288 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6289 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6290 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6292 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6293 (ins RC:$src1, x86memop:$src2),
6295 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6296 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6298 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6301 let Predicates = [HasAVX] in
6302 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6303 memopv2i64, i128mem, 0>, VEX_4V;
6305 let Predicates = [HasAVX2] in
6306 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6307 memopv4i64, i256mem, 0>, VEX_4V;
6309 let Constraints = "$src1 = $dst" in
6310 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6311 memopv2i64, i128mem>;
6313 //===----------------------------------------------------------------------===//
6314 // SSE4.2 - String/text Processing Instructions
6315 //===----------------------------------------------------------------------===//
6317 // Packed Compare Implicit Length Strings, Return Mask
6318 multiclass pseudo_pcmpistrm<string asm> {
6319 def REG : PseudoI<(outs VR128:$dst),
6320 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6321 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6323 def MEM : PseudoI<(outs VR128:$dst),
6324 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6325 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6326 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6329 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6330 let AddedComplexity = 1 in
6331 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6332 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6335 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6336 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6337 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6338 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6340 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6341 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6342 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6345 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6346 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6347 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6348 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6350 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6351 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6352 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6355 // Packed Compare Explicit Length Strings, Return Mask
6356 multiclass pseudo_pcmpestrm<string asm> {
6357 def REG : PseudoI<(outs VR128:$dst),
6358 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6359 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6360 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6361 def MEM : PseudoI<(outs VR128:$dst),
6362 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6363 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6364 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6367 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6368 let AddedComplexity = 1 in
6369 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6370 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6373 let Predicates = [HasAVX],
6374 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6375 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6376 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6377 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6379 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6380 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6381 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6384 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6385 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6386 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6387 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6389 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6390 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6391 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6394 // Packed Compare Implicit Length Strings, Return Index
6395 let Defs = [ECX, EFLAGS] in {
6396 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6397 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6398 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6399 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6400 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6401 (implicit EFLAGS)]>, OpSize;
6402 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6403 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6404 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6405 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6406 (implicit EFLAGS)]>, OpSize;
6410 let Predicates = [HasAVX] in {
6411 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6413 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6415 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6417 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6419 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6421 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6425 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6426 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6427 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6428 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6429 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6430 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6432 // Packed Compare Explicit Length Strings, Return Index
6433 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6434 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6435 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6436 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6437 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6438 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6439 (implicit EFLAGS)]>, OpSize;
6440 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6441 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6442 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6444 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6445 (implicit EFLAGS)]>, OpSize;
6449 let Predicates = [HasAVX] in {
6450 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6452 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6454 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6456 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6458 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6460 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6464 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6465 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6466 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6467 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6468 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6469 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6471 //===----------------------------------------------------------------------===//
6472 // SSE4.2 - CRC Instructions
6473 //===----------------------------------------------------------------------===//
6475 // No CRC instructions have AVX equivalents
6477 // crc intrinsic instruction
6478 // This set of instructions are only rm, the only difference is the size
6480 let Constraints = "$src1 = $dst" in {
6481 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6482 (ins GR32:$src1, i8mem:$src2),
6483 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6485 (int_x86_sse42_crc32_32_8 GR32:$src1,
6486 (load addr:$src2)))]>;
6487 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6488 (ins GR32:$src1, GR8:$src2),
6489 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6491 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6492 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6493 (ins GR32:$src1, i16mem:$src2),
6494 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6496 (int_x86_sse42_crc32_32_16 GR32:$src1,
6497 (load addr:$src2)))]>,
6499 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6500 (ins GR32:$src1, GR16:$src2),
6501 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6503 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6505 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6506 (ins GR32:$src1, i32mem:$src2),
6507 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6509 (int_x86_sse42_crc32_32_32 GR32:$src1,
6510 (load addr:$src2)))]>;
6511 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6512 (ins GR32:$src1, GR32:$src2),
6513 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6515 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6516 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6517 (ins GR64:$src1, i8mem:$src2),
6518 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6520 (int_x86_sse42_crc32_64_8 GR64:$src1,
6521 (load addr:$src2)))]>,
6523 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6524 (ins GR64:$src1, GR8:$src2),
6525 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6527 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6529 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6530 (ins GR64:$src1, i64mem:$src2),
6531 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6533 (int_x86_sse42_crc32_64_64 GR64:$src1,
6534 (load addr:$src2)))]>,
6536 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6537 (ins GR64:$src1, GR64:$src2),
6538 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6540 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6544 //===----------------------------------------------------------------------===//
6545 // AES-NI Instructions
6546 //===----------------------------------------------------------------------===//
6548 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6549 Intrinsic IntId128, bit Is2Addr = 1> {
6550 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6551 (ins VR128:$src1, VR128:$src2),
6553 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6554 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6555 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6557 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6558 (ins VR128:$src1, i128mem:$src2),
6560 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6561 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6563 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
6566 // Perform One Round of an AES Encryption/Decryption Flow
6567 let Predicates = [HasAVX, HasAES] in {
6568 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6569 int_x86_aesni_aesenc, 0>, VEX_4V;
6570 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6571 int_x86_aesni_aesenclast, 0>, VEX_4V;
6572 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6573 int_x86_aesni_aesdec, 0>, VEX_4V;
6574 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6575 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6578 let Constraints = "$src1 = $dst" in {
6579 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6580 int_x86_aesni_aesenc>;
6581 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6582 int_x86_aesni_aesenclast>;
6583 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6584 int_x86_aesni_aesdec>;
6585 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6586 int_x86_aesni_aesdeclast>;
6589 // Perform the AES InvMixColumn Transformation
6590 let Predicates = [HasAVX, HasAES] in {
6591 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6593 "vaesimc\t{$src1, $dst|$dst, $src1}",
6595 (int_x86_aesni_aesimc VR128:$src1))]>,
6597 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6598 (ins i128mem:$src1),
6599 "vaesimc\t{$src1, $dst|$dst, $src1}",
6600 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
6603 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6605 "aesimc\t{$src1, $dst|$dst, $src1}",
6607 (int_x86_aesni_aesimc VR128:$src1))]>,
6609 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6610 (ins i128mem:$src1),
6611 "aesimc\t{$src1, $dst|$dst, $src1}",
6612 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
6615 // AES Round Key Generation Assist
6616 let Predicates = [HasAVX, HasAES] in {
6617 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6618 (ins VR128:$src1, i8imm:$src2),
6619 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6621 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6623 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6624 (ins i128mem:$src1, i8imm:$src2),
6625 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6627 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
6630 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6631 (ins VR128:$src1, i8imm:$src2),
6632 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6634 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6636 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6637 (ins i128mem:$src1, i8imm:$src2),
6638 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6640 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
6643 //===----------------------------------------------------------------------===//
6644 // CLMUL Instructions
6645 //===----------------------------------------------------------------------===//
6647 // Carry-less Multiplication instructions
6648 let neverHasSideEffects = 1 in {
6649 // AVX carry-less Multiplication instructions
6650 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6651 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6652 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6656 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6657 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6658 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6661 let Constraints = "$src1 = $dst" in {
6662 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6663 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6664 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6668 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6669 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6670 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6672 } // Constraints = "$src1 = $dst"
6673 } // neverHasSideEffects = 1
6676 multiclass pclmul_alias<string asm, int immop> {
6677 def : InstAlias<!strconcat("pclmul", asm,
6678 "dq {$src, $dst|$dst, $src}"),
6679 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
6681 def : InstAlias<!strconcat("pclmul", asm,
6682 "dq {$src, $dst|$dst, $src}"),
6683 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
6685 def : InstAlias<!strconcat("vpclmul", asm,
6686 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6687 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
6689 def : InstAlias<!strconcat("vpclmul", asm,
6690 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6691 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
6693 defm : pclmul_alias<"hqhq", 0x11>;
6694 defm : pclmul_alias<"hqlq", 0x01>;
6695 defm : pclmul_alias<"lqhq", 0x10>;
6696 defm : pclmul_alias<"lqlq", 0x00>;
6698 //===----------------------------------------------------------------------===//
6700 //===----------------------------------------------------------------------===//
6702 //===----------------------------------------------------------------------===//
6703 // VBROADCAST - Load from memory and broadcast to all elements of the
6704 // destination operand
6706 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
6707 X86MemOperand x86memop, Intrinsic Int> :
6708 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6709 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6710 [(set RC:$dst, (Int addr:$src))]>, VEX;
6712 // AVX2 adds register forms
6713 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
6715 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
6716 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6717 [(set RC:$dst, (Int VR128:$src))]>, VEX;
6719 let ExeDomain = SSEPackedSingle in {
6720 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
6721 int_x86_avx_vbroadcast_ss>;
6722 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
6723 int_x86_avx_vbroadcast_ss_256>;
6725 let ExeDomain = SSEPackedDouble in
6726 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
6727 int_x86_avx_vbroadcast_sd_256>;
6728 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
6729 int_x86_avx_vbroadcastf128_pd_256>;
6731 let ExeDomain = SSEPackedSingle in {
6732 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
6733 int_x86_avx2_vbroadcast_ss_ps>;
6734 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
6735 int_x86_avx2_vbroadcast_ss_ps_256>;
6737 let ExeDomain = SSEPackedDouble in
6738 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
6739 int_x86_avx2_vbroadcast_sd_pd_256>;
6741 let Predicates = [HasAVX2] in
6742 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
6743 int_x86_avx2_vbroadcasti128>;
6745 let Predicates = [HasAVX] in
6746 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
6747 (VBROADCASTF128 addr:$src)>;
6750 //===----------------------------------------------------------------------===//
6751 // VINSERTF128 - Insert packed floating-point values
6753 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
6754 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
6755 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
6756 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6759 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
6760 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
6761 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6765 let Predicates = [HasAVX] in {
6766 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
6767 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6768 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
6769 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6770 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
6771 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6774 //===----------------------------------------------------------------------===//
6775 // VEXTRACTF128 - Extract packed floating-point values
6777 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
6778 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
6779 (ins VR256:$src1, i8imm:$src2),
6780 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6783 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
6784 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
6785 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6789 let Predicates = [HasAVX] in {
6790 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6791 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6792 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6793 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6794 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6795 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6798 //===----------------------------------------------------------------------===//
6799 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6801 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6802 Intrinsic IntLd, Intrinsic IntLd256,
6803 Intrinsic IntSt, Intrinsic IntSt256> {
6804 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6805 (ins VR128:$src1, f128mem:$src2),
6806 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6807 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6809 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6810 (ins VR256:$src1, f256mem:$src2),
6811 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6812 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6814 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6815 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6816 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6817 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6818 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6819 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6820 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6821 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6824 let ExeDomain = SSEPackedSingle in
6825 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6826 int_x86_avx_maskload_ps,
6827 int_x86_avx_maskload_ps_256,
6828 int_x86_avx_maskstore_ps,
6829 int_x86_avx_maskstore_ps_256>;
6830 let ExeDomain = SSEPackedDouble in
6831 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6832 int_x86_avx_maskload_pd,
6833 int_x86_avx_maskload_pd_256,
6834 int_x86_avx_maskstore_pd,
6835 int_x86_avx_maskstore_pd_256>;
6837 //===----------------------------------------------------------------------===//
6838 // VPERMIL - Permute Single and Double Floating-Point Values
6840 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6841 RegisterClass RC, X86MemOperand x86memop_f,
6842 X86MemOperand x86memop_i, PatFrag i_frag,
6843 Intrinsic IntVar, ValueType vt> {
6844 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6845 (ins RC:$src1, RC:$src2),
6846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6847 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6848 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6849 (ins RC:$src1, x86memop_i:$src2),
6850 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6851 [(set RC:$dst, (IntVar RC:$src1,
6852 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
6854 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6855 (ins RC:$src1, i8imm:$src2),
6856 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6857 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
6858 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6859 (ins x86memop_f:$src1, i8imm:$src2),
6860 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6862 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
6865 let ExeDomain = SSEPackedSingle in {
6866 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6867 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
6868 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6869 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
6871 let ExeDomain = SSEPackedDouble in {
6872 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6873 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
6874 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6875 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
6878 let Predicates = [HasAVX] in {
6879 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
6880 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6881 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
6882 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6883 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
6885 (VPERMILPSYmi addr:$src1, imm:$imm)>;
6886 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
6887 (VPERMILPDYmi addr:$src1, imm:$imm)>;
6889 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
6890 (VPERMILPDri VR128:$src1, imm:$imm)>;
6891 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
6892 (VPERMILPDmi addr:$src1, imm:$imm)>;
6895 //===----------------------------------------------------------------------===//
6896 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6898 let ExeDomain = SSEPackedSingle in {
6899 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6900 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6901 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6902 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
6903 (i8 imm:$src3))))]>, VEX_4V;
6904 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6905 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6906 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6907 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
6908 (i8 imm:$src3)))]>, VEX_4V;
6911 let Predicates = [HasAVX] in {
6912 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6913 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6914 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6915 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6916 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6917 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6918 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6919 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6920 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6921 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6923 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
6924 (memopv8f32 addr:$src2), (i8 imm:$imm))),
6925 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
6926 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
6927 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
6928 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
6929 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
6930 (memopv4i64 addr:$src2), (i8 imm:$imm))),
6931 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
6932 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
6933 (memopv4f64 addr:$src2), (i8 imm:$imm))),
6934 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
6935 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
6936 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
6937 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
6938 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
6939 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
6940 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
6943 //===----------------------------------------------------------------------===//
6944 // VZERO - Zero YMM registers
6946 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
6947 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
6948 // Zero All YMM registers
6949 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6950 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
6952 // Zero Upper bits of YMM registers
6953 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
6954 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
6957 //===----------------------------------------------------------------------===//
6958 // Half precision conversion instructions
6959 //===----------------------------------------------------------------------===//
6960 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
6961 let Predicates = [HasAVX, HasF16C] in {
6962 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
6963 "vcvtph2ps\t{$src, $dst|$dst, $src}",
6964 [(set RC:$dst, (Int VR128:$src))]>,
6966 let neverHasSideEffects = 1, mayLoad = 1 in
6967 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6968 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
6972 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
6973 let Predicates = [HasAVX, HasF16C] in {
6974 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
6975 (ins RC:$src1, i32i8imm:$src2),
6976 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6977 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
6979 let neverHasSideEffects = 1, mayLoad = 1 in
6980 def mr : Ii8<0x1D, MRMDestMem, (outs x86memop:$dst),
6981 (ins RC:$src1, i32i8imm:$src2),
6982 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
6987 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
6988 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
6989 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
6990 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
6992 //===----------------------------------------------------------------------===//
6993 // AVX2 Instructions
6994 //===----------------------------------------------------------------------===//
6996 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
6997 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
6998 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6999 X86MemOperand x86memop> {
7000 let isCommutable = 1 in
7001 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7002 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7003 !strconcat(OpcodeStr,
7004 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7005 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7007 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7008 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7009 !strconcat(OpcodeStr,
7010 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7013 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7017 let isCommutable = 0 in {
7018 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7019 VR128, memopv2i64, i128mem>;
7020 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7021 VR256, memopv4i64, i256mem>;
7024 //===----------------------------------------------------------------------===//
7025 // VPBROADCAST - Load from memory and broadcast to all elements of the
7026 // destination operand
7028 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7029 X86MemOperand x86memop, PatFrag ld_frag,
7030 Intrinsic Int128, Intrinsic Int256> {
7031 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7032 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7033 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7034 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7035 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7037 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7038 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7039 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7040 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7041 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7042 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7044 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7047 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7048 int_x86_avx2_pbroadcastb_128,
7049 int_x86_avx2_pbroadcastb_256>;
7050 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7051 int_x86_avx2_pbroadcastw_128,
7052 int_x86_avx2_pbroadcastw_256>;
7053 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7054 int_x86_avx2_pbroadcastd_128,
7055 int_x86_avx2_pbroadcastd_256>;
7056 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7057 int_x86_avx2_pbroadcastq_128,
7058 int_x86_avx2_pbroadcastq_256>;
7060 let Predicates = [HasAVX2] in {
7061 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7062 (VPBROADCASTBrm addr:$src)>;
7063 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7064 (VPBROADCASTBYrm addr:$src)>;
7065 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7066 (VPBROADCASTWrm addr:$src)>;
7067 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7068 (VPBROADCASTWYrm addr:$src)>;
7069 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7070 (VPBROADCASTDrm addr:$src)>;
7071 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7072 (VPBROADCASTDYrm addr:$src)>;
7073 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7074 (VPBROADCASTQrm addr:$src)>;
7075 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7076 (VPBROADCASTQYrm addr:$src)>;
7079 // AVX1 broadcast patterns
7080 let Predicates = [HasAVX] in {
7081 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7082 (VBROADCASTSSYrm addr:$src)>;
7083 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7084 (VBROADCASTSDrm addr:$src)>;
7085 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7086 (VBROADCASTSSYrm addr:$src)>;
7087 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7088 (VBROADCASTSDrm addr:$src)>;
7090 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7091 (VBROADCASTSSrm addr:$src)>;
7092 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7093 (VBROADCASTSSrm addr:$src)>;
7096 //===----------------------------------------------------------------------===//
7097 // VPERM - Permute instructions
7100 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7102 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7103 (ins VR256:$src1, VR256:$src2),
7104 !strconcat(OpcodeStr,
7105 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7106 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2))]>, VEX_4V;
7107 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7108 (ins VR256:$src1, i256mem:$src2),
7109 !strconcat(OpcodeStr,
7110 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7111 [(set VR256:$dst, (Int VR256:$src1,
7112 (bitconvert (mem_frag addr:$src2))))]>,
7116 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, int_x86_avx2_permd>;
7117 let ExeDomain = SSEPackedSingle in
7118 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>;
7120 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7122 def Yrr : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7123 (ins VR256:$src1, i8imm:$src2),
7124 !strconcat(OpcodeStr,
7125 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7126 [(set VR256:$dst, (Int VR256:$src1, imm:$src2))]>, VEX;
7127 def Yrm : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7128 (ins i256mem:$src1, i8imm:$src2),
7129 !strconcat(OpcodeStr,
7130 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7131 [(set VR256:$dst, (Int (mem_frag addr:$src1), imm:$src2))]>,
7135 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, int_x86_avx2_permq>,
7137 let ExeDomain = SSEPackedDouble in
7138 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, int_x86_avx2_permpd>,
7141 //===----------------------------------------------------------------------===//
7142 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7144 let AddedComplexity = 1 in {
7145 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7146 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7147 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7148 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7149 (i8 imm:$src3))))]>, VEX_4V;
7150 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7151 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7152 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7153 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7154 (i8 imm:$src3)))]>, VEX_4V;
7157 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7158 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7159 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7160 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7161 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7162 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7163 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7165 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7167 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7168 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7169 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7170 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7171 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7173 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7177 //===----------------------------------------------------------------------===//
7178 // VINSERTI128 - Insert packed integer values
7180 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7181 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7182 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7184 (int_x86_avx2_vinserti128 VR256:$src1, VR128:$src2, imm:$src3))]>,
7186 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7187 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7188 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7190 (int_x86_avx2_vinserti128 VR256:$src1, (memopv2i64 addr:$src2),
7191 imm:$src3))]>, VEX_4V;
7193 let Predicates = [HasAVX2] in {
7194 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7196 (VINSERTI128rr VR256:$src1, VR128:$src2,
7197 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7198 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7200 (VINSERTI128rr VR256:$src1, VR128:$src2,
7201 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7202 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7204 (VINSERTI128rr VR256:$src1, VR128:$src2,
7205 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7206 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7208 (VINSERTI128rr VR256:$src1, VR128:$src2,
7209 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7213 let Predicates = [HasAVX] in {
7214 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7216 (VINSERTF128rr VR256:$src1, VR128:$src2,
7217 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7218 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7220 (VINSERTF128rr VR256:$src1, VR128:$src2,
7221 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7222 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7224 (VINSERTF128rr VR256:$src1, VR128:$src2,
7225 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7226 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7228 (VINSERTF128rr VR256:$src1, VR128:$src2,
7229 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7230 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7232 (VINSERTF128rr VR256:$src1, VR128:$src2,
7233 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7234 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7236 (VINSERTF128rr VR256:$src1, VR128:$src2,
7237 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7240 //===----------------------------------------------------------------------===//
7241 // VEXTRACTI128 - Extract packed integer values
7243 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7244 (ins VR256:$src1, i8imm:$src2),
7245 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7247 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7249 let neverHasSideEffects = 1, mayStore = 1 in
7250 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7251 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7252 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7254 let Predicates = [HasAVX2] in {
7255 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7256 (v2i64 (VEXTRACTI128rr
7257 (v4i64 VR256:$src1),
7258 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7259 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7260 (v4i32 (VEXTRACTI128rr
7261 (v8i32 VR256:$src1),
7262 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7263 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7264 (v8i16 (VEXTRACTI128rr
7265 (v16i16 VR256:$src1),
7266 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7267 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7268 (v16i8 (VEXTRACTI128rr
7269 (v32i8 VR256:$src1),
7270 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7274 let Predicates = [HasAVX] in {
7275 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7276 (v4f32 (VEXTRACTF128rr
7277 (v8f32 VR256:$src1),
7278 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7279 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7280 (v2f64 (VEXTRACTF128rr
7281 (v4f64 VR256:$src1),
7282 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7283 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7284 (v2i64 (VEXTRACTF128rr
7285 (v4i64 VR256:$src1),
7286 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7287 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7288 (v4i32 (VEXTRACTF128rr
7289 (v8i32 VR256:$src1),
7290 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7291 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7292 (v8i16 (VEXTRACTF128rr
7293 (v16i16 VR256:$src1),
7294 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7295 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7296 (v16i8 (VEXTRACTF128rr
7297 (v32i8 VR256:$src1),
7298 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7301 //===----------------------------------------------------------------------===//
7302 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7304 multiclass avx2_pmovmask<string OpcodeStr,
7305 Intrinsic IntLd128, Intrinsic IntLd256,
7306 Intrinsic IntSt128, Intrinsic IntSt256> {
7307 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7308 (ins VR128:$src1, i128mem:$src2),
7309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7310 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7311 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7312 (ins VR256:$src1, i256mem:$src2),
7313 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7314 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7315 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7316 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7318 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7319 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7320 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7322 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7325 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7326 int_x86_avx2_maskload_d,
7327 int_x86_avx2_maskload_d_256,
7328 int_x86_avx2_maskstore_d,
7329 int_x86_avx2_maskstore_d_256>;
7330 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7331 int_x86_avx2_maskload_q,
7332 int_x86_avx2_maskload_q_256,
7333 int_x86_avx2_maskstore_q,
7334 int_x86_avx2_maskstore_q_256>, VEX_W;
7337 //===----------------------------------------------------------------------===//
7338 // Variable Bit Shifts
7340 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7341 ValueType vt128, ValueType vt256> {
7342 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7343 (ins VR128:$src1, VR128:$src2),
7344 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7346 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7348 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7349 (ins VR128:$src1, i128mem:$src2),
7350 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7352 (vt128 (OpNode VR128:$src1,
7353 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7355 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7356 (ins VR256:$src1, VR256:$src2),
7357 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7359 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
7361 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7362 (ins VR256:$src1, i256mem:$src2),
7363 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7365 (vt256 (OpNode VR256:$src1,
7366 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
7370 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
7371 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
7372 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
7373 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
7374 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;