1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
246 let isCommutable = 1 in {
247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
252 Sched<[itins.Sched]>;
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
262 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
263 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
264 string asm, string SSEVer, string FPSizeStr,
265 Operand memopr, ComplexPattern mem_cpat,
268 let isCodeGenOnly = 1 in {
269 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
271 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
272 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 [(set RC:$dst, (!cast<Intrinsic>(
274 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
275 RC:$src1, RC:$src2))], itins.rr>,
276 Sched<[itins.Sched]>;
277 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
279 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
280 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
281 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
282 SSEVer, "_", OpcodeStr, FPSizeStr))
283 RC:$src1, mem_cpat:$src2))], itins.rm>,
284 Sched<[itins.Sched.Folded, ReadAfterLd]>;
288 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
290 RegisterClass RC, ValueType vt,
291 X86MemOperand x86memop, PatFrag mem_frag,
292 Domain d, OpndItins itins, bit Is2Addr = 1> {
293 let isCommutable = 1 in
294 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
297 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
299 Sched<[itins.Sched]>;
301 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
307 Sched<[itins.Sched.Folded, ReadAfterLd]>;
310 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
311 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
312 string OpcodeStr, X86MemOperand x86memop,
313 list<dag> pat_rr, list<dag> pat_rm,
315 let isCommutable = 1, hasSideEffects = 0 in
316 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
320 pat_rr, NoItinerary, d>,
321 Sched<[WriteVecLogic]>;
322 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
326 pat_rm, NoItinerary, d>,
327 Sched<[WriteVecLogicLd, ReadAfterLd]>;
330 //===----------------------------------------------------------------------===//
331 // Non-instruction patterns
332 //===----------------------------------------------------------------------===//
334 // A vector extract of the first f32/f64 position is a subregister copy
335 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
337 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
338 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
340 // A 128-bit subvector extract from the first 256-bit vector position
341 // is a subregister copy that needs no instruction.
342 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
343 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
347 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
348 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
353 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
357 // A 128-bit subvector insert to the first 256-bit vector position
358 // is a subregister copy that needs no instruction.
359 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
360 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
374 // Implicitly promote a 32-bit scalar to a vector.
375 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
378 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 // Implicitly promote a 64-bit scalar to a vector.
380 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
382 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
383 (COPY_TO_REGCLASS FR64:$src, VR128)>;
385 // Bitcasts between 128-bit vector types. Return the original type since
386 // no instruction is needed for the conversion
387 let Predicates = [HasSSE2] in {
388 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
397 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
402 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
407 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
417 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr> {
570 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
571 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
574 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
576 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
577 VEX, VEX_LIG, Sched<[WriteStore]>;
579 let Constraints = "$src1 = $dst" in {
580 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
581 "\t{$src2, $dst|$dst, $src2}">;
584 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
586 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
590 // Loading from memory automatically zeroing upper bits.
591 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
592 PatFrag mem_pat, string OpcodeStr> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
604 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
606 let canFoldAsLoad = 1, isReMaterializable = 1 in {
607 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
609 let AddedComplexity = 20 in
610 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
614 let Predicates = [UseAVX] in {
615 let AddedComplexity = 20 in {
616 // MOVSSrm zeros the high parts of the register; represent this
617 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
618 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
619 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
620 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
621 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
622 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
625 // MOVSDrm zeros the high parts of the register; represent this
626 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
627 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
628 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
629 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
630 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
631 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzload addr:$src)),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
638 // Represent the same patterns above but in the form they appear for
640 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
641 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
642 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
643 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
644 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
645 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
646 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
647 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
648 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
650 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
651 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
652 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
654 // Extract and store.
655 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
657 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
658 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
660 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
662 // Shuffle with VMOVSS
663 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
664 (VMOVSSrr (v4i32 VR128:$src1),
665 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
666 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
667 (VMOVSSrr (v4f32 VR128:$src1),
668 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
671 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
672 (SUBREG_TO_REG (i32 0),
673 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
674 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
676 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
677 (SUBREG_TO_REG (i32 0),
678 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
679 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
682 // Shuffle with VMOVSD
683 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
689 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
690 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
693 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
694 (SUBREG_TO_REG (i32 0),
695 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
696 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
698 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
699 (SUBREG_TO_REG (i32 0),
700 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
701 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
704 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
705 // is during lowering, where it's not possible to recognize the fold cause
706 // it has two uses through a bitcast. One use disappears at isel time and the
707 // fold opportunity reappears.
708 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
714 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
715 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
718 let Predicates = [UseSSE1] in {
719 let Predicates = [NoSSE41], AddedComplexity = 15 in {
720 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
721 // MOVSS to the lower bits.
722 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
723 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
724 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
725 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
726 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
727 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
730 let AddedComplexity = 20 in {
731 // MOVSSrm already zeros the high parts of the register.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
743 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
745 // Shuffle with MOVSS
746 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
748 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
749 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
752 let Predicates = [UseSSE2] in {
753 let Predicates = [NoSSE41], AddedComplexity = 15 in {
754 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
755 // MOVSD to the lower bits.
756 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
757 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
760 let AddedComplexity = 20 in {
761 // MOVSDrm already zeros the high parts of the register.
762 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
770 def : Pat<(v2f64 (X86vzload addr:$src)),
771 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
774 // Extract and store.
775 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
777 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
779 // Shuffle with MOVSD
780 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
786 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
787 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
789 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
790 // is during lowering, where it's not possible to recognize the fold cause
791 // it has two uses through a bitcast. One use disappears at isel time and the
792 // fold opportunity reappears.
793 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
799 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
800 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
803 //===----------------------------------------------------------------------===//
804 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
805 //===----------------------------------------------------------------------===//
807 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
808 X86MemOperand x86memop, PatFrag ld_frag,
809 string asm, Domain d,
811 bit IsReMaterializable = 1> {
812 let hasSideEffects = 0 in
813 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
814 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
815 Sched<[WriteFShuffle]>;
816 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
817 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
818 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
819 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
823 let Predicates = [HasAVX, NoVLX] in {
824 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
830 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
837 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
838 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
840 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
841 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
843 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
844 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
846 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
847 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
851 let Predicates = [UseSSE1] in {
852 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
853 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
855 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
856 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
859 let Predicates = [UseSSE2] in {
860 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
861 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
863 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
864 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
868 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
869 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
870 "movaps\t{$src, $dst|$dst, $src}",
871 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
872 IIC_SSE_MOVA_P_MR>, VEX;
873 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
874 "movapd\t{$src, $dst|$dst, $src}",
875 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
876 IIC_SSE_MOVA_P_MR>, VEX;
877 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
878 "movups\t{$src, $dst|$dst, $src}",
879 [(store (v4f32 VR128:$src), addr:$dst)],
880 IIC_SSE_MOVU_P_MR>, VEX;
881 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
882 "movupd\t{$src, $dst|$dst, $src}",
883 [(store (v2f64 VR128:$src), addr:$dst)],
884 IIC_SSE_MOVU_P_MR>, VEX;
885 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
886 "movaps\t{$src, $dst|$dst, $src}",
887 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
888 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
889 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
890 "movapd\t{$src, $dst|$dst, $src}",
891 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
892 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
893 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
894 "movups\t{$src, $dst|$dst, $src}",
895 [(store (v8f32 VR256:$src), addr:$dst)],
896 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
897 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
898 "movupd\t{$src, $dst|$dst, $src}",
899 [(store (v4f64 VR256:$src), addr:$dst)],
900 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
904 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
905 SchedRW = [WriteFShuffle] in {
906 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
908 "movaps\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX;
910 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
912 "movapd\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVA_P_RR>, VEX;
914 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
916 "movups\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX;
918 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
920 "movupd\t{$src, $dst|$dst, $src}", [],
921 IIC_SSE_MOVU_P_RR>, VEX;
922 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
924 "movaps\t{$src, $dst|$dst, $src}", [],
925 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
926 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
928 "movapd\t{$src, $dst|$dst, $src}", [],
929 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
930 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
932 "movups\t{$src, $dst|$dst, $src}", [],
933 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
934 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
936 "movupd\t{$src, $dst|$dst, $src}", [],
937 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
940 let Predicates = [HasAVX] in {
941 def : Pat<(v8i32 (X86vzmovl
942 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
943 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
944 def : Pat<(v4i64 (X86vzmovl
945 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
946 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
947 def : Pat<(v8f32 (X86vzmovl
948 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
949 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
950 def : Pat<(v4f64 (X86vzmovl
951 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
952 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
956 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
957 (VMOVUPSYmr addr:$dst, VR256:$src)>;
958 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
959 (VMOVUPDYmr addr:$dst, VR256:$src)>;
961 let SchedRW = [WriteStore] in {
962 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
963 "movaps\t{$src, $dst|$dst, $src}",
964 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
966 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
967 "movapd\t{$src, $dst|$dst, $src}",
968 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
970 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
971 "movups\t{$src, $dst|$dst, $src}",
972 [(store (v4f32 VR128:$src), addr:$dst)],
974 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
975 "movupd\t{$src, $dst|$dst, $src}",
976 [(store (v2f64 VR128:$src), addr:$dst)],
981 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
982 SchedRW = [WriteFShuffle] in {
983 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
984 "movaps\t{$src, $dst|$dst, $src}", [],
986 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
987 "movapd\t{$src, $dst|$dst, $src}", [],
989 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
990 "movups\t{$src, $dst|$dst, $src}", [],
992 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
993 "movupd\t{$src, $dst|$dst, $src}", [],
997 let Predicates = [HasAVX] in {
998 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
999 (VMOVUPSmr addr:$dst, VR128:$src)>;
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (VMOVUPDmr addr:$dst, VR128:$src)>;
1004 let Predicates = [UseSSE1] in
1005 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1006 (MOVUPSmr addr:$dst, VR128:$src)>;
1007 let Predicates = [UseSSE2] in
1008 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1009 (MOVUPDmr addr:$dst, VR128:$src)>;
1011 // Use vmovaps/vmovups for AVX integer load/store.
1012 let Predicates = [HasAVX, NoVLX] in {
1013 // 128-bit load/store
1014 def : Pat<(alignedloadv2i64 addr:$src),
1015 (VMOVAPSrm addr:$src)>;
1016 def : Pat<(loadv2i64 addr:$src),
1017 (VMOVUPSrm addr:$src)>;
1019 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1026 (VMOVAPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1033 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1034 (VMOVUPSmr addr:$dst, VR128:$src)>;
1036 // 256-bit load/store
1037 def : Pat<(alignedloadv4i64 addr:$src),
1038 (VMOVAPSYrm addr:$src)>;
1039 def : Pat<(loadv4i64 addr:$src),
1040 (VMOVUPSYrm addr:$src)>;
1041 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1048 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1055 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1056 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1058 // Special patterns for storing subvector extracts of lower 128-bits
1059 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1060 def : Pat<(alignedstore (v2f64 (extract_subvector
1061 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1062 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1063 def : Pat<(alignedstore (v4f32 (extract_subvector
1064 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1065 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1066 def : Pat<(alignedstore (v2i64 (extract_subvector
1067 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1068 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1069 def : Pat<(alignedstore (v4i32 (extract_subvector
1070 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1071 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1072 def : Pat<(alignedstore (v8i16 (extract_subvector
1073 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1074 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1075 def : Pat<(alignedstore (v16i8 (extract_subvector
1076 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1077 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1079 def : Pat<(store (v2f64 (extract_subvector
1080 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1081 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1082 def : Pat<(store (v4f32 (extract_subvector
1083 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1084 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1085 def : Pat<(store (v2i64 (extract_subvector
1086 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1087 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1088 def : Pat<(store (v4i32 (extract_subvector
1089 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1090 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1091 def : Pat<(store (v8i16 (extract_subvector
1092 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1093 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1094 def : Pat<(store (v16i8 (extract_subvector
1095 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1096 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1099 // Use movaps / movups for SSE integer load / store (one byte shorter).
1100 // The instructions selected below are then converted to MOVDQA/MOVDQU
1101 // during the SSE domain pass.
1102 let Predicates = [UseSSE1] in {
1103 def : Pat<(alignedloadv2i64 addr:$src),
1104 (MOVAPSrm addr:$src)>;
1105 def : Pat<(loadv2i64 addr:$src),
1106 (MOVUPSrm addr:$src)>;
1108 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1115 (MOVAPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1122 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1123 (MOVUPSmr addr:$dst, VR128:$src)>;
1126 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1127 // bits are disregarded. FIXME: Set encoding to pseudo!
1128 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1129 let isCodeGenOnly = 1 in {
1130 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1131 "movaps\t{$src, $dst|$dst, $src}",
1132 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1133 IIC_SSE_MOVA_P_RM>, VEX;
1134 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1135 "movapd\t{$src, $dst|$dst, $src}",
1136 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1137 IIC_SSE_MOVA_P_RM>, VEX;
1138 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1139 "movaps\t{$src, $dst|$dst, $src}",
1140 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1142 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1143 "movapd\t{$src, $dst|$dst, $src}",
1144 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1149 //===----------------------------------------------------------------------===//
1150 // SSE 1 & 2 - Move Low packed FP Instructions
1151 //===----------------------------------------------------------------------===//
1153 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1154 string base_opc, string asm_opr,
1155 InstrItinClass itin> {
1156 def PSrm : PI<opc, MRMSrcMem,
1157 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1158 !strconcat(base_opc, "s", asm_opr),
1160 (psnode VR128:$src1,
1161 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1162 itin, SSEPackedSingle>, PS,
1163 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1165 def PDrm : PI<opc, MRMSrcMem,
1166 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1167 !strconcat(base_opc, "d", asm_opr),
1168 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1169 (scalar_to_vector (loadf64 addr:$src2)))))],
1170 itin, SSEPackedDouble>, PD,
1171 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1175 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1176 string base_opc, InstrItinClass itin> {
1177 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1178 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1181 let Constraints = "$src1 = $dst" in
1182 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1183 "\t{$src2, $dst|$dst, $src2}",
1187 let AddedComplexity = 20 in {
1188 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1192 let SchedRW = [WriteStore] in {
1193 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1194 "movlps\t{$src, $dst|$dst, $src}",
1195 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1196 (iPTR 0))), addr:$dst)],
1197 IIC_SSE_MOV_LH>, VEX;
1198 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1199 "movlpd\t{$src, $dst|$dst, $src}",
1200 [(store (f64 (vector_extract (v2f64 VR128:$src),
1201 (iPTR 0))), addr:$dst)],
1202 IIC_SSE_MOV_LH>, VEX;
1203 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1204 "movlps\t{$src, $dst|$dst, $src}",
1205 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1206 (iPTR 0))), addr:$dst)],
1208 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1209 "movlpd\t{$src, $dst|$dst, $src}",
1210 [(store (f64 (vector_extract (v2f64 VR128:$src),
1211 (iPTR 0))), addr:$dst)],
1215 let Predicates = [HasAVX] in {
1216 // Shuffle with VMOVLPS
1217 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1219 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1220 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1222 // Shuffle with VMOVLPD
1223 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1226 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1227 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1228 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1229 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1232 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1234 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1235 def : Pat<(store (v4i32 (X86Movlps
1236 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1237 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1238 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1240 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1243 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1246 let Predicates = [UseSSE1] in {
1247 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1248 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1249 (iPTR 0))), addr:$src1),
1250 (MOVLPSmr addr:$src1, VR128:$src2)>;
1252 // Shuffle with MOVLPS
1253 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1256 (MOVLPSrm VR128:$src1, addr:$src2)>;
1257 def : Pat<(X86Movlps VR128:$src1,
1258 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1259 (MOVLPSrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1264 (MOVLPSmr addr:$src1, VR128:$src2)>;
1265 def : Pat<(store (v4i32 (X86Movlps
1266 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1268 (MOVLPSmr addr:$src1, VR128:$src2)>;
1271 let Predicates = [UseSSE2] in {
1272 // Shuffle with MOVLPD
1273 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1276 (MOVLPDrm VR128:$src1, addr:$src2)>;
1277 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1278 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1279 (MOVLPDrm VR128:$src1, addr:$src2)>;
1282 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1284 (MOVLPDmr addr:$src1, VR128:$src2)>;
1285 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1287 (MOVLPDmr addr:$src1, VR128:$src2)>;
1290 //===----------------------------------------------------------------------===//
1291 // SSE 1 & 2 - Move Hi packed FP Instructions
1292 //===----------------------------------------------------------------------===//
1294 let AddedComplexity = 20 in {
1295 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1299 let SchedRW = [WriteStore] in {
1300 // v2f64 extract element 1 is always custom lowered to unpack high to low
1301 // and extract element 0 so the non-store version isn't too horrible.
1302 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1303 "movhps\t{$src, $dst|$dst, $src}",
1304 [(store (f64 (vector_extract
1305 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1306 (bc_v2f64 (v4f32 VR128:$src))),
1307 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1308 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1309 "movhpd\t{$src, $dst|$dst, $src}",
1310 [(store (f64 (vector_extract
1311 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1312 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1313 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1314 "movhps\t{$src, $dst|$dst, $src}",
1315 [(store (f64 (vector_extract
1316 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1317 (bc_v2f64 (v4f32 VR128:$src))),
1318 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1319 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1320 "movhpd\t{$src, $dst|$dst, $src}",
1321 [(store (f64 (vector_extract
1322 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1323 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1326 let Predicates = [HasAVX] in {
1328 def : Pat<(X86Movlhps VR128:$src1,
1329 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1330 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1331 def : Pat<(X86Movlhps VR128:$src1,
1332 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1333 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1335 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1336 // is during lowering, where it's not possible to recognize the load fold
1337 // cause it has two uses through a bitcast. One use disappears at isel time
1338 // and the fold opportunity reappears.
1339 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1340 (scalar_to_vector (loadf64 addr:$src2)))),
1341 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1342 // Also handle an i64 load because that may get selected as a faster way to
1344 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1345 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1346 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1349 let Predicates = [UseSSE1] in {
1351 def : Pat<(X86Movlhps VR128:$src1,
1352 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1353 (MOVHPSrm VR128:$src1, addr:$src2)>;
1354 def : Pat<(X86Movlhps VR128:$src1,
1355 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1356 (MOVHPSrm VR128:$src1, addr:$src2)>;
1359 let Predicates = [UseSSE2] in {
1360 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1361 // is during lowering, where it's not possible to recognize the load fold
1362 // cause it has two uses through a bitcast. One use disappears at isel time
1363 // and the fold opportunity reappears.
1364 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1365 (scalar_to_vector (loadf64 addr:$src2)))),
1366 (MOVHPDrm VR128:$src1, addr:$src2)>;
1367 // Also handle an i64 load because that may get selected as a faster way to
1369 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1370 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1371 (MOVHPDrm VR128:$src1, addr:$src2)>;
1374 //===----------------------------------------------------------------------===//
1375 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1376 //===----------------------------------------------------------------------===//
1378 let AddedComplexity = 20, Predicates = [UseAVX] in {
1379 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1380 (ins VR128:$src1, VR128:$src2),
1381 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1383 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1385 VEX_4V, Sched<[WriteFShuffle]>;
1386 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1387 (ins VR128:$src1, VR128:$src2),
1388 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1390 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1392 VEX_4V, Sched<[WriteFShuffle]>;
1394 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1395 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1396 (ins VR128:$src1, VR128:$src2),
1397 "movlhps\t{$src2, $dst|$dst, $src2}",
1399 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1400 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1401 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1402 (ins VR128:$src1, VR128:$src2),
1403 "movhlps\t{$src2, $dst|$dst, $src2}",
1405 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1406 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1409 let Predicates = [UseAVX] in {
1411 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1412 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1413 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1414 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1417 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1418 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1421 let Predicates = [UseSSE1] in {
1423 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1424 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1425 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1429 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1430 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1433 //===----------------------------------------------------------------------===//
1434 // SSE 1 & 2 - Conversion Instructions
1435 //===----------------------------------------------------------------------===//
1437 def SSE_CVT_PD : OpndItins<
1438 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1441 let Sched = WriteCvtI2F in
1442 def SSE_CVT_PS : OpndItins<
1443 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1446 let Sched = WriteCvtI2F in
1447 def SSE_CVT_Scalar : OpndItins<
1448 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1451 let Sched = WriteCvtF2I in
1452 def SSE_CVT_SS2SI_32 : OpndItins<
1453 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1456 let Sched = WriteCvtF2I in
1457 def SSE_CVT_SS2SI_64 : OpndItins<
1458 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1461 let Sched = WriteCvtF2I in
1462 def SSE_CVT_SD2SI : OpndItins<
1463 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1466 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1467 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1468 string asm, OpndItins itins> {
1469 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1470 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1471 itins.rr>, Sched<[itins.Sched]>;
1472 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1473 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1474 itins.rm>, Sched<[itins.Sched.Folded]>;
1477 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1478 X86MemOperand x86memop, string asm, Domain d,
1480 let hasSideEffects = 0 in {
1481 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1482 [], itins.rr, d>, Sched<[itins.Sched]>;
1484 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1485 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1489 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1490 X86MemOperand x86memop, string asm> {
1491 let hasSideEffects = 0, Predicates = [UseAVX] in {
1492 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1493 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1494 Sched<[WriteCvtI2F]>;
1496 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1497 (ins DstRC:$src1, x86memop:$src),
1498 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1499 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1500 } // hasSideEffects = 0
1503 let Predicates = [UseAVX] in {
1504 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1505 "cvttss2si\t{$src, $dst|$dst, $src}",
1508 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1509 "cvttss2si\t{$src, $dst|$dst, $src}",
1511 XS, VEX, VEX_W, VEX_LIG;
1512 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1513 "cvttsd2si\t{$src, $dst|$dst, $src}",
1516 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1517 "cvttsd2si\t{$src, $dst|$dst, $src}",
1519 XD, VEX, VEX_W, VEX_LIG;
1521 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1522 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1523 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1524 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1525 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1526 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1527 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1528 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1529 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1530 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1531 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1532 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1533 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1534 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1535 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1538 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1539 // register, but the same isn't true when only using memory operands,
1540 // provide other assembly "l" and "q" forms to address this explicitly
1541 // where appropriate to do so.
1542 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1543 XS, VEX_4V, VEX_LIG;
1544 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1545 XS, VEX_4V, VEX_W, VEX_LIG;
1546 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1547 XD, VEX_4V, VEX_LIG;
1548 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1549 XD, VEX_4V, VEX_W, VEX_LIG;
1551 let Predicates = [UseAVX] in {
1552 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1553 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1554 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1555 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1557 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1558 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1559 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1560 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1561 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1562 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1563 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1564 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1566 def : Pat<(f32 (sint_to_fp GR32:$src)),
1567 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1568 def : Pat<(f32 (sint_to_fp GR64:$src)),
1569 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1570 def : Pat<(f64 (sint_to_fp GR32:$src)),
1571 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1572 def : Pat<(f64 (sint_to_fp GR64:$src)),
1573 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1576 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1577 "cvttss2si\t{$src, $dst|$dst, $src}",
1578 SSE_CVT_SS2SI_32>, XS;
1579 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1580 "cvttss2si\t{$src, $dst|$dst, $src}",
1581 SSE_CVT_SS2SI_64>, XS, REX_W;
1582 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1583 "cvttsd2si\t{$src, $dst|$dst, $src}",
1585 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1586 "cvttsd2si\t{$src, $dst|$dst, $src}",
1587 SSE_CVT_SD2SI>, XD, REX_W;
1588 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1589 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1590 SSE_CVT_Scalar>, XS;
1591 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1592 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1593 SSE_CVT_Scalar>, XS, REX_W;
1594 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1595 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1596 SSE_CVT_Scalar>, XD;
1597 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1598 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1599 SSE_CVT_Scalar>, XD, REX_W;
1601 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1602 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1603 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1604 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1605 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1606 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1607 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1608 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1609 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1610 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1611 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1612 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1613 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1614 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1615 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1616 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1618 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1619 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1620 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1621 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1623 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1624 // and/or XMM operand(s).
1626 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1627 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1628 string asm, OpndItins itins> {
1629 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1630 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1631 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1632 Sched<[itins.Sched]>;
1633 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1634 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1635 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1636 Sched<[itins.Sched.Folded]>;
1639 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1640 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1641 PatFrag ld_frag, string asm, OpndItins itins,
1643 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1645 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1646 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1647 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1648 itins.rr>, Sched<[itins.Sched]>;
1649 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1650 (ins DstRC:$src1, x86memop:$src2),
1652 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1653 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1654 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1655 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1658 let Predicates = [UseAVX] in {
1659 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1660 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1661 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1662 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1663 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1664 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1666 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1667 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1668 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1669 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1672 let isCodeGenOnly = 1 in {
1673 let Predicates = [UseAVX] in {
1674 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1675 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1676 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1677 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1678 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1679 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1681 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1682 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1683 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1684 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1685 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1686 SSE_CVT_Scalar, 0>, XD,
1689 let Constraints = "$src1 = $dst" in {
1690 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1691 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1692 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1693 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1694 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1695 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1696 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1697 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1698 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1699 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1700 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1701 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1703 } // isCodeGenOnly = 1
1707 // Aliases for intrinsics
1708 let isCodeGenOnly = 1 in {
1709 let Predicates = [UseAVX] in {
1710 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1711 ssmem, sse_load_f32, "cvttss2si",
1712 SSE_CVT_SS2SI_32>, XS, VEX;
1713 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1714 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1715 "cvttss2si", SSE_CVT_SS2SI_64>,
1717 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1718 sdmem, sse_load_f64, "cvttsd2si",
1719 SSE_CVT_SD2SI>, XD, VEX;
1720 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1721 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1722 "cvttsd2si", SSE_CVT_SD2SI>,
1725 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1726 ssmem, sse_load_f32, "cvttss2si",
1727 SSE_CVT_SS2SI_32>, XS;
1728 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1729 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1730 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1731 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1732 sdmem, sse_load_f64, "cvttsd2si",
1734 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1735 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1736 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1737 } // isCodeGenOnly = 1
1739 let Predicates = [UseAVX] in {
1740 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1741 ssmem, sse_load_f32, "cvtss2si",
1742 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1743 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1744 ssmem, sse_load_f32, "cvtss2si",
1745 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1747 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1748 ssmem, sse_load_f32, "cvtss2si",
1749 SSE_CVT_SS2SI_32>, XS;
1750 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1751 ssmem, sse_load_f32, "cvtss2si",
1752 SSE_CVT_SS2SI_64>, XS, REX_W;
1754 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1755 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1756 SSEPackedSingle, SSE_CVT_PS>,
1757 PS, VEX, Requires<[HasAVX]>;
1758 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1759 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1760 SSEPackedSingle, SSE_CVT_PS>,
1761 PS, VEX, VEX_L, Requires<[HasAVX]>;
1763 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1764 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1765 SSEPackedSingle, SSE_CVT_PS>,
1766 PS, Requires<[UseSSE2]>;
1768 let Predicates = [UseAVX] in {
1769 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1770 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1771 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1772 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1773 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1774 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1775 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1776 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1777 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1778 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1779 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1780 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1781 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1782 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1783 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1784 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1787 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1788 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1789 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1790 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1791 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1792 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1793 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1794 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1795 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1796 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1797 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1798 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1799 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1800 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1801 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1802 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1806 // Convert scalar double to scalar single
1807 let hasSideEffects = 0, Predicates = [UseAVX] in {
1808 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1809 (ins FR64:$src1, FR64:$src2),
1810 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1811 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1812 Sched<[WriteCvtF2F]>;
1814 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1815 (ins FR64:$src1, f64mem:$src2),
1816 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1817 [], IIC_SSE_CVT_Scalar_RM>,
1818 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1819 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1822 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1825 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1826 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1827 [(set FR32:$dst, (fround FR64:$src))],
1828 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1829 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1830 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1831 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1832 IIC_SSE_CVT_Scalar_RM>,
1834 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1836 let isCodeGenOnly = 1 in {
1837 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1838 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1839 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1841 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1842 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1843 Sched<[WriteCvtF2F]>;
1844 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1845 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1846 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1847 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1848 VR128:$src1, sse_load_f64:$src2))],
1849 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1850 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1852 let Constraints = "$src1 = $dst" in {
1853 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1854 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1855 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1857 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1858 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1859 Sched<[WriteCvtF2F]>;
1860 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1861 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1862 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1863 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1864 VR128:$src1, sse_load_f64:$src2))],
1865 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1866 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1868 } // isCodeGenOnly = 1
1870 // Convert scalar single to scalar double
1871 // SSE2 instructions with XS prefix
1872 let hasSideEffects = 0, Predicates = [UseAVX] in {
1873 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1874 (ins FR32:$src1, FR32:$src2),
1875 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1876 [], IIC_SSE_CVT_Scalar_RR>,
1877 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1878 Sched<[WriteCvtF2F]>;
1880 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1881 (ins FR32:$src1, f32mem:$src2),
1882 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1883 [], IIC_SSE_CVT_Scalar_RM>,
1884 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1885 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1888 def : Pat<(f64 (fextend FR32:$src)),
1889 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1890 def : Pat<(fextend (loadf32 addr:$src)),
1891 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1893 def : Pat<(extloadf32 addr:$src),
1894 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1895 Requires<[UseAVX, OptForSize]>;
1896 def : Pat<(extloadf32 addr:$src),
1897 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1898 Requires<[UseAVX, OptForSpeed]>;
1900 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1901 "cvtss2sd\t{$src, $dst|$dst, $src}",
1902 [(set FR64:$dst, (fextend FR32:$src))],
1903 IIC_SSE_CVT_Scalar_RR>, XS,
1904 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1905 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1906 "cvtss2sd\t{$src, $dst|$dst, $src}",
1907 [(set FR64:$dst, (extloadf32 addr:$src))],
1908 IIC_SSE_CVT_Scalar_RM>, XS,
1909 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1911 // extload f32 -> f64. This matches load+fextend because we have a hack in
1912 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1914 // Since these loads aren't folded into the fextend, we have to match it
1916 def : Pat<(fextend (loadf32 addr:$src)),
1917 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1918 def : Pat<(extloadf32 addr:$src),
1919 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1921 let isCodeGenOnly = 1 in {
1922 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1923 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1924 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1926 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1927 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1928 Sched<[WriteCvtF2F]>;
1929 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1930 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1931 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1933 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1934 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1935 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1936 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1937 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1938 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1939 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1941 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1942 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1943 Sched<[WriteCvtF2F]>;
1944 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1945 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1946 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1948 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1949 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1950 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1952 } // isCodeGenOnly = 1
1954 // Convert packed single/double fp to doubleword
1955 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1956 "cvtps2dq\t{$src, $dst|$dst, $src}",
1957 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1958 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1959 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1960 "cvtps2dq\t{$src, $dst|$dst, $src}",
1962 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1963 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1964 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1965 "cvtps2dq\t{$src, $dst|$dst, $src}",
1967 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1968 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1969 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1970 "cvtps2dq\t{$src, $dst|$dst, $src}",
1972 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1973 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1974 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1975 "cvtps2dq\t{$src, $dst|$dst, $src}",
1976 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1977 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1978 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1979 "cvtps2dq\t{$src, $dst|$dst, $src}",
1981 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1982 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1985 // Convert Packed Double FP to Packed DW Integers
1986 let Predicates = [HasAVX] in {
1987 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1988 // register, but the same isn't true when using memory operands instead.
1989 // Provide other assembly rr and rm forms to address this explicitly.
1990 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1991 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1992 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1993 VEX, Sched<[WriteCvtF2I]>;
1996 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1997 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
1998 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1999 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2001 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2002 Sched<[WriteCvtF2ILd]>;
2005 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2006 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2008 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2009 Sched<[WriteCvtF2I]>;
2010 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2011 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2013 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2014 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2015 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2016 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2019 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2020 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2022 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2023 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2024 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2025 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2026 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2027 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2029 // Convert with truncation packed single/double fp to doubleword
2030 // SSE2 packed instructions with XS prefix
2031 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2032 "cvttps2dq\t{$src, $dst|$dst, $src}",
2034 (int_x86_sse2_cvttps2dq VR128:$src))],
2035 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2036 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2037 "cvttps2dq\t{$src, $dst|$dst, $src}",
2038 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2039 (loadv4f32 addr:$src)))],
2040 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2041 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2042 "cvttps2dq\t{$src, $dst|$dst, $src}",
2044 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2045 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2046 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2047 "cvttps2dq\t{$src, $dst|$dst, $src}",
2048 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2049 (loadv8f32 addr:$src)))],
2050 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2051 Sched<[WriteCvtF2ILd]>;
2053 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2054 "cvttps2dq\t{$src, $dst|$dst, $src}",
2055 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2056 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2057 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2058 "cvttps2dq\t{$src, $dst|$dst, $src}",
2060 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2061 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2063 let Predicates = [HasAVX] in {
2064 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2065 (VCVTDQ2PSrr VR128:$src)>;
2066 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2067 (VCVTDQ2PSrm addr:$src)>;
2069 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2070 (VCVTDQ2PSrr VR128:$src)>;
2071 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2072 (VCVTDQ2PSrm addr:$src)>;
2074 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2075 (VCVTTPS2DQrr VR128:$src)>;
2076 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2077 (VCVTTPS2DQrm addr:$src)>;
2079 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2080 (VCVTDQ2PSYrr VR256:$src)>;
2081 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2082 (VCVTDQ2PSYrm addr:$src)>;
2084 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2085 (VCVTTPS2DQYrr VR256:$src)>;
2086 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2087 (VCVTTPS2DQYrm addr:$src)>;
2090 let Predicates = [UseSSE2] in {
2091 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2092 (CVTDQ2PSrr VR128:$src)>;
2093 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2094 (CVTDQ2PSrm addr:$src)>;
2096 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2097 (CVTDQ2PSrr VR128:$src)>;
2098 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2099 (CVTDQ2PSrm addr:$src)>;
2101 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2102 (CVTTPS2DQrr VR128:$src)>;
2103 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2104 (CVTTPS2DQrm addr:$src)>;
2107 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2108 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2110 (int_x86_sse2_cvttpd2dq VR128:$src))],
2111 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2113 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2114 // register, but the same isn't true when using memory operands instead.
2115 // Provide other assembly rr and rm forms to address this explicitly.
2118 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2119 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2120 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2121 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2122 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2123 (loadv2f64 addr:$src)))],
2124 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2127 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2128 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2130 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2131 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2132 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2133 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2135 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2136 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2137 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2138 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2140 let Predicates = [HasAVX] in {
2141 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2142 (VCVTTPD2DQYrr VR256:$src)>;
2143 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2144 (VCVTTPD2DQYrm addr:$src)>;
2145 } // Predicates = [HasAVX]
2147 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2148 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2149 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2150 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2151 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2152 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2153 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2154 (memopv2f64 addr:$src)))],
2156 Sched<[WriteCvtF2ILd]>;
2158 // Convert packed single to packed double
2159 let Predicates = [HasAVX] in {
2160 // SSE2 instructions without OpSize prefix
2161 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2162 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2163 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2164 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2165 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2166 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2167 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2168 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2169 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2170 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2172 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2173 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2174 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2175 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2177 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2178 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2181 let Predicates = [UseSSE2] in {
2182 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2183 "cvtps2pd\t{$src, $dst|$dst, $src}",
2184 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2185 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2186 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2187 "cvtps2pd\t{$src, $dst|$dst, $src}",
2188 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2189 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2192 // Convert Packed DW Integers to Packed Double FP
2193 let Predicates = [HasAVX] in {
2194 let hasSideEffects = 0, mayLoad = 1 in
2195 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2196 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2197 []>, VEX, Sched<[WriteCvtI2FLd]>;
2198 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2199 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2201 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2202 Sched<[WriteCvtI2F]>;
2203 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2204 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2206 (int_x86_avx_cvtdq2_pd_256
2207 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2208 Sched<[WriteCvtI2FLd]>;
2209 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2210 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2212 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2213 Sched<[WriteCvtI2F]>;
2216 let hasSideEffects = 0, mayLoad = 1 in
2217 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2218 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2219 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2220 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2221 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2222 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2223 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2225 // AVX 256-bit register conversion intrinsics
2226 let Predicates = [HasAVX] in {
2227 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2228 (VCVTDQ2PDYrr VR128:$src)>;
2229 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2230 (VCVTDQ2PDYrm addr:$src)>;
2231 } // Predicates = [HasAVX]
2233 // Convert packed double to packed single
2234 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2235 // register, but the same isn't true when using memory operands instead.
2236 // Provide other assembly rr and rm forms to address this explicitly.
2237 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2238 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2239 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2240 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2243 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2244 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2245 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2246 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2248 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2249 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2252 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2253 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2255 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2256 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2257 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2258 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2260 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2261 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2262 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2263 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2265 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2266 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2267 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2268 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2269 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2270 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2272 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2273 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2276 // AVX 256-bit register conversion intrinsics
2277 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2278 // whenever possible to avoid declaring two versions of each one.
2279 let Predicates = [HasAVX] in {
2280 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2281 (VCVTDQ2PSYrr VR256:$src)>;
2282 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2283 (VCVTDQ2PSYrm addr:$src)>;
2285 // Match fround and fextend for 128/256-bit conversions
2286 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2287 (VCVTPD2PSrr VR128:$src)>;
2288 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2289 (VCVTPD2PSXrm addr:$src)>;
2290 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2291 (VCVTPD2PSYrr VR256:$src)>;
2292 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2293 (VCVTPD2PSYrm addr:$src)>;
2295 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2296 (VCVTPS2PDrr VR128:$src)>;
2297 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2298 (VCVTPS2PDYrr VR128:$src)>;
2299 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2300 (VCVTPS2PDYrm addr:$src)>;
2303 let Predicates = [UseSSE2] in {
2304 // Match fround and fextend for 128 conversions
2305 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2306 (CVTPD2PSrr VR128:$src)>;
2307 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2308 (CVTPD2PSrm addr:$src)>;
2310 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2311 (CVTPS2PDrr VR128:$src)>;
2314 //===----------------------------------------------------------------------===//
2315 // SSE 1 & 2 - Compare Instructions
2316 //===----------------------------------------------------------------------===//
2318 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2319 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2320 Operand CC, SDNode OpNode, ValueType VT,
2321 PatFrag ld_frag, string asm, string asm_alt,
2323 def rr : SIi8<0xC2, MRMSrcReg,
2324 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2325 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2326 itins.rr>, Sched<[itins.Sched]>;
2327 def rm : SIi8<0xC2, MRMSrcMem,
2328 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2329 [(set RC:$dst, (OpNode (VT RC:$src1),
2330 (ld_frag addr:$src2), imm:$cc))],
2332 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2334 // Accept explicit immediate argument form instead of comparison code.
2335 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2336 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2337 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2338 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2340 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2341 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2342 IIC_SSE_ALU_F32S_RM>,
2343 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2347 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2348 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2349 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2351 XS, VEX_4V, VEX_LIG;
2352 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2353 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2354 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2355 SSE_ALU_F32S>, // same latency as 32 bit compare
2356 XD, VEX_4V, VEX_LIG;
2358 let Constraints = "$src1 = $dst" in {
2359 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2360 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2361 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2363 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2364 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2365 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2370 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2371 Intrinsic Int, string asm, OpndItins itins> {
2372 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2373 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2374 [(set VR128:$dst, (Int VR128:$src1,
2375 VR128:$src, imm:$cc))],
2377 Sched<[itins.Sched]>;
2378 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2379 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2380 [(set VR128:$dst, (Int VR128:$src1,
2381 (load addr:$src), imm:$cc))],
2383 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2386 let isCodeGenOnly = 1 in {
2387 // Aliases to match intrinsics which expect XMM operand(s).
2388 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2389 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2392 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2393 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2394 SSE_ALU_F32S>, // same latency as f32
2396 let Constraints = "$src1 = $dst" in {
2397 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2398 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2400 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2401 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2408 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2409 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2410 ValueType vt, X86MemOperand x86memop,
2411 PatFrag ld_frag, string OpcodeStr> {
2412 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2413 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2414 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2417 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2418 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2419 [(set EFLAGS, (OpNode (vt RC:$src1),
2420 (ld_frag addr:$src2)))],
2422 Sched<[WriteFAddLd, ReadAfterLd]>;
2425 let Defs = [EFLAGS] in {
2426 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2427 "ucomiss">, PS, VEX, VEX_LIG;
2428 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2429 "ucomisd">, PD, VEX, VEX_LIG;
2430 let Pattern = []<dag> in {
2431 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2432 "comiss">, PS, VEX, VEX_LIG;
2433 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2434 "comisd">, PD, VEX, VEX_LIG;
2437 let isCodeGenOnly = 1 in {
2438 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2439 load, "ucomiss">, PS, VEX;
2440 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2441 load, "ucomisd">, PD, VEX;
2443 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2444 load, "comiss">, PS, VEX;
2445 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2446 load, "comisd">, PD, VEX;
2448 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2450 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2453 let Pattern = []<dag> in {
2454 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2456 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2460 let isCodeGenOnly = 1 in {
2461 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2462 load, "ucomiss">, PS;
2463 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2464 load, "ucomisd">, PD;
2466 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2468 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2471 } // Defs = [EFLAGS]
2473 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2474 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2475 Operand CC, Intrinsic Int, string asm,
2476 string asm_alt, Domain d,
2477 OpndItins itins = SSE_ALU_F32P> {
2478 def rri : PIi8<0xC2, MRMSrcReg,
2479 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2480 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2483 def rmi : PIi8<0xC2, MRMSrcMem,
2484 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2485 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2487 Sched<[WriteFAddLd, ReadAfterLd]>;
2489 // Accept explicit immediate argument form instead of comparison code.
2490 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2491 def rri_alt : PIi8<0xC2, MRMSrcReg,
2492 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2493 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2494 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2495 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2496 asm_alt, [], itins.rm, d>,
2497 Sched<[WriteFAddLd, ReadAfterLd]>;
2501 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2502 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2503 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2504 SSEPackedSingle>, PS, VEX_4V;
2505 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2506 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2507 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2508 SSEPackedDouble>, PD, VEX_4V;
2509 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2510 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2511 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2512 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2513 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2514 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2515 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2516 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2517 let Constraints = "$src1 = $dst" in {
2518 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2519 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2520 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2521 SSEPackedSingle, SSE_ALU_F32P>, PS;
2522 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2523 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2524 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2525 SSEPackedDouble, SSE_ALU_F64P>, PD;
2528 let Predicates = [HasAVX] in {
2529 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2530 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2531 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2532 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2533 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2534 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2535 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2536 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2538 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2539 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2540 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2541 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2542 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2543 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2544 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2545 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2548 let Predicates = [UseSSE1] in {
2549 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2550 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2551 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2552 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2555 let Predicates = [UseSSE2] in {
2556 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2557 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2558 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2559 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2562 //===----------------------------------------------------------------------===//
2563 // SSE 1 & 2 - Shuffle Instructions
2564 //===----------------------------------------------------------------------===//
2566 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2567 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2568 ValueType vt, string asm, PatFrag mem_frag,
2570 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2571 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2572 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2573 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2574 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2575 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2576 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2577 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2578 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2579 Sched<[WriteFShuffle]>;
2582 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2583 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2584 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2585 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2586 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2587 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2588 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2589 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2590 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2591 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2592 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2593 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2595 let Constraints = "$src1 = $dst" in {
2596 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2597 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2598 memopv4f32, SSEPackedSingle>, PS;
2599 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2600 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2601 memopv2f64, SSEPackedDouble>, PD;
2604 let Predicates = [HasAVX] in {
2605 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2606 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2607 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2608 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2609 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2611 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2612 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2613 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2614 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2615 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2618 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2619 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2620 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2621 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2622 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2624 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2625 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2626 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2627 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2628 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2631 let Predicates = [UseSSE1] in {
2632 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2633 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2634 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2635 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2636 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2639 let Predicates = [UseSSE2] in {
2640 // Generic SHUFPD patterns
2641 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2642 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2643 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2644 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2645 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2648 //===----------------------------------------------------------------------===//
2649 // SSE 1 & 2 - Unpack FP Instructions
2650 //===----------------------------------------------------------------------===//
2652 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2653 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2654 PatFrag mem_frag, RegisterClass RC,
2655 X86MemOperand x86memop, string asm,
2657 def rr : PI<opc, MRMSrcReg,
2658 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2660 (vt (OpNode RC:$src1, RC:$src2)))],
2661 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2662 def rm : PI<opc, MRMSrcMem,
2663 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2665 (vt (OpNode RC:$src1,
2666 (mem_frag addr:$src2))))],
2668 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2671 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2672 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2673 SSEPackedSingle>, PS, VEX_4V;
2674 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2675 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2676 SSEPackedDouble>, PD, VEX_4V;
2677 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2678 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2679 SSEPackedSingle>, PS, VEX_4V;
2680 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2681 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2682 SSEPackedDouble>, PD, VEX_4V;
2684 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2685 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2686 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2687 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2688 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2689 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2690 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2691 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2692 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2693 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2694 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2695 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2697 let Constraints = "$src1 = $dst" in {
2698 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2699 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2700 SSEPackedSingle>, PS;
2701 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2702 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2703 SSEPackedDouble>, PD;
2704 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2705 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2706 SSEPackedSingle>, PS;
2707 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2708 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2709 SSEPackedDouble>, PD;
2710 } // Constraints = "$src1 = $dst"
2712 let Predicates = [HasAVX1Only] in {
2713 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2714 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2715 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2716 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2717 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2718 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2719 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2720 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2722 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2723 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2724 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2725 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2726 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2727 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2728 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2729 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2732 let Predicates = [HasAVX] in {
2733 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2734 // problem is during lowering, where it's not possible to recognize the load
2735 // fold cause it has two uses through a bitcast. One use disappears at isel
2736 // time and the fold opportunity reappears.
2737 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2738 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2741 let Predicates = [UseSSE2] in {
2742 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2743 // problem is during lowering, where it's not possible to recognize the load
2744 // fold cause it has two uses through a bitcast. One use disappears at isel
2745 // time and the fold opportunity reappears.
2746 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2747 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2750 //===----------------------------------------------------------------------===//
2751 // SSE 1 & 2 - Extract Floating-Point Sign mask
2752 //===----------------------------------------------------------------------===//
2754 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2755 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2757 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2758 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2759 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2760 Sched<[WriteVecLogic]>;
2763 let Predicates = [HasAVX] in {
2764 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2765 "movmskps", SSEPackedSingle>, PS, VEX;
2766 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2767 "movmskpd", SSEPackedDouble>, PD, VEX;
2768 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2769 "movmskps", SSEPackedSingle>, PS,
2771 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2772 "movmskpd", SSEPackedDouble>, PD,
2775 def : Pat<(i32 (X86fgetsign FR32:$src)),
2776 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2777 def : Pat<(i64 (X86fgetsign FR32:$src)),
2778 (SUBREG_TO_REG (i64 0),
2779 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2780 def : Pat<(i32 (X86fgetsign FR64:$src)),
2781 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2782 def : Pat<(i64 (X86fgetsign FR64:$src)),
2783 (SUBREG_TO_REG (i64 0),
2784 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2787 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2788 SSEPackedSingle>, PS;
2789 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2790 SSEPackedDouble>, PD;
2792 def : Pat<(i32 (X86fgetsign FR32:$src)),
2793 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2794 Requires<[UseSSE1]>;
2795 def : Pat<(i64 (X86fgetsign FR32:$src)),
2796 (SUBREG_TO_REG (i64 0),
2797 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2798 Requires<[UseSSE1]>;
2799 def : Pat<(i32 (X86fgetsign FR64:$src)),
2800 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2801 Requires<[UseSSE2]>;
2802 def : Pat<(i64 (X86fgetsign FR64:$src)),
2803 (SUBREG_TO_REG (i64 0),
2804 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2805 Requires<[UseSSE2]>;
2807 //===---------------------------------------------------------------------===//
2808 // SSE2 - Packed Integer Logical Instructions
2809 //===---------------------------------------------------------------------===//
2811 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2813 /// PDI_binop_rm - Simple SSE2 binary operator.
2814 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2815 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2816 X86MemOperand x86memop, OpndItins itins,
2817 bit IsCommutable, bit Is2Addr> {
2818 let isCommutable = IsCommutable in
2819 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2820 (ins RC:$src1, RC:$src2),
2822 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2823 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2824 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2825 Sched<[itins.Sched]>;
2826 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2827 (ins RC:$src1, x86memop:$src2),
2829 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2830 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2831 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2832 (bitconvert (memop_frag addr:$src2)))))],
2834 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2836 } // ExeDomain = SSEPackedInt
2838 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2839 ValueType OpVT128, ValueType OpVT256,
2840 OpndItins itins, bit IsCommutable = 0> {
2841 let Predicates = [HasAVX] in
2842 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2843 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2845 let Constraints = "$src1 = $dst" in
2846 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2847 memopv2i64, i128mem, itins, IsCommutable, 1>;
2849 let Predicates = [HasAVX2] in
2850 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2851 OpVT256, VR256, loadv4i64, i256mem, itins,
2852 IsCommutable, 0>, VEX_4V, VEX_L;
2855 // These are ordered here for pattern ordering requirements with the fp versions
2857 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2858 SSE_VEC_BIT_ITINS_P, 1>;
2859 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2860 SSE_VEC_BIT_ITINS_P, 1>;
2861 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2862 SSE_VEC_BIT_ITINS_P, 1>;
2863 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2864 SSE_VEC_BIT_ITINS_P, 0>;
2866 //===----------------------------------------------------------------------===//
2867 // SSE 1 & 2 - Logical Instructions
2868 //===----------------------------------------------------------------------===//
2870 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2872 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2873 SDNode OpNode, OpndItins itins> {
2874 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2875 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2878 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2879 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2882 let Constraints = "$src1 = $dst" in {
2883 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2884 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2887 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2888 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2893 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2894 let isCodeGenOnly = 1 in {
2895 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2897 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2899 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2902 let isCommutable = 0 in
2903 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2907 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2909 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2911 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2912 !strconcat(OpcodeStr, "ps"), f256mem,
2913 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2914 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2915 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2917 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2918 !strconcat(OpcodeStr, "pd"), f256mem,
2919 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2920 (bc_v4i64 (v4f64 VR256:$src2))))],
2921 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2922 (loadv4i64 addr:$src2)))], 0>,
2925 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2926 // are all promoted to v2i64, and the patterns are covered by the int
2927 // version. This is needed in SSE only, because v2i64 isn't supported on
2928 // SSE1, but only on SSE2.
2929 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2930 !strconcat(OpcodeStr, "ps"), f128mem, [],
2931 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2932 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2934 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2935 !strconcat(OpcodeStr, "pd"), f128mem,
2936 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2937 (bc_v2i64 (v2f64 VR128:$src2))))],
2938 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2939 (loadv2i64 addr:$src2)))], 0>,
2942 let Constraints = "$src1 = $dst" in {
2943 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2944 !strconcat(OpcodeStr, "ps"), f128mem,
2945 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2946 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2947 (memopv2i64 addr:$src2)))]>, PS;
2949 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2950 !strconcat(OpcodeStr, "pd"), f128mem,
2951 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2952 (bc_v2i64 (v2f64 VR128:$src2))))],
2953 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2954 (memopv2i64 addr:$src2)))]>, PD;
2958 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2959 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2960 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2961 let isCommutable = 0 in
2962 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2964 // AVX1 requires type coercions in order to fold loads directly into logical
2966 let Predicates = [HasAVX1Only] in {
2967 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
2968 (VANDPSYrm VR256:$src1, addr:$src2)>;
2969 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
2970 (VORPSYrm VR256:$src1, addr:$src2)>;
2971 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
2972 (VXORPSYrm VR256:$src1, addr:$src2)>;
2973 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
2974 (VANDNPSYrm VR256:$src1, addr:$src2)>;
2977 //===----------------------------------------------------------------------===//
2978 // SSE 1 & 2 - Arithmetic Instructions
2979 //===----------------------------------------------------------------------===//
2981 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2984 /// In addition, we also have a special variant of the scalar form here to
2985 /// represent the associated intrinsic operation. This form is unlike the
2986 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2987 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2989 /// These three forms can each be reg+reg or reg+mem.
2992 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2994 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2995 SDNode OpNode, SizeItins itins> {
2996 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2997 VR128, v4f32, f128mem, loadv4f32,
2998 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
2999 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3000 VR128, v2f64, f128mem, loadv2f64,
3001 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3003 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3004 OpNode, VR256, v8f32, f256mem, loadv8f32,
3005 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3006 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3007 OpNode, VR256, v4f64, f256mem, loadv4f64,
3008 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3010 let Constraints = "$src1 = $dst" in {
3011 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3012 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3014 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3015 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3020 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3022 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3023 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3024 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3025 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3027 let Constraints = "$src1 = $dst" in {
3028 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3029 OpNode, FR32, f32mem, itins.s>, XS;
3030 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3031 OpNode, FR64, f64mem, itins.d>, XD;
3035 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3037 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3038 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3039 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3040 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3041 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3042 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3044 let Constraints = "$src1 = $dst" in {
3045 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3046 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3048 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3049 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3054 // Binary Arithmetic instructions
3055 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3056 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3057 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3058 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3059 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3060 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3061 let isCommutable = 0 in {
3062 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3063 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3064 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3065 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3066 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3067 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3068 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3069 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3070 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3071 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3072 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3073 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3076 let isCodeGenOnly = 1 in {
3077 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3078 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3079 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3080 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3083 // Patterns used to select SSE scalar fp arithmetic instructions from
3084 // a scalar fp operation followed by a blend.
3086 // These patterns know, for example, how to select an ADDSS from a
3087 // float add plus vector insert.
3089 // The effect is that the backend no longer emits unnecessary vector
3090 // insert instructions immediately after SSE scalar fp instructions
3091 // like addss or mulss.
3093 // For example, given the following code:
3094 // __m128 foo(__m128 A, __m128 B) {
3099 // previously we generated:
3100 // addss %xmm0, %xmm1
3101 // movss %xmm1, %xmm0
3104 // addss %xmm1, %xmm0
3106 let Predicates = [UseSSE1] in {
3107 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3108 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3110 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3111 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3112 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3114 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3115 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3116 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3118 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3119 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3120 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3122 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3125 let Predicates = [UseSSE2] in {
3126 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3127 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3128 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3130 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3131 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3132 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3134 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3135 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3136 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3138 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3139 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3140 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3142 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3145 let Predicates = [UseSSE41] in {
3146 // If the subtarget has SSE4.1 but not AVX, the vector insert instruction is
3147 // lowered into a X86insertps or a X86Blendi rather than a X86Movss. When
3148 // selecting SSE scalar single-precision fp arithmetic instructions, make
3149 // sure that we correctly match them.
3151 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3152 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3153 FR32:$src))), (iPTR 0))),
3154 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3155 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3156 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3157 FR32:$src))), (iPTR 0))),
3158 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3159 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3160 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3161 FR32:$src))), (iPTR 0))),
3162 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3163 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3164 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3165 FR32:$src))), (iPTR 0))),
3166 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3168 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3169 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3170 FR32:$src))), (i8 1))),
3171 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3172 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3173 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3174 FR32:$src))), (i8 1))),
3175 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3176 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3177 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3178 FR32:$src))), (i8 1))),
3179 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3180 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3181 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3182 FR32:$src))), (i8 1))),
3183 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3185 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3186 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3187 FR64:$src))), (i8 1))),
3188 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3189 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3190 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3191 FR64:$src))), (i8 1))),
3192 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3193 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3194 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3195 FR64:$src))), (i8 1))),
3196 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3197 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3198 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3199 FR64:$src))), (i8 1))),
3200 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3202 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3203 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3204 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3205 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3206 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3207 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3208 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3209 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3210 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3211 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3212 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3213 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3214 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3215 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3216 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3217 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3220 let Predicates = [HasAVX] in {
3221 // The following patterns select AVX Scalar single/double precision fp
3222 // arithmetic instructions.
3224 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3225 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3227 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3228 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3229 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3231 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3232 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3233 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3235 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3236 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3237 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3239 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3240 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3241 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3242 FR32:$src))), (iPTR 0))),
3243 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3244 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3245 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3246 FR32:$src))), (iPTR 0))),
3247 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3248 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3249 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3250 FR32:$src))), (iPTR 0))),
3251 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3252 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3253 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3254 FR32:$src))), (iPTR 0))),
3255 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3257 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3258 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3259 FR32:$src))), (i8 1))),
3260 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3261 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3262 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3263 FR32:$src))), (i8 1))),
3264 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3265 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3266 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3267 FR32:$src))), (i8 1))),
3268 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3269 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3270 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3271 FR32:$src))), (i8 1))),
3272 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3274 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3275 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3276 FR64:$src))), (i8 1))),
3277 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3278 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3279 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3280 FR64:$src))), (i8 1))),
3281 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3282 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3283 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3284 FR64:$src))), (i8 1))),
3285 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3286 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3287 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3288 FR64:$src))), (i8 1))),
3289 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3291 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3292 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3293 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3294 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3295 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3296 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3297 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3298 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3299 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3300 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3301 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3302 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3303 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3304 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3305 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3306 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3309 // Patterns used to select SSE scalar fp arithmetic instructions from
3310 // a vector packed single/double fp operation followed by a vector insert.
3312 // The effect is that the backend converts the packed fp instruction
3313 // followed by a vector insert into a single SSE scalar fp instruction.
3315 // For example, given the following code:
3316 // __m128 foo(__m128 A, __m128 B) {
3317 // __m128 C = A + B;
3318 // return (__m128) {c[0], a[1], a[2], a[3]};
3321 // previously we generated:
3322 // addps %xmm0, %xmm1
3323 // movss %xmm1, %xmm0
3326 // addss %xmm1, %xmm0
3328 let Predicates = [UseSSE1] in {
3329 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3330 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3331 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3332 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3333 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3334 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3335 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3336 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3337 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3338 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3339 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3340 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3343 let Predicates = [UseSSE2] in {
3344 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3345 // from a packed double-precision fp instruction plus movsd.
3347 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3348 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3349 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3350 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3351 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3352 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3353 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3354 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3355 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3356 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3357 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3358 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3361 let Predicates = [UseSSE41] in {
3362 // With SSE4.1 we may see these operations using X86Blendi rather than
3364 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3365 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3366 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3367 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3368 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3369 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3370 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3371 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3372 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3373 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3374 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3375 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3377 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3378 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3379 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3380 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3381 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3382 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3383 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3384 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3385 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3386 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3387 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3388 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3390 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3391 (v2f64 VR128:$dst), (i8 2))),
3392 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3393 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3394 (v2f64 VR128:$dst), (i8 2))),
3395 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3396 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3397 (v2f64 VR128:$dst), (i8 2))),
3398 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3399 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3400 (v2f64 VR128:$dst), (i8 2))),
3401 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3404 let Predicates = [HasAVX] in {
3405 // The following patterns select AVX Scalar single/double precision fp
3406 // arithmetic instructions from a packed single precision fp instruction
3407 // plus movss/movsd.
3409 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3410 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3411 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3412 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3413 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3414 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3415 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3416 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3417 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3418 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3419 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3420 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3421 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3422 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3423 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3424 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3425 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3426 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3427 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3428 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3429 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3430 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3431 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3432 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3434 // Also handle X86Blendi-based patterns.
3435 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3436 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3437 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3438 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3439 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3440 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3441 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3442 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3443 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3444 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3445 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3446 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3448 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3449 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3450 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3451 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3452 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3453 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3454 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3455 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3456 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3457 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3458 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3459 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3461 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3462 (v2f64 VR128:$dst), (i8 2))),
3463 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3464 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3465 (v2f64 VR128:$dst), (i8 2))),
3466 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3467 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3468 (v2f64 VR128:$dst), (i8 2))),
3469 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3470 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3471 (v2f64 VR128:$dst), (i8 2))),
3472 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3476 /// In addition, we also have a special variant of the scalar form here to
3477 /// represent the associated intrinsic operation. This form is unlike the
3478 /// plain scalar form, in that it takes an entire vector (instead of a
3479 /// scalar) and leaves the top elements undefined.
3481 /// And, we have a special variant form for a full-vector intrinsic form.
3483 let Sched = WriteFSqrt in {
3484 def SSE_SQRTPS : OpndItins<
3485 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3488 def SSE_SQRTSS : OpndItins<
3489 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3492 def SSE_SQRTPD : OpndItins<
3493 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3496 def SSE_SQRTSD : OpndItins<
3497 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3501 let Sched = WriteFRsqrt in {
3502 def SSE_RSQRTPS : OpndItins<
3503 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3506 def SSE_RSQRTSS : OpndItins<
3507 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3511 let Sched = WriteFRcp in {
3512 def SSE_RCPP : OpndItins<
3513 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3516 def SSE_RCPS : OpndItins<
3517 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3521 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3522 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3523 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3524 let Predicates = [HasAVX], hasSideEffects = 0 in {
3525 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3526 (ins FR32:$src1, FR32:$src2),
3527 !strconcat("v", OpcodeStr,
3528 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3529 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3530 let mayLoad = 1 in {
3531 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3532 (ins FR32:$src1,f32mem:$src2),
3533 !strconcat("v", OpcodeStr,
3534 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3535 []>, VEX_4V, VEX_LIG,
3536 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3537 let isCodeGenOnly = 1 in
3538 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3539 (ins VR128:$src1, ssmem:$src2),
3540 !strconcat("v", OpcodeStr,
3541 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3542 []>, VEX_4V, VEX_LIG,
3543 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3547 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3548 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3549 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3550 // For scalar unary operations, fold a load into the operation
3551 // only in OptForSize mode. It eliminates an instruction, but it also
3552 // eliminates a whole-register clobber (the load), so it introduces a
3553 // partial register update condition.
3554 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3555 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3556 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3557 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3558 let isCodeGenOnly = 1 in {
3559 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3560 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3561 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3562 Sched<[itins.Sched]>;
3563 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3564 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3565 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3566 Sched<[itins.Sched.Folded]>;
3570 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3571 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3573 let Predicates = [HasAVX], hasSideEffects = 0 in {
3574 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3575 (ins FR32:$src1, FR32:$src2),
3576 !strconcat("v", OpcodeStr,
3577 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3578 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3579 let mayLoad = 1 in {
3580 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3581 (ins FR32:$src1,f32mem:$src2),
3582 !strconcat("v", OpcodeStr,
3583 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3584 []>, VEX_4V, VEX_LIG,
3585 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3586 let isCodeGenOnly = 1 in
3587 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3588 (ins VR128:$src1, ssmem:$src2),
3589 !strconcat("v", OpcodeStr,
3590 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3591 []>, VEX_4V, VEX_LIG,
3592 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3596 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3597 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3598 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3599 // For scalar unary operations, fold a load into the operation
3600 // only in OptForSize mode. It eliminates an instruction, but it also
3601 // eliminates a whole-register clobber (the load), so it introduces a
3602 // partial register update condition.
3603 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3604 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3605 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3606 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3607 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3608 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3609 (ins VR128:$src1, VR128:$src2),
3610 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3611 [], itins.rr>, Sched<[itins.Sched]>;
3612 let mayLoad = 1, hasSideEffects = 0 in
3613 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3614 (ins VR128:$src1, ssmem:$src2),
3615 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3616 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3620 /// sse1_fp_unop_p - SSE1 unops in packed form.
3621 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3623 let Predicates = [HasAVX] in {
3624 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3625 !strconcat("v", OpcodeStr,
3626 "ps\t{$src, $dst|$dst, $src}"),
3627 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3628 itins.rr>, VEX, Sched<[itins.Sched]>;
3629 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3630 !strconcat("v", OpcodeStr,
3631 "ps\t{$src, $dst|$dst, $src}"),
3632 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3633 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3634 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3635 !strconcat("v", OpcodeStr,
3636 "ps\t{$src, $dst|$dst, $src}"),
3637 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3638 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3639 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3640 !strconcat("v", OpcodeStr,
3641 "ps\t{$src, $dst|$dst, $src}"),
3642 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3643 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3646 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3647 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3648 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3649 Sched<[itins.Sched]>;
3650 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3651 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3652 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3653 Sched<[itins.Sched.Folded]>;
3656 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3657 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3658 Intrinsic V4F32Int, Intrinsic V8F32Int,
3660 let isCodeGenOnly = 1 in {
3661 let Predicates = [HasAVX] in {
3662 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3663 !strconcat("v", OpcodeStr,
3664 "ps\t{$src, $dst|$dst, $src}"),
3665 [(set VR128:$dst, (V4F32Int VR128:$src))],
3666 itins.rr>, VEX, Sched<[itins.Sched]>;
3667 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3668 !strconcat("v", OpcodeStr,
3669 "ps\t{$src, $dst|$dst, $src}"),
3670 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3671 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3672 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3673 !strconcat("v", OpcodeStr,
3674 "ps\t{$src, $dst|$dst, $src}"),
3675 [(set VR256:$dst, (V8F32Int VR256:$src))],
3676 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3677 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3679 !strconcat("v", OpcodeStr,
3680 "ps\t{$src, $dst|$dst, $src}"),
3681 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3682 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3685 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3686 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3687 [(set VR128:$dst, (V4F32Int VR128:$src))],
3688 itins.rr>, Sched<[itins.Sched]>;
3689 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3690 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3691 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3692 itins.rm>, Sched<[itins.Sched.Folded]>;
3693 } // isCodeGenOnly = 1
3696 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3697 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3698 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3699 let Predicates = [HasAVX], hasSideEffects = 0 in {
3700 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3701 (ins FR64:$src1, FR64:$src2),
3702 !strconcat("v", OpcodeStr,
3703 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3704 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3705 let mayLoad = 1 in {
3706 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3707 (ins FR64:$src1,f64mem:$src2),
3708 !strconcat("v", OpcodeStr,
3709 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3710 []>, VEX_4V, VEX_LIG,
3711 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3712 let isCodeGenOnly = 1 in
3713 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3714 (ins VR128:$src1, sdmem:$src2),
3715 !strconcat("v", OpcodeStr,
3716 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3717 []>, VEX_4V, VEX_LIG,
3718 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3722 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3723 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3724 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3725 Sched<[itins.Sched]>;
3726 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3727 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3728 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3729 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3730 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3731 let isCodeGenOnly = 1 in {
3732 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3733 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3734 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3735 Sched<[itins.Sched]>;
3736 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3737 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3738 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3739 Sched<[itins.Sched.Folded]>;
3743 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3744 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3745 SDNode OpNode, OpndItins itins> {
3746 let Predicates = [HasAVX] in {
3747 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3748 !strconcat("v", OpcodeStr,
3749 "pd\t{$src, $dst|$dst, $src}"),
3750 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3751 itins.rr>, VEX, Sched<[itins.Sched]>;
3752 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3753 !strconcat("v", OpcodeStr,
3754 "pd\t{$src, $dst|$dst, $src}"),
3755 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3756 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3757 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3758 !strconcat("v", OpcodeStr,
3759 "pd\t{$src, $dst|$dst, $src}"),
3760 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3761 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3762 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3763 !strconcat("v", OpcodeStr,
3764 "pd\t{$src, $dst|$dst, $src}"),
3765 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3766 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3769 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3770 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3771 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3772 Sched<[itins.Sched]>;
3773 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3774 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3775 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3776 Sched<[itins.Sched.Folded]>;
3780 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3782 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3783 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3785 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3787 // Reciprocal approximations. Note that these typically require refinement
3788 // in order to obtain suitable precision.
3789 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3790 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
3791 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3792 int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
3793 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3794 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3795 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3796 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3798 let Predicates = [UseAVX] in {
3799 def : Pat<(f32 (fsqrt FR32:$src)),
3800 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3801 def : Pat<(f32 (fsqrt (load addr:$src))),
3802 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3803 Requires<[HasAVX, OptForSize]>;
3804 def : Pat<(f64 (fsqrt FR64:$src)),
3805 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3806 def : Pat<(f64 (fsqrt (load addr:$src))),
3807 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3808 Requires<[HasAVX, OptForSize]>;
3810 def : Pat<(f32 (X86frsqrt FR32:$src)),
3811 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3812 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3813 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3814 Requires<[HasAVX, OptForSize]>;
3816 def : Pat<(f32 (X86frcp FR32:$src)),
3817 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3818 def : Pat<(f32 (X86frcp (load addr:$src))),
3819 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3820 Requires<[HasAVX, OptForSize]>;
3822 let Predicates = [UseAVX] in {
3823 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3824 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3825 (COPY_TO_REGCLASS VR128:$src, FR32)),
3827 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3828 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3830 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3831 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3832 (COPY_TO_REGCLASS VR128:$src, FR64)),
3834 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3835 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3838 let Predicates = [HasAVX] in {
3839 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3840 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3841 (COPY_TO_REGCLASS VR128:$src, FR32)),
3843 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3844 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3846 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3847 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3848 (COPY_TO_REGCLASS VR128:$src, FR32)),
3850 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3851 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3854 // Reciprocal approximations. Note that these typically require refinement
3855 // in order to obtain suitable precision.
3856 let Predicates = [UseSSE1] in {
3857 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3858 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3859 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3860 (RCPSSr_Int VR128:$src, VR128:$src)>;
3863 // There is no f64 version of the reciprocal approximation instructions.
3865 //===----------------------------------------------------------------------===//
3866 // SSE 1 & 2 - Non-temporal stores
3867 //===----------------------------------------------------------------------===//
3869 let AddedComplexity = 400 in { // Prefer non-temporal versions
3870 let SchedRW = [WriteStore] in {
3871 let Predicates = [HasAVX, NoVLX] in {
3872 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3873 (ins f128mem:$dst, VR128:$src),
3874 "movntps\t{$src, $dst|$dst, $src}",
3875 [(alignednontemporalstore (v4f32 VR128:$src),
3877 IIC_SSE_MOVNT>, VEX;
3878 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3879 (ins f128mem:$dst, VR128:$src),
3880 "movntpd\t{$src, $dst|$dst, $src}",
3881 [(alignednontemporalstore (v2f64 VR128:$src),
3883 IIC_SSE_MOVNT>, VEX;
3885 let ExeDomain = SSEPackedInt in
3886 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3887 (ins f128mem:$dst, VR128:$src),
3888 "movntdq\t{$src, $dst|$dst, $src}",
3889 [(alignednontemporalstore (v2i64 VR128:$src),
3891 IIC_SSE_MOVNT>, VEX;
3893 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3894 (ins f256mem:$dst, VR256:$src),
3895 "movntps\t{$src, $dst|$dst, $src}",
3896 [(alignednontemporalstore (v8f32 VR256:$src),
3898 IIC_SSE_MOVNT>, VEX, VEX_L;
3899 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3900 (ins f256mem:$dst, VR256:$src),
3901 "movntpd\t{$src, $dst|$dst, $src}",
3902 [(alignednontemporalstore (v4f64 VR256:$src),
3904 IIC_SSE_MOVNT>, VEX, VEX_L;
3905 let ExeDomain = SSEPackedInt in
3906 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3907 (ins f256mem:$dst, VR256:$src),
3908 "movntdq\t{$src, $dst|$dst, $src}",
3909 [(alignednontemporalstore (v4i64 VR256:$src),
3911 IIC_SSE_MOVNT>, VEX, VEX_L;
3914 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3915 "movntps\t{$src, $dst|$dst, $src}",
3916 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3918 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3919 "movntpd\t{$src, $dst|$dst, $src}",
3920 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3923 let ExeDomain = SSEPackedInt in
3924 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3925 "movntdq\t{$src, $dst|$dst, $src}",
3926 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3929 // There is no AVX form for instructions below this point
3930 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3931 "movnti{l}\t{$src, $dst|$dst, $src}",
3932 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3934 PS, Requires<[HasSSE2]>;
3935 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3936 "movnti{q}\t{$src, $dst|$dst, $src}",
3937 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3939 PS, Requires<[HasSSE2]>;
3940 } // SchedRW = [WriteStore]
3942 let Predicates = [HasAVX, NoVLX] in {
3943 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3944 (VMOVNTPSmr addr:$dst, VR128:$src)>;
3947 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3948 (MOVNTPSmr addr:$dst, VR128:$src)>;
3950 } // AddedComplexity
3952 //===----------------------------------------------------------------------===//
3953 // SSE 1 & 2 - Prefetch and memory fence
3954 //===----------------------------------------------------------------------===//
3956 // Prefetch intrinsic.
3957 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3958 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3959 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3960 IIC_SSE_PREFETCH>, TB;
3961 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3962 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3963 IIC_SSE_PREFETCH>, TB;
3964 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3965 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3966 IIC_SSE_PREFETCH>, TB;
3967 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3968 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3969 IIC_SSE_PREFETCH>, TB;
3972 // FIXME: How should flush instruction be modeled?
3973 let SchedRW = [WriteLoad] in {
3975 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3976 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3977 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3980 let SchedRW = [WriteNop] in {
3981 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3982 // was introduced with SSE2, it's backward compatible.
3983 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3984 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3985 OBXS, Requires<[HasSSE2]>;
3988 let SchedRW = [WriteFence] in {
3989 // Load, store, and memory fence
3990 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3991 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3992 TB, Requires<[HasSSE1]>;
3993 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3994 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3995 TB, Requires<[HasSSE2]>;
3996 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3997 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3998 TB, Requires<[HasSSE2]>;
4001 def : Pat<(X86SFence), (SFENCE)>;
4002 def : Pat<(X86LFence), (LFENCE)>;
4003 def : Pat<(X86MFence), (MFENCE)>;
4005 //===----------------------------------------------------------------------===//
4006 // SSE 1 & 2 - Load/Store XCSR register
4007 //===----------------------------------------------------------------------===//
4009 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
4010 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
4011 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
4012 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
4013 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
4014 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
4016 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
4017 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
4018 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
4019 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
4020 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
4021 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
4023 //===---------------------------------------------------------------------===//
4024 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
4025 //===---------------------------------------------------------------------===//
4027 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4029 let hasSideEffects = 0, SchedRW = [WriteMove] in {
4030 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4031 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
4033 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4034 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
4036 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4037 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4039 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4040 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4045 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4046 SchedRW = [WriteMove] in {
4047 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4048 "movdqa\t{$src, $dst|$dst, $src}", [],
4051 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4052 "movdqa\t{$src, $dst|$dst, $src}", [],
4053 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
4054 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4055 "movdqu\t{$src, $dst|$dst, $src}", [],
4058 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4059 "movdqu\t{$src, $dst|$dst, $src}", [],
4060 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
4063 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4064 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4065 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4066 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4068 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4069 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4071 let Predicates = [HasAVX] in {
4072 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4073 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4075 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4076 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4081 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4082 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
4083 (ins i128mem:$dst, VR128:$src),
4084 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4086 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
4087 (ins i256mem:$dst, VR256:$src),
4088 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4090 let Predicates = [HasAVX] in {
4091 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4092 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4094 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
4095 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4100 let SchedRW = [WriteMove] in {
4101 let hasSideEffects = 0 in
4102 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4103 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
4105 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4106 "movdqu\t{$src, $dst|$dst, $src}",
4107 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4110 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
4111 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4112 "movdqa\t{$src, $dst|$dst, $src}", [],
4115 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4116 "movdqu\t{$src, $dst|$dst, $src}",
4117 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4121 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4122 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4123 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4124 "movdqa\t{$src, $dst|$dst, $src}",
4125 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
4127 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4128 "movdqu\t{$src, $dst|$dst, $src}",
4129 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
4131 XS, Requires<[UseSSE2]>;
4134 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4135 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4136 "movdqa\t{$src, $dst|$dst, $src}",
4137 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
4139 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4140 "movdqu\t{$src, $dst|$dst, $src}",
4141 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
4143 XS, Requires<[UseSSE2]>;
4146 } // ExeDomain = SSEPackedInt
4148 let Predicates = [HasAVX] in {
4149 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4150 (VMOVDQUmr addr:$dst, VR128:$src)>;
4151 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
4152 (VMOVDQUYmr addr:$dst, VR256:$src)>;
4154 let Predicates = [UseSSE2] in
4155 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4156 (MOVDQUmr addr:$dst, VR128:$src)>;
4158 //===---------------------------------------------------------------------===//
4159 // SSE2 - Packed Integer Arithmetic Instructions
4160 //===---------------------------------------------------------------------===//
4162 let Sched = WriteVecIMul in
4163 def SSE_PMADD : OpndItins<
4164 IIC_SSE_PMADD, IIC_SSE_PMADD
4167 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4169 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
4170 RegisterClass RC, PatFrag memop_frag,
4171 X86MemOperand x86memop,
4173 bit IsCommutable = 0,
4175 let isCommutable = IsCommutable in
4176 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4177 (ins RC:$src1, RC:$src2),
4179 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4180 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4181 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
4182 Sched<[itins.Sched]>;
4183 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4184 (ins RC:$src1, x86memop:$src2),
4186 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4187 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4188 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
4189 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
4192 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
4193 Intrinsic IntId256, OpndItins itins,
4194 bit IsCommutable = 0> {
4195 let Predicates = [HasAVX] in
4196 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
4197 VR128, loadv2i64, i128mem, itins,
4198 IsCommutable, 0>, VEX_4V;
4200 let Constraints = "$src1 = $dst" in
4201 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
4202 i128mem, itins, IsCommutable, 1>;
4204 let Predicates = [HasAVX2] in
4205 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
4206 VR256, loadv4i64, i256mem, itins,
4207 IsCommutable, 0>, VEX_4V, VEX_L;
4210 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
4211 string OpcodeStr, SDNode OpNode,
4212 SDNode OpNode2, RegisterClass RC,
4213 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
4214 ShiftOpndItins itins,
4216 // src2 is always 128-bit
4217 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4218 (ins RC:$src1, VR128:$src2),
4220 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4221 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4222 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
4223 itins.rr>, Sched<[WriteVecShift]>;
4224 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4225 (ins RC:$src1, i128mem:$src2),
4227 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4228 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4229 [(set RC:$dst, (DstVT (OpNode RC:$src1,
4230 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
4231 Sched<[WriteVecShiftLd, ReadAfterLd]>;
4232 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
4233 (ins RC:$src1, i8imm:$src2),
4235 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4236 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4237 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
4238 Sched<[WriteVecShift]>;
4241 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4242 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4243 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4244 PatFrag memop_frag, X86MemOperand x86memop,
4246 bit IsCommutable = 0, bit Is2Addr = 1> {
4247 let isCommutable = IsCommutable in
4248 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4249 (ins RC:$src1, RC:$src2),
4251 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4252 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4253 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4254 Sched<[itins.Sched]>;
4255 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4256 (ins RC:$src1, x86memop:$src2),
4258 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4259 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4260 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4261 (bitconvert (memop_frag addr:$src2)))))]>,
4262 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4264 } // ExeDomain = SSEPackedInt
4266 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4267 SSE_INTALU_ITINS_P, 1>;
4268 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4269 SSE_INTALU_ITINS_P, 1>;
4270 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4271 SSE_INTALU_ITINS_P, 1>;
4272 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4273 SSE_INTALUQ_ITINS_P, 1>;
4274 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4275 SSE_INTMUL_ITINS_P, 1>;
4276 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4277 SSE_INTMUL_ITINS_P, 1>;
4278 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4279 SSE_INTMUL_ITINS_P, 1>;
4280 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4281 SSE_INTALU_ITINS_P, 0>;
4282 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4283 SSE_INTALU_ITINS_P, 0>;
4284 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4285 SSE_INTALU_ITINS_P, 0>;
4286 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4287 SSE_INTALUQ_ITINS_P, 0>;
4288 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4289 SSE_INTALU_ITINS_P, 0>;
4290 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4291 SSE_INTALU_ITINS_P, 0>;
4292 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4293 SSE_INTALU_ITINS_P, 1>;
4294 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4295 SSE_INTALU_ITINS_P, 1>;
4296 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4297 SSE_INTALU_ITINS_P, 1>;
4298 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4299 SSE_INTALU_ITINS_P, 1>;
4302 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4303 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4304 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4305 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4306 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4307 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4308 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4309 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4310 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4311 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4312 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4313 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4314 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4315 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4316 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4317 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4318 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4319 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4320 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4321 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4323 let Predicates = [HasAVX] in
4324 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4325 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4327 let Predicates = [HasAVX2] in
4328 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4329 VR256, loadv4i64, i256mem,
4330 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4331 let Constraints = "$src1 = $dst" in
4332 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4333 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4335 //===---------------------------------------------------------------------===//
4336 // SSE2 - Packed Integer Logical Instructions
4337 //===---------------------------------------------------------------------===//
4339 let Predicates = [HasAVX] in {
4340 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4341 VR128, v8i16, v8i16, bc_v8i16,
4342 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4343 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4344 VR128, v4i32, v4i32, bc_v4i32,
4345 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4346 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4347 VR128, v2i64, v2i64, bc_v2i64,
4348 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4350 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4351 VR128, v8i16, v8i16, bc_v8i16,
4352 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4353 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4354 VR128, v4i32, v4i32, bc_v4i32,
4355 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4356 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4357 VR128, v2i64, v2i64, bc_v2i64,
4358 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4360 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4361 VR128, v8i16, v8i16, bc_v8i16,
4362 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4363 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4364 VR128, v4i32, v4i32, bc_v4i32,
4365 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4367 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4368 // 128-bit logical shifts.
4369 def VPSLLDQri : PDIi8<0x73, MRM7r,
4370 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4371 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4373 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4375 def VPSRLDQri : PDIi8<0x73, MRM3r,
4376 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4377 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4379 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4381 // PSRADQri doesn't exist in SSE[1-3].
4383 } // Predicates = [HasAVX]
4385 let Predicates = [HasAVX2] in {
4386 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4387 VR256, v16i16, v8i16, bc_v8i16,
4388 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4389 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4390 VR256, v8i32, v4i32, bc_v4i32,
4391 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4392 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4393 VR256, v4i64, v2i64, bc_v2i64,
4394 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4396 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4397 VR256, v16i16, v8i16, bc_v8i16,
4398 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4399 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4400 VR256, v8i32, v4i32, bc_v4i32,
4401 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4402 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4403 VR256, v4i64, v2i64, bc_v2i64,
4404 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4406 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4407 VR256, v16i16, v8i16, bc_v8i16,
4408 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4409 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4410 VR256, v8i32, v4i32, bc_v4i32,
4411 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4413 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4414 // 256-bit logical shifts.
4415 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4416 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4417 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4419 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4421 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4422 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4423 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4425 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4427 // PSRADQYri doesn't exist in SSE[1-3].
4429 } // Predicates = [HasAVX2]
4431 let Constraints = "$src1 = $dst" in {
4432 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4433 VR128, v8i16, v8i16, bc_v8i16,
4434 SSE_INTSHIFT_ITINS_P>;
4435 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4436 VR128, v4i32, v4i32, bc_v4i32,
4437 SSE_INTSHIFT_ITINS_P>;
4438 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4439 VR128, v2i64, v2i64, bc_v2i64,
4440 SSE_INTSHIFT_ITINS_P>;
4442 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4443 VR128, v8i16, v8i16, bc_v8i16,
4444 SSE_INTSHIFT_ITINS_P>;
4445 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4446 VR128, v4i32, v4i32, bc_v4i32,
4447 SSE_INTSHIFT_ITINS_P>;
4448 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4449 VR128, v2i64, v2i64, bc_v2i64,
4450 SSE_INTSHIFT_ITINS_P>;
4452 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4453 VR128, v8i16, v8i16, bc_v8i16,
4454 SSE_INTSHIFT_ITINS_P>;
4455 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4456 VR128, v4i32, v4i32, bc_v4i32,
4457 SSE_INTSHIFT_ITINS_P>;
4459 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4460 // 128-bit logical shifts.
4461 def PSLLDQri : PDIi8<0x73, MRM7r,
4462 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4463 "pslldq\t{$src2, $dst|$dst, $src2}",
4465 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4466 IIC_SSE_INTSHDQ_P_RI>;
4467 def PSRLDQri : PDIi8<0x73, MRM3r,
4468 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4469 "psrldq\t{$src2, $dst|$dst, $src2}",
4471 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4472 IIC_SSE_INTSHDQ_P_RI>;
4473 // PSRADQri doesn't exist in SSE[1-3].
4475 } // Constraints = "$src1 = $dst"
4477 let Predicates = [HasAVX] in {
4478 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4479 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4480 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4481 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4482 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4483 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4485 // Shift up / down and insert zero's.
4486 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4487 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4488 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4489 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4492 let Predicates = [HasAVX2] in {
4493 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4494 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4495 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4496 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4499 let Predicates = [UseSSE2] in {
4500 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4501 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4502 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4503 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4504 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4505 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4507 // Shift up / down and insert zero's.
4508 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4509 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4510 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4511 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4514 //===---------------------------------------------------------------------===//
4515 // SSE2 - Packed Integer Comparison Instructions
4516 //===---------------------------------------------------------------------===//
4518 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4519 SSE_INTALU_ITINS_P, 1>;
4520 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4521 SSE_INTALU_ITINS_P, 1>;
4522 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4523 SSE_INTALU_ITINS_P, 1>;
4524 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4525 SSE_INTALU_ITINS_P, 0>;
4526 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4527 SSE_INTALU_ITINS_P, 0>;
4528 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4529 SSE_INTALU_ITINS_P, 0>;
4531 //===---------------------------------------------------------------------===//
4532 // SSE2 - Packed Integer Shuffle Instructions
4533 //===---------------------------------------------------------------------===//
4535 let ExeDomain = SSEPackedInt in {
4536 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4538 let Predicates = [HasAVX] in {
4539 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4540 (ins VR128:$src1, i8imm:$src2),
4541 !strconcat("v", OpcodeStr,
4542 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4544 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4545 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4546 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4547 (ins i128mem:$src1, i8imm:$src2),
4548 !strconcat("v", OpcodeStr,
4549 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4551 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4552 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4553 Sched<[WriteShuffleLd]>;
4556 let Predicates = [HasAVX2] in {
4557 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4558 (ins VR256:$src1, i8imm:$src2),
4559 !strconcat("v", OpcodeStr,
4560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4562 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4563 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4564 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4565 (ins i256mem:$src1, i8imm:$src2),
4566 !strconcat("v", OpcodeStr,
4567 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4569 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4570 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4571 Sched<[WriteShuffleLd]>;
4574 let Predicates = [UseSSE2] in {
4575 def ri : Ii8<0x70, MRMSrcReg,
4576 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4577 !strconcat(OpcodeStr,
4578 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4580 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4581 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4582 def mi : Ii8<0x70, MRMSrcMem,
4583 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4584 !strconcat(OpcodeStr,
4585 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4587 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4588 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4589 Sched<[WriteShuffleLd, ReadAfterLd]>;
4592 } // ExeDomain = SSEPackedInt
4594 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4595 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4596 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4598 let Predicates = [HasAVX] in {
4599 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4600 (VPSHUFDmi addr:$src1, imm:$imm)>;
4601 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4602 (VPSHUFDri VR128:$src1, imm:$imm)>;
4605 let Predicates = [UseSSE2] in {
4606 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4607 (PSHUFDmi addr:$src1, imm:$imm)>;
4608 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4609 (PSHUFDri VR128:$src1, imm:$imm)>;
4612 //===---------------------------------------------------------------------===//
4613 // Packed Integer Pack Instructions (SSE & AVX)
4614 //===---------------------------------------------------------------------===//
4616 let ExeDomain = SSEPackedInt in {
4617 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4618 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4620 def rr : PDI<opc, MRMSrcReg,
4621 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4623 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4624 !strconcat(OpcodeStr,
4625 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4627 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4628 Sched<[WriteShuffle]>;
4629 def rm : PDI<opc, MRMSrcMem,
4630 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4632 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4633 !strconcat(OpcodeStr,
4634 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4636 (OutVT (OpNode VR128:$src1,
4637 (bc_frag (memopv2i64 addr:$src2)))))]>,
4638 Sched<[WriteShuffleLd, ReadAfterLd]>;
4641 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4642 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4643 def Yrr : PDI<opc, MRMSrcReg,
4644 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4645 !strconcat(OpcodeStr,
4646 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4648 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4649 Sched<[WriteShuffle]>;
4650 def Yrm : PDI<opc, MRMSrcMem,
4651 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4652 !strconcat(OpcodeStr,
4653 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4655 (OutVT (OpNode VR256:$src1,
4656 (bc_frag (memopv4i64 addr:$src2)))))]>,
4657 Sched<[WriteShuffleLd, ReadAfterLd]>;
4660 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4661 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4663 def rr : SS48I<opc, MRMSrcReg,
4664 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4666 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4667 !strconcat(OpcodeStr,
4668 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4670 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4671 Sched<[WriteShuffle]>;
4672 def rm : SS48I<opc, MRMSrcMem,
4673 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4675 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4676 !strconcat(OpcodeStr,
4677 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4679 (OutVT (OpNode VR128:$src1,
4680 (bc_frag (memopv2i64 addr:$src2)))))]>,
4681 Sched<[WriteShuffleLd, ReadAfterLd]>;
4684 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4685 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4686 def Yrr : SS48I<opc, MRMSrcReg,
4687 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4688 !strconcat(OpcodeStr,
4689 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4691 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4692 Sched<[WriteShuffle]>;
4693 def Yrm : SS48I<opc, MRMSrcMem,
4694 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4695 !strconcat(OpcodeStr,
4696 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4698 (OutVT (OpNode VR256:$src1,
4699 (bc_frag (memopv4i64 addr:$src2)))))]>,
4700 Sched<[WriteShuffleLd, ReadAfterLd]>;
4703 let Predicates = [HasAVX] in {
4704 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4705 bc_v8i16, 0>, VEX_4V;
4706 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4707 bc_v4i32, 0>, VEX_4V;
4709 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4710 bc_v8i16, 0>, VEX_4V;
4711 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4712 bc_v4i32, 0>, VEX_4V;
4715 let Predicates = [HasAVX2] in {
4716 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4717 bc_v16i16>, VEX_4V, VEX_L;
4718 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4719 bc_v8i32>, VEX_4V, VEX_L;
4721 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4722 bc_v16i16>, VEX_4V, VEX_L;
4723 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4724 bc_v8i32>, VEX_4V, VEX_L;
4727 let Constraints = "$src1 = $dst" in {
4728 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4730 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4733 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4736 let Predicates = [HasSSE41] in
4737 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4740 } // ExeDomain = SSEPackedInt
4742 //===---------------------------------------------------------------------===//
4743 // SSE2 - Packed Integer Unpack Instructions
4744 //===---------------------------------------------------------------------===//
4746 let ExeDomain = SSEPackedInt in {
4747 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4748 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4749 def rr : PDI<opc, MRMSrcReg,
4750 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4752 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4753 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4754 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4755 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4756 def rm : PDI<opc, MRMSrcMem,
4757 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4759 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4760 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4761 [(set VR128:$dst, (OpNode VR128:$src1,
4762 (bc_frag (memopv2i64
4765 Sched<[WriteShuffleLd, ReadAfterLd]>;
4768 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4769 SDNode OpNode, PatFrag bc_frag> {
4770 def Yrr : PDI<opc, MRMSrcReg,
4771 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4772 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4773 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4774 Sched<[WriteShuffle]>;
4775 def Yrm : PDI<opc, MRMSrcMem,
4776 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4777 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4778 [(set VR256:$dst, (OpNode VR256:$src1,
4779 (bc_frag (memopv4i64 addr:$src2))))]>,
4780 Sched<[WriteShuffleLd, ReadAfterLd]>;
4783 let Predicates = [HasAVX] in {
4784 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4785 bc_v16i8, 0>, VEX_4V;
4786 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4787 bc_v8i16, 0>, VEX_4V;
4788 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4789 bc_v4i32, 0>, VEX_4V;
4790 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4791 bc_v2i64, 0>, VEX_4V;
4793 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4794 bc_v16i8, 0>, VEX_4V;
4795 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4796 bc_v8i16, 0>, VEX_4V;
4797 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4798 bc_v4i32, 0>, VEX_4V;
4799 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4800 bc_v2i64, 0>, VEX_4V;
4803 let Predicates = [HasAVX2] in {
4804 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4805 bc_v32i8>, VEX_4V, VEX_L;
4806 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4807 bc_v16i16>, VEX_4V, VEX_L;
4808 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4809 bc_v8i32>, VEX_4V, VEX_L;
4810 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4811 bc_v4i64>, VEX_4V, VEX_L;
4813 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4814 bc_v32i8>, VEX_4V, VEX_L;
4815 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4816 bc_v16i16>, VEX_4V, VEX_L;
4817 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4818 bc_v8i32>, VEX_4V, VEX_L;
4819 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4820 bc_v4i64>, VEX_4V, VEX_L;
4823 let Constraints = "$src1 = $dst" in {
4824 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4826 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4828 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4830 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4833 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4835 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4837 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4839 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4842 } // ExeDomain = SSEPackedInt
4844 //===---------------------------------------------------------------------===//
4845 // SSE2 - Packed Integer Extract and Insert
4846 //===---------------------------------------------------------------------===//
4848 let ExeDomain = SSEPackedInt in {
4849 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4850 def rri : Ii8<0xC4, MRMSrcReg,
4851 (outs VR128:$dst), (ins VR128:$src1,
4852 GR32orGR64:$src2, i32i8imm:$src3),
4854 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4855 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4857 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4858 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4859 def rmi : Ii8<0xC4, MRMSrcMem,
4860 (outs VR128:$dst), (ins VR128:$src1,
4861 i16mem:$src2, i32i8imm:$src3),
4863 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4864 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4866 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4867 imm:$src3))], IIC_SSE_PINSRW>,
4868 Sched<[WriteShuffleLd, ReadAfterLd]>;
4872 let Predicates = [HasAVX] in
4873 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4874 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4875 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4876 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4877 imm:$src2))]>, PD, VEX,
4878 Sched<[WriteShuffle]>;
4879 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4880 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4881 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4882 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4883 imm:$src2))], IIC_SSE_PEXTRW>,
4884 Sched<[WriteShuffleLd, ReadAfterLd]>;
4887 let Predicates = [HasAVX] in
4888 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4890 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4891 defm PINSRW : sse2_pinsrw, PD;
4893 } // ExeDomain = SSEPackedInt
4895 //===---------------------------------------------------------------------===//
4896 // SSE2 - Packed Mask Creation
4897 //===---------------------------------------------------------------------===//
4899 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4901 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4903 "pmovmskb\t{$src, $dst|$dst, $src}",
4904 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4905 IIC_SSE_MOVMSK>, VEX;
4907 let Predicates = [HasAVX2] in {
4908 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4910 "pmovmskb\t{$src, $dst|$dst, $src}",
4911 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4915 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4916 "pmovmskb\t{$src, $dst|$dst, $src}",
4917 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4920 } // ExeDomain = SSEPackedInt
4922 //===---------------------------------------------------------------------===//
4923 // SSE2 - Conditional Store
4924 //===---------------------------------------------------------------------===//
4926 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4928 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4929 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4930 (ins VR128:$src, VR128:$mask),
4931 "maskmovdqu\t{$mask, $src|$src, $mask}",
4932 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4933 IIC_SSE_MASKMOV>, VEX;
4934 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4935 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4936 (ins VR128:$src, VR128:$mask),
4937 "maskmovdqu\t{$mask, $src|$src, $mask}",
4938 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4939 IIC_SSE_MASKMOV>, VEX;
4941 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4942 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4943 "maskmovdqu\t{$mask, $src|$src, $mask}",
4944 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4946 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4947 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4948 "maskmovdqu\t{$mask, $src|$src, $mask}",
4949 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4952 } // ExeDomain = SSEPackedInt
4954 //===---------------------------------------------------------------------===//
4955 // SSE2 - Move Doubleword
4956 //===---------------------------------------------------------------------===//
4958 //===---------------------------------------------------------------------===//
4959 // Move Int Doubleword to Packed Double Int
4961 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4962 "movd\t{$src, $dst|$dst, $src}",
4964 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4965 VEX, Sched<[WriteMove]>;
4966 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4967 "movd\t{$src, $dst|$dst, $src}",
4969 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4971 VEX, Sched<[WriteLoad]>;
4972 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4973 "movq\t{$src, $dst|$dst, $src}",
4975 (v2i64 (scalar_to_vector GR64:$src)))],
4976 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4977 let isCodeGenOnly = 1 in
4978 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4979 "movq\t{$src, $dst|$dst, $src}",
4980 [(set FR64:$dst, (bitconvert GR64:$src))],
4981 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4983 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4984 "movd\t{$src, $dst|$dst, $src}",
4986 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4988 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4989 "movd\t{$src, $dst|$dst, $src}",
4991 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4992 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4993 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4994 "mov{d|q}\t{$src, $dst|$dst, $src}",
4996 (v2i64 (scalar_to_vector GR64:$src)))],
4997 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4998 let isCodeGenOnly = 1 in
4999 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
5000 "mov{d|q}\t{$src, $dst|$dst, $src}",
5001 [(set FR64:$dst, (bitconvert GR64:$src))],
5002 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
5004 //===---------------------------------------------------------------------===//
5005 // Move Int Doubleword to Single Scalar
5007 let isCodeGenOnly = 1 in {
5008 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
5009 "movd\t{$src, $dst|$dst, $src}",
5010 [(set FR32:$dst, (bitconvert GR32:$src))],
5011 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
5013 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
5014 "movd\t{$src, $dst|$dst, $src}",
5015 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
5017 VEX, Sched<[WriteLoad]>;
5018 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
5019 "movd\t{$src, $dst|$dst, $src}",
5020 [(set FR32:$dst, (bitconvert GR32:$src))],
5021 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
5023 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
5024 "movd\t{$src, $dst|$dst, $src}",
5025 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
5026 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5029 //===---------------------------------------------------------------------===//
5030 // Move Packed Doubleword Int to Packed Double Int
5032 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5033 "movd\t{$src, $dst|$dst, $src}",
5034 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5035 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
5037 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
5038 (ins i32mem:$dst, VR128:$src),
5039 "movd\t{$src, $dst|$dst, $src}",
5040 [(store (i32 (vector_extract (v4i32 VR128:$src),
5041 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
5042 VEX, Sched<[WriteStore]>;
5043 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5044 "movd\t{$src, $dst|$dst, $src}",
5045 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5046 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
5048 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
5049 "movd\t{$src, $dst|$dst, $src}",
5050 [(store (i32 (vector_extract (v4i32 VR128:$src),
5051 (iPTR 0))), addr:$dst)],
5052 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5054 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
5055 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5057 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
5058 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5060 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
5061 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5063 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
5064 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5066 //===---------------------------------------------------------------------===//
5067 // Move Packed Doubleword Int first element to Doubleword Int
5069 let SchedRW = [WriteMove] in {
5070 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5071 "movq\t{$src, $dst|$dst, $src}",
5072 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5077 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5078 "mov{d|q}\t{$src, $dst|$dst, $src}",
5079 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5084 //===---------------------------------------------------------------------===//
5085 // Bitcast FR64 <-> GR64
5087 let isCodeGenOnly = 1 in {
5088 let Predicates = [UseAVX] in
5089 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5090 "movq\t{$src, $dst|$dst, $src}",
5091 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
5092 VEX, Sched<[WriteLoad]>;
5093 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5094 "movq\t{$src, $dst|$dst, $src}",
5095 [(set GR64:$dst, (bitconvert FR64:$src))],
5096 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
5097 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5098 "movq\t{$src, $dst|$dst, $src}",
5099 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5100 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5102 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5103 "movq\t{$src, $dst|$dst, $src}",
5104 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
5105 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5106 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5107 "mov{d|q}\t{$src, $dst|$dst, $src}",
5108 [(set GR64:$dst, (bitconvert FR64:$src))],
5109 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5110 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5111 "movq\t{$src, $dst|$dst, $src}",
5112 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5113 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5116 //===---------------------------------------------------------------------===//
5117 // Move Scalar Single to Double Int
5119 let isCodeGenOnly = 1 in {
5120 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5121 "movd\t{$src, $dst|$dst, $src}",
5122 [(set GR32:$dst, (bitconvert FR32:$src))],
5123 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
5124 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5125 "movd\t{$src, $dst|$dst, $src}",
5126 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5127 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5128 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5129 "movd\t{$src, $dst|$dst, $src}",
5130 [(set GR32:$dst, (bitconvert FR32:$src))],
5131 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5132 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5133 "movd\t{$src, $dst|$dst, $src}",
5134 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5135 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5138 //===---------------------------------------------------------------------===//
5139 // Patterns and instructions to describe movd/movq to XMM register zero-extends
5141 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
5142 let AddedComplexity = 15 in {
5143 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5144 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
5145 [(set VR128:$dst, (v2i64 (X86vzmovl
5146 (v2i64 (scalar_to_vector GR64:$src)))))],
5149 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5150 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
5151 [(set VR128:$dst, (v2i64 (X86vzmovl
5152 (v2i64 (scalar_to_vector GR64:$src)))))],
5155 } // isCodeGenOnly, SchedRW
5157 let Predicates = [UseAVX] in {
5158 let AddedComplexity = 15 in
5159 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5160 (VMOVDI2PDIrr GR32:$src)>;
5162 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
5163 let AddedComplexity = 20 in {
5164 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5165 (VMOVDI2PDIrm addr:$src)>;
5166 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5167 (VMOVDI2PDIrm addr:$src)>;
5168 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5169 (VMOVDI2PDIrm addr:$src)>;
5171 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
5172 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
5173 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
5174 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
5175 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5176 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
5177 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
5180 let Predicates = [UseSSE2] in {
5181 let AddedComplexity = 15 in
5182 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5183 (MOVDI2PDIrr GR32:$src)>;
5185 let AddedComplexity = 20 in {
5186 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5187 (MOVDI2PDIrm addr:$src)>;
5188 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5189 (MOVDI2PDIrm addr:$src)>;
5190 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5191 (MOVDI2PDIrm addr:$src)>;
5195 // These are the correct encodings of the instructions so that we know how to
5196 // read correct assembly, even though we continue to emit the wrong ones for
5197 // compatibility with Darwin's buggy assembler.
5198 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5199 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5200 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5201 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5202 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
5203 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5204 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5205 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5206 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5208 //===---------------------------------------------------------------------===//
5209 // SSE2 - Move Quadword
5210 //===---------------------------------------------------------------------===//
5212 //===---------------------------------------------------------------------===//
5213 // Move Quadword Int to Packed Quadword Int
5216 let SchedRW = [WriteLoad] in {
5217 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5218 "vmovq\t{$src, $dst|$dst, $src}",
5220 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
5221 VEX, Requires<[UseAVX]>;
5222 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5223 "movq\t{$src, $dst|$dst, $src}",
5225 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
5227 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
5230 //===---------------------------------------------------------------------===//
5231 // Move Packed Quadword Int to Quadword Int
5233 let SchedRW = [WriteStore] in {
5234 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5235 "movq\t{$src, $dst|$dst, $src}",
5236 [(store (i64 (vector_extract (v2i64 VR128:$src),
5237 (iPTR 0))), addr:$dst)],
5238 IIC_SSE_MOVDQ>, VEX;
5239 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5240 "movq\t{$src, $dst|$dst, $src}",
5241 [(store (i64 (vector_extract (v2i64 VR128:$src),
5242 (iPTR 0))), addr:$dst)],
5246 // For disassembler only
5247 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5248 SchedRW = [WriteVecLogic] in {
5249 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5250 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5251 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5252 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5255 //===---------------------------------------------------------------------===//
5256 // Store / copy lower 64-bits of a XMM register.
5258 let Predicates = [UseAVX] in
5259 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5260 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5261 let Predicates = [UseSSE2] in
5262 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5263 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5265 let isCodeGenOnly = 1, AddedComplexity = 20 in {
5266 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5267 "vmovq\t{$src, $dst|$dst, $src}",
5269 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5270 (loadi64 addr:$src))))))],
5272 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5274 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5275 "movq\t{$src, $dst|$dst, $src}",
5277 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5278 (loadi64 addr:$src))))))],
5280 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5283 let Predicates = [UseAVX], AddedComplexity = 20 in {
5284 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5285 (VMOVZQI2PQIrm addr:$src)>;
5286 def : Pat<(v2i64 (X86vzload addr:$src)),
5287 (VMOVZQI2PQIrm addr:$src)>;
5290 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5291 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5292 (MOVZQI2PQIrm addr:$src)>;
5293 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5296 let Predicates = [HasAVX] in {
5297 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5298 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5299 def : Pat<(v4i64 (X86vzload addr:$src)),
5300 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5303 //===---------------------------------------------------------------------===//
5304 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5305 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5307 let SchedRW = [WriteVecLogic] in {
5308 let AddedComplexity = 15 in
5309 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5310 "vmovq\t{$src, $dst|$dst, $src}",
5311 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5313 XS, VEX, Requires<[UseAVX]>;
5314 let AddedComplexity = 15 in
5315 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5316 "movq\t{$src, $dst|$dst, $src}",
5317 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5319 XS, Requires<[UseSSE2]>;
5322 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5323 let AddedComplexity = 20 in
5324 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5325 "vmovq\t{$src, $dst|$dst, $src}",
5326 [(set VR128:$dst, (v2i64 (X86vzmovl
5327 (loadv2i64 addr:$src))))],
5329 XS, VEX, Requires<[UseAVX]>;
5330 let AddedComplexity = 20 in {
5331 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5332 "movq\t{$src, $dst|$dst, $src}",
5333 [(set VR128:$dst, (v2i64 (X86vzmovl
5334 (loadv2i64 addr:$src))))],
5336 XS, Requires<[UseSSE2]>;
5338 } // isCodeGenOnly, SchedRW
5340 let AddedComplexity = 20 in {
5341 let Predicates = [UseAVX] in {
5342 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5343 (VMOVZPQILo2PQIrr VR128:$src)>;
5345 let Predicates = [UseSSE2] in {
5346 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5347 (MOVZPQILo2PQIrr VR128:$src)>;
5351 //===---------------------------------------------------------------------===//
5352 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5353 //===---------------------------------------------------------------------===//
5354 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5355 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5356 X86MemOperand x86memop> {
5357 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5358 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5359 [(set RC:$dst, (vt (OpNode RC:$src)))],
5360 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5361 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5362 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5363 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5364 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5367 let Predicates = [HasAVX] in {
5368 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5369 v4f32, VR128, loadv4f32, f128mem>, VEX;
5370 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5371 v4f32, VR128, loadv4f32, f128mem>, VEX;
5372 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5373 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5374 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5375 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5377 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5378 memopv4f32, f128mem>;
5379 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5380 memopv4f32, f128mem>;
5382 let Predicates = [HasAVX] in {
5383 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5384 (VMOVSHDUPrr VR128:$src)>;
5385 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5386 (VMOVSHDUPrm addr:$src)>;
5387 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5388 (VMOVSLDUPrr VR128:$src)>;
5389 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5390 (VMOVSLDUPrm addr:$src)>;
5391 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5392 (VMOVSHDUPYrr VR256:$src)>;
5393 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5394 (VMOVSHDUPYrm addr:$src)>;
5395 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5396 (VMOVSLDUPYrr VR256:$src)>;
5397 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5398 (VMOVSLDUPYrm addr:$src)>;
5401 let Predicates = [UseSSE3] in {
5402 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5403 (MOVSHDUPrr VR128:$src)>;
5404 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5405 (MOVSHDUPrm addr:$src)>;
5406 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5407 (MOVSLDUPrr VR128:$src)>;
5408 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5409 (MOVSLDUPrm addr:$src)>;
5412 //===---------------------------------------------------------------------===//
5413 // SSE3 - Replicate Double FP - MOVDDUP
5414 //===---------------------------------------------------------------------===//
5416 multiclass sse3_replicate_dfp<string OpcodeStr> {
5417 let hasSideEffects = 0 in
5418 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5419 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5420 [], IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5421 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5422 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5425 (scalar_to_vector (loadf64 addr:$src)))))],
5426 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5429 // FIXME: Merge with above classe when there're patterns for the ymm version
5430 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5431 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5432 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5433 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5434 Sched<[WriteFShuffle]>;
5435 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5436 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5439 (scalar_to_vector (loadf64 addr:$src)))))]>,
5443 let Predicates = [HasAVX] in {
5444 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5445 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5448 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5450 let Predicates = [HasAVX] in {
5451 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5452 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5453 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5454 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5455 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5456 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5457 def : Pat<(X86Movddup (bc_v2f64
5458 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5459 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5462 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5463 (VMOVDDUPYrm addr:$src)>;
5464 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5465 (VMOVDDUPYrm addr:$src)>;
5466 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5467 (VMOVDDUPYrm addr:$src)>;
5468 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5469 (VMOVDDUPYrr VR256:$src)>;
5472 let Predicates = [UseAVX, OptForSize] in {
5473 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5474 (VMOVDDUPrm addr:$src)>;
5475 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5476 (VMOVDDUPrm addr:$src)>;
5479 let Predicates = [UseSSE3] in {
5480 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5481 (MOVDDUPrm addr:$src)>;
5482 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5483 (MOVDDUPrm addr:$src)>;
5484 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5485 (MOVDDUPrm addr:$src)>;
5486 def : Pat<(X86Movddup (bc_v2f64
5487 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5488 (MOVDDUPrm addr:$src)>;
5491 //===---------------------------------------------------------------------===//
5492 // SSE3 - Move Unaligned Integer
5493 //===---------------------------------------------------------------------===//
5495 let SchedRW = [WriteLoad] in {
5496 let Predicates = [HasAVX] in {
5497 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5498 "vlddqu\t{$src, $dst|$dst, $src}",
5499 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5500 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5501 "vlddqu\t{$src, $dst|$dst, $src}",
5502 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5505 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5506 "lddqu\t{$src, $dst|$dst, $src}",
5507 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5511 //===---------------------------------------------------------------------===//
5512 // SSE3 - Arithmetic
5513 //===---------------------------------------------------------------------===//
5515 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5516 X86MemOperand x86memop, OpndItins itins,
5518 def rr : I<0xD0, MRMSrcReg,
5519 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5521 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5522 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5523 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5524 Sched<[itins.Sched]>;
5525 def rm : I<0xD0, MRMSrcMem,
5526 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5528 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5529 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5530 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5531 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5534 let Predicates = [HasAVX] in {
5535 let ExeDomain = SSEPackedSingle in {
5536 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5537 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5538 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5539 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5541 let ExeDomain = SSEPackedDouble in {
5542 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5543 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5544 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5545 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5548 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5549 let ExeDomain = SSEPackedSingle in
5550 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5551 f128mem, SSE_ALU_F32P>, XD;
5552 let ExeDomain = SSEPackedDouble in
5553 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5554 f128mem, SSE_ALU_F64P>, PD;
5557 // Patterns used to select 'addsub' instructions.
5558 let Predicates = [HasAVX] in {
5559 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5560 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5561 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5562 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5563 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5564 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5565 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5566 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5568 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5569 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5570 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 (memop addr:$rhs)))),
5571 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5572 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5573 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5574 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 (memop addr:$rhs)))),
5575 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5578 let Predicates = [UseSSE3] in {
5579 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5580 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5581 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5582 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5583 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5584 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5585 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5586 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5589 //===---------------------------------------------------------------------===//
5590 // SSE3 Instructions
5591 //===---------------------------------------------------------------------===//
5594 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5595 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5596 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5598 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5599 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5600 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5603 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5605 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5606 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5607 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5608 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5610 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5611 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5612 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5614 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5615 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5616 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5619 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5621 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5622 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5623 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5624 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5627 let Predicates = [HasAVX] in {
5628 let ExeDomain = SSEPackedSingle in {
5629 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5630 X86fhadd, 0>, VEX_4V;
5631 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5632 X86fhsub, 0>, VEX_4V;
5633 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5634 X86fhadd, 0>, VEX_4V, VEX_L;
5635 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5636 X86fhsub, 0>, VEX_4V, VEX_L;
5638 let ExeDomain = SSEPackedDouble in {
5639 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5640 X86fhadd, 0>, VEX_4V;
5641 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5642 X86fhsub, 0>, VEX_4V;
5643 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5644 X86fhadd, 0>, VEX_4V, VEX_L;
5645 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5646 X86fhsub, 0>, VEX_4V, VEX_L;
5650 let Constraints = "$src1 = $dst" in {
5651 let ExeDomain = SSEPackedSingle in {
5652 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5653 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5655 let ExeDomain = SSEPackedDouble in {
5656 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5657 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5661 //===---------------------------------------------------------------------===//
5662 // SSSE3 - Packed Absolute Instructions
5663 //===---------------------------------------------------------------------===//
5666 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5667 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5668 Intrinsic IntId128> {
5669 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5671 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5672 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5673 Sched<[WriteVecALU]>;
5675 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5677 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5680 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5681 Sched<[WriteVecALULd]>;
5684 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5685 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5686 Intrinsic IntId256> {
5687 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5689 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5690 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5691 Sched<[WriteVecALU]>;
5693 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5695 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5698 (bitconvert (memopv4i64 addr:$src))))]>,
5699 Sched<[WriteVecALULd]>;
5702 // Helper fragments to match sext vXi1 to vXiY.
5703 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5705 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5706 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5707 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5709 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5710 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5712 let Predicates = [HasAVX] in {
5713 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5714 int_x86_ssse3_pabs_b_128>, VEX;
5715 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5716 int_x86_ssse3_pabs_w_128>, VEX;
5717 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5718 int_x86_ssse3_pabs_d_128>, VEX;
5721 (bc_v2i64 (v16i1sextv16i8)),
5722 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5723 (VPABSBrr128 VR128:$src)>;
5725 (bc_v2i64 (v8i1sextv8i16)),
5726 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5727 (VPABSWrr128 VR128:$src)>;
5729 (bc_v2i64 (v4i1sextv4i32)),
5730 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5731 (VPABSDrr128 VR128:$src)>;
5734 let Predicates = [HasAVX2] in {
5735 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5736 int_x86_avx2_pabs_b>, VEX, VEX_L;
5737 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5738 int_x86_avx2_pabs_w>, VEX, VEX_L;
5739 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5740 int_x86_avx2_pabs_d>, VEX, VEX_L;
5743 (bc_v4i64 (v32i1sextv32i8)),
5744 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5745 (VPABSBrr256 VR256:$src)>;
5747 (bc_v4i64 (v16i1sextv16i16)),
5748 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5749 (VPABSWrr256 VR256:$src)>;
5751 (bc_v4i64 (v8i1sextv8i32)),
5752 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5753 (VPABSDrr256 VR256:$src)>;
5756 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5757 int_x86_ssse3_pabs_b_128>;
5758 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5759 int_x86_ssse3_pabs_w_128>;
5760 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5761 int_x86_ssse3_pabs_d_128>;
5763 let Predicates = [HasSSSE3] in {
5765 (bc_v2i64 (v16i1sextv16i8)),
5766 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5767 (PABSBrr128 VR128:$src)>;
5769 (bc_v2i64 (v8i1sextv8i16)),
5770 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5771 (PABSWrr128 VR128:$src)>;
5773 (bc_v2i64 (v4i1sextv4i32)),
5774 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5775 (PABSDrr128 VR128:$src)>;
5778 //===---------------------------------------------------------------------===//
5779 // SSSE3 - Packed Binary Operator Instructions
5780 //===---------------------------------------------------------------------===//
5782 let Sched = WriteVecALU in {
5783 def SSE_PHADDSUBD : OpndItins<
5784 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5786 def SSE_PHADDSUBSW : OpndItins<
5787 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5789 def SSE_PHADDSUBW : OpndItins<
5790 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5793 let Sched = WriteShuffle in
5794 def SSE_PSHUFB : OpndItins<
5795 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5797 let Sched = WriteVecALU in
5798 def SSE_PSIGN : OpndItins<
5799 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5801 let Sched = WriteVecIMul in
5802 def SSE_PMULHRSW : OpndItins<
5803 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5806 /// SS3I_binop_rm - Simple SSSE3 bin op
5807 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5808 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5809 X86MemOperand x86memop, OpndItins itins,
5811 let isCommutable = 1 in
5812 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5813 (ins RC:$src1, RC:$src2),
5815 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5816 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5817 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5818 Sched<[itins.Sched]>;
5819 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5820 (ins RC:$src1, x86memop:$src2),
5822 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5823 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5825 (OpVT (OpNode RC:$src1,
5826 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5827 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5830 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5831 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5832 Intrinsic IntId128, OpndItins itins,
5834 let isCommutable = 1 in
5835 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5836 (ins VR128:$src1, VR128:$src2),
5838 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5839 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5840 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5841 Sched<[itins.Sched]>;
5842 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5843 (ins VR128:$src1, i128mem:$src2),
5845 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5848 (IntId128 VR128:$src1,
5849 (bitconvert (memopv2i64 addr:$src2))))]>,
5850 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5853 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5855 X86FoldableSchedWrite Sched> {
5856 let isCommutable = 1 in
5857 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5858 (ins VR256:$src1, VR256:$src2),
5859 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5860 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5862 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5863 (ins VR256:$src1, i256mem:$src2),
5864 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5866 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5867 Sched<[Sched.Folded, ReadAfterLd]>;
5870 let ImmT = NoImm, Predicates = [HasAVX] in {
5871 let isCommutable = 0 in {
5872 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5874 SSE_PHADDSUBW, 0>, VEX_4V;
5875 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5877 SSE_PHADDSUBD, 0>, VEX_4V;
5878 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5880 SSE_PHADDSUBW, 0>, VEX_4V;
5881 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5883 SSE_PHADDSUBD, 0>, VEX_4V;
5884 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5886 SSE_PSIGN, 0>, VEX_4V;
5887 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5889 SSE_PSIGN, 0>, VEX_4V;
5890 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5892 SSE_PSIGN, 0>, VEX_4V;
5893 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5895 SSE_PSHUFB, 0>, VEX_4V;
5896 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5897 int_x86_ssse3_phadd_sw_128,
5898 SSE_PHADDSUBSW, 0>, VEX_4V;
5899 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5900 int_x86_ssse3_phsub_sw_128,
5901 SSE_PHADDSUBSW, 0>, VEX_4V;
5902 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5903 int_x86_ssse3_pmadd_ub_sw_128,
5904 SSE_PMADD, 0>, VEX_4V;
5906 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5907 int_x86_ssse3_pmul_hr_sw_128,
5908 SSE_PMULHRSW, 0>, VEX_4V;
5911 let ImmT = NoImm, Predicates = [HasAVX2] in {
5912 let isCommutable = 0 in {
5913 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5915 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5916 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5918 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5919 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5921 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5922 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5924 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5925 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5927 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5928 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5930 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5931 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5933 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5934 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5936 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5937 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5938 int_x86_avx2_phadd_sw,
5939 WriteVecALU>, VEX_4V, VEX_L;
5940 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5941 int_x86_avx2_phsub_sw,
5942 WriteVecALU>, VEX_4V, VEX_L;
5943 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5944 int_x86_avx2_pmadd_ub_sw,
5945 WriteVecIMul>, VEX_4V, VEX_L;
5947 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5948 int_x86_avx2_pmul_hr_sw,
5949 WriteVecIMul>, VEX_4V, VEX_L;
5952 // None of these have i8 immediate fields.
5953 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5954 let isCommutable = 0 in {
5955 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5956 memopv2i64, i128mem, SSE_PHADDSUBW>;
5957 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5958 memopv2i64, i128mem, SSE_PHADDSUBD>;
5959 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5960 memopv2i64, i128mem, SSE_PHADDSUBW>;
5961 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5962 memopv2i64, i128mem, SSE_PHADDSUBD>;
5963 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5964 memopv2i64, i128mem, SSE_PSIGN>;
5965 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5966 memopv2i64, i128mem, SSE_PSIGN>;
5967 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5968 memopv2i64, i128mem, SSE_PSIGN>;
5969 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5970 memopv2i64, i128mem, SSE_PSHUFB>;
5971 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5972 int_x86_ssse3_phadd_sw_128,
5974 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5975 int_x86_ssse3_phsub_sw_128,
5977 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5978 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5980 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5981 int_x86_ssse3_pmul_hr_sw_128,
5985 //===---------------------------------------------------------------------===//
5986 // SSSE3 - Packed Align Instruction Patterns
5987 //===---------------------------------------------------------------------===//
5989 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5990 let hasSideEffects = 0 in {
5991 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5992 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5994 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5996 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5997 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5999 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
6000 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6002 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6004 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6005 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6009 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
6010 let hasSideEffects = 0 in {
6011 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
6012 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6014 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6015 []>, Sched<[WriteShuffle]>;
6017 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
6018 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
6020 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6021 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6025 let Predicates = [HasAVX] in
6026 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
6027 let Predicates = [HasAVX2] in
6028 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
6029 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
6030 defm PALIGN : ssse3_palignr<"palignr">;
6032 let Predicates = [HasAVX2] in {
6033 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6034 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6035 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6036 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6037 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6038 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6039 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6040 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6043 let Predicates = [HasAVX] in {
6044 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6045 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6046 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6047 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6048 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6049 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6050 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6051 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6054 let Predicates = [UseSSSE3] in {
6055 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6056 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6057 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6058 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6059 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6060 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6061 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6062 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6065 //===---------------------------------------------------------------------===//
6066 // SSSE3 - Thread synchronization
6067 //===---------------------------------------------------------------------===//
6069 let SchedRW = [WriteSystem] in {
6070 let usesCustomInserter = 1 in {
6071 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
6072 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
6073 Requires<[HasSSE3]>;
6076 let Uses = [EAX, ECX, EDX] in
6077 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
6078 TB, Requires<[HasSSE3]>;
6079 let Uses = [ECX, EAX] in
6080 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
6081 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
6082 TB, Requires<[HasSSE3]>;
6085 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
6086 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
6088 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
6089 Requires<[Not64BitMode]>;
6090 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
6091 Requires<[In64BitMode]>;
6093 //===----------------------------------------------------------------------===//
6094 // SSE4.1 - Packed Move with Sign/Zero Extend
6095 //===----------------------------------------------------------------------===//
6097 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6098 OpndItins itins = DEFAULT_ITINS> {
6099 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6100 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6101 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>,
6102 Sched<[itins.Sched]>;
6104 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
6105 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6107 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
6108 itins.rm>, Sched<[itins.Sched.Folded]>;
6111 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
6112 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6113 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6115 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6117 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
6118 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6119 [(set VR256:$dst, (IntId (load addr:$src)))]>,
6120 Sched<[Sched.Folded]>;
6123 let Predicates = [HasAVX] in {
6124 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
6125 int_x86_sse41_pmovsxbw,
6126 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6127 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
6128 int_x86_sse41_pmovsxwd,
6129 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6130 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
6131 int_x86_sse41_pmovsxdq,
6132 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6133 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
6134 int_x86_sse41_pmovzxbw,
6135 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6136 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
6137 int_x86_sse41_pmovzxwd,
6138 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6139 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
6140 int_x86_sse41_pmovzxdq,
6141 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6144 let Predicates = [HasAVX2] in {
6145 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
6146 int_x86_avx2_pmovsxbw,
6147 WriteShuffle>, VEX, VEX_L;
6148 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
6149 int_x86_avx2_pmovsxwd,
6150 WriteShuffle>, VEX, VEX_L;
6151 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
6152 int_x86_avx2_pmovsxdq,
6153 WriteShuffle>, VEX, VEX_L;
6154 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
6155 int_x86_avx2_pmovzxbw,
6156 WriteShuffle>, VEX, VEX_L;
6157 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
6158 int_x86_avx2_pmovzxwd,
6159 WriteShuffle>, VEX, VEX_L;
6160 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
6161 int_x86_avx2_pmovzxdq,
6162 WriteShuffle>, VEX, VEX_L;
6165 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw,
6166 SSE_INTALU_ITINS_SHUFF_P>;
6167 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd,
6168 SSE_INTALU_ITINS_SHUFF_P>;
6169 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq,
6170 SSE_INTALU_ITINS_SHUFF_P>;
6171 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw,
6172 SSE_INTALU_ITINS_SHUFF_P>;
6173 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd,
6174 SSE_INTALU_ITINS_SHUFF_P>;
6175 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq,
6176 SSE_INTALU_ITINS_SHUFF_P>;
6178 let Predicates = [HasAVX] in {
6179 // Common patterns involving scalar load.
6180 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
6181 (VPMOVSXBWrm addr:$src)>;
6182 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
6183 (VPMOVSXBWrm addr:$src)>;
6184 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
6185 (VPMOVSXBWrm addr:$src)>;
6187 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
6188 (VPMOVSXWDrm addr:$src)>;
6189 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
6190 (VPMOVSXWDrm addr:$src)>;
6191 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
6192 (VPMOVSXWDrm addr:$src)>;
6194 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
6195 (VPMOVSXDQrm addr:$src)>;
6196 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
6197 (VPMOVSXDQrm addr:$src)>;
6198 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
6199 (VPMOVSXDQrm addr:$src)>;
6201 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
6202 (VPMOVZXBWrm addr:$src)>;
6203 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
6204 (VPMOVZXBWrm addr:$src)>;
6205 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
6206 (VPMOVZXBWrm addr:$src)>;
6208 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
6209 (VPMOVZXWDrm addr:$src)>;
6210 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
6211 (VPMOVZXWDrm addr:$src)>;
6212 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
6213 (VPMOVZXWDrm addr:$src)>;
6215 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
6216 (VPMOVZXDQrm addr:$src)>;
6217 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
6218 (VPMOVZXDQrm addr:$src)>;
6219 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
6220 (VPMOVZXDQrm addr:$src)>;
6223 let Predicates = [UseSSE41] in {
6224 // Common patterns involving scalar load.
6225 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
6226 (PMOVSXBWrm addr:$src)>;
6227 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
6228 (PMOVSXBWrm addr:$src)>;
6229 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
6230 (PMOVSXBWrm addr:$src)>;
6232 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
6233 (PMOVSXWDrm addr:$src)>;
6234 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
6235 (PMOVSXWDrm addr:$src)>;
6236 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
6237 (PMOVSXWDrm addr:$src)>;
6239 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
6240 (PMOVSXDQrm addr:$src)>;
6241 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
6242 (PMOVSXDQrm addr:$src)>;
6243 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
6244 (PMOVSXDQrm addr:$src)>;
6246 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
6247 (PMOVZXBWrm addr:$src)>;
6248 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
6249 (PMOVZXBWrm addr:$src)>;
6250 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
6251 (PMOVZXBWrm addr:$src)>;
6253 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
6254 (PMOVZXWDrm addr:$src)>;
6255 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
6256 (PMOVZXWDrm addr:$src)>;
6257 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
6258 (PMOVZXWDrm addr:$src)>;
6260 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
6261 (PMOVZXDQrm addr:$src)>;
6262 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
6263 (PMOVZXDQrm addr:$src)>;
6264 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
6265 (PMOVZXDQrm addr:$src)>;
6268 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6269 OpndItins itins = DEFAULT_ITINS> {
6270 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6271 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6272 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>,
6273 Sched<[itins.Sched]>;
6275 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
6276 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6278 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
6279 itins.rm>, Sched<[itins.Sched.Folded]>;
6282 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
6283 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6284 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6285 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6286 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6288 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
6289 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6291 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
6292 Sched<[Sched.Folded]>;
6295 let Predicates = [HasAVX] in {
6296 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd,
6297 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6298 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq,
6299 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6300 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd,
6301 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6302 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq,
6303 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6306 let Predicates = [HasAVX2] in {
6307 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
6308 int_x86_avx2_pmovsxbd, WriteShuffle>,
6310 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
6311 int_x86_avx2_pmovsxwq, WriteShuffle>,
6313 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
6314 int_x86_avx2_pmovzxbd, WriteShuffle>,
6316 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
6317 int_x86_avx2_pmovzxwq, WriteShuffle>,
6321 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
6322 SSE_INTALU_ITINS_SHUFF_P>;
6323 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
6324 SSE_INTALU_ITINS_SHUFF_P>;
6325 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
6326 SSE_INTALU_ITINS_SHUFF_P>;
6327 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
6328 SSE_INTALU_ITINS_SHUFF_P>;
6330 let Predicates = [HasAVX] in {
6331 // Common patterns involving scalar load
6332 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
6333 (VPMOVSXBDrm addr:$src)>;
6334 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
6335 (VPMOVSXWQrm addr:$src)>;
6337 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
6338 (VPMOVZXBDrm addr:$src)>;
6339 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
6340 (VPMOVZXWQrm addr:$src)>;
6343 let Predicates = [UseSSE41] in {
6344 // Common patterns involving scalar load
6345 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
6346 (PMOVSXBDrm addr:$src)>;
6347 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
6348 (PMOVSXWQrm addr:$src)>;
6350 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
6351 (PMOVZXBDrm addr:$src)>;
6352 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
6353 (PMOVZXWQrm addr:$src)>;
6356 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6357 X86FoldableSchedWrite Sched> {
6358 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6359 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6360 [(set VR128:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6362 // Expecting a i16 load any extended to i32 value.
6363 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
6364 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6365 [(set VR128:$dst, (IntId (bitconvert
6366 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
6367 Sched<[Sched.Folded]>;
6370 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
6371 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6372 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6373 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6374 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6376 // Expecting a i16 load any extended to i32 value.
6377 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
6378 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6379 [(set VR256:$dst, (IntId (bitconvert
6380 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
6381 Sched<[Sched.Folded]>;
6384 let Predicates = [HasAVX] in {
6385 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq,
6387 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq,
6390 let Predicates = [HasAVX2] in {
6391 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq", int_x86_avx2_pmovsxbq,
6392 WriteShuffle>, VEX, VEX_L;
6393 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq", int_x86_avx2_pmovzxbq,
6394 WriteShuffle>, VEX, VEX_L;
6396 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
6398 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
6401 let Predicates = [HasAVX2] in {
6402 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
6403 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
6404 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
6406 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
6407 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
6409 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
6411 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
6412 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6413 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
6414 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6415 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
6416 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6418 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
6419 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6420 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
6421 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6423 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
6424 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6426 def : Pat<(v8i32 (X86vsext (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
6427 (VPMOVSXWDYrm addr:$src)>;
6428 def : Pat<(v4i64 (X86vsext (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
6429 (VPMOVSXDQYrm addr:$src)>;
6431 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
6432 (scalar_to_vector (loadi64 addr:$src))))))),
6433 (VPMOVSXBDYrm addr:$src)>;
6434 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
6435 (scalar_to_vector (loadf64 addr:$src))))))),
6436 (VPMOVSXBDYrm addr:$src)>;
6438 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
6439 (scalar_to_vector (loadi64 addr:$src))))))),
6440 (VPMOVSXWQYrm addr:$src)>;
6441 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
6442 (scalar_to_vector (loadf64 addr:$src))))))),
6443 (VPMOVSXWQYrm addr:$src)>;
6445 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
6446 (scalar_to_vector (loadi32 addr:$src))))))),
6447 (VPMOVSXBQYrm addr:$src)>;
6450 let Predicates = [HasAVX] in {
6451 // Common patterns involving scalar load
6452 def : Pat<(int_x86_sse41_pmovsxbq
6453 (bitconvert (v4i32 (X86vzmovl
6454 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6455 (VPMOVSXBQrm addr:$src)>;
6457 def : Pat<(int_x86_sse41_pmovzxbq
6458 (bitconvert (v4i32 (X86vzmovl
6459 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6460 (VPMOVZXBQrm addr:$src)>;
6463 let Predicates = [UseSSE41] in {
6464 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
6465 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
6466 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
6468 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
6469 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
6471 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
6473 // Common patterns involving scalar load
6474 def : Pat<(int_x86_sse41_pmovsxbq
6475 (bitconvert (v4i32 (X86vzmovl
6476 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6477 (PMOVSXBQrm addr:$src)>;
6479 def : Pat<(int_x86_sse41_pmovzxbq
6480 (bitconvert (v4i32 (X86vzmovl
6481 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6482 (PMOVZXBQrm addr:$src)>;
6484 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6485 (scalar_to_vector (loadi64 addr:$src))))))),
6486 (PMOVSXWDrm addr:$src)>;
6487 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6488 (scalar_to_vector (loadf64 addr:$src))))))),
6489 (PMOVSXWDrm addr:$src)>;
6490 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6491 (scalar_to_vector (loadi32 addr:$src))))))),
6492 (PMOVSXBDrm addr:$src)>;
6493 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6494 (scalar_to_vector (loadi32 addr:$src))))))),
6495 (PMOVSXWQrm addr:$src)>;
6496 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6497 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6498 (PMOVSXBQrm addr:$src)>;
6499 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6500 (scalar_to_vector (loadi64 addr:$src))))))),
6501 (PMOVSXDQrm addr:$src)>;
6502 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6503 (scalar_to_vector (loadf64 addr:$src))))))),
6504 (PMOVSXDQrm addr:$src)>;
6505 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6506 (scalar_to_vector (loadi64 addr:$src))))))),
6507 (PMOVSXBWrm addr:$src)>;
6508 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6509 (scalar_to_vector (loadf64 addr:$src))))))),
6510 (PMOVSXBWrm addr:$src)>;
6513 let Predicates = [HasAVX2] in {
6514 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
6515 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
6516 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
6518 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
6519 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
6521 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
6523 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
6524 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6525 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
6526 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6527 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
6528 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6530 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
6531 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6532 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
6533 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6535 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
6536 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6539 let Predicates = [HasAVX] in {
6540 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
6541 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
6542 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
6544 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
6545 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
6547 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
6549 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6550 (VPMOVZXBWrm addr:$src)>;
6551 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6552 (VPMOVZXBWrm addr:$src)>;
6553 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6554 (VPMOVZXBDrm addr:$src)>;
6555 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6556 (VPMOVZXBQrm addr:$src)>;
6558 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6559 (VPMOVZXWDrm addr:$src)>;
6560 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6561 (VPMOVZXWDrm addr:$src)>;
6562 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6563 (VPMOVZXWQrm addr:$src)>;
6565 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6566 (VPMOVZXDQrm addr:$src)>;
6567 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6568 (VPMOVZXDQrm addr:$src)>;
6569 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6570 (VPMOVZXDQrm addr:$src)>;
6572 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
6573 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
6574 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
6576 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
6577 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
6579 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
6581 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6582 (scalar_to_vector (loadi64 addr:$src))))))),
6583 (VPMOVSXWDrm addr:$src)>;
6584 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6585 (scalar_to_vector (loadi64 addr:$src))))))),
6586 (VPMOVSXDQrm addr:$src)>;
6587 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6588 (scalar_to_vector (loadf64 addr:$src))))))),
6589 (VPMOVSXWDrm addr:$src)>;
6590 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6591 (scalar_to_vector (loadf64 addr:$src))))))),
6592 (VPMOVSXDQrm addr:$src)>;
6593 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6594 (scalar_to_vector (loadi64 addr:$src))))))),
6595 (VPMOVSXBWrm addr:$src)>;
6596 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6597 (scalar_to_vector (loadf64 addr:$src))))))),
6598 (VPMOVSXBWrm addr:$src)>;
6600 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6601 (scalar_to_vector (loadi32 addr:$src))))))),
6602 (VPMOVSXBDrm addr:$src)>;
6603 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6604 (scalar_to_vector (loadi32 addr:$src))))))),
6605 (VPMOVSXWQrm addr:$src)>;
6606 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6607 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6608 (VPMOVSXBQrm addr:$src)>;
6611 let Predicates = [UseSSE41] in {
6612 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6613 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6614 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6616 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6617 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6619 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6621 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6622 (PMOVZXBWrm addr:$src)>;
6623 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6624 (PMOVZXBWrm addr:$src)>;
6625 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6626 (PMOVZXBDrm addr:$src)>;
6627 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6628 (PMOVZXBQrm addr:$src)>;
6630 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6631 (PMOVZXWDrm addr:$src)>;
6632 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6633 (PMOVZXWDrm addr:$src)>;
6634 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6635 (PMOVZXWQrm addr:$src)>;
6637 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6638 (PMOVZXDQrm addr:$src)>;
6639 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6640 (PMOVZXDQrm addr:$src)>;
6641 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6642 (PMOVZXDQrm addr:$src)>;
6645 //===----------------------------------------------------------------------===//
6646 // SSE4.1 - Extract Instructions
6647 //===----------------------------------------------------------------------===//
6649 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6650 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6651 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6652 (ins VR128:$src1, i32i8imm:$src2),
6653 !strconcat(OpcodeStr,
6654 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6655 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6657 Sched<[WriteShuffle]>;
6658 let hasSideEffects = 0, mayStore = 1,
6659 SchedRW = [WriteShuffleLd, WriteRMW] in
6660 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6661 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6662 !strconcat(OpcodeStr,
6663 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6664 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6665 imm:$src2)))), addr:$dst)]>;
6668 let Predicates = [HasAVX] in
6669 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6671 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6674 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6675 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6676 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6677 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6678 (ins VR128:$src1, i32i8imm:$src2),
6679 !strconcat(OpcodeStr,
6680 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6681 []>, Sched<[WriteShuffle]>;
6683 let hasSideEffects = 0, mayStore = 1,
6684 SchedRW = [WriteShuffleLd, WriteRMW] in
6685 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6686 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6687 !strconcat(OpcodeStr,
6688 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6689 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6690 imm:$src2)))), addr:$dst)]>;
6693 let Predicates = [HasAVX] in
6694 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6696 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6699 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6700 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6701 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6702 (ins VR128:$src1, i32i8imm:$src2),
6703 !strconcat(OpcodeStr,
6704 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6706 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6707 Sched<[WriteShuffle]>;
6708 let SchedRW = [WriteShuffleLd, WriteRMW] in
6709 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6710 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6711 !strconcat(OpcodeStr,
6712 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6713 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6717 let Predicates = [HasAVX] in
6718 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6720 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6722 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6723 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6724 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6725 (ins VR128:$src1, i32i8imm:$src2),
6726 !strconcat(OpcodeStr,
6727 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6729 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6730 Sched<[WriteShuffle]>, REX_W;
6731 let SchedRW = [WriteShuffleLd, WriteRMW] in
6732 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6733 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6734 !strconcat(OpcodeStr,
6735 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6736 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6737 addr:$dst)]>, REX_W;
6740 let Predicates = [HasAVX] in
6741 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6743 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6745 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6747 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6748 OpndItins itins = DEFAULT_ITINS> {
6749 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6750 (ins VR128:$src1, i32i8imm:$src2),
6751 !strconcat(OpcodeStr,
6752 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6753 [(set GR32orGR64:$dst,
6754 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6755 itins.rr>, Sched<[WriteFBlend]>;
6756 let SchedRW = [WriteFBlendLd, WriteRMW] in
6757 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6758 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6759 !strconcat(OpcodeStr,
6760 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6761 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6762 addr:$dst)], itins.rm>;
6765 let ExeDomain = SSEPackedSingle in {
6766 let Predicates = [UseAVX] in
6767 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6768 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6771 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6772 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6775 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6777 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6780 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6781 Requires<[UseSSE41]>;
6783 //===----------------------------------------------------------------------===//
6784 // SSE4.1 - Insert Instructions
6785 //===----------------------------------------------------------------------===//
6787 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6788 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6789 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6791 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6793 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6795 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6796 Sched<[WriteShuffle]>;
6797 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6798 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6800 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6802 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6804 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6805 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6808 let Predicates = [HasAVX] in
6809 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6810 let Constraints = "$src1 = $dst" in
6811 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6813 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6814 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6815 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6817 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6819 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6821 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6822 Sched<[WriteShuffle]>;
6823 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6824 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6826 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6828 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6830 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6831 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6834 let Predicates = [HasAVX] in
6835 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6836 let Constraints = "$src1 = $dst" in
6837 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6839 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6840 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6841 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6843 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6845 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6847 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6848 Sched<[WriteShuffle]>;
6849 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6850 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6852 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6854 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6856 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6857 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6860 let Predicates = [HasAVX] in
6861 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6862 let Constraints = "$src1 = $dst" in
6863 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6865 // insertps has a few different modes, there's the first two here below which
6866 // are optimized inserts that won't zero arbitrary elements in the destination
6867 // vector. The next one matches the intrinsic and could zero arbitrary elements
6868 // in the target vector.
6869 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6870 OpndItins itins = DEFAULT_ITINS> {
6871 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6872 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6874 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6876 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6878 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6879 Sched<[WriteFShuffle]>;
6880 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6881 (ins VR128:$src1, f32mem:$src2, i8imm:$src3),
6883 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6885 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6887 (X86insertps VR128:$src1,
6888 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6889 imm:$src3))], itins.rm>,
6890 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6893 let ExeDomain = SSEPackedSingle in {
6894 let Predicates = [UseAVX] in
6895 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6896 let Constraints = "$src1 = $dst" in
6897 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6900 let Predicates = [UseSSE41] in {
6901 // If we're inserting an element from a load or a null pshuf of a load,
6902 // fold the load into the insertps instruction.
6903 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6904 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6906 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6907 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6908 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6909 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6912 let Predicates = [UseAVX] in {
6913 // If we're inserting an element from a vbroadcast of a load, fold the
6914 // load into the X86insertps instruction.
6915 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6916 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6917 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6918 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6919 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6920 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6923 //===----------------------------------------------------------------------===//
6924 // SSE4.1 - Round Instructions
6925 //===----------------------------------------------------------------------===//
6927 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6928 X86MemOperand x86memop, RegisterClass RC,
6929 PatFrag mem_frag32, PatFrag mem_frag64,
6930 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6931 let ExeDomain = SSEPackedSingle in {
6932 // Intrinsic operation, reg.
6933 // Vector intrinsic operation, reg
6934 def PSr : SS4AIi8<opcps, MRMSrcReg,
6935 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6936 !strconcat(OpcodeStr,
6937 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6938 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6939 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6941 // Vector intrinsic operation, mem
6942 def PSm : SS4AIi8<opcps, MRMSrcMem,
6943 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6944 !strconcat(OpcodeStr,
6945 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6947 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6948 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6949 } // ExeDomain = SSEPackedSingle
6951 let ExeDomain = SSEPackedDouble in {
6952 // Vector intrinsic operation, reg
6953 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6954 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6955 !strconcat(OpcodeStr,
6956 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6957 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6958 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6960 // Vector intrinsic operation, mem
6961 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6962 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6963 !strconcat(OpcodeStr,
6964 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6966 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6967 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6968 } // ExeDomain = SSEPackedDouble
6971 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6974 Intrinsic F64Int, bit Is2Addr = 1> {
6975 let ExeDomain = GenericDomain in {
6977 let hasSideEffects = 0 in
6978 def SSr : SS4AIi8<opcss, MRMSrcReg,
6979 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6981 !strconcat(OpcodeStr,
6982 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6983 !strconcat(OpcodeStr,
6984 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6985 []>, Sched<[WriteFAdd]>;
6987 // Intrinsic operation, reg.
6988 let isCodeGenOnly = 1 in
6989 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6990 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6992 !strconcat(OpcodeStr,
6993 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6994 !strconcat(OpcodeStr,
6995 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6996 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6999 // Intrinsic operation, mem.
7000 def SSm : SS4AIi8<opcss, MRMSrcMem,
7001 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
7003 !strconcat(OpcodeStr,
7004 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7005 !strconcat(OpcodeStr,
7006 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7008 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
7009 Sched<[WriteFAddLd, ReadAfterLd]>;
7012 let hasSideEffects = 0 in
7013 def SDr : SS4AIi8<opcsd, MRMSrcReg,
7014 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
7016 !strconcat(OpcodeStr,
7017 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7018 !strconcat(OpcodeStr,
7019 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7020 []>, Sched<[WriteFAdd]>;
7022 // Intrinsic operation, reg.
7023 let isCodeGenOnly = 1 in
7024 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
7025 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
7027 !strconcat(OpcodeStr,
7028 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7029 !strconcat(OpcodeStr,
7030 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7031 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
7034 // Intrinsic operation, mem.
7035 def SDm : SS4AIi8<opcsd, MRMSrcMem,
7036 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
7038 !strconcat(OpcodeStr,
7039 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7040 !strconcat(OpcodeStr,
7041 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7043 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
7044 Sched<[WriteFAddLd, ReadAfterLd]>;
7045 } // ExeDomain = GenericDomain
7048 // FP round - roundss, roundps, roundsd, roundpd
7049 let Predicates = [HasAVX] in {
7051 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
7052 loadv4f32, loadv2f64,
7053 int_x86_sse41_round_ps,
7054 int_x86_sse41_round_pd>, VEX;
7055 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
7056 loadv8f32, loadv4f64,
7057 int_x86_avx_round_ps_256,
7058 int_x86_avx_round_pd_256>, VEX, VEX_L;
7059 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
7060 int_x86_sse41_round_ss,
7061 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
7063 def : Pat<(ffloor FR32:$src),
7064 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
7065 def : Pat<(f64 (ffloor FR64:$src)),
7066 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
7067 def : Pat<(f32 (fnearbyint FR32:$src)),
7068 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
7069 def : Pat<(f64 (fnearbyint FR64:$src)),
7070 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
7071 def : Pat<(f32 (fceil FR32:$src)),
7072 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
7073 def : Pat<(f64 (fceil FR64:$src)),
7074 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
7075 def : Pat<(f32 (frint FR32:$src)),
7076 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
7077 def : Pat<(f64 (frint FR64:$src)),
7078 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
7079 def : Pat<(f32 (ftrunc FR32:$src)),
7080 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
7081 def : Pat<(f64 (ftrunc FR64:$src)),
7082 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
7084 def : Pat<(v4f32 (ffloor VR128:$src)),
7085 (VROUNDPSr VR128:$src, (i32 0x1))>;
7086 def : Pat<(v4f32 (fnearbyint VR128:$src)),
7087 (VROUNDPSr VR128:$src, (i32 0xC))>;
7088 def : Pat<(v4f32 (fceil VR128:$src)),
7089 (VROUNDPSr VR128:$src, (i32 0x2))>;
7090 def : Pat<(v4f32 (frint VR128:$src)),
7091 (VROUNDPSr VR128:$src, (i32 0x4))>;
7092 def : Pat<(v4f32 (ftrunc VR128:$src)),
7093 (VROUNDPSr VR128:$src, (i32 0x3))>;
7095 def : Pat<(v2f64 (ffloor VR128:$src)),
7096 (VROUNDPDr VR128:$src, (i32 0x1))>;
7097 def : Pat<(v2f64 (fnearbyint VR128:$src)),
7098 (VROUNDPDr VR128:$src, (i32 0xC))>;
7099 def : Pat<(v2f64 (fceil VR128:$src)),
7100 (VROUNDPDr VR128:$src, (i32 0x2))>;
7101 def : Pat<(v2f64 (frint VR128:$src)),
7102 (VROUNDPDr VR128:$src, (i32 0x4))>;
7103 def : Pat<(v2f64 (ftrunc VR128:$src)),
7104 (VROUNDPDr VR128:$src, (i32 0x3))>;
7106 def : Pat<(v8f32 (ffloor VR256:$src)),
7107 (VROUNDYPSr VR256:$src, (i32 0x1))>;
7108 def : Pat<(v8f32 (fnearbyint VR256:$src)),
7109 (VROUNDYPSr VR256:$src, (i32 0xC))>;
7110 def : Pat<(v8f32 (fceil VR256:$src)),
7111 (VROUNDYPSr VR256:$src, (i32 0x2))>;
7112 def : Pat<(v8f32 (frint VR256:$src)),
7113 (VROUNDYPSr VR256:$src, (i32 0x4))>;
7114 def : Pat<(v8f32 (ftrunc VR256:$src)),
7115 (VROUNDYPSr VR256:$src, (i32 0x3))>;
7117 def : Pat<(v4f64 (ffloor VR256:$src)),
7118 (VROUNDYPDr VR256:$src, (i32 0x1))>;
7119 def : Pat<(v4f64 (fnearbyint VR256:$src)),
7120 (VROUNDYPDr VR256:$src, (i32 0xC))>;
7121 def : Pat<(v4f64 (fceil VR256:$src)),
7122 (VROUNDYPDr VR256:$src, (i32 0x2))>;
7123 def : Pat<(v4f64 (frint VR256:$src)),
7124 (VROUNDYPDr VR256:$src, (i32 0x4))>;
7125 def : Pat<(v4f64 (ftrunc VR256:$src)),
7126 (VROUNDYPDr VR256:$src, (i32 0x3))>;
7129 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
7130 memopv4f32, memopv2f64,
7131 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
7132 let Constraints = "$src1 = $dst" in
7133 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
7134 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
7136 let Predicates = [UseSSE41] in {
7137 def : Pat<(ffloor FR32:$src),
7138 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
7139 def : Pat<(f64 (ffloor FR64:$src)),
7140 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
7141 def : Pat<(f32 (fnearbyint FR32:$src)),
7142 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
7143 def : Pat<(f64 (fnearbyint FR64:$src)),
7144 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
7145 def : Pat<(f32 (fceil FR32:$src)),
7146 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
7147 def : Pat<(f64 (fceil FR64:$src)),
7148 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
7149 def : Pat<(f32 (frint FR32:$src)),
7150 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
7151 def : Pat<(f64 (frint FR64:$src)),
7152 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
7153 def : Pat<(f32 (ftrunc FR32:$src)),
7154 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
7155 def : Pat<(f64 (ftrunc FR64:$src)),
7156 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
7158 def : Pat<(v4f32 (ffloor VR128:$src)),
7159 (ROUNDPSr VR128:$src, (i32 0x1))>;
7160 def : Pat<(v4f32 (fnearbyint VR128:$src)),
7161 (ROUNDPSr VR128:$src, (i32 0xC))>;
7162 def : Pat<(v4f32 (fceil VR128:$src)),
7163 (ROUNDPSr VR128:$src, (i32 0x2))>;
7164 def : Pat<(v4f32 (frint VR128:$src)),
7165 (ROUNDPSr VR128:$src, (i32 0x4))>;
7166 def : Pat<(v4f32 (ftrunc VR128:$src)),
7167 (ROUNDPSr VR128:$src, (i32 0x3))>;
7169 def : Pat<(v2f64 (ffloor VR128:$src)),
7170 (ROUNDPDr VR128:$src, (i32 0x1))>;
7171 def : Pat<(v2f64 (fnearbyint VR128:$src)),
7172 (ROUNDPDr VR128:$src, (i32 0xC))>;
7173 def : Pat<(v2f64 (fceil VR128:$src)),
7174 (ROUNDPDr VR128:$src, (i32 0x2))>;
7175 def : Pat<(v2f64 (frint VR128:$src)),
7176 (ROUNDPDr VR128:$src, (i32 0x4))>;
7177 def : Pat<(v2f64 (ftrunc VR128:$src)),
7178 (ROUNDPDr VR128:$src, (i32 0x3))>;
7181 //===----------------------------------------------------------------------===//
7182 // SSE4.1 - Packed Bit Test
7183 //===----------------------------------------------------------------------===//
7185 // ptest instruction we'll lower to this in X86ISelLowering primarily from
7186 // the intel intrinsic that corresponds to this.
7187 let Defs = [EFLAGS], Predicates = [HasAVX] in {
7188 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
7189 "vptest\t{$src2, $src1|$src1, $src2}",
7190 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
7191 Sched<[WriteVecLogic]>, VEX;
7192 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
7193 "vptest\t{$src2, $src1|$src1, $src2}",
7194 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
7195 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
7197 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
7198 "vptest\t{$src2, $src1|$src1, $src2}",
7199 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
7200 Sched<[WriteVecLogic]>, VEX, VEX_L;
7201 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
7202 "vptest\t{$src2, $src1|$src1, $src2}",
7203 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
7204 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
7207 let Defs = [EFLAGS] in {
7208 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
7209 "ptest\t{$src2, $src1|$src1, $src2}",
7210 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
7211 Sched<[WriteVecLogic]>;
7212 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
7213 "ptest\t{$src2, $src1|$src1, $src2}",
7214 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
7215 Sched<[WriteVecLogicLd, ReadAfterLd]>;
7218 // The bit test instructions below are AVX only
7219 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
7220 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
7221 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
7222 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
7223 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
7224 Sched<[WriteVecLogic]>, VEX;
7225 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
7226 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
7227 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
7228 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
7231 let Defs = [EFLAGS], Predicates = [HasAVX] in {
7232 let ExeDomain = SSEPackedSingle in {
7233 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
7234 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
7237 let ExeDomain = SSEPackedDouble in {
7238 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
7239 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
7244 //===----------------------------------------------------------------------===//
7245 // SSE4.1 - Misc Instructions
7246 //===----------------------------------------------------------------------===//
7248 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
7249 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
7250 "popcnt{w}\t{$src, $dst|$dst, $src}",
7251 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
7252 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
7254 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
7255 "popcnt{w}\t{$src, $dst|$dst, $src}",
7256 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
7257 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7258 Sched<[WriteFAddLd]>, OpSize16, XS;
7260 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
7261 "popcnt{l}\t{$src, $dst|$dst, $src}",
7262 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
7263 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
7266 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
7267 "popcnt{l}\t{$src, $dst|$dst, $src}",
7268 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
7269 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7270 Sched<[WriteFAddLd]>, OpSize32, XS;
7272 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
7273 "popcnt{q}\t{$src, $dst|$dst, $src}",
7274 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
7275 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
7276 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
7277 "popcnt{q}\t{$src, $dst|$dst, $src}",
7278 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
7279 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7280 Sched<[WriteFAddLd]>, XS;
7285 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
7286 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
7288 X86FoldableSchedWrite Sched> {
7289 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7291 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7292 [(set VR128:$dst, (IntId128 VR128:$src))]>,
7294 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7296 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7298 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>,
7299 Sched<[Sched.Folded]>;
7302 // PHMIN has the same profile as PSAD, thus we use the same scheduling
7303 // model, although the naming is misleading.
7304 let Predicates = [HasAVX] in
7305 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
7306 int_x86_sse41_phminposuw,
7308 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
7309 int_x86_sse41_phminposuw,
7312 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
7313 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
7314 Intrinsic IntId128, bit Is2Addr = 1,
7315 OpndItins itins = DEFAULT_ITINS> {
7316 let isCommutable = 1 in
7317 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7318 (ins VR128:$src1, VR128:$src2),
7320 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7322 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
7323 itins.rr>, Sched<[itins.Sched]>;
7324 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7325 (ins VR128:$src1, i128mem:$src2),
7327 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7328 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7330 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
7331 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7334 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
7335 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
7337 X86FoldableSchedWrite Sched> {
7338 let isCommutable = 1 in
7339 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
7340 (ins VR256:$src1, VR256:$src2),
7341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7342 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
7344 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
7345 (ins VR256:$src1, i256mem:$src2),
7346 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7348 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
7349 Sched<[Sched.Folded, ReadAfterLd]>;
7353 /// SS48I_binop_rm - Simple SSE41 binary operator.
7354 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7355 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7356 X86MemOperand x86memop, bit Is2Addr = 1,
7357 OpndItins itins = SSE_INTALU_ITINS_P> {
7358 let isCommutable = 1 in
7359 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7360 (ins RC:$src1, RC:$src2),
7362 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7363 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7364 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7365 Sched<[itins.Sched]>;
7366 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7367 (ins RC:$src1, x86memop:$src2),
7369 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7370 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7372 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
7373 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7376 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
7378 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
7379 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
7380 PatFrag memop_frag, X86MemOperand x86memop,
7382 bit IsCommutable = 0, bit Is2Addr = 1> {
7383 let isCommutable = IsCommutable in
7384 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7385 (ins RC:$src1, RC:$src2),
7387 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7388 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7389 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
7390 Sched<[itins.Sched]>;
7391 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7392 (ins RC:$src1, x86memop:$src2),
7394 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7395 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7396 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
7397 (bitconvert (memop_frag addr:$src2)))))]>,
7398 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7401 let Predicates = [HasAVX] in {
7402 let isCommutable = 0 in
7403 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
7404 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7406 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
7407 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7409 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
7410 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7412 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
7413 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7415 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
7416 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7418 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
7419 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7421 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
7422 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7424 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
7425 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7427 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
7428 VR128, loadv2i64, i128mem,
7429 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
7432 let Predicates = [HasAVX2] in {
7433 let isCommutable = 0 in
7434 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
7435 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7437 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
7438 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7440 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
7441 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7443 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
7444 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7446 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
7447 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7449 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
7450 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7452 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
7453 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7455 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
7456 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7458 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
7459 VR256, loadv4i64, i256mem,
7460 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
7463 let Constraints = "$src1 = $dst" in {
7464 let isCommutable = 0 in
7465 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
7466 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7467 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
7468 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7469 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
7470 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7471 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
7472 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7473 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
7474 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7475 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
7476 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7477 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
7478 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7479 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7480 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7481 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
7482 VR128, memopv2i64, i128mem,
7483 SSE_INTMUL_ITINS_P, 1>;
7486 let Predicates = [HasAVX] in {
7487 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7488 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
7490 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7491 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7494 let Predicates = [HasAVX2] in {
7495 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7496 memopv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
7498 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7499 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7503 let Constraints = "$src1 = $dst" in {
7504 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7505 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7506 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7507 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7510 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7511 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7512 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7513 X86MemOperand x86memop, bit Is2Addr = 1,
7514 OpndItins itins = DEFAULT_ITINS> {
7515 let isCommutable = 1 in
7516 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7517 (ins RC:$src1, RC:$src2, i8imm:$src3),
7519 !strconcat(OpcodeStr,
7520 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7521 !strconcat(OpcodeStr,
7522 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7523 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7524 Sched<[itins.Sched]>;
7525 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7526 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
7528 !strconcat(OpcodeStr,
7529 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7530 !strconcat(OpcodeStr,
7531 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7534 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7535 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7538 let Predicates = [HasAVX] in {
7539 let isCommutable = 0 in {
7540 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7541 VR128, loadv2i64, i128mem, 0,
7542 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7545 let ExeDomain = SSEPackedSingle in {
7546 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7547 VR128, loadv4f32, f128mem, 0,
7548 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7549 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7550 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7551 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7554 let ExeDomain = SSEPackedDouble in {
7555 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7556 VR128, loadv2f64, f128mem, 0,
7557 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7558 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7559 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7560 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7563 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7564 VR128, loadv2i64, i128mem, 0,
7565 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7567 let ExeDomain = SSEPackedSingle in
7568 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7569 VR128, loadv4f32, f128mem, 0,
7570 SSE_DPPS_ITINS>, VEX_4V;
7571 let ExeDomain = SSEPackedDouble in
7572 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7573 VR128, loadv2f64, f128mem, 0,
7574 SSE_DPPS_ITINS>, VEX_4V;
7575 let ExeDomain = SSEPackedSingle in
7576 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7577 VR256, loadv8f32, i256mem, 0,
7578 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7581 let Predicates = [HasAVX2] in {
7582 let isCommutable = 0 in {
7583 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7584 VR256, loadv4i64, i256mem, 0,
7585 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7586 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7587 VR256, loadv4i64, i256mem, 0,
7588 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7592 let Constraints = "$src1 = $dst" in {
7593 let isCommutable = 0 in {
7594 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7595 VR128, memopv2i64, i128mem,
7596 1, SSE_MPSADBW_ITINS>;
7598 let ExeDomain = SSEPackedSingle in
7599 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7600 VR128, memopv4f32, f128mem,
7601 1, SSE_INTALU_ITINS_FBLEND_P>;
7602 let ExeDomain = SSEPackedDouble in
7603 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7604 VR128, memopv2f64, f128mem,
7605 1, SSE_INTALU_ITINS_FBLEND_P>;
7606 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7607 VR128, memopv2i64, i128mem,
7608 1, SSE_INTALU_ITINS_BLEND_P>;
7609 let ExeDomain = SSEPackedSingle in
7610 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7611 VR128, memopv4f32, f128mem, 1,
7613 let ExeDomain = SSEPackedDouble in
7614 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7615 VR128, memopv2f64, f128mem, 1,
7619 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7620 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7621 RegisterClass RC, X86MemOperand x86memop,
7622 PatFrag mem_frag, Intrinsic IntId,
7623 X86FoldableSchedWrite Sched> {
7624 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7625 (ins RC:$src1, RC:$src2, RC:$src3),
7626 !strconcat(OpcodeStr,
7627 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7628 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7629 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7632 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7633 (ins RC:$src1, x86memop:$src2, RC:$src3),
7634 !strconcat(OpcodeStr,
7635 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7637 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7639 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7640 Sched<[Sched.Folded, ReadAfterLd]>;
7643 let Predicates = [HasAVX] in {
7644 let ExeDomain = SSEPackedDouble in {
7645 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7646 loadv2f64, int_x86_sse41_blendvpd,
7648 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7649 loadv4f64, int_x86_avx_blendv_pd_256,
7650 WriteFVarBlend>, VEX_L;
7651 } // ExeDomain = SSEPackedDouble
7652 let ExeDomain = SSEPackedSingle in {
7653 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7654 loadv4f32, int_x86_sse41_blendvps,
7656 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7657 loadv8f32, int_x86_avx_blendv_ps_256,
7658 WriteFVarBlend>, VEX_L;
7659 } // ExeDomain = SSEPackedSingle
7660 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7661 loadv2i64, int_x86_sse41_pblendvb,
7665 let Predicates = [HasAVX2] in {
7666 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7667 loadv4i64, int_x86_avx2_pblendvb,
7668 WriteVarBlend>, VEX_L;
7671 let Predicates = [HasAVX] in {
7672 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7673 (v16i8 VR128:$src2))),
7674 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7675 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7676 (v4i32 VR128:$src2))),
7677 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7678 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7679 (v4f32 VR128:$src2))),
7680 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7681 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7682 (v2i64 VR128:$src2))),
7683 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7684 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7685 (v2f64 VR128:$src2))),
7686 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7687 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7688 (v8i32 VR256:$src2))),
7689 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7690 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7691 (v8f32 VR256:$src2))),
7692 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7693 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7694 (v4i64 VR256:$src2))),
7695 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7696 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7697 (v4f64 VR256:$src2))),
7698 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7700 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7702 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7703 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7705 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7707 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7709 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7710 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7712 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7713 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7715 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7718 let Predicates = [HasAVX2] in {
7719 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7720 (v32i8 VR256:$src2))),
7721 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7722 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7724 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7728 let Predicates = [UseAVX] in {
7729 let AddedComplexity = 15 in {
7730 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7731 // MOVS{S,D} to the lower bits.
7732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7733 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7734 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7735 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7736 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7737 (VBLENDPSrri (v4i32 (V_SET0)), VR128:$src, (i8 1))>;
7738 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7739 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7741 // Move low f32 and clear high bits.
7742 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7743 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7744 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7745 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7748 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7749 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7750 (SUBREG_TO_REG (i32 0),
7751 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7753 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7754 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7755 (SUBREG_TO_REG (i64 0),
7756 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7759 // Move low f64 and clear high bits.
7760 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7761 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7763 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7764 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7767 let Predicates = [UseSSE41] in {
7768 // With SSE41 we can use blends for these patterns.
7769 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7770 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7771 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7772 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7773 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7774 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7778 /// SS41I_ternary_int - SSE 4.1 ternary operator
7779 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7780 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7781 X86MemOperand x86memop, Intrinsic IntId,
7782 OpndItins itins = DEFAULT_ITINS> {
7783 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7784 (ins VR128:$src1, VR128:$src2),
7785 !strconcat(OpcodeStr,
7786 "\t{$src2, $dst|$dst, $src2}"),
7787 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7788 itins.rr>, Sched<[itins.Sched]>;
7790 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7791 (ins VR128:$src1, x86memop:$src2),
7792 !strconcat(OpcodeStr,
7793 "\t{$src2, $dst|$dst, $src2}"),
7796 (bitconvert (mem_frag addr:$src2)), XMM0))],
7797 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7801 let ExeDomain = SSEPackedDouble in
7802 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7803 int_x86_sse41_blendvpd,
7804 DEFAULT_ITINS_FBLENDSCHED>;
7805 let ExeDomain = SSEPackedSingle in
7806 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7807 int_x86_sse41_blendvps,
7808 DEFAULT_ITINS_FBLENDSCHED>;
7809 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7810 int_x86_sse41_pblendvb,
7811 DEFAULT_ITINS_VARBLENDSCHED>;
7813 // Aliases with the implicit xmm0 argument
7814 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7815 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7816 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7817 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7818 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7819 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7820 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7821 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7822 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7823 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7824 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7825 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7827 let Predicates = [UseSSE41] in {
7828 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7829 (v16i8 VR128:$src2))),
7830 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7831 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7832 (v4i32 VR128:$src2))),
7833 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7834 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7835 (v4f32 VR128:$src2))),
7836 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7837 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7838 (v2i64 VR128:$src2))),
7839 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7840 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7841 (v2f64 VR128:$src2))),
7842 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7844 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7846 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7847 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7849 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7850 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7852 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7856 let SchedRW = [WriteLoad] in {
7857 let Predicates = [HasAVX] in
7858 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7859 "vmovntdqa\t{$src, $dst|$dst, $src}",
7860 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7862 let Predicates = [HasAVX2] in
7863 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7864 "vmovntdqa\t{$src, $dst|$dst, $src}",
7865 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7867 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7868 "movntdqa\t{$src, $dst|$dst, $src}",
7869 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7872 //===----------------------------------------------------------------------===//
7873 // SSE4.2 - Compare Instructions
7874 //===----------------------------------------------------------------------===//
7876 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7877 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7878 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7879 X86MemOperand x86memop, bit Is2Addr = 1> {
7880 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7881 (ins RC:$src1, RC:$src2),
7883 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7884 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7885 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7886 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7887 (ins RC:$src1, x86memop:$src2),
7889 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7890 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7892 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7895 let Predicates = [HasAVX] in
7896 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7897 loadv2i64, i128mem, 0>, VEX_4V;
7899 let Predicates = [HasAVX2] in
7900 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7901 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7903 let Constraints = "$src1 = $dst" in
7904 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7905 memopv2i64, i128mem>;
7907 //===----------------------------------------------------------------------===//
7908 // SSE4.2 - String/text Processing Instructions
7909 //===----------------------------------------------------------------------===//
7911 // Packed Compare Implicit Length Strings, Return Mask
7912 multiclass pseudo_pcmpistrm<string asm> {
7913 def REG : PseudoI<(outs VR128:$dst),
7914 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7915 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7917 def MEM : PseudoI<(outs VR128:$dst),
7918 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7919 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7920 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7923 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7924 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7925 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7928 multiclass pcmpistrm_SS42AI<string asm> {
7929 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7930 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7931 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7932 []>, Sched<[WritePCmpIStrM]>;
7934 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7935 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7936 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7937 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7940 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7941 let Predicates = [HasAVX] in
7942 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7943 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7946 // Packed Compare Explicit Length Strings, Return Mask
7947 multiclass pseudo_pcmpestrm<string asm> {
7948 def REG : PseudoI<(outs VR128:$dst),
7949 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7950 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7951 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7952 def MEM : PseudoI<(outs VR128:$dst),
7953 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7954 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7955 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7958 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7959 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7960 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7963 multiclass SS42AI_pcmpestrm<string asm> {
7964 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7965 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7966 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7967 []>, Sched<[WritePCmpEStrM]>;
7969 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7970 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7971 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7972 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7975 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7976 let Predicates = [HasAVX] in
7977 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7978 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7981 // Packed Compare Implicit Length Strings, Return Index
7982 multiclass pseudo_pcmpistri<string asm> {
7983 def REG : PseudoI<(outs GR32:$dst),
7984 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7985 [(set GR32:$dst, EFLAGS,
7986 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7987 def MEM : PseudoI<(outs GR32:$dst),
7988 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7989 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7990 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7993 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7994 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7995 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7998 multiclass SS42AI_pcmpistri<string asm> {
7999 def rr : SS42AI<0x63, MRMSrcReg, (outs),
8000 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8001 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
8002 []>, Sched<[WritePCmpIStrI]>;
8004 def rm : SS42AI<0x63, MRMSrcMem, (outs),
8005 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8006 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
8007 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
8010 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
8011 let Predicates = [HasAVX] in
8012 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
8013 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
8016 // Packed Compare Explicit Length Strings, Return Index
8017 multiclass pseudo_pcmpestri<string asm> {
8018 def REG : PseudoI<(outs GR32:$dst),
8019 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
8020 [(set GR32:$dst, EFLAGS,
8021 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
8022 def MEM : PseudoI<(outs GR32:$dst),
8023 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
8024 [(set GR32:$dst, EFLAGS,
8025 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
8029 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
8030 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
8031 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
8034 multiclass SS42AI_pcmpestri<string asm> {
8035 def rr : SS42AI<0x61, MRMSrcReg, (outs),
8036 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
8037 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
8038 []>, Sched<[WritePCmpEStrI]>;
8040 def rm : SS42AI<0x61, MRMSrcMem, (outs),
8041 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
8042 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
8043 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
8046 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
8047 let Predicates = [HasAVX] in
8048 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
8049 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
8052 //===----------------------------------------------------------------------===//
8053 // SSE4.2 - CRC Instructions
8054 //===----------------------------------------------------------------------===//
8056 // No CRC instructions have AVX equivalents
8058 // crc intrinsic instruction
8059 // This set of instructions are only rm, the only difference is the size
8061 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
8062 RegisterClass RCIn, SDPatternOperator Int> :
8063 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
8064 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
8065 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
8068 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
8069 X86MemOperand x86memop, SDPatternOperator Int> :
8070 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
8071 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
8072 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
8073 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
8075 let Constraints = "$src1 = $dst" in {
8076 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
8077 int_x86_sse42_crc32_32_8>;
8078 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
8079 int_x86_sse42_crc32_32_8>;
8080 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
8081 int_x86_sse42_crc32_32_16>, OpSize16;
8082 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
8083 int_x86_sse42_crc32_32_16>, OpSize16;
8084 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
8085 int_x86_sse42_crc32_32_32>, OpSize32;
8086 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
8087 int_x86_sse42_crc32_32_32>, OpSize32;
8088 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
8089 int_x86_sse42_crc32_64_64>, REX_W;
8090 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
8091 int_x86_sse42_crc32_64_64>, REX_W;
8092 let hasSideEffects = 0 in {
8094 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
8096 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
8101 //===----------------------------------------------------------------------===//
8102 // SHA-NI Instructions
8103 //===----------------------------------------------------------------------===//
8105 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
8107 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
8108 (ins VR128:$src1, VR128:$src2),
8109 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
8111 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
8112 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
8114 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
8115 (ins VR128:$src1, i128mem:$src2),
8116 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
8118 (set VR128:$dst, (IntId VR128:$src1,
8119 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
8120 (set VR128:$dst, (IntId VR128:$src1,
8121 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
8124 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
8125 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
8126 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8127 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8129 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
8130 (i8 imm:$src3)))]>, TA;
8131 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
8132 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8133 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8135 (int_x86_sha1rnds4 VR128:$src1,
8136 (bc_v4i32 (memopv2i64 addr:$src2)),
8137 (i8 imm:$src3)))]>, TA;
8139 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
8140 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
8141 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
8144 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
8146 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
8147 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
8150 // Aliases with explicit %xmm0
8151 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
8152 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
8153 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
8154 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
8156 //===----------------------------------------------------------------------===//
8157 // AES-NI Instructions
8158 //===----------------------------------------------------------------------===//
8160 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
8161 Intrinsic IntId128, bit Is2Addr = 1> {
8162 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
8163 (ins VR128:$src1, VR128:$src2),
8165 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
8166 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
8167 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
8168 Sched<[WriteAESDecEnc]>;
8169 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
8170 (ins VR128:$src1, i128mem:$src2),
8172 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
8173 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
8175 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
8176 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
8179 // Perform One Round of an AES Encryption/Decryption Flow
8180 let Predicates = [HasAVX, HasAES] in {
8181 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
8182 int_x86_aesni_aesenc, 0>, VEX_4V;
8183 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
8184 int_x86_aesni_aesenclast, 0>, VEX_4V;
8185 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
8186 int_x86_aesni_aesdec, 0>, VEX_4V;
8187 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
8188 int_x86_aesni_aesdeclast, 0>, VEX_4V;
8191 let Constraints = "$src1 = $dst" in {
8192 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
8193 int_x86_aesni_aesenc>;
8194 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
8195 int_x86_aesni_aesenclast>;
8196 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
8197 int_x86_aesni_aesdec>;
8198 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
8199 int_x86_aesni_aesdeclast>;
8202 // Perform the AES InvMixColumn Transformation
8203 let Predicates = [HasAVX, HasAES] in {
8204 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
8206 "vaesimc\t{$src1, $dst|$dst, $src1}",
8208 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
8210 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
8211 (ins i128mem:$src1),
8212 "vaesimc\t{$src1, $dst|$dst, $src1}",
8213 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
8214 Sched<[WriteAESIMCLd]>, VEX;
8216 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
8218 "aesimc\t{$src1, $dst|$dst, $src1}",
8220 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
8221 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
8222 (ins i128mem:$src1),
8223 "aesimc\t{$src1, $dst|$dst, $src1}",
8224 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
8225 Sched<[WriteAESIMCLd]>;
8227 // AES Round Key Generation Assist
8228 let Predicates = [HasAVX, HasAES] in {
8229 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
8230 (ins VR128:$src1, i8imm:$src2),
8231 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8233 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
8234 Sched<[WriteAESKeyGen]>, VEX;
8235 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
8236 (ins i128mem:$src1, i8imm:$src2),
8237 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8239 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
8240 Sched<[WriteAESKeyGenLd]>, VEX;
8242 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
8243 (ins VR128:$src1, i8imm:$src2),
8244 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8246 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
8247 Sched<[WriteAESKeyGen]>;
8248 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
8249 (ins i128mem:$src1, i8imm:$src2),
8250 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8252 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
8253 Sched<[WriteAESKeyGenLd]>;
8255 //===----------------------------------------------------------------------===//
8256 // PCLMUL Instructions
8257 //===----------------------------------------------------------------------===//
8259 // AVX carry-less Multiplication instructions
8260 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8261 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8262 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8264 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
8265 Sched<[WriteCLMul]>;
8267 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8268 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8269 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8270 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8271 (loadv2i64 addr:$src2), imm:$src3))]>,
8272 Sched<[WriteCLMulLd, ReadAfterLd]>;
8274 // Carry-less Multiplication instructions
8275 let Constraints = "$src1 = $dst" in {
8276 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8277 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8278 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8280 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
8281 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
8283 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8284 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8285 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8286 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8287 (memopv2i64 addr:$src2), imm:$src3))],
8288 IIC_SSE_PCLMULQDQ_RM>,
8289 Sched<[WriteCLMulLd, ReadAfterLd]>;
8290 } // Constraints = "$src1 = $dst"
8293 multiclass pclmul_alias<string asm, int immop> {
8294 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8295 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
8297 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8298 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
8300 def : InstAlias<!strconcat("vpclmul", asm,
8301 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8302 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
8305 def : InstAlias<!strconcat("vpclmul", asm,
8306 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8307 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
8310 defm : pclmul_alias<"hqhq", 0x11>;
8311 defm : pclmul_alias<"hqlq", 0x01>;
8312 defm : pclmul_alias<"lqhq", 0x10>;
8313 defm : pclmul_alias<"lqlq", 0x00>;
8315 //===----------------------------------------------------------------------===//
8316 // SSE4A Instructions
8317 //===----------------------------------------------------------------------===//
8319 let Predicates = [HasSSE4A] in {
8321 let Constraints = "$src = $dst" in {
8322 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
8323 (ins VR128:$src, i8imm:$len, i8imm:$idx),
8324 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
8325 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
8327 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8328 (ins VR128:$src, VR128:$mask),
8329 "extrq\t{$mask, $src|$src, $mask}",
8330 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
8331 VR128:$mask))]>, PD;
8333 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
8334 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
8335 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
8336 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
8337 VR128:$src2, imm:$len, imm:$idx))]>, XD;
8338 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8339 (ins VR128:$src, VR128:$mask),
8340 "insertq\t{$mask, $src|$src, $mask}",
8341 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
8342 VR128:$mask))]>, XD;
8345 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
8346 "movntss\t{$src, $dst|$dst, $src}",
8347 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
8349 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
8350 "movntsd\t{$src, $dst|$dst, $src}",
8351 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
8354 //===----------------------------------------------------------------------===//
8356 //===----------------------------------------------------------------------===//
8358 //===----------------------------------------------------------------------===//
8359 // VBROADCAST - Load from memory and broadcast to all elements of the
8360 // destination operand
8362 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
8363 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
8364 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8365 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8366 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
8368 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
8369 X86MemOperand x86memop, ValueType VT,
8370 PatFrag ld_frag, SchedWrite Sched> :
8371 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8373 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
8374 Sched<[Sched]>, VEX {
8378 // AVX2 adds register forms
8379 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
8380 Intrinsic Int, SchedWrite Sched> :
8381 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8382 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8383 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
8385 let ExeDomain = SSEPackedSingle in {
8386 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
8387 f32mem, v4f32, loadf32, WriteLoad>;
8388 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
8389 f32mem, v8f32, loadf32,
8390 WriteFShuffleLd>, VEX_L;
8392 let ExeDomain = SSEPackedDouble in
8393 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
8394 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
8395 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
8396 int_x86_avx_vbroadcastf128_pd_256,
8397 WriteFShuffleLd>, VEX_L;
8399 let ExeDomain = SSEPackedSingle in {
8400 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
8401 int_x86_avx2_vbroadcast_ss_ps,
8403 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
8404 int_x86_avx2_vbroadcast_ss_ps_256,
8405 WriteFShuffle256>, VEX_L;
8407 let ExeDomain = SSEPackedDouble in
8408 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
8409 int_x86_avx2_vbroadcast_sd_pd_256,
8410 WriteFShuffle256>, VEX_L;
8412 let Predicates = [HasAVX2] in
8413 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
8414 int_x86_avx2_vbroadcasti128, WriteLoad>,
8417 let Predicates = [HasAVX] in
8418 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
8419 (VBROADCASTF128 addr:$src)>;
8422 //===----------------------------------------------------------------------===//
8423 // VINSERTF128 - Insert packed floating-point values
8425 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8426 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8427 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8428 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8429 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
8431 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
8432 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
8433 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8434 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
8437 let Predicates = [HasAVX] in {
8438 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
8440 (VINSERTF128rr VR256:$src1, VR128:$src2,
8441 (INSERT_get_vinsert128_imm VR256:$ins))>;
8442 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
8444 (VINSERTF128rr VR256:$src1, VR128:$src2,
8445 (INSERT_get_vinsert128_imm VR256:$ins))>;
8447 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
8449 (VINSERTF128rm VR256:$src1, addr:$src2,
8450 (INSERT_get_vinsert128_imm VR256:$ins))>;
8451 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
8453 (VINSERTF128rm VR256:$src1, addr:$src2,
8454 (INSERT_get_vinsert128_imm VR256:$ins))>;
8457 let Predicates = [HasAVX1Only] in {
8458 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8460 (VINSERTF128rr VR256:$src1, VR128:$src2,
8461 (INSERT_get_vinsert128_imm VR256:$ins))>;
8462 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8464 (VINSERTF128rr VR256:$src1, VR128:$src2,
8465 (INSERT_get_vinsert128_imm VR256:$ins))>;
8466 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8468 (VINSERTF128rr VR256:$src1, VR128:$src2,
8469 (INSERT_get_vinsert128_imm VR256:$ins))>;
8470 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8472 (VINSERTF128rr VR256:$src1, VR128:$src2,
8473 (INSERT_get_vinsert128_imm VR256:$ins))>;
8475 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8477 (VINSERTF128rm VR256:$src1, addr:$src2,
8478 (INSERT_get_vinsert128_imm VR256:$ins))>;
8479 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8480 (bc_v4i32 (loadv2i64 addr:$src2)),
8482 (VINSERTF128rm VR256:$src1, addr:$src2,
8483 (INSERT_get_vinsert128_imm VR256:$ins))>;
8484 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8485 (bc_v16i8 (loadv2i64 addr:$src2)),
8487 (VINSERTF128rm VR256:$src1, addr:$src2,
8488 (INSERT_get_vinsert128_imm VR256:$ins))>;
8489 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8490 (bc_v8i16 (loadv2i64 addr:$src2)),
8492 (VINSERTF128rm VR256:$src1, addr:$src2,
8493 (INSERT_get_vinsert128_imm VR256:$ins))>;
8496 //===----------------------------------------------------------------------===//
8497 // VEXTRACTF128 - Extract packed floating-point values
8499 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8500 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
8501 (ins VR256:$src1, i8imm:$src2),
8502 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8503 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
8505 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
8506 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
8507 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8508 []>, Sched<[WriteStore]>, VEX, VEX_L;
8512 let Predicates = [HasAVX] in {
8513 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8514 (v4f32 (VEXTRACTF128rr
8515 (v8f32 VR256:$src1),
8516 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8517 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8518 (v2f64 (VEXTRACTF128rr
8519 (v4f64 VR256:$src1),
8520 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8522 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
8523 (iPTR imm))), addr:$dst),
8524 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8525 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8526 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
8527 (iPTR imm))), addr:$dst),
8528 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8529 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8532 let Predicates = [HasAVX1Only] in {
8533 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8534 (v2i64 (VEXTRACTF128rr
8535 (v4i64 VR256:$src1),
8536 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8537 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8538 (v4i32 (VEXTRACTF128rr
8539 (v8i32 VR256:$src1),
8540 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8541 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8542 (v8i16 (VEXTRACTF128rr
8543 (v16i16 VR256:$src1),
8544 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8545 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8546 (v16i8 (VEXTRACTF128rr
8547 (v32i8 VR256:$src1),
8548 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8550 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8551 (iPTR imm))), addr:$dst),
8552 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8553 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8554 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8555 (iPTR imm))), addr:$dst),
8556 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8557 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8558 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8559 (iPTR imm))), addr:$dst),
8560 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8561 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8562 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8563 (iPTR imm))), addr:$dst),
8564 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8565 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8568 //===----------------------------------------------------------------------===//
8569 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8571 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8572 Intrinsic IntLd, Intrinsic IntLd256,
8573 Intrinsic IntSt, Intrinsic IntSt256> {
8574 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8575 (ins VR128:$src1, f128mem:$src2),
8576 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8577 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8579 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8580 (ins VR256:$src1, f256mem:$src2),
8581 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8582 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8584 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8585 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8586 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8587 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8588 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8589 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8590 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8591 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8594 let ExeDomain = SSEPackedSingle in
8595 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8596 int_x86_avx_maskload_ps,
8597 int_x86_avx_maskload_ps_256,
8598 int_x86_avx_maskstore_ps,
8599 int_x86_avx_maskstore_ps_256>;
8600 let ExeDomain = SSEPackedDouble in
8601 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8602 int_x86_avx_maskload_pd,
8603 int_x86_avx_maskload_pd_256,
8604 int_x86_avx_maskstore_pd,
8605 int_x86_avx_maskstore_pd_256>;
8607 //===----------------------------------------------------------------------===//
8608 // VPERMIL - Permute Single and Double Floating-Point Values
8610 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8611 RegisterClass RC, X86MemOperand x86memop_f,
8612 X86MemOperand x86memop_i, PatFrag i_frag,
8613 Intrinsic IntVar, ValueType vt> {
8614 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8615 (ins RC:$src1, RC:$src2),
8616 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8617 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8618 Sched<[WriteFShuffle]>;
8619 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8620 (ins RC:$src1, x86memop_i:$src2),
8621 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8622 [(set RC:$dst, (IntVar RC:$src1,
8623 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8624 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8626 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8627 (ins RC:$src1, i8imm:$src2),
8628 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8629 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8630 Sched<[WriteFShuffle]>;
8631 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8632 (ins x86memop_f:$src1, i8imm:$src2),
8633 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8635 (vt (X86VPermilpi (memop addr:$src1), (i8 imm:$src2))))]>, VEX,
8636 Sched<[WriteFShuffleLd]>;
8639 let ExeDomain = SSEPackedSingle in {
8640 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8641 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8642 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8643 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8645 let ExeDomain = SSEPackedDouble in {
8646 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8647 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8648 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8649 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8652 let Predicates = [HasAVX] in {
8653 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8654 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8655 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8656 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8657 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8658 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8659 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8660 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8662 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8663 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8664 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8665 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8666 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8668 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8669 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8670 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8672 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8673 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8674 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8675 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8676 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8677 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8678 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8679 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8681 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8682 (VPERMILPDri VR128:$src1, imm:$imm)>;
8683 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8684 (VPERMILPDmi addr:$src1, imm:$imm)>;
8687 //===----------------------------------------------------------------------===//
8688 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8690 let ExeDomain = SSEPackedSingle in {
8691 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8692 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8693 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8694 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8695 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8696 Sched<[WriteFShuffle]>;
8697 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8698 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8699 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8700 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8701 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8702 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8705 let Predicates = [HasAVX] in {
8706 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8707 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8708 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8709 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8710 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8713 let Predicates = [HasAVX1Only] in {
8714 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8715 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8716 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8717 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8718 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8719 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8720 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8721 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8723 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8724 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8725 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8726 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8727 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8728 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8729 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8730 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8731 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8732 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8733 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8734 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8737 //===----------------------------------------------------------------------===//
8738 // VZERO - Zero YMM registers
8740 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8741 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8742 // Zero All YMM registers
8743 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8744 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8746 // Zero Upper bits of YMM registers
8747 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8748 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8751 //===----------------------------------------------------------------------===//
8752 // Half precision conversion instructions
8753 //===----------------------------------------------------------------------===//
8754 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8755 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8756 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8757 [(set RC:$dst, (Int VR128:$src))]>,
8758 T8PD, VEX, Sched<[WriteCvtF2F]>;
8759 let hasSideEffects = 0, mayLoad = 1 in
8760 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8761 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8762 Sched<[WriteCvtF2FLd]>;
8765 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8766 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8767 (ins RC:$src1, i32i8imm:$src2),
8768 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8769 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8770 TAPD, VEX, Sched<[WriteCvtF2F]>;
8771 let hasSideEffects = 0, mayStore = 1,
8772 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8773 def mr : Ii8<0x1D, MRMDestMem, (outs),
8774 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8775 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8779 let Predicates = [HasF16C] in {
8780 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8781 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8782 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8783 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8785 // Pattern match vcvtph2ps of a scalar i64 load.
8786 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8787 (VCVTPH2PSrm addr:$src)>;
8788 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8789 (VCVTPH2PSrm addr:$src)>;
8792 // Patterns for matching conversions from float to half-float and vice versa.
8793 let Predicates = [HasF16C] in {
8794 def : Pat<(fp_to_f16 FR32:$src),
8795 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8796 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8798 def : Pat<(f16_to_fp GR16:$src),
8799 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8800 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8802 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8803 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8804 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8807 //===----------------------------------------------------------------------===//
8808 // AVX2 Instructions
8809 //===----------------------------------------------------------------------===//
8811 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8812 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8813 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8814 X86MemOperand x86memop> {
8815 let isCommutable = 1 in
8816 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8817 (ins RC:$src1, RC:$src2, i8imm:$src3),
8818 !strconcat(OpcodeStr,
8819 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8820 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8821 Sched<[WriteBlend]>, VEX_4V;
8822 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8823 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
8824 !strconcat(OpcodeStr,
8825 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8828 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8829 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8832 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8833 VR128, loadv2i64, i128mem>;
8834 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8835 VR256, loadv4i64, i256mem>, VEX_L;
8837 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8839 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8840 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8842 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8844 //===----------------------------------------------------------------------===//
8845 // VPBROADCAST - Load from memory and broadcast to all elements of the
8846 // destination operand
8848 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8849 X86MemOperand x86memop, PatFrag ld_frag,
8850 Intrinsic Int128, Intrinsic Int256> {
8851 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8852 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8853 [(set VR128:$dst, (Int128 VR128:$src))]>,
8854 Sched<[WriteShuffle]>, VEX;
8855 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8856 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8858 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8859 Sched<[WriteLoad]>, VEX;
8860 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8861 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8862 [(set VR256:$dst, (Int256 VR128:$src))]>,
8863 Sched<[WriteShuffle256]>, VEX, VEX_L;
8864 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8865 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8867 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8868 Sched<[WriteLoad]>, VEX, VEX_L;
8871 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8872 int_x86_avx2_pbroadcastb_128,
8873 int_x86_avx2_pbroadcastb_256>;
8874 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8875 int_x86_avx2_pbroadcastw_128,
8876 int_x86_avx2_pbroadcastw_256>;
8877 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8878 int_x86_avx2_pbroadcastd_128,
8879 int_x86_avx2_pbroadcastd_256>;
8880 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8881 int_x86_avx2_pbroadcastq_128,
8882 int_x86_avx2_pbroadcastq_256>;
8884 let Predicates = [HasAVX2] in {
8885 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8886 (VPBROADCASTBrm addr:$src)>;
8887 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8888 (VPBROADCASTBYrm addr:$src)>;
8889 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8890 (VPBROADCASTWrm addr:$src)>;
8891 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8892 (VPBROADCASTWYrm addr:$src)>;
8893 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8894 (VPBROADCASTDrm addr:$src)>;
8895 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8896 (VPBROADCASTDYrm addr:$src)>;
8897 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8898 (VPBROADCASTQrm addr:$src)>;
8899 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8900 (VPBROADCASTQYrm addr:$src)>;
8902 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8903 (VPBROADCASTBrr VR128:$src)>;
8904 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8905 (VPBROADCASTBYrr VR128:$src)>;
8906 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8907 (VPBROADCASTWrr VR128:$src)>;
8908 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8909 (VPBROADCASTWYrr VR128:$src)>;
8910 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8911 (VPBROADCASTDrr VR128:$src)>;
8912 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8913 (VPBROADCASTDYrr VR128:$src)>;
8914 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8915 (VPBROADCASTQrr VR128:$src)>;
8916 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8917 (VPBROADCASTQYrr VR128:$src)>;
8918 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8919 (VBROADCASTSSrr VR128:$src)>;
8920 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8921 (VBROADCASTSSYrr VR128:$src)>;
8922 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8923 (VPBROADCASTQrr VR128:$src)>;
8924 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8925 (VBROADCASTSDYrr VR128:$src)>;
8927 // Provide aliases for broadcast from the same regitser class that
8928 // automatically does the extract.
8929 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8930 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8932 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8933 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8935 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8936 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8938 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8939 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8941 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8942 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8944 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8945 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8948 // Provide fallback in case the load node that is used in the patterns above
8949 // is used by additional users, which prevents the pattern selection.
8950 let AddedComplexity = 20 in {
8951 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8952 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8953 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8954 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8955 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8956 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8958 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8959 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8960 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8961 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8962 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8963 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8965 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8966 (VPBROADCASTBrr (COPY_TO_REGCLASS
8967 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8969 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8970 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8971 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8974 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8975 (VPBROADCASTWrr (COPY_TO_REGCLASS
8976 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8978 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8979 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8980 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8983 // The patterns for VPBROADCASTD are not needed because they would match
8984 // the exact same thing as VBROADCASTSS patterns.
8986 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8987 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8988 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8992 // AVX1 broadcast patterns
8993 let Predicates = [HasAVX1Only] in {
8994 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8995 (VBROADCASTSSYrm addr:$src)>;
8996 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8997 (VBROADCASTSDYrm addr:$src)>;
8998 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8999 (VBROADCASTSSrm addr:$src)>;
9002 let Predicates = [HasAVX] in {
9003 // Provide fallback in case the load node that is used in the patterns above
9004 // is used by additional users, which prevents the pattern selection.
9005 let AddedComplexity = 20 in {
9006 // 128bit broadcasts:
9007 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
9008 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
9009 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
9010 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
9011 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
9012 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
9013 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
9014 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
9015 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
9016 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
9018 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
9019 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
9020 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
9021 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
9022 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
9023 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
9024 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
9025 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
9026 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
9027 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
9030 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
9031 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
9034 //===----------------------------------------------------------------------===//
9035 // VPERM - Permute instructions
9038 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
9039 ValueType OpVT, X86FoldableSchedWrite Sched> {
9040 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
9041 (ins VR256:$src1, VR256:$src2),
9042 !strconcat(OpcodeStr,
9043 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9045 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
9046 Sched<[Sched]>, VEX_4V, VEX_L;
9047 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
9048 (ins VR256:$src1, i256mem:$src2),
9049 !strconcat(OpcodeStr,
9050 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9052 (OpVT (X86VPermv VR256:$src1,
9053 (bitconvert (mem_frag addr:$src2)))))]>,
9054 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
9057 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
9058 let ExeDomain = SSEPackedSingle in
9059 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
9061 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
9062 ValueType OpVT, X86FoldableSchedWrite Sched> {
9063 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
9064 (ins VR256:$src1, i8imm:$src2),
9065 !strconcat(OpcodeStr,
9066 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9068 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
9069 Sched<[Sched]>, VEX, VEX_L;
9070 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
9071 (ins i256mem:$src1, i8imm:$src2),
9072 !strconcat(OpcodeStr,
9073 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9075 (OpVT (X86VPermi (mem_frag addr:$src1),
9076 (i8 imm:$src2))))]>,
9077 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
9080 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
9081 WriteShuffle256>, VEX_W;
9082 let ExeDomain = SSEPackedDouble in
9083 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
9084 WriteFShuffle256>, VEX_W;
9086 //===----------------------------------------------------------------------===//
9087 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
9089 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
9090 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
9091 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
9092 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
9093 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
9095 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
9096 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
9097 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
9098 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
9100 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
9102 let Predicates = [HasAVX2] in {
9103 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
9104 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
9105 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
9106 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
9107 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
9108 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
9110 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
9112 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
9113 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
9114 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
9115 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
9116 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
9118 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
9122 //===----------------------------------------------------------------------===//
9123 // VINSERTI128 - Insert packed integer values
9125 let hasSideEffects = 0 in {
9126 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
9127 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
9128 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
9129 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
9131 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
9132 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
9133 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
9134 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
9137 let Predicates = [HasAVX2] in {
9138 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
9140 (VINSERTI128rr VR256:$src1, VR128:$src2,
9141 (INSERT_get_vinsert128_imm VR256:$ins))>;
9142 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
9144 (VINSERTI128rr VR256:$src1, VR128:$src2,
9145 (INSERT_get_vinsert128_imm VR256:$ins))>;
9146 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
9148 (VINSERTI128rr VR256:$src1, VR128:$src2,
9149 (INSERT_get_vinsert128_imm VR256:$ins))>;
9150 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
9152 (VINSERTI128rr VR256:$src1, VR128:$src2,
9153 (INSERT_get_vinsert128_imm VR256:$ins))>;
9155 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
9157 (VINSERTI128rm VR256:$src1, addr:$src2,
9158 (INSERT_get_vinsert128_imm VR256:$ins))>;
9159 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
9160 (bc_v4i32 (loadv2i64 addr:$src2)),
9162 (VINSERTI128rm VR256:$src1, addr:$src2,
9163 (INSERT_get_vinsert128_imm VR256:$ins))>;
9164 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
9165 (bc_v16i8 (loadv2i64 addr:$src2)),
9167 (VINSERTI128rm VR256:$src1, addr:$src2,
9168 (INSERT_get_vinsert128_imm VR256:$ins))>;
9169 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
9170 (bc_v8i16 (loadv2i64 addr:$src2)),
9172 (VINSERTI128rm VR256:$src1, addr:$src2,
9173 (INSERT_get_vinsert128_imm VR256:$ins))>;
9176 //===----------------------------------------------------------------------===//
9177 // VEXTRACTI128 - Extract packed integer values
9179 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
9180 (ins VR256:$src1, i8imm:$src2),
9181 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
9183 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
9184 Sched<[WriteShuffle256]>, VEX, VEX_L;
9185 let hasSideEffects = 0, mayStore = 1 in
9186 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
9187 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
9188 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
9189 Sched<[WriteStore]>, VEX, VEX_L;
9191 let Predicates = [HasAVX2] in {
9192 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
9193 (v2i64 (VEXTRACTI128rr
9194 (v4i64 VR256:$src1),
9195 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
9196 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
9197 (v4i32 (VEXTRACTI128rr
9198 (v8i32 VR256:$src1),
9199 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
9200 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
9201 (v8i16 (VEXTRACTI128rr
9202 (v16i16 VR256:$src1),
9203 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
9204 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
9205 (v16i8 (VEXTRACTI128rr
9206 (v32i8 VR256:$src1),
9207 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
9209 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
9210 (iPTR imm))), addr:$dst),
9211 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9212 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9213 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
9214 (iPTR imm))), addr:$dst),
9215 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9216 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9217 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
9218 (iPTR imm))), addr:$dst),
9219 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9220 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9221 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
9222 (iPTR imm))), addr:$dst),
9223 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9224 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9227 //===----------------------------------------------------------------------===//
9228 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
9230 multiclass avx2_pmovmask<string OpcodeStr,
9231 Intrinsic IntLd128, Intrinsic IntLd256,
9232 Intrinsic IntSt128, Intrinsic IntSt256> {
9233 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
9234 (ins VR128:$src1, i128mem:$src2),
9235 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9236 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
9237 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
9238 (ins VR256:$src1, i256mem:$src2),
9239 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9240 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
9242 def mr : AVX28I<0x8e, MRMDestMem, (outs),
9243 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
9244 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9245 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
9246 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
9247 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
9248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9249 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
9252 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
9253 int_x86_avx2_maskload_d,
9254 int_x86_avx2_maskload_d_256,
9255 int_x86_avx2_maskstore_d,
9256 int_x86_avx2_maskstore_d_256>;
9257 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
9258 int_x86_avx2_maskload_q,
9259 int_x86_avx2_maskload_q_256,
9260 int_x86_avx2_maskstore_q,
9261 int_x86_avx2_maskstore_q_256>, VEX_W;
9264 //===----------------------------------------------------------------------===//
9265 // Variable Bit Shifts
9267 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
9268 ValueType vt128, ValueType vt256> {
9269 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
9270 (ins VR128:$src1, VR128:$src2),
9271 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9273 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
9274 VEX_4V, Sched<[WriteVarVecShift]>;
9275 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
9276 (ins VR128:$src1, i128mem:$src2),
9277 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9279 (vt128 (OpNode VR128:$src1,
9280 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
9281 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9282 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
9283 (ins VR256:$src1, VR256:$src2),
9284 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9286 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
9287 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
9288 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
9289 (ins VR256:$src1, i256mem:$src2),
9290 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9292 (vt256 (OpNode VR256:$src1,
9293 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
9294 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9297 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
9298 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
9299 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
9300 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
9301 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
9303 //===----------------------------------------------------------------------===//
9304 // VGATHER - GATHER Operations
9305 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
9306 X86MemOperand memop128, X86MemOperand memop256> {
9307 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
9308 (ins VR128:$src1, memop128:$src2, VR128:$mask),
9309 !strconcat(OpcodeStr,
9310 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9312 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
9313 (ins RC256:$src1, memop256:$src2, RC256:$mask),
9314 !strconcat(OpcodeStr,
9315 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9316 []>, VEX_4VOp3, VEX_L;
9319 let mayLoad = 1, Constraints
9320 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
9322 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
9323 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
9324 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
9325 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
9327 let ExeDomain = SSEPackedDouble in {
9328 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
9329 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
9332 let ExeDomain = SSEPackedSingle in {
9333 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
9334 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;