1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
22 def X86loadu : SDNode<"X86ISD::LOAD_UA", SDTLoad,
24 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
25 [SDNPCommutative, SDNPAssociative]>;
26 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
27 [SDNPCommutative, SDNPAssociative]>;
28 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
29 [SDNPHasChain, SDNPOutFlag]>;
30 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
31 [SDNPHasChain, SDNPOutFlag]>;
32 def X86s2vec : SDNode<"X86ISD::S2VEC",
33 SDTypeProfile<1, 1, []>, []>;
34 def X86pextrw : SDNode<"X86ISD::PEXTRW",
35 SDTypeProfile<1, 2, []>, []>;
36 def X86pinsrw : SDNode<"X86ISD::PINSRW",
37 SDTypeProfile<1, 3, []>, []>;
39 //===----------------------------------------------------------------------===//
40 // SSE pattern fragments
41 //===----------------------------------------------------------------------===//
43 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
44 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
46 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
47 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
48 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
50 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
51 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
52 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
53 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
54 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
55 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
57 def fp32imm0 : PatLeaf<(f32 fpimm), [{
58 return N->isExactlyValue(+0.0);
61 def PSxLDQ_imm : SDNodeXForm<imm, [{
62 // Transformation function: imm >> 3
63 return getI32Imm(N->getValue() >> 3);
66 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
68 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
69 return getI8Imm(X86::getShuffleSHUFImmediate(N));
72 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
74 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
75 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
78 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
80 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
81 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
84 def SSE_splat_mask : PatLeaf<(build_vector), [{
85 return X86::isSplatMask(N);
86 }], SHUFFLE_get_shuf_imm>;
88 def SSE_splat_v2_mask : PatLeaf<(build_vector), [{
89 return X86::isSplatMask(N);
92 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
93 return X86::isMOVHLPSMask(N);
96 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
97 return X86::isMOVHPMask(N);
100 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
101 return X86::isMOVLPMask(N);
104 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
105 return X86::isMOVLMask(N);
108 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
109 return X86::isMOVSHDUPMask(N);
112 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
113 return X86::isMOVSLDUPMask(N);
116 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
117 return X86::isUNPCKLMask(N);
120 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
121 return X86::isUNPCKHMask(N);
124 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
125 return X86::isUNPCKL_v_undef_Mask(N);
128 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
129 return X86::isPSHUFDMask(N);
130 }], SHUFFLE_get_shuf_imm>;
132 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
133 return X86::isPSHUFHWMask(N);
134 }], SHUFFLE_get_pshufhw_imm>;
136 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
137 return X86::isPSHUFLWMask(N);
138 }], SHUFFLE_get_pshuflw_imm>;
140 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
141 return X86::isPSHUFDMask(N);
142 }], SHUFFLE_get_shuf_imm>;
144 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
145 return X86::isSHUFPMask(N);
146 }], SHUFFLE_get_shuf_imm>;
148 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
149 return X86::isSHUFPMask(N);
150 }], SHUFFLE_get_shuf_imm>;
152 //===----------------------------------------------------------------------===//
153 // SSE scalar FP Instructions
154 //===----------------------------------------------------------------------===//
156 // Instruction templates
157 // SSI - SSE1 instructions with XS prefix.
158 // SDI - SSE2 instructions with XD prefix.
159 // PSI - SSE1 instructions with TB prefix.
160 // PDI - SSE2 instructions with TB and OpSize prefixes.
161 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
162 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
163 // S3I - SSE3 instructions with TB and OpSize prefixes.
164 // S3SI - SSE3 instructions with XS prefix.
165 // S3DI - SSE3 instructions with XD prefix.
166 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
167 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
168 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
169 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
170 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
171 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
172 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
173 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
174 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
175 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
176 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
177 : Ii8<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
179 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
180 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
181 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
182 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
183 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
184 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
186 //===----------------------------------------------------------------------===//
187 // Helpers for defining instructions that directly correspond to intrinsics.
189 multiclass SS_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
190 def r : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
191 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
192 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
193 def m : SSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
194 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
195 [(set VR128:$dst, (v4f32 (IntId (load addr:$src))))]>;
198 multiclass SD_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
199 def r : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
200 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
201 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
202 def m : SDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
203 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
204 [(set VR128:$dst, (v2f64 (IntId (load addr:$src))))]>;
207 class SS_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
208 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
209 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
210 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
211 class SS_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
212 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
213 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
214 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
215 class SD_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
216 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
217 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
218 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
219 class SD_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
220 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
221 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
222 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
224 class PS_Intr<bits<8> o, string OpcodeStr, Intrinsic IntId>
225 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
226 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
227 [(set VR128:$dst, (IntId VR128:$src))]>;
228 class PS_Intm<bits<8> o, string OpcodeStr, Intrinsic IntId>
229 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
230 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
231 [(set VR128:$dst, (IntId (load addr:$src)))]>;
232 class PD_Intr<bits<8> o, string OpcodeStr, Intrinsic IntId>
233 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
234 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
235 [(set VR128:$dst, (IntId VR128:$src))]>;
236 class PD_Intm<bits<8> o, string OpcodeStr, Intrinsic IntId>
237 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
238 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
239 [(set VR128:$dst, (IntId (load addr:$src)))]>;
241 class PS_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
242 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
243 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
244 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
245 class PS_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
246 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
247 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
248 [(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))]>;
249 class PD_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
250 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
251 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
252 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
253 class PD_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
254 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
255 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
256 [(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))]>;
258 // Some 'special' instructions
259 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
260 "#IMPLICIT_DEF $dst",
261 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
262 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
263 "#IMPLICIT_DEF $dst",
264 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
266 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
267 // scheduler into a branch sequence.
268 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
269 def CMOV_FR32 : I<0, Pseudo,
270 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
271 "#CMOV_FR32 PSEUDO!",
272 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
273 def CMOV_FR64 : I<0, Pseudo,
274 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
275 "#CMOV_FR64 PSEUDO!",
276 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
277 def CMOV_V4F32 : I<0, Pseudo,
278 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
279 "#CMOV_V4F32 PSEUDO!",
281 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
282 def CMOV_V2F64 : I<0, Pseudo,
283 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
284 "#CMOV_V2F64 PSEUDO!",
286 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
287 def CMOV_V2I64 : I<0, Pseudo,
288 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
289 "#CMOV_V2I64 PSEUDO!",
291 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
295 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
296 "movss {$src, $dst|$dst, $src}", []>;
297 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
298 "movss {$src, $dst|$dst, $src}",
299 [(set FR32:$dst, (loadf32 addr:$src))]>;
300 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
301 "movsd {$src, $dst|$dst, $src}", []>;
302 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
303 "movsd {$src, $dst|$dst, $src}",
304 [(set FR64:$dst, (loadf64 addr:$src))]>;
306 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
307 "movss {$src, $dst|$dst, $src}",
308 [(store FR32:$src, addr:$dst)]>;
309 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
310 "movsd {$src, $dst|$dst, $src}",
311 [(store FR64:$src, addr:$dst)]>;
313 // Arithmetic instructions
314 let isTwoAddress = 1 in {
315 let isCommutable = 1 in {
316 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
317 "addss {$src2, $dst|$dst, $src2}",
318 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
319 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
320 "addsd {$src2, $dst|$dst, $src2}",
321 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
322 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
323 "mulss {$src2, $dst|$dst, $src2}",
324 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
325 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
326 "mulsd {$src2, $dst|$dst, $src2}",
327 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
330 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
331 "addss {$src2, $dst|$dst, $src2}",
332 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
333 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
334 "addsd {$src2, $dst|$dst, $src2}",
335 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
336 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
337 "mulss {$src2, $dst|$dst, $src2}",
338 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
339 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
340 "mulsd {$src2, $dst|$dst, $src2}",
341 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
343 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
344 "divss {$src2, $dst|$dst, $src2}",
345 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
346 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
347 "divss {$src2, $dst|$dst, $src2}",
348 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
349 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
350 "divsd {$src2, $dst|$dst, $src2}",
351 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
352 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
353 "divsd {$src2, $dst|$dst, $src2}",
354 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
356 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
357 "subss {$src2, $dst|$dst, $src2}",
358 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
359 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
360 "subss {$src2, $dst|$dst, $src2}",
361 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
362 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
363 "subsd {$src2, $dst|$dst, $src2}",
364 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
365 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
366 "subsd {$src2, $dst|$dst, $src2}",
367 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
370 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
371 "sqrtss {$src, $dst|$dst, $src}",
372 [(set FR32:$dst, (fsqrt FR32:$src))]>;
373 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
374 "sqrtss {$src, $dst|$dst, $src}",
375 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
376 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
377 "sqrtsd {$src, $dst|$dst, $src}",
378 [(set FR64:$dst, (fsqrt FR64:$src))]>;
379 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
380 "sqrtsd {$src, $dst|$dst, $src}",
381 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
383 // Aliases to match intrinsics which expect XMM operand(s).
384 let isTwoAddress = 1 in {
385 let isCommutable = 1 in {
386 def Int_ADDSSrr : SS_Intrr<0x58, "addss", int_x86_sse_add_ss>;
387 def Int_ADDSDrr : SD_Intrr<0x58, "addsd", int_x86_sse2_add_sd>;
388 def Int_MULSSrr : SS_Intrr<0x59, "mulss", int_x86_sse_mul_ss>;
389 def Int_MULSDrr : SD_Intrr<0x59, "mulsd", int_x86_sse2_mul_sd>;
392 def Int_ADDSSrm : SS_Intrm<0x58, "addss", int_x86_sse_add_ss>;
393 def Int_ADDSDrm : SD_Intrm<0x58, "addsd", int_x86_sse2_add_sd>;
394 def Int_MULSSrm : SS_Intrm<0x59, "mulss", int_x86_sse_mul_ss>;
395 def Int_MULSDrm : SD_Intrm<0x59, "mulsd", int_x86_sse2_mul_sd>;
397 def Int_DIVSSrr : SS_Intrr<0x5E, "divss", int_x86_sse_div_ss>;
398 def Int_DIVSSrm : SS_Intrm<0x5E, "divss", int_x86_sse_div_ss>;
399 def Int_DIVSDrr : SD_Intrr<0x5E, "divsd", int_x86_sse2_div_sd>;
400 def Int_DIVSDrm : SD_Intrm<0x5E, "divsd", int_x86_sse2_div_sd>;
402 def Int_SUBSSrr : SS_Intrr<0x5C, "subss", int_x86_sse_sub_ss>;
403 def Int_SUBSSrm : SS_Intrm<0x5C, "subss", int_x86_sse_sub_ss>;
404 def Int_SUBSDrr : SD_Intrr<0x5C, "subsd", int_x86_sse2_sub_sd>;
405 def Int_SUBSDrm : SD_Intrm<0x5C, "subsd", int_x86_sse2_sub_sd>;
408 defm Int_SQRTSS : SS_IntUnary<0x51, "sqrtss" , int_x86_sse_sqrt_ss>;
409 defm Int_SQRTSD : SD_IntUnary<0x51, "sqrtsd" , int_x86_sse2_sqrt_sd>;
410 defm Int_RSQRTSS : SS_IntUnary<0x52, "rsqrtss", int_x86_sse_rsqrt_ss>;
411 defm Int_RCPSS : SS_IntUnary<0x53, "rcpss" , int_x86_sse_rcp_ss>;
413 let isTwoAddress = 1 in {
414 let isCommutable = 1 in {
415 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss", int_x86_sse_max_ss>;
416 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd", int_x86_sse2_max_sd>;
417 def Int_MINSSrr : SS_Intrr<0x5D, "minss", int_x86_sse_min_ss>;
418 def Int_MINSDrr : SD_Intrr<0x5D, "minsd", int_x86_sse2_min_sd>;
420 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss", int_x86_sse_max_ss>;
421 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd", int_x86_sse2_max_sd>;
422 def Int_MINSSrm : SS_Intrm<0x5D, "minss", int_x86_sse_min_ss>;
423 def Int_MINSDrm : SD_Intrm<0x5D, "minsd", int_x86_sse2_min_sd>;
426 // Conversion instructions
427 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src),
428 "cvttss2si {$src, $dst|$dst, $src}",
429 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
430 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
431 "cvttss2si {$src, $dst|$dst, $src}",
432 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
433 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src),
434 "cvttsd2si {$src, $dst|$dst, $src}",
435 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
436 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src),
437 "cvttsd2si {$src, $dst|$dst, $src}",
438 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
439 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
440 "cvtsd2ss {$src, $dst|$dst, $src}",
441 [(set FR32:$dst, (fround FR64:$src))]>;
442 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
443 "cvtsd2ss {$src, $dst|$dst, $src}",
444 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
445 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src),
446 "cvtsi2ss {$src, $dst|$dst, $src}",
447 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
448 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
449 "cvtsi2ss {$src, $dst|$dst, $src}",
450 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
451 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src),
452 "cvtsi2sd {$src, $dst|$dst, $src}",
453 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
454 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
455 "cvtsi2sd {$src, $dst|$dst, $src}",
456 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
458 // SSE2 instructions with XS prefix
459 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
460 "cvtss2sd {$src, $dst|$dst, $src}",
461 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
463 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
464 "cvtss2sd {$src, $dst|$dst, $src}",
465 [(set FR64:$dst, (extload addr:$src, f32))]>, XS,
468 // Match intrinsics which expect XMM operand(s).
469 def Int_CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
470 "cvtss2si {$src, $dst|$dst, $src}",
471 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
472 def Int_CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
473 "cvtss2si {$src, $dst|$dst, $src}",
474 [(set GR32:$dst, (int_x86_sse_cvtss2si
475 (load addr:$src)))]>;
476 def Int_CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
477 "cvtsd2si {$src, $dst|$dst, $src}",
478 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
479 def Int_CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
480 "cvtsd2si {$src, $dst|$dst, $src}",
481 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
482 (load addr:$src)))]>;
484 // Aliases for intrinsics
485 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
486 "cvttss2si {$src, $dst|$dst, $src}",
487 [(set GR32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
488 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
489 "cvttss2si {$src, $dst|$dst, $src}",
490 [(set GR32:$dst, (int_x86_sse_cvttss2si(load addr:$src)))]>;
491 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
492 "cvttsd2si {$src, $dst|$dst, $src}",
493 [(set GR32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
494 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
495 "cvttsd2si {$src, $dst|$dst, $src}",
496 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
497 (load addr:$src)))]>;
499 let isTwoAddress = 1 in {
500 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
501 (ops VR128:$dst, VR128:$src1, GR32:$src2),
502 "cvtsi2ss {$src2, $dst|$dst, $src2}",
503 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
505 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
506 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
507 "cvtsi2ss {$src2, $dst|$dst, $src2}",
508 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
509 (loadi32 addr:$src2)))]>;
512 // Comparison instructions
513 let isTwoAddress = 1 in {
514 def CMPSSrr : SSI<0xC2, MRMSrcReg,
515 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
516 "cmp${cc}ss {$src, $dst|$dst, $src}",
518 def CMPSSrm : SSI<0xC2, MRMSrcMem,
519 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
520 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
521 def CMPSDrr : SDI<0xC2, MRMSrcReg,
522 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
523 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
524 def CMPSDrm : SDI<0xC2, MRMSrcMem,
525 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
526 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
529 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
530 "ucomiss {$src2, $src1|$src1, $src2}",
531 [(X86cmp FR32:$src1, FR32:$src2)]>;
532 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
533 "ucomiss {$src2, $src1|$src1, $src2}",
534 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
535 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
536 "ucomisd {$src2, $src1|$src1, $src2}",
537 [(X86cmp FR64:$src1, FR64:$src2)]>;
538 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
539 "ucomisd {$src2, $src1|$src1, $src2}",
540 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
542 // Aliases to match intrinsics which expect XMM operand(s).
543 let isTwoAddress = 1 in {
544 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
545 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
546 "cmp${cc}ss {$src, $dst|$dst, $src}",
547 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
548 VR128:$src, imm:$cc))]>;
549 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
550 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
551 "cmp${cc}ss {$src, $dst|$dst, $src}",
552 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
553 (load addr:$src), imm:$cc))]>;
554 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
555 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
556 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
557 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
558 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
559 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
562 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
563 "ucomiss {$src2, $src1|$src1, $src2}",
564 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
565 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
566 "ucomiss {$src2, $src1|$src1, $src2}",
567 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>;
568 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
569 "ucomisd {$src2, $src1|$src1, $src2}",
570 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
571 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
572 "ucomisd {$src2, $src1|$src1, $src2}",
573 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>;
575 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
576 "comiss {$src2, $src1|$src1, $src2}",
577 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
578 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
579 "comiss {$src2, $src1|$src1, $src2}",
580 [(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>;
581 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
582 "comisd {$src2, $src1|$src1, $src2}",
583 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
584 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
585 "comisd {$src2, $src1|$src1, $src2}",
586 [(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
588 // Aliases of packed instructions for scalar use. These all have names that
591 // Alias instructions that map fld0 to pxor for sse.
592 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
593 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
594 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
595 Requires<[HasSSE1]>, TB, OpSize;
596 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
597 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
598 Requires<[HasSSE2]>, TB, OpSize;
600 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
601 // Upper bits are disregarded.
602 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
603 "movaps {$src, $dst|$dst, $src}", []>;
604 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
605 "movapd {$src, $dst|$dst, $src}", []>;
607 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
608 // Upper bits are disregarded.
609 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
610 "movaps {$src, $dst|$dst, $src}",
611 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
612 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
613 "movapd {$src, $dst|$dst, $src}",
614 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
616 // Alias bitwise logical operations using SSE logical ops on packed FP values.
617 let isTwoAddress = 1 in {
618 let isCommutable = 1 in {
619 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
620 "andps {$src2, $dst|$dst, $src2}",
621 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
622 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
623 "andpd {$src2, $dst|$dst, $src2}",
624 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
625 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
626 "orps {$src2, $dst|$dst, $src2}", []>;
627 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
628 "orpd {$src2, $dst|$dst, $src2}", []>;
629 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
630 "xorps {$src2, $dst|$dst, $src2}",
631 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
632 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
633 "xorpd {$src2, $dst|$dst, $src2}",
634 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
636 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
637 "andps {$src2, $dst|$dst, $src2}",
638 [(set FR32:$dst, (X86fand FR32:$src1,
639 (X86loadpf32 addr:$src2)))]>;
640 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
641 "andpd {$src2, $dst|$dst, $src2}",
642 [(set FR64:$dst, (X86fand FR64:$src1,
643 (X86loadpf64 addr:$src2)))]>;
644 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
645 "orps {$src2, $dst|$dst, $src2}", []>;
646 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
647 "orpd {$src2, $dst|$dst, $src2}", []>;
648 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
649 "xorps {$src2, $dst|$dst, $src2}",
650 [(set FR32:$dst, (X86fxor FR32:$src1,
651 (X86loadpf32 addr:$src2)))]>;
652 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
653 "xorpd {$src2, $dst|$dst, $src2}",
654 [(set FR64:$dst, (X86fxor FR64:$src1,
655 (X86loadpf64 addr:$src2)))]>;
657 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
658 "andnps {$src2, $dst|$dst, $src2}", []>;
659 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
660 "andnps {$src2, $dst|$dst, $src2}", []>;
661 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
662 "andnpd {$src2, $dst|$dst, $src2}", []>;
663 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
664 "andnpd {$src2, $dst|$dst, $src2}", []>;
667 //===----------------------------------------------------------------------===//
668 // SSE packed FP Instructions
669 //===----------------------------------------------------------------------===//
671 // Some 'special' instructions
672 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
673 "#IMPLICIT_DEF $dst",
674 [(set VR128:$dst, (v4f32 (undef)))]>,
678 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
679 "movaps {$src, $dst|$dst, $src}", []>;
680 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
681 "movaps {$src, $dst|$dst, $src}",
682 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
683 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
684 "movapd {$src, $dst|$dst, $src}", []>;
685 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
686 "movapd {$src, $dst|$dst, $src}",
687 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
689 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
690 "movaps {$src, $dst|$dst, $src}",
691 [(store (v4f32 VR128:$src), addr:$dst)]>;
692 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
693 "movapd {$src, $dst|$dst, $src}",
694 [(store (v2f64 VR128:$src), addr:$dst)]>;
696 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
697 "movups {$src, $dst|$dst, $src}", []>;
698 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
699 "movups {$src, $dst|$dst, $src}",
700 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
701 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
702 "movups {$src, $dst|$dst, $src}",
703 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
704 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
705 "movupd {$src, $dst|$dst, $src}", []>;
706 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
707 "movupd {$src, $dst|$dst, $src}",
708 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
709 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
710 "movupd {$src, $dst|$dst, $src}",
711 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
713 let isTwoAddress = 1 in {
714 let AddedComplexity = 20 in {
715 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
716 "movlps {$src2, $dst|$dst, $src2}",
718 (v4f32 (vector_shuffle VR128:$src1,
719 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
720 MOVLP_shuffle_mask)))]>;
721 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
722 "movlpd {$src2, $dst|$dst, $src2}",
724 (v2f64 (vector_shuffle VR128:$src1,
725 (scalar_to_vector (loadf64 addr:$src2)),
726 MOVLP_shuffle_mask)))]>;
727 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
728 "movhps {$src2, $dst|$dst, $src2}",
730 (v4f32 (vector_shuffle VR128:$src1,
731 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
732 MOVHP_shuffle_mask)))]>;
733 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
734 "movhpd {$src2, $dst|$dst, $src2}",
736 (v2f64 (vector_shuffle VR128:$src1,
737 (scalar_to_vector (loadf64 addr:$src2)),
738 MOVHP_shuffle_mask)))]>;
742 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
743 "movlps {$src, $dst|$dst, $src}",
744 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
745 (iPTR 0))), addr:$dst)]>;
746 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
747 "movlpd {$src, $dst|$dst, $src}",
748 [(store (f64 (vector_extract (v2f64 VR128:$src),
749 (iPTR 0))), addr:$dst)]>;
751 // v2f64 extract element 1 is always custom lowered to unpack high to low
752 // and extract element 0 so the non-store version isn't too horrible.
753 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
754 "movhps {$src, $dst|$dst, $src}",
755 [(store (f64 (vector_extract
756 (v2f64 (vector_shuffle
757 (bc_v2f64 (v4f32 VR128:$src)), (undef),
758 UNPCKH_shuffle_mask)), (iPTR 0))),
760 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
761 "movhpd {$src, $dst|$dst, $src}",
762 [(store (f64 (vector_extract
763 (v2f64 (vector_shuffle VR128:$src, (undef),
764 UNPCKH_shuffle_mask)), (iPTR 0))),
767 let isTwoAddress = 1 in {
768 let AddedComplexity = 20 in {
769 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
770 "movlhps {$src2, $dst|$dst, $src2}",
772 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
773 MOVHP_shuffle_mask)))]>;
775 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
776 "movhlps {$src2, $dst|$dst, $src2}",
778 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
779 MOVHLPS_shuffle_mask)))]>;
783 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
784 "movshdup {$src, $dst|$dst, $src}",
785 [(set VR128:$dst, (v4f32 (vector_shuffle
787 MOVSHDUP_shuffle_mask)))]>;
788 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
789 "movshdup {$src, $dst|$dst, $src}",
790 [(set VR128:$dst, (v4f32 (vector_shuffle
791 (loadv4f32 addr:$src), (undef),
792 MOVSHDUP_shuffle_mask)))]>;
794 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
795 "movsldup {$src, $dst|$dst, $src}",
796 [(set VR128:$dst, (v4f32 (vector_shuffle
798 MOVSLDUP_shuffle_mask)))]>;
799 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
800 "movsldup {$src, $dst|$dst, $src}",
801 [(set VR128:$dst, (v4f32 (vector_shuffle
802 (loadv4f32 addr:$src), (undef),
803 MOVSLDUP_shuffle_mask)))]>;
805 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
806 "movddup {$src, $dst|$dst, $src}",
807 [(set VR128:$dst, (v2f64 (vector_shuffle
809 SSE_splat_v2_mask)))]>;
810 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
811 "movddup {$src, $dst|$dst, $src}",
812 [(set VR128:$dst, (v2f64 (vector_shuffle
813 (scalar_to_vector (loadf64 addr:$src)),
815 SSE_splat_v2_mask)))]>;
817 // SSE2 instructions without OpSize prefix
818 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
819 "cvtdq2ps {$src, $dst|$dst, $src}",
820 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
821 TB, Requires<[HasSSE2]>;
822 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
823 "cvtdq2ps {$src, $dst|$dst, $src}",
824 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
825 (bitconvert (loadv2i64 addr:$src))))]>,
826 TB, Requires<[HasSSE2]>;
828 // SSE2 instructions with XS prefix
829 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
830 "cvtdq2pd {$src, $dst|$dst, $src}",
831 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
832 XS, Requires<[HasSSE2]>;
833 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
834 "cvtdq2pd {$src, $dst|$dst, $src}",
835 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
836 (bitconvert (loadv2i64 addr:$src))))]>,
837 XS, Requires<[HasSSE2]>;
839 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
840 "cvtps2dq {$src, $dst|$dst, $src}",
841 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
842 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
843 "cvtps2dq {$src, $dst|$dst, $src}",
844 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
845 (load addr:$src)))]>;
846 // SSE2 packed instructions with XS prefix
847 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
848 "cvttps2dq {$src, $dst|$dst, $src}",
849 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
850 XS, Requires<[HasSSE2]>;
851 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
852 "cvttps2dq {$src, $dst|$dst, $src}",
853 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
854 (load addr:$src)))]>,
855 XS, Requires<[HasSSE2]>;
857 // SSE2 packed instructions with XD prefix
858 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
859 "cvtpd2dq {$src, $dst|$dst, $src}",
860 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
861 XD, Requires<[HasSSE2]>;
862 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
863 "cvtpd2dq {$src, $dst|$dst, $src}",
864 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
865 (load addr:$src)))]>,
866 XD, Requires<[HasSSE2]>;
867 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
868 "cvttpd2dq {$src, $dst|$dst, $src}",
869 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
870 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
871 "cvttpd2dq {$src, $dst|$dst, $src}",
872 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
873 (load addr:$src)))]>;
875 // SSE2 instructions without OpSize prefix
876 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
877 "cvtps2pd {$src, $dst|$dst, $src}",
878 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
879 TB, Requires<[HasSSE2]>;
880 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
881 "cvtps2pd {$src, $dst|$dst, $src}",
882 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
883 (load addr:$src)))]>,
884 TB, Requires<[HasSSE2]>;
886 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
887 "cvtpd2ps {$src, $dst|$dst, $src}",
888 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
889 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
890 "cvtpd2ps {$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
892 (load addr:$src)))]>;
894 // Match intrinsics which expect XMM operand(s).
895 // Aliases for intrinsics
896 let isTwoAddress = 1 in {
897 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
898 (ops VR128:$dst, VR128:$src1, GR32:$src2),
899 "cvtsi2sd {$src2, $dst|$dst, $src2}",
900 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
902 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
903 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
904 "cvtsi2sd {$src2, $dst|$dst, $src2}",
905 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
906 (loadi32 addr:$src2)))]>;
907 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
908 (ops VR128:$dst, VR128:$src1, VR128:$src2),
909 "cvtsd2ss {$src2, $dst|$dst, $src2}",
910 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
912 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
913 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
914 "cvtsd2ss {$src2, $dst|$dst, $src2}",
915 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
916 (load addr:$src2)))]>;
917 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
918 (ops VR128:$dst, VR128:$src1, VR128:$src2),
919 "cvtss2sd {$src2, $dst|$dst, $src2}",
920 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
923 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
924 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
925 "cvtss2sd {$src2, $dst|$dst, $src2}",
926 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
927 (load addr:$src2)))]>, XS,
932 let isTwoAddress = 1 in {
933 let isCommutable = 1 in {
934 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
935 "addps {$src2, $dst|$dst, $src2}",
936 [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
937 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
938 "addpd {$src2, $dst|$dst, $src2}",
939 [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
940 def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
941 "mulps {$src2, $dst|$dst, $src2}",
942 [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
943 def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
944 "mulpd {$src2, $dst|$dst, $src2}",
945 [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
948 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
949 "addps {$src2, $dst|$dst, $src2}",
950 [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
951 (load addr:$src2))))]>;
952 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
953 "addpd {$src2, $dst|$dst, $src2}",
954 [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
955 (load addr:$src2))))]>;
956 def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
957 "mulps {$src2, $dst|$dst, $src2}",
958 [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
959 (load addr:$src2))))]>;
960 def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
961 "mulpd {$src2, $dst|$dst, $src2}",
962 [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
963 (load addr:$src2))))]>;
965 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
966 "divps {$src2, $dst|$dst, $src2}",
967 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
968 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
969 "divps {$src2, $dst|$dst, $src2}",
970 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
971 (load addr:$src2))))]>;
972 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
973 "divpd {$src2, $dst|$dst, $src2}",
974 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
975 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
976 "divpd {$src2, $dst|$dst, $src2}",
977 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
978 (load addr:$src2))))]>;
980 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
981 "subps {$src2, $dst|$dst, $src2}",
982 [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
983 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
984 "subps {$src2, $dst|$dst, $src2}",
985 [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
986 (load addr:$src2))))]>;
987 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
988 "subpd {$src2, $dst|$dst, $src2}",
989 [(set VR128:$dst, (v2f64 (fsub VR128:$src1, VR128:$src2)))]>;
990 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
991 "subpd {$src2, $dst|$dst, $src2}",
992 [(set VR128:$dst, (v2f64 (fsub VR128:$src1,
993 (load addr:$src2))))]>;
995 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
996 (ops VR128:$dst, VR128:$src1, VR128:$src2),
997 "addsubps {$src2, $dst|$dst, $src2}",
998 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1000 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
1001 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1002 "addsubps {$src2, $dst|$dst, $src2}",
1003 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1004 (load addr:$src2)))]>;
1005 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
1006 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1007 "addsubpd {$src2, $dst|$dst, $src2}",
1008 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1010 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
1011 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1012 "addsubpd {$src2, $dst|$dst, $src2}",
1013 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1014 (load addr:$src2)))]>;
1017 def SQRTPSr : PS_Intr<0x51, "sqrtps", int_x86_sse_sqrt_ps>;
1018 def SQRTPSm : PS_Intm<0x51, "sqrtps", int_x86_sse_sqrt_ps>;
1019 def SQRTPDr : PD_Intr<0x51, "sqrtpd", int_x86_sse2_sqrt_pd>;
1020 def SQRTPDm : PD_Intm<0x51, "sqrtpd", int_x86_sse2_sqrt_pd>;
1022 def RSQRTPSr : PS_Intr<0x52, "rsqrtps", int_x86_sse_rsqrt_ps>;
1023 def RSQRTPSm : PS_Intm<0x52, "rsqrtps", int_x86_sse_rsqrt_ps>;
1024 def RCPPSr : PS_Intr<0x53, "rcpps", int_x86_sse_rcp_ps>;
1025 def RCPPSm : PS_Intm<0x53, "rcpps", int_x86_sse_rcp_ps>;
1027 let isTwoAddress = 1 in {
1028 let isCommutable = 1 in {
1029 def MAXPSrr : PS_Intrr<0x5F, "maxps", int_x86_sse_max_ps>;
1030 def MAXPDrr : PD_Intrr<0x5F, "maxpd", int_x86_sse2_max_pd>;
1031 def MINPSrr : PS_Intrr<0x5D, "minps", int_x86_sse_min_ps>;
1032 def MINPDrr : PD_Intrr<0x5D, "minpd", int_x86_sse2_min_pd>;
1034 def MAXPSrm : PS_Intrm<0x5F, "maxps", int_x86_sse_max_ps>;
1035 def MAXPDrm : PD_Intrm<0x5F, "maxpd", int_x86_sse2_max_pd>;
1036 def MINPSrm : PS_Intrm<0x5D, "minps", int_x86_sse_min_ps>;
1037 def MINPDrm : PD_Intrm<0x5D, "minpd", int_x86_sse2_min_pd>;
1041 let isTwoAddress = 1 in {
1042 let isCommutable = 1 in {
1043 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1044 "andps {$src2, $dst|$dst, $src2}",
1045 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1046 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1047 "andpd {$src2, $dst|$dst, $src2}",
1049 (and (bc_v2i64 (v2f64 VR128:$src1)),
1050 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1051 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1052 "orps {$src2, $dst|$dst, $src2}",
1053 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1054 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1055 "orpd {$src2, $dst|$dst, $src2}",
1057 (or (bc_v2i64 (v2f64 VR128:$src1)),
1058 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1059 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1060 "xorps {$src2, $dst|$dst, $src2}",
1061 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1062 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1063 "xorpd {$src2, $dst|$dst, $src2}",
1065 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1066 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1068 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1069 "andps {$src2, $dst|$dst, $src2}",
1070 [(set VR128:$dst, (and VR128:$src1,
1071 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1072 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1073 "andpd {$src2, $dst|$dst, $src2}",
1075 (and (bc_v2i64 (v2f64 VR128:$src1)),
1076 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1077 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1078 "orps {$src2, $dst|$dst, $src2}",
1079 [(set VR128:$dst, (or VR128:$src1,
1080 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1081 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1082 "orpd {$src2, $dst|$dst, $src2}",
1084 (or (bc_v2i64 (v2f64 VR128:$src1)),
1085 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1086 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1087 "xorps {$src2, $dst|$dst, $src2}",
1088 [(set VR128:$dst, (xor VR128:$src1,
1089 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1090 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1091 "xorpd {$src2, $dst|$dst, $src2}",
1093 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1094 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1095 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1096 "andnps {$src2, $dst|$dst, $src2}",
1097 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1098 (bc_v2i64 (v4i32 immAllOnesV))),
1100 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1101 "andnps {$src2, $dst|$dst, $src2}",
1102 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1103 (bc_v2i64 (v4i32 immAllOnesV))),
1104 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1105 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1106 "andnpd {$src2, $dst|$dst, $src2}",
1108 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1109 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1110 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1111 "andnpd {$src2, $dst|$dst, $src2}",
1113 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1114 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1117 let isTwoAddress = 1 in {
1118 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1119 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1120 "cmp${cc}ps {$src, $dst|$dst, $src}",
1121 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1122 VR128:$src, imm:$cc))]>;
1123 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1124 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1125 "cmp${cc}ps {$src, $dst|$dst, $src}",
1126 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1127 (load addr:$src), imm:$cc))]>;
1128 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1129 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1130 "cmp${cc}pd {$src, $dst|$dst, $src}",
1131 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1132 VR128:$src, imm:$cc))]>;
1133 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1134 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1135 "cmp${cc}pd {$src, $dst|$dst, $src}",
1136 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1137 (load addr:$src), imm:$cc))]>;
1140 // Shuffle and unpack instructions
1141 let isTwoAddress = 1 in {
1142 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1143 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1144 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1145 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1146 [(set VR128:$dst, (v4f32 (vector_shuffle
1147 VR128:$src1, VR128:$src2,
1148 SHUFP_shuffle_mask:$src3)))]>;
1149 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1150 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1151 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1152 [(set VR128:$dst, (v4f32 (vector_shuffle
1153 VR128:$src1, (load addr:$src2),
1154 SHUFP_shuffle_mask:$src3)))]>;
1155 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1156 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1157 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1158 [(set VR128:$dst, (v2f64 (vector_shuffle
1159 VR128:$src1, VR128:$src2,
1160 SHUFP_shuffle_mask:$src3)))]>;
1161 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1162 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1163 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1164 [(set VR128:$dst, (v2f64 (vector_shuffle
1165 VR128:$src1, (load addr:$src2),
1166 SHUFP_shuffle_mask:$src3)))]>;
1168 let AddedComplexity = 10 in {
1169 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1170 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1171 "unpckhps {$src2, $dst|$dst, $src2}",
1172 [(set VR128:$dst, (v4f32 (vector_shuffle
1173 VR128:$src1, VR128:$src2,
1174 UNPCKH_shuffle_mask)))]>;
1175 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1176 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1177 "unpckhps {$src2, $dst|$dst, $src2}",
1178 [(set VR128:$dst, (v4f32 (vector_shuffle
1179 VR128:$src1, (load addr:$src2),
1180 UNPCKH_shuffle_mask)))]>;
1181 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1182 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1183 "unpckhpd {$src2, $dst|$dst, $src2}",
1184 [(set VR128:$dst, (v2f64 (vector_shuffle
1185 VR128:$src1, VR128:$src2,
1186 UNPCKH_shuffle_mask)))]>;
1187 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1188 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1189 "unpckhpd {$src2, $dst|$dst, $src2}",
1190 [(set VR128:$dst, (v2f64 (vector_shuffle
1191 VR128:$src1, (load addr:$src2),
1192 UNPCKH_shuffle_mask)))]>;
1194 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1195 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1196 "unpcklps {$src2, $dst|$dst, $src2}",
1197 [(set VR128:$dst, (v4f32 (vector_shuffle
1198 VR128:$src1, VR128:$src2,
1199 UNPCKL_shuffle_mask)))]>;
1200 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1201 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1202 "unpcklps {$src2, $dst|$dst, $src2}",
1203 [(set VR128:$dst, (v4f32 (vector_shuffle
1204 VR128:$src1, (load addr:$src2),
1205 UNPCKL_shuffle_mask)))]>;
1206 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1207 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1208 "unpcklpd {$src2, $dst|$dst, $src2}",
1209 [(set VR128:$dst, (v2f64 (vector_shuffle
1210 VR128:$src1, VR128:$src2,
1211 UNPCKL_shuffle_mask)))]>;
1212 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1213 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1214 "unpcklpd {$src2, $dst|$dst, $src2}",
1215 [(set VR128:$dst, (v2f64 (vector_shuffle
1216 VR128:$src1, (load addr:$src2),
1217 UNPCKL_shuffle_mask)))]>;
1218 } // AddedComplexity
1223 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
1224 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1225 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1226 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
1227 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
1228 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1229 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1230 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
1231 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
1232 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1233 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1234 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
1235 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
1236 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1237 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1238 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
1240 let isTwoAddress = 1 in {
1241 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
1242 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
1243 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
1244 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
1245 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
1246 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
1247 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
1248 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
1251 //===----------------------------------------------------------------------===//
1252 // SSE integer instructions
1253 //===----------------------------------------------------------------------===//
1255 // Move Instructions
1256 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1257 "movdqa {$src, $dst|$dst, $src}", []>;
1258 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1259 "movdqa {$src, $dst|$dst, $src}",
1260 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1261 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1262 "movdqa {$src, $dst|$dst, $src}",
1263 [(store (v2i64 VR128:$src), addr:$dst)]>;
1264 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1265 "movdqu {$src, $dst|$dst, $src}",
1266 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1267 XS, Requires<[HasSSE2]>;
1268 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1269 "movdqu {$src, $dst|$dst, $src}",
1270 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1271 XS, Requires<[HasSSE2]>;
1272 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1273 "lddqu {$src, $dst|$dst, $src}",
1274 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
1277 let isTwoAddress = 1 in {
1278 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1279 bit Commutable = 0> {
1280 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1281 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1282 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1283 let isCommutable = Commutable;
1285 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1286 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1287 [(set VR128:$dst, (IntId VR128:$src1,
1288 (bitconvert (loadv2i64 addr:$src2))))]>;
1292 let isTwoAddress = 1 in {
1293 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1294 string OpcodeStr, Intrinsic IntId> {
1295 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1296 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1297 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1298 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1299 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1300 [(set VR128:$dst, (IntId VR128:$src1,
1301 (bitconvert (loadv2i64 addr:$src2))))]>;
1302 def ri : PDIi8<opc2, ImmForm, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1303 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1304 [(set VR128:$dst, (IntId VR128:$src1,
1305 (scalar_to_vector (i32 imm:$src2))))]>;
1310 let isTwoAddress = 1 in {
1311 /// PDI_binop_rm - Simple SSE2 binary operator.
1312 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1313 ValueType OpVT, bit Commutable = 0> {
1314 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1315 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1316 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1317 let isCommutable = Commutable;
1319 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1320 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1321 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1322 (bitconvert (loadv2i64 addr:$src2)))))]>;
1327 // 128-bit Integer Arithmetic
1329 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1330 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1331 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1333 //defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, 1>;
1335 let isTwoAddress = 1 in {
1337 let isCommutable = 1 in {
1338 def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1339 "paddq {$src2, $dst|$dst, $src2}",
1340 [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
1342 def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1343 "paddq {$src2, $dst|$dst, $src2}",
1344 [(set VR128:$dst, (add VR128:$src1,
1345 (loadv2i64 addr:$src2)))]>;
1348 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1349 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1350 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1351 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1353 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1354 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1355 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1358 let isTwoAddress = 1 in {
1359 def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1360 "psubq {$src2, $dst|$dst, $src2}",
1361 [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
1363 def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1364 "psubd {$src2, $dst|$dst, $src2}",
1365 [(set VR128:$dst, (sub VR128:$src1,
1366 (loadv2i64 addr:$src2)))]>;
1369 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1370 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1371 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1372 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1374 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1376 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1377 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1378 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1380 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1382 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1383 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1386 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1387 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1388 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1389 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1390 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1393 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1394 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1395 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1397 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1398 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1399 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1401 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1402 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1403 // PSRAQ doesn't exist in SSE[1-3].
1405 let isTwoAddress = 1 in {
1406 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1407 "pslldq {$src2, $dst|$dst, $src2}", []>;
1408 def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1409 "psrldq {$src2, $dst|$dst, $src2}", []>;
1410 // PSRADQri doesn't exist in SSE[1-3].
1414 let isTwoAddress = 1 in {
1415 let isCommutable = 1 in {
1416 def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1417 "pand {$src2, $dst|$dst, $src2}",
1418 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1419 def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1420 "por {$src2, $dst|$dst, $src2}",
1421 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1422 def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1423 "pxor {$src2, $dst|$dst, $src2}",
1424 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1427 def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1428 "pand {$src2, $dst|$dst, $src2}",
1429 [(set VR128:$dst, (v2i64 (and VR128:$src1,
1430 (load addr:$src2))))]>;
1431 def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1432 "por {$src2, $dst|$dst, $src2}",
1433 [(set VR128:$dst, (v2i64 (or VR128:$src1,
1434 (load addr:$src2))))]>;
1435 def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1436 "pxor {$src2, $dst|$dst, $src2}",
1437 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
1438 (load addr:$src2))))]>;
1440 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1441 "pandn {$src2, $dst|$dst, $src2}",
1442 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1445 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1446 "pandn {$src2, $dst|$dst, $src2}",
1447 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1448 (load addr:$src2))))]>;
1451 // SSE2 Integer comparison
1452 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1453 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1454 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1455 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1456 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1457 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1459 // Pack instructions
1460 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1461 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1462 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1464 // Shuffle and unpack instructions
1465 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1466 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1467 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1468 [(set VR128:$dst, (v4i32 (vector_shuffle
1469 VR128:$src1, (undef),
1470 PSHUFD_shuffle_mask:$src2)))]>;
1471 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1472 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1473 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1474 [(set VR128:$dst, (v4i32 (vector_shuffle
1475 (bc_v4i32(loadv2i64 addr:$src1)),
1477 PSHUFD_shuffle_mask:$src2)))]>;
1479 // SSE2 with ImmT == Imm8 and XS prefix.
1480 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1481 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1482 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1483 [(set VR128:$dst, (v8i16 (vector_shuffle
1484 VR128:$src1, (undef),
1485 PSHUFHW_shuffle_mask:$src2)))]>,
1486 XS, Requires<[HasSSE2]>;
1487 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1488 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1489 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1490 [(set VR128:$dst, (v8i16 (vector_shuffle
1491 (bc_v8i16 (loadv2i64 addr:$src1)),
1493 PSHUFHW_shuffle_mask:$src2)))]>,
1494 XS, Requires<[HasSSE2]>;
1496 // SSE2 with ImmT == Imm8 and XD prefix.
1497 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1498 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1499 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1500 [(set VR128:$dst, (v8i16 (vector_shuffle
1501 VR128:$src1, (undef),
1502 PSHUFLW_shuffle_mask:$src2)))]>,
1503 XD, Requires<[HasSSE2]>;
1504 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1505 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1506 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1507 [(set VR128:$dst, (v8i16 (vector_shuffle
1508 (bc_v8i16 (loadv2i64 addr:$src1)),
1510 PSHUFLW_shuffle_mask:$src2)))]>,
1511 XD, Requires<[HasSSE2]>;
1513 let isTwoAddress = 1 in {
1514 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1515 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1516 "punpcklbw {$src2, $dst|$dst, $src2}",
1518 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1519 UNPCKL_shuffle_mask)))]>;
1520 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1521 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1522 "punpcklbw {$src2, $dst|$dst, $src2}",
1524 (v16i8 (vector_shuffle VR128:$src1,
1525 (bc_v16i8 (loadv2i64 addr:$src2)),
1526 UNPCKL_shuffle_mask)))]>;
1527 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1528 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1529 "punpcklwd {$src2, $dst|$dst, $src2}",
1531 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1532 UNPCKL_shuffle_mask)))]>;
1533 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1534 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1535 "punpcklwd {$src2, $dst|$dst, $src2}",
1537 (v8i16 (vector_shuffle VR128:$src1,
1538 (bc_v8i16 (loadv2i64 addr:$src2)),
1539 UNPCKL_shuffle_mask)))]>;
1540 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1541 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1542 "punpckldq {$src2, $dst|$dst, $src2}",
1544 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1545 UNPCKL_shuffle_mask)))]>;
1546 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1547 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1548 "punpckldq {$src2, $dst|$dst, $src2}",
1550 (v4i32 (vector_shuffle VR128:$src1,
1551 (bc_v4i32 (loadv2i64 addr:$src2)),
1552 UNPCKL_shuffle_mask)))]>;
1553 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1554 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1555 "punpcklqdq {$src2, $dst|$dst, $src2}",
1557 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1558 UNPCKL_shuffle_mask)))]>;
1559 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1560 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1561 "punpcklqdq {$src2, $dst|$dst, $src2}",
1563 (v2i64 (vector_shuffle VR128:$src1,
1564 (loadv2i64 addr:$src2),
1565 UNPCKL_shuffle_mask)))]>;
1567 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1568 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1569 "punpckhbw {$src2, $dst|$dst, $src2}",
1571 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1572 UNPCKH_shuffle_mask)))]>;
1573 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1574 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1575 "punpckhbw {$src2, $dst|$dst, $src2}",
1577 (v16i8 (vector_shuffle VR128:$src1,
1578 (bc_v16i8 (loadv2i64 addr:$src2)),
1579 UNPCKH_shuffle_mask)))]>;
1580 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1581 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1582 "punpckhwd {$src2, $dst|$dst, $src2}",
1584 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1585 UNPCKH_shuffle_mask)))]>;
1586 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1587 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1588 "punpckhwd {$src2, $dst|$dst, $src2}",
1590 (v8i16 (vector_shuffle VR128:$src1,
1591 (bc_v8i16 (loadv2i64 addr:$src2)),
1592 UNPCKH_shuffle_mask)))]>;
1593 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1594 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1595 "punpckhdq {$src2, $dst|$dst, $src2}",
1597 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1598 UNPCKH_shuffle_mask)))]>;
1599 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1600 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1601 "punpckhdq {$src2, $dst|$dst, $src2}",
1603 (v4i32 (vector_shuffle VR128:$src1,
1604 (bc_v4i32 (loadv2i64 addr:$src2)),
1605 UNPCKH_shuffle_mask)))]>;
1606 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1607 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1608 "punpckhqdq {$src2, $dst|$dst, $src2}",
1610 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1611 UNPCKH_shuffle_mask)))]>;
1612 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1613 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1614 "punpckhqdq {$src2, $dst|$dst, $src2}",
1616 (v2i64 (vector_shuffle VR128:$src1,
1617 (loadv2i64 addr:$src2),
1618 UNPCKH_shuffle_mask)))]>;
1622 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
1623 (ops GR32:$dst, VR128:$src1, i32i8imm:$src2),
1624 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1625 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
1626 (i32 imm:$src2)))]>;
1627 let isTwoAddress = 1 in {
1628 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
1629 (ops VR128:$dst, VR128:$src1, GR32:$src2, i32i8imm:$src3),
1630 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1631 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1632 GR32:$src2, (iPTR imm:$src3))))]>;
1633 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
1634 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
1635 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1637 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1638 (i32 (anyext (loadi16 addr:$src2))),
1639 (iPTR imm:$src3))))]>;
1642 //===----------------------------------------------------------------------===//
1643 // Miscellaneous Instructions
1644 //===----------------------------------------------------------------------===//
1647 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1648 "movmskps {$src, $dst|$dst, $src}",
1649 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1650 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1651 "movmskpd {$src, $dst|$dst, $src}",
1652 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1654 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1655 "pmovmskb {$src, $dst|$dst, $src}",
1656 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1658 // Conditional store
1659 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (ops VR128:$src, VR128:$mask),
1660 "maskmovdqu {$mask, $src|$src, $mask}",
1661 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1664 // Prefetching loads
1665 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
1666 "prefetcht0 $src", []>;
1667 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
1668 "prefetcht1 $src", []>;
1669 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
1670 "prefetcht2 $src", []>;
1671 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
1672 "prefetchtnta $src", []>;
1674 // Non-temporal stores
1675 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1676 "movntps {$src, $dst|$dst, $src}",
1677 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1678 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1679 "movntpd {$src, $dst|$dst, $src}",
1680 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1681 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1682 "movntdq {$src, $dst|$dst, $src}",
1683 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1684 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1685 "movnti {$src, $dst|$dst, $src}",
1686 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
1687 TB, Requires<[HasSSE2]>;
1690 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
1691 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
1692 TB, Requires<[HasSSE2]>;
1694 // Load, store, and memory fence
1695 def SFENCE : I<0xAE, MRM7m, (ops),
1696 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
1697 def LFENCE : I<0xAE, MRM5m, (ops),
1698 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
1699 def MFENCE : I<0xAE, MRM6m, (ops),
1700 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
1703 def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src),
1705 [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
1706 def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
1708 [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
1710 // Thread synchronization
1711 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
1712 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,
1713 TB, Requires<[HasSSE3]>;
1714 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
1715 [(int_x86_sse3_mwait ECX, EAX)]>,
1716 TB, Requires<[HasSSE3]>;
1718 //===----------------------------------------------------------------------===//
1719 // Alias Instructions
1720 //===----------------------------------------------------------------------===//
1722 // Alias instructions that map zero vector to pxor / xorp* for sse.
1723 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1724 def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
1726 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1728 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
1729 "pcmpeqd $dst, $dst",
1730 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
1732 // FR32 / FR64 to 128-bit vector conversion.
1733 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
1734 "movss {$src, $dst|$dst, $src}",
1736 (v4f32 (scalar_to_vector FR32:$src)))]>;
1737 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1738 "movss {$src, $dst|$dst, $src}",
1740 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1741 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
1742 "movsd {$src, $dst|$dst, $src}",
1744 (v2f64 (scalar_to_vector FR64:$src)))]>;
1745 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1746 "movsd {$src, $dst|$dst, $src}",
1748 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
1750 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1751 "movd {$src, $dst|$dst, $src}",
1753 (v4i32 (scalar_to_vector GR32:$src)))]>;
1754 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1755 "movd {$src, $dst|$dst, $src}",
1757 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
1758 // SSE2 instructions with XS prefix
1759 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
1760 "movq {$src, $dst|$dst, $src}",
1762 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
1763 Requires<[HasSSE2]>;
1764 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1765 "movq {$src, $dst|$dst, $src}",
1767 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
1768 Requires<[HasSSE2]>;
1769 // FIXME: may not be able to eliminate this movss with coalescing the src and
1770 // dest register classes are different. We really want to write this pattern
1772 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1773 // (f32 FR32:$src)>;
1774 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
1775 "movss {$src, $dst|$dst, $src}",
1776 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1778 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
1779 "movss {$src, $dst|$dst, $src}",
1780 [(store (f32 (vector_extract (v4f32 VR128:$src),
1781 (iPTR 0))), addr:$dst)]>;
1782 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
1783 "movsd {$src, $dst|$dst, $src}",
1784 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
1786 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1787 "movsd {$src, $dst|$dst, $src}",
1788 [(store (f64 (vector_extract (v2f64 VR128:$src),
1789 (iPTR 0))), addr:$dst)]>;
1790 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src),
1791 "movd {$src, $dst|$dst, $src}",
1792 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
1794 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
1795 "movd {$src, $dst|$dst, $src}",
1796 [(store (i32 (vector_extract (v4i32 VR128:$src),
1797 (iPTR 0))), addr:$dst)]>;
1799 // Move to lower bits of a VR128, leaving upper bits alone.
1800 // Three operand (but two address) aliases.
1801 let isTwoAddress = 1 in {
1802 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
1803 "movss {$src2, $dst|$dst, $src2}", []>;
1804 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
1805 "movsd {$src2, $dst|$dst, $src2}", []>;
1807 let AddedComplexity = 20 in {
1808 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1809 "movss {$src2, $dst|$dst, $src2}",
1811 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1812 MOVL_shuffle_mask)))]>;
1813 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1814 "movsd {$src2, $dst|$dst, $src2}",
1816 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
1817 MOVL_shuffle_mask)))]>;
1821 // Store / copy lower 64-bits of a XMM register.
1822 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1823 "movq {$src, $dst|$dst, $src}",
1824 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
1826 // Move to lower bits of a VR128 and zeroing upper bits.
1827 // Loading from memory automatically zeroing upper bits.
1828 let AddedComplexity = 20 in {
1829 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1830 "movss {$src, $dst|$dst, $src}",
1831 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
1832 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
1833 MOVL_shuffle_mask)))]>;
1834 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1835 "movsd {$src, $dst|$dst, $src}",
1836 [(set VR128:$dst, (v2f64 (vector_shuffle immAllZerosV,
1837 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
1838 MOVL_shuffle_mask)))]>;
1839 // movd / movq to XMM register zero-extends
1840 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1841 "movd {$src, $dst|$dst, $src}",
1842 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
1843 (v4i32 (scalar_to_vector GR32:$src)),
1844 MOVL_shuffle_mask)))]>;
1845 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1846 "movd {$src, $dst|$dst, $src}",
1847 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
1848 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
1849 MOVL_shuffle_mask)))]>;
1850 // Moving from XMM to XMM but still clear upper 64 bits.
1851 def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1852 "movq {$src, $dst|$dst, $src}",
1853 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
1854 XS, Requires<[HasSSE2]>;
1855 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1856 "movq {$src, $dst|$dst, $src}",
1857 [(set VR128:$dst, (int_x86_sse2_movl_dq
1858 (bitconvert (loadv2i64 addr:$src))))]>,
1859 XS, Requires<[HasSSE2]>;
1862 //===----------------------------------------------------------------------===//
1863 // Non-Instruction Patterns
1864 //===----------------------------------------------------------------------===//
1866 // 128-bit vector undef's.
1867 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1868 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1869 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1870 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1871 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1873 // 128-bit vector all zero's.
1874 def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1875 def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1876 def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1877 def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1878 def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1880 // 128-bit vector all one's.
1881 def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1882 def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1883 def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1884 def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1885 def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
1887 // Store 128-bit integer vector values.
1888 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1889 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1890 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1891 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1892 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1893 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1895 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
1897 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
1898 Requires<[HasSSE2]>;
1899 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
1900 Requires<[HasSSE2]>;
1903 let Predicates = [HasSSE2] in {
1904 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
1905 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
1906 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
1907 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
1908 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
1909 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
1910 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
1911 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
1912 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
1913 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
1914 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
1915 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
1916 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
1917 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
1918 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
1919 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
1920 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
1921 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
1922 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
1923 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
1924 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
1925 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
1926 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
1927 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
1928 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
1929 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
1930 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
1931 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
1932 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
1933 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
1936 // Move scalar to XMM zero-extended
1937 // movd to XMM register zero-extends
1938 let AddedComplexity = 20 in {
1939 def : Pat<(v8i16 (vector_shuffle immAllZerosV,
1940 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
1941 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
1942 def : Pat<(v16i8 (vector_shuffle immAllZerosV,
1943 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
1944 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
1945 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
1946 def : Pat<(v2f64 (vector_shuffle immAllZerosV,
1947 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
1948 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
1949 def : Pat<(v4f32 (vector_shuffle immAllZerosV,
1950 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
1951 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
1954 // Splat v2f64 / v2i64
1955 let AddedComplexity = 10 in {
1956 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
1957 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1958 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
1959 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1963 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
1964 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
1965 Requires<[HasSSE1]>;
1967 // Special unary SHUFPSrri case.
1968 // FIXME: when we want non two-address code, then we should use PSHUFD?
1969 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
1970 SHUFP_unary_shuffle_mask:$sm),
1971 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
1972 Requires<[HasSSE1]>;
1973 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
1974 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
1975 SHUFP_unary_shuffle_mask:$sm),
1976 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
1977 Requires<[HasSSE2]>;
1978 // Special binary v4i32 shuffle cases with SHUFPS.
1979 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
1980 PSHUFD_binary_shuffle_mask:$sm),
1981 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
1982 Requires<[HasSSE2]>;
1983 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
1984 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
1985 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
1986 Requires<[HasSSE2]>;
1988 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
1989 let AddedComplexity = 10 in {
1990 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
1991 UNPCKL_v_undef_shuffle_mask)),
1992 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1993 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
1994 UNPCKL_v_undef_shuffle_mask)),
1995 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1996 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
1997 UNPCKL_v_undef_shuffle_mask)),
1998 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1999 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2000 UNPCKL_v_undef_shuffle_mask)),
2001 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2004 let AddedComplexity = 20 in {
2005 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2006 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2007 MOVSHDUP_shuffle_mask)),
2008 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2009 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2010 MOVSHDUP_shuffle_mask)),
2011 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2013 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2014 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2015 MOVSLDUP_shuffle_mask)),
2016 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2017 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2018 MOVSLDUP_shuffle_mask)),
2019 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2022 let AddedComplexity = 20 in {
2023 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2024 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2025 MOVHP_shuffle_mask)),
2026 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2028 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2029 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2030 MOVHLPS_shuffle_mask)),
2031 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2033 // vector_shuffle v1, undef <2, 3, ?, ?> using MOVHLPS
2034 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2035 UNPCKH_shuffle_mask)),
2036 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2037 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2038 UNPCKH_shuffle_mask)),
2039 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2041 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2042 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2043 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2044 MOVLP_shuffle_mask)),
2045 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2046 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2047 MOVLP_shuffle_mask)),
2048 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2049 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2050 MOVHP_shuffle_mask)),
2051 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2052 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2053 MOVHP_shuffle_mask)),
2054 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2056 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2057 MOVLP_shuffle_mask)),
2058 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2059 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2060 MOVLP_shuffle_mask)),
2061 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2062 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2063 MOVHP_shuffle_mask)),
2064 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2065 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2066 MOVLP_shuffle_mask)),
2067 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2069 // Setting the lowest element in the vector.
2070 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2071 MOVL_shuffle_mask)),
2072 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2073 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2074 MOVL_shuffle_mask)),
2075 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2077 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2078 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2079 MOVLP_shuffle_mask)),
2080 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2081 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2082 MOVLP_shuffle_mask)),
2083 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2085 // Set lowest element and zero upper elements.
2086 def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2087 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2088 MOVL_shuffle_mask)),
2089 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2092 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2093 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2094 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2095 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2096 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2097 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2098 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2099 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2100 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2101 Requires<[HasSSE2]>;
2102 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2103 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2104 Requires<[HasSSE2]>;
2105 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2106 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2107 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2108 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2109 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2110 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2111 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2112 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2113 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2114 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2115 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2116 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2117 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2118 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2119 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2120 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2122 // 128-bit logical shifts
2123 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2124 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2125 Requires<[HasSSE2]>;
2126 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2127 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2128 Requires<[HasSSE2]>;
2130 // Some special case pandn patterns.
2131 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2133 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2134 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2136 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2137 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2139 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2141 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2142 (load addr:$src2))),
2143 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2144 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2145 (load addr:$src2))),
2146 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2147 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2148 (load addr:$src2))),
2149 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2152 def : Pat<(v4f32 (X86loadu addr:$src)), (MOVUPSrm addr:$src)>,
2153 Requires<[HasSSE1]>;