1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 def SSE_PMULLD_ITINS : OpndItins<
185 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
188 // Definitions for backward compatibility.
189 // The instructions mapped on these definitions uses a different itinerary
190 // than the actual scheduling model.
191 let Sched = WriteShuffle in
192 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
193 IIC_ALU_NONMEM, IIC_ALU_MEM
196 let Sched = WriteVecIMul in
197 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
198 IIC_ALU_NONMEM, IIC_ALU_MEM
201 let Sched = WriteShuffle in
202 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
203 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
206 let Sched = WriteMPSAD in
207 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
208 IIC_ALU_NONMEM, IIC_ALU_MEM
211 let Sched = WriteFBlend in
212 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
213 IIC_ALU_NONMEM, IIC_ALU_MEM
216 let Sched = WriteBlend in
217 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
218 IIC_ALU_NONMEM, IIC_ALU_MEM
221 let Sched = WriteFBlend in
222 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
223 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
226 //===----------------------------------------------------------------------===//
227 // SSE 1 & 2 Instructions Classes
228 //===----------------------------------------------------------------------===//
230 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
231 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
232 RegisterClass RC, X86MemOperand x86memop,
235 let isCommutable = 1 in {
236 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
238 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
239 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
240 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
241 Sched<[itins.Sched]>;
243 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
245 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
246 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
247 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
248 Sched<[itins.Sched.Folded, ReadAfterLd]>;
251 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
252 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
253 string asm, string SSEVer, string FPSizeStr,
254 Operand memopr, ComplexPattern mem_cpat,
257 let isCodeGenOnly = 1 in {
258 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
260 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
261 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
262 [(set RC:$dst, (!cast<Intrinsic>(
263 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
264 RC:$src1, RC:$src2))], itins.rr>,
265 Sched<[itins.Sched]>;
266 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
268 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
269 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
270 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
271 SSEVer, "_", OpcodeStr, FPSizeStr))
272 RC:$src1, mem_cpat:$src2))], itins.rm>,
273 Sched<[itins.Sched.Folded, ReadAfterLd]>;
277 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
278 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
279 RegisterClass RC, ValueType vt,
280 X86MemOperand x86memop, PatFrag mem_frag,
281 Domain d, OpndItins itins, bit Is2Addr = 1> {
282 let isCommutable = 1 in
283 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
285 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
286 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
287 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
288 Sched<[itins.Sched]>;
290 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
292 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
293 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
294 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
296 Sched<[itins.Sched.Folded, ReadAfterLd]>;
299 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
300 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
301 string OpcodeStr, X86MemOperand x86memop,
302 list<dag> pat_rr, list<dag> pat_rm,
304 let isCommutable = 1, hasSideEffects = 0 in
305 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
307 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
308 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
309 pat_rr, NoItinerary, d>,
310 Sched<[WriteVecLogic]>;
311 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
313 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
314 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
315 pat_rm, NoItinerary, d>,
316 Sched<[WriteVecLogicLd, ReadAfterLd]>;
319 //===----------------------------------------------------------------------===//
320 // Non-instruction patterns
321 //===----------------------------------------------------------------------===//
323 // A vector extract of the first f32/f64 position is a subregister copy
324 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
325 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
326 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
327 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
329 // A 128-bit subvector extract from the first 256-bit vector position
330 // is a subregister copy that needs no instruction.
331 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
332 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
333 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
334 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
336 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
337 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
338 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
339 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
341 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
342 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
343 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
344 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
346 // A 128-bit subvector insert to the first 256-bit vector position
347 // is a subregister copy that needs no instruction.
348 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
349 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
350 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
351 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
352 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
353 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
354 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
355 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
356 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
357 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
358 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
359 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
360 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
363 // Implicitly promote a 32-bit scalar to a vector.
364 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
365 (COPY_TO_REGCLASS FR32:$src, VR128)>;
366 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
367 (COPY_TO_REGCLASS FR32:$src, VR128)>;
368 // Implicitly promote a 64-bit scalar to a vector.
369 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
370 (COPY_TO_REGCLASS FR64:$src, VR128)>;
371 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
372 (COPY_TO_REGCLASS FR64:$src, VR128)>;
374 // Bitcasts between 128-bit vector types. Return the original type since
375 // no instruction is needed for the conversion
376 let Predicates = [HasSSE2] in {
377 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
378 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
379 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
380 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
381 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
382 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
383 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
384 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
385 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
386 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
387 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
388 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
389 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
390 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
391 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
392 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
393 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
394 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
395 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
396 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
397 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
398 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
399 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
400 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
401 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
402 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
403 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
404 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
405 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
406 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
409 // Bitcasts between 256-bit vector types. Return the original type since
410 // no instruction is needed for the conversion
411 let Predicates = [HasAVX] in {
412 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
413 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
414 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
415 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
416 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
417 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
418 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
419 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
420 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
421 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
422 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
423 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
424 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
425 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
426 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
427 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
428 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
429 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
430 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
431 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
432 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
433 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
434 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
435 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
436 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
437 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
438 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
439 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
440 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
441 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
444 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
445 // This is expanded by ExpandPostRAPseudos.
446 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
447 isPseudo = 1, SchedRW = [WriteZero] in {
448 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
449 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
450 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
451 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
454 //===----------------------------------------------------------------------===//
455 // AVX & SSE - Zero/One Vectors
456 //===----------------------------------------------------------------------===//
458 // Alias instruction that maps zero vector to pxor / xorp* for sse.
459 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
460 // swizzled by ExecutionDepsFix to pxor.
461 // We set canFoldAsLoad because this can be converted to a constant-pool
462 // load of an all-zeros value if folding it would be beneficial.
463 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
464 isPseudo = 1, SchedRW = [WriteZero] in {
465 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
466 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
469 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
470 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
471 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
472 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
473 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
476 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
477 // and doesn't need it because on sandy bridge the register is set to zero
478 // at the rename stage without using any execution unit, so SET0PSY
479 // and SET0PDY can be used for vector int instructions without penalty
480 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
481 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
482 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
483 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
486 let Predicates = [HasAVX] in
487 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
489 let Predicates = [HasAVX2] in {
490 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
491 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
492 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
493 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
496 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
497 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
498 let Predicates = [HasAVX1Only] in {
499 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
500 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
501 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
503 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
504 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
505 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
507 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
508 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
509 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
511 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
512 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
513 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
516 // We set canFoldAsLoad because this can be converted to a constant-pool
517 // load of an all-ones value if folding it would be beneficial.
518 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
519 isPseudo = 1, SchedRW = [WriteZero] in {
520 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
521 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
522 let Predicates = [HasAVX2] in
523 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
524 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
528 //===----------------------------------------------------------------------===//
529 // SSE 1 & 2 - Move FP Scalar Instructions
531 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
532 // register copies because it's a partial register update; Register-to-register
533 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
534 // that the insert be implementable in terms of a copy, and just mentioned, we
535 // don't use movss/movsd for copies.
536 //===----------------------------------------------------------------------===//
538 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
539 X86MemOperand x86memop, string base_opc,
541 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
542 (ins VR128:$src1, RC:$src2),
543 !strconcat(base_opc, asm_opr),
544 [(set VR128:$dst, (vt (OpNode VR128:$src1,
545 (scalar_to_vector RC:$src2))))],
546 IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
548 // For the disassembler
549 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
550 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
551 (ins VR128:$src1, RC:$src2),
552 !strconcat(base_opc, asm_opr),
553 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
556 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
557 X86MemOperand x86memop, string OpcodeStr> {
559 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
563 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
564 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
565 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
566 VEX, VEX_LIG, Sched<[WriteStore]>;
568 let Constraints = "$src1 = $dst" in {
569 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
570 "\t{$src2, $dst|$dst, $src2}">;
573 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
575 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
579 // Loading from memory automatically zeroing upper bits.
580 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
581 PatFrag mem_pat, string OpcodeStr> {
582 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
583 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
584 [(set RC:$dst, (mem_pat addr:$src))],
585 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
586 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
587 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
588 [(set RC:$dst, (mem_pat addr:$src))],
589 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
592 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
593 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
595 let canFoldAsLoad = 1, isReMaterializable = 1 in {
596 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
598 let AddedComplexity = 20 in
599 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
603 let Predicates = [UseAVX] in {
604 let AddedComplexity = 15 in {
605 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
606 // MOVS{S,D} to the lower bits.
607 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
608 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
609 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
610 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
611 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
612 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
613 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
614 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
616 // Move low f32 and clear high bits.
617 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
618 (SUBREG_TO_REG (i32 0),
619 (VMOVSSrr (v4f32 (V_SET0)),
620 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
621 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
622 (SUBREG_TO_REG (i32 0),
623 (VMOVSSrr (v4i32 (V_SET0)),
624 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
627 let AddedComplexity = 20 in {
628 // MOVSSrm zeros the high parts of the register; represent this
629 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
630 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
631 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
632 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
633 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
634 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
635 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
637 // MOVSDrm zeros the high parts of the register; represent this
638 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
639 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
641 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
642 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
643 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
644 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
645 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
646 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
647 def : Pat<(v2f64 (X86vzload addr:$src)),
648 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
650 // Represent the same patterns above but in the form they appear for
652 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
653 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
654 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
655 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
656 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
657 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
658 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
659 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
660 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
662 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
663 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
664 (SUBREG_TO_REG (i32 0),
665 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
667 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
668 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
669 (SUBREG_TO_REG (i64 0),
670 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
672 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
673 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
674 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
676 // Move low f64 and clear high bits.
677 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
678 (SUBREG_TO_REG (i32 0),
679 (VMOVSDrr (v2f64 (V_SET0)),
680 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
682 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
683 (SUBREG_TO_REG (i32 0),
684 (VMOVSDrr (v2i64 (V_SET0)),
685 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
687 // Extract and store.
688 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
690 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
691 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
693 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
695 // Shuffle with VMOVSS
696 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
697 (VMOVSSrr (v4i32 VR128:$src1),
698 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
699 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
700 (VMOVSSrr (v4f32 VR128:$src1),
701 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
704 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
705 (SUBREG_TO_REG (i32 0),
706 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
707 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
709 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
710 (SUBREG_TO_REG (i32 0),
711 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
712 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
715 // Shuffle with VMOVSD
716 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
717 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
718 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
719 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
720 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
721 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
722 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
723 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
726 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
727 (SUBREG_TO_REG (i32 0),
728 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
729 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
731 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
732 (SUBREG_TO_REG (i32 0),
733 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
734 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
738 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
739 // is during lowering, where it's not possible to recognize the fold cause
740 // it has two uses through a bitcast. One use disappears at isel time and the
741 // fold opportunity reappears.
742 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
743 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
744 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
745 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
746 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
747 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
748 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
749 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
752 let Predicates = [UseSSE1] in {
753 let AddedComplexity = 15 in {
754 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
755 // MOVSS to the lower bits.
756 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
757 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
758 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
759 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
760 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
761 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
764 let AddedComplexity = 20 in {
765 // MOVSSrm already zeros the high parts of the register.
766 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
767 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
768 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
769 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
770 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
771 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
774 // Extract and store.
775 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
777 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
779 // Shuffle with MOVSS
780 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
781 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
782 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
783 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
786 let Predicates = [UseSSE2] in {
787 let AddedComplexity = 15 in {
788 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
789 // MOVSD to the lower bits.
790 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
791 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
794 let AddedComplexity = 20 in {
795 // MOVSDrm already zeros the high parts of the register.
796 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
797 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
798 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
799 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
800 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
801 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
802 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
803 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
804 def : Pat<(v2f64 (X86vzload addr:$src)),
805 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
808 // Extract and store.
809 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
811 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
813 // Shuffle with MOVSD
814 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
815 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
816 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
817 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
818 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
819 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
820 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
821 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
823 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
824 // is during lowering, where it's not possible to recognize the fold cause
825 // it has two uses through a bitcast. One use disappears at isel time and the
826 // fold opportunity reappears.
827 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
828 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
829 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
830 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
831 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
832 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
833 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
834 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
837 //===----------------------------------------------------------------------===//
838 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
839 //===----------------------------------------------------------------------===//
841 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
842 X86MemOperand x86memop, PatFrag ld_frag,
843 string asm, Domain d,
845 bit IsReMaterializable = 1> {
846 let neverHasSideEffects = 1 in
847 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
848 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
849 Sched<[WriteFShuffle]>;
850 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
851 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
852 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
853 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
857 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
858 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
860 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
861 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
863 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
864 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
866 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
867 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
870 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
871 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
873 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
874 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
876 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
877 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
879 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
880 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
882 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
883 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
885 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
886 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
888 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
889 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
891 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
892 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
895 let SchedRW = [WriteStore] in {
896 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
897 "movaps\t{$src, $dst|$dst, $src}",
898 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
899 IIC_SSE_MOVA_P_MR>, VEX;
900 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
901 "movapd\t{$src, $dst|$dst, $src}",
902 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
903 IIC_SSE_MOVA_P_MR>, VEX;
904 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
905 "movups\t{$src, $dst|$dst, $src}",
906 [(store (v4f32 VR128:$src), addr:$dst)],
907 IIC_SSE_MOVU_P_MR>, VEX;
908 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
909 "movupd\t{$src, $dst|$dst, $src}",
910 [(store (v2f64 VR128:$src), addr:$dst)],
911 IIC_SSE_MOVU_P_MR>, VEX;
912 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
913 "movaps\t{$src, $dst|$dst, $src}",
914 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
915 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
916 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
917 "movapd\t{$src, $dst|$dst, $src}",
918 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
919 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
920 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
921 "movups\t{$src, $dst|$dst, $src}",
922 [(store (v8f32 VR256:$src), addr:$dst)],
923 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
924 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
925 "movupd\t{$src, $dst|$dst, $src}",
926 [(store (v4f64 VR256:$src), addr:$dst)],
927 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
931 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
932 SchedRW = [WriteFShuffle] in {
933 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
935 "movaps\t{$src, $dst|$dst, $src}", [],
936 IIC_SSE_MOVA_P_RR>, VEX;
937 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
939 "movapd\t{$src, $dst|$dst, $src}", [],
940 IIC_SSE_MOVA_P_RR>, VEX;
941 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
943 "movups\t{$src, $dst|$dst, $src}", [],
944 IIC_SSE_MOVU_P_RR>, VEX;
945 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
947 "movupd\t{$src, $dst|$dst, $src}", [],
948 IIC_SSE_MOVU_P_RR>, VEX;
949 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
951 "movaps\t{$src, $dst|$dst, $src}", [],
952 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
953 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
955 "movapd\t{$src, $dst|$dst, $src}", [],
956 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
957 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
959 "movups\t{$src, $dst|$dst, $src}", [],
960 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
961 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
963 "movupd\t{$src, $dst|$dst, $src}", [],
964 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
967 let Predicates = [HasAVX] in {
968 def : Pat<(v8i32 (X86vzmovl
969 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
970 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
971 def : Pat<(v4i64 (X86vzmovl
972 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
973 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
974 def : Pat<(v8f32 (X86vzmovl
975 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
976 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
977 def : Pat<(v4f64 (X86vzmovl
978 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
979 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
983 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
984 (VMOVUPSYmr addr:$dst, VR256:$src)>;
985 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
986 (VMOVUPDYmr addr:$dst, VR256:$src)>;
988 let SchedRW = [WriteStore] in {
989 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
990 "movaps\t{$src, $dst|$dst, $src}",
991 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
993 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
994 "movapd\t{$src, $dst|$dst, $src}",
995 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
997 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
998 "movups\t{$src, $dst|$dst, $src}",
999 [(store (v4f32 VR128:$src), addr:$dst)],
1001 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1002 "movupd\t{$src, $dst|$dst, $src}",
1003 [(store (v2f64 VR128:$src), addr:$dst)],
1008 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1009 SchedRW = [WriteMove] in {
1010 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1011 "movaps\t{$src, $dst|$dst, $src}", [],
1013 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1014 "movapd\t{$src, $dst|$dst, $src}", [],
1016 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1017 "movups\t{$src, $dst|$dst, $src}", [],
1019 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1020 "movupd\t{$src, $dst|$dst, $src}", [],
1024 let Predicates = [HasAVX] in {
1025 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1028 (VMOVUPDmr addr:$dst, VR128:$src)>;
1031 let Predicates = [UseSSE1] in
1032 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1033 (MOVUPSmr addr:$dst, VR128:$src)>;
1034 let Predicates = [UseSSE2] in
1035 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1036 (MOVUPDmr addr:$dst, VR128:$src)>;
1038 // Use vmovaps/vmovups for AVX integer load/store.
1039 let Predicates = [HasAVX] in {
1040 // 128-bit load/store
1041 def : Pat<(alignedloadv2i64 addr:$src),
1042 (VMOVAPSrm addr:$src)>;
1043 def : Pat<(loadv2i64 addr:$src),
1044 (VMOVUPSrm addr:$src)>;
1046 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1047 (VMOVAPSmr addr:$dst, VR128:$src)>;
1048 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1049 (VMOVAPSmr addr:$dst, VR128:$src)>;
1050 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1051 (VMOVAPSmr addr:$dst, VR128:$src)>;
1052 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1053 (VMOVAPSmr addr:$dst, VR128:$src)>;
1054 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1055 (VMOVUPSmr addr:$dst, VR128:$src)>;
1056 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1057 (VMOVUPSmr addr:$dst, VR128:$src)>;
1058 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1059 (VMOVUPSmr addr:$dst, VR128:$src)>;
1060 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1061 (VMOVUPSmr addr:$dst, VR128:$src)>;
1063 // 256-bit load/store
1064 def : Pat<(alignedloadv4i64 addr:$src),
1065 (VMOVAPSYrm addr:$src)>;
1066 def : Pat<(loadv4i64 addr:$src),
1067 (VMOVUPSYrm addr:$src)>;
1068 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1069 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1070 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1071 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1072 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1073 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1074 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1075 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1076 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1077 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1078 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1079 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1080 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1081 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1082 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1083 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1085 // Special patterns for storing subvector extracts of lower 128-bits
1086 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1087 def : Pat<(alignedstore (v2f64 (extract_subvector
1088 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1089 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1090 def : Pat<(alignedstore (v4f32 (extract_subvector
1091 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1092 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1093 def : Pat<(alignedstore (v2i64 (extract_subvector
1094 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1095 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1096 def : Pat<(alignedstore (v4i32 (extract_subvector
1097 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1098 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1099 def : Pat<(alignedstore (v8i16 (extract_subvector
1100 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1101 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1102 def : Pat<(alignedstore (v16i8 (extract_subvector
1103 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1104 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1106 def : Pat<(store (v2f64 (extract_subvector
1107 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1108 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1109 def : Pat<(store (v4f32 (extract_subvector
1110 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1111 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1112 def : Pat<(store (v2i64 (extract_subvector
1113 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1114 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1115 def : Pat<(store (v4i32 (extract_subvector
1116 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1117 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1118 def : Pat<(store (v8i16 (extract_subvector
1119 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1120 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1121 def : Pat<(store (v16i8 (extract_subvector
1122 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1123 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1126 // Use movaps / movups for SSE integer load / store (one byte shorter).
1127 // The instructions selected below are then converted to MOVDQA/MOVDQU
1128 // during the SSE domain pass.
1129 let Predicates = [UseSSE1] in {
1130 def : Pat<(alignedloadv2i64 addr:$src),
1131 (MOVAPSrm addr:$src)>;
1132 def : Pat<(loadv2i64 addr:$src),
1133 (MOVUPSrm addr:$src)>;
1135 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1136 (MOVAPSmr addr:$dst, VR128:$src)>;
1137 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1138 (MOVAPSmr addr:$dst, VR128:$src)>;
1139 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1140 (MOVAPSmr addr:$dst, VR128:$src)>;
1141 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1142 (MOVAPSmr addr:$dst, VR128:$src)>;
1143 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1144 (MOVUPSmr addr:$dst, VR128:$src)>;
1145 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1146 (MOVUPSmr addr:$dst, VR128:$src)>;
1147 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1148 (MOVUPSmr addr:$dst, VR128:$src)>;
1149 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1150 (MOVUPSmr addr:$dst, VR128:$src)>;
1153 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1154 // bits are disregarded. FIXME: Set encoding to pseudo!
1155 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1156 let isCodeGenOnly = 1 in {
1157 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1158 "movaps\t{$src, $dst|$dst, $src}",
1159 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1160 IIC_SSE_MOVA_P_RM>, VEX;
1161 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1162 "movapd\t{$src, $dst|$dst, $src}",
1163 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1164 IIC_SSE_MOVA_P_RM>, VEX;
1165 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1166 "movaps\t{$src, $dst|$dst, $src}",
1167 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1169 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1170 "movapd\t{$src, $dst|$dst, $src}",
1171 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1176 //===----------------------------------------------------------------------===//
1177 // SSE 1 & 2 - Move Low packed FP Instructions
1178 //===----------------------------------------------------------------------===//
1180 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1181 string base_opc, string asm_opr,
1182 InstrItinClass itin> {
1183 def PSrm : PI<opc, MRMSrcMem,
1184 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1185 !strconcat(base_opc, "s", asm_opr),
1187 (psnode VR128:$src1,
1188 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1189 itin, SSEPackedSingle>, PS,
1190 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1192 def PDrm : PI<opc, MRMSrcMem,
1193 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1194 !strconcat(base_opc, "d", asm_opr),
1195 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1196 (scalar_to_vector (loadf64 addr:$src2)))))],
1197 itin, SSEPackedDouble>, PD,
1198 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1202 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1203 string base_opc, InstrItinClass itin> {
1204 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1205 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1208 let Constraints = "$src1 = $dst" in
1209 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1210 "\t{$src2, $dst|$dst, $src2}",
1214 let AddedComplexity = 20 in {
1215 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1219 let SchedRW = [WriteStore] in {
1220 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1221 "movlps\t{$src, $dst|$dst, $src}",
1222 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1223 (iPTR 0))), addr:$dst)],
1224 IIC_SSE_MOV_LH>, VEX;
1225 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1226 "movlpd\t{$src, $dst|$dst, $src}",
1227 [(store (f64 (vector_extract (v2f64 VR128:$src),
1228 (iPTR 0))), addr:$dst)],
1229 IIC_SSE_MOV_LH>, VEX;
1230 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1231 "movlps\t{$src, $dst|$dst, $src}",
1232 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1233 (iPTR 0))), addr:$dst)],
1235 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1236 "movlpd\t{$src, $dst|$dst, $src}",
1237 [(store (f64 (vector_extract (v2f64 VR128:$src),
1238 (iPTR 0))), addr:$dst)],
1242 let Predicates = [HasAVX] in {
1243 // Shuffle with VMOVLPS
1244 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1245 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1246 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1247 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1249 // Shuffle with VMOVLPD
1250 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1251 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1252 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1253 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1256 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1258 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1259 def : Pat<(store (v4i32 (X86Movlps
1260 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1261 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1262 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1264 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1265 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1267 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1270 let Predicates = [UseSSE1] in {
1271 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1272 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1273 (iPTR 0))), addr:$src1),
1274 (MOVLPSmr addr:$src1, VR128:$src2)>;
1276 // Shuffle with MOVLPS
1277 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1278 (MOVLPSrm VR128:$src1, addr:$src2)>;
1279 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1280 (MOVLPSrm VR128:$src1, addr:$src2)>;
1281 def : Pat<(X86Movlps VR128:$src1,
1282 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1283 (MOVLPSrm VR128:$src1, addr:$src2)>;
1286 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1288 (MOVLPSmr addr:$src1, VR128:$src2)>;
1289 def : Pat<(store (v4i32 (X86Movlps
1290 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1292 (MOVLPSmr addr:$src1, VR128:$src2)>;
1295 let Predicates = [UseSSE2] in {
1296 // Shuffle with MOVLPD
1297 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1298 (MOVLPDrm VR128:$src1, addr:$src2)>;
1299 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1300 (MOVLPDrm VR128:$src1, addr:$src2)>;
1303 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1305 (MOVLPDmr addr:$src1, VR128:$src2)>;
1306 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1308 (MOVLPDmr addr:$src1, VR128:$src2)>;
1311 //===----------------------------------------------------------------------===//
1312 // SSE 1 & 2 - Move Hi packed FP Instructions
1313 //===----------------------------------------------------------------------===//
1315 let AddedComplexity = 20 in {
1316 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1320 let SchedRW = [WriteStore] in {
1321 // v2f64 extract element 1 is always custom lowered to unpack high to low
1322 // and extract element 0 so the non-store version isn't too horrible.
1323 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1324 "movhps\t{$src, $dst|$dst, $src}",
1325 [(store (f64 (vector_extract
1326 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1327 (bc_v2f64 (v4f32 VR128:$src))),
1328 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1329 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1330 "movhpd\t{$src, $dst|$dst, $src}",
1331 [(store (f64 (vector_extract
1332 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1333 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1334 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1335 "movhps\t{$src, $dst|$dst, $src}",
1336 [(store (f64 (vector_extract
1337 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1338 (bc_v2f64 (v4f32 VR128:$src))),
1339 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1340 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1341 "movhpd\t{$src, $dst|$dst, $src}",
1342 [(store (f64 (vector_extract
1343 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1344 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1347 let Predicates = [HasAVX] in {
1349 def : Pat<(X86Movlhps VR128:$src1,
1350 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1351 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1352 def : Pat<(X86Movlhps VR128:$src1,
1353 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1354 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1356 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1357 // is during lowering, where it's not possible to recognize the load fold
1358 // cause it has two uses through a bitcast. One use disappears at isel time
1359 // and the fold opportunity reappears.
1360 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1361 (scalar_to_vector (loadf64 addr:$src2)))),
1362 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1365 let Predicates = [UseSSE1] in {
1367 def : Pat<(X86Movlhps VR128:$src1,
1368 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1369 (MOVHPSrm VR128:$src1, addr:$src2)>;
1370 def : Pat<(X86Movlhps VR128:$src1,
1371 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1372 (MOVHPSrm VR128:$src1, addr:$src2)>;
1375 let Predicates = [UseSSE2] in {
1376 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1377 // is during lowering, where it's not possible to recognize the load fold
1378 // cause it has two uses through a bitcast. One use disappears at isel time
1379 // and the fold opportunity reappears.
1380 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1381 (scalar_to_vector (loadf64 addr:$src2)))),
1382 (MOVHPDrm VR128:$src1, addr:$src2)>;
1385 //===----------------------------------------------------------------------===//
1386 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1387 //===----------------------------------------------------------------------===//
1389 let AddedComplexity = 20, Predicates = [UseAVX] in {
1390 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1391 (ins VR128:$src1, VR128:$src2),
1392 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1394 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1396 VEX_4V, Sched<[WriteFShuffle]>;
1397 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1398 (ins VR128:$src1, VR128:$src2),
1399 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1401 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1403 VEX_4V, Sched<[WriteFShuffle]>;
1405 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1406 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1407 (ins VR128:$src1, VR128:$src2),
1408 "movlhps\t{$src2, $dst|$dst, $src2}",
1410 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1411 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1412 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1413 (ins VR128:$src1, VR128:$src2),
1414 "movhlps\t{$src2, $dst|$dst, $src2}",
1416 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1417 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1420 let Predicates = [UseAVX] in {
1422 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1423 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1424 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1425 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1428 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1429 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1432 let Predicates = [UseSSE1] in {
1434 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1435 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1436 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1437 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1440 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1441 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1444 //===----------------------------------------------------------------------===//
1445 // SSE 1 & 2 - Conversion Instructions
1446 //===----------------------------------------------------------------------===//
1448 def SSE_CVT_PD : OpndItins<
1449 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1452 let Sched = WriteCvtI2F in
1453 def SSE_CVT_PS : OpndItins<
1454 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1457 let Sched = WriteCvtI2F in
1458 def SSE_CVT_Scalar : OpndItins<
1459 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1462 let Sched = WriteCvtF2I in
1463 def SSE_CVT_SS2SI_32 : OpndItins<
1464 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1467 let Sched = WriteCvtF2I in
1468 def SSE_CVT_SS2SI_64 : OpndItins<
1469 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1472 let Sched = WriteCvtF2I in
1473 def SSE_CVT_SD2SI : OpndItins<
1474 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1477 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1478 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1479 string asm, OpndItins itins> {
1480 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1481 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1482 itins.rr>, Sched<[itins.Sched]>;
1483 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1484 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1485 itins.rm>, Sched<[itins.Sched.Folded]>;
1488 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1489 X86MemOperand x86memop, string asm, Domain d,
1491 let neverHasSideEffects = 1 in {
1492 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1493 [], itins.rr, d>, Sched<[itins.Sched]>;
1495 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1496 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1500 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1501 X86MemOperand x86memop, string asm> {
1502 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1503 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1504 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1505 Sched<[WriteCvtI2F]>;
1507 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1508 (ins DstRC:$src1, x86memop:$src),
1509 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1510 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1511 } // neverHasSideEffects = 1
1514 let Predicates = [UseAVX] in {
1515 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1516 "cvttss2si\t{$src, $dst|$dst, $src}",
1519 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1520 "cvttss2si\t{$src, $dst|$dst, $src}",
1522 XS, VEX, VEX_W, VEX_LIG;
1523 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1524 "cvttsd2si\t{$src, $dst|$dst, $src}",
1527 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1528 "cvttsd2si\t{$src, $dst|$dst, $src}",
1530 XD, VEX, VEX_W, VEX_LIG;
1532 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1533 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1534 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1535 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1536 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1537 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1538 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1539 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1540 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1541 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1542 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1543 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1544 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1545 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1546 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1547 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1549 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1550 // register, but the same isn't true when only using memory operands,
1551 // provide other assembly "l" and "q" forms to address this explicitly
1552 // where appropriate to do so.
1553 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1554 XS, VEX_4V, VEX_LIG;
1555 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1556 XS, VEX_4V, VEX_W, VEX_LIG;
1557 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1558 XD, VEX_4V, VEX_LIG;
1559 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1560 XD, VEX_4V, VEX_W, VEX_LIG;
1562 let Predicates = [UseAVX] in {
1563 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1564 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1565 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1566 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1568 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1569 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1570 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1571 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1572 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1573 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1574 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1575 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1577 def : Pat<(f32 (sint_to_fp GR32:$src)),
1578 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1579 def : Pat<(f32 (sint_to_fp GR64:$src)),
1580 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1581 def : Pat<(f64 (sint_to_fp GR32:$src)),
1582 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1583 def : Pat<(f64 (sint_to_fp GR64:$src)),
1584 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1587 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1588 "cvttss2si\t{$src, $dst|$dst, $src}",
1589 SSE_CVT_SS2SI_32>, XS;
1590 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1591 "cvttss2si\t{$src, $dst|$dst, $src}",
1592 SSE_CVT_SS2SI_64>, XS, REX_W;
1593 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1594 "cvttsd2si\t{$src, $dst|$dst, $src}",
1596 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1597 "cvttsd2si\t{$src, $dst|$dst, $src}",
1598 SSE_CVT_SD2SI>, XD, REX_W;
1599 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1600 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1601 SSE_CVT_Scalar>, XS;
1602 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1603 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1604 SSE_CVT_Scalar>, XS, REX_W;
1605 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1606 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1607 SSE_CVT_Scalar>, XD;
1608 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1609 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1610 SSE_CVT_Scalar>, XD, REX_W;
1612 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1613 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1614 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1615 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1616 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1617 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1618 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1619 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1620 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1621 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1622 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1623 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1624 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1625 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1626 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1627 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1629 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1630 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1631 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1632 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1634 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1635 // and/or XMM operand(s).
1637 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1638 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1639 string asm, OpndItins itins> {
1640 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1641 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1642 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1643 Sched<[itins.Sched]>;
1644 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1645 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1646 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1647 Sched<[itins.Sched.Folded]>;
1650 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1651 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1652 PatFrag ld_frag, string asm, OpndItins itins,
1654 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1656 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1657 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1658 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1659 itins.rr>, Sched<[itins.Sched]>;
1660 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1661 (ins DstRC:$src1, x86memop:$src2),
1663 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1664 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1665 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1666 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1669 let Predicates = [UseAVX] in {
1670 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1671 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1672 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1673 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1674 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1675 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1677 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1678 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1679 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1680 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1683 let isCodeGenOnly = 1 in {
1684 let Predicates = [UseAVX] in {
1685 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1686 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1687 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1688 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1689 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1690 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1692 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1693 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1694 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1695 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1696 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1697 SSE_CVT_Scalar, 0>, XD,
1700 let Constraints = "$src1 = $dst" in {
1701 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1702 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1703 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1704 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1705 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1706 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1707 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1708 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1709 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1710 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1711 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1712 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1714 } // isCodeGenOnly = 1
1718 // Aliases for intrinsics
1719 let isCodeGenOnly = 1 in {
1720 let Predicates = [UseAVX] in {
1721 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1722 ssmem, sse_load_f32, "cvttss2si",
1723 SSE_CVT_SS2SI_32>, XS, VEX;
1724 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1725 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1726 "cvttss2si", SSE_CVT_SS2SI_64>,
1728 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1729 sdmem, sse_load_f64, "cvttsd2si",
1730 SSE_CVT_SD2SI>, XD, VEX;
1731 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1732 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1733 "cvttsd2si", SSE_CVT_SD2SI>,
1736 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1737 ssmem, sse_load_f32, "cvttss2si",
1738 SSE_CVT_SS2SI_32>, XS;
1739 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1740 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1741 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1742 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1743 sdmem, sse_load_f64, "cvttsd2si",
1745 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1746 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1747 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1748 } // isCodeGenOnly = 1
1750 let Predicates = [UseAVX] in {
1751 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1752 ssmem, sse_load_f32, "cvtss2si",
1753 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1754 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1755 ssmem, sse_load_f32, "cvtss2si",
1756 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1758 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1759 ssmem, sse_load_f32, "cvtss2si",
1760 SSE_CVT_SS2SI_32>, XS;
1761 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1762 ssmem, sse_load_f32, "cvtss2si",
1763 SSE_CVT_SS2SI_64>, XS, REX_W;
1765 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1766 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1767 SSEPackedSingle, SSE_CVT_PS>,
1768 PS, VEX, Requires<[HasAVX]>;
1769 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1770 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1771 SSEPackedSingle, SSE_CVT_PS>,
1772 PS, VEX, VEX_L, Requires<[HasAVX]>;
1774 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1775 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1776 SSEPackedSingle, SSE_CVT_PS>,
1777 PS, Requires<[UseSSE2]>;
1779 let Predicates = [UseAVX] in {
1780 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1781 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1782 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1783 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1784 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1785 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1786 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1787 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1788 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1789 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1790 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1791 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1792 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1793 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1794 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1795 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1798 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1799 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1800 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1801 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1802 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1803 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1804 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1805 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1806 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1807 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1808 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1809 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1810 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1811 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1812 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1813 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1817 // Convert scalar double to scalar single
1818 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1819 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1820 (ins FR64:$src1, FR64:$src2),
1821 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1822 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1823 Sched<[WriteCvtF2F]>;
1825 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1826 (ins FR64:$src1, f64mem:$src2),
1827 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1828 [], IIC_SSE_CVT_Scalar_RM>,
1829 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1830 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1833 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1836 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1837 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1838 [(set FR32:$dst, (fround FR64:$src))],
1839 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1840 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1841 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1842 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1843 IIC_SSE_CVT_Scalar_RM>,
1845 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1847 let isCodeGenOnly = 1 in {
1848 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1849 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1850 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1852 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1853 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1854 Sched<[WriteCvtF2F]>;
1855 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1856 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1857 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1858 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1859 VR128:$src1, sse_load_f64:$src2))],
1860 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1861 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1863 let Constraints = "$src1 = $dst" in {
1864 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1865 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1866 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1868 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1869 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1870 Sched<[WriteCvtF2F]>;
1871 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1872 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1873 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1874 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1875 VR128:$src1, sse_load_f64:$src2))],
1876 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1877 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1879 } // isCodeGenOnly = 1
1881 // Convert scalar single to scalar double
1882 // SSE2 instructions with XS prefix
1883 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1884 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1885 (ins FR32:$src1, FR32:$src2),
1886 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1887 [], IIC_SSE_CVT_Scalar_RR>,
1888 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1889 Sched<[WriteCvtF2F]>;
1891 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1892 (ins FR32:$src1, f32mem:$src2),
1893 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1894 [], IIC_SSE_CVT_Scalar_RM>,
1895 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1896 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1899 def : Pat<(f64 (fextend FR32:$src)),
1900 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1901 def : Pat<(fextend (loadf32 addr:$src)),
1902 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1904 def : Pat<(extloadf32 addr:$src),
1905 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1906 Requires<[UseAVX, OptForSize]>;
1907 def : Pat<(extloadf32 addr:$src),
1908 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1909 Requires<[UseAVX, OptForSpeed]>;
1911 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1912 "cvtss2sd\t{$src, $dst|$dst, $src}",
1913 [(set FR64:$dst, (fextend FR32:$src))],
1914 IIC_SSE_CVT_Scalar_RR>, XS,
1915 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1916 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1917 "cvtss2sd\t{$src, $dst|$dst, $src}",
1918 [(set FR64:$dst, (extloadf32 addr:$src))],
1919 IIC_SSE_CVT_Scalar_RM>, XS,
1920 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1922 // extload f32 -> f64. This matches load+fextend because we have a hack in
1923 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1925 // Since these loads aren't folded into the fextend, we have to match it
1927 def : Pat<(fextend (loadf32 addr:$src)),
1928 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1929 def : Pat<(extloadf32 addr:$src),
1930 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1932 let isCodeGenOnly = 1 in {
1933 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1934 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1935 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1937 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1938 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1939 Sched<[WriteCvtF2F]>;
1940 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1941 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1942 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1944 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1945 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1946 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1947 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1948 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1949 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1950 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1952 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1953 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1954 Sched<[WriteCvtF2F]>;
1955 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1956 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1957 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1959 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1960 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1961 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1963 } // isCodeGenOnly = 1
1965 // Convert packed single/double fp to doubleword
1966 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1967 "cvtps2dq\t{$src, $dst|$dst, $src}",
1968 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1969 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1970 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1971 "cvtps2dq\t{$src, $dst|$dst, $src}",
1973 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1974 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1975 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1976 "cvtps2dq\t{$src, $dst|$dst, $src}",
1978 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1979 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1980 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1981 "cvtps2dq\t{$src, $dst|$dst, $src}",
1983 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1984 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1985 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1986 "cvtps2dq\t{$src, $dst|$dst, $src}",
1987 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1988 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1989 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1990 "cvtps2dq\t{$src, $dst|$dst, $src}",
1992 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1993 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1996 // Convert Packed Double FP to Packed DW Integers
1997 let Predicates = [HasAVX] in {
1998 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1999 // register, but the same isn't true when using memory operands instead.
2000 // Provide other assembly rr and rm forms to address this explicitly.
2001 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2002 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2003 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2004 VEX, Sched<[WriteCvtF2I]>;
2007 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2008 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2009 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2010 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2012 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2013 Sched<[WriteCvtF2ILd]>;
2016 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2017 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2019 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2020 Sched<[WriteCvtF2I]>;
2021 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2022 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2024 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2025 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2026 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2027 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2030 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2031 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2033 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2034 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2035 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2036 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2037 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2038 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2040 // Convert with truncation packed single/double fp to doubleword
2041 // SSE2 packed instructions with XS prefix
2042 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2043 "cvttps2dq\t{$src, $dst|$dst, $src}",
2045 (int_x86_sse2_cvttps2dq VR128:$src))],
2046 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2047 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2048 "cvttps2dq\t{$src, $dst|$dst, $src}",
2049 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2050 (loadv4f32 addr:$src)))],
2051 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2052 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2053 "cvttps2dq\t{$src, $dst|$dst, $src}",
2055 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2056 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2057 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2058 "cvttps2dq\t{$src, $dst|$dst, $src}",
2059 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2060 (loadv8f32 addr:$src)))],
2061 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2062 Sched<[WriteCvtF2ILd]>;
2064 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2065 "cvttps2dq\t{$src, $dst|$dst, $src}",
2066 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2067 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2068 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2069 "cvttps2dq\t{$src, $dst|$dst, $src}",
2071 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2072 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2074 let Predicates = [HasAVX] in {
2075 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2076 (VCVTDQ2PSrr VR128:$src)>;
2077 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2078 (VCVTDQ2PSrm addr:$src)>;
2080 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2081 (VCVTDQ2PSrr VR128:$src)>;
2082 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2083 (VCVTDQ2PSrm addr:$src)>;
2085 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2086 (VCVTTPS2DQrr VR128:$src)>;
2087 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2088 (VCVTTPS2DQrm addr:$src)>;
2090 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2091 (VCVTDQ2PSYrr VR256:$src)>;
2092 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2093 (VCVTDQ2PSYrm addr:$src)>;
2095 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2096 (VCVTTPS2DQYrr VR256:$src)>;
2097 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2098 (VCVTTPS2DQYrm addr:$src)>;
2101 let Predicates = [UseSSE2] in {
2102 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2103 (CVTDQ2PSrr VR128:$src)>;
2104 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2105 (CVTDQ2PSrm addr:$src)>;
2107 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2108 (CVTDQ2PSrr VR128:$src)>;
2109 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2110 (CVTDQ2PSrm addr:$src)>;
2112 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2113 (CVTTPS2DQrr VR128:$src)>;
2114 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2115 (CVTTPS2DQrm addr:$src)>;
2118 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2119 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2121 (int_x86_sse2_cvttpd2dq VR128:$src))],
2122 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2124 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2125 // register, but the same isn't true when using memory operands instead.
2126 // Provide other assembly rr and rm forms to address this explicitly.
2129 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2130 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2131 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2132 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2133 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2134 (loadv2f64 addr:$src)))],
2135 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2138 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2139 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2141 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2142 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2143 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2144 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2146 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2147 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2148 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2149 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2151 let Predicates = [HasAVX] in {
2152 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2153 (VCVTTPD2DQYrr VR256:$src)>;
2154 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2155 (VCVTTPD2DQYrm addr:$src)>;
2156 } // Predicates = [HasAVX]
2158 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2159 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2160 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2161 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2162 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2163 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2164 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2165 (memopv2f64 addr:$src)))],
2167 Sched<[WriteCvtF2ILd]>;
2169 // Convert packed single to packed double
2170 let Predicates = [HasAVX] in {
2171 // SSE2 instructions without OpSize prefix
2172 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2173 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2174 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2175 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2176 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2177 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2178 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2179 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2180 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2181 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2183 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2184 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2185 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2186 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2188 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2189 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2192 let Predicates = [UseSSE2] in {
2193 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2194 "cvtps2pd\t{$src, $dst|$dst, $src}",
2195 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2196 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2197 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2198 "cvtps2pd\t{$src, $dst|$dst, $src}",
2199 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2200 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2203 // Convert Packed DW Integers to Packed Double FP
2204 let Predicates = [HasAVX] in {
2205 let neverHasSideEffects = 1, mayLoad = 1 in
2206 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2207 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2208 []>, VEX, Sched<[WriteCvtI2FLd]>;
2209 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2210 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2212 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2213 Sched<[WriteCvtI2F]>;
2214 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2215 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2217 (int_x86_avx_cvtdq2_pd_256
2218 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2219 Sched<[WriteCvtI2FLd]>;
2220 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2221 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2223 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2224 Sched<[WriteCvtI2F]>;
2227 let neverHasSideEffects = 1, mayLoad = 1 in
2228 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2229 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2230 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2231 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2232 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2233 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2234 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2236 // AVX 256-bit register conversion intrinsics
2237 let Predicates = [HasAVX] in {
2238 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2239 (VCVTDQ2PDYrr VR128:$src)>;
2240 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2241 (VCVTDQ2PDYrm addr:$src)>;
2242 } // Predicates = [HasAVX]
2244 // Convert packed double to packed single
2245 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2246 // register, but the same isn't true when using memory operands instead.
2247 // Provide other assembly rr and rm forms to address this explicitly.
2248 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2249 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2250 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2251 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2254 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2255 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2256 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2257 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2259 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2260 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2263 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2264 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2266 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2267 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2268 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2269 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2271 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2272 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2273 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2274 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2276 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2277 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2278 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2279 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2280 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2281 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2283 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2284 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2287 // AVX 256-bit register conversion intrinsics
2288 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2289 // whenever possible to avoid declaring two versions of each one.
2290 let Predicates = [HasAVX] in {
2291 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2292 (VCVTDQ2PSYrr VR256:$src)>;
2293 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2294 (VCVTDQ2PSYrm addr:$src)>;
2296 // Match fround and fextend for 128/256-bit conversions
2297 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2298 (VCVTPD2PSrr VR128:$src)>;
2299 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2300 (VCVTPD2PSXrm addr:$src)>;
2301 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2302 (VCVTPD2PSYrr VR256:$src)>;
2303 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2304 (VCVTPD2PSYrm addr:$src)>;
2306 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2307 (VCVTPS2PDrr VR128:$src)>;
2308 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2309 (VCVTPS2PDYrr VR128:$src)>;
2310 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2311 (VCVTPS2PDYrm addr:$src)>;
2314 let Predicates = [UseSSE2] in {
2315 // Match fround and fextend for 128 conversions
2316 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2317 (CVTPD2PSrr VR128:$src)>;
2318 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2319 (CVTPD2PSrm addr:$src)>;
2321 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2322 (CVTPS2PDrr VR128:$src)>;
2325 //===----------------------------------------------------------------------===//
2326 // SSE 1 & 2 - Compare Instructions
2327 //===----------------------------------------------------------------------===//
2329 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2330 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2331 Operand CC, SDNode OpNode, ValueType VT,
2332 PatFrag ld_frag, string asm, string asm_alt,
2334 def rr : SIi8<0xC2, MRMSrcReg,
2335 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2336 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2337 itins.rr>, Sched<[itins.Sched]>;
2338 def rm : SIi8<0xC2, MRMSrcMem,
2339 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2340 [(set RC:$dst, (OpNode (VT RC:$src1),
2341 (ld_frag addr:$src2), imm:$cc))],
2343 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2345 // Accept explicit immediate argument form instead of comparison code.
2346 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2347 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2348 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2349 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2351 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2352 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2353 IIC_SSE_ALU_F32S_RM>,
2354 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2358 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2359 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2360 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2362 XS, VEX_4V, VEX_LIG;
2363 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2364 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2365 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2366 SSE_ALU_F32S>, // same latency as 32 bit compare
2367 XD, VEX_4V, VEX_LIG;
2369 let Constraints = "$src1 = $dst" in {
2370 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2371 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2372 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2374 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2375 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2376 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2381 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2382 Intrinsic Int, string asm, OpndItins itins> {
2383 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2384 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2385 [(set VR128:$dst, (Int VR128:$src1,
2386 VR128:$src, imm:$cc))],
2388 Sched<[itins.Sched]>;
2389 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2390 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2391 [(set VR128:$dst, (Int VR128:$src1,
2392 (load addr:$src), imm:$cc))],
2394 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2397 let isCodeGenOnly = 1 in {
2398 // Aliases to match intrinsics which expect XMM operand(s).
2399 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2400 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2403 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2404 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2405 SSE_ALU_F32S>, // same latency as f32
2407 let Constraints = "$src1 = $dst" in {
2408 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2409 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2411 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2412 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2419 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2420 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2421 ValueType vt, X86MemOperand x86memop,
2422 PatFrag ld_frag, string OpcodeStr> {
2423 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2424 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2425 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2428 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2429 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2430 [(set EFLAGS, (OpNode (vt RC:$src1),
2431 (ld_frag addr:$src2)))],
2433 Sched<[WriteFAddLd, ReadAfterLd]>;
2436 let Defs = [EFLAGS] in {
2437 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2438 "ucomiss">, PS, VEX, VEX_LIG;
2439 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2440 "ucomisd">, PD, VEX, VEX_LIG;
2441 let Pattern = []<dag> in {
2442 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2443 "comiss">, PS, VEX, VEX_LIG;
2444 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2445 "comisd">, PD, VEX, VEX_LIG;
2448 let isCodeGenOnly = 1 in {
2449 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2450 load, "ucomiss">, PS, VEX;
2451 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2452 load, "ucomisd">, PD, VEX;
2454 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2455 load, "comiss">, PS, VEX;
2456 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2457 load, "comisd">, PD, VEX;
2459 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2461 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2464 let Pattern = []<dag> in {
2465 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2467 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2471 let isCodeGenOnly = 1 in {
2472 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2473 load, "ucomiss">, PS;
2474 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2475 load, "ucomisd">, PD;
2477 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2479 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2482 } // Defs = [EFLAGS]
2484 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2485 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2486 Operand CC, Intrinsic Int, string asm,
2487 string asm_alt, Domain d,
2488 OpndItins itins = SSE_ALU_F32P> {
2489 def rri : PIi8<0xC2, MRMSrcReg,
2490 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2491 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2494 def rmi : PIi8<0xC2, MRMSrcMem,
2495 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2496 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2498 Sched<[WriteFAddLd, ReadAfterLd]>;
2500 // Accept explicit immediate argument form instead of comparison code.
2501 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2502 def rri_alt : PIi8<0xC2, MRMSrcReg,
2503 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2504 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2505 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2506 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2507 asm_alt, [], itins.rm, d>,
2508 Sched<[WriteFAddLd, ReadAfterLd]>;
2512 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2513 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2514 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2515 SSEPackedSingle>, PS, VEX_4V;
2516 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2517 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2518 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2519 SSEPackedDouble>, PD, VEX_4V;
2520 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2521 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2522 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2523 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2524 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2525 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2526 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2527 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2528 let Constraints = "$src1 = $dst" in {
2529 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2530 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2531 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2532 SSEPackedSingle, SSE_ALU_F32P>, PS;
2533 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2534 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2535 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2536 SSEPackedDouble, SSE_ALU_F64P>, PD;
2539 let Predicates = [HasAVX] in {
2540 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2541 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2542 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2543 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2544 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2545 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2546 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2547 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2549 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2550 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2551 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2552 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2553 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2554 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2555 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2556 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2559 let Predicates = [UseSSE1] in {
2560 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2561 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2562 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2563 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2566 let Predicates = [UseSSE2] in {
2567 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2568 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2569 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2570 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2573 //===----------------------------------------------------------------------===//
2574 // SSE 1 & 2 - Shuffle Instructions
2575 //===----------------------------------------------------------------------===//
2577 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2578 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2579 ValueType vt, string asm, PatFrag mem_frag,
2580 Domain d, bit IsConvertibleToThreeAddress = 0> {
2581 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2582 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2583 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2584 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2585 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2586 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2587 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2588 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2589 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2590 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2591 Sched<[WriteFShuffle]>;
2594 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2595 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2596 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2597 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2598 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2599 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2600 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2601 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2602 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2603 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2604 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2605 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2607 let Constraints = "$src1 = $dst" in {
2608 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2609 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2610 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>, PS;
2611 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2612 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2613 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>, PD;
2616 let Predicates = [HasAVX] in {
2617 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2618 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2619 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2620 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2621 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2623 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2624 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2625 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2626 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2627 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2630 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2631 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2632 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2633 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2634 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2636 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2637 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2638 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2639 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2640 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2643 let Predicates = [UseSSE1] in {
2644 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2645 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2646 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2647 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2648 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2651 let Predicates = [UseSSE2] in {
2652 // Generic SHUFPD patterns
2653 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2654 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2655 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2656 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2657 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2660 //===----------------------------------------------------------------------===//
2661 // SSE 1 & 2 - Unpack FP Instructions
2662 //===----------------------------------------------------------------------===//
2664 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2665 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2666 PatFrag mem_frag, RegisterClass RC,
2667 X86MemOperand x86memop, string asm,
2669 def rr : PI<opc, MRMSrcReg,
2670 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2672 (vt (OpNode RC:$src1, RC:$src2)))],
2673 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2674 def rm : PI<opc, MRMSrcMem,
2675 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2677 (vt (OpNode RC:$src1,
2678 (mem_frag addr:$src2))))],
2680 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2683 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2684 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2685 SSEPackedSingle>, PS, VEX_4V;
2686 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2687 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2688 SSEPackedDouble>, PD, VEX_4V;
2689 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2690 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2691 SSEPackedSingle>, PS, VEX_4V;
2692 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2693 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2694 SSEPackedDouble>, PD, VEX_4V;
2696 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2697 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2698 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2699 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2700 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2701 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2702 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2703 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2704 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2705 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2706 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2707 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2709 let Constraints = "$src1 = $dst" in {
2710 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2711 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2712 SSEPackedSingle>, PS;
2713 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2714 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2715 SSEPackedDouble>, PD;
2716 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2717 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2718 SSEPackedSingle>, PS;
2719 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2720 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2721 SSEPackedDouble>, PD;
2722 } // Constraints = "$src1 = $dst"
2724 let Predicates = [HasAVX1Only] in {
2725 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2726 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2727 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2728 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2729 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2730 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2731 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2732 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2734 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2735 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2736 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2737 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2738 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2739 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2740 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2741 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2744 let Predicates = [HasAVX] in {
2745 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2746 // problem is during lowering, where it's not possible to recognize the load
2747 // fold cause it has two uses through a bitcast. One use disappears at isel
2748 // time and the fold opportunity reappears.
2749 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2750 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2753 let Predicates = [UseSSE2] in {
2754 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2755 // problem is during lowering, where it's not possible to recognize the load
2756 // fold cause it has two uses through a bitcast. One use disappears at isel
2757 // time and the fold opportunity reappears.
2758 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2759 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2762 //===----------------------------------------------------------------------===//
2763 // SSE 1 & 2 - Extract Floating-Point Sign mask
2764 //===----------------------------------------------------------------------===//
2766 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2767 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2769 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2770 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2771 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2772 Sched<[WriteVecLogic]>;
2775 let Predicates = [HasAVX] in {
2776 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2777 "movmskps", SSEPackedSingle>, PS, VEX;
2778 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2779 "movmskpd", SSEPackedDouble>, PD, VEX;
2780 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2781 "movmskps", SSEPackedSingle>, PS,
2783 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2784 "movmskpd", SSEPackedDouble>, PD,
2787 def : Pat<(i32 (X86fgetsign FR32:$src)),
2788 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2789 def : Pat<(i64 (X86fgetsign FR32:$src)),
2790 (SUBREG_TO_REG (i64 0),
2791 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2792 def : Pat<(i32 (X86fgetsign FR64:$src)),
2793 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2794 def : Pat<(i64 (X86fgetsign FR64:$src)),
2795 (SUBREG_TO_REG (i64 0),
2796 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2799 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2800 SSEPackedSingle>, PS;
2801 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2802 SSEPackedDouble>, PD;
2804 def : Pat<(i32 (X86fgetsign FR32:$src)),
2805 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2806 Requires<[UseSSE1]>;
2807 def : Pat<(i64 (X86fgetsign FR32:$src)),
2808 (SUBREG_TO_REG (i64 0),
2809 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2810 Requires<[UseSSE1]>;
2811 def : Pat<(i32 (X86fgetsign FR64:$src)),
2812 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2813 Requires<[UseSSE2]>;
2814 def : Pat<(i64 (X86fgetsign FR64:$src)),
2815 (SUBREG_TO_REG (i64 0),
2816 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2817 Requires<[UseSSE2]>;
2819 //===---------------------------------------------------------------------===//
2820 // SSE2 - Packed Integer Logical Instructions
2821 //===---------------------------------------------------------------------===//
2823 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2825 /// PDI_binop_rm - Simple SSE2 binary operator.
2826 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2827 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2828 X86MemOperand x86memop, OpndItins itins,
2829 bit IsCommutable, bit Is2Addr> {
2830 let isCommutable = IsCommutable in
2831 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2832 (ins RC:$src1, RC:$src2),
2834 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2835 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2836 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2837 Sched<[itins.Sched]>;
2838 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2839 (ins RC:$src1, x86memop:$src2),
2841 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2842 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2843 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2844 (bitconvert (memop_frag addr:$src2)))))],
2846 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2848 } // ExeDomain = SSEPackedInt
2850 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2851 ValueType OpVT128, ValueType OpVT256,
2852 OpndItins itins, bit IsCommutable = 0> {
2853 let Predicates = [HasAVX] in
2854 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2855 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2857 let Constraints = "$src1 = $dst" in
2858 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2859 memopv2i64, i128mem, itins, IsCommutable, 1>;
2861 let Predicates = [HasAVX2] in
2862 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2863 OpVT256, VR256, loadv4i64, i256mem, itins,
2864 IsCommutable, 0>, VEX_4V, VEX_L;
2867 // These are ordered here for pattern ordering requirements with the fp versions
2869 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2870 SSE_VEC_BIT_ITINS_P, 1>;
2871 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2872 SSE_VEC_BIT_ITINS_P, 1>;
2873 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2874 SSE_VEC_BIT_ITINS_P, 1>;
2875 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2876 SSE_VEC_BIT_ITINS_P, 0>;
2878 //===----------------------------------------------------------------------===//
2879 // SSE 1 & 2 - Logical Instructions
2880 //===----------------------------------------------------------------------===//
2882 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2884 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2885 SDNode OpNode, OpndItins itins> {
2886 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2887 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2890 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2891 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2894 let Constraints = "$src1 = $dst" in {
2895 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2896 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2899 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2900 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2905 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2906 let isCodeGenOnly = 1 in {
2907 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2909 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2911 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2914 let isCommutable = 0 in
2915 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2919 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2921 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2923 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2924 !strconcat(OpcodeStr, "ps"), f256mem,
2925 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2926 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2927 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2929 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2930 !strconcat(OpcodeStr, "pd"), f256mem,
2931 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2932 (bc_v4i64 (v4f64 VR256:$src2))))],
2933 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2934 (loadv4i64 addr:$src2)))], 0>,
2937 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2938 // are all promoted to v2i64, and the patterns are covered by the int
2939 // version. This is needed in SSE only, because v2i64 isn't supported on
2940 // SSE1, but only on SSE2.
2941 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2942 !strconcat(OpcodeStr, "ps"), f128mem, [],
2943 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2944 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2946 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2947 !strconcat(OpcodeStr, "pd"), f128mem,
2948 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2949 (bc_v2i64 (v2f64 VR128:$src2))))],
2950 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2951 (loadv2i64 addr:$src2)))], 0>,
2954 let Constraints = "$src1 = $dst" in {
2955 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2956 !strconcat(OpcodeStr, "ps"), f128mem,
2957 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2958 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2959 (memopv2i64 addr:$src2)))]>, PS;
2961 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2962 !strconcat(OpcodeStr, "pd"), f128mem,
2963 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2964 (bc_v2i64 (v2f64 VR128:$src2))))],
2965 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2966 (memopv2i64 addr:$src2)))]>, PD;
2970 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2971 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2972 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2973 let isCommutable = 0 in
2974 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2976 // AVX1 requires type coercions in order to fold loads directly into logical
2978 let Predicates = [HasAVX1Only] in {
2979 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
2980 (VANDPSYrm VR256:$src1, addr:$src2)>;
2981 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
2982 (VORPSYrm VR256:$src1, addr:$src2)>;
2983 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
2984 (VXORPSYrm VR256:$src1, addr:$src2)>;
2985 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
2986 (VANDNPSYrm VR256:$src1, addr:$src2)>;
2989 //===----------------------------------------------------------------------===//
2990 // SSE 1 & 2 - Arithmetic Instructions
2991 //===----------------------------------------------------------------------===//
2993 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2996 /// In addition, we also have a special variant of the scalar form here to
2997 /// represent the associated intrinsic operation. This form is unlike the
2998 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2999 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3001 /// These three forms can each be reg+reg or reg+mem.
3004 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3006 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3007 SDNode OpNode, SizeItins itins> {
3008 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3009 VR128, v4f32, f128mem, loadv4f32,
3010 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3011 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3012 VR128, v2f64, f128mem, loadv2f64,
3013 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3015 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3016 OpNode, VR256, v8f32, f256mem, loadv8f32,
3017 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3018 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3019 OpNode, VR256, v4f64, f256mem, loadv4f64,
3020 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3022 let Constraints = "$src1 = $dst" in {
3023 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3024 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3026 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3027 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3032 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3034 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3035 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3036 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3037 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3039 let Constraints = "$src1 = $dst" in {
3040 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3041 OpNode, FR32, f32mem, itins.s>, XS;
3042 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3043 OpNode, FR64, f64mem, itins.d>, XD;
3047 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3049 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3050 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3051 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3052 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3053 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3054 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3056 let Constraints = "$src1 = $dst" in {
3057 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3058 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3060 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3061 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3066 // Binary Arithmetic instructions
3067 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3068 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3069 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3070 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3071 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3072 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3073 let isCommutable = 0 in {
3074 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3075 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3076 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3077 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3078 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3079 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3080 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3081 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3082 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3083 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3084 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3085 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3088 let isCodeGenOnly = 1 in {
3089 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3090 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3091 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3092 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3095 // Patterns used to select SSE scalar fp arithmetic instructions from
3096 // a scalar fp operation followed by a blend.
3098 // These patterns know, for example, how to select an ADDSS from a
3099 // float add plus vector insert.
3101 // The effect is that the backend no longer emits unnecessary vector
3102 // insert instructions immediately after SSE scalar fp instructions
3103 // like addss or mulss.
3105 // For example, given the following code:
3106 // __m128 foo(__m128 A, __m128 B) {
3111 // previously we generated:
3112 // addss %xmm0, %xmm1
3113 // movss %xmm1, %xmm0
3116 // addss %xmm1, %xmm0
3118 let Predicates = [UseSSE1] in {
3119 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3120 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3122 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3123 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3124 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3126 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3127 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3128 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3130 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3131 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3132 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3134 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3137 let Predicates = [UseSSE2] in {
3138 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3140 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3141 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3143 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3144 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3145 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3147 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3148 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3149 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3151 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3152 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3153 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3155 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3158 let Predicates = [UseSSE41] in {
3159 // If the subtarget has SSE4.1 but not AVX, the vector insert
3160 // instruction is lowered into a X86insertps rather than a X86Movss.
3161 // When selecting SSE scalar single-precision fp arithmetic instructions,
3162 // make sure that we correctly match the X86insertps.
3164 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3165 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3166 FR32:$src))), (iPTR 0))),
3167 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3168 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3169 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3170 FR32:$src))), (iPTR 0))),
3171 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3172 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3173 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3174 FR32:$src))), (iPTR 0))),
3175 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3176 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3177 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3178 FR32:$src))), (iPTR 0))),
3179 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3182 let Predicates = [HasAVX] in {
3183 // The following patterns select AVX Scalar single/double precision fp
3184 // arithmetic instructions.
3186 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3187 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3189 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3190 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3191 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3193 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3194 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3195 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3197 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3198 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3199 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3201 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3202 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3203 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3204 FR32:$src))), (iPTR 0))),
3205 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3206 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3207 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3208 FR32:$src))), (iPTR 0))),
3209 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3210 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3211 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3212 FR32:$src))), (iPTR 0))),
3213 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3214 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3215 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3216 FR32:$src))), (iPTR 0))),
3217 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3220 // Patterns used to select SSE scalar fp arithmetic instructions from
3221 // a vector packed single/double fp operation followed by a vector insert.
3223 // The effect is that the backend converts the packed fp instruction
3224 // followed by a vector insert into a single SSE scalar fp instruction.
3226 // For example, given the following code:
3227 // __m128 foo(__m128 A, __m128 B) {
3228 // __m128 C = A + B;
3229 // return (__m128) {c[0], a[1], a[2], a[3]};
3232 // previously we generated:
3233 // addps %xmm0, %xmm1
3234 // movss %xmm1, %xmm0
3237 // addss %xmm1, %xmm0
3239 let Predicates = [UseSSE1] in {
3240 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3241 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3242 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3243 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3244 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3245 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3246 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3247 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3248 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3249 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3250 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3251 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3254 let Predicates = [UseSSE2] in {
3255 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3256 // from a packed double-precision fp instruction plus movsd.
3258 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3259 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3260 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3261 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3262 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3263 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3264 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3265 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3266 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3267 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3268 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3269 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3272 let Predicates = [HasAVX] in {
3273 // The following patterns select AVX Scalar single/double precision fp
3274 // arithmetic instructions from a packed single precision fp instruction
3275 // plus movss/movsd.
3277 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3278 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3279 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3280 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3281 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3282 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3283 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3284 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3285 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3286 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3287 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3288 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3289 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3290 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3291 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3292 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3293 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3294 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3295 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3296 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3297 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3298 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3299 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3300 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3304 /// In addition, we also have a special variant of the scalar form here to
3305 /// represent the associated intrinsic operation. This form is unlike the
3306 /// plain scalar form, in that it takes an entire vector (instead of a
3307 /// scalar) and leaves the top elements undefined.
3309 /// And, we have a special variant form for a full-vector intrinsic form.
3311 let Sched = WriteFSqrt in {
3312 def SSE_SQRTPS : OpndItins<
3313 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3316 def SSE_SQRTSS : OpndItins<
3317 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3320 def SSE_SQRTPD : OpndItins<
3321 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3324 def SSE_SQRTSD : OpndItins<
3325 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3329 let Sched = WriteFRcp in {
3330 def SSE_RCPP : OpndItins<
3331 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3334 def SSE_RCPS : OpndItins<
3335 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3339 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3340 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3341 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3342 let Predicates = [HasAVX], hasSideEffects = 0 in {
3343 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3344 (ins FR32:$src1, FR32:$src2),
3345 !strconcat("v", OpcodeStr,
3346 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3347 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3348 let mayLoad = 1 in {
3349 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3350 (ins FR32:$src1,f32mem:$src2),
3351 !strconcat("v", OpcodeStr,
3352 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3353 []>, VEX_4V, VEX_LIG,
3354 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3355 let isCodeGenOnly = 1 in
3356 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3357 (ins VR128:$src1, ssmem:$src2),
3358 !strconcat("v", OpcodeStr,
3359 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3360 []>, VEX_4V, VEX_LIG,
3361 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3365 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3366 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3367 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3368 // For scalar unary operations, fold a load into the operation
3369 // only in OptForSize mode. It eliminates an instruction, but it also
3370 // eliminates a whole-register clobber (the load), so it introduces a
3371 // partial register update condition.
3372 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3373 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3374 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3375 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3376 let isCodeGenOnly = 1 in {
3377 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3378 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3379 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3380 Sched<[itins.Sched]>;
3381 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3382 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3383 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3384 Sched<[itins.Sched.Folded]>;
3388 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3389 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3391 let Predicates = [HasAVX], hasSideEffects = 0 in {
3392 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3393 (ins FR32:$src1, FR32:$src2),
3394 !strconcat("v", OpcodeStr,
3395 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3396 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3397 let mayLoad = 1 in {
3398 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3399 (ins FR32:$src1,f32mem:$src2),
3400 !strconcat("v", OpcodeStr,
3401 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3402 []>, VEX_4V, VEX_LIG,
3403 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3404 let isCodeGenOnly = 1 in
3405 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3406 (ins VR128:$src1, ssmem:$src2),
3407 !strconcat("v", OpcodeStr,
3408 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3409 []>, VEX_4V, VEX_LIG,
3410 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3414 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3415 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3416 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3417 // For scalar unary operations, fold a load into the operation
3418 // only in OptForSize mode. It eliminates an instruction, but it also
3419 // eliminates a whole-register clobber (the load), so it introduces a
3420 // partial register update condition.
3421 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3422 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3423 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3424 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3425 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3426 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3427 (ins VR128:$src1, VR128:$src2),
3428 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3429 [], itins.rr>, Sched<[itins.Sched]>;
3430 let mayLoad = 1, hasSideEffects = 0 in
3431 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3432 (ins VR128:$src1, ssmem:$src2),
3433 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3434 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3438 /// sse1_fp_unop_p - SSE1 unops in packed form.
3439 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3441 let Predicates = [HasAVX] in {
3442 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3443 !strconcat("v", OpcodeStr,
3444 "ps\t{$src, $dst|$dst, $src}"),
3445 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3446 itins.rr>, VEX, Sched<[itins.Sched]>;
3447 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3448 !strconcat("v", OpcodeStr,
3449 "ps\t{$src, $dst|$dst, $src}"),
3450 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3451 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3452 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3453 !strconcat("v", OpcodeStr,
3454 "ps\t{$src, $dst|$dst, $src}"),
3455 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3456 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3457 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3458 !strconcat("v", OpcodeStr,
3459 "ps\t{$src, $dst|$dst, $src}"),
3460 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3461 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3464 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3465 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3466 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3467 Sched<[itins.Sched]>;
3468 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3469 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3470 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3471 Sched<[itins.Sched.Folded]>;
3474 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3475 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3476 Intrinsic V4F32Int, Intrinsic V8F32Int,
3478 let isCodeGenOnly = 1 in {
3479 let Predicates = [HasAVX] in {
3480 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3481 !strconcat("v", OpcodeStr,
3482 "ps\t{$src, $dst|$dst, $src}"),
3483 [(set VR128:$dst, (V4F32Int VR128:$src))],
3484 itins.rr>, VEX, Sched<[itins.Sched]>;
3485 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3486 !strconcat("v", OpcodeStr,
3487 "ps\t{$src, $dst|$dst, $src}"),
3488 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3489 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3490 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3491 !strconcat("v", OpcodeStr,
3492 "ps\t{$src, $dst|$dst, $src}"),
3493 [(set VR256:$dst, (V8F32Int VR256:$src))],
3494 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3495 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3497 !strconcat("v", OpcodeStr,
3498 "ps\t{$src, $dst|$dst, $src}"),
3499 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3500 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3503 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3504 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3505 [(set VR128:$dst, (V4F32Int VR128:$src))],
3506 itins.rr>, Sched<[itins.Sched]>;
3507 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3508 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3509 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3510 itins.rm>, Sched<[itins.Sched.Folded]>;
3511 } // isCodeGenOnly = 1
3514 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3515 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3516 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3517 let Predicates = [HasAVX], hasSideEffects = 0 in {
3518 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3519 (ins FR64:$src1, FR64:$src2),
3520 !strconcat("v", OpcodeStr,
3521 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3522 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3523 let mayLoad = 1 in {
3524 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3525 (ins FR64:$src1,f64mem:$src2),
3526 !strconcat("v", OpcodeStr,
3527 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3528 []>, VEX_4V, VEX_LIG,
3529 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3530 let isCodeGenOnly = 1 in
3531 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3532 (ins VR128:$src1, sdmem:$src2),
3533 !strconcat("v", OpcodeStr,
3534 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3535 []>, VEX_4V, VEX_LIG,
3536 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3540 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3541 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3542 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3543 Sched<[itins.Sched]>;
3544 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3545 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3546 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3547 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3548 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3549 let isCodeGenOnly = 1 in {
3550 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3551 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3552 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3553 Sched<[itins.Sched]>;
3554 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3555 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3556 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3557 Sched<[itins.Sched.Folded]>;
3561 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3562 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3563 SDNode OpNode, OpndItins itins> {
3564 let Predicates = [HasAVX] in {
3565 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3566 !strconcat("v", OpcodeStr,
3567 "pd\t{$src, $dst|$dst, $src}"),
3568 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3569 itins.rr>, VEX, Sched<[itins.Sched]>;
3570 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3571 !strconcat("v", OpcodeStr,
3572 "pd\t{$src, $dst|$dst, $src}"),
3573 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3574 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3575 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3576 !strconcat("v", OpcodeStr,
3577 "pd\t{$src, $dst|$dst, $src}"),
3578 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3579 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3580 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3581 !strconcat("v", OpcodeStr,
3582 "pd\t{$src, $dst|$dst, $src}"),
3583 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3584 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3587 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3588 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3589 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3590 Sched<[itins.Sched]>;
3591 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3592 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3593 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3594 Sched<[itins.Sched.Folded]>;
3598 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3600 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3601 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3603 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3605 // Reciprocal approximations. Note that these typically require refinement
3606 // in order to obtain suitable precision.
3607 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3608 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3609 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3610 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3611 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3612 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3613 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3614 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3616 let Predicates = [UseAVX] in {
3617 def : Pat<(f32 (fsqrt FR32:$src)),
3618 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3619 def : Pat<(f32 (fsqrt (load addr:$src))),
3620 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3621 Requires<[HasAVX, OptForSize]>;
3622 def : Pat<(f64 (fsqrt FR64:$src)),
3623 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3624 def : Pat<(f64 (fsqrt (load addr:$src))),
3625 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3626 Requires<[HasAVX, OptForSize]>;
3628 def : Pat<(f32 (X86frsqrt FR32:$src)),
3629 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3630 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3631 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3632 Requires<[HasAVX, OptForSize]>;
3634 def : Pat<(f32 (X86frcp FR32:$src)),
3635 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3636 def : Pat<(f32 (X86frcp (load addr:$src))),
3637 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3638 Requires<[HasAVX, OptForSize]>;
3640 let Predicates = [UseAVX] in {
3641 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3642 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3643 (COPY_TO_REGCLASS VR128:$src, FR32)),
3645 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3646 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3648 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3649 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3650 (COPY_TO_REGCLASS VR128:$src, FR64)),
3652 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3653 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3656 let Predicates = [HasAVX] in {
3657 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3658 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3659 (COPY_TO_REGCLASS VR128:$src, FR32)),
3661 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3662 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3664 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3665 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3666 (COPY_TO_REGCLASS VR128:$src, FR32)),
3668 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3669 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3672 // Reciprocal approximations. Note that these typically require refinement
3673 // in order to obtain suitable precision.
3674 let Predicates = [UseSSE1] in {
3675 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3676 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3677 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3678 (RCPSSr_Int VR128:$src, VR128:$src)>;
3681 // There is no f64 version of the reciprocal approximation instructions.
3683 //===----------------------------------------------------------------------===//
3684 // SSE 1 & 2 - Non-temporal stores
3685 //===----------------------------------------------------------------------===//
3687 let AddedComplexity = 400 in { // Prefer non-temporal versions
3688 let SchedRW = [WriteStore] in {
3689 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3690 (ins f128mem:$dst, VR128:$src),
3691 "movntps\t{$src, $dst|$dst, $src}",
3692 [(alignednontemporalstore (v4f32 VR128:$src),
3694 IIC_SSE_MOVNT>, VEX;
3695 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3696 (ins f128mem:$dst, VR128:$src),
3697 "movntpd\t{$src, $dst|$dst, $src}",
3698 [(alignednontemporalstore (v2f64 VR128:$src),
3700 IIC_SSE_MOVNT>, VEX;
3702 let ExeDomain = SSEPackedInt in
3703 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3704 (ins f128mem:$dst, VR128:$src),
3705 "movntdq\t{$src, $dst|$dst, $src}",
3706 [(alignednontemporalstore (v2i64 VR128:$src),
3708 IIC_SSE_MOVNT>, VEX;
3710 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3711 (ins f256mem:$dst, VR256:$src),
3712 "movntps\t{$src, $dst|$dst, $src}",
3713 [(alignednontemporalstore (v8f32 VR256:$src),
3715 IIC_SSE_MOVNT>, VEX, VEX_L;
3716 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3717 (ins f256mem:$dst, VR256:$src),
3718 "movntpd\t{$src, $dst|$dst, $src}",
3719 [(alignednontemporalstore (v4f64 VR256:$src),
3721 IIC_SSE_MOVNT>, VEX, VEX_L;
3722 let ExeDomain = SSEPackedInt in
3723 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3724 (ins f256mem:$dst, VR256:$src),
3725 "movntdq\t{$src, $dst|$dst, $src}",
3726 [(alignednontemporalstore (v4i64 VR256:$src),
3728 IIC_SSE_MOVNT>, VEX, VEX_L;
3730 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3731 "movntps\t{$src, $dst|$dst, $src}",
3732 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3734 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3735 "movntpd\t{$src, $dst|$dst, $src}",
3736 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3739 let ExeDomain = SSEPackedInt in
3740 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3741 "movntdq\t{$src, $dst|$dst, $src}",
3742 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3745 // There is no AVX form for instructions below this point
3746 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3747 "movnti{l}\t{$src, $dst|$dst, $src}",
3748 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3750 PS, Requires<[HasSSE2]>;
3751 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3752 "movnti{q}\t{$src, $dst|$dst, $src}",
3753 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3755 PS, Requires<[HasSSE2]>;
3756 } // SchedRW = [WriteStore]
3758 } // AddedComplexity
3760 //===----------------------------------------------------------------------===//
3761 // SSE 1 & 2 - Prefetch and memory fence
3762 //===----------------------------------------------------------------------===//
3764 // Prefetch intrinsic.
3765 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3766 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3767 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3768 IIC_SSE_PREFETCH>, TB;
3769 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3770 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3771 IIC_SSE_PREFETCH>, TB;
3772 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3773 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3774 IIC_SSE_PREFETCH>, TB;
3775 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3776 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3777 IIC_SSE_PREFETCH>, TB;
3780 // FIXME: How should flush instruction be modeled?
3781 let SchedRW = [WriteLoad] in {
3783 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3784 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3785 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3788 let SchedRW = [WriteNop] in {
3789 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3790 // was introduced with SSE2, it's backward compatible.
3791 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3792 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3793 OBXS, Requires<[HasSSE2]>;
3796 let SchedRW = [WriteFence] in {
3797 // Load, store, and memory fence
3798 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3799 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3800 TB, Requires<[HasSSE1]>;
3801 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3802 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3803 TB, Requires<[HasSSE2]>;
3804 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3805 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3806 TB, Requires<[HasSSE2]>;
3809 def : Pat<(X86SFence), (SFENCE)>;
3810 def : Pat<(X86LFence), (LFENCE)>;
3811 def : Pat<(X86MFence), (MFENCE)>;
3813 //===----------------------------------------------------------------------===//
3814 // SSE 1 & 2 - Load/Store XCSR register
3815 //===----------------------------------------------------------------------===//
3817 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3818 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3819 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3820 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3821 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3822 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3824 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3825 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3826 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3827 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3828 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3829 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3831 //===---------------------------------------------------------------------===//
3832 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3833 //===---------------------------------------------------------------------===//
3835 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3837 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3838 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3839 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3841 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3842 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3844 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3845 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3847 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3848 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3853 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3854 SchedRW = [WriteMove] in {
3855 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3856 "movdqa\t{$src, $dst|$dst, $src}", [],
3859 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3860 "movdqa\t{$src, $dst|$dst, $src}", [],
3861 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3862 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3863 "movdqu\t{$src, $dst|$dst, $src}", [],
3866 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3867 "movdqu\t{$src, $dst|$dst, $src}", [],
3868 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3871 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3872 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3873 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3874 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3876 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3877 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3879 let Predicates = [HasAVX] in {
3880 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3881 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3883 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3884 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3889 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3890 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3891 (ins i128mem:$dst, VR128:$src),
3892 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3894 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3895 (ins i256mem:$dst, VR256:$src),
3896 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3898 let Predicates = [HasAVX] in {
3899 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3900 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3902 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3903 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3908 let SchedRW = [WriteMove] in {
3909 let neverHasSideEffects = 1 in
3910 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3911 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3913 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3914 "movdqu\t{$src, $dst|$dst, $src}",
3915 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3918 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3919 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3920 "movdqa\t{$src, $dst|$dst, $src}", [],
3923 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3924 "movdqu\t{$src, $dst|$dst, $src}",
3925 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3929 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3930 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3931 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3932 "movdqa\t{$src, $dst|$dst, $src}",
3933 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3935 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3936 "movdqu\t{$src, $dst|$dst, $src}",
3937 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3939 XS, Requires<[UseSSE2]>;
3942 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3943 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3944 "movdqa\t{$src, $dst|$dst, $src}",
3945 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3947 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3948 "movdqu\t{$src, $dst|$dst, $src}",
3949 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3951 XS, Requires<[UseSSE2]>;
3954 } // ExeDomain = SSEPackedInt
3956 let Predicates = [HasAVX] in {
3957 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3958 (VMOVDQUmr addr:$dst, VR128:$src)>;
3959 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3960 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3962 let Predicates = [UseSSE2] in
3963 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3964 (MOVDQUmr addr:$dst, VR128:$src)>;
3966 //===---------------------------------------------------------------------===//
3967 // SSE2 - Packed Integer Arithmetic Instructions
3968 //===---------------------------------------------------------------------===//
3970 let Sched = WriteVecIMul in
3971 def SSE_PMADD : OpndItins<
3972 IIC_SSE_PMADD, IIC_SSE_PMADD
3975 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3977 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3978 RegisterClass RC, PatFrag memop_frag,
3979 X86MemOperand x86memop,
3981 bit IsCommutable = 0,
3983 let isCommutable = IsCommutable in
3984 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3985 (ins RC:$src1, RC:$src2),
3987 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3988 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3989 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3990 Sched<[itins.Sched]>;
3991 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3992 (ins RC:$src1, x86memop:$src2),
3994 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3995 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3996 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3997 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
4000 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
4001 Intrinsic IntId256, OpndItins itins,
4002 bit IsCommutable = 0> {
4003 let Predicates = [HasAVX] in
4004 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
4005 VR128, loadv2i64, i128mem, itins,
4006 IsCommutable, 0>, VEX_4V;
4008 let Constraints = "$src1 = $dst" in
4009 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
4010 i128mem, itins, IsCommutable, 1>;
4012 let Predicates = [HasAVX2] in
4013 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
4014 VR256, loadv4i64, i256mem, itins,
4015 IsCommutable, 0>, VEX_4V, VEX_L;
4018 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
4019 string OpcodeStr, SDNode OpNode,
4020 SDNode OpNode2, RegisterClass RC,
4021 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
4022 ShiftOpndItins itins,
4024 // src2 is always 128-bit
4025 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4026 (ins RC:$src1, VR128:$src2),
4028 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4029 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4030 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
4031 itins.rr>, Sched<[WriteVecShift]>;
4032 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4033 (ins RC:$src1, i128mem:$src2),
4035 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4036 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4037 [(set RC:$dst, (DstVT (OpNode RC:$src1,
4038 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
4039 Sched<[WriteVecShiftLd, ReadAfterLd]>;
4040 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
4041 (ins RC:$src1, i8imm:$src2),
4043 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4044 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4045 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
4046 Sched<[WriteVecShift]>;
4049 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4050 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4051 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4052 PatFrag memop_frag, X86MemOperand x86memop,
4054 bit IsCommutable = 0, bit Is2Addr = 1> {
4055 let isCommutable = IsCommutable in
4056 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4057 (ins RC:$src1, RC:$src2),
4059 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4060 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4061 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4062 Sched<[itins.Sched]>;
4063 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4064 (ins RC:$src1, x86memop:$src2),
4066 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4067 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4068 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4069 (bitconvert (memop_frag addr:$src2)))))]>,
4070 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4072 } // ExeDomain = SSEPackedInt
4074 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4075 SSE_INTALU_ITINS_P, 1>;
4076 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4077 SSE_INTALU_ITINS_P, 1>;
4078 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4079 SSE_INTALU_ITINS_P, 1>;
4080 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4081 SSE_INTALUQ_ITINS_P, 1>;
4082 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4083 SSE_INTMUL_ITINS_P, 1>;
4084 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4085 SSE_INTMUL_ITINS_P, 1>;
4086 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4087 SSE_INTMUL_ITINS_P, 1>;
4088 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4089 SSE_INTALU_ITINS_P, 0>;
4090 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4091 SSE_INTALU_ITINS_P, 0>;
4092 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4093 SSE_INTALU_ITINS_P, 0>;
4094 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4095 SSE_INTALUQ_ITINS_P, 0>;
4096 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4097 SSE_INTALU_ITINS_P, 0>;
4098 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4099 SSE_INTALU_ITINS_P, 0>;
4100 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4101 SSE_INTALU_ITINS_P, 1>;
4102 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4103 SSE_INTALU_ITINS_P, 1>;
4104 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4105 SSE_INTALU_ITINS_P, 1>;
4106 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4107 SSE_INTALU_ITINS_P, 1>;
4110 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4111 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4112 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4113 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4114 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4115 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4116 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4117 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4118 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4119 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4120 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4121 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4122 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4123 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4124 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4125 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4126 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4127 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4128 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4129 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4131 let Predicates = [HasAVX] in
4132 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4133 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4135 let Predicates = [HasAVX2] in
4136 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4137 VR256, loadv4i64, i256mem,
4138 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4139 let Constraints = "$src1 = $dst" in
4140 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4141 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4143 //===---------------------------------------------------------------------===//
4144 // SSE2 - Packed Integer Logical Instructions
4145 //===---------------------------------------------------------------------===//
4147 let Predicates = [HasAVX] in {
4148 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4149 VR128, v8i16, v8i16, bc_v8i16,
4150 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4151 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4152 VR128, v4i32, v4i32, bc_v4i32,
4153 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4154 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4155 VR128, v2i64, v2i64, bc_v2i64,
4156 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4158 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4159 VR128, v8i16, v8i16, bc_v8i16,
4160 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4161 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4162 VR128, v4i32, v4i32, bc_v4i32,
4163 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4164 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4165 VR128, v2i64, v2i64, bc_v2i64,
4166 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4168 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4169 VR128, v8i16, v8i16, bc_v8i16,
4170 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4171 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4172 VR128, v4i32, v4i32, bc_v4i32,
4173 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4175 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4176 // 128-bit logical shifts.
4177 def VPSLLDQri : PDIi8<0x73, MRM7r,
4178 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4179 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4181 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4183 def VPSRLDQri : PDIi8<0x73, MRM3r,
4184 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4185 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4187 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4189 // PSRADQri doesn't exist in SSE[1-3].
4191 } // Predicates = [HasAVX]
4193 let Predicates = [HasAVX2] in {
4194 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4195 VR256, v16i16, v8i16, bc_v8i16,
4196 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4197 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4198 VR256, v8i32, v4i32, bc_v4i32,
4199 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4200 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4201 VR256, v4i64, v2i64, bc_v2i64,
4202 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4204 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4205 VR256, v16i16, v8i16, bc_v8i16,
4206 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4207 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4208 VR256, v8i32, v4i32, bc_v4i32,
4209 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4210 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4211 VR256, v4i64, v2i64, bc_v2i64,
4212 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4214 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4215 VR256, v16i16, v8i16, bc_v8i16,
4216 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4217 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4218 VR256, v8i32, v4i32, bc_v4i32,
4219 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4221 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4222 // 256-bit logical shifts.
4223 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4224 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4225 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4227 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4229 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4230 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4231 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4233 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4235 // PSRADQYri doesn't exist in SSE[1-3].
4237 } // Predicates = [HasAVX2]
4239 let Constraints = "$src1 = $dst" in {
4240 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4241 VR128, v8i16, v8i16, bc_v8i16,
4242 SSE_INTSHIFT_ITINS_P>;
4243 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4244 VR128, v4i32, v4i32, bc_v4i32,
4245 SSE_INTSHIFT_ITINS_P>;
4246 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4247 VR128, v2i64, v2i64, bc_v2i64,
4248 SSE_INTSHIFT_ITINS_P>;
4250 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4251 VR128, v8i16, v8i16, bc_v8i16,
4252 SSE_INTSHIFT_ITINS_P>;
4253 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4254 VR128, v4i32, v4i32, bc_v4i32,
4255 SSE_INTSHIFT_ITINS_P>;
4256 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4257 VR128, v2i64, v2i64, bc_v2i64,
4258 SSE_INTSHIFT_ITINS_P>;
4260 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4261 VR128, v8i16, v8i16, bc_v8i16,
4262 SSE_INTSHIFT_ITINS_P>;
4263 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4264 VR128, v4i32, v4i32, bc_v4i32,
4265 SSE_INTSHIFT_ITINS_P>;
4267 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4268 // 128-bit logical shifts.
4269 def PSLLDQri : PDIi8<0x73, MRM7r,
4270 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4271 "pslldq\t{$src2, $dst|$dst, $src2}",
4273 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4274 IIC_SSE_INTSHDQ_P_RI>;
4275 def PSRLDQri : PDIi8<0x73, MRM3r,
4276 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4277 "psrldq\t{$src2, $dst|$dst, $src2}",
4279 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4280 IIC_SSE_INTSHDQ_P_RI>;
4281 // PSRADQri doesn't exist in SSE[1-3].
4283 } // Constraints = "$src1 = $dst"
4285 let Predicates = [HasAVX] in {
4286 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4287 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4288 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4289 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4290 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4291 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4293 // Shift up / down and insert zero's.
4294 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4295 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4296 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4297 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4300 let Predicates = [HasAVX2] in {
4301 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4302 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4303 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4304 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4307 let Predicates = [UseSSE2] in {
4308 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4309 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4310 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4311 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4312 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4313 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4315 // Shift up / down and insert zero's.
4316 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4317 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4318 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4319 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4322 //===---------------------------------------------------------------------===//
4323 // SSE2 - Packed Integer Comparison Instructions
4324 //===---------------------------------------------------------------------===//
4326 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4327 SSE_INTALU_ITINS_P, 1>;
4328 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4329 SSE_INTALU_ITINS_P, 1>;
4330 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4331 SSE_INTALU_ITINS_P, 1>;
4332 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4333 SSE_INTALU_ITINS_P, 0>;
4334 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4335 SSE_INTALU_ITINS_P, 0>;
4336 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4337 SSE_INTALU_ITINS_P, 0>;
4339 //===---------------------------------------------------------------------===//
4340 // SSE2 - Packed Integer Shuffle Instructions
4341 //===---------------------------------------------------------------------===//
4343 let ExeDomain = SSEPackedInt in {
4344 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4346 let Predicates = [HasAVX] in {
4347 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4348 (ins VR128:$src1, i8imm:$src2),
4349 !strconcat("v", OpcodeStr,
4350 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4352 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4353 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4354 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4355 (ins i128mem:$src1, i8imm:$src2),
4356 !strconcat("v", OpcodeStr,
4357 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4359 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4360 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4361 Sched<[WriteShuffleLd]>;
4364 let Predicates = [HasAVX2] in {
4365 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4366 (ins VR256:$src1, i8imm:$src2),
4367 !strconcat("v", OpcodeStr,
4368 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4370 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4371 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4372 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4373 (ins i256mem:$src1, i8imm:$src2),
4374 !strconcat("v", OpcodeStr,
4375 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4377 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4378 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4379 Sched<[WriteShuffleLd]>;
4382 let Predicates = [UseSSE2] in {
4383 def ri : Ii8<0x70, MRMSrcReg,
4384 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4385 !strconcat(OpcodeStr,
4386 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4388 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4389 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4390 def mi : Ii8<0x70, MRMSrcMem,
4391 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4392 !strconcat(OpcodeStr,
4393 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4395 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4396 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4397 Sched<[WriteShuffleLd, ReadAfterLd]>;
4400 } // ExeDomain = SSEPackedInt
4402 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4403 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4404 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4406 let Predicates = [HasAVX] in {
4407 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4408 (VPSHUFDmi addr:$src1, imm:$imm)>;
4409 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4410 (VPSHUFDri VR128:$src1, imm:$imm)>;
4413 let Predicates = [UseSSE2] in {
4414 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4415 (PSHUFDmi addr:$src1, imm:$imm)>;
4416 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4417 (PSHUFDri VR128:$src1, imm:$imm)>;
4420 //===---------------------------------------------------------------------===//
4421 // Packed Integer Pack Instructions (SSE & AVX)
4422 //===---------------------------------------------------------------------===//
4424 let ExeDomain = SSEPackedInt in {
4425 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4426 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4428 def rr : PDI<opc, MRMSrcReg,
4429 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4431 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4432 !strconcat(OpcodeStr,
4433 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4435 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4436 Sched<[WriteShuffle]>;
4437 def rm : PDI<opc, MRMSrcMem,
4438 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4440 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4441 !strconcat(OpcodeStr,
4442 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4444 (OutVT (OpNode VR128:$src1,
4445 (bc_frag (memopv2i64 addr:$src2)))))]>,
4446 Sched<[WriteShuffleLd, ReadAfterLd]>;
4449 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4450 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4451 def Yrr : PDI<opc, MRMSrcReg,
4452 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4453 !strconcat(OpcodeStr,
4454 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4456 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4457 Sched<[WriteShuffle]>;
4458 def Yrm : PDI<opc, MRMSrcMem,
4459 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4460 !strconcat(OpcodeStr,
4461 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4463 (OutVT (OpNode VR256:$src1,
4464 (bc_frag (memopv4i64 addr:$src2)))))]>,
4465 Sched<[WriteShuffleLd, ReadAfterLd]>;
4468 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4469 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4471 def rr : SS48I<opc, MRMSrcReg,
4472 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4474 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4475 !strconcat(OpcodeStr,
4476 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4478 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4479 Sched<[WriteShuffle]>;
4480 def rm : SS48I<opc, MRMSrcMem,
4481 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4483 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4484 !strconcat(OpcodeStr,
4485 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4487 (OutVT (OpNode VR128:$src1,
4488 (bc_frag (memopv2i64 addr:$src2)))))]>,
4489 Sched<[WriteShuffleLd, ReadAfterLd]>;
4492 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4493 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4494 def Yrr : SS48I<opc, MRMSrcReg,
4495 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4496 !strconcat(OpcodeStr,
4497 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4499 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4500 Sched<[WriteShuffle]>;
4501 def Yrm : SS48I<opc, MRMSrcMem,
4502 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4503 !strconcat(OpcodeStr,
4504 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4506 (OutVT (OpNode VR256:$src1,
4507 (bc_frag (memopv4i64 addr:$src2)))))]>,
4508 Sched<[WriteShuffleLd, ReadAfterLd]>;
4511 let Predicates = [HasAVX] in {
4512 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4513 bc_v8i16, 0>, VEX_4V;
4514 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4515 bc_v4i32, 0>, VEX_4V;
4517 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4518 bc_v8i16, 0>, VEX_4V;
4519 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4520 bc_v4i32, 0>, VEX_4V;
4523 let Predicates = [HasAVX2] in {
4524 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4525 bc_v16i16>, VEX_4V, VEX_L;
4526 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4527 bc_v8i32>, VEX_4V, VEX_L;
4529 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4530 bc_v16i16>, VEX_4V, VEX_L;
4531 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4532 bc_v8i32>, VEX_4V, VEX_L;
4535 let Constraints = "$src1 = $dst" in {
4536 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4538 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4541 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4544 let Predicates = [HasSSE41] in
4545 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4548 } // ExeDomain = SSEPackedInt
4550 //===---------------------------------------------------------------------===//
4551 // SSE2 - Packed Integer Unpack Instructions
4552 //===---------------------------------------------------------------------===//
4554 let ExeDomain = SSEPackedInt in {
4555 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4556 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4557 def rr : PDI<opc, MRMSrcReg,
4558 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4560 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4561 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4562 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4563 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4564 def rm : PDI<opc, MRMSrcMem,
4565 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4567 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4568 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4569 [(set VR128:$dst, (OpNode VR128:$src1,
4570 (bc_frag (memopv2i64
4573 Sched<[WriteShuffleLd, ReadAfterLd]>;
4576 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4577 SDNode OpNode, PatFrag bc_frag> {
4578 def Yrr : PDI<opc, MRMSrcReg,
4579 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4580 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4581 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4582 Sched<[WriteShuffle]>;
4583 def Yrm : PDI<opc, MRMSrcMem,
4584 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4585 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4586 [(set VR256:$dst, (OpNode VR256:$src1,
4587 (bc_frag (memopv4i64 addr:$src2))))]>,
4588 Sched<[WriteShuffleLd, ReadAfterLd]>;
4591 let Predicates = [HasAVX] in {
4592 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4593 bc_v16i8, 0>, VEX_4V;
4594 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4595 bc_v8i16, 0>, VEX_4V;
4596 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4597 bc_v4i32, 0>, VEX_4V;
4598 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4599 bc_v2i64, 0>, VEX_4V;
4601 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4602 bc_v16i8, 0>, VEX_4V;
4603 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4604 bc_v8i16, 0>, VEX_4V;
4605 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4606 bc_v4i32, 0>, VEX_4V;
4607 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4608 bc_v2i64, 0>, VEX_4V;
4611 let Predicates = [HasAVX2] in {
4612 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4613 bc_v32i8>, VEX_4V, VEX_L;
4614 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4615 bc_v16i16>, VEX_4V, VEX_L;
4616 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4617 bc_v8i32>, VEX_4V, VEX_L;
4618 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4619 bc_v4i64>, VEX_4V, VEX_L;
4621 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4622 bc_v32i8>, VEX_4V, VEX_L;
4623 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4624 bc_v16i16>, VEX_4V, VEX_L;
4625 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4626 bc_v8i32>, VEX_4V, VEX_L;
4627 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4628 bc_v4i64>, VEX_4V, VEX_L;
4631 let Constraints = "$src1 = $dst" in {
4632 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4634 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4636 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4638 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4641 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4643 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4645 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4647 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4650 } // ExeDomain = SSEPackedInt
4652 //===---------------------------------------------------------------------===//
4653 // SSE2 - Packed Integer Extract and Insert
4654 //===---------------------------------------------------------------------===//
4656 let ExeDomain = SSEPackedInt in {
4657 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4658 def rri : Ii8<0xC4, MRMSrcReg,
4659 (outs VR128:$dst), (ins VR128:$src1,
4660 GR32orGR64:$src2, i32i8imm:$src3),
4662 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4663 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4665 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4666 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4667 def rmi : Ii8<0xC4, MRMSrcMem,
4668 (outs VR128:$dst), (ins VR128:$src1,
4669 i16mem:$src2, i32i8imm:$src3),
4671 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4672 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4674 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4675 imm:$src3))], IIC_SSE_PINSRW>,
4676 Sched<[WriteShuffleLd, ReadAfterLd]>;
4680 let Predicates = [HasAVX] in
4681 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4682 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4683 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4684 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4685 imm:$src2))]>, PD, VEX,
4686 Sched<[WriteShuffle]>;
4687 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4688 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4689 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4690 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4691 imm:$src2))], IIC_SSE_PEXTRW>,
4692 Sched<[WriteShuffleLd, ReadAfterLd]>;
4695 let Predicates = [HasAVX] in
4696 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4698 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4699 defm PINSRW : sse2_pinsrw, PD;
4701 } // ExeDomain = SSEPackedInt
4703 //===---------------------------------------------------------------------===//
4704 // SSE2 - Packed Mask Creation
4705 //===---------------------------------------------------------------------===//
4707 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4709 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4711 "pmovmskb\t{$src, $dst|$dst, $src}",
4712 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4713 IIC_SSE_MOVMSK>, VEX;
4715 let Predicates = [HasAVX2] in {
4716 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4718 "pmovmskb\t{$src, $dst|$dst, $src}",
4719 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4723 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4724 "pmovmskb\t{$src, $dst|$dst, $src}",
4725 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4728 } // ExeDomain = SSEPackedInt
4730 //===---------------------------------------------------------------------===//
4731 // SSE2 - Conditional Store
4732 //===---------------------------------------------------------------------===//
4734 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4736 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4737 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4738 (ins VR128:$src, VR128:$mask),
4739 "maskmovdqu\t{$mask, $src|$src, $mask}",
4740 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4741 IIC_SSE_MASKMOV>, VEX;
4742 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4743 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4744 (ins VR128:$src, VR128:$mask),
4745 "maskmovdqu\t{$mask, $src|$src, $mask}",
4746 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4747 IIC_SSE_MASKMOV>, VEX;
4749 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4750 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4751 "maskmovdqu\t{$mask, $src|$src, $mask}",
4752 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4754 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4755 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4756 "maskmovdqu\t{$mask, $src|$src, $mask}",
4757 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4760 } // ExeDomain = SSEPackedInt
4762 //===---------------------------------------------------------------------===//
4763 // SSE2 - Move Doubleword
4764 //===---------------------------------------------------------------------===//
4766 //===---------------------------------------------------------------------===//
4767 // Move Int Doubleword to Packed Double Int
4769 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4770 "movd\t{$src, $dst|$dst, $src}",
4772 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4773 VEX, Sched<[WriteMove]>;
4774 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4775 "movd\t{$src, $dst|$dst, $src}",
4777 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4779 VEX, Sched<[WriteLoad]>;
4780 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4781 "movq\t{$src, $dst|$dst, $src}",
4783 (v2i64 (scalar_to_vector GR64:$src)))],
4784 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4785 let isCodeGenOnly = 1 in
4786 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4787 "movq\t{$src, $dst|$dst, $src}",
4788 [(set FR64:$dst, (bitconvert GR64:$src))],
4789 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4791 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4792 "movd\t{$src, $dst|$dst, $src}",
4794 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4796 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4797 "movd\t{$src, $dst|$dst, $src}",
4799 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4800 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4801 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4802 "mov{d|q}\t{$src, $dst|$dst, $src}",
4804 (v2i64 (scalar_to_vector GR64:$src)))],
4805 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4806 let isCodeGenOnly = 1 in
4807 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4808 "mov{d|q}\t{$src, $dst|$dst, $src}",
4809 [(set FR64:$dst, (bitconvert GR64:$src))],
4810 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4812 //===---------------------------------------------------------------------===//
4813 // Move Int Doubleword to Single Scalar
4815 let isCodeGenOnly = 1 in {
4816 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4817 "movd\t{$src, $dst|$dst, $src}",
4818 [(set FR32:$dst, (bitconvert GR32:$src))],
4819 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4821 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4822 "movd\t{$src, $dst|$dst, $src}",
4823 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4825 VEX, Sched<[WriteLoad]>;
4826 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4827 "movd\t{$src, $dst|$dst, $src}",
4828 [(set FR32:$dst, (bitconvert GR32:$src))],
4829 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4831 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4832 "movd\t{$src, $dst|$dst, $src}",
4833 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4834 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4837 //===---------------------------------------------------------------------===//
4838 // Move Packed Doubleword Int to Packed Double Int
4840 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4841 "movd\t{$src, $dst|$dst, $src}",
4842 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4843 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4845 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4846 (ins i32mem:$dst, VR128:$src),
4847 "movd\t{$src, $dst|$dst, $src}",
4848 [(store (i32 (vector_extract (v4i32 VR128:$src),
4849 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4850 VEX, Sched<[WriteStore]>;
4851 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4852 "movd\t{$src, $dst|$dst, $src}",
4853 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4854 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4856 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4857 "movd\t{$src, $dst|$dst, $src}",
4858 [(store (i32 (vector_extract (v4i32 VR128:$src),
4859 (iPTR 0))), addr:$dst)],
4860 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4862 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4863 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4865 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4866 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4868 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4869 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4871 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4872 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4874 //===---------------------------------------------------------------------===//
4875 // Move Packed Doubleword Int first element to Doubleword Int
4877 let SchedRW = [WriteMove] in {
4878 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4879 "movq\t{$src, $dst|$dst, $src}",
4880 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4885 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4886 "mov{d|q}\t{$src, $dst|$dst, $src}",
4887 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4892 //===---------------------------------------------------------------------===//
4893 // Bitcast FR64 <-> GR64
4895 let isCodeGenOnly = 1 in {
4896 let Predicates = [UseAVX] in
4897 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4898 "movq\t{$src, $dst|$dst, $src}",
4899 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4900 VEX, Sched<[WriteLoad]>;
4901 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4902 "movq\t{$src, $dst|$dst, $src}",
4903 [(set GR64:$dst, (bitconvert FR64:$src))],
4904 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4905 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4906 "movq\t{$src, $dst|$dst, $src}",
4907 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4908 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4910 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4911 "movq\t{$src, $dst|$dst, $src}",
4912 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4913 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4914 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4915 "mov{d|q}\t{$src, $dst|$dst, $src}",
4916 [(set GR64:$dst, (bitconvert FR64:$src))],
4917 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4918 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4919 "movq\t{$src, $dst|$dst, $src}",
4920 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4921 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4924 //===---------------------------------------------------------------------===//
4925 // Move Scalar Single to Double Int
4927 let isCodeGenOnly = 1 in {
4928 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4929 "movd\t{$src, $dst|$dst, $src}",
4930 [(set GR32:$dst, (bitconvert FR32:$src))],
4931 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4932 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4933 "movd\t{$src, $dst|$dst, $src}",
4934 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4935 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4936 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4937 "movd\t{$src, $dst|$dst, $src}",
4938 [(set GR32:$dst, (bitconvert FR32:$src))],
4939 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4940 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4941 "movd\t{$src, $dst|$dst, $src}",
4942 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4943 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4946 //===---------------------------------------------------------------------===//
4947 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4949 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4950 let AddedComplexity = 15 in {
4951 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4952 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4953 [(set VR128:$dst, (v2i64 (X86vzmovl
4954 (v2i64 (scalar_to_vector GR64:$src)))))],
4957 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4958 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4959 [(set VR128:$dst, (v2i64 (X86vzmovl
4960 (v2i64 (scalar_to_vector GR64:$src)))))],
4963 } // isCodeGenOnly, SchedRW
4965 let Predicates = [UseAVX] in {
4966 let AddedComplexity = 15 in
4967 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4968 (VMOVDI2PDIrr GR32:$src)>;
4970 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4971 let AddedComplexity = 20 in {
4972 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4973 (VMOVDI2PDIrm addr:$src)>;
4974 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4975 (VMOVDI2PDIrm addr:$src)>;
4976 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4977 (VMOVDI2PDIrm addr:$src)>;
4979 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4980 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4981 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4982 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4983 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4984 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4985 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4988 let Predicates = [UseSSE2] in {
4989 let AddedComplexity = 15 in
4990 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4991 (MOVDI2PDIrr GR32:$src)>;
4993 let AddedComplexity = 20 in {
4994 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4995 (MOVDI2PDIrm addr:$src)>;
4996 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4997 (MOVDI2PDIrm addr:$src)>;
4998 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4999 (MOVDI2PDIrm addr:$src)>;
5003 // These are the correct encodings of the instructions so that we know how to
5004 // read correct assembly, even though we continue to emit the wrong ones for
5005 // compatibility with Darwin's buggy assembler.
5006 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5007 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5008 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5009 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5010 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
5011 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5012 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5013 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5014 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5016 //===---------------------------------------------------------------------===//
5017 // SSE2 - Move Quadword
5018 //===---------------------------------------------------------------------===//
5020 //===---------------------------------------------------------------------===//
5021 // Move Quadword Int to Packed Quadword Int
5024 let SchedRW = [WriteLoad] in {
5025 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5026 "vmovq\t{$src, $dst|$dst, $src}",
5028 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
5029 VEX, Requires<[UseAVX]>;
5030 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5031 "movq\t{$src, $dst|$dst, $src}",
5033 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
5035 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
5038 //===---------------------------------------------------------------------===//
5039 // Move Packed Quadword Int to Quadword Int
5041 let SchedRW = [WriteStore] in {
5042 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5043 "movq\t{$src, $dst|$dst, $src}",
5044 [(store (i64 (vector_extract (v2i64 VR128:$src),
5045 (iPTR 0))), addr:$dst)],
5046 IIC_SSE_MOVDQ>, VEX;
5047 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5048 "movq\t{$src, $dst|$dst, $src}",
5049 [(store (i64 (vector_extract (v2i64 VR128:$src),
5050 (iPTR 0))), addr:$dst)],
5054 // For disassembler only
5055 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5056 SchedRW = [WriteVecLogic] in {
5057 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5058 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5059 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5060 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5063 //===---------------------------------------------------------------------===//
5064 // Store / copy lower 64-bits of a XMM register.
5066 let Predicates = [UseAVX] in
5067 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5068 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5069 let Predicates = [UseSSE2] in
5070 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5071 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5073 let isCodeGenOnly = 1, AddedComplexity = 20 in {
5074 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5075 "vmovq\t{$src, $dst|$dst, $src}",
5077 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5078 (loadi64 addr:$src))))))],
5080 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5082 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5083 "movq\t{$src, $dst|$dst, $src}",
5085 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5086 (loadi64 addr:$src))))))],
5088 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5091 let Predicates = [UseAVX], AddedComplexity = 20 in {
5092 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5093 (VMOVZQI2PQIrm addr:$src)>;
5094 def : Pat<(v2i64 (X86vzload addr:$src)),
5095 (VMOVZQI2PQIrm addr:$src)>;
5098 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5099 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5100 (MOVZQI2PQIrm addr:$src)>;
5101 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5104 let Predicates = [HasAVX] in {
5105 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5106 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5107 def : Pat<(v4i64 (X86vzload addr:$src)),
5108 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5111 //===---------------------------------------------------------------------===//
5112 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5113 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5115 let SchedRW = [WriteVecLogic] in {
5116 let AddedComplexity = 15 in
5117 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5118 "vmovq\t{$src, $dst|$dst, $src}",
5119 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5121 XS, VEX, Requires<[UseAVX]>;
5122 let AddedComplexity = 15 in
5123 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5124 "movq\t{$src, $dst|$dst, $src}",
5125 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5127 XS, Requires<[UseSSE2]>;
5130 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5131 let AddedComplexity = 20 in
5132 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5133 "vmovq\t{$src, $dst|$dst, $src}",
5134 [(set VR128:$dst, (v2i64 (X86vzmovl
5135 (loadv2i64 addr:$src))))],
5137 XS, VEX, Requires<[UseAVX]>;
5138 let AddedComplexity = 20 in {
5139 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5140 "movq\t{$src, $dst|$dst, $src}",
5141 [(set VR128:$dst, (v2i64 (X86vzmovl
5142 (loadv2i64 addr:$src))))],
5144 XS, Requires<[UseSSE2]>;
5146 } // isCodeGenOnly, SchedRW
5148 let AddedComplexity = 20 in {
5149 let Predicates = [UseAVX] in {
5150 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5151 (VMOVZPQILo2PQIrr VR128:$src)>;
5153 let Predicates = [UseSSE2] in {
5154 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5155 (MOVZPQILo2PQIrr VR128:$src)>;
5159 //===---------------------------------------------------------------------===//
5160 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5161 //===---------------------------------------------------------------------===//
5162 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5163 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5164 X86MemOperand x86memop> {
5165 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5166 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5167 [(set RC:$dst, (vt (OpNode RC:$src)))],
5168 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5169 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5170 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5171 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5172 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5175 let Predicates = [HasAVX] in {
5176 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5177 v4f32, VR128, loadv4f32, f128mem>, VEX;
5178 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5179 v4f32, VR128, loadv4f32, f128mem>, VEX;
5180 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5181 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5182 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5183 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5185 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5186 memopv4f32, f128mem>;
5187 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5188 memopv4f32, f128mem>;
5190 let Predicates = [HasAVX] in {
5191 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5192 (VMOVSHDUPrr VR128:$src)>;
5193 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5194 (VMOVSHDUPrm addr:$src)>;
5195 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5196 (VMOVSLDUPrr VR128:$src)>;
5197 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5198 (VMOVSLDUPrm addr:$src)>;
5199 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5200 (VMOVSHDUPYrr VR256:$src)>;
5201 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5202 (VMOVSHDUPYrm addr:$src)>;
5203 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5204 (VMOVSLDUPYrr VR256:$src)>;
5205 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5206 (VMOVSLDUPYrm addr:$src)>;
5209 let Predicates = [UseSSE3] in {
5210 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5211 (MOVSHDUPrr VR128:$src)>;
5212 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5213 (MOVSHDUPrm addr:$src)>;
5214 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5215 (MOVSLDUPrr VR128:$src)>;
5216 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5217 (MOVSLDUPrm addr:$src)>;
5220 //===---------------------------------------------------------------------===//
5221 // SSE3 - Replicate Double FP - MOVDDUP
5222 //===---------------------------------------------------------------------===//
5224 multiclass sse3_replicate_dfp<string OpcodeStr> {
5225 let neverHasSideEffects = 1 in
5226 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5227 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5228 [], IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5229 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5230 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5233 (scalar_to_vector (loadf64 addr:$src)))))],
5234 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5237 // FIXME: Merge with above classe when there're patterns for the ymm version
5238 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5239 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5240 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5241 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5242 Sched<[WriteFShuffle]>;
5243 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5244 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5247 (scalar_to_vector (loadf64 addr:$src)))))]>,
5251 let Predicates = [HasAVX] in {
5252 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5253 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5256 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5258 let Predicates = [HasAVX] in {
5259 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5260 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5261 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5262 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5263 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5264 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5265 def : Pat<(X86Movddup (bc_v2f64
5266 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5267 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5270 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5271 (VMOVDDUPYrm addr:$src)>;
5272 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5273 (VMOVDDUPYrm addr:$src)>;
5274 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5275 (VMOVDDUPYrm addr:$src)>;
5276 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5277 (VMOVDDUPYrr VR256:$src)>;
5280 let Predicates = [UseSSE3] in {
5281 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5282 (MOVDDUPrm addr:$src)>;
5283 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5284 (MOVDDUPrm addr:$src)>;
5285 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5286 (MOVDDUPrm addr:$src)>;
5287 def : Pat<(X86Movddup (bc_v2f64
5288 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5289 (MOVDDUPrm addr:$src)>;
5292 //===---------------------------------------------------------------------===//
5293 // SSE3 - Move Unaligned Integer
5294 //===---------------------------------------------------------------------===//
5296 let SchedRW = [WriteLoad] in {
5297 let Predicates = [HasAVX] in {
5298 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5299 "vlddqu\t{$src, $dst|$dst, $src}",
5300 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5301 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5302 "vlddqu\t{$src, $dst|$dst, $src}",
5303 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5306 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5307 "lddqu\t{$src, $dst|$dst, $src}",
5308 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5312 //===---------------------------------------------------------------------===//
5313 // SSE3 - Arithmetic
5314 //===---------------------------------------------------------------------===//
5316 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5317 X86MemOperand x86memop, OpndItins itins,
5319 def rr : I<0xD0, MRMSrcReg,
5320 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5324 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5325 Sched<[itins.Sched]>;
5326 def rm : I<0xD0, MRMSrcMem,
5327 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5329 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5330 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5331 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5332 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5335 let Predicates = [HasAVX] in {
5336 let ExeDomain = SSEPackedSingle in {
5337 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5338 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5339 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5340 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5342 let ExeDomain = SSEPackedDouble in {
5343 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5344 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5345 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5346 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5349 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5350 let ExeDomain = SSEPackedSingle in
5351 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5352 f128mem, SSE_ALU_F32P>, XD;
5353 let ExeDomain = SSEPackedDouble in
5354 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5355 f128mem, SSE_ALU_F64P>, PD;
5358 // Patterns used to select 'addsub' instructions.
5359 let Predicates = [HasAVX] in {
5360 // Constant 170 corresponds to the binary mask '10101010'.
5361 // When used as a blend mask, it allows selecting eight elements from two
5362 // input vectors as follow:
5363 // - Even-numbered values in the destination are copied from
5364 // the corresponding elements in the first input vector;
5365 // - Odd-numbered values in the destination are copied from
5366 // the corresponding elements in the second input vector.
5368 def : Pat<(v8f32 (X86Blendi (v8f32 (fsub VR256:$lhs, VR256:$rhs)),
5369 (v8f32 (fadd VR256:$lhs, VR256:$rhs)), (i32 170))),
5370 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5372 // Constant 10 corresponds to the binary mask '1010'.
5373 // In the two pattens below, constant 10 is used as a blend mask to select
5374 // - the 1st and 3rd element from the first input vector (the 'fsub' node);
5375 // - the 2nd and 4th element from the second input vector (the 'fadd' node).
5377 def : Pat<(v4f64 (X86Shufp (v4f64 (fsub VR256:$lhs, VR256:$rhs)),
5378 (v4f64 (fadd VR256:$lhs, VR256:$rhs)), (i8 10))),
5379 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5380 def : Pat<(v4f32 (X86Blendi (v4f32 (fsub VR128:$lhs, VR128:$rhs)),
5381 (v4f32 (fadd VR128:$lhs, VR128:$rhs)), (i32 10))),
5382 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5384 def : Pat<(v2f64 (X86Movsd (v2f64 (fadd VR128:$lhs, VR128:$rhs)),
5385 (v2f64 (fsub VR128:$lhs, VR128:$rhs)))),
5386 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5389 let Predicates = [UseSSE3] in {
5390 // Constant 10 corresponds to the binary mask '1010'.
5391 // In the pattern below, it is used as a blend mask to select:
5392 // - the 1st and 3rd element from the first input vector (the fsub node);
5393 // - the 2nd and 4th element from the second input vector (the fadd node).
5395 def : Pat<(v4f32 (X86Blendi (v4f32 (fsub VR128:$lhs, VR128:$rhs)),
5396 (v4f32 (fadd VR128:$lhs, VR128:$rhs)), (i32 10))),
5397 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5399 def : Pat<(v2f64 (X86Movsd (v2f64 (fadd VR128:$lhs, VR128:$rhs)),
5400 (v2f64 (fsub VR128:$lhs, VR128:$rhs)))),
5401 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5404 //===---------------------------------------------------------------------===//
5405 // SSE3 Instructions
5406 //===---------------------------------------------------------------------===//
5409 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5410 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5411 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5413 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5414 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5415 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5418 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5420 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5421 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5422 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5423 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5425 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5426 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5427 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5429 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5430 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5431 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5434 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5436 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5437 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5438 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5439 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5442 let Predicates = [HasAVX] in {
5443 let ExeDomain = SSEPackedSingle in {
5444 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5445 X86fhadd, 0>, VEX_4V;
5446 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5447 X86fhsub, 0>, VEX_4V;
5448 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5449 X86fhadd, 0>, VEX_4V, VEX_L;
5450 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5451 X86fhsub, 0>, VEX_4V, VEX_L;
5453 let ExeDomain = SSEPackedDouble in {
5454 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5455 X86fhadd, 0>, VEX_4V;
5456 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5457 X86fhsub, 0>, VEX_4V;
5458 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5459 X86fhadd, 0>, VEX_4V, VEX_L;
5460 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5461 X86fhsub, 0>, VEX_4V, VEX_L;
5465 let Constraints = "$src1 = $dst" in {
5466 let ExeDomain = SSEPackedSingle in {
5467 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5468 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5470 let ExeDomain = SSEPackedDouble in {
5471 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5472 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5476 //===---------------------------------------------------------------------===//
5477 // SSSE3 - Packed Absolute Instructions
5478 //===---------------------------------------------------------------------===//
5481 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5482 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5483 Intrinsic IntId128> {
5484 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5486 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5487 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5488 Sched<[WriteVecALU]>;
5490 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5492 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5495 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5496 Sched<[WriteVecALULd]>;
5499 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5500 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5501 Intrinsic IntId256> {
5502 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5504 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5505 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5506 Sched<[WriteVecALU]>;
5508 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5510 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5513 (bitconvert (memopv4i64 addr:$src))))]>,
5514 Sched<[WriteVecALULd]>;
5517 // Helper fragments to match sext vXi1 to vXiY.
5518 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5520 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5521 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5522 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5524 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5525 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5527 let Predicates = [HasAVX] in {
5528 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5529 int_x86_ssse3_pabs_b_128>, VEX;
5530 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5531 int_x86_ssse3_pabs_w_128>, VEX;
5532 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5533 int_x86_ssse3_pabs_d_128>, VEX;
5536 (bc_v2i64 (v16i1sextv16i8)),
5537 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5538 (VPABSBrr128 VR128:$src)>;
5540 (bc_v2i64 (v8i1sextv8i16)),
5541 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5542 (VPABSWrr128 VR128:$src)>;
5544 (bc_v2i64 (v4i1sextv4i32)),
5545 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5546 (VPABSDrr128 VR128:$src)>;
5549 let Predicates = [HasAVX2] in {
5550 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5551 int_x86_avx2_pabs_b>, VEX, VEX_L;
5552 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5553 int_x86_avx2_pabs_w>, VEX, VEX_L;
5554 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5555 int_x86_avx2_pabs_d>, VEX, VEX_L;
5558 (bc_v4i64 (v32i1sextv32i8)),
5559 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5560 (VPABSBrr256 VR256:$src)>;
5562 (bc_v4i64 (v16i1sextv16i16)),
5563 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5564 (VPABSWrr256 VR256:$src)>;
5566 (bc_v4i64 (v8i1sextv8i32)),
5567 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5568 (VPABSDrr256 VR256:$src)>;
5571 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5572 int_x86_ssse3_pabs_b_128>;
5573 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5574 int_x86_ssse3_pabs_w_128>;
5575 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5576 int_x86_ssse3_pabs_d_128>;
5578 let Predicates = [HasSSSE3] in {
5580 (bc_v2i64 (v16i1sextv16i8)),
5581 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5582 (PABSBrr128 VR128:$src)>;
5584 (bc_v2i64 (v8i1sextv8i16)),
5585 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5586 (PABSWrr128 VR128:$src)>;
5588 (bc_v2i64 (v4i1sextv4i32)),
5589 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5590 (PABSDrr128 VR128:$src)>;
5593 //===---------------------------------------------------------------------===//
5594 // SSSE3 - Packed Binary Operator Instructions
5595 //===---------------------------------------------------------------------===//
5597 let Sched = WriteVecALU in {
5598 def SSE_PHADDSUBD : OpndItins<
5599 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5601 def SSE_PHADDSUBSW : OpndItins<
5602 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5604 def SSE_PHADDSUBW : OpndItins<
5605 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5608 let Sched = WriteShuffle in
5609 def SSE_PSHUFB : OpndItins<
5610 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5612 let Sched = WriteVecALU in
5613 def SSE_PSIGN : OpndItins<
5614 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5616 let Sched = WriteVecIMul in
5617 def SSE_PMULHRSW : OpndItins<
5618 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5621 /// SS3I_binop_rm - Simple SSSE3 bin op
5622 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5623 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5624 X86MemOperand x86memop, OpndItins itins,
5626 let isCommutable = 1 in
5627 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5628 (ins RC:$src1, RC:$src2),
5630 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5631 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5632 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5633 Sched<[itins.Sched]>;
5634 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5635 (ins RC:$src1, x86memop:$src2),
5637 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5638 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5640 (OpVT (OpNode RC:$src1,
5641 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5642 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5645 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5646 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5647 Intrinsic IntId128, OpndItins itins,
5649 let isCommutable = 1 in
5650 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5651 (ins VR128:$src1, VR128:$src2),
5653 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5654 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5655 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5656 Sched<[itins.Sched]>;
5657 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5658 (ins VR128:$src1, i128mem:$src2),
5660 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5661 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5663 (IntId128 VR128:$src1,
5664 (bitconvert (memopv2i64 addr:$src2))))]>,
5665 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5668 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5670 X86FoldableSchedWrite Sched> {
5671 let isCommutable = 1 in
5672 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5673 (ins VR256:$src1, VR256:$src2),
5674 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5675 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5677 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5678 (ins VR256:$src1, i256mem:$src2),
5679 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5681 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5682 Sched<[Sched.Folded, ReadAfterLd]>;
5685 let ImmT = NoImm, Predicates = [HasAVX] in {
5686 let isCommutable = 0 in {
5687 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5689 SSE_PHADDSUBW, 0>, VEX_4V;
5690 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5692 SSE_PHADDSUBD, 0>, VEX_4V;
5693 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5695 SSE_PHADDSUBW, 0>, VEX_4V;
5696 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5698 SSE_PHADDSUBD, 0>, VEX_4V;
5699 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5701 SSE_PSIGN, 0>, VEX_4V;
5702 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5704 SSE_PSIGN, 0>, VEX_4V;
5705 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5707 SSE_PSIGN, 0>, VEX_4V;
5708 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5710 SSE_PSHUFB, 0>, VEX_4V;
5711 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5712 int_x86_ssse3_phadd_sw_128,
5713 SSE_PHADDSUBSW, 0>, VEX_4V;
5714 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5715 int_x86_ssse3_phsub_sw_128,
5716 SSE_PHADDSUBSW, 0>, VEX_4V;
5717 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5718 int_x86_ssse3_pmadd_ub_sw_128,
5719 SSE_PMADD, 0>, VEX_4V;
5721 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5722 int_x86_ssse3_pmul_hr_sw_128,
5723 SSE_PMULHRSW, 0>, VEX_4V;
5726 let ImmT = NoImm, Predicates = [HasAVX2] in {
5727 let isCommutable = 0 in {
5728 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5730 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5731 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5733 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5734 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5736 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5737 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5739 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5740 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5742 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5743 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5745 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5746 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5748 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5749 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5751 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5752 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5753 int_x86_avx2_phadd_sw,
5754 WriteVecALU>, VEX_4V, VEX_L;
5755 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5756 int_x86_avx2_phsub_sw,
5757 WriteVecALU>, VEX_4V, VEX_L;
5758 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5759 int_x86_avx2_pmadd_ub_sw,
5760 WriteVecIMul>, VEX_4V, VEX_L;
5762 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5763 int_x86_avx2_pmul_hr_sw,
5764 WriteVecIMul>, VEX_4V, VEX_L;
5767 // None of these have i8 immediate fields.
5768 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5769 let isCommutable = 0 in {
5770 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5771 memopv2i64, i128mem, SSE_PHADDSUBW>;
5772 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5773 memopv2i64, i128mem, SSE_PHADDSUBD>;
5774 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5775 memopv2i64, i128mem, SSE_PHADDSUBW>;
5776 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5777 memopv2i64, i128mem, SSE_PHADDSUBD>;
5778 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5779 memopv2i64, i128mem, SSE_PSIGN>;
5780 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5781 memopv2i64, i128mem, SSE_PSIGN>;
5782 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5783 memopv2i64, i128mem, SSE_PSIGN>;
5784 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5785 memopv2i64, i128mem, SSE_PSHUFB>;
5786 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5787 int_x86_ssse3_phadd_sw_128,
5789 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5790 int_x86_ssse3_phsub_sw_128,
5792 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5793 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5795 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5796 int_x86_ssse3_pmul_hr_sw_128,
5800 //===---------------------------------------------------------------------===//
5801 // SSSE3 - Packed Align Instruction Patterns
5802 //===---------------------------------------------------------------------===//
5804 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5805 let neverHasSideEffects = 1 in {
5806 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5807 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5809 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5811 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5812 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5814 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5815 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5817 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5819 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5820 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5824 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5825 let neverHasSideEffects = 1 in {
5826 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5827 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5829 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5830 []>, Sched<[WriteShuffle]>;
5832 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5833 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5835 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5836 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5840 let Predicates = [HasAVX] in
5841 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5842 let Predicates = [HasAVX2] in
5843 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5844 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5845 defm PALIGN : ssse3_palignr<"palignr">;
5847 let Predicates = [HasAVX2] in {
5848 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5849 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5850 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5851 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5852 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5853 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5854 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5855 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5858 let Predicates = [HasAVX] in {
5859 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5860 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5861 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5862 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5863 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5864 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5865 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5866 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5869 let Predicates = [UseSSSE3] in {
5870 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5871 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5872 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5873 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5874 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5875 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5876 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5877 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5880 //===---------------------------------------------------------------------===//
5881 // SSSE3 - Thread synchronization
5882 //===---------------------------------------------------------------------===//
5884 let SchedRW = [WriteSystem] in {
5885 let usesCustomInserter = 1 in {
5886 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5887 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5888 Requires<[HasSSE3]>;
5891 let Uses = [EAX, ECX, EDX] in
5892 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5893 TB, Requires<[HasSSE3]>;
5894 let Uses = [ECX, EAX] in
5895 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5896 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5897 TB, Requires<[HasSSE3]>;
5900 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5901 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5903 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5904 Requires<[Not64BitMode]>;
5905 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5906 Requires<[In64BitMode]>;
5908 //===----------------------------------------------------------------------===//
5909 // SSE4.1 - Packed Move with Sign/Zero Extend
5910 //===----------------------------------------------------------------------===//
5912 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5913 OpndItins itins = DEFAULT_ITINS> {
5914 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5915 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5916 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>,
5917 Sched<[itins.Sched]>;
5919 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5920 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5922 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5923 itins.rm>, Sched<[itins.Sched.Folded]>;
5926 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5927 Intrinsic IntId, X86FoldableSchedWrite Sched> {
5928 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5929 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5930 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
5932 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5933 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5934 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5935 Sched<[Sched.Folded]>;
5938 let Predicates = [HasAVX] in {
5939 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5940 int_x86_sse41_pmovsxbw,
5941 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5942 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5943 int_x86_sse41_pmovsxwd,
5944 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5945 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5946 int_x86_sse41_pmovsxdq,
5947 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5948 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5949 int_x86_sse41_pmovzxbw,
5950 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5951 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5952 int_x86_sse41_pmovzxwd,
5953 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5954 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5955 int_x86_sse41_pmovzxdq,
5956 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5959 let Predicates = [HasAVX2] in {
5960 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5961 int_x86_avx2_pmovsxbw,
5962 WriteShuffle>, VEX, VEX_L;
5963 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5964 int_x86_avx2_pmovsxwd,
5965 WriteShuffle>, VEX, VEX_L;
5966 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5967 int_x86_avx2_pmovsxdq,
5968 WriteShuffle>, VEX, VEX_L;
5969 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5970 int_x86_avx2_pmovzxbw,
5971 WriteShuffle>, VEX, VEX_L;
5972 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5973 int_x86_avx2_pmovzxwd,
5974 WriteShuffle>, VEX, VEX_L;
5975 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5976 int_x86_avx2_pmovzxdq,
5977 WriteShuffle>, VEX, VEX_L;
5980 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw,
5981 SSE_INTALU_ITINS_SHUFF_P>;
5982 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd,
5983 SSE_INTALU_ITINS_SHUFF_P>;
5984 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq,
5985 SSE_INTALU_ITINS_SHUFF_P>;
5986 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw,
5987 SSE_INTALU_ITINS_SHUFF_P>;
5988 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd,
5989 SSE_INTALU_ITINS_SHUFF_P>;
5990 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq,
5991 SSE_INTALU_ITINS_SHUFF_P>;
5993 let Predicates = [HasAVX] in {
5994 // Common patterns involving scalar load.
5995 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5996 (VPMOVSXBWrm addr:$src)>;
5997 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5998 (VPMOVSXBWrm addr:$src)>;
5999 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
6000 (VPMOVSXBWrm addr:$src)>;
6002 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
6003 (VPMOVSXWDrm addr:$src)>;
6004 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
6005 (VPMOVSXWDrm addr:$src)>;
6006 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
6007 (VPMOVSXWDrm addr:$src)>;
6009 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
6010 (VPMOVSXDQrm addr:$src)>;
6011 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
6012 (VPMOVSXDQrm addr:$src)>;
6013 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
6014 (VPMOVSXDQrm addr:$src)>;
6016 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
6017 (VPMOVZXBWrm addr:$src)>;
6018 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
6019 (VPMOVZXBWrm addr:$src)>;
6020 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
6021 (VPMOVZXBWrm addr:$src)>;
6023 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
6024 (VPMOVZXWDrm addr:$src)>;
6025 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
6026 (VPMOVZXWDrm addr:$src)>;
6027 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
6028 (VPMOVZXWDrm addr:$src)>;
6030 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
6031 (VPMOVZXDQrm addr:$src)>;
6032 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
6033 (VPMOVZXDQrm addr:$src)>;
6034 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
6035 (VPMOVZXDQrm addr:$src)>;
6038 let Predicates = [UseSSE41] in {
6039 // Common patterns involving scalar load.
6040 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
6041 (PMOVSXBWrm addr:$src)>;
6042 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
6043 (PMOVSXBWrm addr:$src)>;
6044 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
6045 (PMOVSXBWrm addr:$src)>;
6047 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
6048 (PMOVSXWDrm addr:$src)>;
6049 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
6050 (PMOVSXWDrm addr:$src)>;
6051 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
6052 (PMOVSXWDrm addr:$src)>;
6054 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
6055 (PMOVSXDQrm addr:$src)>;
6056 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
6057 (PMOVSXDQrm addr:$src)>;
6058 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
6059 (PMOVSXDQrm addr:$src)>;
6061 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
6062 (PMOVZXBWrm addr:$src)>;
6063 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
6064 (PMOVZXBWrm addr:$src)>;
6065 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
6066 (PMOVZXBWrm addr:$src)>;
6068 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
6069 (PMOVZXWDrm addr:$src)>;
6070 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
6071 (PMOVZXWDrm addr:$src)>;
6072 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
6073 (PMOVZXWDrm addr:$src)>;
6075 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
6076 (PMOVZXDQrm addr:$src)>;
6077 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
6078 (PMOVZXDQrm addr:$src)>;
6079 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
6080 (PMOVZXDQrm addr:$src)>;
6083 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6084 OpndItins itins = DEFAULT_ITINS> {
6085 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6086 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6087 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>,
6088 Sched<[itins.Sched]>;
6090 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
6091 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6093 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
6094 itins.rm>, Sched<[itins.Sched.Folded]>;
6097 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
6098 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6099 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6100 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6101 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6103 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
6104 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6106 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
6107 Sched<[Sched.Folded]>;
6110 let Predicates = [HasAVX] in {
6111 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd,
6112 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6113 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq,
6114 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6115 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd,
6116 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6117 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq,
6118 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6121 let Predicates = [HasAVX2] in {
6122 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
6123 int_x86_avx2_pmovsxbd, WriteShuffle>,
6125 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
6126 int_x86_avx2_pmovsxwq, WriteShuffle>,
6128 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
6129 int_x86_avx2_pmovzxbd, WriteShuffle>,
6131 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
6132 int_x86_avx2_pmovzxwq, WriteShuffle>,
6136 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
6137 SSE_INTALU_ITINS_SHUFF_P>;
6138 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
6139 SSE_INTALU_ITINS_SHUFF_P>;
6140 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
6141 SSE_INTALU_ITINS_SHUFF_P>;
6142 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
6143 SSE_INTALU_ITINS_SHUFF_P>;
6145 let Predicates = [HasAVX] in {
6146 // Common patterns involving scalar load
6147 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
6148 (VPMOVSXBDrm addr:$src)>;
6149 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
6150 (VPMOVSXWQrm addr:$src)>;
6152 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
6153 (VPMOVZXBDrm addr:$src)>;
6154 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
6155 (VPMOVZXWQrm addr:$src)>;
6158 let Predicates = [UseSSE41] in {
6159 // Common patterns involving scalar load
6160 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
6161 (PMOVSXBDrm addr:$src)>;
6162 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
6163 (PMOVSXWQrm addr:$src)>;
6165 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
6166 (PMOVZXBDrm addr:$src)>;
6167 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
6168 (PMOVZXWQrm addr:$src)>;
6171 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6172 X86FoldableSchedWrite Sched> {
6173 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6174 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6175 [(set VR128:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6177 // Expecting a i16 load any extended to i32 value.
6178 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
6179 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6180 [(set VR128:$dst, (IntId (bitconvert
6181 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
6182 Sched<[Sched.Folded]>;
6185 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
6186 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6187 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6188 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6189 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6191 // Expecting a i16 load any extended to i32 value.
6192 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
6193 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6194 [(set VR256:$dst, (IntId (bitconvert
6195 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
6196 Sched<[Sched.Folded]>;
6199 let Predicates = [HasAVX] in {
6200 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq,
6202 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq,
6205 let Predicates = [HasAVX2] in {
6206 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq", int_x86_avx2_pmovsxbq,
6207 WriteShuffle>, VEX, VEX_L;
6208 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq", int_x86_avx2_pmovzxbq,
6209 WriteShuffle>, VEX, VEX_L;
6211 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
6213 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
6216 let Predicates = [HasAVX2] in {
6217 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
6218 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
6219 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
6221 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
6222 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
6224 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
6226 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
6227 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6228 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
6229 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6230 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
6231 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6233 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
6234 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6235 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
6236 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6238 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
6239 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6241 def : Pat<(v8i32 (X86vsext (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
6242 (VPMOVSXWDYrm addr:$src)>;
6243 def : Pat<(v4i64 (X86vsext (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
6244 (VPMOVSXDQYrm addr:$src)>;
6246 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
6247 (scalar_to_vector (loadi64 addr:$src))))))),
6248 (VPMOVSXBDYrm addr:$src)>;
6249 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
6250 (scalar_to_vector (loadf64 addr:$src))))))),
6251 (VPMOVSXBDYrm addr:$src)>;
6253 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
6254 (scalar_to_vector (loadi64 addr:$src))))))),
6255 (VPMOVSXWQYrm addr:$src)>;
6256 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
6257 (scalar_to_vector (loadf64 addr:$src))))))),
6258 (VPMOVSXWQYrm addr:$src)>;
6260 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
6261 (scalar_to_vector (loadi32 addr:$src))))))),
6262 (VPMOVSXBQYrm addr:$src)>;
6265 let Predicates = [HasAVX] in {
6266 // Common patterns involving scalar load
6267 def : Pat<(int_x86_sse41_pmovsxbq
6268 (bitconvert (v4i32 (X86vzmovl
6269 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6270 (VPMOVSXBQrm addr:$src)>;
6272 def : Pat<(int_x86_sse41_pmovzxbq
6273 (bitconvert (v4i32 (X86vzmovl
6274 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6275 (VPMOVZXBQrm addr:$src)>;
6278 let Predicates = [UseSSE41] in {
6279 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
6280 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
6281 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
6283 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
6284 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
6286 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
6288 // Common patterns involving scalar load
6289 def : Pat<(int_x86_sse41_pmovsxbq
6290 (bitconvert (v4i32 (X86vzmovl
6291 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6292 (PMOVSXBQrm addr:$src)>;
6294 def : Pat<(int_x86_sse41_pmovzxbq
6295 (bitconvert (v4i32 (X86vzmovl
6296 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6297 (PMOVZXBQrm addr:$src)>;
6299 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6300 (scalar_to_vector (loadi64 addr:$src))))))),
6301 (PMOVSXWDrm addr:$src)>;
6302 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6303 (scalar_to_vector (loadf64 addr:$src))))))),
6304 (PMOVSXWDrm addr:$src)>;
6305 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6306 (scalar_to_vector (loadi32 addr:$src))))))),
6307 (PMOVSXBDrm addr:$src)>;
6308 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6309 (scalar_to_vector (loadi32 addr:$src))))))),
6310 (PMOVSXWQrm addr:$src)>;
6311 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6312 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6313 (PMOVSXBQrm addr:$src)>;
6314 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6315 (scalar_to_vector (loadi64 addr:$src))))))),
6316 (PMOVSXDQrm addr:$src)>;
6317 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6318 (scalar_to_vector (loadf64 addr:$src))))))),
6319 (PMOVSXDQrm addr:$src)>;
6320 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6321 (scalar_to_vector (loadi64 addr:$src))))))),
6322 (PMOVSXBWrm addr:$src)>;
6323 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6324 (scalar_to_vector (loadf64 addr:$src))))))),
6325 (PMOVSXBWrm addr:$src)>;
6328 let Predicates = [HasAVX2] in {
6329 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
6330 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
6331 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
6333 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
6334 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
6336 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
6338 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
6339 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6340 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
6341 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6342 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
6343 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6345 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
6346 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6347 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
6348 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6350 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
6351 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6354 let Predicates = [HasAVX] in {
6355 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
6356 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
6357 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
6359 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
6360 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
6362 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
6364 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6365 (VPMOVZXBWrm addr:$src)>;
6366 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6367 (VPMOVZXBWrm addr:$src)>;
6368 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6369 (VPMOVZXBDrm addr:$src)>;
6370 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6371 (VPMOVZXBQrm addr:$src)>;
6373 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6374 (VPMOVZXWDrm addr:$src)>;
6375 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6376 (VPMOVZXWDrm addr:$src)>;
6377 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6378 (VPMOVZXWQrm addr:$src)>;
6380 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6381 (VPMOVZXDQrm addr:$src)>;
6382 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6383 (VPMOVZXDQrm addr:$src)>;
6384 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6385 (VPMOVZXDQrm addr:$src)>;
6387 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
6388 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
6389 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
6391 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
6392 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
6394 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
6396 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6397 (scalar_to_vector (loadi64 addr:$src))))))),
6398 (VPMOVSXWDrm addr:$src)>;
6399 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6400 (scalar_to_vector (loadi64 addr:$src))))))),
6401 (VPMOVSXDQrm addr:$src)>;
6402 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6403 (scalar_to_vector (loadf64 addr:$src))))))),
6404 (VPMOVSXWDrm addr:$src)>;
6405 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6406 (scalar_to_vector (loadf64 addr:$src))))))),
6407 (VPMOVSXDQrm addr:$src)>;
6408 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6409 (scalar_to_vector (loadi64 addr:$src))))))),
6410 (VPMOVSXBWrm addr:$src)>;
6411 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6412 (scalar_to_vector (loadf64 addr:$src))))))),
6413 (VPMOVSXBWrm addr:$src)>;
6415 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6416 (scalar_to_vector (loadi32 addr:$src))))))),
6417 (VPMOVSXBDrm addr:$src)>;
6418 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6419 (scalar_to_vector (loadi32 addr:$src))))))),
6420 (VPMOVSXWQrm addr:$src)>;
6421 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6422 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6423 (VPMOVSXBQrm addr:$src)>;
6426 let Predicates = [UseSSE41] in {
6427 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6428 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6429 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6431 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6432 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6434 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6436 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6437 (PMOVZXBWrm addr:$src)>;
6438 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6439 (PMOVZXBWrm addr:$src)>;
6440 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6441 (PMOVZXBDrm addr:$src)>;
6442 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6443 (PMOVZXBQrm addr:$src)>;
6445 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6446 (PMOVZXWDrm addr:$src)>;
6447 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6448 (PMOVZXWDrm addr:$src)>;
6449 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6450 (PMOVZXWQrm addr:$src)>;
6452 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6453 (PMOVZXDQrm addr:$src)>;
6454 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6455 (PMOVZXDQrm addr:$src)>;
6456 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6457 (PMOVZXDQrm addr:$src)>;
6460 //===----------------------------------------------------------------------===//
6461 // SSE4.1 - Extract Instructions
6462 //===----------------------------------------------------------------------===//
6464 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6465 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6466 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6467 (ins VR128:$src1, i32i8imm:$src2),
6468 !strconcat(OpcodeStr,
6469 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6470 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6472 Sched<[WriteShuffle]>;
6473 let neverHasSideEffects = 1, mayStore = 1,
6474 SchedRW = [WriteShuffleLd, WriteRMW] in
6475 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6476 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6477 !strconcat(OpcodeStr,
6478 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6479 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6480 imm:$src2)))), addr:$dst)]>;
6483 let Predicates = [HasAVX] in
6484 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6486 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6489 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6490 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6491 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6492 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6493 (ins VR128:$src1, i32i8imm:$src2),
6494 !strconcat(OpcodeStr,
6495 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6496 []>, Sched<[WriteShuffle]>;
6498 let neverHasSideEffects = 1, mayStore = 1,
6499 SchedRW = [WriteShuffleLd, WriteRMW] in
6500 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6501 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6502 !strconcat(OpcodeStr,
6503 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6504 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6505 imm:$src2)))), addr:$dst)]>;
6508 let Predicates = [HasAVX] in
6509 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6511 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6514 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6515 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6516 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6517 (ins VR128:$src1, i32i8imm:$src2),
6518 !strconcat(OpcodeStr,
6519 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6521 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6522 Sched<[WriteShuffle]>;
6523 let SchedRW = [WriteShuffleLd, WriteRMW] in
6524 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6525 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6526 !strconcat(OpcodeStr,
6527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6528 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6532 let Predicates = [HasAVX] in
6533 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6535 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6537 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6538 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6539 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6540 (ins VR128:$src1, i32i8imm:$src2),
6541 !strconcat(OpcodeStr,
6542 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6544 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6545 Sched<[WriteShuffle]>, REX_W;
6546 let SchedRW = [WriteShuffleLd, WriteRMW] in
6547 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6548 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6549 !strconcat(OpcodeStr,
6550 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6551 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6552 addr:$dst)]>, REX_W;
6555 let Predicates = [HasAVX] in
6556 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6558 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6560 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6562 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6563 OpndItins itins = DEFAULT_ITINS> {
6564 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6565 (ins VR128:$src1, i32i8imm:$src2),
6566 !strconcat(OpcodeStr,
6567 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6568 [(set GR32orGR64:$dst,
6569 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6570 itins.rr>, Sched<[WriteFBlend]>;
6571 let SchedRW = [WriteFBlendLd, WriteRMW] in
6572 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6573 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6574 !strconcat(OpcodeStr,
6575 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6576 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6577 addr:$dst)], itins.rm>;
6580 let ExeDomain = SSEPackedSingle in {
6581 let Predicates = [UseAVX] in
6582 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6583 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6586 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6587 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6590 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6592 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6595 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6596 Requires<[UseSSE41]>;
6598 //===----------------------------------------------------------------------===//
6599 // SSE4.1 - Insert Instructions
6600 //===----------------------------------------------------------------------===//
6602 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6603 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6604 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6606 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6608 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6610 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6611 Sched<[WriteShuffle]>;
6612 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6613 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6615 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6617 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6619 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6620 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6623 let Predicates = [HasAVX] in
6624 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6625 let Constraints = "$src1 = $dst" in
6626 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6628 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6629 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6630 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6632 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6634 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6636 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6637 Sched<[WriteShuffle]>;
6638 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6639 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6641 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6643 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6645 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6646 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6649 let Predicates = [HasAVX] in
6650 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6651 let Constraints = "$src1 = $dst" in
6652 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6654 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6655 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6656 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6658 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6660 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6662 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6663 Sched<[WriteShuffle]>;
6664 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6665 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6667 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6669 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6671 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6672 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6675 let Predicates = [HasAVX] in
6676 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6677 let Constraints = "$src1 = $dst" in
6678 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6680 // insertps has a few different modes, there's the first two here below which
6681 // are optimized inserts that won't zero arbitrary elements in the destination
6682 // vector. The next one matches the intrinsic and could zero arbitrary elements
6683 // in the target vector.
6684 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6685 OpndItins itins = DEFAULT_ITINS> {
6686 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6687 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6689 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6691 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6693 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6694 Sched<[WriteFShuffle]>;
6695 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6696 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6698 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6700 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6702 (X86insertps VR128:$src1,
6703 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6704 imm:$src3))], itins.rm>,
6705 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6708 let ExeDomain = SSEPackedSingle in {
6709 let Predicates = [UseAVX] in
6710 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6711 let Constraints = "$src1 = $dst" in
6712 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6715 let Predicates = [UseSSE41] in {
6716 // If we're inserting an element from a load or a null pshuf of a load,
6717 // fold the load into the insertps instruction.
6718 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6719 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6721 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6722 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6723 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6724 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6727 let Predicates = [UseAVX] in {
6728 // If we're inserting an element from a vbroadcast of a load, fold the
6729 // load into the X86insertps instruction.
6730 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6731 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6732 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6733 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6734 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6735 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6738 //===----------------------------------------------------------------------===//
6739 // SSE4.1 - Round Instructions
6740 //===----------------------------------------------------------------------===//
6742 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6743 X86MemOperand x86memop, RegisterClass RC,
6744 PatFrag mem_frag32, PatFrag mem_frag64,
6745 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6746 let ExeDomain = SSEPackedSingle in {
6747 // Intrinsic operation, reg.
6748 // Vector intrinsic operation, reg
6749 def PSr : SS4AIi8<opcps, MRMSrcReg,
6750 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6751 !strconcat(OpcodeStr,
6752 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6753 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6754 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6756 // Vector intrinsic operation, mem
6757 def PSm : SS4AIi8<opcps, MRMSrcMem,
6758 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6759 !strconcat(OpcodeStr,
6760 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6762 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6763 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6764 } // ExeDomain = SSEPackedSingle
6766 let ExeDomain = SSEPackedDouble in {
6767 // Vector intrinsic operation, reg
6768 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6769 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6770 !strconcat(OpcodeStr,
6771 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6772 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6773 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6775 // Vector intrinsic operation, mem
6776 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6777 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6778 !strconcat(OpcodeStr,
6779 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6781 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6782 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6783 } // ExeDomain = SSEPackedDouble
6786 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6789 Intrinsic F64Int, bit Is2Addr = 1> {
6790 let ExeDomain = GenericDomain in {
6792 let hasSideEffects = 0 in
6793 def SSr : SS4AIi8<opcss, MRMSrcReg,
6794 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6796 !strconcat(OpcodeStr,
6797 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6798 !strconcat(OpcodeStr,
6799 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6800 []>, Sched<[WriteFAdd]>;
6802 // Intrinsic operation, reg.
6803 let isCodeGenOnly = 1 in
6804 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6805 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6807 !strconcat(OpcodeStr,
6808 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6809 !strconcat(OpcodeStr,
6810 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6811 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6814 // Intrinsic operation, mem.
6815 def SSm : SS4AIi8<opcss, MRMSrcMem,
6816 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6818 !strconcat(OpcodeStr,
6819 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6820 !strconcat(OpcodeStr,
6821 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6823 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6824 Sched<[WriteFAddLd, ReadAfterLd]>;
6827 let hasSideEffects = 0 in
6828 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6829 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6831 !strconcat(OpcodeStr,
6832 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6833 !strconcat(OpcodeStr,
6834 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6835 []>, Sched<[WriteFAdd]>;
6837 // Intrinsic operation, reg.
6838 let isCodeGenOnly = 1 in
6839 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6840 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6842 !strconcat(OpcodeStr,
6843 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6844 !strconcat(OpcodeStr,
6845 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6846 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6849 // Intrinsic operation, mem.
6850 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6851 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6853 !strconcat(OpcodeStr,
6854 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6855 !strconcat(OpcodeStr,
6856 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6858 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6859 Sched<[WriteFAddLd, ReadAfterLd]>;
6860 } // ExeDomain = GenericDomain
6863 // FP round - roundss, roundps, roundsd, roundpd
6864 let Predicates = [HasAVX] in {
6866 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6867 loadv4f32, loadv2f64,
6868 int_x86_sse41_round_ps,
6869 int_x86_sse41_round_pd>, VEX;
6870 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6871 loadv8f32, loadv4f64,
6872 int_x86_avx_round_ps_256,
6873 int_x86_avx_round_pd_256>, VEX, VEX_L;
6874 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6875 int_x86_sse41_round_ss,
6876 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6878 def : Pat<(ffloor FR32:$src),
6879 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6880 def : Pat<(f64 (ffloor FR64:$src)),
6881 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6882 def : Pat<(f32 (fnearbyint FR32:$src)),
6883 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6884 def : Pat<(f64 (fnearbyint FR64:$src)),
6885 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6886 def : Pat<(f32 (fceil FR32:$src)),
6887 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6888 def : Pat<(f64 (fceil FR64:$src)),
6889 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6890 def : Pat<(f32 (frint FR32:$src)),
6891 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6892 def : Pat<(f64 (frint FR64:$src)),
6893 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6894 def : Pat<(f32 (ftrunc FR32:$src)),
6895 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6896 def : Pat<(f64 (ftrunc FR64:$src)),
6897 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6899 def : Pat<(v4f32 (ffloor VR128:$src)),
6900 (VROUNDPSr VR128:$src, (i32 0x1))>;
6901 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6902 (VROUNDPSr VR128:$src, (i32 0xC))>;
6903 def : Pat<(v4f32 (fceil VR128:$src)),
6904 (VROUNDPSr VR128:$src, (i32 0x2))>;
6905 def : Pat<(v4f32 (frint VR128:$src)),
6906 (VROUNDPSr VR128:$src, (i32 0x4))>;
6907 def : Pat<(v4f32 (ftrunc VR128:$src)),
6908 (VROUNDPSr VR128:$src, (i32 0x3))>;
6910 def : Pat<(v2f64 (ffloor VR128:$src)),
6911 (VROUNDPDr VR128:$src, (i32 0x1))>;
6912 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6913 (VROUNDPDr VR128:$src, (i32 0xC))>;
6914 def : Pat<(v2f64 (fceil VR128:$src)),
6915 (VROUNDPDr VR128:$src, (i32 0x2))>;
6916 def : Pat<(v2f64 (frint VR128:$src)),
6917 (VROUNDPDr VR128:$src, (i32 0x4))>;
6918 def : Pat<(v2f64 (ftrunc VR128:$src)),
6919 (VROUNDPDr VR128:$src, (i32 0x3))>;
6921 def : Pat<(v8f32 (ffloor VR256:$src)),
6922 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6923 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6924 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6925 def : Pat<(v8f32 (fceil VR256:$src)),
6926 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6927 def : Pat<(v8f32 (frint VR256:$src)),
6928 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6929 def : Pat<(v8f32 (ftrunc VR256:$src)),
6930 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6932 def : Pat<(v4f64 (ffloor VR256:$src)),
6933 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6934 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6935 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6936 def : Pat<(v4f64 (fceil VR256:$src)),
6937 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6938 def : Pat<(v4f64 (frint VR256:$src)),
6939 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6940 def : Pat<(v4f64 (ftrunc VR256:$src)),
6941 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6944 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6945 memopv4f32, memopv2f64,
6946 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6947 let Constraints = "$src1 = $dst" in
6948 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6949 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6951 let Predicates = [UseSSE41] in {
6952 def : Pat<(ffloor FR32:$src),
6953 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6954 def : Pat<(f64 (ffloor FR64:$src)),
6955 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6956 def : Pat<(f32 (fnearbyint FR32:$src)),
6957 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6958 def : Pat<(f64 (fnearbyint FR64:$src)),
6959 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6960 def : Pat<(f32 (fceil FR32:$src)),
6961 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6962 def : Pat<(f64 (fceil FR64:$src)),
6963 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6964 def : Pat<(f32 (frint FR32:$src)),
6965 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6966 def : Pat<(f64 (frint FR64:$src)),
6967 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6968 def : Pat<(f32 (ftrunc FR32:$src)),
6969 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6970 def : Pat<(f64 (ftrunc FR64:$src)),
6971 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6973 def : Pat<(v4f32 (ffloor VR128:$src)),
6974 (ROUNDPSr VR128:$src, (i32 0x1))>;
6975 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6976 (ROUNDPSr VR128:$src, (i32 0xC))>;
6977 def : Pat<(v4f32 (fceil VR128:$src)),
6978 (ROUNDPSr VR128:$src, (i32 0x2))>;
6979 def : Pat<(v4f32 (frint VR128:$src)),
6980 (ROUNDPSr VR128:$src, (i32 0x4))>;
6981 def : Pat<(v4f32 (ftrunc VR128:$src)),
6982 (ROUNDPSr VR128:$src, (i32 0x3))>;
6984 def : Pat<(v2f64 (ffloor VR128:$src)),
6985 (ROUNDPDr VR128:$src, (i32 0x1))>;
6986 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6987 (ROUNDPDr VR128:$src, (i32 0xC))>;
6988 def : Pat<(v2f64 (fceil VR128:$src)),
6989 (ROUNDPDr VR128:$src, (i32 0x2))>;
6990 def : Pat<(v2f64 (frint VR128:$src)),
6991 (ROUNDPDr VR128:$src, (i32 0x4))>;
6992 def : Pat<(v2f64 (ftrunc VR128:$src)),
6993 (ROUNDPDr VR128:$src, (i32 0x3))>;
6996 //===----------------------------------------------------------------------===//
6997 // SSE4.1 - Packed Bit Test
6998 //===----------------------------------------------------------------------===//
7000 // ptest instruction we'll lower to this in X86ISelLowering primarily from
7001 // the intel intrinsic that corresponds to this.
7002 let Defs = [EFLAGS], Predicates = [HasAVX] in {
7003 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
7004 "vptest\t{$src2, $src1|$src1, $src2}",
7005 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
7006 Sched<[WriteVecLogic]>, VEX;
7007 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
7008 "vptest\t{$src2, $src1|$src1, $src2}",
7009 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
7010 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
7012 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
7013 "vptest\t{$src2, $src1|$src1, $src2}",
7014 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
7015 Sched<[WriteVecLogic]>, VEX, VEX_L;
7016 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
7017 "vptest\t{$src2, $src1|$src1, $src2}",
7018 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
7019 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
7022 let Defs = [EFLAGS] in {
7023 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
7024 "ptest\t{$src2, $src1|$src1, $src2}",
7025 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
7026 Sched<[WriteVecLogic]>;
7027 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
7028 "ptest\t{$src2, $src1|$src1, $src2}",
7029 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
7030 Sched<[WriteVecLogicLd, ReadAfterLd]>;
7033 // The bit test instructions below are AVX only
7034 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
7035 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
7036 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
7037 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
7038 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
7039 Sched<[WriteVecLogic]>, VEX;
7040 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
7041 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
7042 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
7043 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
7046 let Defs = [EFLAGS], Predicates = [HasAVX] in {
7047 let ExeDomain = SSEPackedSingle in {
7048 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
7049 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
7052 let ExeDomain = SSEPackedDouble in {
7053 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
7054 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
7059 //===----------------------------------------------------------------------===//
7060 // SSE4.1 - Misc Instructions
7061 //===----------------------------------------------------------------------===//
7063 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
7064 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
7065 "popcnt{w}\t{$src, $dst|$dst, $src}",
7066 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
7067 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
7069 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
7070 "popcnt{w}\t{$src, $dst|$dst, $src}",
7071 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
7072 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7073 Sched<[WriteFAddLd]>, OpSize16, XS;
7075 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
7076 "popcnt{l}\t{$src, $dst|$dst, $src}",
7077 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
7078 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
7081 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
7082 "popcnt{l}\t{$src, $dst|$dst, $src}",
7083 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
7084 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7085 Sched<[WriteFAddLd]>, OpSize32, XS;
7087 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
7088 "popcnt{q}\t{$src, $dst|$dst, $src}",
7089 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
7090 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
7091 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
7092 "popcnt{q}\t{$src, $dst|$dst, $src}",
7093 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
7094 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7095 Sched<[WriteFAddLd]>, XS;
7100 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
7101 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
7103 X86FoldableSchedWrite Sched> {
7104 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7106 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7107 [(set VR128:$dst, (IntId128 VR128:$src))]>,
7109 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7111 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7113 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>,
7114 Sched<[Sched.Folded]>;
7117 // PHMIN has the same profile as PSAD, thus we use the same scheduling
7118 // model, although the naming is misleading.
7119 let Predicates = [HasAVX] in
7120 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
7121 int_x86_sse41_phminposuw,
7123 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
7124 int_x86_sse41_phminposuw,
7127 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
7128 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
7129 Intrinsic IntId128, bit Is2Addr = 1,
7130 OpndItins itins = DEFAULT_ITINS> {
7131 let isCommutable = 1 in
7132 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7133 (ins VR128:$src1, VR128:$src2),
7135 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7136 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7137 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
7138 itins.rr>, Sched<[itins.Sched]>;
7139 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7140 (ins VR128:$src1, i128mem:$src2),
7142 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7143 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7145 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
7146 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7149 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
7150 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
7152 X86FoldableSchedWrite Sched> {
7153 let isCommutable = 1 in
7154 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
7155 (ins VR256:$src1, VR256:$src2),
7156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7157 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
7159 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
7160 (ins VR256:$src1, i256mem:$src2),
7161 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7163 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
7164 Sched<[Sched.Folded, ReadAfterLd]>;
7168 /// SS48I_binop_rm - Simple SSE41 binary operator.
7169 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7170 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7171 X86MemOperand x86memop, bit Is2Addr = 1,
7172 OpndItins itins = SSE_INTALU_ITINS_P> {
7173 let isCommutable = 1 in
7174 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7175 (ins RC:$src1, RC:$src2),
7177 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7178 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7179 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7180 Sched<[itins.Sched]>;
7181 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7182 (ins RC:$src1, x86memop:$src2),
7184 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7185 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7187 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
7188 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7191 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
7193 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
7194 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
7195 PatFrag memop_frag, X86MemOperand x86memop,
7197 bit IsCommutable = 0, bit Is2Addr = 1> {
7198 let isCommutable = IsCommutable in
7199 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7200 (ins RC:$src1, RC:$src2),
7202 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7203 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7204 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
7205 Sched<[itins.Sched]>;
7206 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7207 (ins RC:$src1, x86memop:$src2),
7209 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7210 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7211 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
7212 (bitconvert (memop_frag addr:$src2)))))]>,
7213 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7216 let Predicates = [HasAVX] in {
7217 let isCommutable = 0 in
7218 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
7219 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7221 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
7222 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7224 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
7225 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7227 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
7228 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7230 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
7231 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7233 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
7234 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7236 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
7237 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7239 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
7240 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7242 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
7243 VR128, loadv2i64, i128mem,
7244 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
7247 let Predicates = [HasAVX2] in {
7248 let isCommutable = 0 in
7249 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
7250 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7252 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
7253 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7255 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
7256 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7258 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
7259 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7261 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
7262 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7264 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
7265 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7267 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
7268 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7270 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
7271 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7273 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
7274 VR256, loadv4i64, i256mem,
7275 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
7278 let Constraints = "$src1 = $dst" in {
7279 let isCommutable = 0 in
7280 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
7281 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7282 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
7283 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7284 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
7285 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7286 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
7287 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7288 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
7289 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7290 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
7291 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7292 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
7293 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7294 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7295 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7296 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
7297 VR128, memopv2i64, i128mem,
7298 SSE_INTMUL_ITINS_P, 1>;
7301 let Predicates = [HasAVX] in {
7302 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7303 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7305 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7306 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7309 let Predicates = [HasAVX2] in {
7310 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7311 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7313 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7314 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7318 let Constraints = "$src1 = $dst" in {
7319 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7320 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7321 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7322 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7325 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7326 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7327 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7328 X86MemOperand x86memop, bit Is2Addr = 1,
7329 OpndItins itins = DEFAULT_ITINS> {
7330 let isCommutable = 1 in
7331 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7332 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7334 !strconcat(OpcodeStr,
7335 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7336 !strconcat(OpcodeStr,
7337 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7338 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7339 Sched<[itins.Sched]>;
7340 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7341 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7343 !strconcat(OpcodeStr,
7344 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7345 !strconcat(OpcodeStr,
7346 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7349 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7350 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7353 let Predicates = [HasAVX] in {
7354 let isCommutable = 0 in {
7355 let ExeDomain = SSEPackedSingle in {
7356 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7357 VR128, loadv4f32, f128mem, 0,
7358 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7359 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7360 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7361 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7364 let ExeDomain = SSEPackedDouble in {
7365 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7366 VR128, loadv2f64, f128mem, 0,
7367 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7368 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7369 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7370 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7373 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7374 VR128, loadv2i64, i128mem, 0,
7375 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7376 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7377 VR128, loadv2i64, i128mem, 0,
7378 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7380 let ExeDomain = SSEPackedSingle in
7381 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7382 VR128, loadv4f32, f128mem, 0,
7383 SSE_DPPS_ITINS>, VEX_4V;
7384 let ExeDomain = SSEPackedDouble in
7385 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7386 VR128, loadv2f64, f128mem, 0,
7387 SSE_DPPS_ITINS>, VEX_4V;
7388 let ExeDomain = SSEPackedSingle in
7389 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7390 VR256, loadv8f32, i256mem, 0,
7391 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7394 let Predicates = [HasAVX2] in {
7395 let isCommutable = 0 in {
7396 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7397 VR256, loadv4i64, i256mem, 0,
7398 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7399 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7400 VR256, loadv4i64, i256mem, 0,
7401 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7405 let Constraints = "$src1 = $dst" in {
7406 let isCommutable = 0 in {
7407 let ExeDomain = SSEPackedSingle in
7408 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7409 VR128, memopv4f32, f128mem,
7410 1, SSE_INTALU_ITINS_FBLEND_P>;
7411 let ExeDomain = SSEPackedDouble in
7412 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7413 VR128, memopv2f64, f128mem,
7414 1, SSE_INTALU_ITINS_FBLEND_P>;
7415 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7416 VR128, memopv2i64, i128mem,
7417 1, SSE_INTALU_ITINS_FBLEND_P>;
7418 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7419 VR128, memopv2i64, i128mem,
7420 1, SSE_MPSADBW_ITINS>;
7422 let ExeDomain = SSEPackedSingle in
7423 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7424 VR128, memopv4f32, f128mem, 1,
7426 let ExeDomain = SSEPackedDouble in
7427 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7428 VR128, memopv2f64, f128mem, 1,
7432 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7433 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7434 RegisterClass RC, X86MemOperand x86memop,
7435 PatFrag mem_frag, Intrinsic IntId,
7436 X86FoldableSchedWrite Sched> {
7437 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7438 (ins RC:$src1, RC:$src2, RC:$src3),
7439 !strconcat(OpcodeStr,
7440 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7441 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7442 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7445 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7446 (ins RC:$src1, x86memop:$src2, RC:$src3),
7447 !strconcat(OpcodeStr,
7448 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7450 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7452 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7453 Sched<[Sched.Folded, ReadAfterLd]>;
7456 let Predicates = [HasAVX] in {
7457 let ExeDomain = SSEPackedDouble in {
7458 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7459 loadv2f64, int_x86_sse41_blendvpd,
7461 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7462 loadv4f64, int_x86_avx_blendv_pd_256,
7463 WriteFVarBlend>, VEX_L;
7464 } // ExeDomain = SSEPackedDouble
7465 let ExeDomain = SSEPackedSingle in {
7466 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7467 loadv4f32, int_x86_sse41_blendvps,
7469 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7470 loadv8f32, int_x86_avx_blendv_ps_256,
7471 WriteFVarBlend>, VEX_L;
7472 } // ExeDomain = SSEPackedSingle
7473 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7474 loadv2i64, int_x86_sse41_pblendvb,
7478 let Predicates = [HasAVX2] in {
7479 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7480 loadv4i64, int_x86_avx2_pblendvb,
7481 WriteVarBlend>, VEX_L;
7484 let Predicates = [HasAVX] in {
7485 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7486 (v16i8 VR128:$src2))),
7487 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7488 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7489 (v4i32 VR128:$src2))),
7490 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7491 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7492 (v4f32 VR128:$src2))),
7493 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7494 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7495 (v2i64 VR128:$src2))),
7496 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7497 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7498 (v2f64 VR128:$src2))),
7499 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7500 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7501 (v8i32 VR256:$src2))),
7502 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7503 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7504 (v8f32 VR256:$src2))),
7505 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7506 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7507 (v4i64 VR256:$src2))),
7508 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7509 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7510 (v4f64 VR256:$src2))),
7511 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7513 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7515 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7516 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7518 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7520 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7522 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7523 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7525 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7526 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7528 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7531 let Predicates = [HasAVX2] in {
7532 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7533 (v32i8 VR256:$src2))),
7534 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7535 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7537 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7540 /// SS41I_ternary_int - SSE 4.1 ternary operator
7541 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7542 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7543 X86MemOperand x86memop, Intrinsic IntId,
7544 OpndItins itins = DEFAULT_ITINS> {
7545 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7546 (ins VR128:$src1, VR128:$src2),
7547 !strconcat(OpcodeStr,
7548 "\t{$src2, $dst|$dst, $src2}"),
7549 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7552 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7553 (ins VR128:$src1, x86memop:$src2),
7554 !strconcat(OpcodeStr,
7555 "\t{$src2, $dst|$dst, $src2}"),
7558 (bitconvert (mem_frag addr:$src2)), XMM0))],
7563 let ExeDomain = SSEPackedDouble in
7564 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7565 int_x86_sse41_blendvpd>;
7566 let ExeDomain = SSEPackedSingle in
7567 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7568 int_x86_sse41_blendvps>;
7569 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7570 int_x86_sse41_pblendvb>;
7572 // Aliases with the implicit xmm0 argument
7573 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7574 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7575 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7576 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7577 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7578 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7579 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7580 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7581 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7582 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7583 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7584 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7586 let Predicates = [UseSSE41] in {
7587 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7588 (v16i8 VR128:$src2))),
7589 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7590 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7591 (v4i32 VR128:$src2))),
7592 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7593 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7594 (v4f32 VR128:$src2))),
7595 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7596 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7597 (v2i64 VR128:$src2))),
7598 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7599 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7600 (v2f64 VR128:$src2))),
7601 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7603 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7605 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7606 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7608 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7609 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7611 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7615 let SchedRW = [WriteLoad] in {
7616 let Predicates = [HasAVX] in
7617 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7618 "vmovntdqa\t{$src, $dst|$dst, $src}",
7619 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7621 let Predicates = [HasAVX2] in
7622 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7623 "vmovntdqa\t{$src, $dst|$dst, $src}",
7624 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7626 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7627 "movntdqa\t{$src, $dst|$dst, $src}",
7628 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7631 //===----------------------------------------------------------------------===//
7632 // SSE4.2 - Compare Instructions
7633 //===----------------------------------------------------------------------===//
7635 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7636 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7637 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7638 X86MemOperand x86memop, bit Is2Addr = 1> {
7639 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7640 (ins RC:$src1, RC:$src2),
7642 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7643 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7644 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7645 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7646 (ins RC:$src1, x86memop:$src2),
7648 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7649 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7651 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7654 let Predicates = [HasAVX] in
7655 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7656 loadv2i64, i128mem, 0>, VEX_4V;
7658 let Predicates = [HasAVX2] in
7659 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7660 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7662 let Constraints = "$src1 = $dst" in
7663 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7664 memopv2i64, i128mem>;
7666 //===----------------------------------------------------------------------===//
7667 // SSE4.2 - String/text Processing Instructions
7668 //===----------------------------------------------------------------------===//
7670 // Packed Compare Implicit Length Strings, Return Mask
7671 multiclass pseudo_pcmpistrm<string asm> {
7672 def REG : PseudoI<(outs VR128:$dst),
7673 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7674 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7676 def MEM : PseudoI<(outs VR128:$dst),
7677 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7678 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7679 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7682 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7683 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7684 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7687 multiclass pcmpistrm_SS42AI<string asm> {
7688 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7689 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7690 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7691 []>, Sched<[WritePCmpIStrM]>;
7693 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7694 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7695 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7696 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7699 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7700 let Predicates = [HasAVX] in
7701 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7702 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7705 // Packed Compare Explicit Length Strings, Return Mask
7706 multiclass pseudo_pcmpestrm<string asm> {
7707 def REG : PseudoI<(outs VR128:$dst),
7708 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7709 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7710 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7711 def MEM : PseudoI<(outs VR128:$dst),
7712 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7713 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7714 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7717 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7718 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7719 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7722 multiclass SS42AI_pcmpestrm<string asm> {
7723 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7724 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7725 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7726 []>, Sched<[WritePCmpEStrM]>;
7728 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7729 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7730 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7731 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7734 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7735 let Predicates = [HasAVX] in
7736 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7737 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7740 // Packed Compare Implicit Length Strings, Return Index
7741 multiclass pseudo_pcmpistri<string asm> {
7742 def REG : PseudoI<(outs GR32:$dst),
7743 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7744 [(set GR32:$dst, EFLAGS,
7745 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7746 def MEM : PseudoI<(outs GR32:$dst),
7747 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7748 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7749 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7752 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7753 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7754 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7757 multiclass SS42AI_pcmpistri<string asm> {
7758 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7759 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7760 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7761 []>, Sched<[WritePCmpIStrI]>;
7763 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7764 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7765 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7766 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7769 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7770 let Predicates = [HasAVX] in
7771 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7772 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7775 // Packed Compare Explicit Length Strings, Return Index
7776 multiclass pseudo_pcmpestri<string asm> {
7777 def REG : PseudoI<(outs GR32:$dst),
7778 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7779 [(set GR32:$dst, EFLAGS,
7780 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7781 def MEM : PseudoI<(outs GR32:$dst),
7782 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7783 [(set GR32:$dst, EFLAGS,
7784 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7788 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7789 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7790 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7793 multiclass SS42AI_pcmpestri<string asm> {
7794 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7795 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7796 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7797 []>, Sched<[WritePCmpEStrI]>;
7799 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7800 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7801 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7802 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7805 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7806 let Predicates = [HasAVX] in
7807 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7808 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7811 //===----------------------------------------------------------------------===//
7812 // SSE4.2 - CRC Instructions
7813 //===----------------------------------------------------------------------===//
7815 // No CRC instructions have AVX equivalents
7817 // crc intrinsic instruction
7818 // This set of instructions are only rm, the only difference is the size
7820 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7821 RegisterClass RCIn, SDPatternOperator Int> :
7822 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7823 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7824 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7827 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7828 X86MemOperand x86memop, SDPatternOperator Int> :
7829 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7830 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7831 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7832 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7834 let Constraints = "$src1 = $dst" in {
7835 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7836 int_x86_sse42_crc32_32_8>;
7837 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7838 int_x86_sse42_crc32_32_8>;
7839 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7840 int_x86_sse42_crc32_32_16>, OpSize16;
7841 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7842 int_x86_sse42_crc32_32_16>, OpSize16;
7843 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7844 int_x86_sse42_crc32_32_32>, OpSize32;
7845 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7846 int_x86_sse42_crc32_32_32>, OpSize32;
7847 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7848 int_x86_sse42_crc32_64_64>, REX_W;
7849 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7850 int_x86_sse42_crc32_64_64>, REX_W;
7851 let hasSideEffects = 0 in {
7853 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7855 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7860 //===----------------------------------------------------------------------===//
7861 // SHA-NI Instructions
7862 //===----------------------------------------------------------------------===//
7864 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7866 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7867 (ins VR128:$src1, VR128:$src2),
7868 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7870 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7871 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7873 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7874 (ins VR128:$src1, i128mem:$src2),
7875 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7877 (set VR128:$dst, (IntId VR128:$src1,
7878 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7879 (set VR128:$dst, (IntId VR128:$src1,
7880 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7883 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7884 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7885 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7886 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7888 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7889 (i8 imm:$src3)))]>, TA;
7890 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7891 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7892 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7894 (int_x86_sha1rnds4 VR128:$src1,
7895 (bc_v4i32 (memopv2i64 addr:$src2)),
7896 (i8 imm:$src3)))]>, TA;
7898 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7899 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7900 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7903 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7905 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7906 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7909 // Aliases with explicit %xmm0
7910 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7911 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7912 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7913 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7915 //===----------------------------------------------------------------------===//
7916 // AES-NI Instructions
7917 //===----------------------------------------------------------------------===//
7919 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7920 Intrinsic IntId128, bit Is2Addr = 1> {
7921 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7922 (ins VR128:$src1, VR128:$src2),
7924 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7925 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7926 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7927 Sched<[WriteAESDecEnc]>;
7928 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7929 (ins VR128:$src1, i128mem:$src2),
7931 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7932 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7934 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
7935 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7938 // Perform One Round of an AES Encryption/Decryption Flow
7939 let Predicates = [HasAVX, HasAES] in {
7940 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7941 int_x86_aesni_aesenc, 0>, VEX_4V;
7942 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7943 int_x86_aesni_aesenclast, 0>, VEX_4V;
7944 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7945 int_x86_aesni_aesdec, 0>, VEX_4V;
7946 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7947 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7950 let Constraints = "$src1 = $dst" in {
7951 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7952 int_x86_aesni_aesenc>;
7953 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7954 int_x86_aesni_aesenclast>;
7955 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7956 int_x86_aesni_aesdec>;
7957 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7958 int_x86_aesni_aesdeclast>;
7961 // Perform the AES InvMixColumn Transformation
7962 let Predicates = [HasAVX, HasAES] in {
7963 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7965 "vaesimc\t{$src1, $dst|$dst, $src1}",
7967 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7969 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7970 (ins i128mem:$src1),
7971 "vaesimc\t{$src1, $dst|$dst, $src1}",
7972 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7973 Sched<[WriteAESIMCLd]>, VEX;
7975 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7977 "aesimc\t{$src1, $dst|$dst, $src1}",
7979 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7980 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7981 (ins i128mem:$src1),
7982 "aesimc\t{$src1, $dst|$dst, $src1}",
7983 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7984 Sched<[WriteAESIMCLd]>;
7986 // AES Round Key Generation Assist
7987 let Predicates = [HasAVX, HasAES] in {
7988 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7989 (ins VR128:$src1, i8imm:$src2),
7990 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7992 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7993 Sched<[WriteAESKeyGen]>, VEX;
7994 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7995 (ins i128mem:$src1, i8imm:$src2),
7996 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7998 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7999 Sched<[WriteAESKeyGenLd]>, VEX;
8001 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
8002 (ins VR128:$src1, i8imm:$src2),
8003 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8005 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
8006 Sched<[WriteAESKeyGen]>;
8007 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
8008 (ins i128mem:$src1, i8imm:$src2),
8009 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8011 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
8012 Sched<[WriteAESKeyGenLd]>;
8014 //===----------------------------------------------------------------------===//
8015 // PCLMUL Instructions
8016 //===----------------------------------------------------------------------===//
8018 // AVX carry-less Multiplication instructions
8019 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8020 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8021 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8023 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
8024 Sched<[WriteCLMul]>;
8026 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8027 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8028 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8029 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8030 (loadv2i64 addr:$src2), imm:$src3))]>,
8031 Sched<[WriteCLMulLd, ReadAfterLd]>;
8033 // Carry-less Multiplication instructions
8034 let Constraints = "$src1 = $dst" in {
8035 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8036 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8037 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8039 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
8040 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
8042 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8043 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8044 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8045 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8046 (memopv2i64 addr:$src2), imm:$src3))],
8047 IIC_SSE_PCLMULQDQ_RM>,
8048 Sched<[WriteCLMulLd, ReadAfterLd]>;
8049 } // Constraints = "$src1 = $dst"
8052 multiclass pclmul_alias<string asm, int immop> {
8053 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8054 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
8056 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8057 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
8059 def : InstAlias<!strconcat("vpclmul", asm,
8060 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8061 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
8064 def : InstAlias<!strconcat("vpclmul", asm,
8065 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8066 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
8069 defm : pclmul_alias<"hqhq", 0x11>;
8070 defm : pclmul_alias<"hqlq", 0x01>;
8071 defm : pclmul_alias<"lqhq", 0x10>;
8072 defm : pclmul_alias<"lqlq", 0x00>;
8074 //===----------------------------------------------------------------------===//
8075 // SSE4A Instructions
8076 //===----------------------------------------------------------------------===//
8078 let Predicates = [HasSSE4A] in {
8080 let Constraints = "$src = $dst" in {
8081 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
8082 (ins VR128:$src, i8imm:$len, i8imm:$idx),
8083 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
8084 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
8086 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8087 (ins VR128:$src, VR128:$mask),
8088 "extrq\t{$mask, $src|$src, $mask}",
8089 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
8090 VR128:$mask))]>, PD;
8092 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
8093 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
8094 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
8095 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
8096 VR128:$src2, imm:$len, imm:$idx))]>, XD;
8097 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8098 (ins VR128:$src, VR128:$mask),
8099 "insertq\t{$mask, $src|$src, $mask}",
8100 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
8101 VR128:$mask))]>, XD;
8104 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
8105 "movntss\t{$src, $dst|$dst, $src}",
8106 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
8108 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
8109 "movntsd\t{$src, $dst|$dst, $src}",
8110 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
8113 //===----------------------------------------------------------------------===//
8115 //===----------------------------------------------------------------------===//
8117 //===----------------------------------------------------------------------===//
8118 // VBROADCAST - Load from memory and broadcast to all elements of the
8119 // destination operand
8121 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
8122 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
8123 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8124 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8125 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
8127 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
8128 X86MemOperand x86memop, ValueType VT,
8129 PatFrag ld_frag, SchedWrite Sched> :
8130 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8131 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8132 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
8133 Sched<[Sched]>, VEX {
8137 // AVX2 adds register forms
8138 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
8139 Intrinsic Int, SchedWrite Sched> :
8140 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8141 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8142 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
8144 let ExeDomain = SSEPackedSingle in {
8145 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
8146 f32mem, v4f32, loadf32, WriteLoad>;
8147 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
8148 f32mem, v8f32, loadf32,
8149 WriteFShuffleLd>, VEX_L;
8151 let ExeDomain = SSEPackedDouble in
8152 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
8153 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
8154 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
8155 int_x86_avx_vbroadcastf128_pd_256,
8156 WriteFShuffleLd>, VEX_L;
8158 let ExeDomain = SSEPackedSingle in {
8159 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
8160 int_x86_avx2_vbroadcast_ss_ps,
8162 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
8163 int_x86_avx2_vbroadcast_ss_ps_256,
8164 WriteFShuffle256>, VEX_L;
8166 let ExeDomain = SSEPackedDouble in
8167 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
8168 int_x86_avx2_vbroadcast_sd_pd_256,
8169 WriteFShuffle256>, VEX_L;
8171 let Predicates = [HasAVX2] in
8172 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
8173 int_x86_avx2_vbroadcasti128, WriteLoad>,
8176 let Predicates = [HasAVX] in
8177 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
8178 (VBROADCASTF128 addr:$src)>;
8181 //===----------------------------------------------------------------------===//
8182 // VINSERTF128 - Insert packed floating-point values
8184 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
8185 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8186 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8187 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8188 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
8190 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
8191 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
8192 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8193 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
8196 let Predicates = [HasAVX] in {
8197 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
8199 (VINSERTF128rr VR256:$src1, VR128:$src2,
8200 (INSERT_get_vinsert128_imm VR256:$ins))>;
8201 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
8203 (VINSERTF128rr VR256:$src1, VR128:$src2,
8204 (INSERT_get_vinsert128_imm VR256:$ins))>;
8206 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
8208 (VINSERTF128rm VR256:$src1, addr:$src2,
8209 (INSERT_get_vinsert128_imm VR256:$ins))>;
8210 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
8212 (VINSERTF128rm VR256:$src1, addr:$src2,
8213 (INSERT_get_vinsert128_imm VR256:$ins))>;
8216 let Predicates = [HasAVX1Only] in {
8217 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8219 (VINSERTF128rr VR256:$src1, VR128:$src2,
8220 (INSERT_get_vinsert128_imm VR256:$ins))>;
8221 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8223 (VINSERTF128rr VR256:$src1, VR128:$src2,
8224 (INSERT_get_vinsert128_imm VR256:$ins))>;
8225 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8227 (VINSERTF128rr VR256:$src1, VR128:$src2,
8228 (INSERT_get_vinsert128_imm VR256:$ins))>;
8229 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8231 (VINSERTF128rr VR256:$src1, VR128:$src2,
8232 (INSERT_get_vinsert128_imm VR256:$ins))>;
8234 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8236 (VINSERTF128rm VR256:$src1, addr:$src2,
8237 (INSERT_get_vinsert128_imm VR256:$ins))>;
8238 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8239 (bc_v4i32 (loadv2i64 addr:$src2)),
8241 (VINSERTF128rm VR256:$src1, addr:$src2,
8242 (INSERT_get_vinsert128_imm VR256:$ins))>;
8243 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8244 (bc_v16i8 (loadv2i64 addr:$src2)),
8246 (VINSERTF128rm VR256:$src1, addr:$src2,
8247 (INSERT_get_vinsert128_imm VR256:$ins))>;
8248 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8249 (bc_v8i16 (loadv2i64 addr:$src2)),
8251 (VINSERTF128rm VR256:$src1, addr:$src2,
8252 (INSERT_get_vinsert128_imm VR256:$ins))>;
8255 //===----------------------------------------------------------------------===//
8256 // VEXTRACTF128 - Extract packed floating-point values
8258 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
8259 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
8260 (ins VR256:$src1, i8imm:$src2),
8261 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8262 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
8264 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
8265 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
8266 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8267 []>, Sched<[WriteStore]>, VEX, VEX_L;
8271 let Predicates = [HasAVX] in {
8272 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8273 (v4f32 (VEXTRACTF128rr
8274 (v8f32 VR256:$src1),
8275 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8276 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8277 (v2f64 (VEXTRACTF128rr
8278 (v4f64 VR256:$src1),
8279 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8281 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
8282 (iPTR imm))), addr:$dst),
8283 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8284 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8285 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
8286 (iPTR imm))), addr:$dst),
8287 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8288 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8291 let Predicates = [HasAVX1Only] in {
8292 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8293 (v2i64 (VEXTRACTF128rr
8294 (v4i64 VR256:$src1),
8295 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8296 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8297 (v4i32 (VEXTRACTF128rr
8298 (v8i32 VR256:$src1),
8299 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8300 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8301 (v8i16 (VEXTRACTF128rr
8302 (v16i16 VR256:$src1),
8303 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8304 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8305 (v16i8 (VEXTRACTF128rr
8306 (v32i8 VR256:$src1),
8307 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8309 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8310 (iPTR imm))), addr:$dst),
8311 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8312 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8313 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8314 (iPTR imm))), addr:$dst),
8315 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8316 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8317 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8318 (iPTR imm))), addr:$dst),
8319 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8320 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8321 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8322 (iPTR imm))), addr:$dst),
8323 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8324 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8327 //===----------------------------------------------------------------------===//
8328 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8330 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8331 Intrinsic IntLd, Intrinsic IntLd256,
8332 Intrinsic IntSt, Intrinsic IntSt256> {
8333 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8334 (ins VR128:$src1, f128mem:$src2),
8335 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8336 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8338 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8339 (ins VR256:$src1, f256mem:$src2),
8340 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8341 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8343 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8344 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8345 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8346 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8347 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8348 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8349 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8350 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8353 let ExeDomain = SSEPackedSingle in
8354 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8355 int_x86_avx_maskload_ps,
8356 int_x86_avx_maskload_ps_256,
8357 int_x86_avx_maskstore_ps,
8358 int_x86_avx_maskstore_ps_256>;
8359 let ExeDomain = SSEPackedDouble in
8360 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8361 int_x86_avx_maskload_pd,
8362 int_x86_avx_maskload_pd_256,
8363 int_x86_avx_maskstore_pd,
8364 int_x86_avx_maskstore_pd_256>;
8366 //===----------------------------------------------------------------------===//
8367 // VPERMIL - Permute Single and Double Floating-Point Values
8369 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8370 RegisterClass RC, X86MemOperand x86memop_f,
8371 X86MemOperand x86memop_i, PatFrag i_frag,
8372 Intrinsic IntVar, ValueType vt> {
8373 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8374 (ins RC:$src1, RC:$src2),
8375 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8376 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8377 Sched<[WriteFShuffle]>;
8378 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8379 (ins RC:$src1, x86memop_i:$src2),
8380 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8381 [(set RC:$dst, (IntVar RC:$src1,
8382 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8383 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8385 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8386 (ins RC:$src1, i8imm:$src2),
8387 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8388 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX,
8389 Sched<[WriteFShuffle]>;
8390 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8391 (ins x86memop_f:$src1, i8imm:$src2),
8392 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8394 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX,
8395 Sched<[WriteFShuffleLd]>;
8398 let ExeDomain = SSEPackedSingle in {
8399 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8400 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8401 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8402 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8404 let ExeDomain = SSEPackedDouble in {
8405 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8406 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8407 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8408 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8411 let Predicates = [HasAVX] in {
8412 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
8413 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8414 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
8415 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8416 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (loadv4i64 addr:$src1)),
8418 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8419 def : Pat<(v4i64 (X86VPermilp (loadv4i64 addr:$src1), (i8 imm:$imm))),
8420 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8422 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
8423 (VPERMILPDri VR128:$src1, imm:$imm)>;
8424 def : Pat<(v2i64 (X86VPermilp (loadv2i64 addr:$src1), (i8 imm:$imm))),
8425 (VPERMILPDmi addr:$src1, imm:$imm)>;
8428 //===----------------------------------------------------------------------===//
8429 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8431 let ExeDomain = SSEPackedSingle in {
8432 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8433 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8434 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8435 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8436 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8437 Sched<[WriteFShuffle]>;
8438 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8439 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8440 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8441 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8442 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8443 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8446 let Predicates = [HasAVX] in {
8447 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8448 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8449 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8450 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8451 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8454 let Predicates = [HasAVX1Only] in {
8455 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8456 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8457 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8458 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8459 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8460 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8461 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8462 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8464 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8465 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8466 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8467 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8468 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8469 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8470 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8471 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8472 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8473 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8474 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8475 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8478 //===----------------------------------------------------------------------===//
8479 // VZERO - Zero YMM registers
8481 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8482 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8483 // Zero All YMM registers
8484 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8485 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8487 // Zero Upper bits of YMM registers
8488 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8489 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8492 //===----------------------------------------------------------------------===//
8493 // Half precision conversion instructions
8494 //===----------------------------------------------------------------------===//
8495 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8496 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8497 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8498 [(set RC:$dst, (Int VR128:$src))]>,
8499 T8PD, VEX, Sched<[WriteCvtF2F]>;
8500 let neverHasSideEffects = 1, mayLoad = 1 in
8501 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8502 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8503 Sched<[WriteCvtF2FLd]>;
8506 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8507 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8508 (ins RC:$src1, i32i8imm:$src2),
8509 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8510 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8511 TAPD, VEX, Sched<[WriteCvtF2F]>;
8512 let neverHasSideEffects = 1, mayStore = 1,
8513 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8514 def mr : Ii8<0x1D, MRMDestMem, (outs),
8515 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8516 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8520 let Predicates = [HasF16C] in {
8521 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8522 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8523 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8524 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8526 // Pattern match vcvtph2ps of a scalar i64 load.
8527 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8528 (VCVTPH2PSrm addr:$src)>;
8529 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8530 (VCVTPH2PSrm addr:$src)>;
8533 //===----------------------------------------------------------------------===//
8534 // AVX2 Instructions
8535 //===----------------------------------------------------------------------===//
8537 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8538 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8539 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8540 X86MemOperand x86memop> {
8541 let isCommutable = 1 in
8542 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8543 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
8544 !strconcat(OpcodeStr,
8545 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8546 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8547 Sched<[WriteBlend]>, VEX_4V;
8548 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8549 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
8550 !strconcat(OpcodeStr,
8551 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8554 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8555 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8558 let isCommutable = 0 in {
8559 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8560 VR128, loadv2i64, i128mem>;
8561 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8562 VR256, loadv4i64, i256mem>, VEX_L;
8565 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8567 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8568 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8570 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8572 //===----------------------------------------------------------------------===//
8573 // VPBROADCAST - Load from memory and broadcast to all elements of the
8574 // destination operand
8576 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8577 X86MemOperand x86memop, PatFrag ld_frag,
8578 Intrinsic Int128, Intrinsic Int256> {
8579 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8581 [(set VR128:$dst, (Int128 VR128:$src))]>,
8582 Sched<[WriteShuffle]>, VEX;
8583 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8586 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8587 Sched<[WriteLoad]>, VEX;
8588 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8589 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8590 [(set VR256:$dst, (Int256 VR128:$src))]>,
8591 Sched<[WriteShuffle256]>, VEX, VEX_L;
8592 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8593 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8595 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8596 Sched<[WriteLoad]>, VEX, VEX_L;
8599 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8600 int_x86_avx2_pbroadcastb_128,
8601 int_x86_avx2_pbroadcastb_256>;
8602 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8603 int_x86_avx2_pbroadcastw_128,
8604 int_x86_avx2_pbroadcastw_256>;
8605 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8606 int_x86_avx2_pbroadcastd_128,
8607 int_x86_avx2_pbroadcastd_256>;
8608 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8609 int_x86_avx2_pbroadcastq_128,
8610 int_x86_avx2_pbroadcastq_256>;
8612 let Predicates = [HasAVX2] in {
8613 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8614 (VPBROADCASTBrm addr:$src)>;
8615 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8616 (VPBROADCASTBYrm addr:$src)>;
8617 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8618 (VPBROADCASTWrm addr:$src)>;
8619 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8620 (VPBROADCASTWYrm addr:$src)>;
8621 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8622 (VPBROADCASTDrm addr:$src)>;
8623 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8624 (VPBROADCASTDYrm addr:$src)>;
8625 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8626 (VPBROADCASTQrm addr:$src)>;
8627 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8628 (VPBROADCASTQYrm addr:$src)>;
8630 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8631 (VPBROADCASTBrr VR128:$src)>;
8632 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8633 (VPBROADCASTBYrr VR128:$src)>;
8634 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8635 (VPBROADCASTWrr VR128:$src)>;
8636 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8637 (VPBROADCASTWYrr VR128:$src)>;
8638 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8639 (VPBROADCASTDrr VR128:$src)>;
8640 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8641 (VPBROADCASTDYrr VR128:$src)>;
8642 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8643 (VPBROADCASTQrr VR128:$src)>;
8644 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8645 (VPBROADCASTQYrr VR128:$src)>;
8646 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8647 (VBROADCASTSSrr VR128:$src)>;
8648 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8649 (VBROADCASTSSYrr VR128:$src)>;
8650 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8651 (VPBROADCASTQrr VR128:$src)>;
8652 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8653 (VBROADCASTSDYrr VR128:$src)>;
8655 // Provide fallback in case the load node that is used in the patterns above
8656 // is used by additional users, which prevents the pattern selection.
8657 let AddedComplexity = 20 in {
8658 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8659 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8660 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8661 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8662 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8663 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8665 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8666 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8667 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8668 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8669 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8670 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8672 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8673 (VPBROADCASTBrr (COPY_TO_REGCLASS
8674 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8676 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8677 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8678 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8681 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8682 (VPBROADCASTWrr (COPY_TO_REGCLASS
8683 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8685 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8686 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8687 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8690 // The patterns for VPBROADCASTD are not needed because they would match
8691 // the exact same thing as VBROADCASTSS patterns.
8693 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8694 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8695 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8699 // AVX1 broadcast patterns
8700 let Predicates = [HasAVX1Only] in {
8701 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8702 (VBROADCASTSSYrm addr:$src)>;
8703 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8704 (VBROADCASTSDYrm addr:$src)>;
8705 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8706 (VBROADCASTSSrm addr:$src)>;
8709 let Predicates = [HasAVX] in {
8710 // Provide fallback in case the load node that is used in the patterns above
8711 // is used by additional users, which prevents the pattern selection.
8712 let AddedComplexity = 20 in {
8713 // 128bit broadcasts:
8714 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8715 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8716 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8717 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8718 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8719 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8720 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8721 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8722 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8723 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8725 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8726 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8727 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8728 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8729 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8730 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8731 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8732 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8733 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8734 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8738 //===----------------------------------------------------------------------===//
8739 // VPERM - Permute instructions
8742 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8744 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8745 (ins VR256:$src1, VR256:$src2),
8746 !strconcat(OpcodeStr,
8747 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8749 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8750 Sched<[WriteFShuffle256]>, VEX_4V, VEX_L;
8751 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8752 (ins VR256:$src1, i256mem:$src2),
8753 !strconcat(OpcodeStr,
8754 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8756 (OpVT (X86VPermv VR256:$src1,
8757 (bitconvert (mem_frag addr:$src2)))))]>,
8758 Sched<[WriteFShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8761 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32>;
8762 let ExeDomain = SSEPackedSingle in
8763 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32>;
8765 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8767 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8768 (ins VR256:$src1, i8imm:$src2),
8769 !strconcat(OpcodeStr,
8770 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8772 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8773 Sched<[WriteShuffle256]>, VEX, VEX_L;
8774 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8775 (ins i256mem:$src1, i8imm:$src2),
8776 !strconcat(OpcodeStr,
8777 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8779 (OpVT (X86VPermi (mem_frag addr:$src1),
8780 (i8 imm:$src2))))]>,
8781 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX, VEX_L;
8784 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64>, VEX_W;
8785 let ExeDomain = SSEPackedDouble in
8786 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64>, VEX_W;
8788 //===----------------------------------------------------------------------===//
8789 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8791 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8792 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8793 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8794 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8795 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8797 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8798 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8799 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8800 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8802 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8804 let Predicates = [HasAVX2] in {
8805 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8806 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8807 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8808 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8809 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8810 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8812 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8814 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8815 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8816 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8817 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8818 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8820 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8824 //===----------------------------------------------------------------------===//
8825 // VINSERTI128 - Insert packed integer values
8827 let neverHasSideEffects = 1 in {
8828 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8829 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8830 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8831 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8833 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8834 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8835 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8836 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8839 let Predicates = [HasAVX2] in {
8840 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8842 (VINSERTI128rr VR256:$src1, VR128:$src2,
8843 (INSERT_get_vinsert128_imm VR256:$ins))>;
8844 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8846 (VINSERTI128rr VR256:$src1, VR128:$src2,
8847 (INSERT_get_vinsert128_imm VR256:$ins))>;
8848 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8850 (VINSERTI128rr VR256:$src1, VR128:$src2,
8851 (INSERT_get_vinsert128_imm VR256:$ins))>;
8852 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8854 (VINSERTI128rr VR256:$src1, VR128:$src2,
8855 (INSERT_get_vinsert128_imm VR256:$ins))>;
8857 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8859 (VINSERTI128rm VR256:$src1, addr:$src2,
8860 (INSERT_get_vinsert128_imm VR256:$ins))>;
8861 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8862 (bc_v4i32 (loadv2i64 addr:$src2)),
8864 (VINSERTI128rm VR256:$src1, addr:$src2,
8865 (INSERT_get_vinsert128_imm VR256:$ins))>;
8866 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8867 (bc_v16i8 (loadv2i64 addr:$src2)),
8869 (VINSERTI128rm VR256:$src1, addr:$src2,
8870 (INSERT_get_vinsert128_imm VR256:$ins))>;
8871 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8872 (bc_v8i16 (loadv2i64 addr:$src2)),
8874 (VINSERTI128rm VR256:$src1, addr:$src2,
8875 (INSERT_get_vinsert128_imm VR256:$ins))>;
8878 //===----------------------------------------------------------------------===//
8879 // VEXTRACTI128 - Extract packed integer values
8881 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8882 (ins VR256:$src1, i8imm:$src2),
8883 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8885 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8886 Sched<[WriteShuffle256]>, VEX, VEX_L;
8887 let neverHasSideEffects = 1, mayStore = 1 in
8888 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8889 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8890 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8891 Sched<[WriteStore]>, VEX, VEX_L;
8893 let Predicates = [HasAVX2] in {
8894 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8895 (v2i64 (VEXTRACTI128rr
8896 (v4i64 VR256:$src1),
8897 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8898 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8899 (v4i32 (VEXTRACTI128rr
8900 (v8i32 VR256:$src1),
8901 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8902 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8903 (v8i16 (VEXTRACTI128rr
8904 (v16i16 VR256:$src1),
8905 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8906 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8907 (v16i8 (VEXTRACTI128rr
8908 (v32i8 VR256:$src1),
8909 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8911 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8912 (iPTR imm))), addr:$dst),
8913 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8914 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8915 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8916 (iPTR imm))), addr:$dst),
8917 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8918 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8919 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8920 (iPTR imm))), addr:$dst),
8921 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8922 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8923 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8924 (iPTR imm))), addr:$dst),
8925 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8926 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8929 //===----------------------------------------------------------------------===//
8930 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8932 multiclass avx2_pmovmask<string OpcodeStr,
8933 Intrinsic IntLd128, Intrinsic IntLd256,
8934 Intrinsic IntSt128, Intrinsic IntSt256> {
8935 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8936 (ins VR128:$src1, i128mem:$src2),
8937 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8938 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8939 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8940 (ins VR256:$src1, i256mem:$src2),
8941 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8942 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8944 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8945 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8946 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8947 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8948 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8949 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8950 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8951 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8954 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8955 int_x86_avx2_maskload_d,
8956 int_x86_avx2_maskload_d_256,
8957 int_x86_avx2_maskstore_d,
8958 int_x86_avx2_maskstore_d_256>;
8959 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8960 int_x86_avx2_maskload_q,
8961 int_x86_avx2_maskload_q_256,
8962 int_x86_avx2_maskstore_q,
8963 int_x86_avx2_maskstore_q_256>, VEX_W;
8966 //===----------------------------------------------------------------------===//
8967 // Variable Bit Shifts
8969 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8970 ValueType vt128, ValueType vt256> {
8971 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8972 (ins VR128:$src1, VR128:$src2),
8973 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8975 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8976 VEX_4V, Sched<[WriteVarVecShift]>;
8977 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8978 (ins VR128:$src1, i128mem:$src2),
8979 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8981 (vt128 (OpNode VR128:$src1,
8982 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8983 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8984 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8985 (ins VR256:$src1, VR256:$src2),
8986 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8988 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8989 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8990 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8991 (ins VR256:$src1, i256mem:$src2),
8992 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8994 (vt256 (OpNode VR256:$src1,
8995 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8996 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8999 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
9000 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
9001 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
9002 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
9003 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
9005 //===----------------------------------------------------------------------===//
9006 // VGATHER - GATHER Operations
9007 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
9008 X86MemOperand memop128, X86MemOperand memop256> {
9009 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
9010 (ins VR128:$src1, memop128:$src2, VR128:$mask),
9011 !strconcat(OpcodeStr,
9012 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9014 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
9015 (ins RC256:$src1, memop256:$src2, RC256:$mask),
9016 !strconcat(OpcodeStr,
9017 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9018 []>, VEX_4VOp3, VEX_L;
9021 let mayLoad = 1, Constraints
9022 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
9024 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
9025 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
9026 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
9027 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
9029 let ExeDomain = SSEPackedDouble in {
9030 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
9031 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
9034 let ExeDomain = SSEPackedSingle in {
9035 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
9036 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;