1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
246 let isCommutable = 1 in {
247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
252 Sched<[itins.Sched]>;
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
262 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
263 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
264 string asm, string SSEVer, string FPSizeStr,
265 Operand memopr, ComplexPattern mem_cpat,
268 let isCodeGenOnly = 1 in {
269 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
271 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
272 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 [(set RC:$dst, (!cast<Intrinsic>(
274 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
275 RC:$src1, RC:$src2))], itins.rr>,
276 Sched<[itins.Sched]>;
277 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
279 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
280 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
281 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
282 SSEVer, "_", OpcodeStr, FPSizeStr))
283 RC:$src1, mem_cpat:$src2))], itins.rm>,
284 Sched<[itins.Sched.Folded, ReadAfterLd]>;
288 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
290 RegisterClass RC, ValueType vt,
291 X86MemOperand x86memop, PatFrag mem_frag,
292 Domain d, OpndItins itins, bit Is2Addr = 1> {
293 let isCommutable = 1 in
294 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
297 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
299 Sched<[itins.Sched]>;
301 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
307 Sched<[itins.Sched.Folded, ReadAfterLd]>;
310 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
311 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
312 string OpcodeStr, X86MemOperand x86memop,
313 list<dag> pat_rr, list<dag> pat_rm,
315 let isCommutable = 1, hasSideEffects = 0 in
316 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
320 pat_rr, NoItinerary, d>,
321 Sched<[WriteVecLogic]>;
322 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
326 pat_rm, NoItinerary, d>,
327 Sched<[WriteVecLogicLd, ReadAfterLd]>;
330 //===----------------------------------------------------------------------===//
331 // Non-instruction patterns
332 //===----------------------------------------------------------------------===//
334 // A vector extract of the first f32/f64 position is a subregister copy
335 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
337 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
338 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
340 // A 128-bit subvector extract from the first 256-bit vector position
341 // is a subregister copy that needs no instruction.
342 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
343 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
347 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
348 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
353 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
357 // A 128-bit subvector insert to the first 256-bit vector position
358 // is a subregister copy that needs no instruction.
359 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
360 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
374 // Implicitly promote a 32-bit scalar to a vector.
375 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
378 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 // Implicitly promote a 64-bit scalar to a vector.
380 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
382 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
383 (COPY_TO_REGCLASS FR64:$src, VR128)>;
385 // Bitcasts between 128-bit vector types. Return the original type since
386 // no instruction is needed for the conversion
387 let Predicates = [HasSSE2] in {
388 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
397 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
402 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
407 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
417 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr> {
570 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
571 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
574 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
576 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
577 VEX, VEX_LIG, Sched<[WriteStore]>;
579 let Constraints = "$src1 = $dst" in {
580 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
581 "\t{$src2, $dst|$dst, $src2}">;
584 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
586 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
590 // Loading from memory automatically zeroing upper bits.
591 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
592 PatFrag mem_pat, string OpcodeStr> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
604 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
606 let canFoldAsLoad = 1, isReMaterializable = 1 in {
607 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
609 let AddedComplexity = 20 in
610 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
614 let Predicates = [UseAVX] in {
615 let AddedComplexity = 20 in {
616 // MOVSSrm zeros the high parts of the register; represent this
617 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
618 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
619 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
620 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
621 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
622 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
625 // MOVSDrm zeros the high parts of the register; represent this
626 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
627 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
628 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
629 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
630 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
631 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzload addr:$src)),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
638 // Represent the same patterns above but in the form they appear for
640 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
641 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
642 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
643 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
644 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
645 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
646 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
647 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
648 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
650 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
651 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
652 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
654 // Extract and store.
655 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
657 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
658 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
660 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
662 // Shuffle with VMOVSS
663 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
664 (VMOVSSrr (v4i32 VR128:$src1),
665 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
666 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
667 (VMOVSSrr (v4f32 VR128:$src1),
668 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
671 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
672 (SUBREG_TO_REG (i32 0),
673 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
674 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
676 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
677 (SUBREG_TO_REG (i32 0),
678 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
679 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
682 // Shuffle with VMOVSD
683 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
689 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
690 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
693 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
694 (SUBREG_TO_REG (i32 0),
695 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
696 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
698 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
699 (SUBREG_TO_REG (i32 0),
700 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
701 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
704 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
705 // is during lowering, where it's not possible to recognize the fold cause
706 // it has two uses through a bitcast. One use disappears at isel time and the
707 // fold opportunity reappears.
708 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
714 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
715 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
718 let Predicates = [UseSSE1] in {
719 let Predicates = [NoSSE41], AddedComplexity = 15 in {
720 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
721 // MOVSS to the lower bits.
722 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
723 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
724 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
725 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
726 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
727 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
730 let AddedComplexity = 20 in {
731 // MOVSSrm already zeros the high parts of the register.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
743 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
745 // Shuffle with MOVSS
746 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
748 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
749 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
752 let Predicates = [UseSSE2] in {
753 let Predicates = [NoSSE41], AddedComplexity = 15 in {
754 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
755 // MOVSD to the lower bits.
756 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
757 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
760 let AddedComplexity = 20 in {
761 // MOVSDrm already zeros the high parts of the register.
762 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
770 def : Pat<(v2f64 (X86vzload addr:$src)),
771 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
774 // Extract and store.
775 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
777 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
779 // Shuffle with MOVSD
780 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
786 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
787 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
789 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
790 // is during lowering, where it's not possible to recognize the fold cause
791 // it has two uses through a bitcast. One use disappears at isel time and the
792 // fold opportunity reappears.
793 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
799 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
800 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
803 //===----------------------------------------------------------------------===//
804 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
805 //===----------------------------------------------------------------------===//
807 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
808 X86MemOperand x86memop, PatFrag ld_frag,
809 string asm, Domain d,
811 bit IsReMaterializable = 1> {
812 let hasSideEffects = 0 in
813 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
814 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
815 Sched<[WriteFShuffle]>;
816 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
817 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
818 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
819 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
823 let Predicates = [HasAVX, NoVLX] in {
824 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
830 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
837 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
838 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
840 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
841 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
843 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
844 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
846 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
847 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
851 let Predicates = [UseSSE1] in {
852 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
853 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
855 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
856 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
859 let Predicates = [UseSSE2] in {
860 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
861 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
863 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
864 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
868 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
869 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
870 "movaps\t{$src, $dst|$dst, $src}",
871 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
872 IIC_SSE_MOVA_P_MR>, VEX;
873 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
874 "movapd\t{$src, $dst|$dst, $src}",
875 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
876 IIC_SSE_MOVA_P_MR>, VEX;
877 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
878 "movups\t{$src, $dst|$dst, $src}",
879 [(store (v4f32 VR128:$src), addr:$dst)],
880 IIC_SSE_MOVU_P_MR>, VEX;
881 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
882 "movupd\t{$src, $dst|$dst, $src}",
883 [(store (v2f64 VR128:$src), addr:$dst)],
884 IIC_SSE_MOVU_P_MR>, VEX;
885 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
886 "movaps\t{$src, $dst|$dst, $src}",
887 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
888 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
889 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
890 "movapd\t{$src, $dst|$dst, $src}",
891 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
892 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
893 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
894 "movups\t{$src, $dst|$dst, $src}",
895 [(store (v8f32 VR256:$src), addr:$dst)],
896 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
897 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
898 "movupd\t{$src, $dst|$dst, $src}",
899 [(store (v4f64 VR256:$src), addr:$dst)],
900 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
904 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
905 SchedRW = [WriteFShuffle] in {
906 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
908 "movaps\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX;
910 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
912 "movapd\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVA_P_RR>, VEX;
914 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
916 "movups\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX;
918 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
920 "movupd\t{$src, $dst|$dst, $src}", [],
921 IIC_SSE_MOVU_P_RR>, VEX;
922 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
924 "movaps\t{$src, $dst|$dst, $src}", [],
925 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
926 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
928 "movapd\t{$src, $dst|$dst, $src}", [],
929 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
930 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
932 "movups\t{$src, $dst|$dst, $src}", [],
933 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
934 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
936 "movupd\t{$src, $dst|$dst, $src}", [],
937 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
940 let Predicates = [HasAVX] in {
941 def : Pat<(v8i32 (X86vzmovl
942 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
943 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
944 def : Pat<(v4i64 (X86vzmovl
945 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
946 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
947 def : Pat<(v8f32 (X86vzmovl
948 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
949 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
950 def : Pat<(v4f64 (X86vzmovl
951 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
952 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
956 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
957 (VMOVUPSYmr addr:$dst, VR256:$src)>;
958 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
959 (VMOVUPDYmr addr:$dst, VR256:$src)>;
961 let SchedRW = [WriteStore] in {
962 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
963 "movaps\t{$src, $dst|$dst, $src}",
964 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
966 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
967 "movapd\t{$src, $dst|$dst, $src}",
968 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
970 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
971 "movups\t{$src, $dst|$dst, $src}",
972 [(store (v4f32 VR128:$src), addr:$dst)],
974 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
975 "movupd\t{$src, $dst|$dst, $src}",
976 [(store (v2f64 VR128:$src), addr:$dst)],
981 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
982 SchedRW = [WriteFShuffle] in {
983 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
984 "movaps\t{$src, $dst|$dst, $src}", [],
986 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
987 "movapd\t{$src, $dst|$dst, $src}", [],
989 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
990 "movups\t{$src, $dst|$dst, $src}", [],
992 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
993 "movupd\t{$src, $dst|$dst, $src}", [],
997 let Predicates = [HasAVX] in {
998 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
999 (VMOVUPSmr addr:$dst, VR128:$src)>;
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (VMOVUPDmr addr:$dst, VR128:$src)>;
1004 let Predicates = [UseSSE1] in
1005 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1006 (MOVUPSmr addr:$dst, VR128:$src)>;
1007 let Predicates = [UseSSE2] in
1008 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1009 (MOVUPDmr addr:$dst, VR128:$src)>;
1011 // Use vmovaps/vmovups for AVX integer load/store.
1012 let Predicates = [HasAVX, NoVLX] in {
1013 // 128-bit load/store
1014 def : Pat<(alignedloadv2i64 addr:$src),
1015 (VMOVAPSrm addr:$src)>;
1016 def : Pat<(loadv2i64 addr:$src),
1017 (VMOVUPSrm addr:$src)>;
1019 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1026 (VMOVAPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1033 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1034 (VMOVUPSmr addr:$dst, VR128:$src)>;
1036 // 256-bit load/store
1037 def : Pat<(alignedloadv4i64 addr:$src),
1038 (VMOVAPSYrm addr:$src)>;
1039 def : Pat<(loadv4i64 addr:$src),
1040 (VMOVUPSYrm addr:$src)>;
1041 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1048 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1055 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1056 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1058 // Special patterns for storing subvector extracts of lower 128-bits
1059 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1060 def : Pat<(alignedstore (v2f64 (extract_subvector
1061 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1062 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1063 def : Pat<(alignedstore (v4f32 (extract_subvector
1064 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1065 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1066 def : Pat<(alignedstore (v2i64 (extract_subvector
1067 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1068 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1069 def : Pat<(alignedstore (v4i32 (extract_subvector
1070 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1071 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1072 def : Pat<(alignedstore (v8i16 (extract_subvector
1073 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1074 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1075 def : Pat<(alignedstore (v16i8 (extract_subvector
1076 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1077 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1079 def : Pat<(store (v2f64 (extract_subvector
1080 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1081 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1082 def : Pat<(store (v4f32 (extract_subvector
1083 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1084 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1085 def : Pat<(store (v2i64 (extract_subvector
1086 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1087 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1088 def : Pat<(store (v4i32 (extract_subvector
1089 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1090 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1091 def : Pat<(store (v8i16 (extract_subvector
1092 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1093 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1094 def : Pat<(store (v16i8 (extract_subvector
1095 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1096 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1099 // Use movaps / movups for SSE integer load / store (one byte shorter).
1100 // The instructions selected below are then converted to MOVDQA/MOVDQU
1101 // during the SSE domain pass.
1102 let Predicates = [UseSSE1] in {
1103 def : Pat<(alignedloadv2i64 addr:$src),
1104 (MOVAPSrm addr:$src)>;
1105 def : Pat<(loadv2i64 addr:$src),
1106 (MOVUPSrm addr:$src)>;
1108 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1115 (MOVAPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1122 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1123 (MOVUPSmr addr:$dst, VR128:$src)>;
1126 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1127 // bits are disregarded. FIXME: Set encoding to pseudo!
1128 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1129 let isCodeGenOnly = 1 in {
1130 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1131 "movaps\t{$src, $dst|$dst, $src}",
1132 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1133 IIC_SSE_MOVA_P_RM>, VEX;
1134 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1135 "movapd\t{$src, $dst|$dst, $src}",
1136 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1137 IIC_SSE_MOVA_P_RM>, VEX;
1138 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1139 "movaps\t{$src, $dst|$dst, $src}",
1140 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1142 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1143 "movapd\t{$src, $dst|$dst, $src}",
1144 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1149 //===----------------------------------------------------------------------===//
1150 // SSE 1 & 2 - Move Low packed FP Instructions
1151 //===----------------------------------------------------------------------===//
1153 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1154 string base_opc, string asm_opr,
1155 InstrItinClass itin> {
1156 def PSrm : PI<opc, MRMSrcMem,
1157 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1158 !strconcat(base_opc, "s", asm_opr),
1160 (psnode VR128:$src1,
1161 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1162 itin, SSEPackedSingle>, PS,
1163 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1165 def PDrm : PI<opc, MRMSrcMem,
1166 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1167 !strconcat(base_opc, "d", asm_opr),
1168 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1169 (scalar_to_vector (loadf64 addr:$src2)))))],
1170 itin, SSEPackedDouble>, PD,
1171 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1175 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1176 string base_opc, InstrItinClass itin> {
1177 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1178 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1181 let Constraints = "$src1 = $dst" in
1182 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1183 "\t{$src2, $dst|$dst, $src2}",
1187 let AddedComplexity = 20 in {
1188 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1192 let SchedRW = [WriteStore] in {
1193 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1194 "movlps\t{$src, $dst|$dst, $src}",
1195 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1196 (iPTR 0))), addr:$dst)],
1197 IIC_SSE_MOV_LH>, VEX;
1198 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1199 "movlpd\t{$src, $dst|$dst, $src}",
1200 [(store (f64 (vector_extract (v2f64 VR128:$src),
1201 (iPTR 0))), addr:$dst)],
1202 IIC_SSE_MOV_LH>, VEX;
1203 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1204 "movlps\t{$src, $dst|$dst, $src}",
1205 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1206 (iPTR 0))), addr:$dst)],
1208 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1209 "movlpd\t{$src, $dst|$dst, $src}",
1210 [(store (f64 (vector_extract (v2f64 VR128:$src),
1211 (iPTR 0))), addr:$dst)],
1215 let Predicates = [HasAVX] in {
1216 // Shuffle with VMOVLPS
1217 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1219 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1220 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1222 // Shuffle with VMOVLPD
1223 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1226 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1227 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1228 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1229 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1232 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1234 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1235 def : Pat<(store (v4i32 (X86Movlps
1236 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1237 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1238 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1240 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1243 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1246 let Predicates = [UseSSE1] in {
1247 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1248 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1249 (iPTR 0))), addr:$src1),
1250 (MOVLPSmr addr:$src1, VR128:$src2)>;
1252 // Shuffle with MOVLPS
1253 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1256 (MOVLPSrm VR128:$src1, addr:$src2)>;
1257 def : Pat<(X86Movlps VR128:$src1,
1258 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1259 (MOVLPSrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1264 (MOVLPSmr addr:$src1, VR128:$src2)>;
1265 def : Pat<(store (v4i32 (X86Movlps
1266 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1268 (MOVLPSmr addr:$src1, VR128:$src2)>;
1271 let Predicates = [UseSSE2] in {
1272 // Shuffle with MOVLPD
1273 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1276 (MOVLPDrm VR128:$src1, addr:$src2)>;
1277 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1278 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1279 (MOVLPDrm VR128:$src1, addr:$src2)>;
1282 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1284 (MOVLPDmr addr:$src1, VR128:$src2)>;
1285 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1287 (MOVLPDmr addr:$src1, VR128:$src2)>;
1290 //===----------------------------------------------------------------------===//
1291 // SSE 1 & 2 - Move Hi packed FP Instructions
1292 //===----------------------------------------------------------------------===//
1294 let AddedComplexity = 20 in {
1295 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1299 let SchedRW = [WriteStore] in {
1300 // v2f64 extract element 1 is always custom lowered to unpack high to low
1301 // and extract element 0 so the non-store version isn't too horrible.
1302 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1303 "movhps\t{$src, $dst|$dst, $src}",
1304 [(store (f64 (vector_extract
1305 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1306 (bc_v2f64 (v4f32 VR128:$src))),
1307 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1308 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1309 "movhpd\t{$src, $dst|$dst, $src}",
1310 [(store (f64 (vector_extract
1311 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1312 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1313 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1314 "movhps\t{$src, $dst|$dst, $src}",
1315 [(store (f64 (vector_extract
1316 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1317 (bc_v2f64 (v4f32 VR128:$src))),
1318 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1319 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1320 "movhpd\t{$src, $dst|$dst, $src}",
1321 [(store (f64 (vector_extract
1322 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1323 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1326 let Predicates = [HasAVX] in {
1328 def : Pat<(X86Movlhps VR128:$src1,
1329 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1330 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1331 def : Pat<(X86Movlhps VR128:$src1,
1332 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1333 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1337 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1338 // is during lowering, where it's not possible to recognize the load fold
1339 // cause it has two uses through a bitcast. One use disappears at isel time
1340 // and the fold opportunity reappears.
1341 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1342 (scalar_to_vector (loadf64 addr:$src2)))),
1343 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1344 // Also handle an i64 load because that may get selected as a faster way to
1346 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1347 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1348 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1350 def : Pat<(store (f64 (vector_extract
1351 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1352 (iPTR 0))), addr:$dst),
1353 (VMOVHPDmr addr:$dst, VR128:$src)>;
1356 let Predicates = [UseSSE1] in {
1358 def : Pat<(X86Movlhps VR128:$src1,
1359 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1360 (MOVHPSrm VR128:$src1, addr:$src2)>;
1361 def : Pat<(X86Movlhps VR128:$src1,
1362 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1363 (MOVHPSrm VR128:$src1, addr:$src2)>;
1366 let Predicates = [UseSSE2] in {
1369 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1370 // is during lowering, where it's not possible to recognize the load fold
1371 // cause it has two uses through a bitcast. One use disappears at isel time
1372 // and the fold opportunity reappears.
1373 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1374 (scalar_to_vector (loadf64 addr:$src2)))),
1375 (MOVHPDrm VR128:$src1, addr:$src2)>;
1376 // Also handle an i64 load because that may get selected as a faster way to
1378 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1379 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1380 (MOVHPDrm VR128:$src1, addr:$src2)>;
1382 def : Pat<(store (f64 (vector_extract
1383 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1384 (iPTR 0))), addr:$dst),
1385 (MOVHPDmr addr:$dst, VR128:$src)>;
1388 //===----------------------------------------------------------------------===//
1389 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1390 //===----------------------------------------------------------------------===//
1392 let AddedComplexity = 20, Predicates = [UseAVX] in {
1393 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1394 (ins VR128:$src1, VR128:$src2),
1395 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1397 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1399 VEX_4V, Sched<[WriteFShuffle]>;
1400 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1401 (ins VR128:$src1, VR128:$src2),
1402 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1404 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1406 VEX_4V, Sched<[WriteFShuffle]>;
1408 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1409 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1410 (ins VR128:$src1, VR128:$src2),
1411 "movlhps\t{$src2, $dst|$dst, $src2}",
1413 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1414 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1415 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1416 (ins VR128:$src1, VR128:$src2),
1417 "movhlps\t{$src2, $dst|$dst, $src2}",
1419 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1420 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1423 let Predicates = [UseAVX] in {
1425 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1427 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1428 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1431 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1432 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1435 let Predicates = [UseSSE1] in {
1437 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1439 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1440 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1443 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1444 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1447 //===----------------------------------------------------------------------===//
1448 // SSE 1 & 2 - Conversion Instructions
1449 //===----------------------------------------------------------------------===//
1451 def SSE_CVT_PD : OpndItins<
1452 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1455 let Sched = WriteCvtI2F in
1456 def SSE_CVT_PS : OpndItins<
1457 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1460 let Sched = WriteCvtI2F in
1461 def SSE_CVT_Scalar : OpndItins<
1462 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1465 let Sched = WriteCvtF2I in
1466 def SSE_CVT_SS2SI_32 : OpndItins<
1467 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1470 let Sched = WriteCvtF2I in
1471 def SSE_CVT_SS2SI_64 : OpndItins<
1472 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1475 let Sched = WriteCvtF2I in
1476 def SSE_CVT_SD2SI : OpndItins<
1477 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1480 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1481 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1482 string asm, OpndItins itins> {
1483 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1484 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1485 itins.rr>, Sched<[itins.Sched]>;
1486 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1487 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1488 itins.rm>, Sched<[itins.Sched.Folded]>;
1491 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1492 X86MemOperand x86memop, string asm, Domain d,
1494 let hasSideEffects = 0 in {
1495 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1496 [], itins.rr, d>, Sched<[itins.Sched]>;
1498 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1499 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1503 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1504 X86MemOperand x86memop, string asm> {
1505 let hasSideEffects = 0, Predicates = [UseAVX] in {
1506 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1507 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1508 Sched<[WriteCvtI2F]>;
1510 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1511 (ins DstRC:$src1, x86memop:$src),
1512 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1513 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1514 } // hasSideEffects = 0
1517 let Predicates = [UseAVX] in {
1518 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1519 "cvttss2si\t{$src, $dst|$dst, $src}",
1522 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1523 "cvttss2si\t{$src, $dst|$dst, $src}",
1525 XS, VEX, VEX_W, VEX_LIG;
1526 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1527 "cvttsd2si\t{$src, $dst|$dst, $src}",
1530 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1531 "cvttsd2si\t{$src, $dst|$dst, $src}",
1533 XD, VEX, VEX_W, VEX_LIG;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1537 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1541 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1545 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1549 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1550 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1552 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1553 // register, but the same isn't true when only using memory operands,
1554 // provide other assembly "l" and "q" forms to address this explicitly
1555 // where appropriate to do so.
1556 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1557 XS, VEX_4V, VEX_LIG;
1558 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1559 XS, VEX_4V, VEX_W, VEX_LIG;
1560 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1561 XD, VEX_4V, VEX_LIG;
1562 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1563 XD, VEX_4V, VEX_W, VEX_LIG;
1565 let Predicates = [UseAVX] in {
1566 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1568 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1569 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1571 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1572 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1574 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1576 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1577 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1578 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR32:$src)),
1581 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1582 def : Pat<(f32 (sint_to_fp GR64:$src)),
1583 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR32:$src)),
1585 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1586 def : Pat<(f64 (sint_to_fp GR64:$src)),
1587 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1590 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1591 "cvttss2si\t{$src, $dst|$dst, $src}",
1592 SSE_CVT_SS2SI_32>, XS;
1593 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1594 "cvttss2si\t{$src, $dst|$dst, $src}",
1595 SSE_CVT_SS2SI_64>, XS, REX_W;
1596 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1597 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1600 "cvttsd2si\t{$src, $dst|$dst, $src}",
1601 SSE_CVT_SD2SI>, XD, REX_W;
1602 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1603 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1604 SSE_CVT_Scalar>, XS;
1605 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1606 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1607 SSE_CVT_Scalar>, XS, REX_W;
1608 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1609 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1610 SSE_CVT_Scalar>, XD;
1611 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1612 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1613 SSE_CVT_Scalar>, XD, REX_W;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1617 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1621 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1622 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1625 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1629 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1630 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1632 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1634 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1635 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1637 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1638 // and/or XMM operand(s).
1640 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1641 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1642 string asm, OpndItins itins> {
1643 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1644 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1645 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1646 Sched<[itins.Sched]>;
1647 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1648 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1649 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1650 Sched<[itins.Sched.Folded]>;
1653 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1654 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1655 PatFrag ld_frag, string asm, OpndItins itins,
1657 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1659 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1660 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1661 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1662 itins.rr>, Sched<[itins.Sched]>;
1663 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1664 (ins DstRC:$src1, x86memop:$src2),
1666 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1667 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1668 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1669 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1672 let Predicates = [UseAVX] in {
1673 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1674 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1675 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1676 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1677 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1678 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1680 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1682 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1683 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1686 let isCodeGenOnly = 1 in {
1687 let Predicates = [UseAVX] in {
1688 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1689 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1690 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1691 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1692 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1693 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1695 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1696 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1697 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1698 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1699 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1700 SSE_CVT_Scalar, 0>, XD,
1703 let Constraints = "$src1 = $dst" in {
1704 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1705 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1706 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1707 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1708 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1709 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1710 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1711 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1712 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1713 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1714 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1715 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1717 } // isCodeGenOnly = 1
1721 // Aliases for intrinsics
1722 let isCodeGenOnly = 1 in {
1723 let Predicates = [UseAVX] in {
1724 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1725 ssmem, sse_load_f32, "cvttss2si",
1726 SSE_CVT_SS2SI_32>, XS, VEX;
1727 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1728 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1729 "cvttss2si", SSE_CVT_SS2SI_64>,
1731 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1732 sdmem, sse_load_f64, "cvttsd2si",
1733 SSE_CVT_SD2SI>, XD, VEX;
1734 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1735 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1736 "cvttsd2si", SSE_CVT_SD2SI>,
1739 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1740 ssmem, sse_load_f32, "cvttss2si",
1741 SSE_CVT_SS2SI_32>, XS;
1742 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1743 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1744 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1745 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1746 sdmem, sse_load_f64, "cvttsd2si",
1748 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1749 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1750 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1751 } // isCodeGenOnly = 1
1753 let Predicates = [UseAVX] in {
1754 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1755 ssmem, sse_load_f32, "cvtss2si",
1756 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1757 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1758 ssmem, sse_load_f32, "cvtss2si",
1759 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1761 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1762 ssmem, sse_load_f32, "cvtss2si",
1763 SSE_CVT_SS2SI_32>, XS;
1764 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1765 ssmem, sse_load_f32, "cvtss2si",
1766 SSE_CVT_SS2SI_64>, XS, REX_W;
1768 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1769 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1770 SSEPackedSingle, SSE_CVT_PS>,
1771 PS, VEX, Requires<[HasAVX]>;
1772 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1773 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1774 SSEPackedSingle, SSE_CVT_PS>,
1775 PS, VEX, VEX_L, Requires<[HasAVX]>;
1777 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1778 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1779 SSEPackedSingle, SSE_CVT_PS>,
1780 PS, Requires<[UseSSE2]>;
1782 let Predicates = [UseAVX] in {
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1785 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1789 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1790 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1793 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1797 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1798 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1803 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1807 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1808 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1811 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1815 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1816 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1820 // Convert scalar double to scalar single
1821 let hasSideEffects = 0, Predicates = [UseAVX] in {
1822 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1823 (ins FR64:$src1, FR64:$src2),
1824 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1825 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1826 Sched<[WriteCvtF2F]>;
1828 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1829 (ins FR64:$src1, f64mem:$src2),
1830 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1831 [], IIC_SSE_CVT_Scalar_RM>,
1832 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1833 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1836 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1839 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1840 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1841 [(set FR32:$dst, (fround FR64:$src))],
1842 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1843 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1844 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1845 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1846 IIC_SSE_CVT_Scalar_RM>,
1848 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1850 let isCodeGenOnly = 1 in {
1851 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1852 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1853 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1855 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1856 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1857 Sched<[WriteCvtF2F]>;
1858 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1859 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1860 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1861 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1862 VR128:$src1, sse_load_f64:$src2))],
1863 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1864 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1866 let Constraints = "$src1 = $dst" in {
1867 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1868 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1869 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1871 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1872 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1873 Sched<[WriteCvtF2F]>;
1874 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1875 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1876 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1877 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1878 VR128:$src1, sse_load_f64:$src2))],
1879 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1880 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1882 } // isCodeGenOnly = 1
1884 // Convert scalar single to scalar double
1885 // SSE2 instructions with XS prefix
1886 let hasSideEffects = 0, Predicates = [UseAVX] in {
1887 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1888 (ins FR32:$src1, FR32:$src2),
1889 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1890 [], IIC_SSE_CVT_Scalar_RR>,
1891 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1892 Sched<[WriteCvtF2F]>;
1894 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1895 (ins FR32:$src1, f32mem:$src2),
1896 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1897 [], IIC_SSE_CVT_Scalar_RM>,
1898 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1899 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1902 def : Pat<(f64 (fextend FR32:$src)),
1903 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1904 def : Pat<(fextend (loadf32 addr:$src)),
1905 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1907 def : Pat<(extloadf32 addr:$src),
1908 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1909 Requires<[UseAVX, OptForSize]>;
1910 def : Pat<(extloadf32 addr:$src),
1911 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1912 Requires<[UseAVX, OptForSpeed]>;
1914 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1915 "cvtss2sd\t{$src, $dst|$dst, $src}",
1916 [(set FR64:$dst, (fextend FR32:$src))],
1917 IIC_SSE_CVT_Scalar_RR>, XS,
1918 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1919 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1920 "cvtss2sd\t{$src, $dst|$dst, $src}",
1921 [(set FR64:$dst, (extloadf32 addr:$src))],
1922 IIC_SSE_CVT_Scalar_RM>, XS,
1923 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1925 // extload f32 -> f64. This matches load+fextend because we have a hack in
1926 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1928 // Since these loads aren't folded into the fextend, we have to match it
1930 def : Pat<(fextend (loadf32 addr:$src)),
1931 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1932 def : Pat<(extloadf32 addr:$src),
1933 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1935 let isCodeGenOnly = 1 in {
1936 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1937 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1938 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1940 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1941 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1942 Sched<[WriteCvtF2F]>;
1943 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1944 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1945 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1947 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1948 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1949 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1950 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1951 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1952 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1953 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1955 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1956 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1957 Sched<[WriteCvtF2F]>;
1958 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1959 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1960 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1962 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1963 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1964 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1966 } // isCodeGenOnly = 1
1968 // Convert packed single/double fp to doubleword
1969 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1970 "cvtps2dq\t{$src, $dst|$dst, $src}",
1971 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1972 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1973 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1974 "cvtps2dq\t{$src, $dst|$dst, $src}",
1976 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1977 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1978 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1979 "cvtps2dq\t{$src, $dst|$dst, $src}",
1981 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1982 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1983 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1984 "cvtps2dq\t{$src, $dst|$dst, $src}",
1986 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1987 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1988 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1989 "cvtps2dq\t{$src, $dst|$dst, $src}",
1990 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1991 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1992 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1993 "cvtps2dq\t{$src, $dst|$dst, $src}",
1995 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1996 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1999 // Convert Packed Double FP to Packed DW Integers
2000 let Predicates = [HasAVX] in {
2001 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2002 // register, but the same isn't true when using memory operands instead.
2003 // Provide other assembly rr and rm forms to address this explicitly.
2004 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2005 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2006 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2007 VEX, Sched<[WriteCvtF2I]>;
2010 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2011 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2012 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2013 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2015 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2016 Sched<[WriteCvtF2ILd]>;
2019 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2020 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2022 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2023 Sched<[WriteCvtF2I]>;
2024 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2025 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2027 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2028 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2029 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2030 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2033 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2034 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2036 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2037 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2038 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2039 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2040 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2041 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2043 // Convert with truncation packed single/double fp to doubleword
2044 // SSE2 packed instructions with XS prefix
2045 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2046 "cvttps2dq\t{$src, $dst|$dst, $src}",
2048 (int_x86_sse2_cvttps2dq VR128:$src))],
2049 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2050 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2051 "cvttps2dq\t{$src, $dst|$dst, $src}",
2052 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2053 (loadv4f32 addr:$src)))],
2054 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2055 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2056 "cvttps2dq\t{$src, $dst|$dst, $src}",
2058 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2059 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2060 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2061 "cvttps2dq\t{$src, $dst|$dst, $src}",
2062 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2063 (loadv8f32 addr:$src)))],
2064 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2065 Sched<[WriteCvtF2ILd]>;
2067 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2068 "cvttps2dq\t{$src, $dst|$dst, $src}",
2069 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2070 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2071 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2072 "cvttps2dq\t{$src, $dst|$dst, $src}",
2074 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2075 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2077 let Predicates = [HasAVX] in {
2078 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2079 (VCVTDQ2PSrr VR128:$src)>;
2080 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2081 (VCVTDQ2PSrm addr:$src)>;
2083 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2084 (VCVTDQ2PSrr VR128:$src)>;
2085 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2086 (VCVTDQ2PSrm addr:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2089 (VCVTTPS2DQrr VR128:$src)>;
2090 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2091 (VCVTTPS2DQrm addr:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2094 (VCVTDQ2PSYrr VR256:$src)>;
2095 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2096 (VCVTDQ2PSYrm addr:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2099 (VCVTTPS2DQYrr VR256:$src)>;
2100 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2101 (VCVTTPS2DQYrm addr:$src)>;
2104 let Predicates = [UseSSE2] in {
2105 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2106 (CVTDQ2PSrr VR128:$src)>;
2107 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2108 (CVTDQ2PSrm addr:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2111 (CVTDQ2PSrr VR128:$src)>;
2112 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2113 (CVTDQ2PSrm addr:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2116 (CVTTPS2DQrr VR128:$src)>;
2117 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2118 (CVTTPS2DQrm addr:$src)>;
2121 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2122 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2124 (int_x86_sse2_cvttpd2dq VR128:$src))],
2125 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2127 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2128 // register, but the same isn't true when using memory operands instead.
2129 // Provide other assembly rr and rm forms to address this explicitly.
2132 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2133 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2134 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2135 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2136 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2137 (loadv2f64 addr:$src)))],
2138 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2141 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2142 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2145 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2146 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2147 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2149 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2150 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2151 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2152 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2154 let Predicates = [HasAVX] in {
2155 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2156 (VCVTTPD2DQYrr VR256:$src)>;
2157 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2158 (VCVTTPD2DQYrm addr:$src)>;
2159 } // Predicates = [HasAVX]
2161 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2162 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2163 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2164 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2165 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2166 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2167 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2168 (memopv2f64 addr:$src)))],
2170 Sched<[WriteCvtF2ILd]>;
2172 // Convert packed single to packed double
2173 let Predicates = [HasAVX] in {
2174 // SSE2 instructions without OpSize prefix
2175 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2179 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2180 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2181 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2182 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2183 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2184 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2186 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2187 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2188 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2189 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2192 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2195 let Predicates = [UseSSE2] in {
2196 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2197 "cvtps2pd\t{$src, $dst|$dst, $src}",
2198 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2199 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2200 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2201 "cvtps2pd\t{$src, $dst|$dst, $src}",
2202 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2203 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2206 // Convert Packed DW Integers to Packed Double FP
2207 let Predicates = [HasAVX] in {
2208 let hasSideEffects = 0, mayLoad = 1 in
2209 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2210 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2211 []>, VEX, Sched<[WriteCvtI2FLd]>;
2212 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2213 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2215 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2216 Sched<[WriteCvtI2F]>;
2217 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2218 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2220 (int_x86_avx_cvtdq2_pd_256
2221 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2222 Sched<[WriteCvtI2FLd]>;
2223 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2224 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2227 Sched<[WriteCvtI2F]>;
2230 let hasSideEffects = 0, mayLoad = 1 in
2231 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2232 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2233 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2234 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2235 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2236 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2237 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2239 // AVX 256-bit register conversion intrinsics
2240 let Predicates = [HasAVX] in {
2241 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2242 (VCVTDQ2PDYrr VR128:$src)>;
2243 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2244 (VCVTDQ2PDYrm addr:$src)>;
2245 } // Predicates = [HasAVX]
2247 // Convert packed double to packed single
2248 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2249 // register, but the same isn't true when using memory operands instead.
2250 // Provide other assembly rr and rm forms to address this explicitly.
2251 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2252 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2253 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2254 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2257 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2258 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2259 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2260 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2262 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2263 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2266 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2267 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2269 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2270 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2271 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2272 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2274 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2275 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2276 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2277 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2279 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2280 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2281 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2282 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2283 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2284 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2286 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2287 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2290 // AVX 256-bit register conversion intrinsics
2291 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2292 // whenever possible to avoid declaring two versions of each one.
2293 let Predicates = [HasAVX] in {
2294 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2295 (VCVTDQ2PSYrr VR256:$src)>;
2296 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2297 (VCVTDQ2PSYrm addr:$src)>;
2299 // Match fround and fextend for 128/256-bit conversions
2300 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2301 (VCVTPD2PSrr VR128:$src)>;
2302 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2303 (VCVTPD2PSXrm addr:$src)>;
2304 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2305 (VCVTPD2PSYrr VR256:$src)>;
2306 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2307 (VCVTPD2PSYrm addr:$src)>;
2309 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2310 (VCVTPS2PDrr VR128:$src)>;
2311 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2312 (VCVTPS2PDYrr VR128:$src)>;
2313 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2314 (VCVTPS2PDYrm addr:$src)>;
2317 let Predicates = [UseSSE2] in {
2318 // Match fround and fextend for 128 conversions
2319 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2320 (CVTPD2PSrr VR128:$src)>;
2321 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2322 (CVTPD2PSrm addr:$src)>;
2324 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2325 (CVTPS2PDrr VR128:$src)>;
2328 //===----------------------------------------------------------------------===//
2329 // SSE 1 & 2 - Compare Instructions
2330 //===----------------------------------------------------------------------===//
2332 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2333 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2334 Operand CC, SDNode OpNode, ValueType VT,
2335 PatFrag ld_frag, string asm, string asm_alt,
2337 def rr : SIi8<0xC2, MRMSrcReg,
2338 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2339 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2340 itins.rr>, Sched<[itins.Sched]>;
2341 def rm : SIi8<0xC2, MRMSrcMem,
2342 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2343 [(set RC:$dst, (OpNode (VT RC:$src1),
2344 (ld_frag addr:$src2), imm:$cc))],
2346 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2348 // Accept explicit immediate argument form instead of comparison code.
2349 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2350 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2351 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2352 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2354 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2355 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2356 IIC_SSE_ALU_F32S_RM>,
2357 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2361 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2362 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2363 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2365 XS, VEX_4V, VEX_LIG;
2366 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2367 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2368 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2369 SSE_ALU_F32S>, // same latency as 32 bit compare
2370 XD, VEX_4V, VEX_LIG;
2372 let Constraints = "$src1 = $dst" in {
2373 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2374 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2375 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2377 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2378 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2379 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2384 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2385 Intrinsic Int, string asm, OpndItins itins> {
2386 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2387 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2388 [(set VR128:$dst, (Int VR128:$src1,
2389 VR128:$src, imm:$cc))],
2391 Sched<[itins.Sched]>;
2392 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2393 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2394 [(set VR128:$dst, (Int VR128:$src1,
2395 (load addr:$src), imm:$cc))],
2397 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2400 let isCodeGenOnly = 1 in {
2401 // Aliases to match intrinsics which expect XMM operand(s).
2402 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2403 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2406 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2407 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2408 SSE_ALU_F32S>, // same latency as f32
2410 let Constraints = "$src1 = $dst" in {
2411 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2412 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2414 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2415 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2422 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2423 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2424 ValueType vt, X86MemOperand x86memop,
2425 PatFrag ld_frag, string OpcodeStr> {
2426 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2427 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2428 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2431 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2432 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2433 [(set EFLAGS, (OpNode (vt RC:$src1),
2434 (ld_frag addr:$src2)))],
2436 Sched<[WriteFAddLd, ReadAfterLd]>;
2439 let Defs = [EFLAGS] in {
2440 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2441 "ucomiss">, PS, VEX, VEX_LIG;
2442 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2443 "ucomisd">, PD, VEX, VEX_LIG;
2444 let Pattern = []<dag> in {
2445 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2446 "comiss">, PS, VEX, VEX_LIG;
2447 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2448 "comisd">, PD, VEX, VEX_LIG;
2451 let isCodeGenOnly = 1 in {
2452 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2453 load, "ucomiss">, PS, VEX;
2454 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2455 load, "ucomisd">, PD, VEX;
2457 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2458 load, "comiss">, PS, VEX;
2459 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2460 load, "comisd">, PD, VEX;
2462 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2464 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2467 let Pattern = []<dag> in {
2468 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2470 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2474 let isCodeGenOnly = 1 in {
2475 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2476 load, "ucomiss">, PS;
2477 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2478 load, "ucomisd">, PD;
2480 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2482 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2485 } // Defs = [EFLAGS]
2487 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2488 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2489 Operand CC, Intrinsic Int, string asm,
2490 string asm_alt, Domain d,
2491 OpndItins itins = SSE_ALU_F32P> {
2492 def rri : PIi8<0xC2, MRMSrcReg,
2493 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2494 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2497 def rmi : PIi8<0xC2, MRMSrcMem,
2498 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2499 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2501 Sched<[WriteFAddLd, ReadAfterLd]>;
2503 // Accept explicit immediate argument form instead of comparison code.
2504 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2505 def rri_alt : PIi8<0xC2, MRMSrcReg,
2506 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2507 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2508 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2509 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2510 asm_alt, [], itins.rm, d>,
2511 Sched<[WriteFAddLd, ReadAfterLd]>;
2515 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2516 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2517 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2518 SSEPackedSingle>, PS, VEX_4V;
2519 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2520 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2521 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2522 SSEPackedDouble>, PD, VEX_4V;
2523 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2524 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2525 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2526 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2527 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2528 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2529 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2530 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2531 let Constraints = "$src1 = $dst" in {
2532 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2533 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2534 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2535 SSEPackedSingle, SSE_ALU_F32P>, PS;
2536 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2537 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2538 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2539 SSEPackedDouble, SSE_ALU_F64P>, PD;
2542 let Predicates = [HasAVX] in {
2543 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2544 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2545 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2546 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2547 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2548 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2549 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2550 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2552 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2553 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2554 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2555 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2556 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2557 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2558 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2559 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2562 let Predicates = [UseSSE1] in {
2563 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2564 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2565 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2566 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2569 let Predicates = [UseSSE2] in {
2570 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2571 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2572 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2573 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2576 //===----------------------------------------------------------------------===//
2577 // SSE 1 & 2 - Shuffle Instructions
2578 //===----------------------------------------------------------------------===//
2580 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2581 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2582 ValueType vt, string asm, PatFrag mem_frag,
2584 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2585 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2586 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2587 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2588 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2589 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2590 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2591 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2592 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2593 Sched<[WriteFShuffle]>;
2596 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2597 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2598 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2599 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2600 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2601 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2602 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2603 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2604 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2605 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2606 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2607 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2609 let Constraints = "$src1 = $dst" in {
2610 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2611 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2612 memopv4f32, SSEPackedSingle>, PS;
2613 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2614 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2615 memopv2f64, SSEPackedDouble>, PD;
2618 let Predicates = [HasAVX] in {
2619 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2620 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2621 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2622 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2623 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2625 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2626 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2627 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2628 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2629 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2632 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2633 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2634 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2635 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2636 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2638 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2639 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2640 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2641 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2642 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2645 let Predicates = [UseSSE1] in {
2646 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2647 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2648 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2649 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2650 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2653 let Predicates = [UseSSE2] in {
2654 // Generic SHUFPD patterns
2655 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2656 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2657 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2658 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2659 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2662 //===----------------------------------------------------------------------===//
2663 // SSE 1 & 2 - Unpack FP Instructions
2664 //===----------------------------------------------------------------------===//
2666 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2667 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2668 PatFrag mem_frag, RegisterClass RC,
2669 X86MemOperand x86memop, string asm,
2671 def rr : PI<opc, MRMSrcReg,
2672 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2674 (vt (OpNode RC:$src1, RC:$src2)))],
2675 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2676 def rm : PI<opc, MRMSrcMem,
2677 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2679 (vt (OpNode RC:$src1,
2680 (mem_frag addr:$src2))))],
2682 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2685 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2686 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2687 SSEPackedSingle>, PS, VEX_4V;
2688 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2689 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2690 SSEPackedDouble>, PD, VEX_4V;
2691 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2692 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2693 SSEPackedSingle>, PS, VEX_4V;
2694 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2695 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2696 SSEPackedDouble>, PD, VEX_4V;
2698 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2699 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2700 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2701 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2702 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2704 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2705 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2706 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2707 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2708 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2709 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2711 let Constraints = "$src1 = $dst" in {
2712 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2713 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2714 SSEPackedSingle>, PS;
2715 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2716 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2717 SSEPackedDouble>, PD;
2718 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2719 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2720 SSEPackedSingle>, PS;
2721 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2722 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2723 SSEPackedDouble>, PD;
2724 } // Constraints = "$src1 = $dst"
2726 let Predicates = [HasAVX1Only] in {
2727 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2728 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2729 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2730 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2731 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2732 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2733 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2734 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2736 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2737 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2738 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2739 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2740 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2741 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2742 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2743 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2746 let Predicates = [HasAVX] in {
2747 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2748 // problem is during lowering, where it's not possible to recognize the load
2749 // fold cause it has two uses through a bitcast. One use disappears at isel
2750 // time and the fold opportunity reappears.
2751 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2752 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2755 let Predicates = [UseSSE2] in {
2756 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2757 // problem is during lowering, where it's not possible to recognize the load
2758 // fold cause it has two uses through a bitcast. One use disappears at isel
2759 // time and the fold opportunity reappears.
2760 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2761 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2764 //===----------------------------------------------------------------------===//
2765 // SSE 1 & 2 - Extract Floating-Point Sign mask
2766 //===----------------------------------------------------------------------===//
2768 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2769 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2771 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2772 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2773 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2774 Sched<[WriteVecLogic]>;
2777 let Predicates = [HasAVX] in {
2778 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2779 "movmskps", SSEPackedSingle>, PS, VEX;
2780 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2781 "movmskpd", SSEPackedDouble>, PD, VEX;
2782 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2783 "movmskps", SSEPackedSingle>, PS,
2785 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2786 "movmskpd", SSEPackedDouble>, PD,
2789 def : Pat<(i32 (X86fgetsign FR32:$src)),
2790 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2791 def : Pat<(i64 (X86fgetsign FR32:$src)),
2792 (SUBREG_TO_REG (i64 0),
2793 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2794 def : Pat<(i32 (X86fgetsign FR64:$src)),
2795 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2796 def : Pat<(i64 (X86fgetsign FR64:$src)),
2797 (SUBREG_TO_REG (i64 0),
2798 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2801 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2802 SSEPackedSingle>, PS;
2803 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2804 SSEPackedDouble>, PD;
2806 def : Pat<(i32 (X86fgetsign FR32:$src)),
2807 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2808 Requires<[UseSSE1]>;
2809 def : Pat<(i64 (X86fgetsign FR32:$src)),
2810 (SUBREG_TO_REG (i64 0),
2811 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2812 Requires<[UseSSE1]>;
2813 def : Pat<(i32 (X86fgetsign FR64:$src)),
2814 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2815 Requires<[UseSSE2]>;
2816 def : Pat<(i64 (X86fgetsign FR64:$src)),
2817 (SUBREG_TO_REG (i64 0),
2818 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2819 Requires<[UseSSE2]>;
2821 //===---------------------------------------------------------------------===//
2822 // SSE2 - Packed Integer Logical Instructions
2823 //===---------------------------------------------------------------------===//
2825 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2827 /// PDI_binop_rm - Simple SSE2 binary operator.
2828 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2829 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2830 X86MemOperand x86memop, OpndItins itins,
2831 bit IsCommutable, bit Is2Addr> {
2832 let isCommutable = IsCommutable in
2833 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2834 (ins RC:$src1, RC:$src2),
2836 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2837 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2838 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2839 Sched<[itins.Sched]>;
2840 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2841 (ins RC:$src1, x86memop:$src2),
2843 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2844 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2845 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2846 (bitconvert (memop_frag addr:$src2)))))],
2848 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2850 } // ExeDomain = SSEPackedInt
2852 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2853 ValueType OpVT128, ValueType OpVT256,
2854 OpndItins itins, bit IsCommutable = 0> {
2855 let Predicates = [HasAVX, NoVLX] in
2856 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2857 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2859 let Constraints = "$src1 = $dst" in
2860 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2861 memopv2i64, i128mem, itins, IsCommutable, 1>;
2863 let Predicates = [HasAVX2, NoVLX] in
2864 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2865 OpVT256, VR256, loadv4i64, i256mem, itins,
2866 IsCommutable, 0>, VEX_4V, VEX_L;
2869 // These are ordered here for pattern ordering requirements with the fp versions
2871 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2872 SSE_VEC_BIT_ITINS_P, 1>;
2873 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2874 SSE_VEC_BIT_ITINS_P, 1>;
2875 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2876 SSE_VEC_BIT_ITINS_P, 1>;
2877 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2878 SSE_VEC_BIT_ITINS_P, 0>;
2880 //===----------------------------------------------------------------------===//
2881 // SSE 1 & 2 - Logical Instructions
2882 //===----------------------------------------------------------------------===//
2884 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2886 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2887 SDNode OpNode, OpndItins itins> {
2888 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2889 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2892 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2893 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2896 let Constraints = "$src1 = $dst" in {
2897 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2898 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2901 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2902 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2907 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2908 let isCodeGenOnly = 1 in {
2909 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2911 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2913 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2916 let isCommutable = 0 in
2917 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2921 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2923 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2925 let Predicates = [HasAVX, NoVLX] in {
2926 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2927 !strconcat(OpcodeStr, "ps"), f256mem,
2928 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2929 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2930 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2932 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2933 !strconcat(OpcodeStr, "pd"), f256mem,
2934 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2935 (bc_v4i64 (v4f64 VR256:$src2))))],
2936 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2937 (loadv4i64 addr:$src2)))], 0>,
2940 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2941 // are all promoted to v2i64, and the patterns are covered by the int
2942 // version. This is needed in SSE only, because v2i64 isn't supported on
2943 // SSE1, but only on SSE2.
2944 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2945 !strconcat(OpcodeStr, "ps"), f128mem, [],
2946 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2947 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2949 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2950 !strconcat(OpcodeStr, "pd"), f128mem,
2951 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2952 (bc_v2i64 (v2f64 VR128:$src2))))],
2953 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2954 (loadv2i64 addr:$src2)))], 0>,
2958 let Constraints = "$src1 = $dst" in {
2959 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2960 !strconcat(OpcodeStr, "ps"), f128mem,
2961 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2962 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2963 (memopv2i64 addr:$src2)))]>, PS;
2965 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2966 !strconcat(OpcodeStr, "pd"), f128mem,
2967 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2968 (bc_v2i64 (v2f64 VR128:$src2))))],
2969 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2970 (memopv2i64 addr:$src2)))]>, PD;
2974 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2975 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2976 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2977 let isCommutable = 0 in
2978 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2980 // AVX1 requires type coercions in order to fold loads directly into logical
2982 let Predicates = [HasAVX1Only] in {
2983 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
2984 (VANDPSYrm VR256:$src1, addr:$src2)>;
2985 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
2986 (VORPSYrm VR256:$src1, addr:$src2)>;
2987 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
2988 (VXORPSYrm VR256:$src1, addr:$src2)>;
2989 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
2990 (VANDNPSYrm VR256:$src1, addr:$src2)>;
2993 //===----------------------------------------------------------------------===//
2994 // SSE 1 & 2 - Arithmetic Instructions
2995 //===----------------------------------------------------------------------===//
2997 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3000 /// In addition, we also have a special variant of the scalar form here to
3001 /// represent the associated intrinsic operation. This form is unlike the
3002 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3003 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3005 /// These three forms can each be reg+reg or reg+mem.
3008 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3010 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3011 SDNode OpNode, SizeItins itins> {
3012 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3013 VR128, v4f32, f128mem, loadv4f32,
3014 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3015 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3016 VR128, v2f64, f128mem, loadv2f64,
3017 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3019 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3020 OpNode, VR256, v8f32, f256mem, loadv8f32,
3021 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3022 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3023 OpNode, VR256, v4f64, f256mem, loadv4f64,
3024 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3026 let Constraints = "$src1 = $dst" in {
3027 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3028 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3030 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3031 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3036 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3038 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3039 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3040 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3041 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3043 let Constraints = "$src1 = $dst" in {
3044 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3045 OpNode, FR32, f32mem, itins.s>, XS;
3046 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3047 OpNode, FR64, f64mem, itins.d>, XD;
3051 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3053 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3054 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3055 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3056 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3057 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3058 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3060 let Constraints = "$src1 = $dst" in {
3061 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3062 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3064 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3065 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3070 // Binary Arithmetic instructions
3071 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3072 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3073 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3074 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3075 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3076 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3077 let isCommutable = 0 in {
3078 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3079 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3080 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3081 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3082 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3083 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3084 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3085 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3086 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3087 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3088 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3089 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3092 let isCodeGenOnly = 1 in {
3093 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3094 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3095 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3096 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3099 // Patterns used to select SSE scalar fp arithmetic instructions from
3100 // a scalar fp operation followed by a blend.
3102 // These patterns know, for example, how to select an ADDSS from a
3103 // float add plus vector insert.
3105 // The effect is that the backend no longer emits unnecessary vector
3106 // insert instructions immediately after SSE scalar fp instructions
3107 // like addss or mulss.
3109 // For example, given the following code:
3110 // __m128 foo(__m128 A, __m128 B) {
3115 // previously we generated:
3116 // addss %xmm0, %xmm1
3117 // movss %xmm1, %xmm0
3120 // addss %xmm1, %xmm0
3122 let Predicates = [UseSSE1] in {
3123 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3124 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3126 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3127 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3128 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3130 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3131 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3132 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3134 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3135 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3136 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3138 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3141 let Predicates = [UseSSE2] in {
3142 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3143 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3144 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3146 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3147 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3148 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3150 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3151 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3152 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3154 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3155 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3156 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3158 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3161 let Predicates = [UseSSE41] in {
3162 // If the subtarget has SSE4.1 but not AVX, the vector insert instruction is
3163 // lowered into a X86insertps or a X86Blendi rather than a X86Movss. When
3164 // selecting SSE scalar single-precision fp arithmetic instructions, make
3165 // sure that we correctly match them.
3167 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3168 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3169 FR32:$src))), (iPTR 0))),
3170 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3171 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3172 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3173 FR32:$src))), (iPTR 0))),
3174 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3175 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3176 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3177 FR32:$src))), (iPTR 0))),
3178 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3179 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3180 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3181 FR32:$src))), (iPTR 0))),
3182 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3184 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3185 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3186 FR32:$src))), (i8 1))),
3187 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3188 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3189 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3190 FR32:$src))), (i8 1))),
3191 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3192 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3193 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3194 FR32:$src))), (i8 1))),
3195 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3196 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3197 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3198 FR32:$src))), (i8 1))),
3199 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3201 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3202 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3203 FR64:$src))), (i8 1))),
3204 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3205 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3206 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3207 FR64:$src))), (i8 1))),
3208 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3209 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3210 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3211 FR64:$src))), (i8 1))),
3212 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3213 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3214 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3215 FR64:$src))), (i8 1))),
3216 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3218 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3219 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3220 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3221 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3222 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3223 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3224 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3225 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3226 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3227 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3228 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3229 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3230 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3231 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3232 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3233 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3236 let Predicates = [HasAVX] in {
3237 // The following patterns select AVX Scalar single/double precision fp
3238 // arithmetic instructions.
3240 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3241 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3243 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3244 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3245 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3247 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3248 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3249 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3251 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3252 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3253 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3255 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3256 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3257 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3258 FR32:$src))), (iPTR 0))),
3259 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3260 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3261 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3262 FR32:$src))), (iPTR 0))),
3263 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3264 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3265 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3266 FR32:$src))), (iPTR 0))),
3267 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3268 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3269 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3270 FR32:$src))), (iPTR 0))),
3271 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3273 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3274 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3275 FR32:$src))), (i8 1))),
3276 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3277 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3278 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3279 FR32:$src))), (i8 1))),
3280 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3281 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3282 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3283 FR32:$src))), (i8 1))),
3284 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3285 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3286 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3287 FR32:$src))), (i8 1))),
3288 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3290 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3291 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3292 FR64:$src))), (i8 1))),
3293 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3294 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3295 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3296 FR64:$src))), (i8 1))),
3297 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3298 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3299 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3300 FR64:$src))), (i8 1))),
3301 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3302 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3303 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3304 FR64:$src))), (i8 1))),
3305 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3307 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fadd
3308 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3309 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3310 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3311 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fsub
3312 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3313 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3314 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3315 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fmul
3316 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3317 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3318 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3319 def : Pat<(v2f64 (X86Blendi (v2f64 (scalar_to_vector (fdiv
3320 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3321 FR64:$src))), (v2f64 VR128:$dst), (i8 2))),
3322 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3325 // Patterns used to select SSE scalar fp arithmetic instructions from
3326 // a vector packed single/double fp operation followed by a vector insert.
3328 // The effect is that the backend converts the packed fp instruction
3329 // followed by a vector insert into a single SSE scalar fp instruction.
3331 // For example, given the following code:
3332 // __m128 foo(__m128 A, __m128 B) {
3333 // __m128 C = A + B;
3334 // return (__m128) {c[0], a[1], a[2], a[3]};
3337 // previously we generated:
3338 // addps %xmm0, %xmm1
3339 // movss %xmm1, %xmm0
3342 // addss %xmm1, %xmm0
3344 let Predicates = [UseSSE1] in {
3345 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3346 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3347 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3348 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3349 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3350 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3351 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3352 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3353 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3354 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3355 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3356 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3359 let Predicates = [UseSSE2] in {
3360 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3361 // from a packed double-precision fp instruction plus movsd.
3363 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3364 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3365 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3366 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3367 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3368 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3369 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3370 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3371 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3372 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3373 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3374 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3377 let Predicates = [UseSSE41] in {
3378 // With SSE4.1 we may see these operations using X86Blendi rather than
3380 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3381 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3382 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3383 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3384 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3385 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3386 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3387 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3388 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3389 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3390 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3391 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3393 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3394 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3395 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3396 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3397 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3398 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3399 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3400 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3401 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3402 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3403 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3404 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3406 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3407 (v2f64 VR128:$dst), (i8 2))),
3408 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3409 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3410 (v2f64 VR128:$dst), (i8 2))),
3411 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3412 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3413 (v2f64 VR128:$dst), (i8 2))),
3414 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3415 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3416 (v2f64 VR128:$dst), (i8 2))),
3417 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3420 let Predicates = [HasAVX] in {
3421 // The following patterns select AVX Scalar single/double precision fp
3422 // arithmetic instructions from a packed single precision fp instruction
3423 // plus movss/movsd.
3425 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3426 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3427 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3428 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3429 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3430 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3431 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3432 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3433 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3434 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3435 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3436 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3437 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3438 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3439 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3440 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3441 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3442 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3443 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3444 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3445 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3446 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3447 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3448 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3450 // Also handle X86Blendi-based patterns.
3451 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3452 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3453 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3454 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3455 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3456 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3457 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3458 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3459 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3460 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3461 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3462 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3464 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3465 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3466 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3467 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3468 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3469 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3470 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3471 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3472 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3473 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3474 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3475 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3477 def : Pat<(v2f64 (X86Blendi (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3478 (v2f64 VR128:$dst), (i8 2))),
3479 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3480 def : Pat<(v2f64 (X86Blendi (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3481 (v2f64 VR128:$dst), (i8 2))),
3482 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3483 def : Pat<(v2f64 (X86Blendi (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3484 (v2f64 VR128:$dst), (i8 2))),
3485 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3486 def : Pat<(v2f64 (X86Blendi (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)),
3487 (v2f64 VR128:$dst), (i8 2))),
3488 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3492 /// In addition, we also have a special variant of the scalar form here to
3493 /// represent the associated intrinsic operation. This form is unlike the
3494 /// plain scalar form, in that it takes an entire vector (instead of a
3495 /// scalar) and leaves the top elements undefined.
3497 /// And, we have a special variant form for a full-vector intrinsic form.
3499 let Sched = WriteFSqrt in {
3500 def SSE_SQRTPS : OpndItins<
3501 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3504 def SSE_SQRTSS : OpndItins<
3505 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3508 def SSE_SQRTPD : OpndItins<
3509 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3512 def SSE_SQRTSD : OpndItins<
3513 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3517 let Sched = WriteFRsqrt in {
3518 def SSE_RSQRTPS : OpndItins<
3519 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3522 def SSE_RSQRTSS : OpndItins<
3523 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3527 let Sched = WriteFRcp in {
3528 def SSE_RCPP : OpndItins<
3529 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3532 def SSE_RCPS : OpndItins<
3533 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3537 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3538 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3539 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3540 let Predicates = [HasAVX], hasSideEffects = 0 in {
3541 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3542 (ins FR32:$src1, FR32:$src2),
3543 !strconcat("v", OpcodeStr,
3544 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3545 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3546 let mayLoad = 1 in {
3547 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3548 (ins FR32:$src1,f32mem:$src2),
3549 !strconcat("v", OpcodeStr,
3550 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3551 []>, VEX_4V, VEX_LIG,
3552 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3553 let isCodeGenOnly = 1 in
3554 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3555 (ins VR128:$src1, ssmem:$src2),
3556 !strconcat("v", OpcodeStr,
3557 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3558 []>, VEX_4V, VEX_LIG,
3559 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3563 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3564 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3565 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3566 // For scalar unary operations, fold a load into the operation
3567 // only in OptForSize mode. It eliminates an instruction, but it also
3568 // eliminates a whole-register clobber (the load), so it introduces a
3569 // partial register update condition.
3570 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3571 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3572 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3573 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3574 let isCodeGenOnly = 1 in {
3575 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3576 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3577 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3578 Sched<[itins.Sched]>;
3579 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3580 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3581 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3582 Sched<[itins.Sched.Folded]>;
3586 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3587 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3589 let Predicates = [HasAVX], hasSideEffects = 0 in {
3590 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3591 (ins FR32:$src1, FR32:$src2),
3592 !strconcat("v", OpcodeStr,
3593 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3594 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3595 let mayLoad = 1 in {
3596 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3597 (ins FR32:$src1,f32mem:$src2),
3598 !strconcat("v", OpcodeStr,
3599 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3600 []>, VEX_4V, VEX_LIG,
3601 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3602 let isCodeGenOnly = 1 in
3603 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3604 (ins VR128:$src1, ssmem:$src2),
3605 !strconcat("v", OpcodeStr,
3606 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3607 []>, VEX_4V, VEX_LIG,
3608 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3612 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3613 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3614 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3615 // For scalar unary operations, fold a load into the operation
3616 // only in OptForSize mode. It eliminates an instruction, but it also
3617 // eliminates a whole-register clobber (the load), so it introduces a
3618 // partial register update condition.
3619 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3620 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3621 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3622 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3623 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3624 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3625 (ins VR128:$src1, VR128:$src2),
3626 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3627 [], itins.rr>, Sched<[itins.Sched]>;
3628 let mayLoad = 1, hasSideEffects = 0 in
3629 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3630 (ins VR128:$src1, ssmem:$src2),
3631 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3632 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3636 /// sse1_fp_unop_p - SSE1 unops in packed form.
3637 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3639 let Predicates = [HasAVX] in {
3640 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3641 !strconcat("v", OpcodeStr,
3642 "ps\t{$src, $dst|$dst, $src}"),
3643 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3644 itins.rr>, VEX, Sched<[itins.Sched]>;
3645 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3646 !strconcat("v", OpcodeStr,
3647 "ps\t{$src, $dst|$dst, $src}"),
3648 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3649 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3650 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3651 !strconcat("v", OpcodeStr,
3652 "ps\t{$src, $dst|$dst, $src}"),
3653 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3654 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3655 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3656 !strconcat("v", OpcodeStr,
3657 "ps\t{$src, $dst|$dst, $src}"),
3658 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3659 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3662 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3663 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3664 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3665 Sched<[itins.Sched]>;
3666 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3667 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3668 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3669 Sched<[itins.Sched.Folded]>;
3672 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3673 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3674 Intrinsic V4F32Int, Intrinsic V8F32Int,
3676 let isCodeGenOnly = 1 in {
3677 let Predicates = [HasAVX] in {
3678 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3679 !strconcat("v", OpcodeStr,
3680 "ps\t{$src, $dst|$dst, $src}"),
3681 [(set VR128:$dst, (V4F32Int VR128:$src))],
3682 itins.rr>, VEX, Sched<[itins.Sched]>;
3683 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3684 !strconcat("v", OpcodeStr,
3685 "ps\t{$src, $dst|$dst, $src}"),
3686 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3687 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3688 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3689 !strconcat("v", OpcodeStr,
3690 "ps\t{$src, $dst|$dst, $src}"),
3691 [(set VR256:$dst, (V8F32Int VR256:$src))],
3692 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3693 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3695 !strconcat("v", OpcodeStr,
3696 "ps\t{$src, $dst|$dst, $src}"),
3697 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3698 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3701 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3702 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3703 [(set VR128:$dst, (V4F32Int VR128:$src))],
3704 itins.rr>, Sched<[itins.Sched]>;
3705 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3706 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3707 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3708 itins.rm>, Sched<[itins.Sched.Folded]>;
3709 } // isCodeGenOnly = 1
3712 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3713 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3714 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3715 let Predicates = [HasAVX], hasSideEffects = 0 in {
3716 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3717 (ins FR64:$src1, FR64:$src2),
3718 !strconcat("v", OpcodeStr,
3719 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3720 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3721 let mayLoad = 1 in {
3722 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3723 (ins FR64:$src1,f64mem:$src2),
3724 !strconcat("v", OpcodeStr,
3725 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3726 []>, VEX_4V, VEX_LIG,
3727 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3728 let isCodeGenOnly = 1 in
3729 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3730 (ins VR128:$src1, sdmem:$src2),
3731 !strconcat("v", OpcodeStr,
3732 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3733 []>, VEX_4V, VEX_LIG,
3734 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3738 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3739 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3740 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3741 Sched<[itins.Sched]>;
3742 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3743 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3744 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3745 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3746 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3747 let isCodeGenOnly = 1 in {
3748 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3749 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3750 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3751 Sched<[itins.Sched]>;
3752 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3753 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3754 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3755 Sched<[itins.Sched.Folded]>;
3759 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3760 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3761 SDNode OpNode, OpndItins itins> {
3762 let Predicates = [HasAVX] in {
3763 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3764 !strconcat("v", OpcodeStr,
3765 "pd\t{$src, $dst|$dst, $src}"),
3766 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3767 itins.rr>, VEX, Sched<[itins.Sched]>;
3768 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3769 !strconcat("v", OpcodeStr,
3770 "pd\t{$src, $dst|$dst, $src}"),
3771 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3772 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3773 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3774 !strconcat("v", OpcodeStr,
3775 "pd\t{$src, $dst|$dst, $src}"),
3776 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3777 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3778 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3779 !strconcat("v", OpcodeStr,
3780 "pd\t{$src, $dst|$dst, $src}"),
3781 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3782 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3785 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3786 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3787 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3788 Sched<[itins.Sched]>;
3789 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3790 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3791 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3792 Sched<[itins.Sched.Folded]>;
3796 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3798 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3799 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3801 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3803 // Reciprocal approximations. Note that these typically require refinement
3804 // in order to obtain suitable precision.
3805 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3806 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
3807 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3808 int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
3809 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3810 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3811 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3812 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3814 let Predicates = [UseAVX] in {
3815 def : Pat<(f32 (fsqrt FR32:$src)),
3816 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3817 def : Pat<(f32 (fsqrt (load addr:$src))),
3818 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3819 Requires<[HasAVX, OptForSize]>;
3820 def : Pat<(f64 (fsqrt FR64:$src)),
3821 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3822 def : Pat<(f64 (fsqrt (load addr:$src))),
3823 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3824 Requires<[HasAVX, OptForSize]>;
3826 def : Pat<(f32 (X86frsqrt FR32:$src)),
3827 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3828 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3829 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3830 Requires<[HasAVX, OptForSize]>;
3832 def : Pat<(f32 (X86frcp FR32:$src)),
3833 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3834 def : Pat<(f32 (X86frcp (load addr:$src))),
3835 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3836 Requires<[HasAVX, OptForSize]>;
3838 let Predicates = [UseAVX] in {
3839 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3840 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3841 (COPY_TO_REGCLASS VR128:$src, FR32)),
3843 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3844 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3846 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3847 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3848 (COPY_TO_REGCLASS VR128:$src, FR64)),
3850 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3851 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3854 let Predicates = [HasAVX] in {
3855 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3856 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3857 (COPY_TO_REGCLASS VR128:$src, FR32)),
3859 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3860 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3862 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3863 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3864 (COPY_TO_REGCLASS VR128:$src, FR32)),
3866 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3867 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3870 // Reciprocal approximations. Note that these typically require refinement
3871 // in order to obtain suitable precision.
3872 let Predicates = [UseSSE1] in {
3873 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3874 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3875 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3876 (RCPSSr_Int VR128:$src, VR128:$src)>;
3879 // There is no f64 version of the reciprocal approximation instructions.
3881 //===----------------------------------------------------------------------===//
3882 // SSE 1 & 2 - Non-temporal stores
3883 //===----------------------------------------------------------------------===//
3885 let AddedComplexity = 400 in { // Prefer non-temporal versions
3886 let SchedRW = [WriteStore] in {
3887 let Predicates = [HasAVX, NoVLX] in {
3888 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3889 (ins f128mem:$dst, VR128:$src),
3890 "movntps\t{$src, $dst|$dst, $src}",
3891 [(alignednontemporalstore (v4f32 VR128:$src),
3893 IIC_SSE_MOVNT>, VEX;
3894 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3895 (ins f128mem:$dst, VR128:$src),
3896 "movntpd\t{$src, $dst|$dst, $src}",
3897 [(alignednontemporalstore (v2f64 VR128:$src),
3899 IIC_SSE_MOVNT>, VEX;
3901 let ExeDomain = SSEPackedInt in
3902 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3903 (ins f128mem:$dst, VR128:$src),
3904 "movntdq\t{$src, $dst|$dst, $src}",
3905 [(alignednontemporalstore (v2i64 VR128:$src),
3907 IIC_SSE_MOVNT>, VEX;
3909 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3910 (ins f256mem:$dst, VR256:$src),
3911 "movntps\t{$src, $dst|$dst, $src}",
3912 [(alignednontemporalstore (v8f32 VR256:$src),
3914 IIC_SSE_MOVNT>, VEX, VEX_L;
3915 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3916 (ins f256mem:$dst, VR256:$src),
3917 "movntpd\t{$src, $dst|$dst, $src}",
3918 [(alignednontemporalstore (v4f64 VR256:$src),
3920 IIC_SSE_MOVNT>, VEX, VEX_L;
3921 let ExeDomain = SSEPackedInt in
3922 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3923 (ins f256mem:$dst, VR256:$src),
3924 "movntdq\t{$src, $dst|$dst, $src}",
3925 [(alignednontemporalstore (v4i64 VR256:$src),
3927 IIC_SSE_MOVNT>, VEX, VEX_L;
3930 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3931 "movntps\t{$src, $dst|$dst, $src}",
3932 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3934 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3935 "movntpd\t{$src, $dst|$dst, $src}",
3936 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3939 let ExeDomain = SSEPackedInt in
3940 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3941 "movntdq\t{$src, $dst|$dst, $src}",
3942 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3945 // There is no AVX form for instructions below this point
3946 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3947 "movnti{l}\t{$src, $dst|$dst, $src}",
3948 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3950 PS, Requires<[HasSSE2]>;
3951 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3952 "movnti{q}\t{$src, $dst|$dst, $src}",
3953 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3955 PS, Requires<[HasSSE2]>;
3956 } // SchedRW = [WriteStore]
3958 let Predicates = [HasAVX, NoVLX] in {
3959 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3960 (VMOVNTPSmr addr:$dst, VR128:$src)>;
3963 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3964 (MOVNTPSmr addr:$dst, VR128:$src)>;
3966 } // AddedComplexity
3968 //===----------------------------------------------------------------------===//
3969 // SSE 1 & 2 - Prefetch and memory fence
3970 //===----------------------------------------------------------------------===//
3972 // Prefetch intrinsic.
3973 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3974 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3975 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3976 IIC_SSE_PREFETCH>, TB;
3977 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3978 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3979 IIC_SSE_PREFETCH>, TB;
3980 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3981 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3982 IIC_SSE_PREFETCH>, TB;
3983 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3984 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3985 IIC_SSE_PREFETCH>, TB;
3988 // FIXME: How should flush instruction be modeled?
3989 let SchedRW = [WriteLoad] in {
3991 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3992 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3993 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3996 let SchedRW = [WriteNop] in {
3997 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3998 // was introduced with SSE2, it's backward compatible.
3999 def PAUSE : I<0x90, RawFrm, (outs), (ins),
4000 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
4001 OBXS, Requires<[HasSSE2]>;
4004 let SchedRW = [WriteFence] in {
4005 // Load, store, and memory fence
4006 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
4007 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
4008 TB, Requires<[HasSSE1]>;
4009 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
4010 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
4011 TB, Requires<[HasSSE2]>;
4012 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
4013 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
4014 TB, Requires<[HasSSE2]>;
4017 def : Pat<(X86SFence), (SFENCE)>;
4018 def : Pat<(X86LFence), (LFENCE)>;
4019 def : Pat<(X86MFence), (MFENCE)>;
4021 //===----------------------------------------------------------------------===//
4022 // SSE 1 & 2 - Load/Store XCSR register
4023 //===----------------------------------------------------------------------===//
4025 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
4026 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
4027 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
4028 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
4029 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
4030 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
4032 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
4033 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
4034 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
4035 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
4036 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
4037 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
4039 //===---------------------------------------------------------------------===//
4040 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
4041 //===---------------------------------------------------------------------===//
4043 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4045 let hasSideEffects = 0, SchedRW = [WriteMove] in {
4046 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4047 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
4049 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4050 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
4052 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4053 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4055 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4056 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
4061 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4062 SchedRW = [WriteMove] in {
4063 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4064 "movdqa\t{$src, $dst|$dst, $src}", [],
4067 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4068 "movdqa\t{$src, $dst|$dst, $src}", [],
4069 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
4070 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4071 "movdqu\t{$src, $dst|$dst, $src}", [],
4074 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
4075 "movdqu\t{$src, $dst|$dst, $src}", [],
4076 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
4079 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4080 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4081 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4082 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4084 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4085 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
4087 let Predicates = [HasAVX] in {
4088 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4089 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4091 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4092 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
4097 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4098 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
4099 (ins i128mem:$dst, VR128:$src),
4100 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4102 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
4103 (ins i256mem:$dst, VR256:$src),
4104 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
4106 let Predicates = [HasAVX] in {
4107 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4108 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4110 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
4111 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
4116 let SchedRW = [WriteMove] in {
4117 let hasSideEffects = 0 in
4118 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4119 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
4121 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4122 "movdqu\t{$src, $dst|$dst, $src}",
4123 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4126 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
4127 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4128 "movdqa\t{$src, $dst|$dst, $src}", [],
4131 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4132 "movdqu\t{$src, $dst|$dst, $src}",
4133 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
4137 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
4138 hasSideEffects = 0, SchedRW = [WriteLoad] in {
4139 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4140 "movdqa\t{$src, $dst|$dst, $src}",
4141 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
4143 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4144 "movdqu\t{$src, $dst|$dst, $src}",
4145 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
4147 XS, Requires<[UseSSE2]>;
4150 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
4151 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4152 "movdqa\t{$src, $dst|$dst, $src}",
4153 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
4155 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
4156 "movdqu\t{$src, $dst|$dst, $src}",
4157 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
4159 XS, Requires<[UseSSE2]>;
4162 } // ExeDomain = SSEPackedInt
4164 let Predicates = [HasAVX] in {
4165 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4166 (VMOVDQUmr addr:$dst, VR128:$src)>;
4167 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
4168 (VMOVDQUYmr addr:$dst, VR256:$src)>;
4170 let Predicates = [UseSSE2] in
4171 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4172 (MOVDQUmr addr:$dst, VR128:$src)>;
4174 //===---------------------------------------------------------------------===//
4175 // SSE2 - Packed Integer Arithmetic Instructions
4176 //===---------------------------------------------------------------------===//
4178 let Sched = WriteVecIMul in
4179 def SSE_PMADD : OpndItins<
4180 IIC_SSE_PMADD, IIC_SSE_PMADD
4183 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4185 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
4186 RegisterClass RC, PatFrag memop_frag,
4187 X86MemOperand x86memop,
4189 bit IsCommutable = 0,
4191 let isCommutable = IsCommutable in
4192 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4193 (ins RC:$src1, RC:$src2),
4195 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4196 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4197 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
4198 Sched<[itins.Sched]>;
4199 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4200 (ins RC:$src1, x86memop:$src2),
4202 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4203 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4204 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
4205 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
4208 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
4209 Intrinsic IntId256, OpndItins itins,
4210 bit IsCommutable = 0> {
4211 let Predicates = [HasAVX] in
4212 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
4213 VR128, loadv2i64, i128mem, itins,
4214 IsCommutable, 0>, VEX_4V;
4216 let Constraints = "$src1 = $dst" in
4217 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
4218 i128mem, itins, IsCommutable, 1>;
4220 let Predicates = [HasAVX2] in
4221 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
4222 VR256, loadv4i64, i256mem, itins,
4223 IsCommutable, 0>, VEX_4V, VEX_L;
4226 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
4227 string OpcodeStr, SDNode OpNode,
4228 SDNode OpNode2, RegisterClass RC,
4229 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
4230 ShiftOpndItins itins,
4232 // src2 is always 128-bit
4233 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4234 (ins RC:$src1, VR128:$src2),
4236 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4237 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4238 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
4239 itins.rr>, Sched<[WriteVecShift]>;
4240 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4241 (ins RC:$src1, i128mem:$src2),
4243 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4244 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4245 [(set RC:$dst, (DstVT (OpNode RC:$src1,
4246 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
4247 Sched<[WriteVecShiftLd, ReadAfterLd]>;
4248 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
4249 (ins RC:$src1, i8imm:$src2),
4251 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4252 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4253 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
4254 Sched<[WriteVecShift]>;
4257 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4258 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4259 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4260 PatFrag memop_frag, X86MemOperand x86memop,
4262 bit IsCommutable = 0, bit Is2Addr = 1> {
4263 let isCommutable = IsCommutable in
4264 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4265 (ins RC:$src1, RC:$src2),
4267 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4269 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4270 Sched<[itins.Sched]>;
4271 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4272 (ins RC:$src1, x86memop:$src2),
4274 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4275 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4276 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4277 (bitconvert (memop_frag addr:$src2)))))]>,
4278 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4280 } // ExeDomain = SSEPackedInt
4282 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4283 SSE_INTALU_ITINS_P, 1>;
4284 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4285 SSE_INTALU_ITINS_P, 1>;
4286 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4287 SSE_INTALU_ITINS_P, 1>;
4288 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4289 SSE_INTALUQ_ITINS_P, 1>;
4290 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4291 SSE_INTMUL_ITINS_P, 1>;
4292 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4293 SSE_INTMUL_ITINS_P, 1>;
4294 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4295 SSE_INTMUL_ITINS_P, 1>;
4296 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4297 SSE_INTALU_ITINS_P, 0>;
4298 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4299 SSE_INTALU_ITINS_P, 0>;
4300 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4301 SSE_INTALU_ITINS_P, 0>;
4302 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4303 SSE_INTALUQ_ITINS_P, 0>;
4304 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4305 SSE_INTALU_ITINS_P, 0>;
4306 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4307 SSE_INTALU_ITINS_P, 0>;
4308 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4309 SSE_INTALU_ITINS_P, 1>;
4310 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4311 SSE_INTALU_ITINS_P, 1>;
4312 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4313 SSE_INTALU_ITINS_P, 1>;
4314 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4315 SSE_INTALU_ITINS_P, 1>;
4318 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4319 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4320 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4321 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4322 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4323 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4324 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4325 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4326 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4327 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4328 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4329 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4330 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4331 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4332 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4333 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4334 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4335 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4336 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4337 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4339 let Predicates = [HasAVX] in
4340 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4341 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4343 let Predicates = [HasAVX2] in
4344 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4345 VR256, loadv4i64, i256mem,
4346 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4347 let Constraints = "$src1 = $dst" in
4348 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4349 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4351 //===---------------------------------------------------------------------===//
4352 // SSE2 - Packed Integer Logical Instructions
4353 //===---------------------------------------------------------------------===//
4355 let Predicates = [HasAVX] in {
4356 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4357 VR128, v8i16, v8i16, bc_v8i16,
4358 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4359 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4360 VR128, v4i32, v4i32, bc_v4i32,
4361 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4362 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4363 VR128, v2i64, v2i64, bc_v2i64,
4364 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4366 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4367 VR128, v8i16, v8i16, bc_v8i16,
4368 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4369 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4370 VR128, v4i32, v4i32, bc_v4i32,
4371 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4372 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4373 VR128, v2i64, v2i64, bc_v2i64,
4374 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4376 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4377 VR128, v8i16, v8i16, bc_v8i16,
4378 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4379 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4380 VR128, v4i32, v4i32, bc_v4i32,
4381 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4383 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4384 // 128-bit logical shifts.
4385 def VPSLLDQri : PDIi8<0x73, MRM7r,
4386 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4387 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4389 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4391 def VPSRLDQri : PDIi8<0x73, MRM3r,
4392 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4393 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4395 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4397 // PSRADQri doesn't exist in SSE[1-3].
4399 } // Predicates = [HasAVX]
4401 let Predicates = [HasAVX2] in {
4402 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4403 VR256, v16i16, v8i16, bc_v8i16,
4404 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4405 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4406 VR256, v8i32, v4i32, bc_v4i32,
4407 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4408 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4409 VR256, v4i64, v2i64, bc_v2i64,
4410 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4412 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4413 VR256, v16i16, v8i16, bc_v8i16,
4414 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4415 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4416 VR256, v8i32, v4i32, bc_v4i32,
4417 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4418 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4419 VR256, v4i64, v2i64, bc_v2i64,
4420 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4422 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4423 VR256, v16i16, v8i16, bc_v8i16,
4424 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4425 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4426 VR256, v8i32, v4i32, bc_v4i32,
4427 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4429 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4430 // 256-bit logical shifts.
4431 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4432 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4433 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4435 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4437 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4438 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4439 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4441 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4443 // PSRADQYri doesn't exist in SSE[1-3].
4445 } // Predicates = [HasAVX2]
4447 let Constraints = "$src1 = $dst" in {
4448 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4449 VR128, v8i16, v8i16, bc_v8i16,
4450 SSE_INTSHIFT_ITINS_P>;
4451 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4452 VR128, v4i32, v4i32, bc_v4i32,
4453 SSE_INTSHIFT_ITINS_P>;
4454 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4455 VR128, v2i64, v2i64, bc_v2i64,
4456 SSE_INTSHIFT_ITINS_P>;
4458 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4459 VR128, v8i16, v8i16, bc_v8i16,
4460 SSE_INTSHIFT_ITINS_P>;
4461 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4462 VR128, v4i32, v4i32, bc_v4i32,
4463 SSE_INTSHIFT_ITINS_P>;
4464 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4465 VR128, v2i64, v2i64, bc_v2i64,
4466 SSE_INTSHIFT_ITINS_P>;
4468 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4469 VR128, v8i16, v8i16, bc_v8i16,
4470 SSE_INTSHIFT_ITINS_P>;
4471 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4472 VR128, v4i32, v4i32, bc_v4i32,
4473 SSE_INTSHIFT_ITINS_P>;
4475 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4476 // 128-bit logical shifts.
4477 def PSLLDQri : PDIi8<0x73, MRM7r,
4478 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4479 "pslldq\t{$src2, $dst|$dst, $src2}",
4481 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4482 IIC_SSE_INTSHDQ_P_RI>;
4483 def PSRLDQri : PDIi8<0x73, MRM3r,
4484 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4485 "psrldq\t{$src2, $dst|$dst, $src2}",
4487 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4488 IIC_SSE_INTSHDQ_P_RI>;
4489 // PSRADQri doesn't exist in SSE[1-3].
4491 } // Constraints = "$src1 = $dst"
4493 let Predicates = [HasAVX] in {
4494 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4495 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4496 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4497 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4498 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4499 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4501 // Shift up / down and insert zero's.
4502 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4503 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4504 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4505 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4508 let Predicates = [HasAVX2] in {
4509 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4510 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4511 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4512 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4515 let Predicates = [UseSSE2] in {
4516 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4517 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4518 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4519 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4520 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4521 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4523 // Shift up / down and insert zero's.
4524 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4525 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4526 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4527 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4530 //===---------------------------------------------------------------------===//
4531 // SSE2 - Packed Integer Comparison Instructions
4532 //===---------------------------------------------------------------------===//
4534 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4535 SSE_INTALU_ITINS_P, 1>;
4536 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4537 SSE_INTALU_ITINS_P, 1>;
4538 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4539 SSE_INTALU_ITINS_P, 1>;
4540 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4541 SSE_INTALU_ITINS_P, 0>;
4542 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4543 SSE_INTALU_ITINS_P, 0>;
4544 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4545 SSE_INTALU_ITINS_P, 0>;
4547 //===---------------------------------------------------------------------===//
4548 // SSE2 - Packed Integer Shuffle Instructions
4549 //===---------------------------------------------------------------------===//
4551 let ExeDomain = SSEPackedInt in {
4552 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4554 let Predicates = [HasAVX] in {
4555 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4556 (ins VR128:$src1, i8imm:$src2),
4557 !strconcat("v", OpcodeStr,
4558 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4560 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4561 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4562 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4563 (ins i128mem:$src1, i8imm:$src2),
4564 !strconcat("v", OpcodeStr,
4565 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4567 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4568 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4569 Sched<[WriteShuffleLd]>;
4572 let Predicates = [HasAVX2] in {
4573 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4574 (ins VR256:$src1, i8imm:$src2),
4575 !strconcat("v", OpcodeStr,
4576 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4578 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4579 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4580 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4581 (ins i256mem:$src1, i8imm:$src2),
4582 !strconcat("v", OpcodeStr,
4583 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4585 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4586 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4587 Sched<[WriteShuffleLd]>;
4590 let Predicates = [UseSSE2] in {
4591 def ri : Ii8<0x70, MRMSrcReg,
4592 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4593 !strconcat(OpcodeStr,
4594 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4596 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4597 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4598 def mi : Ii8<0x70, MRMSrcMem,
4599 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4600 !strconcat(OpcodeStr,
4601 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4603 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4604 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4605 Sched<[WriteShuffleLd, ReadAfterLd]>;
4608 } // ExeDomain = SSEPackedInt
4610 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4611 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4612 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4614 let Predicates = [HasAVX] in {
4615 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4616 (VPSHUFDmi addr:$src1, imm:$imm)>;
4617 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4618 (VPSHUFDri VR128:$src1, imm:$imm)>;
4621 let Predicates = [UseSSE2] in {
4622 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4623 (PSHUFDmi addr:$src1, imm:$imm)>;
4624 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4625 (PSHUFDri VR128:$src1, imm:$imm)>;
4628 //===---------------------------------------------------------------------===//
4629 // Packed Integer Pack Instructions (SSE & AVX)
4630 //===---------------------------------------------------------------------===//
4632 let ExeDomain = SSEPackedInt in {
4633 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4634 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4636 def rr : PDI<opc, MRMSrcReg,
4637 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4639 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4640 !strconcat(OpcodeStr,
4641 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4643 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4644 Sched<[WriteShuffle]>;
4645 def rm : PDI<opc, MRMSrcMem,
4646 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4648 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4649 !strconcat(OpcodeStr,
4650 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4652 (OutVT (OpNode VR128:$src1,
4653 (bc_frag (memopv2i64 addr:$src2)))))]>,
4654 Sched<[WriteShuffleLd, ReadAfterLd]>;
4657 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4658 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4659 def Yrr : PDI<opc, MRMSrcReg,
4660 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4661 !strconcat(OpcodeStr,
4662 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4664 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4665 Sched<[WriteShuffle]>;
4666 def Yrm : PDI<opc, MRMSrcMem,
4667 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4668 !strconcat(OpcodeStr,
4669 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4671 (OutVT (OpNode VR256:$src1,
4672 (bc_frag (memopv4i64 addr:$src2)))))]>,
4673 Sched<[WriteShuffleLd, ReadAfterLd]>;
4676 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4677 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4679 def rr : SS48I<opc, MRMSrcReg,
4680 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4682 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4683 !strconcat(OpcodeStr,
4684 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4686 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4687 Sched<[WriteShuffle]>;
4688 def rm : SS48I<opc, MRMSrcMem,
4689 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4691 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4692 !strconcat(OpcodeStr,
4693 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4695 (OutVT (OpNode VR128:$src1,
4696 (bc_frag (memopv2i64 addr:$src2)))))]>,
4697 Sched<[WriteShuffleLd, ReadAfterLd]>;
4700 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4701 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4702 def Yrr : SS48I<opc, MRMSrcReg,
4703 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4704 !strconcat(OpcodeStr,
4705 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4707 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4708 Sched<[WriteShuffle]>;
4709 def Yrm : SS48I<opc, MRMSrcMem,
4710 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4711 !strconcat(OpcodeStr,
4712 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4714 (OutVT (OpNode VR256:$src1,
4715 (bc_frag (memopv4i64 addr:$src2)))))]>,
4716 Sched<[WriteShuffleLd, ReadAfterLd]>;
4719 let Predicates = [HasAVX] in {
4720 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4721 bc_v8i16, 0>, VEX_4V;
4722 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4723 bc_v4i32, 0>, VEX_4V;
4725 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4726 bc_v8i16, 0>, VEX_4V;
4727 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4728 bc_v4i32, 0>, VEX_4V;
4731 let Predicates = [HasAVX2] in {
4732 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4733 bc_v16i16>, VEX_4V, VEX_L;
4734 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4735 bc_v8i32>, VEX_4V, VEX_L;
4737 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4738 bc_v16i16>, VEX_4V, VEX_L;
4739 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4740 bc_v8i32>, VEX_4V, VEX_L;
4743 let Constraints = "$src1 = $dst" in {
4744 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4746 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4749 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4752 let Predicates = [HasSSE41] in
4753 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4756 } // ExeDomain = SSEPackedInt
4758 //===---------------------------------------------------------------------===//
4759 // SSE2 - Packed Integer Unpack Instructions
4760 //===---------------------------------------------------------------------===//
4762 let ExeDomain = SSEPackedInt in {
4763 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4764 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4765 def rr : PDI<opc, MRMSrcReg,
4766 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4768 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4769 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4770 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4771 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4772 def rm : PDI<opc, MRMSrcMem,
4773 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4775 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4776 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4777 [(set VR128:$dst, (OpNode VR128:$src1,
4778 (bc_frag (memopv2i64
4781 Sched<[WriteShuffleLd, ReadAfterLd]>;
4784 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4785 SDNode OpNode, PatFrag bc_frag> {
4786 def Yrr : PDI<opc, MRMSrcReg,
4787 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4788 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4789 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4790 Sched<[WriteShuffle]>;
4791 def Yrm : PDI<opc, MRMSrcMem,
4792 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4793 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4794 [(set VR256:$dst, (OpNode VR256:$src1,
4795 (bc_frag (memopv4i64 addr:$src2))))]>,
4796 Sched<[WriteShuffleLd, ReadAfterLd]>;
4799 let Predicates = [HasAVX] in {
4800 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4801 bc_v16i8, 0>, VEX_4V;
4802 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4803 bc_v8i16, 0>, VEX_4V;
4804 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4805 bc_v4i32, 0>, VEX_4V;
4806 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4807 bc_v2i64, 0>, VEX_4V;
4809 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4810 bc_v16i8, 0>, VEX_4V;
4811 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4812 bc_v8i16, 0>, VEX_4V;
4813 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4814 bc_v4i32, 0>, VEX_4V;
4815 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4816 bc_v2i64, 0>, VEX_4V;
4819 let Predicates = [HasAVX2] in {
4820 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4821 bc_v32i8>, VEX_4V, VEX_L;
4822 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4823 bc_v16i16>, VEX_4V, VEX_L;
4824 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4825 bc_v8i32>, VEX_4V, VEX_L;
4826 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4827 bc_v4i64>, VEX_4V, VEX_L;
4829 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4830 bc_v32i8>, VEX_4V, VEX_L;
4831 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4832 bc_v16i16>, VEX_4V, VEX_L;
4833 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4834 bc_v8i32>, VEX_4V, VEX_L;
4835 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4836 bc_v4i64>, VEX_4V, VEX_L;
4839 let Constraints = "$src1 = $dst" in {
4840 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4842 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4844 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4846 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4849 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4851 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4853 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4855 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4858 } // ExeDomain = SSEPackedInt
4860 //===---------------------------------------------------------------------===//
4861 // SSE2 - Packed Integer Extract and Insert
4862 //===---------------------------------------------------------------------===//
4864 let ExeDomain = SSEPackedInt in {
4865 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4866 def rri : Ii8<0xC4, MRMSrcReg,
4867 (outs VR128:$dst), (ins VR128:$src1,
4868 GR32orGR64:$src2, i32i8imm:$src3),
4870 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4871 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4873 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4874 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4875 def rmi : Ii8<0xC4, MRMSrcMem,
4876 (outs VR128:$dst), (ins VR128:$src1,
4877 i16mem:$src2, i32i8imm:$src3),
4879 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4880 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4882 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4883 imm:$src3))], IIC_SSE_PINSRW>,
4884 Sched<[WriteShuffleLd, ReadAfterLd]>;
4888 let Predicates = [HasAVX] in
4889 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4890 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4891 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4892 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4893 imm:$src2))]>, PD, VEX,
4894 Sched<[WriteShuffle]>;
4895 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4896 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4897 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4898 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4899 imm:$src2))], IIC_SSE_PEXTRW>,
4900 Sched<[WriteShuffleLd, ReadAfterLd]>;
4903 let Predicates = [HasAVX] in
4904 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4906 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4907 defm PINSRW : sse2_pinsrw, PD;
4909 } // ExeDomain = SSEPackedInt
4911 //===---------------------------------------------------------------------===//
4912 // SSE2 - Packed Mask Creation
4913 //===---------------------------------------------------------------------===//
4915 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4917 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4919 "pmovmskb\t{$src, $dst|$dst, $src}",
4920 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4921 IIC_SSE_MOVMSK>, VEX;
4923 let Predicates = [HasAVX2] in {
4924 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4926 "pmovmskb\t{$src, $dst|$dst, $src}",
4927 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4931 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4932 "pmovmskb\t{$src, $dst|$dst, $src}",
4933 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4936 } // ExeDomain = SSEPackedInt
4938 //===---------------------------------------------------------------------===//
4939 // SSE2 - Conditional Store
4940 //===---------------------------------------------------------------------===//
4942 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4944 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4945 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4946 (ins VR128:$src, VR128:$mask),
4947 "maskmovdqu\t{$mask, $src|$src, $mask}",
4948 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4949 IIC_SSE_MASKMOV>, VEX;
4950 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4951 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4952 (ins VR128:$src, VR128:$mask),
4953 "maskmovdqu\t{$mask, $src|$src, $mask}",
4954 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4955 IIC_SSE_MASKMOV>, VEX;
4957 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4958 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4959 "maskmovdqu\t{$mask, $src|$src, $mask}",
4960 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4962 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4963 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4964 "maskmovdqu\t{$mask, $src|$src, $mask}",
4965 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4968 } // ExeDomain = SSEPackedInt
4970 //===---------------------------------------------------------------------===//
4971 // SSE2 - Move Doubleword
4972 //===---------------------------------------------------------------------===//
4974 //===---------------------------------------------------------------------===//
4975 // Move Int Doubleword to Packed Double Int
4977 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4978 "movd\t{$src, $dst|$dst, $src}",
4980 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4981 VEX, Sched<[WriteMove]>;
4982 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4983 "movd\t{$src, $dst|$dst, $src}",
4985 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4987 VEX, Sched<[WriteLoad]>;
4988 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4989 "movq\t{$src, $dst|$dst, $src}",
4991 (v2i64 (scalar_to_vector GR64:$src)))],
4992 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4993 let isCodeGenOnly = 1 in
4994 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4995 "movq\t{$src, $dst|$dst, $src}",
4996 [(set FR64:$dst, (bitconvert GR64:$src))],
4997 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4999 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
5000 "movd\t{$src, $dst|$dst, $src}",
5002 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
5004 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5005 "movd\t{$src, $dst|$dst, $src}",
5007 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
5008 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5009 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5010 "mov{d|q}\t{$src, $dst|$dst, $src}",
5012 (v2i64 (scalar_to_vector GR64:$src)))],
5013 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
5014 let isCodeGenOnly = 1 in
5015 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
5016 "mov{d|q}\t{$src, $dst|$dst, $src}",
5017 [(set FR64:$dst, (bitconvert GR64:$src))],
5018 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
5020 //===---------------------------------------------------------------------===//
5021 // Move Int Doubleword to Single Scalar
5023 let isCodeGenOnly = 1 in {
5024 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
5025 "movd\t{$src, $dst|$dst, $src}",
5026 [(set FR32:$dst, (bitconvert GR32:$src))],
5027 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
5029 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
5030 "movd\t{$src, $dst|$dst, $src}",
5031 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
5033 VEX, Sched<[WriteLoad]>;
5034 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
5035 "movd\t{$src, $dst|$dst, $src}",
5036 [(set FR32:$dst, (bitconvert GR32:$src))],
5037 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
5039 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
5040 "movd\t{$src, $dst|$dst, $src}",
5041 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
5042 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5045 //===---------------------------------------------------------------------===//
5046 // Move Packed Doubleword Int to Packed Double Int
5048 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5049 "movd\t{$src, $dst|$dst, $src}",
5050 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5051 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
5053 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
5054 (ins i32mem:$dst, VR128:$src),
5055 "movd\t{$src, $dst|$dst, $src}",
5056 [(store (i32 (vector_extract (v4i32 VR128:$src),
5057 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
5058 VEX, Sched<[WriteStore]>;
5059 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
5060 "movd\t{$src, $dst|$dst, $src}",
5061 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
5062 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
5064 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
5065 "movd\t{$src, $dst|$dst, $src}",
5066 [(store (i32 (vector_extract (v4i32 VR128:$src),
5067 (iPTR 0))), addr:$dst)],
5068 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5070 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
5071 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5073 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
5074 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5076 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
5077 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
5079 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
5080 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
5082 //===---------------------------------------------------------------------===//
5083 // Move Packed Doubleword Int first element to Doubleword Int
5085 let SchedRW = [WriteMove] in {
5086 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5087 "movq\t{$src, $dst|$dst, $src}",
5088 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5093 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
5094 "mov{d|q}\t{$src, $dst|$dst, $src}",
5095 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
5100 //===---------------------------------------------------------------------===//
5101 // Bitcast FR64 <-> GR64
5103 let isCodeGenOnly = 1 in {
5104 let Predicates = [UseAVX] in
5105 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5106 "movq\t{$src, $dst|$dst, $src}",
5107 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
5108 VEX, Sched<[WriteLoad]>;
5109 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5110 "movq\t{$src, $dst|$dst, $src}",
5111 [(set GR64:$dst, (bitconvert FR64:$src))],
5112 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
5113 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5114 "movq\t{$src, $dst|$dst, $src}",
5115 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5116 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5118 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
5119 "movq\t{$src, $dst|$dst, $src}",
5120 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
5121 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
5122 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
5123 "mov{d|q}\t{$src, $dst|$dst, $src}",
5124 [(set GR64:$dst, (bitconvert FR64:$src))],
5125 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5126 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
5127 "movq\t{$src, $dst|$dst, $src}",
5128 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
5129 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5132 //===---------------------------------------------------------------------===//
5133 // Move Scalar Single to Double Int
5135 let isCodeGenOnly = 1 in {
5136 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5137 "movd\t{$src, $dst|$dst, $src}",
5138 [(set GR32:$dst, (bitconvert FR32:$src))],
5139 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
5140 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5141 "movd\t{$src, $dst|$dst, $src}",
5142 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5143 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
5144 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
5145 "movd\t{$src, $dst|$dst, $src}",
5146 [(set GR32:$dst, (bitconvert FR32:$src))],
5147 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
5148 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
5149 "movd\t{$src, $dst|$dst, $src}",
5150 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
5151 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
5154 //===---------------------------------------------------------------------===//
5155 // Patterns and instructions to describe movd/movq to XMM register zero-extends
5157 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
5158 let AddedComplexity = 15 in {
5159 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5160 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
5161 [(set VR128:$dst, (v2i64 (X86vzmovl
5162 (v2i64 (scalar_to_vector GR64:$src)))))],
5165 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
5166 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
5167 [(set VR128:$dst, (v2i64 (X86vzmovl
5168 (v2i64 (scalar_to_vector GR64:$src)))))],
5171 } // isCodeGenOnly, SchedRW
5173 let Predicates = [UseAVX] in {
5174 let AddedComplexity = 15 in
5175 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5176 (VMOVDI2PDIrr GR32:$src)>;
5178 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
5179 let AddedComplexity = 20 in {
5180 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5181 (VMOVDI2PDIrm addr:$src)>;
5182 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5183 (VMOVDI2PDIrm addr:$src)>;
5184 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5185 (VMOVDI2PDIrm addr:$src)>;
5187 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
5188 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
5189 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
5190 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
5191 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5192 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
5193 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
5196 let Predicates = [UseSSE2] in {
5197 let AddedComplexity = 15 in
5198 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5199 (MOVDI2PDIrr GR32:$src)>;
5201 let AddedComplexity = 20 in {
5202 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5203 (MOVDI2PDIrm addr:$src)>;
5204 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5205 (MOVDI2PDIrm addr:$src)>;
5206 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5207 (MOVDI2PDIrm addr:$src)>;
5211 // These are the correct encodings of the instructions so that we know how to
5212 // read correct assembly, even though we continue to emit the wrong ones for
5213 // compatibility with Darwin's buggy assembler.
5214 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5215 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5216 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5217 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5218 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
5219 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5220 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5221 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5222 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5224 //===---------------------------------------------------------------------===//
5225 // SSE2 - Move Quadword
5226 //===---------------------------------------------------------------------===//
5228 //===---------------------------------------------------------------------===//
5229 // Move Quadword Int to Packed Quadword Int
5232 let SchedRW = [WriteLoad] in {
5233 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5234 "vmovq\t{$src, $dst|$dst, $src}",
5236 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
5237 VEX, Requires<[UseAVX]>;
5238 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5239 "movq\t{$src, $dst|$dst, $src}",
5241 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
5243 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
5246 //===---------------------------------------------------------------------===//
5247 // Move Packed Quadword Int to Quadword Int
5249 let SchedRW = [WriteStore] in {
5250 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5251 "movq\t{$src, $dst|$dst, $src}",
5252 [(store (i64 (vector_extract (v2i64 VR128:$src),
5253 (iPTR 0))), addr:$dst)],
5254 IIC_SSE_MOVDQ>, VEX;
5255 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5256 "movq\t{$src, $dst|$dst, $src}",
5257 [(store (i64 (vector_extract (v2i64 VR128:$src),
5258 (iPTR 0))), addr:$dst)],
5262 // For disassembler only
5263 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5264 SchedRW = [WriteVecLogic] in {
5265 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5266 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5267 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5268 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5271 //===---------------------------------------------------------------------===//
5272 // Store / copy lower 64-bits of a XMM register.
5274 let Predicates = [UseAVX] in
5275 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5276 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5277 let Predicates = [UseSSE2] in
5278 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5279 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5281 let isCodeGenOnly = 1, AddedComplexity = 20 in {
5282 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5283 "vmovq\t{$src, $dst|$dst, $src}",
5285 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5286 (loadi64 addr:$src))))))],
5288 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5290 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5291 "movq\t{$src, $dst|$dst, $src}",
5293 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5294 (loadi64 addr:$src))))))],
5296 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5299 let Predicates = [UseAVX], AddedComplexity = 20 in {
5300 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5301 (VMOVZQI2PQIrm addr:$src)>;
5302 def : Pat<(v2i64 (X86vzload addr:$src)),
5303 (VMOVZQI2PQIrm addr:$src)>;
5306 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5307 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5308 (MOVZQI2PQIrm addr:$src)>;
5309 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5312 let Predicates = [HasAVX] in {
5313 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5314 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5315 def : Pat<(v4i64 (X86vzload addr:$src)),
5316 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5319 //===---------------------------------------------------------------------===//
5320 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5321 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5323 let SchedRW = [WriteVecLogic] in {
5324 let AddedComplexity = 15 in
5325 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5326 "vmovq\t{$src, $dst|$dst, $src}",
5327 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5329 XS, VEX, Requires<[UseAVX]>;
5330 let AddedComplexity = 15 in
5331 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5332 "movq\t{$src, $dst|$dst, $src}",
5333 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5335 XS, Requires<[UseSSE2]>;
5338 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5339 let AddedComplexity = 20 in
5340 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5341 "vmovq\t{$src, $dst|$dst, $src}",
5342 [(set VR128:$dst, (v2i64 (X86vzmovl
5343 (loadv2i64 addr:$src))))],
5345 XS, VEX, Requires<[UseAVX]>;
5346 let AddedComplexity = 20 in {
5347 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5348 "movq\t{$src, $dst|$dst, $src}",
5349 [(set VR128:$dst, (v2i64 (X86vzmovl
5350 (loadv2i64 addr:$src))))],
5352 XS, Requires<[UseSSE2]>;
5354 } // isCodeGenOnly, SchedRW
5356 let AddedComplexity = 20 in {
5357 let Predicates = [UseAVX] in {
5358 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5359 (VMOVZPQILo2PQIrr VR128:$src)>;
5361 let Predicates = [UseSSE2] in {
5362 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5363 (MOVZPQILo2PQIrr VR128:$src)>;
5367 //===---------------------------------------------------------------------===//
5368 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5369 //===---------------------------------------------------------------------===//
5370 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5371 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5372 X86MemOperand x86memop> {
5373 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5374 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5375 [(set RC:$dst, (vt (OpNode RC:$src)))],
5376 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5377 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5378 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5379 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5380 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5383 let Predicates = [HasAVX] in {
5384 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5385 v4f32, VR128, loadv4f32, f128mem>, VEX;
5386 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5387 v4f32, VR128, loadv4f32, f128mem>, VEX;
5388 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5389 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5390 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5391 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5393 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5394 memopv4f32, f128mem>;
5395 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5396 memopv4f32, f128mem>;
5398 let Predicates = [HasAVX] in {
5399 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5400 (VMOVSHDUPrr VR128:$src)>;
5401 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5402 (VMOVSHDUPrm addr:$src)>;
5403 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5404 (VMOVSLDUPrr VR128:$src)>;
5405 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5406 (VMOVSLDUPrm addr:$src)>;
5407 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5408 (VMOVSHDUPYrr VR256:$src)>;
5409 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5410 (VMOVSHDUPYrm addr:$src)>;
5411 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5412 (VMOVSLDUPYrr VR256:$src)>;
5413 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5414 (VMOVSLDUPYrm addr:$src)>;
5417 let Predicates = [UseSSE3] in {
5418 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5419 (MOVSHDUPrr VR128:$src)>;
5420 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5421 (MOVSHDUPrm addr:$src)>;
5422 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5423 (MOVSLDUPrr VR128:$src)>;
5424 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5425 (MOVSLDUPrm addr:$src)>;
5428 //===---------------------------------------------------------------------===//
5429 // SSE3 - Replicate Double FP - MOVDDUP
5430 //===---------------------------------------------------------------------===//
5432 multiclass sse3_replicate_dfp<string OpcodeStr> {
5433 let hasSideEffects = 0 in
5434 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5435 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5436 [], IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5437 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5438 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5441 (scalar_to_vector (loadf64 addr:$src)))))],
5442 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5445 // FIXME: Merge with above classe when there're patterns for the ymm version
5446 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5447 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5448 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5449 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5450 Sched<[WriteFShuffle]>;
5451 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5455 (scalar_to_vector (loadf64 addr:$src)))))]>,
5459 let Predicates = [HasAVX] in {
5460 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5461 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5464 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5466 let Predicates = [HasAVX] in {
5467 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5468 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5469 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5470 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5471 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5472 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5473 def : Pat<(X86Movddup (bc_v2f64
5474 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5475 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5478 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5479 (VMOVDDUPYrm addr:$src)>;
5480 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5481 (VMOVDDUPYrm addr:$src)>;
5482 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5483 (VMOVDDUPYrm addr:$src)>;
5484 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5485 (VMOVDDUPYrr VR256:$src)>;
5488 let Predicates = [UseAVX, OptForSize] in {
5489 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5490 (VMOVDDUPrm addr:$src)>;
5491 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5492 (VMOVDDUPrm addr:$src)>;
5495 let Predicates = [UseSSE3] in {
5496 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5497 (MOVDDUPrm addr:$src)>;
5498 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5499 (MOVDDUPrm addr:$src)>;
5500 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5501 (MOVDDUPrm addr:$src)>;
5502 def : Pat<(X86Movddup (bc_v2f64
5503 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5504 (MOVDDUPrm addr:$src)>;
5507 //===---------------------------------------------------------------------===//
5508 // SSE3 - Move Unaligned Integer
5509 //===---------------------------------------------------------------------===//
5511 let SchedRW = [WriteLoad] in {
5512 let Predicates = [HasAVX] in {
5513 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5514 "vlddqu\t{$src, $dst|$dst, $src}",
5515 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5516 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5517 "vlddqu\t{$src, $dst|$dst, $src}",
5518 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5521 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5522 "lddqu\t{$src, $dst|$dst, $src}",
5523 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5527 //===---------------------------------------------------------------------===//
5528 // SSE3 - Arithmetic
5529 //===---------------------------------------------------------------------===//
5531 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5532 X86MemOperand x86memop, OpndItins itins,
5534 def rr : I<0xD0, MRMSrcReg,
5535 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5537 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5538 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5539 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5540 Sched<[itins.Sched]>;
5541 def rm : I<0xD0, MRMSrcMem,
5542 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5544 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5545 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5546 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5547 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5550 let Predicates = [HasAVX] in {
5551 let ExeDomain = SSEPackedSingle in {
5552 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5553 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5554 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5555 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5557 let ExeDomain = SSEPackedDouble in {
5558 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5559 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5560 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5561 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5564 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5565 let ExeDomain = SSEPackedSingle in
5566 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5567 f128mem, SSE_ALU_F32P>, XD;
5568 let ExeDomain = SSEPackedDouble in
5569 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5570 f128mem, SSE_ALU_F64P>, PD;
5573 // Patterns used to select 'addsub' instructions.
5574 let Predicates = [HasAVX] in {
5575 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5576 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5577 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5578 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5579 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5580 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5581 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5582 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5584 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5585 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5586 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 (memop addr:$rhs)))),
5587 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5588 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5589 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5590 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 (memop addr:$rhs)))),
5591 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5594 let Predicates = [UseSSE3] in {
5595 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5596 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5597 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5598 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5599 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5600 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5601 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5602 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5605 //===---------------------------------------------------------------------===//
5606 // SSE3 Instructions
5607 //===---------------------------------------------------------------------===//
5610 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5611 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5612 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5614 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5615 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5616 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5619 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5621 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5622 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5623 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5624 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5626 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5627 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5628 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5630 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5631 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5632 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5635 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5637 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5638 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5639 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5640 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5643 let Predicates = [HasAVX] in {
5644 let ExeDomain = SSEPackedSingle in {
5645 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5646 X86fhadd, 0>, VEX_4V;
5647 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5648 X86fhsub, 0>, VEX_4V;
5649 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5650 X86fhadd, 0>, VEX_4V, VEX_L;
5651 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5652 X86fhsub, 0>, VEX_4V, VEX_L;
5654 let ExeDomain = SSEPackedDouble in {
5655 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5656 X86fhadd, 0>, VEX_4V;
5657 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5658 X86fhsub, 0>, VEX_4V;
5659 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5660 X86fhadd, 0>, VEX_4V, VEX_L;
5661 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5662 X86fhsub, 0>, VEX_4V, VEX_L;
5666 let Constraints = "$src1 = $dst" in {
5667 let ExeDomain = SSEPackedSingle in {
5668 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5669 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5671 let ExeDomain = SSEPackedDouble in {
5672 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5673 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5677 //===---------------------------------------------------------------------===//
5678 // SSSE3 - Packed Absolute Instructions
5679 //===---------------------------------------------------------------------===//
5682 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5683 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5684 Intrinsic IntId128> {
5685 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5687 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5688 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5689 Sched<[WriteVecALU]>;
5691 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5693 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5696 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5697 Sched<[WriteVecALULd]>;
5700 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5701 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5702 Intrinsic IntId256> {
5703 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5705 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5706 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5707 Sched<[WriteVecALU]>;
5709 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5711 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5714 (bitconvert (memopv4i64 addr:$src))))]>,
5715 Sched<[WriteVecALULd]>;
5718 // Helper fragments to match sext vXi1 to vXiY.
5719 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5721 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5722 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5723 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5725 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5726 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5728 let Predicates = [HasAVX] in {
5729 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5730 int_x86_ssse3_pabs_b_128>, VEX;
5731 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5732 int_x86_ssse3_pabs_w_128>, VEX;
5733 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5734 int_x86_ssse3_pabs_d_128>, VEX;
5737 (bc_v2i64 (v16i1sextv16i8)),
5738 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5739 (VPABSBrr128 VR128:$src)>;
5741 (bc_v2i64 (v8i1sextv8i16)),
5742 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5743 (VPABSWrr128 VR128:$src)>;
5745 (bc_v2i64 (v4i1sextv4i32)),
5746 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5747 (VPABSDrr128 VR128:$src)>;
5750 let Predicates = [HasAVX2] in {
5751 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5752 int_x86_avx2_pabs_b>, VEX, VEX_L;
5753 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5754 int_x86_avx2_pabs_w>, VEX, VEX_L;
5755 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5756 int_x86_avx2_pabs_d>, VEX, VEX_L;
5759 (bc_v4i64 (v32i1sextv32i8)),
5760 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5761 (VPABSBrr256 VR256:$src)>;
5763 (bc_v4i64 (v16i1sextv16i16)),
5764 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5765 (VPABSWrr256 VR256:$src)>;
5767 (bc_v4i64 (v8i1sextv8i32)),
5768 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5769 (VPABSDrr256 VR256:$src)>;
5772 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5773 int_x86_ssse3_pabs_b_128>;
5774 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5775 int_x86_ssse3_pabs_w_128>;
5776 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5777 int_x86_ssse3_pabs_d_128>;
5779 let Predicates = [HasSSSE3] in {
5781 (bc_v2i64 (v16i1sextv16i8)),
5782 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5783 (PABSBrr128 VR128:$src)>;
5785 (bc_v2i64 (v8i1sextv8i16)),
5786 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5787 (PABSWrr128 VR128:$src)>;
5789 (bc_v2i64 (v4i1sextv4i32)),
5790 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5791 (PABSDrr128 VR128:$src)>;
5794 //===---------------------------------------------------------------------===//
5795 // SSSE3 - Packed Binary Operator Instructions
5796 //===---------------------------------------------------------------------===//
5798 let Sched = WriteVecALU in {
5799 def SSE_PHADDSUBD : OpndItins<
5800 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5802 def SSE_PHADDSUBSW : OpndItins<
5803 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5805 def SSE_PHADDSUBW : OpndItins<
5806 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5809 let Sched = WriteShuffle in
5810 def SSE_PSHUFB : OpndItins<
5811 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5813 let Sched = WriteVecALU in
5814 def SSE_PSIGN : OpndItins<
5815 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5817 let Sched = WriteVecIMul in
5818 def SSE_PMULHRSW : OpndItins<
5819 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5822 /// SS3I_binop_rm - Simple SSSE3 bin op
5823 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5824 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5825 X86MemOperand x86memop, OpndItins itins,
5827 let isCommutable = 1 in
5828 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5829 (ins RC:$src1, RC:$src2),
5831 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5832 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5833 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5834 Sched<[itins.Sched]>;
5835 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5836 (ins RC:$src1, x86memop:$src2),
5838 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5839 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5841 (OpVT (OpNode RC:$src1,
5842 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5843 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5846 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5847 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5848 Intrinsic IntId128, OpndItins itins,
5850 let isCommutable = 1 in
5851 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5852 (ins VR128:$src1, VR128:$src2),
5854 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5855 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5856 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5857 Sched<[itins.Sched]>;
5858 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5859 (ins VR128:$src1, i128mem:$src2),
5861 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5862 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5864 (IntId128 VR128:$src1,
5865 (bitconvert (memopv2i64 addr:$src2))))]>,
5866 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5869 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5871 X86FoldableSchedWrite Sched> {
5872 let isCommutable = 1 in
5873 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5874 (ins VR256:$src1, VR256:$src2),
5875 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5876 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5878 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5879 (ins VR256:$src1, i256mem:$src2),
5880 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5882 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5883 Sched<[Sched.Folded, ReadAfterLd]>;
5886 let ImmT = NoImm, Predicates = [HasAVX] in {
5887 let isCommutable = 0 in {
5888 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5890 SSE_PHADDSUBW, 0>, VEX_4V;
5891 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5893 SSE_PHADDSUBD, 0>, VEX_4V;
5894 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5896 SSE_PHADDSUBW, 0>, VEX_4V;
5897 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5899 SSE_PHADDSUBD, 0>, VEX_4V;
5900 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5902 SSE_PSIGN, 0>, VEX_4V;
5903 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5905 SSE_PSIGN, 0>, VEX_4V;
5906 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5908 SSE_PSIGN, 0>, VEX_4V;
5909 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5911 SSE_PSHUFB, 0>, VEX_4V;
5912 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5913 int_x86_ssse3_phadd_sw_128,
5914 SSE_PHADDSUBSW, 0>, VEX_4V;
5915 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5916 int_x86_ssse3_phsub_sw_128,
5917 SSE_PHADDSUBSW, 0>, VEX_4V;
5918 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5919 int_x86_ssse3_pmadd_ub_sw_128,
5920 SSE_PMADD, 0>, VEX_4V;
5922 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5923 int_x86_ssse3_pmul_hr_sw_128,
5924 SSE_PMULHRSW, 0>, VEX_4V;
5927 let ImmT = NoImm, Predicates = [HasAVX2] in {
5928 let isCommutable = 0 in {
5929 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5931 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5932 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5934 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5935 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5937 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5938 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5940 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5941 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5943 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5944 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5946 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5947 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5949 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5950 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5952 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5953 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5954 int_x86_avx2_phadd_sw,
5955 WriteVecALU>, VEX_4V, VEX_L;
5956 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5957 int_x86_avx2_phsub_sw,
5958 WriteVecALU>, VEX_4V, VEX_L;
5959 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5960 int_x86_avx2_pmadd_ub_sw,
5961 WriteVecIMul>, VEX_4V, VEX_L;
5963 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5964 int_x86_avx2_pmul_hr_sw,
5965 WriteVecIMul>, VEX_4V, VEX_L;
5968 // None of these have i8 immediate fields.
5969 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5970 let isCommutable = 0 in {
5971 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5972 memopv2i64, i128mem, SSE_PHADDSUBW>;
5973 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5974 memopv2i64, i128mem, SSE_PHADDSUBD>;
5975 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5976 memopv2i64, i128mem, SSE_PHADDSUBW>;
5977 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5978 memopv2i64, i128mem, SSE_PHADDSUBD>;
5979 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5980 memopv2i64, i128mem, SSE_PSIGN>;
5981 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5982 memopv2i64, i128mem, SSE_PSIGN>;
5983 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5984 memopv2i64, i128mem, SSE_PSIGN>;
5985 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5986 memopv2i64, i128mem, SSE_PSHUFB>;
5987 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5988 int_x86_ssse3_phadd_sw_128,
5990 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5991 int_x86_ssse3_phsub_sw_128,
5993 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5994 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5996 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5997 int_x86_ssse3_pmul_hr_sw_128,
6001 //===---------------------------------------------------------------------===//
6002 // SSSE3 - Packed Align Instruction Patterns
6003 //===---------------------------------------------------------------------===//
6005 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
6006 let hasSideEffects = 0 in {
6007 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
6008 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6010 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6012 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6013 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
6015 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
6016 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6018 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6020 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6021 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6025 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
6026 let hasSideEffects = 0 in {
6027 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
6028 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6030 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6031 []>, Sched<[WriteShuffle]>;
6033 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
6034 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
6036 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6037 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6041 let Predicates = [HasAVX] in
6042 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
6043 let Predicates = [HasAVX2] in
6044 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
6045 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
6046 defm PALIGN : ssse3_palignr<"palignr">;
6048 let Predicates = [HasAVX2] in {
6049 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6050 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6051 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6052 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6053 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6054 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6055 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6056 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
6059 let Predicates = [HasAVX] in {
6060 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6061 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6062 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6063 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6064 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6065 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6066 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6067 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6070 let Predicates = [UseSSSE3] in {
6071 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6072 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6073 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6074 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6075 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6076 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6077 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
6078 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
6081 //===---------------------------------------------------------------------===//
6082 // SSSE3 - Thread synchronization
6083 //===---------------------------------------------------------------------===//
6085 let SchedRW = [WriteSystem] in {
6086 let usesCustomInserter = 1 in {
6087 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
6088 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
6089 Requires<[HasSSE3]>;
6092 let Uses = [EAX, ECX, EDX] in
6093 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
6094 TB, Requires<[HasSSE3]>;
6095 let Uses = [ECX, EAX] in
6096 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
6097 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
6098 TB, Requires<[HasSSE3]>;
6101 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
6102 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
6104 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
6105 Requires<[Not64BitMode]>;
6106 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
6107 Requires<[In64BitMode]>;
6109 //===----------------------------------------------------------------------===//
6110 // SSE4.1 - Packed Move with Sign/Zero Extend
6111 //===----------------------------------------------------------------------===//
6113 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
6114 RegisterClass OutRC, RegisterClass InRC,
6116 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
6117 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6119 Sched<[itins.Sched]>;
6121 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
6122 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6124 itins.rm>, Sched<[itins.Sched.Folded]>;
6127 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
6128 X86MemOperand MemOp, X86MemOperand MemYOp,
6129 OpndItins SSEItins, OpndItins AVXItins,
6130 OpndItins AVX2Itins> {
6131 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
6132 let Predicates = [HasAVX] in
6133 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
6134 VR128, VR128, AVXItins>, VEX;
6135 let Predicates = [HasAVX2] in
6136 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
6137 VR256, VR128, AVX2Itins>, VEX, VEX_L;
6140 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
6141 X86MemOperand MemOp, X86MemOperand MemYOp> {
6142 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
6144 SSE_INTALU_ITINS_SHUFF_P,
6145 DEFAULT_ITINS_SHUFFLESCHED,
6146 DEFAULT_ITINS_SHUFFLESCHED>;
6147 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
6148 !strconcat("pmovzx", OpcodeStr),
6150 SSE_INTALU_ITINS_SHUFF_P,
6151 DEFAULT_ITINS_SHUFFLESCHED,
6152 DEFAULT_ITINS_SHUFFLESCHED>;
6155 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
6156 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
6157 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
6159 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
6160 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
6162 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
6165 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, SDNode ExtOp> {
6166 // Register-Register patterns
6167 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
6168 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
6169 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
6170 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
6171 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
6172 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
6174 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
6175 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
6176 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
6177 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
6179 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
6180 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
6182 // On AVX2, we also support 256bit inputs.
6183 // FIXME: remove these patterns when the old shuffle lowering goes away.
6184 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
6185 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6186 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
6187 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6188 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
6189 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6191 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
6192 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6193 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
6194 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6196 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
6197 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6199 // AVX2 Register-Memory patterns
6200 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6201 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6202 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6203 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6204 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6205 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6206 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6207 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
6209 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6210 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6211 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6212 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6213 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6214 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6215 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6216 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
6218 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6219 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6220 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6221 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6222 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6223 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6224 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6225 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
6227 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6228 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6229 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6230 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6231 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6232 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6233 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6234 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
6236 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6237 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6238 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6239 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6240 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6241 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6242 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6243 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6245 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6246 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6247 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6248 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6249 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6250 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6251 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6252 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6255 let Predicates = [HasAVX2] in {
6256 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", X86vsext>;
6257 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", X86vzext>;
6260 // SSE4.1/AVX patterns.
6261 multiclass SS41I_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
6262 PatFrag ExtLoad16> {
6263 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6264 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6265 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6266 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6267 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6268 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6270 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6271 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6272 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6273 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6275 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6276 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6278 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6279 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6280 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6281 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6282 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6283 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6284 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6285 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6286 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6287 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6289 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6290 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6291 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6292 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6293 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6294 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6295 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6296 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6298 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6299 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6300 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6301 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6302 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6303 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6304 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6305 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6307 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6308 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6309 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6310 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6311 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6312 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6313 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6314 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6315 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6316 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6318 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6319 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6320 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6321 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6322 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6323 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6324 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6325 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6327 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6328 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6329 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6330 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6331 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6332 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6333 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6334 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6335 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6336 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6339 let Predicates = [HasAVX] in {
6340 defm : SS41I_pmovx_patterns<"VPMOVSX", X86vsext, extloadi32i16>;
6341 defm : SS41I_pmovx_patterns<"VPMOVZX", X86vzext, loadi16_anyext>;
6344 let Predicates = [UseSSE41] in {
6345 defm : SS41I_pmovx_patterns<"PMOVSX", X86vsext, extloadi32i16>;
6346 defm : SS41I_pmovx_patterns<"PMOVZX", X86vzext, loadi16_anyext>;
6349 //===----------------------------------------------------------------------===//
6350 // SSE4.1 - Extract Instructions
6351 //===----------------------------------------------------------------------===//
6353 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6354 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6355 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6356 (ins VR128:$src1, i32i8imm:$src2),
6357 !strconcat(OpcodeStr,
6358 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6359 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6361 Sched<[WriteShuffle]>;
6362 let hasSideEffects = 0, mayStore = 1,
6363 SchedRW = [WriteShuffleLd, WriteRMW] in
6364 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6365 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6366 !strconcat(OpcodeStr,
6367 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6368 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6369 imm:$src2)))), addr:$dst)]>;
6372 let Predicates = [HasAVX] in
6373 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6375 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6378 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6379 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6380 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6381 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6382 (ins VR128:$src1, i32i8imm:$src2),
6383 !strconcat(OpcodeStr,
6384 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6385 []>, Sched<[WriteShuffle]>;
6387 let hasSideEffects = 0, mayStore = 1,
6388 SchedRW = [WriteShuffleLd, WriteRMW] in
6389 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6390 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6391 !strconcat(OpcodeStr,
6392 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6393 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6394 imm:$src2)))), addr:$dst)]>;
6397 let Predicates = [HasAVX] in
6398 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6400 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6403 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6404 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6405 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6406 (ins VR128:$src1, i32i8imm:$src2),
6407 !strconcat(OpcodeStr,
6408 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6410 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6411 Sched<[WriteShuffle]>;
6412 let SchedRW = [WriteShuffleLd, WriteRMW] in
6413 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6414 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6415 !strconcat(OpcodeStr,
6416 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6417 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6421 let Predicates = [HasAVX] in
6422 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6424 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6426 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6427 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6428 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6429 (ins VR128:$src1, i32i8imm:$src2),
6430 !strconcat(OpcodeStr,
6431 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6433 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6434 Sched<[WriteShuffle]>, REX_W;
6435 let SchedRW = [WriteShuffleLd, WriteRMW] in
6436 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6437 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6438 !strconcat(OpcodeStr,
6439 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6440 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6441 addr:$dst)]>, REX_W;
6444 let Predicates = [HasAVX] in
6445 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6447 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6449 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6451 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6452 OpndItins itins = DEFAULT_ITINS> {
6453 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6454 (ins VR128:$src1, i32i8imm:$src2),
6455 !strconcat(OpcodeStr,
6456 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6457 [(set GR32orGR64:$dst,
6458 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6459 itins.rr>, Sched<[WriteFBlend]>;
6460 let SchedRW = [WriteFBlendLd, WriteRMW] in
6461 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6462 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6463 !strconcat(OpcodeStr,
6464 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6465 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6466 addr:$dst)], itins.rm>;
6469 let ExeDomain = SSEPackedSingle in {
6470 let Predicates = [UseAVX] in
6471 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6472 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6475 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6476 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6479 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6481 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6484 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6485 Requires<[UseSSE41]>;
6487 //===----------------------------------------------------------------------===//
6488 // SSE4.1 - Insert Instructions
6489 //===----------------------------------------------------------------------===//
6491 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6492 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6493 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6495 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6497 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6499 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6500 Sched<[WriteShuffle]>;
6501 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6502 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6504 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6506 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6508 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6509 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6512 let Predicates = [HasAVX] in
6513 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6514 let Constraints = "$src1 = $dst" in
6515 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6517 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6518 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6519 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6521 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6523 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6525 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6526 Sched<[WriteShuffle]>;
6527 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6528 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6530 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6532 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6534 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6535 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6538 let Predicates = [HasAVX] in
6539 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6540 let Constraints = "$src1 = $dst" in
6541 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6543 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6544 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6545 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6547 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6549 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6551 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6552 Sched<[WriteShuffle]>;
6553 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6554 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6556 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6558 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6560 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6561 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6564 let Predicates = [HasAVX] in
6565 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6566 let Constraints = "$src1 = $dst" in
6567 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6569 // insertps has a few different modes, there's the first two here below which
6570 // are optimized inserts that won't zero arbitrary elements in the destination
6571 // vector. The next one matches the intrinsic and could zero arbitrary elements
6572 // in the target vector.
6573 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6574 OpndItins itins = DEFAULT_ITINS> {
6575 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6576 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6578 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6580 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6582 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6583 Sched<[WriteFShuffle]>;
6584 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6585 (ins VR128:$src1, f32mem:$src2, i8imm:$src3),
6587 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6589 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6591 (X86insertps VR128:$src1,
6592 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6593 imm:$src3))], itins.rm>,
6594 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6597 let ExeDomain = SSEPackedSingle in {
6598 let Predicates = [UseAVX] in
6599 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6600 let Constraints = "$src1 = $dst" in
6601 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6604 let Predicates = [UseSSE41] in {
6605 // If we're inserting an element from a load or a null pshuf of a load,
6606 // fold the load into the insertps instruction.
6607 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6608 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6610 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6611 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6612 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6613 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6616 let Predicates = [UseAVX] in {
6617 // If we're inserting an element from a vbroadcast of a load, fold the
6618 // load into the X86insertps instruction.
6619 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6620 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6621 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6622 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6623 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6624 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6627 //===----------------------------------------------------------------------===//
6628 // SSE4.1 - Round Instructions
6629 //===----------------------------------------------------------------------===//
6631 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6632 X86MemOperand x86memop, RegisterClass RC,
6633 PatFrag mem_frag32, PatFrag mem_frag64,
6634 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6635 let ExeDomain = SSEPackedSingle in {
6636 // Intrinsic operation, reg.
6637 // Vector intrinsic operation, reg
6638 def PSr : SS4AIi8<opcps, MRMSrcReg,
6639 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6640 !strconcat(OpcodeStr,
6641 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6642 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6643 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6645 // Vector intrinsic operation, mem
6646 def PSm : SS4AIi8<opcps, MRMSrcMem,
6647 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6648 !strconcat(OpcodeStr,
6649 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6651 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6652 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6653 } // ExeDomain = SSEPackedSingle
6655 let ExeDomain = SSEPackedDouble in {
6656 // Vector intrinsic operation, reg
6657 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6658 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6659 !strconcat(OpcodeStr,
6660 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6661 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6662 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6664 // Vector intrinsic operation, mem
6665 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6666 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6667 !strconcat(OpcodeStr,
6668 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6670 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6671 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6672 } // ExeDomain = SSEPackedDouble
6675 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6678 Intrinsic F64Int, bit Is2Addr = 1> {
6679 let ExeDomain = GenericDomain in {
6681 let hasSideEffects = 0 in
6682 def SSr : SS4AIi8<opcss, MRMSrcReg,
6683 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6685 !strconcat(OpcodeStr,
6686 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6687 !strconcat(OpcodeStr,
6688 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6689 []>, Sched<[WriteFAdd]>;
6691 // Intrinsic operation, reg.
6692 let isCodeGenOnly = 1 in
6693 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6694 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6696 !strconcat(OpcodeStr,
6697 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6698 !strconcat(OpcodeStr,
6699 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6700 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6703 // Intrinsic operation, mem.
6704 def SSm : SS4AIi8<opcss, MRMSrcMem,
6705 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6707 !strconcat(OpcodeStr,
6708 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6709 !strconcat(OpcodeStr,
6710 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6712 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6713 Sched<[WriteFAddLd, ReadAfterLd]>;
6716 let hasSideEffects = 0 in
6717 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6718 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6720 !strconcat(OpcodeStr,
6721 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6722 !strconcat(OpcodeStr,
6723 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6724 []>, Sched<[WriteFAdd]>;
6726 // Intrinsic operation, reg.
6727 let isCodeGenOnly = 1 in
6728 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6729 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6731 !strconcat(OpcodeStr,
6732 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6733 !strconcat(OpcodeStr,
6734 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6735 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6738 // Intrinsic operation, mem.
6739 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6740 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6742 !strconcat(OpcodeStr,
6743 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6744 !strconcat(OpcodeStr,
6745 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6747 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6748 Sched<[WriteFAddLd, ReadAfterLd]>;
6749 } // ExeDomain = GenericDomain
6752 // FP round - roundss, roundps, roundsd, roundpd
6753 let Predicates = [HasAVX] in {
6755 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6756 loadv4f32, loadv2f64,
6757 int_x86_sse41_round_ps,
6758 int_x86_sse41_round_pd>, VEX;
6759 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6760 loadv8f32, loadv4f64,
6761 int_x86_avx_round_ps_256,
6762 int_x86_avx_round_pd_256>, VEX, VEX_L;
6763 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6764 int_x86_sse41_round_ss,
6765 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6767 def : Pat<(ffloor FR32:$src),
6768 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6769 def : Pat<(f64 (ffloor FR64:$src)),
6770 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6771 def : Pat<(f32 (fnearbyint FR32:$src)),
6772 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6773 def : Pat<(f64 (fnearbyint FR64:$src)),
6774 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6775 def : Pat<(f32 (fceil FR32:$src)),
6776 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6777 def : Pat<(f64 (fceil FR64:$src)),
6778 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6779 def : Pat<(f32 (frint FR32:$src)),
6780 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6781 def : Pat<(f64 (frint FR64:$src)),
6782 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6783 def : Pat<(f32 (ftrunc FR32:$src)),
6784 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6785 def : Pat<(f64 (ftrunc FR64:$src)),
6786 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6788 def : Pat<(v4f32 (ffloor VR128:$src)),
6789 (VROUNDPSr VR128:$src, (i32 0x1))>;
6790 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6791 (VROUNDPSr VR128:$src, (i32 0xC))>;
6792 def : Pat<(v4f32 (fceil VR128:$src)),
6793 (VROUNDPSr VR128:$src, (i32 0x2))>;
6794 def : Pat<(v4f32 (frint VR128:$src)),
6795 (VROUNDPSr VR128:$src, (i32 0x4))>;
6796 def : Pat<(v4f32 (ftrunc VR128:$src)),
6797 (VROUNDPSr VR128:$src, (i32 0x3))>;
6799 def : Pat<(v2f64 (ffloor VR128:$src)),
6800 (VROUNDPDr VR128:$src, (i32 0x1))>;
6801 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6802 (VROUNDPDr VR128:$src, (i32 0xC))>;
6803 def : Pat<(v2f64 (fceil VR128:$src)),
6804 (VROUNDPDr VR128:$src, (i32 0x2))>;
6805 def : Pat<(v2f64 (frint VR128:$src)),
6806 (VROUNDPDr VR128:$src, (i32 0x4))>;
6807 def : Pat<(v2f64 (ftrunc VR128:$src)),
6808 (VROUNDPDr VR128:$src, (i32 0x3))>;
6810 def : Pat<(v8f32 (ffloor VR256:$src)),
6811 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6812 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6813 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6814 def : Pat<(v8f32 (fceil VR256:$src)),
6815 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6816 def : Pat<(v8f32 (frint VR256:$src)),
6817 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6818 def : Pat<(v8f32 (ftrunc VR256:$src)),
6819 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6821 def : Pat<(v4f64 (ffloor VR256:$src)),
6822 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6823 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6824 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6825 def : Pat<(v4f64 (fceil VR256:$src)),
6826 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6827 def : Pat<(v4f64 (frint VR256:$src)),
6828 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6829 def : Pat<(v4f64 (ftrunc VR256:$src)),
6830 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6833 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6834 memopv4f32, memopv2f64,
6835 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6836 let Constraints = "$src1 = $dst" in
6837 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6838 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6840 let Predicates = [UseSSE41] in {
6841 def : Pat<(ffloor FR32:$src),
6842 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6843 def : Pat<(f64 (ffloor FR64:$src)),
6844 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6845 def : Pat<(f32 (fnearbyint FR32:$src)),
6846 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6847 def : Pat<(f64 (fnearbyint FR64:$src)),
6848 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6849 def : Pat<(f32 (fceil FR32:$src)),
6850 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6851 def : Pat<(f64 (fceil FR64:$src)),
6852 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6853 def : Pat<(f32 (frint FR32:$src)),
6854 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6855 def : Pat<(f64 (frint FR64:$src)),
6856 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6857 def : Pat<(f32 (ftrunc FR32:$src)),
6858 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6859 def : Pat<(f64 (ftrunc FR64:$src)),
6860 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6862 def : Pat<(v4f32 (ffloor VR128:$src)),
6863 (ROUNDPSr VR128:$src, (i32 0x1))>;
6864 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6865 (ROUNDPSr VR128:$src, (i32 0xC))>;
6866 def : Pat<(v4f32 (fceil VR128:$src)),
6867 (ROUNDPSr VR128:$src, (i32 0x2))>;
6868 def : Pat<(v4f32 (frint VR128:$src)),
6869 (ROUNDPSr VR128:$src, (i32 0x4))>;
6870 def : Pat<(v4f32 (ftrunc VR128:$src)),
6871 (ROUNDPSr VR128:$src, (i32 0x3))>;
6873 def : Pat<(v2f64 (ffloor VR128:$src)),
6874 (ROUNDPDr VR128:$src, (i32 0x1))>;
6875 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6876 (ROUNDPDr VR128:$src, (i32 0xC))>;
6877 def : Pat<(v2f64 (fceil VR128:$src)),
6878 (ROUNDPDr VR128:$src, (i32 0x2))>;
6879 def : Pat<(v2f64 (frint VR128:$src)),
6880 (ROUNDPDr VR128:$src, (i32 0x4))>;
6881 def : Pat<(v2f64 (ftrunc VR128:$src)),
6882 (ROUNDPDr VR128:$src, (i32 0x3))>;
6885 //===----------------------------------------------------------------------===//
6886 // SSE4.1 - Packed Bit Test
6887 //===----------------------------------------------------------------------===//
6889 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6890 // the intel intrinsic that corresponds to this.
6891 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6892 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6893 "vptest\t{$src2, $src1|$src1, $src2}",
6894 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6895 Sched<[WriteVecLogic]>, VEX;
6896 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6897 "vptest\t{$src2, $src1|$src1, $src2}",
6898 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6899 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6901 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6902 "vptest\t{$src2, $src1|$src1, $src2}",
6903 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6904 Sched<[WriteVecLogic]>, VEX, VEX_L;
6905 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6906 "vptest\t{$src2, $src1|$src1, $src2}",
6907 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6908 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6911 let Defs = [EFLAGS] in {
6912 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6913 "ptest\t{$src2, $src1|$src1, $src2}",
6914 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6915 Sched<[WriteVecLogic]>;
6916 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6917 "ptest\t{$src2, $src1|$src1, $src2}",
6918 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6919 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6922 // The bit test instructions below are AVX only
6923 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6924 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6925 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6926 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6927 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6928 Sched<[WriteVecLogic]>, VEX;
6929 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6930 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6931 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6932 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6935 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6936 let ExeDomain = SSEPackedSingle in {
6937 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6938 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6941 let ExeDomain = SSEPackedDouble in {
6942 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6943 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6948 //===----------------------------------------------------------------------===//
6949 // SSE4.1 - Misc Instructions
6950 //===----------------------------------------------------------------------===//
6952 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6953 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6954 "popcnt{w}\t{$src, $dst|$dst, $src}",
6955 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6956 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6958 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6959 "popcnt{w}\t{$src, $dst|$dst, $src}",
6960 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6961 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6962 Sched<[WriteFAddLd]>, OpSize16, XS;
6964 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6965 "popcnt{l}\t{$src, $dst|$dst, $src}",
6966 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6967 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6970 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6971 "popcnt{l}\t{$src, $dst|$dst, $src}",
6972 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6973 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6974 Sched<[WriteFAddLd]>, OpSize32, XS;
6976 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6977 "popcnt{q}\t{$src, $dst|$dst, $src}",
6978 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6979 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6980 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6981 "popcnt{q}\t{$src, $dst|$dst, $src}",
6982 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6983 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6984 Sched<[WriteFAddLd]>, XS;
6989 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6990 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6992 X86FoldableSchedWrite Sched> {
6993 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6995 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6996 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6998 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7000 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7002 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>,
7003 Sched<[Sched.Folded]>;
7006 // PHMIN has the same profile as PSAD, thus we use the same scheduling
7007 // model, although the naming is misleading.
7008 let Predicates = [HasAVX] in
7009 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
7010 int_x86_sse41_phminposuw,
7012 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
7013 int_x86_sse41_phminposuw,
7016 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
7017 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
7018 Intrinsic IntId128, bit Is2Addr = 1,
7019 OpndItins itins = DEFAULT_ITINS> {
7020 let isCommutable = 1 in
7021 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7022 (ins VR128:$src1, VR128:$src2),
7024 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7025 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7026 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
7027 itins.rr>, Sched<[itins.Sched]>;
7028 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7029 (ins VR128:$src1, i128mem:$src2),
7031 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7032 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7034 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
7035 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7038 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
7039 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
7041 X86FoldableSchedWrite Sched> {
7042 let isCommutable = 1 in
7043 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
7044 (ins VR256:$src1, VR256:$src2),
7045 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7046 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
7048 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
7049 (ins VR256:$src1, i256mem:$src2),
7050 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7052 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
7053 Sched<[Sched.Folded, ReadAfterLd]>;
7057 /// SS48I_binop_rm - Simple SSE41 binary operator.
7058 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7059 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7060 X86MemOperand x86memop, bit Is2Addr = 1,
7061 OpndItins itins = SSE_INTALU_ITINS_P> {
7062 let isCommutable = 1 in
7063 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7064 (ins RC:$src1, RC:$src2),
7066 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7067 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7068 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7069 Sched<[itins.Sched]>;
7070 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7071 (ins RC:$src1, x86memop:$src2),
7073 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7074 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7076 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
7077 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7080 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
7082 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
7083 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
7084 PatFrag memop_frag, X86MemOperand x86memop,
7086 bit IsCommutable = 0, bit Is2Addr = 1> {
7087 let isCommutable = IsCommutable in
7088 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7089 (ins RC:$src1, RC:$src2),
7091 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7092 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7093 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
7094 Sched<[itins.Sched]>;
7095 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7096 (ins RC:$src1, x86memop:$src2),
7098 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7099 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7100 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
7101 (bitconvert (memop_frag addr:$src2)))))]>,
7102 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7105 let Predicates = [HasAVX, NoVLX] in {
7106 let isCommutable = 0 in
7107 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
7108 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7110 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
7111 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7113 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
7114 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7116 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
7117 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7119 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
7120 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7122 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
7123 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7125 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
7126 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7128 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
7129 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7131 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
7132 VR128, loadv2i64, i128mem,
7133 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
7136 let Predicates = [HasAVX2, NoVLX] in {
7137 let isCommutable = 0 in
7138 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
7139 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7141 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
7142 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7144 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
7145 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7147 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
7148 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7150 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
7151 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7153 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
7154 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7156 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
7157 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7159 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
7160 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7162 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
7163 VR256, loadv4i64, i256mem,
7164 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
7167 let Constraints = "$src1 = $dst" in {
7168 let isCommutable = 0 in
7169 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
7170 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7171 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
7172 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7173 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
7174 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7175 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
7176 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7177 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
7178 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7179 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
7180 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7181 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
7182 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7183 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7184 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7185 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
7186 VR128, memopv2i64, i128mem,
7187 SSE_INTMUL_ITINS_P, 1>;
7190 let Predicates = [HasAVX] in {
7191 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7192 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
7194 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7195 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7198 let Predicates = [HasAVX2] in {
7199 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7200 memopv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
7202 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7203 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7207 let Constraints = "$src1 = $dst" in {
7208 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7209 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7210 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7211 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7214 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7215 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7216 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7217 X86MemOperand x86memop, bit Is2Addr = 1,
7218 OpndItins itins = DEFAULT_ITINS> {
7219 let isCommutable = 1 in
7220 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7221 (ins RC:$src1, RC:$src2, i8imm:$src3),
7223 !strconcat(OpcodeStr,
7224 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7225 !strconcat(OpcodeStr,
7226 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7227 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7228 Sched<[itins.Sched]>;
7229 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7230 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
7232 !strconcat(OpcodeStr,
7233 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7234 !strconcat(OpcodeStr,
7235 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7238 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7239 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7242 let Predicates = [HasAVX] in {
7243 let isCommutable = 0 in {
7244 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7245 VR128, loadv2i64, i128mem, 0,
7246 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7249 let ExeDomain = SSEPackedSingle in {
7250 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7251 VR128, loadv4f32, f128mem, 0,
7252 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7253 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7254 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7255 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7258 let ExeDomain = SSEPackedDouble in {
7259 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7260 VR128, loadv2f64, f128mem, 0,
7261 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7262 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7263 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7264 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7267 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7268 VR128, loadv2i64, i128mem, 0,
7269 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7271 let ExeDomain = SSEPackedSingle in
7272 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7273 VR128, loadv4f32, f128mem, 0,
7274 SSE_DPPS_ITINS>, VEX_4V;
7275 let ExeDomain = SSEPackedDouble in
7276 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7277 VR128, loadv2f64, f128mem, 0,
7278 SSE_DPPS_ITINS>, VEX_4V;
7279 let ExeDomain = SSEPackedSingle in
7280 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7281 VR256, loadv8f32, i256mem, 0,
7282 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7285 let Predicates = [HasAVX2] in {
7286 let isCommutable = 0 in {
7287 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7288 VR256, loadv4i64, i256mem, 0,
7289 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7290 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7291 VR256, loadv4i64, i256mem, 0,
7292 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7296 let Constraints = "$src1 = $dst" in {
7297 let isCommutable = 0 in {
7298 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7299 VR128, memopv2i64, i128mem,
7300 1, SSE_MPSADBW_ITINS>;
7302 let ExeDomain = SSEPackedSingle in
7303 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7304 VR128, memopv4f32, f128mem,
7305 1, SSE_INTALU_ITINS_FBLEND_P>;
7306 let ExeDomain = SSEPackedDouble in
7307 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7308 VR128, memopv2f64, f128mem,
7309 1, SSE_INTALU_ITINS_FBLEND_P>;
7310 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7311 VR128, memopv2i64, i128mem,
7312 1, SSE_INTALU_ITINS_BLEND_P>;
7313 let ExeDomain = SSEPackedSingle in
7314 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7315 VR128, memopv4f32, f128mem, 1,
7317 let ExeDomain = SSEPackedDouble in
7318 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7319 VR128, memopv2f64, f128mem, 1,
7323 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7324 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7325 RegisterClass RC, X86MemOperand x86memop,
7326 PatFrag mem_frag, Intrinsic IntId,
7327 X86FoldableSchedWrite Sched> {
7328 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7329 (ins RC:$src1, RC:$src2, RC:$src3),
7330 !strconcat(OpcodeStr,
7331 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7332 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7333 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7336 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7337 (ins RC:$src1, x86memop:$src2, RC:$src3),
7338 !strconcat(OpcodeStr,
7339 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7341 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7343 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7344 Sched<[Sched.Folded, ReadAfterLd]>;
7347 let Predicates = [HasAVX] in {
7348 let ExeDomain = SSEPackedDouble in {
7349 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7350 loadv2f64, int_x86_sse41_blendvpd,
7352 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7353 loadv4f64, int_x86_avx_blendv_pd_256,
7354 WriteFVarBlend>, VEX_L;
7355 } // ExeDomain = SSEPackedDouble
7356 let ExeDomain = SSEPackedSingle in {
7357 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7358 loadv4f32, int_x86_sse41_blendvps,
7360 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7361 loadv8f32, int_x86_avx_blendv_ps_256,
7362 WriteFVarBlend>, VEX_L;
7363 } // ExeDomain = SSEPackedSingle
7364 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7365 loadv2i64, int_x86_sse41_pblendvb,
7369 let Predicates = [HasAVX2] in {
7370 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7371 loadv4i64, int_x86_avx2_pblendvb,
7372 WriteVarBlend>, VEX_L;
7375 let Predicates = [HasAVX] in {
7376 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7377 (v16i8 VR128:$src2))),
7378 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7379 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7380 (v4i32 VR128:$src2))),
7381 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7382 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7383 (v4f32 VR128:$src2))),
7384 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7385 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7386 (v2i64 VR128:$src2))),
7387 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7388 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7389 (v2f64 VR128:$src2))),
7390 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7391 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7392 (v8i32 VR256:$src2))),
7393 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7394 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7395 (v8f32 VR256:$src2))),
7396 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7397 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7398 (v4i64 VR256:$src2))),
7399 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7400 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7401 (v4f64 VR256:$src2))),
7402 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7404 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7406 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7407 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7409 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7411 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7413 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7414 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7416 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7417 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7419 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7422 let Predicates = [HasAVX2] in {
7423 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7424 (v32i8 VR256:$src2))),
7425 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7426 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7428 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7432 let Predicates = [UseAVX] in {
7433 let AddedComplexity = 15 in {
7434 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7435 // MOVS{S,D} to the lower bits.
7436 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7437 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7438 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7439 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7440 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7441 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7442 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7443 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7445 // Move low f32 and clear high bits.
7446 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7447 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7448 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7449 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7452 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7453 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7454 (SUBREG_TO_REG (i32 0),
7455 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7457 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7458 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7459 (SUBREG_TO_REG (i64 0),
7460 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7463 // Move low f64 and clear high bits.
7464 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7465 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7467 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7468 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7471 let Predicates = [UseSSE41] in {
7472 // With SSE41 we can use blends for these patterns.
7473 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7474 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7475 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7476 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7477 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7478 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7482 /// SS41I_ternary_int - SSE 4.1 ternary operator
7483 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7484 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7485 X86MemOperand x86memop, Intrinsic IntId,
7486 OpndItins itins = DEFAULT_ITINS> {
7487 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7488 (ins VR128:$src1, VR128:$src2),
7489 !strconcat(OpcodeStr,
7490 "\t{$src2, $dst|$dst, $src2}"),
7491 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7492 itins.rr>, Sched<[itins.Sched]>;
7494 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7495 (ins VR128:$src1, x86memop:$src2),
7496 !strconcat(OpcodeStr,
7497 "\t{$src2, $dst|$dst, $src2}"),
7500 (bitconvert (mem_frag addr:$src2)), XMM0))],
7501 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7505 let ExeDomain = SSEPackedDouble in
7506 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7507 int_x86_sse41_blendvpd,
7508 DEFAULT_ITINS_FBLENDSCHED>;
7509 let ExeDomain = SSEPackedSingle in
7510 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7511 int_x86_sse41_blendvps,
7512 DEFAULT_ITINS_FBLENDSCHED>;
7513 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7514 int_x86_sse41_pblendvb,
7515 DEFAULT_ITINS_VARBLENDSCHED>;
7517 // Aliases with the implicit xmm0 argument
7518 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7519 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7520 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7521 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7522 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7523 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7524 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7525 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7526 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7527 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7528 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7529 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7531 let Predicates = [UseSSE41] in {
7532 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7533 (v16i8 VR128:$src2))),
7534 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7535 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7536 (v4i32 VR128:$src2))),
7537 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7538 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7539 (v4f32 VR128:$src2))),
7540 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7541 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7542 (v2i64 VR128:$src2))),
7543 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7544 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7545 (v2f64 VR128:$src2))),
7546 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7548 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7550 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7551 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7553 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7554 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7556 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7560 let SchedRW = [WriteLoad] in {
7561 let Predicates = [HasAVX] in
7562 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7563 "vmovntdqa\t{$src, $dst|$dst, $src}",
7564 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7566 let Predicates = [HasAVX2] in
7567 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7568 "vmovntdqa\t{$src, $dst|$dst, $src}",
7569 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7571 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7572 "movntdqa\t{$src, $dst|$dst, $src}",
7573 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7576 //===----------------------------------------------------------------------===//
7577 // SSE4.2 - Compare Instructions
7578 //===----------------------------------------------------------------------===//
7580 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7581 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7582 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7583 X86MemOperand x86memop, bit Is2Addr = 1> {
7584 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7585 (ins RC:$src1, RC:$src2),
7587 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7588 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7589 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7590 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7591 (ins RC:$src1, x86memop:$src2),
7593 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7594 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7596 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7599 let Predicates = [HasAVX] in
7600 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7601 loadv2i64, i128mem, 0>, VEX_4V;
7603 let Predicates = [HasAVX2] in
7604 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7605 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7607 let Constraints = "$src1 = $dst" in
7608 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7609 memopv2i64, i128mem>;
7611 //===----------------------------------------------------------------------===//
7612 // SSE4.2 - String/text Processing Instructions
7613 //===----------------------------------------------------------------------===//
7615 // Packed Compare Implicit Length Strings, Return Mask
7616 multiclass pseudo_pcmpistrm<string asm> {
7617 def REG : PseudoI<(outs VR128:$dst),
7618 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7619 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7621 def MEM : PseudoI<(outs VR128:$dst),
7622 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7623 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7624 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7627 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7628 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7629 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7632 multiclass pcmpistrm_SS42AI<string asm> {
7633 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7634 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7635 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7636 []>, Sched<[WritePCmpIStrM]>;
7638 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7639 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7640 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7641 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7644 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7645 let Predicates = [HasAVX] in
7646 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7647 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7650 // Packed Compare Explicit Length Strings, Return Mask
7651 multiclass pseudo_pcmpestrm<string asm> {
7652 def REG : PseudoI<(outs VR128:$dst),
7653 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7654 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7655 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7656 def MEM : PseudoI<(outs VR128:$dst),
7657 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7658 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7659 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7662 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7663 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7664 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7667 multiclass SS42AI_pcmpestrm<string asm> {
7668 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7669 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7670 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7671 []>, Sched<[WritePCmpEStrM]>;
7673 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7674 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7675 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7676 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7679 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7680 let Predicates = [HasAVX] in
7681 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7682 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7685 // Packed Compare Implicit Length Strings, Return Index
7686 multiclass pseudo_pcmpistri<string asm> {
7687 def REG : PseudoI<(outs GR32:$dst),
7688 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7689 [(set GR32:$dst, EFLAGS,
7690 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7691 def MEM : PseudoI<(outs GR32:$dst),
7692 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7693 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7694 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7697 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7698 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7699 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7702 multiclass SS42AI_pcmpistri<string asm> {
7703 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7704 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7705 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7706 []>, Sched<[WritePCmpIStrI]>;
7708 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7709 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7710 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7711 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7714 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7715 let Predicates = [HasAVX] in
7716 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7717 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7720 // Packed Compare Explicit Length Strings, Return Index
7721 multiclass pseudo_pcmpestri<string asm> {
7722 def REG : PseudoI<(outs GR32:$dst),
7723 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7724 [(set GR32:$dst, EFLAGS,
7725 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7726 def MEM : PseudoI<(outs GR32:$dst),
7727 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7728 [(set GR32:$dst, EFLAGS,
7729 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7733 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7734 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7735 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7738 multiclass SS42AI_pcmpestri<string asm> {
7739 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7740 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7741 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7742 []>, Sched<[WritePCmpEStrI]>;
7744 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7745 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7746 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7747 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7750 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7751 let Predicates = [HasAVX] in
7752 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7753 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7756 //===----------------------------------------------------------------------===//
7757 // SSE4.2 - CRC Instructions
7758 //===----------------------------------------------------------------------===//
7760 // No CRC instructions have AVX equivalents
7762 // crc intrinsic instruction
7763 // This set of instructions are only rm, the only difference is the size
7765 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7766 RegisterClass RCIn, SDPatternOperator Int> :
7767 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7768 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7769 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7772 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7773 X86MemOperand x86memop, SDPatternOperator Int> :
7774 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7775 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7776 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7777 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7779 let Constraints = "$src1 = $dst" in {
7780 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7781 int_x86_sse42_crc32_32_8>;
7782 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7783 int_x86_sse42_crc32_32_8>;
7784 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7785 int_x86_sse42_crc32_32_16>, OpSize16;
7786 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7787 int_x86_sse42_crc32_32_16>, OpSize16;
7788 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7789 int_x86_sse42_crc32_32_32>, OpSize32;
7790 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7791 int_x86_sse42_crc32_32_32>, OpSize32;
7792 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7793 int_x86_sse42_crc32_64_64>, REX_W;
7794 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7795 int_x86_sse42_crc32_64_64>, REX_W;
7796 let hasSideEffects = 0 in {
7798 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7800 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7805 //===----------------------------------------------------------------------===//
7806 // SHA-NI Instructions
7807 //===----------------------------------------------------------------------===//
7809 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7811 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7812 (ins VR128:$src1, VR128:$src2),
7813 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7815 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7816 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7818 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7819 (ins VR128:$src1, i128mem:$src2),
7820 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7822 (set VR128:$dst, (IntId VR128:$src1,
7823 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7824 (set VR128:$dst, (IntId VR128:$src1,
7825 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7828 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7829 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7830 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7831 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7833 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7834 (i8 imm:$src3)))]>, TA;
7835 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7836 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7837 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7839 (int_x86_sha1rnds4 VR128:$src1,
7840 (bc_v4i32 (memopv2i64 addr:$src2)),
7841 (i8 imm:$src3)))]>, TA;
7843 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7844 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7845 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7848 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7850 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7851 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7854 // Aliases with explicit %xmm0
7855 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7856 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7857 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7858 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7860 //===----------------------------------------------------------------------===//
7861 // AES-NI Instructions
7862 //===----------------------------------------------------------------------===//
7864 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7865 Intrinsic IntId128, bit Is2Addr = 1> {
7866 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7867 (ins VR128:$src1, VR128:$src2),
7869 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7870 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7871 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7872 Sched<[WriteAESDecEnc]>;
7873 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7874 (ins VR128:$src1, i128mem:$src2),
7876 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7877 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7879 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
7880 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7883 // Perform One Round of an AES Encryption/Decryption Flow
7884 let Predicates = [HasAVX, HasAES] in {
7885 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7886 int_x86_aesni_aesenc, 0>, VEX_4V;
7887 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7888 int_x86_aesni_aesenclast, 0>, VEX_4V;
7889 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7890 int_x86_aesni_aesdec, 0>, VEX_4V;
7891 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7892 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7895 let Constraints = "$src1 = $dst" in {
7896 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7897 int_x86_aesni_aesenc>;
7898 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7899 int_x86_aesni_aesenclast>;
7900 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7901 int_x86_aesni_aesdec>;
7902 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7903 int_x86_aesni_aesdeclast>;
7906 // Perform the AES InvMixColumn Transformation
7907 let Predicates = [HasAVX, HasAES] in {
7908 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7910 "vaesimc\t{$src1, $dst|$dst, $src1}",
7912 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7914 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7915 (ins i128mem:$src1),
7916 "vaesimc\t{$src1, $dst|$dst, $src1}",
7917 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7918 Sched<[WriteAESIMCLd]>, VEX;
7920 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7922 "aesimc\t{$src1, $dst|$dst, $src1}",
7924 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7925 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7926 (ins i128mem:$src1),
7927 "aesimc\t{$src1, $dst|$dst, $src1}",
7928 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7929 Sched<[WriteAESIMCLd]>;
7931 // AES Round Key Generation Assist
7932 let Predicates = [HasAVX, HasAES] in {
7933 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7934 (ins VR128:$src1, i8imm:$src2),
7935 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7937 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7938 Sched<[WriteAESKeyGen]>, VEX;
7939 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7940 (ins i128mem:$src1, i8imm:$src2),
7941 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7943 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7944 Sched<[WriteAESKeyGenLd]>, VEX;
7946 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7947 (ins VR128:$src1, i8imm:$src2),
7948 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7950 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7951 Sched<[WriteAESKeyGen]>;
7952 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7953 (ins i128mem:$src1, i8imm:$src2),
7954 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7956 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7957 Sched<[WriteAESKeyGenLd]>;
7959 //===----------------------------------------------------------------------===//
7960 // PCLMUL Instructions
7961 //===----------------------------------------------------------------------===//
7963 // AVX carry-less Multiplication instructions
7964 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7965 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7966 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7968 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7969 Sched<[WriteCLMul]>;
7971 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7972 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7973 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7974 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7975 (loadv2i64 addr:$src2), imm:$src3))]>,
7976 Sched<[WriteCLMulLd, ReadAfterLd]>;
7978 // Carry-less Multiplication instructions
7979 let Constraints = "$src1 = $dst" in {
7980 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7981 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7982 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7984 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7985 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7987 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7988 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7989 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7990 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7991 (memopv2i64 addr:$src2), imm:$src3))],
7992 IIC_SSE_PCLMULQDQ_RM>,
7993 Sched<[WriteCLMulLd, ReadAfterLd]>;
7994 } // Constraints = "$src1 = $dst"
7997 multiclass pclmul_alias<string asm, int immop> {
7998 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7999 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
8001 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8002 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
8004 def : InstAlias<!strconcat("vpclmul", asm,
8005 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8006 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
8009 def : InstAlias<!strconcat("vpclmul", asm,
8010 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8011 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
8014 defm : pclmul_alias<"hqhq", 0x11>;
8015 defm : pclmul_alias<"hqlq", 0x01>;
8016 defm : pclmul_alias<"lqhq", 0x10>;
8017 defm : pclmul_alias<"lqlq", 0x00>;
8019 //===----------------------------------------------------------------------===//
8020 // SSE4A Instructions
8021 //===----------------------------------------------------------------------===//
8023 let Predicates = [HasSSE4A] in {
8025 let Constraints = "$src = $dst" in {
8026 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
8027 (ins VR128:$src, i8imm:$len, i8imm:$idx),
8028 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
8029 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
8031 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8032 (ins VR128:$src, VR128:$mask),
8033 "extrq\t{$mask, $src|$src, $mask}",
8034 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
8035 VR128:$mask))]>, PD;
8037 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
8038 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
8039 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
8040 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
8041 VR128:$src2, imm:$len, imm:$idx))]>, XD;
8042 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8043 (ins VR128:$src, VR128:$mask),
8044 "insertq\t{$mask, $src|$src, $mask}",
8045 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
8046 VR128:$mask))]>, XD;
8049 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
8050 "movntss\t{$src, $dst|$dst, $src}",
8051 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
8053 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
8054 "movntsd\t{$src, $dst|$dst, $src}",
8055 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
8058 //===----------------------------------------------------------------------===//
8060 //===----------------------------------------------------------------------===//
8062 //===----------------------------------------------------------------------===//
8063 // VBROADCAST - Load from memory and broadcast to all elements of the
8064 // destination operand
8066 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
8067 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
8068 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8069 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8070 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
8072 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
8073 X86MemOperand x86memop, ValueType VT,
8074 PatFrag ld_frag, SchedWrite Sched> :
8075 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8076 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8077 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
8078 Sched<[Sched]>, VEX {
8082 // AVX2 adds register forms
8083 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
8084 Intrinsic Int, SchedWrite Sched> :
8085 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8086 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8087 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
8089 let ExeDomain = SSEPackedSingle in {
8090 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
8091 f32mem, v4f32, loadf32, WriteLoad>;
8092 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
8093 f32mem, v8f32, loadf32,
8094 WriteFShuffleLd>, VEX_L;
8096 let ExeDomain = SSEPackedDouble in
8097 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
8098 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
8099 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
8100 int_x86_avx_vbroadcastf128_pd_256,
8101 WriteFShuffleLd>, VEX_L;
8103 let ExeDomain = SSEPackedSingle in {
8104 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
8105 int_x86_avx2_vbroadcast_ss_ps,
8107 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
8108 int_x86_avx2_vbroadcast_ss_ps_256,
8109 WriteFShuffle256>, VEX_L;
8111 let ExeDomain = SSEPackedDouble in
8112 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
8113 int_x86_avx2_vbroadcast_sd_pd_256,
8114 WriteFShuffle256>, VEX_L;
8116 let Predicates = [HasAVX2] in
8117 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
8118 int_x86_avx2_vbroadcasti128, WriteLoad>,
8121 let Predicates = [HasAVX] in
8122 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
8123 (VBROADCASTF128 addr:$src)>;
8126 //===----------------------------------------------------------------------===//
8127 // VINSERTF128 - Insert packed floating-point values
8129 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8130 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8131 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8132 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8133 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
8135 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
8136 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
8137 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8138 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
8141 let Predicates = [HasAVX] in {
8142 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
8144 (VINSERTF128rr VR256:$src1, VR128:$src2,
8145 (INSERT_get_vinsert128_imm VR256:$ins))>;
8146 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
8148 (VINSERTF128rr VR256:$src1, VR128:$src2,
8149 (INSERT_get_vinsert128_imm VR256:$ins))>;
8151 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
8153 (VINSERTF128rm VR256:$src1, addr:$src2,
8154 (INSERT_get_vinsert128_imm VR256:$ins))>;
8155 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
8157 (VINSERTF128rm VR256:$src1, addr:$src2,
8158 (INSERT_get_vinsert128_imm VR256:$ins))>;
8161 let Predicates = [HasAVX1Only] in {
8162 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8164 (VINSERTF128rr VR256:$src1, VR128:$src2,
8165 (INSERT_get_vinsert128_imm VR256:$ins))>;
8166 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8168 (VINSERTF128rr VR256:$src1, VR128:$src2,
8169 (INSERT_get_vinsert128_imm VR256:$ins))>;
8170 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8172 (VINSERTF128rr VR256:$src1, VR128:$src2,
8173 (INSERT_get_vinsert128_imm VR256:$ins))>;
8174 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8176 (VINSERTF128rr VR256:$src1, VR128:$src2,
8177 (INSERT_get_vinsert128_imm VR256:$ins))>;
8179 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8181 (VINSERTF128rm VR256:$src1, addr:$src2,
8182 (INSERT_get_vinsert128_imm VR256:$ins))>;
8183 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8184 (bc_v4i32 (loadv2i64 addr:$src2)),
8186 (VINSERTF128rm VR256:$src1, addr:$src2,
8187 (INSERT_get_vinsert128_imm VR256:$ins))>;
8188 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8189 (bc_v16i8 (loadv2i64 addr:$src2)),
8191 (VINSERTF128rm VR256:$src1, addr:$src2,
8192 (INSERT_get_vinsert128_imm VR256:$ins))>;
8193 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8194 (bc_v8i16 (loadv2i64 addr:$src2)),
8196 (VINSERTF128rm VR256:$src1, addr:$src2,
8197 (INSERT_get_vinsert128_imm VR256:$ins))>;
8200 //===----------------------------------------------------------------------===//
8201 // VEXTRACTF128 - Extract packed floating-point values
8203 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
8204 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
8205 (ins VR256:$src1, i8imm:$src2),
8206 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8207 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
8209 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
8210 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
8211 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8212 []>, Sched<[WriteStore]>, VEX, VEX_L;
8216 let Predicates = [HasAVX] in {
8217 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8218 (v4f32 (VEXTRACTF128rr
8219 (v8f32 VR256:$src1),
8220 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8221 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8222 (v2f64 (VEXTRACTF128rr
8223 (v4f64 VR256:$src1),
8224 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8226 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
8227 (iPTR imm))), addr:$dst),
8228 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8229 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8230 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
8231 (iPTR imm))), addr:$dst),
8232 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8233 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8236 let Predicates = [HasAVX1Only] in {
8237 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8238 (v2i64 (VEXTRACTF128rr
8239 (v4i64 VR256:$src1),
8240 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8241 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8242 (v4i32 (VEXTRACTF128rr
8243 (v8i32 VR256:$src1),
8244 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8245 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8246 (v8i16 (VEXTRACTF128rr
8247 (v16i16 VR256:$src1),
8248 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8249 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8250 (v16i8 (VEXTRACTF128rr
8251 (v32i8 VR256:$src1),
8252 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8254 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8255 (iPTR imm))), addr:$dst),
8256 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8257 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8258 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8259 (iPTR imm))), addr:$dst),
8260 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8261 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8262 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8263 (iPTR imm))), addr:$dst),
8264 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8265 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8266 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8267 (iPTR imm))), addr:$dst),
8268 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8269 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8272 //===----------------------------------------------------------------------===//
8273 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8275 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8276 Intrinsic IntLd, Intrinsic IntLd256,
8277 Intrinsic IntSt, Intrinsic IntSt256> {
8278 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8279 (ins VR128:$src1, f128mem:$src2),
8280 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8281 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8283 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8284 (ins VR256:$src1, f256mem:$src2),
8285 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8286 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8288 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8289 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8290 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8291 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8292 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8293 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8294 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8295 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8298 let ExeDomain = SSEPackedSingle in
8299 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8300 int_x86_avx_maskload_ps,
8301 int_x86_avx_maskload_ps_256,
8302 int_x86_avx_maskstore_ps,
8303 int_x86_avx_maskstore_ps_256>;
8304 let ExeDomain = SSEPackedDouble in
8305 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8306 int_x86_avx_maskload_pd,
8307 int_x86_avx_maskload_pd_256,
8308 int_x86_avx_maskstore_pd,
8309 int_x86_avx_maskstore_pd_256>;
8311 //===----------------------------------------------------------------------===//
8312 // VPERMIL - Permute Single and Double Floating-Point Values
8314 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8315 RegisterClass RC, X86MemOperand x86memop_f,
8316 X86MemOperand x86memop_i, PatFrag i_frag,
8317 Intrinsic IntVar, ValueType vt> {
8318 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8319 (ins RC:$src1, RC:$src2),
8320 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8321 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8322 Sched<[WriteFShuffle]>;
8323 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8324 (ins RC:$src1, x86memop_i:$src2),
8325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8326 [(set RC:$dst, (IntVar RC:$src1,
8327 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8328 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8330 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8331 (ins RC:$src1, i8imm:$src2),
8332 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8333 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8334 Sched<[WriteFShuffle]>;
8335 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8336 (ins x86memop_f:$src1, i8imm:$src2),
8337 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8339 (vt (X86VPermilpi (memop addr:$src1), (i8 imm:$src2))))]>, VEX,
8340 Sched<[WriteFShuffleLd]>;
8343 let ExeDomain = SSEPackedSingle in {
8344 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8345 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8346 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8347 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8349 let ExeDomain = SSEPackedDouble in {
8350 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8351 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8352 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8353 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8356 let Predicates = [HasAVX] in {
8357 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8358 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8359 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8360 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8361 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8362 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8363 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8364 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8366 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8367 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8368 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8369 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8370 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8372 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8373 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8374 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8376 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8377 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8378 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8379 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8380 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8381 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8382 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8383 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8385 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8386 (VPERMILPDri VR128:$src1, imm:$imm)>;
8387 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8388 (VPERMILPDmi addr:$src1, imm:$imm)>;
8391 //===----------------------------------------------------------------------===//
8392 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8394 let ExeDomain = SSEPackedSingle in {
8395 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8396 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8397 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8398 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8399 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8400 Sched<[WriteFShuffle]>;
8401 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8402 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8403 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8404 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8405 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8406 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8409 let Predicates = [HasAVX] in {
8410 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8411 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8412 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8413 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8414 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8417 let Predicates = [HasAVX1Only] in {
8418 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8419 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8420 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8421 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8422 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8423 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8424 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8425 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8427 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8428 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8429 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8430 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8431 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8432 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8433 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8434 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8435 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8436 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8437 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8438 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8441 //===----------------------------------------------------------------------===//
8442 // VZERO - Zero YMM registers
8444 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8445 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8446 // Zero All YMM registers
8447 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8448 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8450 // Zero Upper bits of YMM registers
8451 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8452 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8455 //===----------------------------------------------------------------------===//
8456 // Half precision conversion instructions
8457 //===----------------------------------------------------------------------===//
8458 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8459 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8460 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8461 [(set RC:$dst, (Int VR128:$src))]>,
8462 T8PD, VEX, Sched<[WriteCvtF2F]>;
8463 let hasSideEffects = 0, mayLoad = 1 in
8464 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8465 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8466 Sched<[WriteCvtF2FLd]>;
8469 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8470 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8471 (ins RC:$src1, i32i8imm:$src2),
8472 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8473 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8474 TAPD, VEX, Sched<[WriteCvtF2F]>;
8475 let hasSideEffects = 0, mayStore = 1,
8476 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8477 def mr : Ii8<0x1D, MRMDestMem, (outs),
8478 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8479 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8483 let Predicates = [HasF16C] in {
8484 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8485 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8486 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8487 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8489 // Pattern match vcvtph2ps of a scalar i64 load.
8490 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8491 (VCVTPH2PSrm addr:$src)>;
8492 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8493 (VCVTPH2PSrm addr:$src)>;
8496 // Patterns for matching conversions from float to half-float and vice versa.
8497 let Predicates = [HasF16C] in {
8498 def : Pat<(fp_to_f16 FR32:$src),
8499 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8500 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8502 def : Pat<(f16_to_fp GR16:$src),
8503 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8504 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8506 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8507 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8508 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8511 //===----------------------------------------------------------------------===//
8512 // AVX2 Instructions
8513 //===----------------------------------------------------------------------===//
8515 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8516 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8517 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8518 X86MemOperand x86memop> {
8519 let isCommutable = 1 in
8520 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8521 (ins RC:$src1, RC:$src2, i8imm:$src3),
8522 !strconcat(OpcodeStr,
8523 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8524 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8525 Sched<[WriteBlend]>, VEX_4V;
8526 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8527 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
8528 !strconcat(OpcodeStr,
8529 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8532 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8533 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8536 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8537 VR128, loadv2i64, i128mem>;
8538 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8539 VR256, loadv4i64, i256mem>, VEX_L;
8541 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8543 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8544 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8546 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8548 //===----------------------------------------------------------------------===//
8549 // VPBROADCAST - Load from memory and broadcast to all elements of the
8550 // destination operand
8552 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8553 X86MemOperand x86memop, PatFrag ld_frag,
8554 Intrinsic Int128, Intrinsic Int256> {
8555 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8556 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8557 [(set VR128:$dst, (Int128 VR128:$src))]>,
8558 Sched<[WriteShuffle]>, VEX;
8559 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8560 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8562 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8563 Sched<[WriteLoad]>, VEX;
8564 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8565 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8566 [(set VR256:$dst, (Int256 VR128:$src))]>,
8567 Sched<[WriteShuffle256]>, VEX, VEX_L;
8568 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8569 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8571 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8572 Sched<[WriteLoad]>, VEX, VEX_L;
8575 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8576 int_x86_avx2_pbroadcastb_128,
8577 int_x86_avx2_pbroadcastb_256>;
8578 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8579 int_x86_avx2_pbroadcastw_128,
8580 int_x86_avx2_pbroadcastw_256>;
8581 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8582 int_x86_avx2_pbroadcastd_128,
8583 int_x86_avx2_pbroadcastd_256>;
8584 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8585 int_x86_avx2_pbroadcastq_128,
8586 int_x86_avx2_pbroadcastq_256>;
8588 let Predicates = [HasAVX2] in {
8589 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8590 (VPBROADCASTBrm addr:$src)>;
8591 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8592 (VPBROADCASTBYrm addr:$src)>;
8593 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8594 (VPBROADCASTWrm addr:$src)>;
8595 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8596 (VPBROADCASTWYrm addr:$src)>;
8597 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8598 (VPBROADCASTDrm addr:$src)>;
8599 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8600 (VPBROADCASTDYrm addr:$src)>;
8601 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8602 (VPBROADCASTQrm addr:$src)>;
8603 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8604 (VPBROADCASTQYrm addr:$src)>;
8606 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8607 (VPBROADCASTBrr VR128:$src)>;
8608 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8609 (VPBROADCASTBYrr VR128:$src)>;
8610 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8611 (VPBROADCASTWrr VR128:$src)>;
8612 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8613 (VPBROADCASTWYrr VR128:$src)>;
8614 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8615 (VPBROADCASTDrr VR128:$src)>;
8616 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8617 (VPBROADCASTDYrr VR128:$src)>;
8618 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8619 (VPBROADCASTQrr VR128:$src)>;
8620 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8621 (VPBROADCASTQYrr VR128:$src)>;
8622 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8623 (VBROADCASTSSrr VR128:$src)>;
8624 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8625 (VBROADCASTSSYrr VR128:$src)>;
8626 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8627 (VPBROADCASTQrr VR128:$src)>;
8628 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8629 (VBROADCASTSDYrr VR128:$src)>;
8631 // Provide aliases for broadcast from the same regitser class that
8632 // automatically does the extract.
8633 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8634 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8636 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8637 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8639 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8640 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8642 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8643 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8645 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8646 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8648 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8649 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8652 // Provide fallback in case the load node that is used in the patterns above
8653 // is used by additional users, which prevents the pattern selection.
8654 let AddedComplexity = 20 in {
8655 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8656 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8657 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8658 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8659 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8660 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8662 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8663 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8664 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8665 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8666 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8667 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8669 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8670 (VPBROADCASTBrr (COPY_TO_REGCLASS
8671 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8673 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8674 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8675 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8678 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8679 (VPBROADCASTWrr (COPY_TO_REGCLASS
8680 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8682 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8683 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8684 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8687 // The patterns for VPBROADCASTD are not needed because they would match
8688 // the exact same thing as VBROADCASTSS patterns.
8690 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8691 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8692 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8696 // AVX1 broadcast patterns
8697 let Predicates = [HasAVX1Only] in {
8698 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8699 (VBROADCASTSSYrm addr:$src)>;
8700 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8701 (VBROADCASTSDYrm addr:$src)>;
8702 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8703 (VBROADCASTSSrm addr:$src)>;
8706 let Predicates = [HasAVX] in {
8707 // Provide fallback in case the load node that is used in the patterns above
8708 // is used by additional users, which prevents the pattern selection.
8709 let AddedComplexity = 20 in {
8710 // 128bit broadcasts:
8711 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8712 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8713 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8714 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8715 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8716 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8717 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8718 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8719 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8720 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8722 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8723 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8724 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8725 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8726 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8727 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8728 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8729 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8730 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8731 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8734 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8735 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8738 //===----------------------------------------------------------------------===//
8739 // VPERM - Permute instructions
8742 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8743 ValueType OpVT, X86FoldableSchedWrite Sched> {
8744 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8745 (ins VR256:$src1, VR256:$src2),
8746 !strconcat(OpcodeStr,
8747 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8749 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8750 Sched<[Sched]>, VEX_4V, VEX_L;
8751 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8752 (ins VR256:$src1, i256mem:$src2),
8753 !strconcat(OpcodeStr,
8754 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8756 (OpVT (X86VPermv VR256:$src1,
8757 (bitconvert (mem_frag addr:$src2)))))]>,
8758 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8761 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8762 let ExeDomain = SSEPackedSingle in
8763 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8765 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8766 ValueType OpVT, X86FoldableSchedWrite Sched> {
8767 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8768 (ins VR256:$src1, i8imm:$src2),
8769 !strconcat(OpcodeStr,
8770 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8772 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8773 Sched<[Sched]>, VEX, VEX_L;
8774 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8775 (ins i256mem:$src1, i8imm:$src2),
8776 !strconcat(OpcodeStr,
8777 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8779 (OpVT (X86VPermi (mem_frag addr:$src1),
8780 (i8 imm:$src2))))]>,
8781 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8784 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8785 WriteShuffle256>, VEX_W;
8786 let ExeDomain = SSEPackedDouble in
8787 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8788 WriteFShuffle256>, VEX_W;
8790 //===----------------------------------------------------------------------===//
8791 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8793 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8794 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8795 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8796 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8797 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8799 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8800 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8801 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8802 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8804 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8806 let Predicates = [HasAVX2] in {
8807 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8808 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8809 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8810 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8811 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8812 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8814 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8816 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8817 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8818 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8819 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8820 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8822 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8826 //===----------------------------------------------------------------------===//
8827 // VINSERTI128 - Insert packed integer values
8829 let hasSideEffects = 0 in {
8830 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8831 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8832 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8833 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8835 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8836 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8837 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8838 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8841 let Predicates = [HasAVX2] in {
8842 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8844 (VINSERTI128rr VR256:$src1, VR128:$src2,
8845 (INSERT_get_vinsert128_imm VR256:$ins))>;
8846 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8848 (VINSERTI128rr VR256:$src1, VR128:$src2,
8849 (INSERT_get_vinsert128_imm VR256:$ins))>;
8850 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8852 (VINSERTI128rr VR256:$src1, VR128:$src2,
8853 (INSERT_get_vinsert128_imm VR256:$ins))>;
8854 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8856 (VINSERTI128rr VR256:$src1, VR128:$src2,
8857 (INSERT_get_vinsert128_imm VR256:$ins))>;
8859 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8861 (VINSERTI128rm VR256:$src1, addr:$src2,
8862 (INSERT_get_vinsert128_imm VR256:$ins))>;
8863 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8864 (bc_v4i32 (loadv2i64 addr:$src2)),
8866 (VINSERTI128rm VR256:$src1, addr:$src2,
8867 (INSERT_get_vinsert128_imm VR256:$ins))>;
8868 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8869 (bc_v16i8 (loadv2i64 addr:$src2)),
8871 (VINSERTI128rm VR256:$src1, addr:$src2,
8872 (INSERT_get_vinsert128_imm VR256:$ins))>;
8873 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8874 (bc_v8i16 (loadv2i64 addr:$src2)),
8876 (VINSERTI128rm VR256:$src1, addr:$src2,
8877 (INSERT_get_vinsert128_imm VR256:$ins))>;
8880 //===----------------------------------------------------------------------===//
8881 // VEXTRACTI128 - Extract packed integer values
8883 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8884 (ins VR256:$src1, i8imm:$src2),
8885 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8887 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8888 Sched<[WriteShuffle256]>, VEX, VEX_L;
8889 let hasSideEffects = 0, mayStore = 1 in
8890 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8891 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8892 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8893 Sched<[WriteStore]>, VEX, VEX_L;
8895 let Predicates = [HasAVX2] in {
8896 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8897 (v2i64 (VEXTRACTI128rr
8898 (v4i64 VR256:$src1),
8899 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8900 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8901 (v4i32 (VEXTRACTI128rr
8902 (v8i32 VR256:$src1),
8903 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8904 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8905 (v8i16 (VEXTRACTI128rr
8906 (v16i16 VR256:$src1),
8907 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8908 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8909 (v16i8 (VEXTRACTI128rr
8910 (v32i8 VR256:$src1),
8911 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8913 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8914 (iPTR imm))), addr:$dst),
8915 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8916 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8917 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8918 (iPTR imm))), addr:$dst),
8919 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8920 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8921 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8922 (iPTR imm))), addr:$dst),
8923 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8924 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8925 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8926 (iPTR imm))), addr:$dst),
8927 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8928 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8931 //===----------------------------------------------------------------------===//
8932 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8934 multiclass avx2_pmovmask<string OpcodeStr,
8935 Intrinsic IntLd128, Intrinsic IntLd256,
8936 Intrinsic IntSt128, Intrinsic IntSt256> {
8937 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8938 (ins VR128:$src1, i128mem:$src2),
8939 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8940 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8941 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8942 (ins VR256:$src1, i256mem:$src2),
8943 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8944 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8946 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8947 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8948 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8949 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8950 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8951 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8952 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8953 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8956 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8957 int_x86_avx2_maskload_d,
8958 int_x86_avx2_maskload_d_256,
8959 int_x86_avx2_maskstore_d,
8960 int_x86_avx2_maskstore_d_256>;
8961 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8962 int_x86_avx2_maskload_q,
8963 int_x86_avx2_maskload_q_256,
8964 int_x86_avx2_maskstore_q,
8965 int_x86_avx2_maskstore_q_256>, VEX_W;
8967 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8968 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8970 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8971 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8973 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8974 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8976 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8977 (bc_v8f32 (v8i32 immAllZerosV)))),
8978 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8980 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8981 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8984 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8985 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8987 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8988 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8990 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8991 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8994 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8995 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8997 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8998 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
9000 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
9001 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9003 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
9004 (v4f64 immAllZerosV))),
9005 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9007 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
9008 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
9011 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
9012 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9014 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
9015 (bc_v4i64 (v8i32 immAllZerosV)))),
9016 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
9018 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
9019 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
9023 //===----------------------------------------------------------------------===//
9024 // Variable Bit Shifts
9026 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
9027 ValueType vt128, ValueType vt256> {
9028 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
9029 (ins VR128:$src1, VR128:$src2),
9030 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9032 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
9033 VEX_4V, Sched<[WriteVarVecShift]>;
9034 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
9035 (ins VR128:$src1, i128mem:$src2),
9036 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9038 (vt128 (OpNode VR128:$src1,
9039 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
9040 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9041 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
9042 (ins VR256:$src1, VR256:$src2),
9043 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9045 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
9046 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
9047 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
9048 (ins VR256:$src1, i256mem:$src2),
9049 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9051 (vt256 (OpNode VR256:$src1,
9052 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
9053 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9056 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
9057 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
9058 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
9059 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
9060 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
9062 //===----------------------------------------------------------------------===//
9063 // VGATHER - GATHER Operations
9064 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
9065 X86MemOperand memop128, X86MemOperand memop256> {
9066 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
9067 (ins VR128:$src1, memop128:$src2, VR128:$mask),
9068 !strconcat(OpcodeStr,
9069 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9071 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
9072 (ins RC256:$src1, memop256:$src2, RC256:$mask),
9073 !strconcat(OpcodeStr,
9074 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9075 []>, VEX_4VOp3, VEX_L;
9078 let mayLoad = 1, Constraints
9079 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
9081 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
9082 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
9083 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
9084 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
9086 let ExeDomain = SSEPackedDouble in {
9087 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
9088 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
9091 let ExeDomain = SSEPackedSingle in {
9092 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
9093 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;