1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 def SSE_BIT_ITINS_P : OpndItins<
124 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
127 let Sched = WriteVecALU in {
128 def SSE_INTALU_ITINS_P : OpndItins<
129 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
132 def SSE_INTALUQ_ITINS_P : OpndItins<
133 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
137 let Sched = WriteVecIMul in
138 def SSE_INTMUL_ITINS_P : OpndItins<
139 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
142 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
143 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
146 def SSE_MOVA_ITINS : OpndItins<
147 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
150 def SSE_MOVU_ITINS : OpndItins<
151 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
154 def SSE_DPPD_ITINS : OpndItins<
155 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
158 def SSE_DPPS_ITINS : OpndItins<
159 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
162 def DEFAULT_ITINS : OpndItins<
163 IIC_ALU_NONMEM, IIC_ALU_MEM
166 def SSE_EXTRACT_ITINS : OpndItins<
167 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
170 def SSE_INSERT_ITINS : OpndItins<
171 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
174 def SSE_MPSADBW_ITINS : OpndItins<
175 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
178 def SSE_PMULLD_ITINS : OpndItins<
179 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
182 //===----------------------------------------------------------------------===//
183 // SSE 1 & 2 Instructions Classes
184 //===----------------------------------------------------------------------===//
186 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
187 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
188 RegisterClass RC, X86MemOperand x86memop,
191 let isCommutable = 1 in {
192 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
194 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
196 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
197 Sched<[itins.Sched]>;
199 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
201 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
203 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
204 Sched<[itins.Sched.Folded, ReadAfterLd]>;
207 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
208 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
209 string asm, string SSEVer, string FPSizeStr,
210 Operand memopr, ComplexPattern mem_cpat,
213 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
215 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
216 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
217 [(set RC:$dst, (!cast<Intrinsic>(
218 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
219 RC:$src1, RC:$src2))], itins.rr>,
220 Sched<[itins.Sched]>;
221 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
223 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
224 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
225 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
226 SSEVer, "_", OpcodeStr, FPSizeStr))
227 RC:$src1, mem_cpat:$src2))], itins.rm>,
228 Sched<[itins.Sched.Folded, ReadAfterLd]>;
231 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
232 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
233 RegisterClass RC, ValueType vt,
234 X86MemOperand x86memop, PatFrag mem_frag,
235 Domain d, OpndItins itins, bit Is2Addr = 1> {
236 let isCommutable = 1 in
237 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
241 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
242 Sched<[itins.Sched]>;
244 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
246 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
247 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
248 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
250 Sched<[itins.Sched.Folded, ReadAfterLd]>;
253 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
254 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
255 string OpcodeStr, X86MemOperand x86memop,
256 list<dag> pat_rr, list<dag> pat_rm,
258 let isCommutable = 1, hasSideEffects = 0 in
259 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
261 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
262 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
263 pat_rr, NoItinerary, d>,
264 Sched<[WriteVecLogic]>;
265 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
267 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
269 pat_rm, NoItinerary, d>,
270 Sched<[WriteVecLogicLd, ReadAfterLd]>;
273 //===----------------------------------------------------------------------===//
274 // Non-instruction patterns
275 //===----------------------------------------------------------------------===//
277 // A vector extract of the first f32/f64 position is a subregister copy
278 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
279 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
280 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
281 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
283 // A 128-bit subvector extract from the first 256-bit vector position
284 // is a subregister copy that needs no instruction.
285 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
286 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
287 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
288 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
290 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
291 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
292 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
293 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
295 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
296 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
297 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
298 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
300 // A 128-bit subvector insert to the first 256-bit vector position
301 // is a subregister copy that needs no instruction.
302 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
303 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
304 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
305 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
306 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
307 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
308 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
309 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
310 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
311 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
312 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
313 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
314 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
317 // Implicitly promote a 32-bit scalar to a vector.
318 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
319 (COPY_TO_REGCLASS FR32:$src, VR128)>;
320 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
321 (COPY_TO_REGCLASS FR32:$src, VR128)>;
322 // Implicitly promote a 64-bit scalar to a vector.
323 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
324 (COPY_TO_REGCLASS FR64:$src, VR128)>;
325 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
326 (COPY_TO_REGCLASS FR64:$src, VR128)>;
328 // Bitcasts between 128-bit vector types. Return the original type since
329 // no instruction is needed for the conversion
330 let Predicates = [HasSSE2] in {
331 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
332 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
333 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
334 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
335 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
336 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
337 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
338 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
339 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
340 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
341 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
342 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
343 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
344 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
345 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
346 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
347 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
348 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
349 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
350 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
351 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
352 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
353 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
354 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
355 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
356 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
357 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
358 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
359 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
360 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
363 // Bitcasts between 256-bit vector types. Return the original type since
364 // no instruction is needed for the conversion
365 let Predicates = [HasAVX] in {
366 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
367 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
368 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
369 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
370 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
371 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
372 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
373 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
374 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
375 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
376 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
377 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
378 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
379 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
380 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
381 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
382 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
383 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
384 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
385 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
386 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
387 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
388 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
389 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
390 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
391 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
392 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
393 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
394 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
395 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
398 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
399 // This is expanded by ExpandPostRAPseudos.
400 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
401 isPseudo = 1, SchedRW = [WriteZero] in {
402 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
403 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
404 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
405 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
408 //===----------------------------------------------------------------------===//
409 // AVX & SSE - Zero/One Vectors
410 //===----------------------------------------------------------------------===//
412 // Alias instruction that maps zero vector to pxor / xorp* for sse.
413 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
414 // swizzled by ExecutionDepsFix to pxor.
415 // We set canFoldAsLoad because this can be converted to a constant-pool
416 // load of an all-zeros value if folding it would be beneficial.
417 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
418 isPseudo = 1, SchedRW = [WriteZero] in {
419 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
420 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
423 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
424 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
425 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
426 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
427 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
430 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
431 // and doesn't need it because on sandy bridge the register is set to zero
432 // at the rename stage without using any execution unit, so SET0PSY
433 // and SET0PDY can be used for vector int instructions without penalty
434 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
435 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
436 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
437 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
440 let Predicates = [HasAVX] in
441 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
443 let Predicates = [HasAVX2] in {
444 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
445 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
446 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
447 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
450 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
451 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
452 let Predicates = [HasAVX1Only] in {
453 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
454 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
455 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
457 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
458 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
459 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
461 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
462 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
463 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
465 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
466 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
467 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-ones value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
476 let Predicates = [HasAVX2] in
477 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
478 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
482 //===----------------------------------------------------------------------===//
483 // SSE 1 & 2 - Move FP Scalar Instructions
485 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
486 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
487 // is used instead. Register-to-register movss/movsd is not modeled as an
488 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
489 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
490 //===----------------------------------------------------------------------===//
492 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
493 X86MemOperand x86memop, string base_opc,
495 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
496 (ins VR128:$src1, RC:$src2),
497 !strconcat(base_opc, asm_opr),
498 [(set VR128:$dst, (vt (OpNode VR128:$src1,
499 (scalar_to_vector RC:$src2))))],
500 IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
502 // For the disassembler
503 let isCodeGenOnly = 1, hasSideEffects = 0 in
504 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
505 (ins VR128:$src1, RC:$src2),
506 !strconcat(base_opc, asm_opr),
507 [], IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
510 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
511 X86MemOperand x86memop, string OpcodeStr> {
513 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
514 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
517 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
519 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
520 VEX, VEX_LIG, Sched<[WriteStore]>;
522 let Constraints = "$src1 = $dst" in {
523 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
524 "\t{$src2, $dst|$dst, $src2}">;
527 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
528 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
529 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
533 // Loading from memory automatically zeroing upper bits.
534 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
535 PatFrag mem_pat, string OpcodeStr> {
536 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
538 [(set RC:$dst, (mem_pat addr:$src))],
539 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
540 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
541 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
542 [(set RC:$dst, (mem_pat addr:$src))],
543 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
546 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
547 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
549 let canFoldAsLoad = 1, isReMaterializable = 1 in {
550 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
552 let AddedComplexity = 20 in
553 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
557 let Predicates = [UseAVX] in {
558 let AddedComplexity = 15 in {
559 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
560 // MOVS{S,D} to the lower bits.
561 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
562 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
563 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
564 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
565 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
566 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
567 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
568 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
570 // Move low f32 and clear high bits.
571 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
572 (SUBREG_TO_REG (i32 0),
573 (VMOVSSrr (v4f32 (V_SET0)),
574 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
575 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
576 (SUBREG_TO_REG (i32 0),
577 (VMOVSSrr (v4i32 (V_SET0)),
578 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
581 let AddedComplexity = 20 in {
582 // MOVSSrm zeros the high parts of the register; represent this
583 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
584 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
585 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
586 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
587 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
588 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
589 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
591 // MOVSDrm zeros the high parts of the register; represent this
592 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
593 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
594 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
595 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
596 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
597 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
598 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
599 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
600 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
601 def : Pat<(v2f64 (X86vzload addr:$src)),
602 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
604 // Represent the same patterns above but in the form they appear for
606 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
607 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
608 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
609 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
610 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
612 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
613 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
616 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
617 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
618 (SUBREG_TO_REG (i32 0),
619 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
621 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
622 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
623 (SUBREG_TO_REG (i64 0),
624 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
626 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
627 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
628 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
630 // Move low f64 and clear high bits.
631 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
632 (SUBREG_TO_REG (i32 0),
633 (VMOVSDrr (v2f64 (V_SET0)),
634 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
636 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
637 (SUBREG_TO_REG (i32 0),
638 (VMOVSDrr (v2i64 (V_SET0)),
639 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
641 // Extract and store.
642 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
644 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
645 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
647 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
649 // Shuffle with VMOVSS
650 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
651 (VMOVSSrr (v4i32 VR128:$src1),
652 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
653 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
654 (VMOVSSrr (v4f32 VR128:$src1),
655 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
658 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
659 (SUBREG_TO_REG (i32 0),
660 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
661 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
663 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
666 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
669 // Shuffle with VMOVSD
670 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
671 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
674 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
675 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
676 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
680 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
681 (SUBREG_TO_REG (i32 0),
682 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
683 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
685 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
686 (SUBREG_TO_REG (i32 0),
687 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
688 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
692 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
693 // is during lowering, where it's not possible to recognize the fold cause
694 // it has two uses through a bitcast. One use disappears at isel time and the
695 // fold opportunity reappears.
696 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
697 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
698 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
699 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
700 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
701 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
702 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
703 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
706 let Predicates = [UseSSE1] in {
707 let AddedComplexity = 15 in {
708 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
709 // MOVSS to the lower bits.
710 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
711 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
712 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
713 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
714 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
715 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
718 let AddedComplexity = 20 in {
719 // MOVSSrm already zeros the high parts of the register.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
721 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
722 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
723 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
724 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
728 // Extract and store.
729 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
731 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
733 // Shuffle with MOVSS
734 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
735 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
736 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
737 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
740 let Predicates = [UseSSE2] in {
741 let AddedComplexity = 15 in {
742 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
743 // MOVSD to the lower bits.
744 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
745 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
748 let AddedComplexity = 20 in {
749 // MOVSDrm already zeros the high parts of the register.
750 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
751 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
752 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
753 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
754 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
755 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
756 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
757 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
758 def : Pat<(v2f64 (X86vzload addr:$src)),
759 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 // Extract and store.
763 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
765 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
767 // Shuffle with MOVSD
768 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
769 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
770 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
771 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
772 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
773 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
774 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
775 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
777 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
778 // is during lowering, where it's not possible to recognize the fold cause
779 // it has two uses through a bitcast. One use disappears at isel time and the
780 // fold opportunity reappears.
781 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
782 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
783 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
784 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
785 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
786 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
788 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
791 //===----------------------------------------------------------------------===//
792 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
793 //===----------------------------------------------------------------------===//
795 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
796 X86MemOperand x86memop, PatFrag ld_frag,
797 string asm, Domain d,
799 bit IsReMaterializable = 1> {
800 let neverHasSideEffects = 1 in
801 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
802 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
804 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
805 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
806 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
807 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
811 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
812 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
814 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
815 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
817 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
818 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
820 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
821 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
824 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
825 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
828 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
829 TB, OpSize, VEX, VEX_L;
830 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
831 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
834 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 TB, OpSize, VEX, VEX_L;
836 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
837 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
839 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
840 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
842 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
843 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
845 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
846 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let SchedRW = [WriteStore] in {
850 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
851 "movaps\t{$src, $dst|$dst, $src}",
852 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
853 IIC_SSE_MOVA_P_MR>, VEX;
854 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
855 "movapd\t{$src, $dst|$dst, $src}",
856 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
857 IIC_SSE_MOVA_P_MR>, VEX;
858 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
859 "movups\t{$src, $dst|$dst, $src}",
860 [(store (v4f32 VR128:$src), addr:$dst)],
861 IIC_SSE_MOVU_P_MR>, VEX;
862 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
863 "movupd\t{$src, $dst|$dst, $src}",
864 [(store (v2f64 VR128:$src), addr:$dst)],
865 IIC_SSE_MOVU_P_MR>, VEX;
866 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
870 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
874 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v8f32 VR256:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
878 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v4f64 VR256:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
885 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
886 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
888 "movaps\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVA_P_RR>, VEX;
890 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
892 "movapd\t{$src, $dst|$dst, $src}", [],
893 IIC_SSE_MOVA_P_RR>, VEX;
894 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
896 "movups\t{$src, $dst|$dst, $src}", [],
897 IIC_SSE_MOVU_P_RR>, VEX;
898 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
900 "movupd\t{$src, $dst|$dst, $src}", [],
901 IIC_SSE_MOVU_P_RR>, VEX;
902 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
904 "movaps\t{$src, $dst|$dst, $src}", [],
905 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
906 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
908 "movapd\t{$src, $dst|$dst, $src}", [],
909 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
910 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
912 "movups\t{$src, $dst|$dst, $src}", [],
913 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
914 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
916 "movupd\t{$src, $dst|$dst, $src}", [],
917 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
920 let Predicates = [HasAVX] in {
921 def : Pat<(v8i32 (X86vzmovl
922 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
923 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
924 def : Pat<(v4i64 (X86vzmovl
925 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
926 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
927 def : Pat<(v8f32 (X86vzmovl
928 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
929 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
930 def : Pat<(v4f64 (X86vzmovl
931 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
932 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
936 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
937 (VMOVUPSYmr addr:$dst, VR256:$src)>;
938 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
939 (VMOVUPDYmr addr:$dst, VR256:$src)>;
941 let SchedRW = [WriteStore] in {
942 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
943 "movaps\t{$src, $dst|$dst, $src}",
944 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
946 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
947 "movapd\t{$src, $dst|$dst, $src}",
948 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
950 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
951 "movups\t{$src, $dst|$dst, $src}",
952 [(store (v4f32 VR128:$src), addr:$dst)],
954 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
955 "movupd\t{$src, $dst|$dst, $src}",
956 [(store (v2f64 VR128:$src), addr:$dst)],
961 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
962 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
963 "movaps\t{$src, $dst|$dst, $src}", [],
965 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
966 "movapd\t{$src, $dst|$dst, $src}", [],
968 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}", [],
971 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
972 "movupd\t{$src, $dst|$dst, $src}", [],
976 let Predicates = [HasAVX] in {
977 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
978 (VMOVUPSmr addr:$dst, VR128:$src)>;
979 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
980 (VMOVUPDmr addr:$dst, VR128:$src)>;
983 let Predicates = [UseSSE1] in
984 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
985 (MOVUPSmr addr:$dst, VR128:$src)>;
986 let Predicates = [UseSSE2] in
987 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
988 (MOVUPDmr addr:$dst, VR128:$src)>;
990 // Use vmovaps/vmovups for AVX integer load/store.
991 let Predicates = [HasAVX] in {
992 // 128-bit load/store
993 def : Pat<(alignedloadv2i64 addr:$src),
994 (VMOVAPSrm addr:$src)>;
995 def : Pat<(loadv2i64 addr:$src),
996 (VMOVUPSrm addr:$src)>;
998 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
999 (VMOVAPSmr addr:$dst, VR128:$src)>;
1000 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1001 (VMOVAPSmr addr:$dst, VR128:$src)>;
1002 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1003 (VMOVAPSmr addr:$dst, VR128:$src)>;
1004 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1005 (VMOVAPSmr addr:$dst, VR128:$src)>;
1006 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1007 (VMOVUPSmr addr:$dst, VR128:$src)>;
1008 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1009 (VMOVUPSmr addr:$dst, VR128:$src)>;
1010 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1011 (VMOVUPSmr addr:$dst, VR128:$src)>;
1012 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1013 (VMOVUPSmr addr:$dst, VR128:$src)>;
1015 // 256-bit load/store
1016 def : Pat<(alignedloadv4i64 addr:$src),
1017 (VMOVAPSYrm addr:$src)>;
1018 def : Pat<(loadv4i64 addr:$src),
1019 (VMOVUPSYrm addr:$src)>;
1020 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1021 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1022 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1023 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1024 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1025 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1026 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1027 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1028 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1029 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1030 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1031 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1032 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1033 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1034 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1035 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1037 // Special patterns for storing subvector extracts of lower 128-bits
1038 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1039 def : Pat<(alignedstore (v2f64 (extract_subvector
1040 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1041 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1042 def : Pat<(alignedstore (v4f32 (extract_subvector
1043 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1044 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1045 def : Pat<(alignedstore (v2i64 (extract_subvector
1046 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1047 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1048 def : Pat<(alignedstore (v4i32 (extract_subvector
1049 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1050 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1051 def : Pat<(alignedstore (v8i16 (extract_subvector
1052 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1053 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1054 def : Pat<(alignedstore (v16i8 (extract_subvector
1055 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1056 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1058 def : Pat<(store (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(store (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(store (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(store (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(store (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(store (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1078 // Use movaps / movups for SSE integer load / store (one byte shorter).
1079 // The instructions selected below are then converted to MOVDQA/MOVDQU
1080 // during the SSE domain pass.
1081 let Predicates = [UseSSE1] in {
1082 def : Pat<(alignedloadv2i64 addr:$src),
1083 (MOVAPSrm addr:$src)>;
1084 def : Pat<(loadv2i64 addr:$src),
1085 (MOVUPSrm addr:$src)>;
1087 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1088 (MOVAPSmr addr:$dst, VR128:$src)>;
1089 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1090 (MOVAPSmr addr:$dst, VR128:$src)>;
1091 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1092 (MOVAPSmr addr:$dst, VR128:$src)>;
1093 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1094 (MOVAPSmr addr:$dst, VR128:$src)>;
1095 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1096 (MOVUPSmr addr:$dst, VR128:$src)>;
1097 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1098 (MOVUPSmr addr:$dst, VR128:$src)>;
1099 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1100 (MOVUPSmr addr:$dst, VR128:$src)>;
1101 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1102 (MOVUPSmr addr:$dst, VR128:$src)>;
1105 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1106 // bits are disregarded. FIXME: Set encoding to pseudo!
1107 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
1108 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1109 "movaps\t{$src, $dst|$dst, $src}", [],
1110 IIC_SSE_MOVA_P_RR>, VEX;
1111 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1112 "movapd\t{$src, $dst|$dst, $src}", [],
1113 IIC_SSE_MOVA_P_RR>, VEX;
1114 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1115 "movaps\t{$src, $dst|$dst, $src}", [],
1117 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1118 "movapd\t{$src, $dst|$dst, $src}", [],
1122 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1123 // bits are disregarded. FIXME: Set encoding to pseudo!
1124 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1125 let isCodeGenOnly = 1 in {
1126 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1127 "movaps\t{$src, $dst|$dst, $src}",
1128 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1129 IIC_SSE_MOVA_P_RM>, VEX;
1130 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1131 "movapd\t{$src, $dst|$dst, $src}",
1132 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1133 IIC_SSE_MOVA_P_RM>, VEX;
1135 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1136 "movaps\t{$src, $dst|$dst, $src}",
1137 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1139 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1140 "movapd\t{$src, $dst|$dst, $src}",
1141 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1145 //===----------------------------------------------------------------------===//
1146 // SSE 1 & 2 - Move Low packed FP Instructions
1147 //===----------------------------------------------------------------------===//
1149 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1150 string base_opc, string asm_opr,
1151 InstrItinClass itin> {
1152 def PSrm : PI<opc, MRMSrcMem,
1153 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1154 !strconcat(base_opc, "s", asm_opr),
1156 (psnode VR128:$src1,
1157 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1158 itin, SSEPackedSingle>, TB,
1159 Sched<[WriteShuffleLd, ReadAfterLd]>;
1161 def PDrm : PI<opc, MRMSrcMem,
1162 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1163 !strconcat(base_opc, "d", asm_opr),
1164 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1165 (scalar_to_vector (loadf64 addr:$src2)))))],
1166 itin, SSEPackedDouble>, TB, OpSize,
1167 Sched<[WriteShuffleLd, ReadAfterLd]>;
1171 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1172 string base_opc, InstrItinClass itin> {
1173 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1174 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1177 let Constraints = "$src1 = $dst" in
1178 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1179 "\t{$src2, $dst|$dst, $src2}",
1183 let AddedComplexity = 20 in {
1184 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1188 let SchedRW = [WriteStore] in {
1189 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1190 "movlps\t{$src, $dst|$dst, $src}",
1191 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1192 (iPTR 0))), addr:$dst)],
1193 IIC_SSE_MOV_LH>, VEX;
1194 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1195 "movlpd\t{$src, $dst|$dst, $src}",
1196 [(store (f64 (vector_extract (v2f64 VR128:$src),
1197 (iPTR 0))), addr:$dst)],
1198 IIC_SSE_MOV_LH>, VEX;
1199 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1200 "movlps\t{$src, $dst|$dst, $src}",
1201 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1202 (iPTR 0))), addr:$dst)],
1204 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1205 "movlpd\t{$src, $dst|$dst, $src}",
1206 [(store (f64 (vector_extract (v2f64 VR128:$src),
1207 (iPTR 0))), addr:$dst)],
1211 let Predicates = [HasAVX] in {
1212 // Shuffle with VMOVLPS
1213 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1214 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1215 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1216 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1218 // Shuffle with VMOVLPD
1219 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1220 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1221 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1222 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1227 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1228 def : Pat<(store (v4i32 (X86Movlps
1229 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1230 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1231 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1233 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1234 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1236 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1239 let Predicates = [UseSSE1] in {
1240 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1241 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1242 (iPTR 0))), addr:$src1),
1243 (MOVLPSmr addr:$src1, VR128:$src2)>;
1245 // Shuffle with MOVLPS
1246 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1247 (MOVLPSrm VR128:$src1, addr:$src2)>;
1248 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1249 (MOVLPSrm VR128:$src1, addr:$src2)>;
1250 def : Pat<(X86Movlps VR128:$src1,
1251 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1252 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1257 (MOVLPSmr addr:$src1, VR128:$src2)>;
1258 def : Pat<(store (v4i32 (X86Movlps
1259 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1261 (MOVLPSmr addr:$src1, VR128:$src2)>;
1264 let Predicates = [UseSSE2] in {
1265 // Shuffle with MOVLPD
1266 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1267 (MOVLPDrm VR128:$src1, addr:$src2)>;
1268 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1269 (MOVLPDrm VR128:$src1, addr:$src2)>;
1272 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1274 (MOVLPDmr addr:$src1, VR128:$src2)>;
1275 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1277 (MOVLPDmr addr:$src1, VR128:$src2)>;
1280 //===----------------------------------------------------------------------===//
1281 // SSE 1 & 2 - Move Hi packed FP Instructions
1282 //===----------------------------------------------------------------------===//
1284 let AddedComplexity = 20 in {
1285 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1289 let SchedRW = [WriteStore] in {
1290 // v2f64 extract element 1 is always custom lowered to unpack high to low
1291 // and extract element 0 so the non-store version isn't too horrible.
1292 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1293 "movhps\t{$src, $dst|$dst, $src}",
1294 [(store (f64 (vector_extract
1295 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1296 (bc_v2f64 (v4f32 VR128:$src))),
1297 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1298 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1299 "movhpd\t{$src, $dst|$dst, $src}",
1300 [(store (f64 (vector_extract
1301 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1302 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1303 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1304 "movhps\t{$src, $dst|$dst, $src}",
1305 [(store (f64 (vector_extract
1306 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1307 (bc_v2f64 (v4f32 VR128:$src))),
1308 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1309 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1310 "movhpd\t{$src, $dst|$dst, $src}",
1311 [(store (f64 (vector_extract
1312 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1313 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1316 let Predicates = [HasAVX] in {
1318 def : Pat<(X86Movlhps VR128:$src1,
1319 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1320 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1321 def : Pat<(X86Movlhps VR128:$src1,
1322 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1323 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1325 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1326 // is during lowering, where it's not possible to recognize the load fold
1327 // cause it has two uses through a bitcast. One use disappears at isel time
1328 // and the fold opportunity reappears.
1329 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1330 (scalar_to_vector (loadf64 addr:$src2)))),
1331 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1334 let Predicates = [UseSSE1] in {
1336 def : Pat<(X86Movlhps VR128:$src1,
1337 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1338 (MOVHPSrm VR128:$src1, addr:$src2)>;
1339 def : Pat<(X86Movlhps VR128:$src1,
1340 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1341 (MOVHPSrm VR128:$src1, addr:$src2)>;
1344 let Predicates = [UseSSE2] in {
1345 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1346 // is during lowering, where it's not possible to recognize the load fold
1347 // cause it has two uses through a bitcast. One use disappears at isel time
1348 // and the fold opportunity reappears.
1349 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1350 (scalar_to_vector (loadf64 addr:$src2)))),
1351 (MOVHPDrm VR128:$src1, addr:$src2)>;
1354 //===----------------------------------------------------------------------===//
1355 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1356 //===----------------------------------------------------------------------===//
1358 let AddedComplexity = 20, Predicates = [UseAVX] in {
1359 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1360 (ins VR128:$src1, VR128:$src2),
1361 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1363 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1365 VEX_4V, Sched<[WriteShuffle]>;
1366 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1367 (ins VR128:$src1, VR128:$src2),
1368 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1370 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1372 VEX_4V, Sched<[WriteShuffle]>;
1374 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1375 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1376 (ins VR128:$src1, VR128:$src2),
1377 "movlhps\t{$src2, $dst|$dst, $src2}",
1379 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1380 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1381 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1382 (ins VR128:$src1, VR128:$src2),
1383 "movhlps\t{$src2, $dst|$dst, $src2}",
1385 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1386 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1389 let Predicates = [UseAVX] in {
1391 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1392 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1393 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1394 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1397 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1398 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1401 let Predicates = [UseSSE1] in {
1403 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1404 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1405 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1406 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1409 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1410 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1413 //===----------------------------------------------------------------------===//
1414 // SSE 1 & 2 - Conversion Instructions
1415 //===----------------------------------------------------------------------===//
1417 def SSE_CVT_PD : OpndItins<
1418 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1421 let Sched = WriteCvtI2F in
1422 def SSE_CVT_PS : OpndItins<
1423 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1426 let Sched = WriteCvtI2F in
1427 def SSE_CVT_Scalar : OpndItins<
1428 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1431 let Sched = WriteCvtF2I in
1432 def SSE_CVT_SS2SI_32 : OpndItins<
1433 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1436 let Sched = WriteCvtF2I in
1437 def SSE_CVT_SS2SI_64 : OpndItins<
1438 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1441 let Sched = WriteCvtF2I in
1442 def SSE_CVT_SD2SI : OpndItins<
1443 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1446 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1447 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1448 string asm, OpndItins itins> {
1449 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1450 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1451 itins.rr>, Sched<[itins.Sched]>;
1452 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1453 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1454 itins.rm>, Sched<[itins.Sched.Folded]>;
1457 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1458 X86MemOperand x86memop, string asm, Domain d,
1460 let neverHasSideEffects = 1 in {
1461 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1462 [], itins.rr, d>, Sched<[itins.Sched]>;
1464 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1465 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1469 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1470 X86MemOperand x86memop, string asm> {
1471 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1472 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1473 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1474 Sched<[WriteCvtI2F]>;
1476 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1477 (ins DstRC:$src1, x86memop:$src),
1478 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1479 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1480 } // neverHasSideEffects = 1
1483 let Predicates = [UseAVX] in {
1484 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1485 "cvttss2si\t{$src, $dst|$dst, $src}",
1488 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1489 "cvttss2si\t{$src, $dst|$dst, $src}",
1491 XS, VEX, VEX_W, VEX_LIG;
1492 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1493 "cvttsd2si\t{$src, $dst|$dst, $src}",
1496 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1497 "cvttsd2si\t{$src, $dst|$dst, $src}",
1499 XD, VEX, VEX_W, VEX_LIG;
1501 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1502 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1503 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1504 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1505 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1506 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1507 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1508 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1509 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1510 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1511 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1512 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1513 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1514 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1515 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1516 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1518 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1519 // register, but the same isn't true when only using memory operands,
1520 // provide other assembly "l" and "q" forms to address this explicitly
1521 // where appropriate to do so.
1522 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1523 XS, VEX_4V, VEX_LIG;
1524 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1525 XS, VEX_4V, VEX_W, VEX_LIG;
1526 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1527 XD, VEX_4V, VEX_LIG;
1528 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1529 XD, VEX_4V, VEX_W, VEX_LIG;
1531 let Predicates = [UseAVX] in {
1532 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1533 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1534 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1535 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1537 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1538 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1539 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1540 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1541 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1542 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1543 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1544 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1546 def : Pat<(f32 (sint_to_fp GR32:$src)),
1547 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1548 def : Pat<(f32 (sint_to_fp GR64:$src)),
1549 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1550 def : Pat<(f64 (sint_to_fp GR32:$src)),
1551 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1552 def : Pat<(f64 (sint_to_fp GR64:$src)),
1553 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1556 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1557 "cvttss2si\t{$src, $dst|$dst, $src}",
1558 SSE_CVT_SS2SI_32>, XS;
1559 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1560 "cvttss2si\t{$src, $dst|$dst, $src}",
1561 SSE_CVT_SS2SI_64>, XS, REX_W;
1562 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1563 "cvttsd2si\t{$src, $dst|$dst, $src}",
1565 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1566 "cvttsd2si\t{$src, $dst|$dst, $src}",
1567 SSE_CVT_SD2SI>, XD, REX_W;
1568 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1569 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1570 SSE_CVT_Scalar>, XS;
1571 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1572 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1573 SSE_CVT_Scalar>, XS, REX_W;
1574 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1575 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1576 SSE_CVT_Scalar>, XD;
1577 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1578 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1579 SSE_CVT_Scalar>, XD, REX_W;
1581 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1582 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1583 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1584 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1585 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1586 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1587 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1588 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1589 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1590 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1591 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1592 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1593 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1594 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1595 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1596 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1598 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1599 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1600 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1601 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1603 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1604 // and/or XMM operand(s).
1606 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1607 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1608 string asm, OpndItins itins> {
1609 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1610 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1611 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1612 Sched<[itins.Sched]>;
1613 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1614 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1615 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1616 Sched<[itins.Sched.Folded]>;
1619 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1620 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1621 PatFrag ld_frag, string asm, OpndItins itins,
1623 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1625 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1626 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1627 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1628 itins.rr>, Sched<[itins.Sched]>;
1629 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1630 (ins DstRC:$src1, x86memop:$src2),
1632 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1633 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1634 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1635 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1638 let Predicates = [UseAVX] in {
1639 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1640 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1641 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1642 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1643 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1644 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1646 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1647 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1648 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1649 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1652 let Predicates = [UseAVX] in {
1653 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1654 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1655 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1656 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1657 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1658 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1660 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1661 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1662 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1663 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1664 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1665 SSE_CVT_Scalar, 0>, XD,
1668 let Constraints = "$src1 = $dst" in {
1669 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1670 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1671 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1672 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1673 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1674 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1675 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1676 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1677 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1678 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1679 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1680 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1685 // Aliases for intrinsics
1686 let Predicates = [UseAVX] in {
1687 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1688 ssmem, sse_load_f32, "cvttss2si",
1689 SSE_CVT_SS2SI_32>, XS, VEX;
1690 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1691 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1692 "cvttss2si", SSE_CVT_SS2SI_64>,
1694 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1695 sdmem, sse_load_f64, "cvttsd2si",
1696 SSE_CVT_SD2SI>, XD, VEX;
1697 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1698 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1699 "cvttsd2si", SSE_CVT_SD2SI>,
1702 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1703 ssmem, sse_load_f32, "cvttss2si",
1704 SSE_CVT_SS2SI_32>, XS;
1705 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1706 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1707 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1708 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1709 sdmem, sse_load_f64, "cvttsd2si",
1711 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1712 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1713 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1715 let Predicates = [UseAVX] in {
1716 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1717 ssmem, sse_load_f32, "cvtss2si",
1718 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1719 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1720 ssmem, sse_load_f32, "cvtss2si",
1721 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1723 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1724 ssmem, sse_load_f32, "cvtss2si",
1725 SSE_CVT_SS2SI_32>, XS;
1726 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1727 ssmem, sse_load_f32, "cvtss2si",
1728 SSE_CVT_SS2SI_64>, XS, REX_W;
1730 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1731 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1732 SSEPackedSingle, SSE_CVT_PS>,
1733 TB, VEX, Requires<[HasAVX]>;
1734 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1735 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1736 SSEPackedSingle, SSE_CVT_PS>,
1737 TB, VEX, VEX_L, Requires<[HasAVX]>;
1739 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1740 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1741 SSEPackedSingle, SSE_CVT_PS>,
1742 TB, Requires<[UseSSE2]>;
1744 let Predicates = [UseAVX] in {
1745 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1746 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1747 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1748 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1749 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1750 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1751 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1752 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1753 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1754 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1755 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1756 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1757 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1758 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1759 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1760 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1763 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1764 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1765 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1766 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1767 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1768 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1769 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1770 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1771 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1772 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1773 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1774 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1775 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1776 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1777 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1778 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1782 // Convert scalar double to scalar single
1783 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1784 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1785 (ins FR64:$src1, FR64:$src2),
1786 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1787 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1788 Sched<[WriteCvtF2F]>;
1790 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1791 (ins FR64:$src1, f64mem:$src2),
1792 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1793 [], IIC_SSE_CVT_Scalar_RM>,
1794 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1795 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1798 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1801 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1802 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1803 [(set FR32:$dst, (fround FR64:$src))],
1804 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1805 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1806 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1807 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1808 IIC_SSE_CVT_Scalar_RM>,
1810 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1812 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1813 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1814 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1816 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1817 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1818 Sched<[WriteCvtF2F]>;
1819 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1820 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1821 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1822 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1823 VR128:$src1, sse_load_f64:$src2))],
1824 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1825 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1827 let Constraints = "$src1 = $dst" in {
1828 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1829 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1830 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1832 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1833 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1834 Sched<[WriteCvtF2F]>;
1835 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1836 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1837 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1838 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1839 VR128:$src1, sse_load_f64:$src2))],
1840 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1841 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1844 // Convert scalar single to scalar double
1845 // SSE2 instructions with XS prefix
1846 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1847 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1848 (ins FR32:$src1, FR32:$src2),
1849 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1850 [], IIC_SSE_CVT_Scalar_RR>,
1851 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1852 Sched<[WriteCvtF2F]>;
1854 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1855 (ins FR32:$src1, f32mem:$src2),
1856 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1857 [], IIC_SSE_CVT_Scalar_RM>,
1858 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1859 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1862 def : Pat<(f64 (fextend FR32:$src)),
1863 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1864 def : Pat<(fextend (loadf32 addr:$src)),
1865 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1867 def : Pat<(extloadf32 addr:$src),
1868 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1869 Requires<[UseAVX, OptForSize]>;
1870 def : Pat<(extloadf32 addr:$src),
1871 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1872 Requires<[UseAVX, OptForSpeed]>;
1874 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1875 "cvtss2sd\t{$src, $dst|$dst, $src}",
1876 [(set FR64:$dst, (fextend FR32:$src))],
1877 IIC_SSE_CVT_Scalar_RR>, XS,
1878 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1879 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1880 "cvtss2sd\t{$src, $dst|$dst, $src}",
1881 [(set FR64:$dst, (extloadf32 addr:$src))],
1882 IIC_SSE_CVT_Scalar_RM>, XS,
1883 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1885 // extload f32 -> f64. This matches load+fextend because we have a hack in
1886 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1888 // Since these loads aren't folded into the fextend, we have to match it
1890 def : Pat<(fextend (loadf32 addr:$src)),
1891 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1892 def : Pat<(extloadf32 addr:$src),
1893 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1895 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1896 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1897 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1899 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1900 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1901 Sched<[WriteCvtF2F]>;
1902 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1903 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1904 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1906 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1907 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1908 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1909 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1910 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1911 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1912 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1914 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1915 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1916 Sched<[WriteCvtF2F]>;
1917 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1918 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1919 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1921 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1922 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1923 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1926 // Convert packed single/double fp to doubleword
1927 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1928 "cvtps2dq\t{$src, $dst|$dst, $src}",
1929 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1930 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1931 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1932 "cvtps2dq\t{$src, $dst|$dst, $src}",
1934 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1935 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1936 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1937 "cvtps2dq\t{$src, $dst|$dst, $src}",
1939 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1940 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1941 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1942 "cvtps2dq\t{$src, $dst|$dst, $src}",
1944 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1945 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1946 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1947 "cvtps2dq\t{$src, $dst|$dst, $src}",
1948 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1949 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1950 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1951 "cvtps2dq\t{$src, $dst|$dst, $src}",
1953 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1954 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1957 // Convert Packed Double FP to Packed DW Integers
1958 let Predicates = [HasAVX] in {
1959 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1960 // register, but the same isn't true when using memory operands instead.
1961 // Provide other assembly rr and rm forms to address this explicitly.
1962 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1963 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1964 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1965 VEX, Sched<[WriteCvtF2I]>;
1968 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1969 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1970 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1971 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1973 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX,
1974 Sched<[WriteCvtF2ILd]>;
1977 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1978 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1980 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
1981 Sched<[WriteCvtF2I]>;
1982 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1983 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1985 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1986 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1987 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1988 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1991 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1992 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1994 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1995 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
1996 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1997 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1998 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1999 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2001 // Convert with truncation packed single/double fp to doubleword
2002 // SSE2 packed instructions with XS prefix
2003 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2004 "cvttps2dq\t{$src, $dst|$dst, $src}",
2006 (int_x86_sse2_cvttps2dq VR128:$src))],
2007 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2008 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2009 "cvttps2dq\t{$src, $dst|$dst, $src}",
2010 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2011 (memopv4f32 addr:$src)))],
2012 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2013 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2014 "cvttps2dq\t{$src, $dst|$dst, $src}",
2016 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2017 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2018 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2019 "cvttps2dq\t{$src, $dst|$dst, $src}",
2020 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2021 (memopv8f32 addr:$src)))],
2022 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2023 Sched<[WriteCvtF2ILd]>;
2025 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2026 "cvttps2dq\t{$src, $dst|$dst, $src}",
2027 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2028 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2029 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2030 "cvttps2dq\t{$src, $dst|$dst, $src}",
2032 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2033 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2035 let Predicates = [HasAVX] in {
2036 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2037 (VCVTDQ2PSrr VR128:$src)>;
2038 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2039 (VCVTDQ2PSrm addr:$src)>;
2041 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2042 (VCVTDQ2PSrr VR128:$src)>;
2043 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2044 (VCVTDQ2PSrm addr:$src)>;
2046 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2047 (VCVTTPS2DQrr VR128:$src)>;
2048 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2049 (VCVTTPS2DQrm addr:$src)>;
2051 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2052 (VCVTDQ2PSYrr VR256:$src)>;
2053 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
2054 (VCVTDQ2PSYrm addr:$src)>;
2056 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2057 (VCVTTPS2DQYrr VR256:$src)>;
2058 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
2059 (VCVTTPS2DQYrm addr:$src)>;
2062 let Predicates = [UseSSE2] in {
2063 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2064 (CVTDQ2PSrr VR128:$src)>;
2065 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2066 (CVTDQ2PSrm addr:$src)>;
2068 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2069 (CVTDQ2PSrr VR128:$src)>;
2070 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2071 (CVTDQ2PSrm addr:$src)>;
2073 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2074 (CVTTPS2DQrr VR128:$src)>;
2075 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2076 (CVTTPS2DQrm addr:$src)>;
2079 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2080 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2082 (int_x86_sse2_cvttpd2dq VR128:$src))],
2083 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2085 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2086 // register, but the same isn't true when using memory operands instead.
2087 // Provide other assembly rr and rm forms to address this explicitly.
2090 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2091 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
2092 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2093 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2094 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2095 (memopv2f64 addr:$src)))],
2096 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2099 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2100 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2102 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2103 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2104 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2105 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2107 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
2108 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2109 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2110 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2112 let Predicates = [HasAVX] in {
2113 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2114 (VCVTTPD2DQYrr VR256:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
2116 (VCVTTPD2DQYrm addr:$src)>;
2117 } // Predicates = [HasAVX]
2119 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2120 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2121 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2122 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2123 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2124 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2125 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2126 (memopv2f64 addr:$src)))],
2128 Sched<[WriteCvtF2ILd]>;
2130 // Convert packed single to packed double
2131 let Predicates = [HasAVX] in {
2132 // SSE2 instructions without OpSize prefix
2133 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2134 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2135 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2136 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2137 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2138 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2139 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2140 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2141 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2142 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2145 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2146 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2147 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2149 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2150 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2153 let Predicates = [UseSSE2] in {
2154 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2155 "cvtps2pd\t{$src, $dst|$dst, $src}",
2156 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2157 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2158 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2159 "cvtps2pd\t{$src, $dst|$dst, $src}",
2160 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2161 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2164 // Convert Packed DW Integers to Packed Double FP
2165 let Predicates = [HasAVX] in {
2166 let neverHasSideEffects = 1, mayLoad = 1 in
2167 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2168 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2169 []>, VEX, Sched<[WriteCvtI2FLd]>;
2170 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2171 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2173 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2174 Sched<[WriteCvtI2F]>;
2175 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2176 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2178 (int_x86_avx_cvtdq2_pd_256
2179 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L,
2180 Sched<[WriteCvtI2FLd]>;
2181 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2182 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2184 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2185 Sched<[WriteCvtI2F]>;
2188 let neverHasSideEffects = 1, mayLoad = 1 in
2189 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2190 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2191 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2192 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2193 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2194 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2195 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2197 // AVX 256-bit register conversion intrinsics
2198 let Predicates = [HasAVX] in {
2199 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2200 (VCVTDQ2PDYrr VR128:$src)>;
2201 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2202 (VCVTDQ2PDYrm addr:$src)>;
2203 } // Predicates = [HasAVX]
2205 // Convert packed double to packed single
2206 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2207 // register, but the same isn't true when using memory operands instead.
2208 // Provide other assembly rr and rm forms to address this explicitly.
2209 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2210 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2211 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2212 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2215 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2216 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2217 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2218 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2220 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2221 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2224 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2225 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2227 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2228 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2229 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2230 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2232 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2233 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2234 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2235 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2237 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2238 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2239 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2240 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2241 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2242 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2244 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2245 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2248 // AVX 256-bit register conversion intrinsics
2249 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2250 // whenever possible to avoid declaring two versions of each one.
2251 let Predicates = [HasAVX] in {
2252 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2253 (VCVTDQ2PSYrr VR256:$src)>;
2254 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2255 (VCVTDQ2PSYrm addr:$src)>;
2257 // Match fround and fextend for 128/256-bit conversions
2258 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2259 (VCVTPD2PSrr VR128:$src)>;
2260 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2261 (VCVTPD2PSXrm addr:$src)>;
2262 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2263 (VCVTPD2PSYrr VR256:$src)>;
2264 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2265 (VCVTPD2PSYrm addr:$src)>;
2267 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2268 (VCVTPS2PDrr VR128:$src)>;
2269 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2270 (VCVTPS2PDYrr VR128:$src)>;
2271 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2272 (VCVTPS2PDYrm addr:$src)>;
2275 let Predicates = [UseSSE2] in {
2276 // Match fround and fextend for 128 conversions
2277 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2278 (CVTPD2PSrr VR128:$src)>;
2279 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2280 (CVTPD2PSrm addr:$src)>;
2282 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2283 (CVTPS2PDrr VR128:$src)>;
2286 //===----------------------------------------------------------------------===//
2287 // SSE 1 & 2 - Compare Instructions
2288 //===----------------------------------------------------------------------===//
2290 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2291 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2292 Operand CC, SDNode OpNode, ValueType VT,
2293 PatFrag ld_frag, string asm, string asm_alt,
2295 def rr : SIi8<0xC2, MRMSrcReg,
2296 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2297 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2298 itins.rr>, Sched<[itins.Sched]>;
2299 def rm : SIi8<0xC2, MRMSrcMem,
2300 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2301 [(set RC:$dst, (OpNode (VT RC:$src1),
2302 (ld_frag addr:$src2), imm:$cc))],
2304 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2306 // Accept explicit immediate argument form instead of comparison code.
2307 let neverHasSideEffects = 1 in {
2308 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2309 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2310 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2312 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2313 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2314 IIC_SSE_ALU_F32S_RM>,
2315 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2319 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2320 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2321 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2323 XS, VEX_4V, VEX_LIG;
2324 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2325 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2326 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2327 SSE_ALU_F32S>, // same latency as 32 bit compare
2328 XD, VEX_4V, VEX_LIG;
2330 let Constraints = "$src1 = $dst" in {
2331 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2332 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2333 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2335 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2336 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2337 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2342 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2343 Intrinsic Int, string asm, OpndItins itins> {
2344 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2345 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2346 [(set VR128:$dst, (Int VR128:$src1,
2347 VR128:$src, imm:$cc))],
2349 Sched<[itins.Sched]>;
2350 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2351 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2352 [(set VR128:$dst, (Int VR128:$src1,
2353 (load addr:$src), imm:$cc))],
2355 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2358 // Aliases to match intrinsics which expect XMM operand(s).
2359 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2360 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2363 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2364 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2365 SSE_ALU_F32S>, // same latency as f32
2367 let Constraints = "$src1 = $dst" in {
2368 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2369 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2371 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2372 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2378 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2379 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2380 ValueType vt, X86MemOperand x86memop,
2381 PatFrag ld_frag, string OpcodeStr> {
2382 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2383 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2384 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2387 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2388 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2389 [(set EFLAGS, (OpNode (vt RC:$src1),
2390 (ld_frag addr:$src2)))],
2392 Sched<[WriteFAddLd, ReadAfterLd]>;
2395 let Defs = [EFLAGS] in {
2396 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2397 "ucomiss">, TB, VEX, VEX_LIG;
2398 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2399 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2400 let Pattern = []<dag> in {
2401 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2402 "comiss">, TB, VEX, VEX_LIG;
2403 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2404 "comisd">, TB, OpSize, VEX, VEX_LIG;
2407 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2408 load, "ucomiss">, TB, VEX;
2409 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2410 load, "ucomisd">, TB, OpSize, VEX;
2412 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2413 load, "comiss">, TB, VEX;
2414 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2415 load, "comisd">, TB, OpSize, VEX;
2416 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2418 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2419 "ucomisd">, TB, OpSize;
2421 let Pattern = []<dag> in {
2422 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2424 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2425 "comisd">, TB, OpSize;
2428 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2429 load, "ucomiss">, TB;
2430 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2431 load, "ucomisd">, TB, OpSize;
2433 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2435 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2436 "comisd">, TB, OpSize;
2437 } // Defs = [EFLAGS]
2439 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2440 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2441 Operand CC, Intrinsic Int, string asm,
2442 string asm_alt, Domain d,
2443 OpndItins itins = SSE_ALU_F32P> {
2444 def rri : PIi8<0xC2, MRMSrcReg,
2445 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2446 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2449 def rmi : PIi8<0xC2, MRMSrcMem,
2450 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2451 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2453 Sched<[WriteFAddLd, ReadAfterLd]>;
2455 // Accept explicit immediate argument form instead of comparison code.
2456 let neverHasSideEffects = 1 in {
2457 def rri_alt : PIi8<0xC2, MRMSrcReg,
2458 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2459 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2460 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2461 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2462 asm_alt, [], itins.rm, d>,
2463 Sched<[WriteFAddLd, ReadAfterLd]>;
2467 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2468 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2469 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2470 SSEPackedSingle>, TB, VEX_4V;
2471 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2472 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2473 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2474 SSEPackedDouble>, TB, OpSize, VEX_4V;
2475 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2476 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2477 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2478 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2479 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2480 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2481 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2482 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2483 let Constraints = "$src1 = $dst" in {
2484 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2485 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2486 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2487 SSEPackedSingle, SSE_ALU_F32P>, TB;
2488 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2489 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2490 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2491 SSEPackedDouble, SSE_ALU_F64P>, TB, OpSize;
2494 let Predicates = [HasAVX] in {
2495 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2496 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2497 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2498 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2499 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2500 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2501 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2502 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2504 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2505 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2506 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2507 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2508 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2509 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2510 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2511 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2514 let Predicates = [UseSSE1] in {
2515 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2516 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2517 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2518 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2521 let Predicates = [UseSSE2] in {
2522 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2523 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2524 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2525 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2528 //===----------------------------------------------------------------------===//
2529 // SSE 1 & 2 - Shuffle Instructions
2530 //===----------------------------------------------------------------------===//
2532 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2533 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2534 ValueType vt, string asm, PatFrag mem_frag,
2535 Domain d, bit IsConvertibleToThreeAddress = 0> {
2536 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2537 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2538 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2539 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2540 Sched<[WriteShuffleLd, ReadAfterLd]>;
2541 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2542 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2543 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2544 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2545 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2546 Sched<[WriteShuffle]>;
2549 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2550 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2551 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2552 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2553 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2554 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2555 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2556 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2557 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2558 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2559 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2560 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2562 let Constraints = "$src1 = $dst" in {
2563 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2564 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2565 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2567 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2568 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2569 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2573 let Predicates = [HasAVX] in {
2574 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2575 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2576 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2577 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2578 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2580 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2581 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2582 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2583 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2584 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2587 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2588 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2589 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2590 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2591 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2593 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2594 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2595 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2596 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2597 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2600 let Predicates = [UseSSE1] in {
2601 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2602 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2603 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2604 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2605 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2608 let Predicates = [UseSSE2] in {
2609 // Generic SHUFPD patterns
2610 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2611 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2612 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2613 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2614 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2617 //===----------------------------------------------------------------------===//
2618 // SSE 1 & 2 - Unpack Instructions
2619 //===----------------------------------------------------------------------===//
2621 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2622 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2623 PatFrag mem_frag, RegisterClass RC,
2624 X86MemOperand x86memop, string asm,
2626 def rr : PI<opc, MRMSrcReg,
2627 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2629 (vt (OpNode RC:$src1, RC:$src2)))],
2630 IIC_SSE_UNPCK, d>, Sched<[WriteShuffle]>;
2631 def rm : PI<opc, MRMSrcMem,
2632 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2634 (vt (OpNode RC:$src1,
2635 (mem_frag addr:$src2))))],
2637 Sched<[WriteShuffleLd, ReadAfterLd]>;
2640 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2641 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2642 SSEPackedSingle>, TB, VEX_4V;
2643 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2644 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2645 SSEPackedDouble>, TB, OpSize, VEX_4V;
2646 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2647 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2648 SSEPackedSingle>, TB, VEX_4V;
2649 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2650 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2651 SSEPackedDouble>, TB, OpSize, VEX_4V;
2653 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2654 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2655 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2656 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2657 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2658 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2659 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2660 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2661 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2662 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2663 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2664 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2666 let Constraints = "$src1 = $dst" in {
2667 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2668 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2669 SSEPackedSingle>, TB;
2670 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2671 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2672 SSEPackedDouble>, TB, OpSize;
2673 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2674 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2675 SSEPackedSingle>, TB;
2676 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2677 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2678 SSEPackedDouble>, TB, OpSize;
2679 } // Constraints = "$src1 = $dst"
2681 let Predicates = [HasAVX1Only] in {
2682 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2683 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2684 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2685 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2686 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2687 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2688 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2689 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2691 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2692 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2693 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2694 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2695 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2696 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2697 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2698 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2701 let Predicates = [HasAVX] in {
2702 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2703 // problem is during lowering, where it's not possible to recognize the load
2704 // fold cause it has two uses through a bitcast. One use disappears at isel
2705 // time and the fold opportunity reappears.
2706 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2707 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2710 let Predicates = [UseSSE2] in {
2711 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2712 // problem is during lowering, where it's not possible to recognize the load
2713 // fold cause it has two uses through a bitcast. One use disappears at isel
2714 // time and the fold opportunity reappears.
2715 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2716 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2719 //===----------------------------------------------------------------------===//
2720 // SSE 1 & 2 - Extract Floating-Point Sign mask
2721 //===----------------------------------------------------------------------===//
2723 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2724 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2726 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2727 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2728 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2729 Sched<[WriteVecLogic]>;
2730 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2731 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2732 IIC_SSE_MOVMSK, d>, REX_W, Sched<[WriteVecLogic]>;
2735 let Predicates = [HasAVX] in {
2736 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2737 "movmskps", SSEPackedSingle>, TB, VEX;
2738 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2739 "movmskpd", SSEPackedDouble>, TB,
2741 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2742 "movmskps", SSEPackedSingle>, TB,
2744 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2745 "movmskpd", SSEPackedDouble>, TB,
2748 def : Pat<(i32 (X86fgetsign FR32:$src)),
2749 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2750 def : Pat<(i64 (X86fgetsign FR32:$src)),
2751 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2752 def : Pat<(i32 (X86fgetsign FR64:$src)),
2753 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2754 def : Pat<(i64 (X86fgetsign FR64:$src)),
2755 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2758 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2759 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2760 SSEPackedSingle>, TB, VEX, Sched<[WriteVecLogic]>;
2761 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2762 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2763 SSEPackedDouble>, TB,
2764 OpSize, VEX, Sched<[WriteVecLogic]>;
2765 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2766 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2767 SSEPackedSingle>, TB, VEX, VEX_L, Sched<[WriteVecLogic]>;
2768 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2769 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2770 SSEPackedDouble>, TB,
2771 OpSize, VEX, VEX_L, Sched<[WriteVecLogic]>;
2774 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2775 SSEPackedSingle>, TB;
2776 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2777 SSEPackedDouble>, TB, OpSize;
2779 def : Pat<(i32 (X86fgetsign FR32:$src)),
2780 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2781 Requires<[UseSSE1]>;
2782 def : Pat<(i64 (X86fgetsign FR32:$src)),
2783 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2784 Requires<[UseSSE1]>;
2785 def : Pat<(i32 (X86fgetsign FR64:$src)),
2786 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2787 Requires<[UseSSE2]>;
2788 def : Pat<(i64 (X86fgetsign FR64:$src)),
2789 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2790 Requires<[UseSSE2]>;
2792 //===---------------------------------------------------------------------===//
2793 // SSE2 - Packed Integer Logical Instructions
2794 //===---------------------------------------------------------------------===//
2796 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2798 /// PDI_binop_rm - Simple SSE2 binary operator.
2799 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2800 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2801 X86MemOperand x86memop, OpndItins itins,
2802 bit IsCommutable, bit Is2Addr> {
2803 let isCommutable = IsCommutable in
2804 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2805 (ins RC:$src1, RC:$src2),
2807 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2808 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2809 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2810 Sched<[itins.Sched]>;
2811 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2812 (ins RC:$src1, x86memop:$src2),
2814 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2815 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2816 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2817 (bitconvert (memop_frag addr:$src2)))))],
2819 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2821 } // ExeDomain = SSEPackedInt
2823 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2824 ValueType OpVT128, ValueType OpVT256,
2825 OpndItins itins, bit IsCommutable = 0> {
2826 let Predicates = [HasAVX] in
2827 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2828 VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2830 let Constraints = "$src1 = $dst" in
2831 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2832 memopv2i64, i128mem, itins, IsCommutable, 1>;
2834 let Predicates = [HasAVX2] in
2835 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2836 OpVT256, VR256, memopv4i64, i256mem, itins,
2837 IsCommutable, 0>, VEX_4V, VEX_L;
2840 // These are ordered here for pattern ordering requirements with the fp versions
2842 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2843 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2844 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2845 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2846 SSE_BIT_ITINS_P, 0>;
2848 //===----------------------------------------------------------------------===//
2849 // SSE 1 & 2 - Logical Instructions
2850 //===----------------------------------------------------------------------===//
2852 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2854 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2855 SDNode OpNode, OpndItins itins> {
2856 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2857 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2860 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2861 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2864 let Constraints = "$src1 = $dst" in {
2865 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2866 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2869 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2870 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2875 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2876 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2878 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2880 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2883 let isCommutable = 0 in
2884 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2887 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2889 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2891 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2892 !strconcat(OpcodeStr, "ps"), f256mem,
2893 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2894 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2895 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2897 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2898 !strconcat(OpcodeStr, "pd"), f256mem,
2899 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2900 (bc_v4i64 (v4f64 VR256:$src2))))],
2901 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2902 (memopv4i64 addr:$src2)))], 0>,
2903 TB, OpSize, VEX_4V, VEX_L;
2905 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2906 // are all promoted to v2i64, and the patterns are covered by the int
2907 // version. This is needed in SSE only, because v2i64 isn't supported on
2908 // SSE1, but only on SSE2.
2909 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2910 !strconcat(OpcodeStr, "ps"), f128mem, [],
2911 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2912 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2914 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2915 !strconcat(OpcodeStr, "pd"), f128mem,
2916 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2917 (bc_v2i64 (v2f64 VR128:$src2))))],
2918 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2919 (memopv2i64 addr:$src2)))], 0>,
2922 let Constraints = "$src1 = $dst" in {
2923 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2924 !strconcat(OpcodeStr, "ps"), f128mem,
2925 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2926 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2927 (memopv2i64 addr:$src2)))]>, TB;
2929 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2930 !strconcat(OpcodeStr, "pd"), f128mem,
2931 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2932 (bc_v2i64 (v2f64 VR128:$src2))))],
2933 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2934 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2938 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2939 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2940 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2941 let isCommutable = 0 in
2942 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2944 //===----------------------------------------------------------------------===//
2945 // SSE 1 & 2 - Arithmetic Instructions
2946 //===----------------------------------------------------------------------===//
2948 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2951 /// In addition, we also have a special variant of the scalar form here to
2952 /// represent the associated intrinsic operation. This form is unlike the
2953 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2954 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2956 /// These three forms can each be reg+reg or reg+mem.
2959 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2961 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2962 SDNode OpNode, SizeItins itins> {
2963 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2964 VR128, v4f32, f128mem, memopv4f32,
2965 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2966 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2967 VR128, v2f64, f128mem, memopv2f64,
2968 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2970 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2971 OpNode, VR256, v8f32, f256mem, memopv8f32,
2972 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2973 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2974 OpNode, VR256, v4f64, f256mem, memopv4f64,
2975 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2977 let Constraints = "$src1 = $dst" in {
2978 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2979 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2981 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2982 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2983 itins.d>, TB, OpSize;
2987 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2989 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2990 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
2991 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2992 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
2994 let Constraints = "$src1 = $dst" in {
2995 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2996 OpNode, FR32, f32mem, itins.s>, XS;
2997 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2998 OpNode, FR64, f64mem, itins.d>, XD;
3002 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3004 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3005 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3006 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3007 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3008 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3009 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3011 let Constraints = "$src1 = $dst" in {
3012 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3013 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3015 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3016 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3021 // Binary Arithmetic instructions
3022 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3023 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3024 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3025 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3026 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3027 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3028 let isCommutable = 0 in {
3029 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3030 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3031 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3032 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3033 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3034 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3035 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3036 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3037 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3038 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3039 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3040 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3043 let isCodeGenOnly = 1 in {
3044 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3045 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3046 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3047 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3051 /// In addition, we also have a special variant of the scalar form here to
3052 /// represent the associated intrinsic operation. This form is unlike the
3053 /// plain scalar form, in that it takes an entire vector (instead of a
3054 /// scalar) and leaves the top elements undefined.
3056 /// And, we have a special variant form for a full-vector intrinsic form.
3058 let Sched = WriteFSqrt in {
3059 def SSE_SQRTPS : OpndItins<
3060 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3063 def SSE_SQRTSS : OpndItins<
3064 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3067 def SSE_SQRTPD : OpndItins<
3068 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3071 def SSE_SQRTSD : OpndItins<
3072 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3076 let Sched = WriteFRcp in {
3077 def SSE_RCPP : OpndItins<
3078 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3081 def SSE_RCPS : OpndItins<
3082 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3086 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3087 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3088 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3089 let Predicates = [HasAVX], hasSideEffects = 0 in {
3090 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3091 (ins FR32:$src1, FR32:$src2),
3092 !strconcat("v", OpcodeStr,
3093 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3094 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3095 let mayLoad = 1 in {
3096 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3097 (ins FR32:$src1,f32mem:$src2),
3098 !strconcat("v", OpcodeStr,
3099 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3100 []>, VEX_4V, VEX_LIG,
3101 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3102 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3103 (ins VR128:$src1, ssmem:$src2),
3104 !strconcat("v", OpcodeStr,
3105 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3106 []>, VEX_4V, VEX_LIG,
3107 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3111 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3112 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3113 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3114 // For scalar unary operations, fold a load into the operation
3115 // only in OptForSize mode. It eliminates an instruction, but it also
3116 // eliminates a whole-register clobber (the load), so it introduces a
3117 // partial register update condition.
3118 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3119 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3120 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3121 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3122 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3123 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3124 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3125 Sched<[itins.Sched]>;
3126 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3127 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3128 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3129 Sched<[itins.Sched.Folded]>;
3132 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3133 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3135 let Predicates = [HasAVX], hasSideEffects = 0 in {
3136 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3137 (ins FR32:$src1, FR32:$src2),
3138 !strconcat("v", OpcodeStr,
3139 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3140 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3141 let mayLoad = 1 in {
3142 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3143 (ins FR32:$src1,f32mem:$src2),
3144 !strconcat("v", OpcodeStr,
3145 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3146 []>, VEX_4V, VEX_LIG,
3147 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3148 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3149 (ins VR128:$src1, ssmem:$src2),
3150 !strconcat("v", OpcodeStr,
3151 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3152 []>, VEX_4V, VEX_LIG,
3153 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3157 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3158 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3159 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3160 // For scalar unary operations, fold a load into the operation
3161 // only in OptForSize mode. It eliminates an instruction, but it also
3162 // eliminates a whole-register clobber (the load), so it introduces a
3163 // partial register update condition.
3164 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3165 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3166 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3167 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3168 let Constraints = "$src1 = $dst" in {
3169 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3170 (ins VR128:$src1, VR128:$src2),
3171 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3172 [], itins.rr>, Sched<[itins.Sched]>;
3173 let mayLoad = 1, hasSideEffects = 0 in
3174 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3175 (ins VR128:$src1, ssmem:$src2),
3176 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3177 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3181 /// sse1_fp_unop_p - SSE1 unops in packed form.
3182 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3184 let Predicates = [HasAVX] in {
3185 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3186 !strconcat("v", OpcodeStr,
3187 "ps\t{$src, $dst|$dst, $src}"),
3188 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3189 itins.rr>, VEX, Sched<[itins.Sched]>;
3190 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3191 !strconcat("v", OpcodeStr,
3192 "ps\t{$src, $dst|$dst, $src}"),
3193 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))],
3194 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3195 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3196 !strconcat("v", OpcodeStr,
3197 "ps\t{$src, $dst|$dst, $src}"),
3198 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3199 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3200 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3201 !strconcat("v", OpcodeStr,
3202 "ps\t{$src, $dst|$dst, $src}"),
3203 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3204 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3207 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3208 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3209 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3210 Sched<[itins.Sched]>;
3211 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3212 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3213 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3214 Sched<[itins.Sched.Folded]>;
3217 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3218 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3219 Intrinsic V4F32Int, Intrinsic V8F32Int,
3221 let Predicates = [HasAVX] in {
3222 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3223 !strconcat("v", OpcodeStr,
3224 "ps\t{$src, $dst|$dst, $src}"),
3225 [(set VR128:$dst, (V4F32Int VR128:$src))],
3226 itins.rr>, VEX, Sched<[itins.Sched]>;
3227 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3228 !strconcat("v", OpcodeStr,
3229 "ps\t{$src, $dst|$dst, $src}"),
3230 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3231 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3232 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3233 !strconcat("v", OpcodeStr,
3234 "ps\t{$src, $dst|$dst, $src}"),
3235 [(set VR256:$dst, (V8F32Int VR256:$src))],
3236 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3237 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3239 !strconcat("v", OpcodeStr,
3240 "ps\t{$src, $dst|$dst, $src}"),
3241 [(set VR256:$dst, (V8F32Int (memopv8f32 addr:$src)))],
3242 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3245 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3246 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3247 [(set VR128:$dst, (V4F32Int VR128:$src))],
3248 itins.rr>, Sched<[itins.Sched]>;
3249 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3250 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3251 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3252 itins.rm>, Sched<[itins.Sched.Folded]>;
3255 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3256 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3257 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3258 let Predicates = [HasAVX], hasSideEffects = 0 in {
3259 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3260 (ins FR64:$src1, FR64:$src2),
3261 !strconcat("v", OpcodeStr,
3262 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3263 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3264 let mayLoad = 1 in {
3265 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3266 (ins FR64:$src1,f64mem:$src2),
3267 !strconcat("v", OpcodeStr,
3268 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3269 []>, VEX_4V, VEX_LIG,
3270 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3271 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3272 (ins VR128:$src1, sdmem:$src2),
3273 !strconcat("v", OpcodeStr,
3274 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3275 []>, VEX_4V, VEX_LIG,
3276 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3280 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3281 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3282 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3283 Sched<[itins.Sched]>;
3284 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3285 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3286 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3287 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3288 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3289 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3290 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3291 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3292 Sched<[itins.Sched]>;
3293 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3294 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3295 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3296 Sched<[itins.Sched.Folded]>;
3299 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3300 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3301 SDNode OpNode, OpndItins itins> {
3302 let Predicates = [HasAVX] in {
3303 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3304 !strconcat("v", OpcodeStr,
3305 "pd\t{$src, $dst|$dst, $src}"),
3306 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3307 itins.rr>, VEX, Sched<[itins.Sched]>;
3308 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3309 !strconcat("v", OpcodeStr,
3310 "pd\t{$src, $dst|$dst, $src}"),
3311 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))],
3312 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3313 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3314 !strconcat("v", OpcodeStr,
3315 "pd\t{$src, $dst|$dst, $src}"),
3316 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3317 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3318 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3319 !strconcat("v", OpcodeStr,
3320 "pd\t{$src, $dst|$dst, $src}"),
3321 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3322 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3325 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3326 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3327 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3328 Sched<[itins.Sched]>;
3329 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3330 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3331 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3332 Sched<[itins.Sched.Folded]>;
3336 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3338 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3339 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3341 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3343 // Reciprocal approximations. Note that these typically require refinement
3344 // in order to obtain suitable precision.
3345 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3346 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3347 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3348 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3349 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3350 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3351 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3352 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3354 let Predicates = [UseAVX] in {
3355 def : Pat<(f32 (fsqrt FR32:$src)),
3356 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3357 def : Pat<(f32 (fsqrt (load addr:$src))),
3358 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3359 Requires<[HasAVX, OptForSize]>;
3360 def : Pat<(f64 (fsqrt FR64:$src)),
3361 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3362 def : Pat<(f64 (fsqrt (load addr:$src))),
3363 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3364 Requires<[HasAVX, OptForSize]>;
3366 def : Pat<(f32 (X86frsqrt FR32:$src)),
3367 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3368 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3369 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3370 Requires<[HasAVX, OptForSize]>;
3372 def : Pat<(f32 (X86frcp FR32:$src)),
3373 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3374 def : Pat<(f32 (X86frcp (load addr:$src))),
3375 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3376 Requires<[HasAVX, OptForSize]>;
3378 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3379 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3380 (COPY_TO_REGCLASS VR128:$src, FR32)),
3382 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3383 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3385 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3386 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3387 (COPY_TO_REGCLASS VR128:$src, FR64)),
3389 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3390 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3392 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3393 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3394 (COPY_TO_REGCLASS VR128:$src, FR32)),
3396 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3397 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3399 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3400 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3401 (COPY_TO_REGCLASS VR128:$src, FR32)),
3403 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3404 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3407 // Reciprocal approximations. Note that these typically require refinement
3408 // in order to obtain suitable precision.
3409 let Predicates = [UseSSE1] in {
3410 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3411 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3412 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3413 (RCPSSr_Int VR128:$src, VR128:$src)>;
3416 // There is no f64 version of the reciprocal approximation instructions.
3418 //===----------------------------------------------------------------------===//
3419 // SSE 1 & 2 - Non-temporal stores
3420 //===----------------------------------------------------------------------===//
3422 let AddedComplexity = 400 in { // Prefer non-temporal versions
3423 let SchedRW = [WriteStore] in {
3424 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3425 (ins f128mem:$dst, VR128:$src),
3426 "movntps\t{$src, $dst|$dst, $src}",
3427 [(alignednontemporalstore (v4f32 VR128:$src),
3429 IIC_SSE_MOVNT>, VEX;
3430 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3431 (ins f128mem:$dst, VR128:$src),
3432 "movntpd\t{$src, $dst|$dst, $src}",
3433 [(alignednontemporalstore (v2f64 VR128:$src),
3435 IIC_SSE_MOVNT>, VEX;
3437 let ExeDomain = SSEPackedInt in
3438 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3439 (ins f128mem:$dst, VR128:$src),
3440 "movntdq\t{$src, $dst|$dst, $src}",
3441 [(alignednontemporalstore (v2i64 VR128:$src),
3443 IIC_SSE_MOVNT>, VEX;
3445 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3446 (ins f256mem:$dst, VR256:$src),
3447 "movntps\t{$src, $dst|$dst, $src}",
3448 [(alignednontemporalstore (v8f32 VR256:$src),
3450 IIC_SSE_MOVNT>, VEX, VEX_L;
3451 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3452 (ins f256mem:$dst, VR256:$src),
3453 "movntpd\t{$src, $dst|$dst, $src}",
3454 [(alignednontemporalstore (v4f64 VR256:$src),
3456 IIC_SSE_MOVNT>, VEX, VEX_L;
3457 let ExeDomain = SSEPackedInt in
3458 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3459 (ins f256mem:$dst, VR256:$src),
3460 "movntdq\t{$src, $dst|$dst, $src}",
3461 [(alignednontemporalstore (v4i64 VR256:$src),
3463 IIC_SSE_MOVNT>, VEX, VEX_L;
3465 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3466 "movntps\t{$src, $dst|$dst, $src}",
3467 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3469 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3470 "movntpd\t{$src, $dst|$dst, $src}",
3471 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3474 let ExeDomain = SSEPackedInt in
3475 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3476 "movntdq\t{$src, $dst|$dst, $src}",
3477 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3480 // There is no AVX form for instructions below this point
3481 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3482 "movnti{l}\t{$src, $dst|$dst, $src}",
3483 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3485 TB, Requires<[HasSSE2]>;
3486 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3487 "movnti{q}\t{$src, $dst|$dst, $src}",
3488 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3490 TB, Requires<[HasSSE2]>;
3491 } // SchedRW = [WriteStore]
3493 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3494 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3496 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3497 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3498 } // AddedComplexity
3500 //===----------------------------------------------------------------------===//
3501 // SSE 1 & 2 - Prefetch and memory fence
3502 //===----------------------------------------------------------------------===//
3504 // Prefetch intrinsic.
3505 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3506 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3507 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3508 IIC_SSE_PREFETCH>, TB;
3509 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3510 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3511 IIC_SSE_PREFETCH>, TB;
3512 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3513 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3514 IIC_SSE_PREFETCH>, TB;
3515 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3516 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3517 IIC_SSE_PREFETCH>, TB;
3520 // FIXME: How should these memory instructions be modeled?
3521 let SchedRW = [WriteLoad] in {
3523 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3524 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3525 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3527 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3528 // was introduced with SSE2, it's backward compatible.
3529 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3531 // Load, store, and memory fence
3532 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3533 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3534 TB, Requires<[HasSSE1]>;
3535 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3536 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3537 TB, Requires<[HasSSE2]>;
3538 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3539 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3540 TB, Requires<[HasSSE2]>;
3543 def : Pat<(X86SFence), (SFENCE)>;
3544 def : Pat<(X86LFence), (LFENCE)>;
3545 def : Pat<(X86MFence), (MFENCE)>;
3547 //===----------------------------------------------------------------------===//
3548 // SSE 1 & 2 - Load/Store XCSR register
3549 //===----------------------------------------------------------------------===//
3551 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3552 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3553 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3554 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3555 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3556 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3558 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3559 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3560 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3561 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3562 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3563 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3565 //===---------------------------------------------------------------------===//
3566 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3567 //===---------------------------------------------------------------------===//
3569 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3571 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3572 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3573 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3575 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3576 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3578 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3579 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3581 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3582 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3587 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
3588 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3589 "movdqa\t{$src, $dst|$dst, $src}", [],
3592 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3593 "movdqa\t{$src, $dst|$dst, $src}", [],
3594 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3595 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3596 "movdqu\t{$src, $dst|$dst, $src}", [],
3599 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3600 "movdqu\t{$src, $dst|$dst, $src}", [],
3601 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3604 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3605 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3606 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3607 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3609 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3610 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3612 let Predicates = [HasAVX] in {
3613 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3614 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3616 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3617 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3622 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3623 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3624 (ins i128mem:$dst, VR128:$src),
3625 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3627 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3628 (ins i256mem:$dst, VR256:$src),
3629 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3631 let Predicates = [HasAVX] in {
3632 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3633 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3635 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3636 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3641 let SchedRW = [WriteMove] in {
3642 let neverHasSideEffects = 1 in
3643 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3644 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3646 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3647 "movdqu\t{$src, $dst|$dst, $src}",
3648 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3651 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3652 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3653 "movdqa\t{$src, $dst|$dst, $src}", [],
3656 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3657 "movdqu\t{$src, $dst|$dst, $src}",
3658 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3662 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3663 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3664 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3665 "movdqa\t{$src, $dst|$dst, $src}",
3666 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3668 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3669 "movdqu\t{$src, $dst|$dst, $src}",
3670 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3672 XS, Requires<[UseSSE2]>;
3675 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3676 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3677 "movdqa\t{$src, $dst|$dst, $src}",
3678 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3680 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3681 "movdqu\t{$src, $dst|$dst, $src}",
3682 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3684 XS, Requires<[UseSSE2]>;
3687 } // ExeDomain = SSEPackedInt
3689 let Predicates = [HasAVX] in {
3690 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3691 (VMOVDQUmr addr:$dst, VR128:$src)>;
3692 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3693 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3695 let Predicates = [UseSSE2] in
3696 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3697 (MOVDQUmr addr:$dst, VR128:$src)>;
3699 //===---------------------------------------------------------------------===//
3700 // SSE2 - Packed Integer Arithmetic Instructions
3701 //===---------------------------------------------------------------------===//
3703 let Sched = WriteVecIMul in
3704 def SSE_PMADD : OpndItins<
3705 IIC_SSE_PMADD, IIC_SSE_PMADD
3708 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3710 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3711 RegisterClass RC, PatFrag memop_frag,
3712 X86MemOperand x86memop,
3714 bit IsCommutable = 0,
3716 let isCommutable = IsCommutable in
3717 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3718 (ins RC:$src1, RC:$src2),
3720 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3721 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3722 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3723 Sched<[itins.Sched]>;
3724 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3725 (ins RC:$src1, x86memop:$src2),
3727 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3728 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3729 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3730 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3733 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3734 Intrinsic IntId256, OpndItins itins,
3735 bit IsCommutable = 0> {
3736 let Predicates = [HasAVX] in
3737 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3738 VR128, memopv2i64, i128mem, itins,
3739 IsCommutable, 0>, VEX_4V;
3741 let Constraints = "$src1 = $dst" in
3742 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3743 i128mem, itins, IsCommutable, 1>;
3745 let Predicates = [HasAVX2] in
3746 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3747 VR256, memopv4i64, i256mem, itins,
3748 IsCommutable, 0>, VEX_4V, VEX_L;
3751 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3752 string OpcodeStr, SDNode OpNode,
3753 SDNode OpNode2, RegisterClass RC,
3754 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3755 ShiftOpndItins itins,
3757 // src2 is always 128-bit
3758 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3759 (ins RC:$src1, VR128:$src2),
3761 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3762 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3763 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3764 itins.rr>, Sched<[WriteVecShift]>;
3765 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3766 (ins RC:$src1, i128mem:$src2),
3768 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3769 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3770 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3771 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
3772 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3773 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3774 (ins RC:$src1, i32i8imm:$src2),
3776 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3777 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3778 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>,
3779 Sched<[WriteVecShift]>;
3782 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3783 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3784 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3785 PatFrag memop_frag, X86MemOperand x86memop,
3787 bit IsCommutable = 0, bit Is2Addr = 1> {
3788 let isCommutable = IsCommutable in
3789 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3790 (ins RC:$src1, RC:$src2),
3792 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3793 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3794 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3795 Sched<[itins.Sched]>;
3796 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3797 (ins RC:$src1, x86memop:$src2),
3799 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3800 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3801 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3802 (bitconvert (memop_frag addr:$src2)))))]>,
3803 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3805 } // ExeDomain = SSEPackedInt
3807 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3808 SSE_INTALU_ITINS_P, 1>;
3809 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3810 SSE_INTALU_ITINS_P, 1>;
3811 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3812 SSE_INTALU_ITINS_P, 1>;
3813 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3814 SSE_INTALUQ_ITINS_P, 1>;
3815 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3816 SSE_INTMUL_ITINS_P, 1>;
3817 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3818 SSE_INTALU_ITINS_P, 0>;
3819 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3820 SSE_INTALU_ITINS_P, 0>;
3821 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3822 SSE_INTALU_ITINS_P, 0>;
3823 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3824 SSE_INTALUQ_ITINS_P, 0>;
3825 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3826 SSE_INTALU_ITINS_P, 0>;
3827 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3828 SSE_INTALU_ITINS_P, 0>;
3829 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3830 SSE_INTALU_ITINS_P, 1>;
3831 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3832 SSE_INTALU_ITINS_P, 1>;
3833 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3834 SSE_INTALU_ITINS_P, 1>;
3835 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3836 SSE_INTALU_ITINS_P, 1>;
3839 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
3840 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
3841 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3842 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
3843 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3844 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
3845 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3846 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
3847 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3848 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
3849 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3850 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
3851 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3852 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
3853 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3854 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
3855 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3856 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
3857 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3858 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
3859 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3860 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
3861 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3862 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
3864 let Predicates = [HasAVX] in
3865 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3866 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3868 let Predicates = [HasAVX2] in
3869 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3870 VR256, memopv4i64, i256mem,
3871 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3872 let Constraints = "$src1 = $dst" in
3873 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3874 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3876 //===---------------------------------------------------------------------===//
3877 // SSE2 - Packed Integer Logical Instructions
3878 //===---------------------------------------------------------------------===//
3880 let Predicates = [HasAVX] in {
3881 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3882 VR128, v8i16, v8i16, bc_v8i16,
3883 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3884 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3885 VR128, v4i32, v4i32, bc_v4i32,
3886 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3887 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3888 VR128, v2i64, v2i64, bc_v2i64,
3889 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3891 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3892 VR128, v8i16, v8i16, bc_v8i16,
3893 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3894 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3895 VR128, v4i32, v4i32, bc_v4i32,
3896 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3897 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3898 VR128, v2i64, v2i64, bc_v2i64,
3899 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3901 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3902 VR128, v8i16, v8i16, bc_v8i16,
3903 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3904 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3905 VR128, v4i32, v4i32, bc_v4i32,
3906 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3908 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3909 // 128-bit logical shifts.
3910 def VPSLLDQri : PDIi8<0x73, MRM7r,
3911 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3912 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3914 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3916 def VPSRLDQri : PDIi8<0x73, MRM3r,
3917 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3918 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3920 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3922 // PSRADQri doesn't exist in SSE[1-3].
3924 } // Predicates = [HasAVX]
3926 let Predicates = [HasAVX2] in {
3927 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3928 VR256, v16i16, v8i16, bc_v8i16,
3929 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3930 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3931 VR256, v8i32, v4i32, bc_v4i32,
3932 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3933 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3934 VR256, v4i64, v2i64, bc_v2i64,
3935 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3937 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3938 VR256, v16i16, v8i16, bc_v8i16,
3939 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3940 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3941 VR256, v8i32, v4i32, bc_v4i32,
3942 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3943 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3944 VR256, v4i64, v2i64, bc_v2i64,
3945 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3947 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3948 VR256, v16i16, v8i16, bc_v8i16,
3949 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3950 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3951 VR256, v8i32, v4i32, bc_v4i32,
3952 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3954 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3955 // 256-bit logical shifts.
3956 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3957 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3958 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3960 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3962 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3963 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3964 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3966 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3968 // PSRADQYri doesn't exist in SSE[1-3].
3970 } // Predicates = [HasAVX2]
3972 let Constraints = "$src1 = $dst" in {
3973 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3974 VR128, v8i16, v8i16, bc_v8i16,
3975 SSE_INTSHIFT_ITINS_P>;
3976 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3977 VR128, v4i32, v4i32, bc_v4i32,
3978 SSE_INTSHIFT_ITINS_P>;
3979 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3980 VR128, v2i64, v2i64, bc_v2i64,
3981 SSE_INTSHIFT_ITINS_P>;
3983 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3984 VR128, v8i16, v8i16, bc_v8i16,
3985 SSE_INTSHIFT_ITINS_P>;
3986 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3987 VR128, v4i32, v4i32, bc_v4i32,
3988 SSE_INTSHIFT_ITINS_P>;
3989 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3990 VR128, v2i64, v2i64, bc_v2i64,
3991 SSE_INTSHIFT_ITINS_P>;
3993 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3994 VR128, v8i16, v8i16, bc_v8i16,
3995 SSE_INTSHIFT_ITINS_P>;
3996 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3997 VR128, v4i32, v4i32, bc_v4i32,
3998 SSE_INTSHIFT_ITINS_P>;
4000 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4001 // 128-bit logical shifts.
4002 def PSLLDQri : PDIi8<0x73, MRM7r,
4003 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4004 "pslldq\t{$src2, $dst|$dst, $src2}",
4006 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4007 IIC_SSE_INTSHDQ_P_RI>;
4008 def PSRLDQri : PDIi8<0x73, MRM3r,
4009 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4010 "psrldq\t{$src2, $dst|$dst, $src2}",
4012 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4013 IIC_SSE_INTSHDQ_P_RI>;
4014 // PSRADQri doesn't exist in SSE[1-3].
4016 } // Constraints = "$src1 = $dst"
4018 let Predicates = [HasAVX] in {
4019 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4020 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4021 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4022 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4023 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4024 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4026 // Shift up / down and insert zero's.
4027 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4028 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4029 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4030 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4033 let Predicates = [HasAVX2] in {
4034 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4035 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4036 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4037 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4040 let Predicates = [UseSSE2] in {
4041 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4042 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4043 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4044 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4045 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4046 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4048 // Shift up / down and insert zero's.
4049 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4050 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4051 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4052 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4055 //===---------------------------------------------------------------------===//
4056 // SSE2 - Packed Integer Comparison Instructions
4057 //===---------------------------------------------------------------------===//
4059 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4060 SSE_INTALU_ITINS_P, 1>;
4061 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4062 SSE_INTALU_ITINS_P, 1>;
4063 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4064 SSE_INTALU_ITINS_P, 1>;
4065 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4066 SSE_INTALU_ITINS_P, 0>;
4067 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4068 SSE_INTALU_ITINS_P, 0>;
4069 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4070 SSE_INTALU_ITINS_P, 0>;
4072 //===---------------------------------------------------------------------===//
4073 // SSE2 - Packed Integer Pack Instructions
4074 //===---------------------------------------------------------------------===//
4076 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4077 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
4078 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4079 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
4080 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4081 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
4083 //===---------------------------------------------------------------------===//
4084 // SSE2 - Packed Integer Shuffle Instructions
4085 //===---------------------------------------------------------------------===//
4087 let ExeDomain = SSEPackedInt in {
4088 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4090 let Predicates = [HasAVX] in {
4091 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4092 (ins VR128:$src1, i8imm:$src2),
4093 !strconcat("v", OpcodeStr,
4094 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4096 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4097 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4098 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4099 (ins i128mem:$src1, i8imm:$src2),
4100 !strconcat("v", OpcodeStr,
4101 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4103 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4104 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4105 Sched<[WriteShuffleLd]>;
4108 let Predicates = [HasAVX2] in {
4109 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4110 (ins VR256:$src1, i8imm:$src2),
4111 !strconcat("v", OpcodeStr,
4112 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4114 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4115 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4116 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4117 (ins i256mem:$src1, i8imm:$src2),
4118 !strconcat("v", OpcodeStr,
4119 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4121 (vt256 (OpNode (bitconvert (memopv4i64 addr:$src1)),
4122 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4123 Sched<[WriteShuffleLd]>;
4126 let Predicates = [UseSSE2] in {
4127 def ri : Ii8<0x70, MRMSrcReg,
4128 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4129 !strconcat(OpcodeStr,
4130 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4132 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4133 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4134 def mi : Ii8<0x70, MRMSrcMem,
4135 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4136 !strconcat(OpcodeStr,
4137 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4139 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4140 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4141 Sched<[WriteShuffleLd]>;
4144 } // ExeDomain = SSEPackedInt
4146 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4147 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4148 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4150 let Predicates = [HasAVX] in {
4151 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4152 (VPSHUFDmi addr:$src1, imm:$imm)>;
4153 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4154 (VPSHUFDri VR128:$src1, imm:$imm)>;
4157 let Predicates = [UseSSE2] in {
4158 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4159 (PSHUFDmi addr:$src1, imm:$imm)>;
4160 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4161 (PSHUFDri VR128:$src1, imm:$imm)>;
4164 //===---------------------------------------------------------------------===//
4165 // SSE2 - Packed Integer Unpack Instructions
4166 //===---------------------------------------------------------------------===//
4168 let ExeDomain = SSEPackedInt in {
4169 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4170 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4171 def rr : PDI<opc, MRMSrcReg,
4172 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4174 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4175 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4176 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4177 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4178 def rm : PDI<opc, MRMSrcMem,
4179 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4181 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4182 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4183 [(set VR128:$dst, (OpNode VR128:$src1,
4184 (bc_frag (memopv2i64
4187 Sched<[WriteShuffleLd, ReadAfterLd]>;
4190 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4191 SDNode OpNode, PatFrag bc_frag> {
4192 def Yrr : PDI<opc, MRMSrcReg,
4193 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4194 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4195 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4196 Sched<[WriteShuffle]>;
4197 def Yrm : PDI<opc, MRMSrcMem,
4198 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4199 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4200 [(set VR256:$dst, (OpNode VR256:$src1,
4201 (bc_frag (memopv4i64 addr:$src2))))]>,
4202 Sched<[WriteShuffleLd, ReadAfterLd]>;
4205 let Predicates = [HasAVX] in {
4206 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4207 bc_v16i8, 0>, VEX_4V;
4208 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4209 bc_v8i16, 0>, VEX_4V;
4210 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4211 bc_v4i32, 0>, VEX_4V;
4212 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4213 bc_v2i64, 0>, VEX_4V;
4215 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4216 bc_v16i8, 0>, VEX_4V;
4217 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4218 bc_v8i16, 0>, VEX_4V;
4219 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4220 bc_v4i32, 0>, VEX_4V;
4221 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4222 bc_v2i64, 0>, VEX_4V;
4225 let Predicates = [HasAVX2] in {
4226 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4227 bc_v32i8>, VEX_4V, VEX_L;
4228 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4229 bc_v16i16>, VEX_4V, VEX_L;
4230 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4231 bc_v8i32>, VEX_4V, VEX_L;
4232 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4233 bc_v4i64>, VEX_4V, VEX_L;
4235 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4236 bc_v32i8>, VEX_4V, VEX_L;
4237 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4238 bc_v16i16>, VEX_4V, VEX_L;
4239 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4240 bc_v8i32>, VEX_4V, VEX_L;
4241 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4242 bc_v4i64>, VEX_4V, VEX_L;
4245 let Constraints = "$src1 = $dst" in {
4246 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4248 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4250 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4252 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4255 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4257 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4259 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4261 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4264 } // ExeDomain = SSEPackedInt
4266 //===---------------------------------------------------------------------===//
4267 // SSE2 - Packed Integer Extract and Insert
4268 //===---------------------------------------------------------------------===//
4270 let ExeDomain = SSEPackedInt in {
4271 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4272 def rri : Ii8<0xC4, MRMSrcReg,
4273 (outs VR128:$dst), (ins VR128:$src1,
4274 GR32:$src2, i32i8imm:$src3),
4276 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4277 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4279 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>,
4280 Sched<[WriteShuffle]>;
4281 def rmi : Ii8<0xC4, MRMSrcMem,
4282 (outs VR128:$dst), (ins VR128:$src1,
4283 i16mem:$src2, i32i8imm:$src3),
4285 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4286 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4288 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4289 imm:$src3))], IIC_SSE_PINSRW>,
4290 Sched<[WriteShuffleLd, ReadAfterLd]>;
4294 let Predicates = [HasAVX] in
4295 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4296 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4297 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4298 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4299 imm:$src2))]>, TB, OpSize, VEX,
4300 Sched<[WriteShuffle]>;
4301 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4302 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4303 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4304 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4305 imm:$src2))], IIC_SSE_PEXTRW>,
4306 Sched<[WriteShuffleLd, ReadAfterLd]>;
4309 let Predicates = [HasAVX] in {
4310 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4311 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4312 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4313 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4314 []>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>;
4317 let Constraints = "$src1 = $dst" in
4318 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4320 } // ExeDomain = SSEPackedInt
4322 //===---------------------------------------------------------------------===//
4323 // SSE2 - Packed Mask Creation
4324 //===---------------------------------------------------------------------===//
4326 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4328 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4329 "pmovmskb\t{$src, $dst|$dst, $src}",
4330 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4331 IIC_SSE_MOVMSK>, VEX;
4332 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4333 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4335 let Predicates = [HasAVX2] in {
4336 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4337 "pmovmskb\t{$src, $dst|$dst, $src}",
4338 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4339 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4340 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4343 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4344 "pmovmskb\t{$src, $dst|$dst, $src}",
4345 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4348 } // ExeDomain = SSEPackedInt
4350 //===---------------------------------------------------------------------===//
4351 // SSE2 - Conditional Store
4352 //===---------------------------------------------------------------------===//
4354 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4357 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4358 (ins VR128:$src, VR128:$mask),
4359 "maskmovdqu\t{$mask, $src|$src, $mask}",
4360 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4361 IIC_SSE_MASKMOV>, VEX;
4363 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4364 (ins VR128:$src, VR128:$mask),
4365 "maskmovdqu\t{$mask, $src|$src, $mask}",
4366 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4367 IIC_SSE_MASKMOV>, VEX;
4370 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4371 "maskmovdqu\t{$mask, $src|$src, $mask}",
4372 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4375 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4376 "maskmovdqu\t{$mask, $src|$src, $mask}",
4377 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4380 } // ExeDomain = SSEPackedInt
4382 //===---------------------------------------------------------------------===//
4383 // SSE2 - Move Doubleword
4384 //===---------------------------------------------------------------------===//
4386 //===---------------------------------------------------------------------===//
4387 // Move Int Doubleword to Packed Double Int
4389 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4390 "movd\t{$src, $dst|$dst, $src}",
4392 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4393 VEX, Sched<[WriteMove]>;
4394 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4395 "movd\t{$src, $dst|$dst, $src}",
4397 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4399 VEX, Sched<[WriteLoad]>;
4400 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4401 "mov{d|q}\t{$src, $dst|$dst, $src}",
4403 (v2i64 (scalar_to_vector GR64:$src)))],
4404 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4405 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4406 "mov{d|q}\t{$src, $dst|$dst, $src}",
4407 [(set FR64:$dst, (bitconvert GR64:$src))],
4408 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4410 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4411 "movd\t{$src, $dst|$dst, $src}",
4413 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4415 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4416 "movd\t{$src, $dst|$dst, $src}",
4418 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4419 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4420 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4421 "mov{d|q}\t{$src, $dst|$dst, $src}",
4423 (v2i64 (scalar_to_vector GR64:$src)))],
4424 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4425 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4426 "mov{d|q}\t{$src, $dst|$dst, $src}",
4427 [(set FR64:$dst, (bitconvert GR64:$src))],
4428 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4430 //===---------------------------------------------------------------------===//
4431 // Move Int Doubleword to Single Scalar
4433 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4434 "movd\t{$src, $dst|$dst, $src}",
4435 [(set FR32:$dst, (bitconvert GR32:$src))],
4436 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4438 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4439 "movd\t{$src, $dst|$dst, $src}",
4440 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4442 VEX, Sched<[WriteLoad]>;
4443 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4444 "movd\t{$src, $dst|$dst, $src}",
4445 [(set FR32:$dst, (bitconvert GR32:$src))],
4446 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4448 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4449 "movd\t{$src, $dst|$dst, $src}",
4450 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4451 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4453 //===---------------------------------------------------------------------===//
4454 // Move Packed Doubleword Int to Packed Double Int
4456 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4457 "movd\t{$src, $dst|$dst, $src}",
4458 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4459 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4461 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4462 (ins i32mem:$dst, VR128:$src),
4463 "movd\t{$src, $dst|$dst, $src}",
4464 [(store (i32 (vector_extract (v4i32 VR128:$src),
4465 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4466 VEX, Sched<[WriteLoad]>;
4467 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4468 "movd\t{$src, $dst|$dst, $src}",
4469 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4470 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4472 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4473 "movd\t{$src, $dst|$dst, $src}",
4474 [(store (i32 (vector_extract (v4i32 VR128:$src),
4475 (iPTR 0))), addr:$dst)],
4476 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4478 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4479 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4481 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4482 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4484 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4485 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4487 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4488 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4490 //===---------------------------------------------------------------------===//
4491 // Move Packed Doubleword Int first element to Doubleword Int
4493 let SchedRW = [WriteMove] in {
4494 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4495 "mov{d|q}\t{$src, $dst|$dst, $src}",
4496 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4501 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4502 "mov{d|q}\t{$src, $dst|$dst, $src}",
4503 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4508 //===---------------------------------------------------------------------===//
4509 // Bitcast FR64 <-> GR64
4511 let Predicates = [UseAVX] in
4512 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4513 "vmovq\t{$src, $dst|$dst, $src}",
4514 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4515 VEX, Sched<[WriteLoad]>;
4516 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4517 "mov{d|q}\t{$src, $dst|$dst, $src}",
4518 [(set GR64:$dst, (bitconvert FR64:$src))],
4519 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4520 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4521 "movq\t{$src, $dst|$dst, $src}",
4522 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4523 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4525 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4526 "movq\t{$src, $dst|$dst, $src}",
4527 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4528 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4529 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4530 "mov{d|q}\t{$src, $dst|$dst, $src}",
4531 [(set GR64:$dst, (bitconvert FR64:$src))],
4532 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4533 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4534 "movq\t{$src, $dst|$dst, $src}",
4535 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4536 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4538 //===---------------------------------------------------------------------===//
4539 // Move Scalar Single to Double Int
4541 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4542 "movd\t{$src, $dst|$dst, $src}",
4543 [(set GR32:$dst, (bitconvert FR32:$src))],
4544 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4545 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4546 "movd\t{$src, $dst|$dst, $src}",
4547 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4548 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4549 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4550 "movd\t{$src, $dst|$dst, $src}",
4551 [(set GR32:$dst, (bitconvert FR32:$src))],
4552 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4553 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4554 "movd\t{$src, $dst|$dst, $src}",
4555 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4556 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4558 //===---------------------------------------------------------------------===//
4559 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4561 let SchedRW = [WriteMove] in {
4562 let AddedComplexity = 15 in {
4563 def VMOVZDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4564 "movd\t{$src, $dst|$dst, $src}",
4565 [(set VR128:$dst, (v4i32 (X86vzmovl
4566 (v4i32 (scalar_to_vector GR32:$src)))))],
4567 IIC_SSE_MOVDQ>, VEX;
4568 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4569 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4570 [(set VR128:$dst, (v2i64 (X86vzmovl
4571 (v2i64 (scalar_to_vector GR64:$src)))))],
4575 let AddedComplexity = 15 in {
4576 def MOVZDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4577 "movd\t{$src, $dst|$dst, $src}",
4578 [(set VR128:$dst, (v4i32 (X86vzmovl
4579 (v4i32 (scalar_to_vector GR32:$src)))))],
4581 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4582 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4583 [(set VR128:$dst, (v2i64 (X86vzmovl
4584 (v2i64 (scalar_to_vector GR64:$src)))))],
4589 let AddedComplexity = 20, SchedRW = [WriteLoad] in {
4590 def VMOVZDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4591 "movd\t{$src, $dst|$dst, $src}",
4593 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4594 (loadi32 addr:$src))))))],
4595 IIC_SSE_MOVDQ>, VEX;
4596 def MOVZDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4597 "movd\t{$src, $dst|$dst, $src}",
4599 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4600 (loadi32 addr:$src))))))],
4602 } // AddedComplexity, SchedRW
4604 let Predicates = [UseAVX] in {
4605 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4606 let AddedComplexity = 20 in {
4607 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4608 (VMOVZDI2PDIrm addr:$src)>;
4609 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4610 (VMOVZDI2PDIrm addr:$src)>;
4612 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4613 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4614 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4615 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4616 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4617 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4618 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4621 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4622 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4623 (MOVZDI2PDIrm addr:$src)>;
4624 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4625 (MOVZDI2PDIrm addr:$src)>;
4628 // These are the correct encodings of the instructions so that we know how to
4629 // read correct assembly, even though we continue to emit the wrong ones for
4630 // compatibility with Darwin's buggy assembler.
4631 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4632 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4633 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4634 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4635 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4636 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4637 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4638 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4639 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4640 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4641 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4642 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4644 //===---------------------------------------------------------------------===//
4645 // SSE2 - Move Quadword
4646 //===---------------------------------------------------------------------===//
4648 //===---------------------------------------------------------------------===//
4649 // Move Quadword Int to Packed Quadword Int
4652 let SchedRW = [WriteLoad] in {
4653 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4654 "vmovq\t{$src, $dst|$dst, $src}",
4656 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4657 VEX, Requires<[UseAVX]>;
4658 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4659 "movq\t{$src, $dst|$dst, $src}",
4661 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4663 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4666 //===---------------------------------------------------------------------===//
4667 // Move Packed Quadword Int to Quadword Int
4669 let SchedRW = [WriteStore] in {
4670 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4671 "movq\t{$src, $dst|$dst, $src}",
4672 [(store (i64 (vector_extract (v2i64 VR128:$src),
4673 (iPTR 0))), addr:$dst)],
4674 IIC_SSE_MOVDQ>, VEX;
4675 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4676 "movq\t{$src, $dst|$dst, $src}",
4677 [(store (i64 (vector_extract (v2i64 VR128:$src),
4678 (iPTR 0))), addr:$dst)],
4682 //===---------------------------------------------------------------------===//
4683 // Store / copy lower 64-bits of a XMM register.
4685 def VMOVLQ128mr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4686 "movq\t{$src, $dst|$dst, $src}",
4687 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX,
4688 Sched<[WriteStore]>;
4689 def MOVLQ128mr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4690 "movq\t{$src, $dst|$dst, $src}",
4691 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4692 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4694 let AddedComplexity = 20 in
4695 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4696 "vmovq\t{$src, $dst|$dst, $src}",
4698 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4699 (loadi64 addr:$src))))))],
4701 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
4703 let AddedComplexity = 20 in
4704 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4705 "movq\t{$src, $dst|$dst, $src}",
4707 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4708 (loadi64 addr:$src))))))],
4710 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4712 let Predicates = [UseAVX], AddedComplexity = 20 in {
4713 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4714 (VMOVZQI2PQIrm addr:$src)>;
4715 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4716 (VMOVZQI2PQIrm addr:$src)>;
4717 def : Pat<(v2i64 (X86vzload addr:$src)),
4718 (VMOVZQI2PQIrm addr:$src)>;
4721 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4722 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4723 (MOVZQI2PQIrm addr:$src)>;
4724 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4725 (MOVZQI2PQIrm addr:$src)>;
4726 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4729 let Predicates = [HasAVX] in {
4730 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4731 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4732 def : Pat<(v4i64 (X86vzload addr:$src)),
4733 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4736 //===---------------------------------------------------------------------===//
4737 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4738 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4740 let SchedRW = [WriteVecLogic] in {
4741 let AddedComplexity = 15 in
4742 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4743 "vmovq\t{$src, $dst|$dst, $src}",
4744 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4746 XS, VEX, Requires<[UseAVX]>;
4747 let AddedComplexity = 15 in
4748 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4749 "movq\t{$src, $dst|$dst, $src}",
4750 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4752 XS, Requires<[UseSSE2]>;
4755 let SchedRW = [WriteVecLogicLd] in {
4756 let AddedComplexity = 20 in
4757 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4758 "vmovq\t{$src, $dst|$dst, $src}",
4759 [(set VR128:$dst, (v2i64 (X86vzmovl
4760 (loadv2i64 addr:$src))))],
4762 XS, VEX, Requires<[UseAVX]>;
4763 let AddedComplexity = 20 in {
4764 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4765 "movq\t{$src, $dst|$dst, $src}",
4766 [(set VR128:$dst, (v2i64 (X86vzmovl
4767 (loadv2i64 addr:$src))))],
4769 XS, Requires<[UseSSE2]>;
4773 let AddedComplexity = 20 in {
4774 let Predicates = [UseAVX] in {
4775 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4776 (VMOVZPQILo2PQIrm addr:$src)>;
4777 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4778 (VMOVZPQILo2PQIrr VR128:$src)>;
4780 let Predicates = [UseSSE2] in {
4781 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4782 (MOVZPQILo2PQIrm addr:$src)>;
4783 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4784 (MOVZPQILo2PQIrr VR128:$src)>;
4788 // Instructions to match in the assembler
4789 let SchedRW = [WriteMove] in {
4790 def VMOVQs64rr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4791 "movq\t{$src, $dst|$dst, $src}", [],
4792 IIC_SSE_MOVDQ>, VEX, VEX_W;
4793 def VMOVQd64rr : VS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4794 "movq\t{$src, $dst|$dst, $src}", [],
4795 IIC_SSE_MOVDQ>, VEX, VEX_W;
4796 // Recognize "movd" with GR64 destination, but encode as a "movq"
4797 def VMOVQd64rr_alt : VS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4798 "movq\t{$src, $dst|$dst, $src}", [],
4799 IIC_SSE_MOVDQ>, VEX, VEX_W;
4802 // Instructions for the disassembler
4803 // xr = XMM register
4806 let SchedRW = [WriteMove] in {
4807 let Predicates = [UseAVX] in
4808 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4809 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4810 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4811 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4814 //===---------------------------------------------------------------------===//
4815 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4816 //===---------------------------------------------------------------------===//
4817 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4818 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4819 X86MemOperand x86memop> {
4820 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4821 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4822 [(set RC:$dst, (vt (OpNode RC:$src)))],
4823 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4824 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4825 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4826 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4827 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4830 let Predicates = [HasAVX] in {
4831 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4832 v4f32, VR128, memopv4f32, f128mem>, VEX;
4833 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4834 v4f32, VR128, memopv4f32, f128mem>, VEX;
4835 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4836 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4837 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4838 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4840 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4841 memopv4f32, f128mem>;
4842 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4843 memopv4f32, f128mem>;
4845 let Predicates = [HasAVX] in {
4846 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4847 (VMOVSHDUPrr VR128:$src)>;
4848 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4849 (VMOVSHDUPrm addr:$src)>;
4850 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4851 (VMOVSLDUPrr VR128:$src)>;
4852 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4853 (VMOVSLDUPrm addr:$src)>;
4854 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4855 (VMOVSHDUPYrr VR256:$src)>;
4856 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4857 (VMOVSHDUPYrm addr:$src)>;
4858 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4859 (VMOVSLDUPYrr VR256:$src)>;
4860 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4861 (VMOVSLDUPYrm addr:$src)>;
4864 let Predicates = [UseSSE3] in {
4865 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4866 (MOVSHDUPrr VR128:$src)>;
4867 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4868 (MOVSHDUPrm addr:$src)>;
4869 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4870 (MOVSLDUPrr VR128:$src)>;
4871 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4872 (MOVSLDUPrm addr:$src)>;
4875 //===---------------------------------------------------------------------===//
4876 // SSE3 - Replicate Double FP - MOVDDUP
4877 //===---------------------------------------------------------------------===//
4879 multiclass sse3_replicate_dfp<string OpcodeStr> {
4880 let neverHasSideEffects = 1 in
4881 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4882 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4883 [], IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4884 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4885 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4888 (scalar_to_vector (loadf64 addr:$src)))))],
4889 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4892 // FIXME: Merge with above classe when there're patterns for the ymm version
4893 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4894 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4895 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4896 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
4897 Sched<[WriteShuffle]>;
4898 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4899 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4902 (scalar_to_vector (loadf64 addr:$src)))))]>,
4903 Sched<[WriteShuffleLd]>;
4906 let Predicates = [HasAVX] in {
4907 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4908 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4911 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4913 let Predicates = [HasAVX] in {
4914 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4915 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4916 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4917 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4918 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4919 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4920 def : Pat<(X86Movddup (bc_v2f64
4921 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4922 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4925 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4926 (VMOVDDUPYrm addr:$src)>;
4927 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4928 (VMOVDDUPYrm addr:$src)>;
4929 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4930 (VMOVDDUPYrm addr:$src)>;
4931 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4932 (VMOVDDUPYrr VR256:$src)>;
4935 let Predicates = [UseSSE3] in {
4936 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4937 (MOVDDUPrm addr:$src)>;
4938 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4939 (MOVDDUPrm addr:$src)>;
4940 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4941 (MOVDDUPrm addr:$src)>;
4942 def : Pat<(X86Movddup (bc_v2f64
4943 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4944 (MOVDDUPrm addr:$src)>;
4947 //===---------------------------------------------------------------------===//
4948 // SSE3 - Move Unaligned Integer
4949 //===---------------------------------------------------------------------===//
4951 let SchedRW = [WriteLoad] in {
4952 let Predicates = [HasAVX] in {
4953 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4954 "vlddqu\t{$src, $dst|$dst, $src}",
4955 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4956 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4957 "vlddqu\t{$src, $dst|$dst, $src}",
4958 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
4961 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4962 "lddqu\t{$src, $dst|$dst, $src}",
4963 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4967 //===---------------------------------------------------------------------===//
4968 // SSE3 - Arithmetic
4969 //===---------------------------------------------------------------------===//
4971 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4972 X86MemOperand x86memop, OpndItins itins,
4974 def rr : I<0xD0, MRMSrcReg,
4975 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4977 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4978 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4979 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
4980 Sched<[itins.Sched]>;
4981 def rm : I<0xD0, MRMSrcMem,
4982 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4984 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4985 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4986 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
4987 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4990 let Predicates = [HasAVX] in {
4991 let ExeDomain = SSEPackedSingle in {
4992 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4993 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
4994 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4995 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
4997 let ExeDomain = SSEPackedDouble in {
4998 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4999 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5000 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5001 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
5004 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5005 let ExeDomain = SSEPackedSingle in
5006 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5007 f128mem, SSE_ALU_F32P>, TB, XD;
5008 let ExeDomain = SSEPackedDouble in
5009 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5010 f128mem, SSE_ALU_F64P>, TB, OpSize;
5013 //===---------------------------------------------------------------------===//
5014 // SSE3 Instructions
5015 //===---------------------------------------------------------------------===//
5018 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5019 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5020 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5022 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5023 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5024 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5027 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5029 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5030 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5031 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5032 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5034 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5035 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5036 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5038 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5039 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5040 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5043 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5045 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5046 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5047 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5048 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5051 let Predicates = [HasAVX] in {
5052 let ExeDomain = SSEPackedSingle in {
5053 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5054 X86fhadd, 0>, VEX_4V;
5055 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5056 X86fhsub, 0>, VEX_4V;
5057 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5058 X86fhadd, 0>, VEX_4V, VEX_L;
5059 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5060 X86fhsub, 0>, VEX_4V, VEX_L;
5062 let ExeDomain = SSEPackedDouble in {
5063 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5064 X86fhadd, 0>, VEX_4V;
5065 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5066 X86fhsub, 0>, VEX_4V;
5067 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5068 X86fhadd, 0>, VEX_4V, VEX_L;
5069 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5070 X86fhsub, 0>, VEX_4V, VEX_L;
5074 let Constraints = "$src1 = $dst" in {
5075 let ExeDomain = SSEPackedSingle in {
5076 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5077 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5079 let ExeDomain = SSEPackedDouble in {
5080 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5081 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5085 //===---------------------------------------------------------------------===//
5086 // SSSE3 - Packed Absolute Instructions
5087 //===---------------------------------------------------------------------===//
5090 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5091 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5092 Intrinsic IntId128> {
5093 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5095 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5096 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5097 OpSize, Sched<[WriteVecALU]>;
5099 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5101 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5104 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5105 OpSize, Sched<[WriteVecALULd]>;
5108 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5109 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5110 Intrinsic IntId256> {
5111 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5113 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5114 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5115 OpSize, Sched<[WriteVecALU]>;
5117 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5122 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5123 Sched<[WriteVecALULd]>;
5126 // Helper fragments to match sext vXi1 to vXiY.
5127 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5129 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i32 15)))>;
5130 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i32 31)))>;
5131 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5133 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i32 15)))>;
5134 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i32 31)))>;
5136 let Predicates = [HasAVX] in {
5137 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5138 int_x86_ssse3_pabs_b_128>, VEX;
5139 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5140 int_x86_ssse3_pabs_w_128>, VEX;
5141 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5142 int_x86_ssse3_pabs_d_128>, VEX;
5145 (bc_v2i64 (v16i1sextv16i8)),
5146 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5147 (VPABSBrr128 VR128:$src)>;
5149 (bc_v2i64 (v8i1sextv8i16)),
5150 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5151 (VPABSWrr128 VR128:$src)>;
5153 (bc_v2i64 (v4i1sextv4i32)),
5154 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5155 (VPABSDrr128 VR128:$src)>;
5158 let Predicates = [HasAVX2] in {
5159 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5160 int_x86_avx2_pabs_b>, VEX, VEX_L;
5161 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5162 int_x86_avx2_pabs_w>, VEX, VEX_L;
5163 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5164 int_x86_avx2_pabs_d>, VEX, VEX_L;
5167 (bc_v4i64 (v32i1sextv32i8)),
5168 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5169 (VPABSBrr256 VR256:$src)>;
5171 (bc_v4i64 (v16i1sextv16i16)),
5172 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5173 (VPABSWrr256 VR256:$src)>;
5175 (bc_v4i64 (v8i1sextv8i32)),
5176 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5177 (VPABSDrr256 VR256:$src)>;
5180 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5181 int_x86_ssse3_pabs_b_128>;
5182 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5183 int_x86_ssse3_pabs_w_128>;
5184 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5185 int_x86_ssse3_pabs_d_128>;
5187 let Predicates = [HasSSSE3] in {
5189 (bc_v2i64 (v16i1sextv16i8)),
5190 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5191 (PABSBrr128 VR128:$src)>;
5193 (bc_v2i64 (v8i1sextv8i16)),
5194 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5195 (PABSWrr128 VR128:$src)>;
5197 (bc_v2i64 (v4i1sextv4i32)),
5198 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5199 (PABSDrr128 VR128:$src)>;
5202 //===---------------------------------------------------------------------===//
5203 // SSSE3 - Packed Binary Operator Instructions
5204 //===---------------------------------------------------------------------===//
5206 let Sched = WriteVecALU in {
5207 def SSE_PHADDSUBD : OpndItins<
5208 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5210 def SSE_PHADDSUBSW : OpndItins<
5211 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5213 def SSE_PHADDSUBW : OpndItins<
5214 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5217 let Sched = WriteShuffle in
5218 def SSE_PSHUFB : OpndItins<
5219 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5221 let Sched = WriteVecALU in
5222 def SSE_PSIGN : OpndItins<
5223 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5225 let Sched = WriteVecIMul in
5226 def SSE_PMULHRSW : OpndItins<
5227 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5230 /// SS3I_binop_rm - Simple SSSE3 bin op
5231 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5232 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5233 X86MemOperand x86memop, OpndItins itins,
5235 let isCommutable = 1 in
5236 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5237 (ins RC:$src1, RC:$src2),
5239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5241 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5242 OpSize, Sched<[itins.Sched]>;
5243 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5244 (ins RC:$src1, x86memop:$src2),
5246 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5247 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5249 (OpVT (OpNode RC:$src1,
5250 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5251 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5254 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5255 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5256 Intrinsic IntId128, OpndItins itins,
5258 let isCommutable = 1 in
5259 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5260 (ins VR128:$src1, VR128:$src2),
5262 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5263 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5264 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5265 OpSize, Sched<[itins.Sched]>;
5266 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5267 (ins VR128:$src1, i128mem:$src2),
5269 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5270 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5272 (IntId128 VR128:$src1,
5273 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5274 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5277 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5278 Intrinsic IntId256> {
5279 let isCommutable = 1 in
5280 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5281 (ins VR256:$src1, VR256:$src2),
5282 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5283 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5285 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5286 (ins VR256:$src1, i256mem:$src2),
5287 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5289 (IntId256 VR256:$src1,
5290 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5293 let ImmT = NoImm, Predicates = [HasAVX] in {
5294 let isCommutable = 0 in {
5295 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5296 memopv2i64, i128mem,
5297 SSE_PHADDSUBW, 0>, VEX_4V;
5298 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5299 memopv2i64, i128mem,
5300 SSE_PHADDSUBD, 0>, VEX_4V;
5301 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5302 memopv2i64, i128mem,
5303 SSE_PHADDSUBW, 0>, VEX_4V;
5304 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5305 memopv2i64, i128mem,
5306 SSE_PHADDSUBD, 0>, VEX_4V;
5307 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5308 memopv2i64, i128mem,
5309 SSE_PSIGN, 0>, VEX_4V;
5310 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5311 memopv2i64, i128mem,
5312 SSE_PSIGN, 0>, VEX_4V;
5313 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5314 memopv2i64, i128mem,
5315 SSE_PSIGN, 0>, VEX_4V;
5316 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5317 memopv2i64, i128mem,
5318 SSE_PSHUFB, 0>, VEX_4V;
5319 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5320 int_x86_ssse3_phadd_sw_128,
5321 SSE_PHADDSUBSW, 0>, VEX_4V;
5322 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5323 int_x86_ssse3_phsub_sw_128,
5324 SSE_PHADDSUBSW, 0>, VEX_4V;
5325 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5326 int_x86_ssse3_pmadd_ub_sw_128,
5327 SSE_PMADD, 0>, VEX_4V;
5329 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5330 int_x86_ssse3_pmul_hr_sw_128,
5331 SSE_PMULHRSW, 0>, VEX_4V;
5334 let ImmT = NoImm, Predicates = [HasAVX2] in {
5335 let isCommutable = 0 in {
5336 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5337 memopv4i64, i256mem,
5338 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5339 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5340 memopv4i64, i256mem,
5341 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5342 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5343 memopv4i64, i256mem,
5344 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5345 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5346 memopv4i64, i256mem,
5347 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5348 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5349 memopv4i64, i256mem,
5350 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5351 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5352 memopv4i64, i256mem,
5353 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5354 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5355 memopv4i64, i256mem,
5356 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5357 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5358 memopv4i64, i256mem,
5359 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5360 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5361 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5362 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5363 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5364 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5365 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5367 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5368 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5371 // None of these have i8 immediate fields.
5372 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5373 let isCommutable = 0 in {
5374 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5375 memopv2i64, i128mem, SSE_PHADDSUBW>;
5376 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5377 memopv2i64, i128mem, SSE_PHADDSUBD>;
5378 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5379 memopv2i64, i128mem, SSE_PHADDSUBW>;
5380 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5381 memopv2i64, i128mem, SSE_PHADDSUBD>;
5382 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5383 memopv2i64, i128mem, SSE_PSIGN>;
5384 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5385 memopv2i64, i128mem, SSE_PSIGN>;
5386 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5387 memopv2i64, i128mem, SSE_PSIGN>;
5388 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5389 memopv2i64, i128mem, SSE_PSHUFB>;
5390 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5391 int_x86_ssse3_phadd_sw_128,
5393 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5394 int_x86_ssse3_phsub_sw_128,
5396 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5397 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5399 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5400 int_x86_ssse3_pmul_hr_sw_128,
5404 //===---------------------------------------------------------------------===//
5405 // SSSE3 - Packed Align Instruction Patterns
5406 //===---------------------------------------------------------------------===//
5408 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5409 let neverHasSideEffects = 1 in {
5410 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5411 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5413 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5415 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5416 [], IIC_SSE_PALIGNRR>, OpSize, Sched<[WriteShuffle]>;
5418 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5419 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5421 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5423 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5424 [], IIC_SSE_PALIGNRM>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5428 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5429 let neverHasSideEffects = 1 in {
5430 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5431 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5433 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5434 []>, OpSize, Sched<[WriteShuffle]>;
5436 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5437 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5439 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5440 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5444 let Predicates = [HasAVX] in
5445 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5446 let Predicates = [HasAVX2] in
5447 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5448 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5449 defm PALIGN : ssse3_palignr<"palignr">;
5451 let Predicates = [HasAVX2] in {
5452 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5453 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5454 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5455 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5456 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5457 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5458 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5459 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5462 let Predicates = [HasAVX] in {
5463 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5464 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5465 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5466 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5467 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5468 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5469 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5470 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5473 let Predicates = [UseSSSE3] in {
5474 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5475 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5476 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5477 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5478 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5479 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5480 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5481 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5484 //===---------------------------------------------------------------------===//
5485 // SSSE3 - Thread synchronization
5486 //===---------------------------------------------------------------------===//
5488 let SchedRW = [WriteSystem] in {
5489 let usesCustomInserter = 1 in {
5490 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5491 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5492 Requires<[HasSSE3]>;
5495 let Uses = [EAX, ECX, EDX] in
5496 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5497 TB, Requires<[HasSSE3]>;
5498 let Uses = [ECX, EAX] in
5499 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5500 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5501 TB, Requires<[HasSSE3]>;
5504 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[In32BitMode]>;
5505 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5507 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5508 Requires<[In32BitMode]>;
5509 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5510 Requires<[In64BitMode]>;
5512 //===----------------------------------------------------------------------===//
5513 // SSE4.1 - Packed Move with Sign/Zero Extend
5514 //===----------------------------------------------------------------------===//
5516 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5517 OpndItins itins = DEFAULT_ITINS> {
5518 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5519 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5520 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5522 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5523 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5525 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5529 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5531 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5532 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5533 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5535 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5536 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5537 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5541 let Predicates = [HasAVX] in {
5542 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5543 int_x86_sse41_pmovsxbw>, VEX;
5544 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5545 int_x86_sse41_pmovsxwd>, VEX;
5546 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5547 int_x86_sse41_pmovsxdq>, VEX;
5548 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5549 int_x86_sse41_pmovzxbw>, VEX;
5550 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5551 int_x86_sse41_pmovzxwd>, VEX;
5552 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5553 int_x86_sse41_pmovzxdq>, VEX;
5556 let Predicates = [HasAVX2] in {
5557 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5558 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5559 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5560 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5561 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5562 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5563 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5564 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5565 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5566 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5567 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5568 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5571 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw, SSE_INTALU_ITINS_P>;
5572 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd, SSE_INTALU_ITINS_P>;
5573 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq, SSE_INTALU_ITINS_P>;
5574 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw, SSE_INTALU_ITINS_P>;
5575 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd, SSE_INTALU_ITINS_P>;
5576 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq, SSE_INTALU_ITINS_P>;
5578 let Predicates = [HasAVX] in {
5579 // Common patterns involving scalar load.
5580 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5581 (VPMOVSXBWrm addr:$src)>;
5582 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5583 (VPMOVSXBWrm addr:$src)>;
5584 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5585 (VPMOVSXBWrm addr:$src)>;
5587 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5588 (VPMOVSXWDrm addr:$src)>;
5589 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5590 (VPMOVSXWDrm addr:$src)>;
5591 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5592 (VPMOVSXWDrm addr:$src)>;
5594 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5595 (VPMOVSXDQrm addr:$src)>;
5596 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5597 (VPMOVSXDQrm addr:$src)>;
5598 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5599 (VPMOVSXDQrm addr:$src)>;
5601 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5602 (VPMOVZXBWrm addr:$src)>;
5603 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5604 (VPMOVZXBWrm addr:$src)>;
5605 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5606 (VPMOVZXBWrm addr:$src)>;
5608 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5609 (VPMOVZXWDrm addr:$src)>;
5610 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5611 (VPMOVZXWDrm addr:$src)>;
5612 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5613 (VPMOVZXWDrm addr:$src)>;
5615 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5616 (VPMOVZXDQrm addr:$src)>;
5617 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5618 (VPMOVZXDQrm addr:$src)>;
5619 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5620 (VPMOVZXDQrm addr:$src)>;
5623 let Predicates = [UseSSE41] in {
5624 // Common patterns involving scalar load.
5625 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5626 (PMOVSXBWrm addr:$src)>;
5627 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5628 (PMOVSXBWrm addr:$src)>;
5629 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5630 (PMOVSXBWrm addr:$src)>;
5632 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5633 (PMOVSXWDrm addr:$src)>;
5634 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5635 (PMOVSXWDrm addr:$src)>;
5636 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5637 (PMOVSXWDrm addr:$src)>;
5639 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5640 (PMOVSXDQrm addr:$src)>;
5641 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5642 (PMOVSXDQrm addr:$src)>;
5643 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5644 (PMOVSXDQrm addr:$src)>;
5646 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5647 (PMOVZXBWrm addr:$src)>;
5648 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5649 (PMOVZXBWrm addr:$src)>;
5650 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5651 (PMOVZXBWrm addr:$src)>;
5653 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5654 (PMOVZXWDrm addr:$src)>;
5655 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5656 (PMOVZXWDrm addr:$src)>;
5657 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5658 (PMOVZXWDrm addr:$src)>;
5660 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5661 (PMOVZXDQrm addr:$src)>;
5662 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5663 (PMOVZXDQrm addr:$src)>;
5664 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5665 (PMOVZXDQrm addr:$src)>;
5668 let Predicates = [HasAVX2] in {
5669 let AddedComplexity = 15 in {
5670 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5671 (VPMOVZXDQYrr VR128:$src)>;
5672 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5673 (VPMOVZXWDYrr VR128:$src)>;
5676 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5677 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5680 let Predicates = [HasAVX] in {
5681 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5682 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5685 let Predicates = [UseSSE41] in {
5686 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5687 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5691 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5692 OpndItins itins = DEFAULT_ITINS> {
5693 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5694 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5695 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5697 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5698 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5700 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
5705 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5707 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5708 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5709 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5711 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5712 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5714 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5718 let Predicates = [HasAVX] in {
5719 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5721 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5723 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5725 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5729 let Predicates = [HasAVX2] in {
5730 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5731 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5732 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5733 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5734 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5735 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5736 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5737 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5740 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
5741 SSE_INTALU_ITINS_P>;
5742 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
5743 SSE_INTALU_ITINS_P>;
5744 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
5745 SSE_INTALU_ITINS_P>;
5746 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
5747 SSE_INTALU_ITINS_P>;
5749 let Predicates = [HasAVX] in {
5750 // Common patterns involving scalar load
5751 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5752 (VPMOVSXBDrm addr:$src)>;
5753 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5754 (VPMOVSXWQrm addr:$src)>;
5756 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5757 (VPMOVZXBDrm addr:$src)>;
5758 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5759 (VPMOVZXWQrm addr:$src)>;
5762 let Predicates = [UseSSE41] in {
5763 // Common patterns involving scalar load
5764 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5765 (PMOVSXBDrm addr:$src)>;
5766 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5767 (PMOVSXWQrm addr:$src)>;
5769 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5770 (PMOVZXBDrm addr:$src)>;
5771 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5772 (PMOVZXWQrm addr:$src)>;
5775 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5776 OpndItins itins = DEFAULT_ITINS> {
5777 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5778 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5779 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5781 // Expecting a i16 load any extended to i32 value.
5782 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5783 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5784 [(set VR128:$dst, (IntId (bitconvert
5785 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5789 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5791 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5792 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5793 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5795 // Expecting a i16 load any extended to i32 value.
5796 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5797 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5798 [(set VR256:$dst, (IntId (bitconvert
5799 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5803 let Predicates = [HasAVX] in {
5804 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5806 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5809 let Predicates = [HasAVX2] in {
5810 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5811 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5812 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5813 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5815 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
5816 SSE_INTALU_ITINS_P>;
5817 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
5818 SSE_INTALU_ITINS_P>;
5820 let Predicates = [HasAVX2] in {
5821 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5822 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5823 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
5825 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5826 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
5828 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5830 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
5831 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5832 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
5833 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5834 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
5835 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5837 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
5838 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5839 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
5840 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5842 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
5843 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5845 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5846 (VPMOVSXWDYrm addr:$src)>;
5847 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5848 (VPMOVSXDQYrm addr:$src)>;
5850 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5851 (scalar_to_vector (loadi64 addr:$src))))))),
5852 (VPMOVSXBDYrm addr:$src)>;
5853 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5854 (scalar_to_vector (loadf64 addr:$src))))))),
5855 (VPMOVSXBDYrm addr:$src)>;
5857 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5858 (scalar_to_vector (loadi64 addr:$src))))))),
5859 (VPMOVSXWQYrm addr:$src)>;
5860 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5861 (scalar_to_vector (loadf64 addr:$src))))))),
5862 (VPMOVSXWQYrm addr:$src)>;
5864 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5865 (scalar_to_vector (loadi32 addr:$src))))))),
5866 (VPMOVSXBQYrm addr:$src)>;
5869 let Predicates = [HasAVX] in {
5870 // Common patterns involving scalar load
5871 def : Pat<(int_x86_sse41_pmovsxbq
5872 (bitconvert (v4i32 (X86vzmovl
5873 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5874 (VPMOVSXBQrm addr:$src)>;
5876 def : Pat<(int_x86_sse41_pmovzxbq
5877 (bitconvert (v4i32 (X86vzmovl
5878 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5879 (VPMOVZXBQrm addr:$src)>;
5882 let Predicates = [UseSSE41] in {
5883 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5884 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
5885 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
5887 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5888 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
5890 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5892 // Common patterns involving scalar load
5893 def : Pat<(int_x86_sse41_pmovsxbq
5894 (bitconvert (v4i32 (X86vzmovl
5895 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5896 (PMOVSXBQrm addr:$src)>;
5898 def : Pat<(int_x86_sse41_pmovzxbq
5899 (bitconvert (v4i32 (X86vzmovl
5900 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5901 (PMOVZXBQrm addr:$src)>;
5903 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5904 (scalar_to_vector (loadi64 addr:$src))))))),
5905 (PMOVSXWDrm addr:$src)>;
5906 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5907 (scalar_to_vector (loadf64 addr:$src))))))),
5908 (PMOVSXWDrm addr:$src)>;
5909 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5910 (scalar_to_vector (loadi32 addr:$src))))))),
5911 (PMOVSXBDrm addr:$src)>;
5912 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5913 (scalar_to_vector (loadi32 addr:$src))))))),
5914 (PMOVSXWQrm addr:$src)>;
5915 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5916 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5917 (PMOVSXBQrm addr:$src)>;
5918 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5919 (scalar_to_vector (loadi64 addr:$src))))))),
5920 (PMOVSXDQrm addr:$src)>;
5921 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5922 (scalar_to_vector (loadf64 addr:$src))))))),
5923 (PMOVSXDQrm addr:$src)>;
5924 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5925 (scalar_to_vector (loadi64 addr:$src))))))),
5926 (PMOVSXBWrm addr:$src)>;
5927 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5928 (scalar_to_vector (loadf64 addr:$src))))))),
5929 (PMOVSXBWrm addr:$src)>;
5932 let Predicates = [HasAVX2] in {
5933 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5934 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5935 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5937 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5938 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5940 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5942 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5943 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5944 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5945 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5946 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5947 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5949 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5950 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5951 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5952 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5954 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5955 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5958 let Predicates = [HasAVX] in {
5959 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5960 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5961 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5963 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5964 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5966 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5968 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5969 (VPMOVZXBWrm addr:$src)>;
5970 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5971 (VPMOVZXBWrm addr:$src)>;
5972 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5973 (VPMOVZXBDrm addr:$src)>;
5974 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5975 (VPMOVZXBQrm addr:$src)>;
5977 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5978 (VPMOVZXWDrm addr:$src)>;
5979 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5980 (VPMOVZXWDrm addr:$src)>;
5981 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5982 (VPMOVZXWQrm addr:$src)>;
5984 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5985 (VPMOVZXDQrm addr:$src)>;
5986 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5987 (VPMOVZXDQrm addr:$src)>;
5988 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5989 (VPMOVZXDQrm addr:$src)>;
5991 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5992 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
5993 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
5995 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5996 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
5998 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
6000 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6001 (scalar_to_vector (loadi64 addr:$src))))))),
6002 (VPMOVSXWDrm addr:$src)>;
6003 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6004 (scalar_to_vector (loadi64 addr:$src))))))),
6005 (VPMOVSXDQrm addr:$src)>;
6006 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6007 (scalar_to_vector (loadf64 addr:$src))))))),
6008 (VPMOVSXWDrm addr:$src)>;
6009 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6010 (scalar_to_vector (loadf64 addr:$src))))))),
6011 (VPMOVSXDQrm addr:$src)>;
6012 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6013 (scalar_to_vector (loadi64 addr:$src))))))),
6014 (VPMOVSXBWrm addr:$src)>;
6015 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6016 (scalar_to_vector (loadf64 addr:$src))))))),
6017 (VPMOVSXBWrm addr:$src)>;
6019 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6020 (scalar_to_vector (loadi32 addr:$src))))))),
6021 (VPMOVSXBDrm addr:$src)>;
6022 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6023 (scalar_to_vector (loadi32 addr:$src))))))),
6024 (VPMOVSXWQrm addr:$src)>;
6025 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6026 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6027 (VPMOVSXBQrm addr:$src)>;
6030 let Predicates = [UseSSE41] in {
6031 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6032 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6033 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6035 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6036 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6038 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6040 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6041 (PMOVZXBWrm addr:$src)>;
6042 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6043 (PMOVZXBWrm addr:$src)>;
6044 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6045 (PMOVZXBDrm addr:$src)>;
6046 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6047 (PMOVZXBQrm addr:$src)>;
6049 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6050 (PMOVZXWDrm addr:$src)>;
6051 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6052 (PMOVZXWDrm addr:$src)>;
6053 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6054 (PMOVZXWQrm addr:$src)>;
6056 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6057 (PMOVZXDQrm addr:$src)>;
6058 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6059 (PMOVZXDQrm addr:$src)>;
6060 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6061 (PMOVZXDQrm addr:$src)>;
6064 //===----------------------------------------------------------------------===//
6065 // SSE4.1 - Extract Instructions
6066 //===----------------------------------------------------------------------===//
6068 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6069 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6070 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6071 (ins VR128:$src1, i32i8imm:$src2),
6072 !strconcat(OpcodeStr,
6073 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6074 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
6076 let neverHasSideEffects = 1, mayStore = 1 in
6077 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6078 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6079 !strconcat(OpcodeStr,
6080 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6083 // There's an AssertZext in the way of writing the store pattern
6084 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6087 let Predicates = [HasAVX] in {
6088 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6089 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
6090 (ins VR128:$src1, i32i8imm:$src2),
6091 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
6094 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6097 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6098 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6099 let neverHasSideEffects = 1, mayStore = 1 in
6100 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6101 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6102 !strconcat(OpcodeStr,
6103 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6106 // There's an AssertZext in the way of writing the store pattern
6107 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6110 let Predicates = [HasAVX] in
6111 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6113 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6116 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6117 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6118 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6119 (ins VR128:$src1, i32i8imm:$src2),
6120 !strconcat(OpcodeStr,
6121 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6123 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6124 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6125 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6126 !strconcat(OpcodeStr,
6127 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6128 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6129 addr:$dst)]>, OpSize;
6132 let Predicates = [HasAVX] in
6133 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6135 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6137 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6138 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6139 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6140 (ins VR128:$src1, i32i8imm:$src2),
6141 !strconcat(OpcodeStr,
6142 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6144 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6145 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6146 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6147 !strconcat(OpcodeStr,
6148 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6149 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6150 addr:$dst)]>, OpSize, REX_W;
6153 let Predicates = [HasAVX] in
6154 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6156 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6158 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6160 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6161 OpndItins itins = DEFAULT_ITINS> {
6162 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6163 (ins VR128:$src1, i32i8imm:$src2),
6164 !strconcat(OpcodeStr,
6165 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6167 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6170 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6171 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6172 !strconcat(OpcodeStr,
6173 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6174 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6175 addr:$dst)], itins.rm>, OpSize;
6178 let ExeDomain = SSEPackedSingle in {
6179 let Predicates = [UseAVX] in {
6180 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6181 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6182 (ins VR128:$src1, i32i8imm:$src2),
6183 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6186 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6189 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6190 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6193 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6195 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6198 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6199 Requires<[UseSSE41]>;
6201 //===----------------------------------------------------------------------===//
6202 // SSE4.1 - Insert Instructions
6203 //===----------------------------------------------------------------------===//
6205 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6206 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6207 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6209 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6211 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6213 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6214 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6215 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6217 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6219 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6221 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6222 imm:$src3))]>, OpSize;
6225 let Predicates = [HasAVX] in
6226 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6227 let Constraints = "$src1 = $dst" in
6228 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6230 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6231 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6232 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6234 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6236 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6238 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6240 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6241 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6243 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6245 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6247 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6248 imm:$src3)))]>, OpSize;
6251 let Predicates = [HasAVX] in
6252 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6253 let Constraints = "$src1 = $dst" in
6254 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6256 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6257 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6258 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6260 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6262 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6264 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6266 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6267 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6269 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6271 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6273 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6274 imm:$src3)))]>, OpSize;
6277 let Predicates = [HasAVX] in
6278 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6279 let Constraints = "$src1 = $dst" in
6280 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6282 // insertps has a few different modes, there's the first two here below which
6283 // are optimized inserts that won't zero arbitrary elements in the destination
6284 // vector. The next one matches the intrinsic and could zero arbitrary elements
6285 // in the target vector.
6286 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6287 OpndItins itins = DEFAULT_ITINS> {
6288 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6289 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6291 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6293 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6295 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6297 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6298 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6300 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6302 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6304 (X86insrtps VR128:$src1,
6305 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6306 imm:$src3))], itins.rm>, OpSize;
6309 let ExeDomain = SSEPackedSingle in {
6310 let Predicates = [HasAVX] in
6311 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6312 let Constraints = "$src1 = $dst" in
6313 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6316 //===----------------------------------------------------------------------===//
6317 // SSE4.1 - Round Instructions
6318 //===----------------------------------------------------------------------===//
6320 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6321 X86MemOperand x86memop, RegisterClass RC,
6322 PatFrag mem_frag32, PatFrag mem_frag64,
6323 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6324 let ExeDomain = SSEPackedSingle in {
6325 // Intrinsic operation, reg.
6326 // Vector intrinsic operation, reg
6327 def PSr : SS4AIi8<opcps, MRMSrcReg,
6328 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6329 !strconcat(OpcodeStr,
6330 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6331 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6332 IIC_SSE_ROUNDPS_REG>,
6335 // Vector intrinsic operation, mem
6336 def PSm : SS4AIi8<opcps, MRMSrcMem,
6337 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6338 !strconcat(OpcodeStr,
6339 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6341 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6342 IIC_SSE_ROUNDPS_MEM>,
6344 } // ExeDomain = SSEPackedSingle
6346 let ExeDomain = SSEPackedDouble in {
6347 // Vector intrinsic operation, reg
6348 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6349 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6350 !strconcat(OpcodeStr,
6351 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6352 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6353 IIC_SSE_ROUNDPS_REG>,
6356 // Vector intrinsic operation, mem
6357 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6358 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6359 !strconcat(OpcodeStr,
6360 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6362 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6363 IIC_SSE_ROUNDPS_REG>,
6365 } // ExeDomain = SSEPackedDouble
6368 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6371 Intrinsic F64Int, bit Is2Addr = 1> {
6372 let ExeDomain = GenericDomain in {
6374 let hasSideEffects = 0 in
6375 def SSr : SS4AIi8<opcss, MRMSrcReg,
6376 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6378 !strconcat(OpcodeStr,
6379 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6380 !strconcat(OpcodeStr,
6381 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6384 // Intrinsic operation, reg.
6385 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6386 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6388 !strconcat(OpcodeStr,
6389 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6390 !strconcat(OpcodeStr,
6391 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6392 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6395 // Intrinsic operation, mem.
6396 def SSm : SS4AIi8<opcss, MRMSrcMem,
6397 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6399 !strconcat(OpcodeStr,
6400 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6401 !strconcat(OpcodeStr,
6402 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6404 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6408 let hasSideEffects = 0 in
6409 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6410 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6412 !strconcat(OpcodeStr,
6413 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6414 !strconcat(OpcodeStr,
6415 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6418 // Intrinsic operation, reg.
6419 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6420 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6422 !strconcat(OpcodeStr,
6423 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6424 !strconcat(OpcodeStr,
6425 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6426 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6429 // Intrinsic operation, mem.
6430 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6431 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6433 !strconcat(OpcodeStr,
6434 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6435 !strconcat(OpcodeStr,
6436 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6438 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6440 } // ExeDomain = GenericDomain
6443 // FP round - roundss, roundps, roundsd, roundpd
6444 let Predicates = [HasAVX] in {
6446 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6447 memopv4f32, memopv2f64,
6448 int_x86_sse41_round_ps,
6449 int_x86_sse41_round_pd>, VEX;
6450 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6451 memopv8f32, memopv4f64,
6452 int_x86_avx_round_ps_256,
6453 int_x86_avx_round_pd_256>, VEX, VEX_L;
6454 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6455 int_x86_sse41_round_ss,
6456 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6458 def : Pat<(ffloor FR32:$src),
6459 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6460 def : Pat<(f64 (ffloor FR64:$src)),
6461 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6462 def : Pat<(f32 (fnearbyint FR32:$src)),
6463 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6464 def : Pat<(f64 (fnearbyint FR64:$src)),
6465 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6466 def : Pat<(f32 (fceil FR32:$src)),
6467 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6468 def : Pat<(f64 (fceil FR64:$src)),
6469 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6470 def : Pat<(f32 (frint FR32:$src)),
6471 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6472 def : Pat<(f64 (frint FR64:$src)),
6473 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6474 def : Pat<(f32 (ftrunc FR32:$src)),
6475 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6476 def : Pat<(f64 (ftrunc FR64:$src)),
6477 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6479 def : Pat<(v4f32 (ffloor VR128:$src)),
6480 (VROUNDPSr VR128:$src, (i32 0x1))>;
6481 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6482 (VROUNDPSr VR128:$src, (i32 0xC))>;
6483 def : Pat<(v4f32 (fceil VR128:$src)),
6484 (VROUNDPSr VR128:$src, (i32 0x2))>;
6485 def : Pat<(v4f32 (frint VR128:$src)),
6486 (VROUNDPSr VR128:$src, (i32 0x4))>;
6487 def : Pat<(v4f32 (ftrunc VR128:$src)),
6488 (VROUNDPSr VR128:$src, (i32 0x3))>;
6490 def : Pat<(v2f64 (ffloor VR128:$src)),
6491 (VROUNDPDr VR128:$src, (i32 0x1))>;
6492 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6493 (VROUNDPDr VR128:$src, (i32 0xC))>;
6494 def : Pat<(v2f64 (fceil VR128:$src)),
6495 (VROUNDPDr VR128:$src, (i32 0x2))>;
6496 def : Pat<(v2f64 (frint VR128:$src)),
6497 (VROUNDPDr VR128:$src, (i32 0x4))>;
6498 def : Pat<(v2f64 (ftrunc VR128:$src)),
6499 (VROUNDPDr VR128:$src, (i32 0x3))>;
6501 def : Pat<(v8f32 (ffloor VR256:$src)),
6502 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6503 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6504 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6505 def : Pat<(v8f32 (fceil VR256:$src)),
6506 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6507 def : Pat<(v8f32 (frint VR256:$src)),
6508 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6509 def : Pat<(v8f32 (ftrunc VR256:$src)),
6510 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6512 def : Pat<(v4f64 (ffloor VR256:$src)),
6513 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6514 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6515 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6516 def : Pat<(v4f64 (fceil VR256:$src)),
6517 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6518 def : Pat<(v4f64 (frint VR256:$src)),
6519 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6520 def : Pat<(v4f64 (ftrunc VR256:$src)),
6521 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6524 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6525 memopv4f32, memopv2f64,
6526 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6527 let Constraints = "$src1 = $dst" in
6528 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6529 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6531 let Predicates = [UseSSE41] in {
6532 def : Pat<(ffloor FR32:$src),
6533 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6534 def : Pat<(f64 (ffloor FR64:$src)),
6535 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6536 def : Pat<(f32 (fnearbyint FR32:$src)),
6537 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6538 def : Pat<(f64 (fnearbyint FR64:$src)),
6539 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6540 def : Pat<(f32 (fceil FR32:$src)),
6541 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6542 def : Pat<(f64 (fceil FR64:$src)),
6543 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6544 def : Pat<(f32 (frint FR32:$src)),
6545 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6546 def : Pat<(f64 (frint FR64:$src)),
6547 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6548 def : Pat<(f32 (ftrunc FR32:$src)),
6549 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6550 def : Pat<(f64 (ftrunc FR64:$src)),
6551 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6553 def : Pat<(v4f32 (ffloor VR128:$src)),
6554 (ROUNDPSr VR128:$src, (i32 0x1))>;
6555 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6556 (ROUNDPSr VR128:$src, (i32 0xC))>;
6557 def : Pat<(v4f32 (fceil VR128:$src)),
6558 (ROUNDPSr VR128:$src, (i32 0x2))>;
6559 def : Pat<(v4f32 (frint VR128:$src)),
6560 (ROUNDPSr VR128:$src, (i32 0x4))>;
6561 def : Pat<(v4f32 (ftrunc VR128:$src)),
6562 (ROUNDPSr VR128:$src, (i32 0x3))>;
6564 def : Pat<(v2f64 (ffloor VR128:$src)),
6565 (ROUNDPDr VR128:$src, (i32 0x1))>;
6566 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6567 (ROUNDPDr VR128:$src, (i32 0xC))>;
6568 def : Pat<(v2f64 (fceil VR128:$src)),
6569 (ROUNDPDr VR128:$src, (i32 0x2))>;
6570 def : Pat<(v2f64 (frint VR128:$src)),
6571 (ROUNDPDr VR128:$src, (i32 0x4))>;
6572 def : Pat<(v2f64 (ftrunc VR128:$src)),
6573 (ROUNDPDr VR128:$src, (i32 0x3))>;
6576 //===----------------------------------------------------------------------===//
6577 // SSE4.1 - Packed Bit Test
6578 //===----------------------------------------------------------------------===//
6580 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6581 // the intel intrinsic that corresponds to this.
6582 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6583 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6584 "vptest\t{$src2, $src1|$src1, $src2}",
6585 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6587 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6588 "vptest\t{$src2, $src1|$src1, $src2}",
6589 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6592 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6593 "vptest\t{$src2, $src1|$src1, $src2}",
6594 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6596 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6597 "vptest\t{$src2, $src1|$src1, $src2}",
6598 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6602 let Defs = [EFLAGS] in {
6603 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6604 "ptest\t{$src2, $src1|$src1, $src2}",
6605 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6607 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6608 "ptest\t{$src2, $src1|$src1, $src2}",
6609 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6613 // The bit test instructions below are AVX only
6614 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6615 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6616 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6617 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6618 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6619 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6620 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6621 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6625 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6626 let ExeDomain = SSEPackedSingle in {
6627 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6628 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6631 let ExeDomain = SSEPackedDouble in {
6632 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6633 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6638 //===----------------------------------------------------------------------===//
6639 // SSE4.1 - Misc Instructions
6640 //===----------------------------------------------------------------------===//
6642 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6643 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6644 "popcnt{w}\t{$src, $dst|$dst, $src}",
6645 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6648 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6649 "popcnt{w}\t{$src, $dst|$dst, $src}",
6650 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6651 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize, XS;
6653 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6654 "popcnt{l}\t{$src, $dst|$dst, $src}",
6655 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6658 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6659 "popcnt{l}\t{$src, $dst|$dst, $src}",
6660 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6661 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6663 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6664 "popcnt{q}\t{$src, $dst|$dst, $src}",
6665 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6668 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6669 "popcnt{q}\t{$src, $dst|$dst, $src}",
6670 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6671 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6676 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6677 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6678 Intrinsic IntId128> {
6679 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6681 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6682 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6683 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6685 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6688 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6691 let Predicates = [HasAVX] in
6692 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6693 int_x86_sse41_phminposuw>, VEX;
6694 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6695 int_x86_sse41_phminposuw>;
6697 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6698 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6699 Intrinsic IntId128, bit Is2Addr = 1,
6700 OpndItins itins = DEFAULT_ITINS> {
6701 let isCommutable = 1 in
6702 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6703 (ins VR128:$src1, VR128:$src2),
6705 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6706 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6707 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
6709 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6710 (ins VR128:$src1, i128mem:$src2),
6712 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6713 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6715 (IntId128 VR128:$src1,
6716 (bitconvert (memopv2i64 addr:$src2))))],
6720 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6721 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6722 Intrinsic IntId256> {
6723 let isCommutable = 1 in
6724 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6725 (ins VR256:$src1, VR256:$src2),
6726 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6727 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6728 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6729 (ins VR256:$src1, i256mem:$src2),
6730 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6732 (IntId256 VR256:$src1,
6733 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6737 /// SS48I_binop_rm - Simple SSE41 binary operator.
6738 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6739 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6740 X86MemOperand x86memop, bit Is2Addr = 1,
6741 OpndItins itins = DEFAULT_ITINS> {
6742 let isCommutable = 1 in
6743 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6744 (ins RC:$src1, RC:$src2),
6746 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6747 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6748 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6749 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6750 (ins RC:$src1, x86memop:$src2),
6752 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6753 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6755 (OpVT (OpNode RC:$src1,
6756 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6759 let Predicates = [HasAVX] in {
6760 let isCommutable = 0 in
6761 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6763 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6764 memopv2i64, i128mem, 0>, VEX_4V;
6765 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6766 memopv2i64, i128mem, 0>, VEX_4V;
6767 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6768 memopv2i64, i128mem, 0>, VEX_4V;
6769 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6770 memopv2i64, i128mem, 0>, VEX_4V;
6771 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6772 memopv2i64, i128mem, 0>, VEX_4V;
6773 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6774 memopv2i64, i128mem, 0>, VEX_4V;
6775 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6776 memopv2i64, i128mem, 0>, VEX_4V;
6777 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6778 memopv2i64, i128mem, 0>, VEX_4V;
6779 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6783 let Predicates = [HasAVX2] in {
6784 let isCommutable = 0 in
6785 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6786 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6787 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6788 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6789 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6790 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6791 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6792 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6793 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6794 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6795 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6796 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6797 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6798 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6799 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6800 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6801 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6802 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6803 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6804 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6807 let Constraints = "$src1 = $dst" in {
6808 let isCommutable = 0 in
6809 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6810 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6811 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6812 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6813 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6814 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6815 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6816 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6817 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6818 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6819 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6820 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6821 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6822 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6823 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6824 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6825 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6826 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq,
6827 1, SSE_INTMUL_ITINS_P>;
6830 let Predicates = [HasAVX] in {
6831 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6832 memopv2i64, i128mem, 0>, VEX_4V;
6833 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6834 memopv2i64, i128mem, 0>, VEX_4V;
6836 let Predicates = [HasAVX2] in {
6837 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6838 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6839 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6840 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6843 let Constraints = "$src1 = $dst" in {
6844 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6845 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6846 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6847 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6850 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6851 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6852 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6853 X86MemOperand x86memop, bit Is2Addr = 1,
6854 OpndItins itins = DEFAULT_ITINS> {
6855 let isCommutable = 1 in
6856 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6857 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6859 !strconcat(OpcodeStr,
6860 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6861 !strconcat(OpcodeStr,
6862 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6863 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6865 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6866 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6868 !strconcat(OpcodeStr,
6869 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6870 !strconcat(OpcodeStr,
6871 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6874 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6878 let Predicates = [HasAVX] in {
6879 let isCommutable = 0 in {
6880 let ExeDomain = SSEPackedSingle in {
6881 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6882 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6883 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6884 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6885 f256mem, 0>, VEX_4V, VEX_L;
6887 let ExeDomain = SSEPackedDouble in {
6888 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6889 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6890 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6891 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6892 f256mem, 0>, VEX_4V, VEX_L;
6894 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6895 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6896 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6897 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6899 let ExeDomain = SSEPackedSingle in
6900 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6901 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6902 let ExeDomain = SSEPackedDouble in
6903 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6904 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6905 let ExeDomain = SSEPackedSingle in
6906 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6907 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6910 let Predicates = [HasAVX2] in {
6911 let isCommutable = 0 in {
6912 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6913 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6914 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6915 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6919 let Constraints = "$src1 = $dst" in {
6920 let isCommutable = 0 in {
6921 let ExeDomain = SSEPackedSingle in
6922 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6923 VR128, memopv4f32, f128mem,
6924 1, SSE_INTALU_ITINS_P>;
6925 let ExeDomain = SSEPackedDouble in
6926 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6927 VR128, memopv2f64, f128mem,
6928 1, SSE_INTALU_ITINS_P>;
6929 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6930 VR128, memopv2i64, i128mem,
6931 1, SSE_INTALU_ITINS_P>;
6932 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6933 VR128, memopv2i64, i128mem,
6934 1, SSE_INTMUL_ITINS_P>;
6936 let ExeDomain = SSEPackedSingle in
6937 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6938 VR128, memopv4f32, f128mem, 1,
6940 let ExeDomain = SSEPackedDouble in
6941 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6942 VR128, memopv2f64, f128mem, 1,
6946 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6947 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6948 RegisterClass RC, X86MemOperand x86memop,
6949 PatFrag mem_frag, Intrinsic IntId> {
6950 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6951 (ins RC:$src1, RC:$src2, RC:$src3),
6952 !strconcat(OpcodeStr,
6953 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6954 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6955 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6957 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6958 (ins RC:$src1, x86memop:$src2, RC:$src3),
6959 !strconcat(OpcodeStr,
6960 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6962 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6964 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6967 let Predicates = [HasAVX] in {
6968 let ExeDomain = SSEPackedDouble in {
6969 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6970 memopv2f64, int_x86_sse41_blendvpd>;
6971 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6972 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6973 } // ExeDomain = SSEPackedDouble
6974 let ExeDomain = SSEPackedSingle in {
6975 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6976 memopv4f32, int_x86_sse41_blendvps>;
6977 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6978 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6979 } // ExeDomain = SSEPackedSingle
6980 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6981 memopv2i64, int_x86_sse41_pblendvb>;
6984 let Predicates = [HasAVX2] in {
6985 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6986 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6989 let Predicates = [HasAVX] in {
6990 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6991 (v16i8 VR128:$src2))),
6992 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6993 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6994 (v4i32 VR128:$src2))),
6995 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6996 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6997 (v4f32 VR128:$src2))),
6998 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6999 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7000 (v2i64 VR128:$src2))),
7001 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7002 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7003 (v2f64 VR128:$src2))),
7004 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7005 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7006 (v8i32 VR256:$src2))),
7007 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7008 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7009 (v8f32 VR256:$src2))),
7010 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7011 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7012 (v4i64 VR256:$src2))),
7013 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7014 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7015 (v4f64 VR256:$src2))),
7016 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7018 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7020 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7021 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7023 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7025 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7027 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7028 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7030 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7031 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7033 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7036 let Predicates = [HasAVX2] in {
7037 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7038 (v32i8 VR256:$src2))),
7039 (VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
7040 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7042 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7045 /// SS41I_ternary_int - SSE 4.1 ternary operator
7046 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7047 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7048 X86MemOperand x86memop, Intrinsic IntId,
7049 OpndItins itins = DEFAULT_ITINS> {
7050 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7051 (ins VR128:$src1, VR128:$src2),
7052 !strconcat(OpcodeStr,
7053 "\t{$src2, $dst|$dst, $src2}"),
7054 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7057 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7058 (ins VR128:$src1, x86memop:$src2),
7059 !strconcat(OpcodeStr,
7060 "\t{$src2, $dst|$dst, $src2}"),
7063 (bitconvert (mem_frag addr:$src2)), XMM0))],
7068 let ExeDomain = SSEPackedDouble in
7069 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7070 int_x86_sse41_blendvpd>;
7071 let ExeDomain = SSEPackedSingle in
7072 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7073 int_x86_sse41_blendvps>;
7074 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7075 int_x86_sse41_pblendvb>;
7077 // Aliases with the implicit xmm0 argument
7078 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7079 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7080 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7081 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7082 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7083 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7084 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7085 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7086 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7087 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7088 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7089 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7091 let Predicates = [UseSSE41] in {
7092 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7093 (v16i8 VR128:$src2))),
7094 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7095 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7096 (v4i32 VR128:$src2))),
7097 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7098 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7099 (v4f32 VR128:$src2))),
7100 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7101 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7102 (v2i64 VR128:$src2))),
7103 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7104 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7105 (v2f64 VR128:$src2))),
7106 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7108 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7110 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7111 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7113 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7114 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7116 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7120 let Predicates = [HasAVX] in
7121 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7122 "vmovntdqa\t{$src, $dst|$dst, $src}",
7123 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7125 let Predicates = [HasAVX2] in
7126 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7127 "vmovntdqa\t{$src, $dst|$dst, $src}",
7128 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7130 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7131 "movntdqa\t{$src, $dst|$dst, $src}",
7132 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7135 //===----------------------------------------------------------------------===//
7136 // SSE4.2 - Compare Instructions
7137 //===----------------------------------------------------------------------===//
7139 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7140 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7141 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7142 X86MemOperand x86memop, bit Is2Addr = 1> {
7143 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7144 (ins RC:$src1, RC:$src2),
7146 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7147 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7148 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7150 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7151 (ins RC:$src1, x86memop:$src2),
7153 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7154 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7156 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7159 let Predicates = [HasAVX] in
7160 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7161 memopv2i64, i128mem, 0>, VEX_4V;
7163 let Predicates = [HasAVX2] in
7164 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7165 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
7167 let Constraints = "$src1 = $dst" in
7168 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7169 memopv2i64, i128mem>;
7171 //===----------------------------------------------------------------------===//
7172 // SSE4.2 - String/text Processing Instructions
7173 //===----------------------------------------------------------------------===//
7175 // Packed Compare Implicit Length Strings, Return Mask
7176 multiclass pseudo_pcmpistrm<string asm> {
7177 def REG : PseudoI<(outs VR128:$dst),
7178 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7179 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7181 def MEM : PseudoI<(outs VR128:$dst),
7182 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7183 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7184 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7187 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7188 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7189 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7192 multiclass pcmpistrm_SS42AI<string asm> {
7193 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7194 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7195 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7198 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7199 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7200 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7204 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7205 let Predicates = [HasAVX] in
7206 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7207 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7210 // Packed Compare Explicit Length Strings, Return Mask
7211 multiclass pseudo_pcmpestrm<string asm> {
7212 def REG : PseudoI<(outs VR128:$dst),
7213 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7214 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7215 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7216 def MEM : PseudoI<(outs VR128:$dst),
7217 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7218 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7219 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7222 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7223 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7224 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7227 multiclass SS42AI_pcmpestrm<string asm> {
7228 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7229 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7230 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7233 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7234 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7235 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7239 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7240 let Predicates = [HasAVX] in
7241 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7242 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7245 // Packed Compare Implicit Length Strings, Return Index
7246 multiclass pseudo_pcmpistri<string asm> {
7247 def REG : PseudoI<(outs GR32:$dst),
7248 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7249 [(set GR32:$dst, EFLAGS,
7250 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7251 def MEM : PseudoI<(outs GR32:$dst),
7252 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7253 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7254 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7257 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7258 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7259 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7262 multiclass SS42AI_pcmpistri<string asm> {
7263 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7264 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7265 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7268 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7269 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7270 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7274 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7275 let Predicates = [HasAVX] in
7276 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7277 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7280 // Packed Compare Explicit Length Strings, Return Index
7281 multiclass pseudo_pcmpestri<string asm> {
7282 def REG : PseudoI<(outs GR32:$dst),
7283 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7284 [(set GR32:$dst, EFLAGS,
7285 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7286 def MEM : PseudoI<(outs GR32:$dst),
7287 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7288 [(set GR32:$dst, EFLAGS,
7289 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7293 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7294 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7295 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7298 multiclass SS42AI_pcmpestri<string asm> {
7299 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7300 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7301 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7304 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7305 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7306 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7310 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7311 let Predicates = [HasAVX] in
7312 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7313 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7316 //===----------------------------------------------------------------------===//
7317 // SSE4.2 - CRC Instructions
7318 //===----------------------------------------------------------------------===//
7320 // No CRC instructions have AVX equivalents
7322 // crc intrinsic instruction
7323 // This set of instructions are only rm, the only difference is the size
7325 let Constraints = "$src1 = $dst" in {
7326 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7327 (ins GR32:$src1, i8mem:$src2),
7328 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7330 (int_x86_sse42_crc32_32_8 GR32:$src1,
7331 (load addr:$src2)))], IIC_CRC32_MEM>;
7332 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7333 (ins GR32:$src1, GR8:$src2),
7334 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7336 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))],
7338 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7339 (ins GR32:$src1, i16mem:$src2),
7340 "crc32{w}\t{$src2, $src1|$src1, $src2}",
7342 (int_x86_sse42_crc32_32_16 GR32:$src1,
7343 (load addr:$src2)))], IIC_CRC32_MEM>,
7345 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7346 (ins GR32:$src1, GR16:$src2),
7347 "crc32{w}\t{$src2, $src1|$src1, $src2}",
7349 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))],
7352 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7353 (ins GR32:$src1, i32mem:$src2),
7354 "crc32{l}\t{$src2, $src1|$src1, $src2}",
7356 (int_x86_sse42_crc32_32_32 GR32:$src1,
7357 (load addr:$src2)))], IIC_CRC32_MEM>;
7358 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7359 (ins GR32:$src1, GR32:$src2),
7360 "crc32{l}\t{$src2, $src1|$src1, $src2}",
7362 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))],
7364 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7365 (ins GR64:$src1, i8mem:$src2),
7366 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7368 (int_x86_sse42_crc32_64_8 GR64:$src1,
7369 (load addr:$src2)))], IIC_CRC32_MEM>,
7371 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7372 (ins GR64:$src1, GR8:$src2),
7373 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7375 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))],
7378 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7379 (ins GR64:$src1, i64mem:$src2),
7380 "crc32{q}\t{$src2, $src1|$src1, $src2}",
7382 (int_x86_sse42_crc32_64_64 GR64:$src1,
7383 (load addr:$src2)))], IIC_CRC32_MEM>,
7385 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7386 (ins GR64:$src1, GR64:$src2),
7387 "crc32{q}\t{$src2, $src1|$src1, $src2}",
7389 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))],
7394 //===----------------------------------------------------------------------===//
7395 // SHA-NI Instructions
7396 //===----------------------------------------------------------------------===//
7398 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr> {
7399 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7400 (ins VR128:$src1, VR128:$src2),
7401 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), []>, T8;
7404 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7405 (ins VR128:$src1, i128mem:$src2),
7406 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), []>, T8;
7409 let Constraints = "$src1 = $dst", hasSideEffects = 0, Predicates = [HasSHA] in {
7410 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7411 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7412 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7415 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7416 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7417 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7420 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte">;
7421 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1">;
7422 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2">;
7425 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2">;
7427 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1">;
7428 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2">;
7431 // Aliases with explicit %xmm0
7432 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7433 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7434 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7435 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7437 //===----------------------------------------------------------------------===//
7438 // AES-NI Instructions
7439 //===----------------------------------------------------------------------===//
7441 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7442 Intrinsic IntId128, bit Is2Addr = 1> {
7443 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7444 (ins VR128:$src1, VR128:$src2),
7446 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7447 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7448 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7450 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7451 (ins VR128:$src1, i128mem:$src2),
7453 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7454 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7456 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7459 // Perform One Round of an AES Encryption/Decryption Flow
7460 let Predicates = [HasAVX, HasAES] in {
7461 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7462 int_x86_aesni_aesenc, 0>, VEX_4V;
7463 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7464 int_x86_aesni_aesenclast, 0>, VEX_4V;
7465 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7466 int_x86_aesni_aesdec, 0>, VEX_4V;
7467 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7468 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7471 let Constraints = "$src1 = $dst" in {
7472 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7473 int_x86_aesni_aesenc>;
7474 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7475 int_x86_aesni_aesenclast>;
7476 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7477 int_x86_aesni_aesdec>;
7478 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7479 int_x86_aesni_aesdeclast>;
7482 // Perform the AES InvMixColumn Transformation
7483 let Predicates = [HasAVX, HasAES] in {
7484 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7486 "vaesimc\t{$src1, $dst|$dst, $src1}",
7488 (int_x86_aesni_aesimc VR128:$src1))]>,
7490 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7491 (ins i128mem:$src1),
7492 "vaesimc\t{$src1, $dst|$dst, $src1}",
7493 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7496 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7498 "aesimc\t{$src1, $dst|$dst, $src1}",
7500 (int_x86_aesni_aesimc VR128:$src1))]>,
7502 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7503 (ins i128mem:$src1),
7504 "aesimc\t{$src1, $dst|$dst, $src1}",
7505 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7508 // AES Round Key Generation Assist
7509 let Predicates = [HasAVX, HasAES] in {
7510 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7511 (ins VR128:$src1, i8imm:$src2),
7512 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7514 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7516 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7517 (ins i128mem:$src1, i8imm:$src2),
7518 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7520 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7523 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7524 (ins VR128:$src1, i8imm:$src2),
7525 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7527 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7529 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7530 (ins i128mem:$src1, i8imm:$src2),
7531 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7533 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7536 //===----------------------------------------------------------------------===//
7537 // PCLMUL Instructions
7538 //===----------------------------------------------------------------------===//
7540 // AVX carry-less Multiplication instructions
7541 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7542 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7543 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7545 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7547 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7548 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7549 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7550 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7551 (memopv2i64 addr:$src2), imm:$src3))]>;
7553 // Carry-less Multiplication instructions
7554 let Constraints = "$src1 = $dst" in {
7555 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7556 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7557 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7559 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7560 IIC_SSE_PCLMULQDQ_RR>;
7562 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7563 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7564 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7565 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7566 (memopv2i64 addr:$src2), imm:$src3))],
7567 IIC_SSE_PCLMULQDQ_RM>;
7568 } // Constraints = "$src1 = $dst"
7571 multiclass pclmul_alias<string asm, int immop> {
7572 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7573 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7575 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7576 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7578 def : InstAlias<!strconcat("vpclmul", asm,
7579 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7580 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7582 def : InstAlias<!strconcat("vpclmul", asm,
7583 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7584 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7586 defm : pclmul_alias<"hqhq", 0x11>;
7587 defm : pclmul_alias<"hqlq", 0x01>;
7588 defm : pclmul_alias<"lqhq", 0x10>;
7589 defm : pclmul_alias<"lqlq", 0x00>;
7591 //===----------------------------------------------------------------------===//
7592 // SSE4A Instructions
7593 //===----------------------------------------------------------------------===//
7595 let Predicates = [HasSSE4A] in {
7597 let Constraints = "$src = $dst" in {
7598 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7599 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7600 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7601 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7602 imm:$idx))]>, TB, OpSize;
7603 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7604 (ins VR128:$src, VR128:$mask),
7605 "extrq\t{$mask, $src|$src, $mask}",
7606 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7607 VR128:$mask))]>, TB, OpSize;
7609 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7610 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7611 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7612 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7613 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7614 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7615 (ins VR128:$src, VR128:$mask),
7616 "insertq\t{$mask, $src|$src, $mask}",
7617 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7618 VR128:$mask))]>, XD;
7621 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7622 "movntss\t{$src, $dst|$dst, $src}",
7623 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7625 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7626 "movntsd\t{$src, $dst|$dst, $src}",
7627 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7630 //===----------------------------------------------------------------------===//
7632 //===----------------------------------------------------------------------===//
7634 //===----------------------------------------------------------------------===//
7635 // VBROADCAST - Load from memory and broadcast to all elements of the
7636 // destination operand
7638 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7639 X86MemOperand x86memop, Intrinsic Int> :
7640 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7641 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7642 [(set RC:$dst, (Int addr:$src))]>, VEX;
7644 // AVX2 adds register forms
7645 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7647 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7648 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7649 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7651 let ExeDomain = SSEPackedSingle in {
7652 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7653 int_x86_avx_vbroadcast_ss>;
7654 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7655 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7657 let ExeDomain = SSEPackedDouble in
7658 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7659 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7660 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7661 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7663 let ExeDomain = SSEPackedSingle in {
7664 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7665 int_x86_avx2_vbroadcast_ss_ps>;
7666 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7667 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7669 let ExeDomain = SSEPackedDouble in
7670 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7671 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7673 let Predicates = [HasAVX2] in
7674 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7675 int_x86_avx2_vbroadcasti128>, VEX_L;
7677 let Predicates = [HasAVX] in
7678 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7679 (VBROADCASTF128 addr:$src)>;
7682 //===----------------------------------------------------------------------===//
7683 // VINSERTF128 - Insert packed floating-point values
7685 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7686 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7687 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7688 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7691 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7692 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7693 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7697 let Predicates = [HasAVX] in {
7698 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7700 (VINSERTF128rr VR256:$src1, VR128:$src2,
7701 (INSERT_get_vinsert128_imm VR256:$ins))>;
7702 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7704 (VINSERTF128rr VR256:$src1, VR128:$src2,
7705 (INSERT_get_vinsert128_imm VR256:$ins))>;
7707 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7709 (VINSERTF128rm VR256:$src1, addr:$src2,
7710 (INSERT_get_vinsert128_imm VR256:$ins))>;
7711 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7713 (VINSERTF128rm VR256:$src1, addr:$src2,
7714 (INSERT_get_vinsert128_imm VR256:$ins))>;
7717 let Predicates = [HasAVX1Only] in {
7718 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7720 (VINSERTF128rr VR256:$src1, VR128:$src2,
7721 (INSERT_get_vinsert128_imm VR256:$ins))>;
7722 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7724 (VINSERTF128rr VR256:$src1, VR128:$src2,
7725 (INSERT_get_vinsert128_imm VR256:$ins))>;
7726 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7728 (VINSERTF128rr VR256:$src1, VR128:$src2,
7729 (INSERT_get_vinsert128_imm VR256:$ins))>;
7730 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7732 (VINSERTF128rr VR256:$src1, VR128:$src2,
7733 (INSERT_get_vinsert128_imm VR256:$ins))>;
7735 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7737 (VINSERTF128rm VR256:$src1, addr:$src2,
7738 (INSERT_get_vinsert128_imm VR256:$ins))>;
7739 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7740 (bc_v4i32 (memopv2i64 addr:$src2)),
7742 (VINSERTF128rm VR256:$src1, addr:$src2,
7743 (INSERT_get_vinsert128_imm VR256:$ins))>;
7744 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7745 (bc_v16i8 (memopv2i64 addr:$src2)),
7747 (VINSERTF128rm VR256:$src1, addr:$src2,
7748 (INSERT_get_vinsert128_imm VR256:$ins))>;
7749 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7750 (bc_v8i16 (memopv2i64 addr:$src2)),
7752 (VINSERTF128rm VR256:$src1, addr:$src2,
7753 (INSERT_get_vinsert128_imm VR256:$ins))>;
7756 //===----------------------------------------------------------------------===//
7757 // VEXTRACTF128 - Extract packed floating-point values
7759 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7760 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7761 (ins VR256:$src1, i8imm:$src2),
7762 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7765 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7766 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7767 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7772 let Predicates = [HasAVX] in {
7773 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7774 (v4f32 (VEXTRACTF128rr
7775 (v8f32 VR256:$src1),
7776 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7777 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7778 (v2f64 (VEXTRACTF128rr
7779 (v4f64 VR256:$src1),
7780 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7782 def : Pat<(alignedstore (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7783 (iPTR imm))), addr:$dst),
7784 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7785 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7786 def : Pat<(alignedstore (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7787 (iPTR imm))), addr:$dst),
7788 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7789 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7792 let Predicates = [HasAVX1Only] in {
7793 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7794 (v2i64 (VEXTRACTF128rr
7795 (v4i64 VR256:$src1),
7796 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7797 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7798 (v4i32 (VEXTRACTF128rr
7799 (v8i32 VR256:$src1),
7800 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7801 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7802 (v8i16 (VEXTRACTF128rr
7803 (v16i16 VR256:$src1),
7804 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7805 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7806 (v16i8 (VEXTRACTF128rr
7807 (v32i8 VR256:$src1),
7808 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7810 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7811 (iPTR imm))), addr:$dst),
7812 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7813 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7814 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7815 (iPTR imm))), addr:$dst),
7816 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7817 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7818 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7819 (iPTR imm))), addr:$dst),
7820 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7821 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7822 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7823 (iPTR imm))), addr:$dst),
7824 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7825 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7828 //===----------------------------------------------------------------------===//
7829 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7831 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7832 Intrinsic IntLd, Intrinsic IntLd256,
7833 Intrinsic IntSt, Intrinsic IntSt256> {
7834 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7835 (ins VR128:$src1, f128mem:$src2),
7836 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7837 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7839 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7840 (ins VR256:$src1, f256mem:$src2),
7841 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7842 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7844 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7845 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7847 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7848 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7849 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7850 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7851 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7854 let ExeDomain = SSEPackedSingle in
7855 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7856 int_x86_avx_maskload_ps,
7857 int_x86_avx_maskload_ps_256,
7858 int_x86_avx_maskstore_ps,
7859 int_x86_avx_maskstore_ps_256>;
7860 let ExeDomain = SSEPackedDouble in
7861 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7862 int_x86_avx_maskload_pd,
7863 int_x86_avx_maskload_pd_256,
7864 int_x86_avx_maskstore_pd,
7865 int_x86_avx_maskstore_pd_256>;
7867 //===----------------------------------------------------------------------===//
7868 // VPERMIL - Permute Single and Double Floating-Point Values
7870 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7871 RegisterClass RC, X86MemOperand x86memop_f,
7872 X86MemOperand x86memop_i, PatFrag i_frag,
7873 Intrinsic IntVar, ValueType vt> {
7874 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7875 (ins RC:$src1, RC:$src2),
7876 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7877 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7878 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7879 (ins RC:$src1, x86memop_i:$src2),
7880 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7881 [(set RC:$dst, (IntVar RC:$src1,
7882 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7884 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7885 (ins RC:$src1, i8imm:$src2),
7886 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7887 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7888 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7889 (ins x86memop_f:$src1, i8imm:$src2),
7890 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7892 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7895 let ExeDomain = SSEPackedSingle in {
7896 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7897 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7898 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7899 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7901 let ExeDomain = SSEPackedDouble in {
7902 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7903 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7904 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7905 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7908 let Predicates = [HasAVX] in {
7909 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7910 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7911 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7912 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7913 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7915 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7916 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7917 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7919 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7920 (VPERMILPDri VR128:$src1, imm:$imm)>;
7921 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7922 (VPERMILPDmi addr:$src1, imm:$imm)>;
7925 //===----------------------------------------------------------------------===//
7926 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7928 let ExeDomain = SSEPackedSingle in {
7929 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7930 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7931 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7932 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7933 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7934 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7935 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7936 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7937 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7938 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7941 let Predicates = [HasAVX] in {
7942 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7943 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7944 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7945 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7946 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7949 let Predicates = [HasAVX1Only] in {
7950 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7951 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7952 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7953 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7954 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7955 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7956 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7957 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7959 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7960 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7961 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7962 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7963 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7964 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7965 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7966 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7967 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7968 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7969 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7970 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7973 //===----------------------------------------------------------------------===//
7974 // VZERO - Zero YMM registers
7976 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7977 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7978 // Zero All YMM registers
7979 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7980 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7982 // Zero Upper bits of YMM registers
7983 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7984 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7987 //===----------------------------------------------------------------------===//
7988 // Half precision conversion instructions
7989 //===----------------------------------------------------------------------===//
7990 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7991 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7992 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7993 [(set RC:$dst, (Int VR128:$src))]>,
7995 let neverHasSideEffects = 1, mayLoad = 1 in
7996 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7997 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
8000 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8001 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8002 (ins RC:$src1, i32i8imm:$src2),
8003 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8004 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8006 let neverHasSideEffects = 1, mayStore = 1 in
8007 def mr : Ii8<0x1D, MRMDestMem, (outs),
8008 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8009 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8013 let Predicates = [HasF16C] in {
8014 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8015 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8016 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8017 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8020 //===----------------------------------------------------------------------===//
8021 // AVX2 Instructions
8022 //===----------------------------------------------------------------------===//
8024 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8025 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8026 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8027 X86MemOperand x86memop> {
8028 let isCommutable = 1 in
8029 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8030 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
8031 !strconcat(OpcodeStr,
8032 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8033 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8035 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8036 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
8037 !strconcat(OpcodeStr,
8038 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8041 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8045 let isCommutable = 0 in {
8046 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8047 VR128, memopv2i64, i128mem>;
8048 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8049 VR256, memopv4i64, i256mem>, VEX_L;
8052 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8054 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8055 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8057 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8059 //===----------------------------------------------------------------------===//
8060 // VPBROADCAST - Load from memory and broadcast to all elements of the
8061 // destination operand
8063 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8064 X86MemOperand x86memop, PatFrag ld_frag,
8065 Intrinsic Int128, Intrinsic Int256> {
8066 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8067 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8068 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
8069 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8070 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8072 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
8073 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8074 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8075 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
8076 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8077 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8079 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8083 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8084 int_x86_avx2_pbroadcastb_128,
8085 int_x86_avx2_pbroadcastb_256>;
8086 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8087 int_x86_avx2_pbroadcastw_128,
8088 int_x86_avx2_pbroadcastw_256>;
8089 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8090 int_x86_avx2_pbroadcastd_128,
8091 int_x86_avx2_pbroadcastd_256>;
8092 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8093 int_x86_avx2_pbroadcastq_128,
8094 int_x86_avx2_pbroadcastq_256>;
8096 let Predicates = [HasAVX2] in {
8097 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8098 (VPBROADCASTBrm addr:$src)>;
8099 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8100 (VPBROADCASTBYrm addr:$src)>;
8101 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8102 (VPBROADCASTWrm addr:$src)>;
8103 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8104 (VPBROADCASTWYrm addr:$src)>;
8105 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8106 (VPBROADCASTDrm addr:$src)>;
8107 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8108 (VPBROADCASTDYrm addr:$src)>;
8109 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8110 (VPBROADCASTQrm addr:$src)>;
8111 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8112 (VPBROADCASTQYrm addr:$src)>;
8114 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8115 (VPBROADCASTBrr VR128:$src)>;
8116 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8117 (VPBROADCASTBYrr VR128:$src)>;
8118 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8119 (VPBROADCASTWrr VR128:$src)>;
8120 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8121 (VPBROADCASTWYrr VR128:$src)>;
8122 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8123 (VPBROADCASTDrr VR128:$src)>;
8124 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8125 (VPBROADCASTDYrr VR128:$src)>;
8126 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8127 (VPBROADCASTQrr VR128:$src)>;
8128 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8129 (VPBROADCASTQYrr VR128:$src)>;
8130 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8131 (VBROADCASTSSrr VR128:$src)>;
8132 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8133 (VBROADCASTSSYrr VR128:$src)>;
8134 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8135 (VPBROADCASTQrr VR128:$src)>;
8136 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8137 (VBROADCASTSDYrr VR128:$src)>;
8139 // Provide fallback in case the load node that is used in the patterns above
8140 // is used by additional users, which prevents the pattern selection.
8141 let AddedComplexity = 20 in {
8142 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8143 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8144 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8145 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8146 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8147 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8149 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8150 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8151 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8152 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8153 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8154 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8158 // AVX1 broadcast patterns
8159 let Predicates = [HasAVX1Only] in {
8160 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8161 (VBROADCASTSSYrm addr:$src)>;
8162 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8163 (VBROADCASTSDYrm addr:$src)>;
8164 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8165 (VBROADCASTSSrm addr:$src)>;
8168 let Predicates = [HasAVX] in {
8169 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8170 (VBROADCASTSSYrm addr:$src)>;
8171 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8172 (VBROADCASTSDYrm addr:$src)>;
8173 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8174 (VBROADCASTSSrm addr:$src)>;
8176 // Provide fallback in case the load node that is used in the patterns above
8177 // is used by additional users, which prevents the pattern selection.
8178 let AddedComplexity = 20 in {
8179 // 128bit broadcasts:
8180 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8181 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8182 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8183 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8184 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8185 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8186 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8187 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8188 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8189 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8191 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8192 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8193 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8194 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8195 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8196 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8197 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8198 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8199 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8200 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8204 //===----------------------------------------------------------------------===//
8205 // VPERM - Permute instructions
8208 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8210 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8211 (ins VR256:$src1, VR256:$src2),
8212 !strconcat(OpcodeStr,
8213 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8215 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8217 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8218 (ins VR256:$src1, i256mem:$src2),
8219 !strconcat(OpcodeStr,
8220 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8222 (OpVT (X86VPermv VR256:$src1,
8223 (bitconvert (mem_frag addr:$src2)))))]>,
8227 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
8228 let ExeDomain = SSEPackedSingle in
8229 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
8231 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8233 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8234 (ins VR256:$src1, i8imm:$src2),
8235 !strconcat(OpcodeStr,
8236 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8238 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8240 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8241 (ins i256mem:$src1, i8imm:$src2),
8242 !strconcat(OpcodeStr,
8243 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8245 (OpVT (X86VPermi (mem_frag addr:$src1),
8246 (i8 imm:$src2))))]>, VEX, VEX_L;
8249 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
8250 let ExeDomain = SSEPackedDouble in
8251 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
8253 //===----------------------------------------------------------------------===//
8254 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8256 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8257 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8258 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8259 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8260 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8261 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8262 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8263 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8264 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
8265 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8267 let Predicates = [HasAVX2] in {
8268 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8269 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8270 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8271 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8272 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8273 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8275 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
8277 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8278 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8279 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
8280 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8281 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
8283 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8287 //===----------------------------------------------------------------------===//
8288 // VINSERTI128 - Insert packed integer values
8290 let neverHasSideEffects = 1 in {
8291 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8292 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8293 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8296 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8297 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8298 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8302 let Predicates = [HasAVX2] in {
8303 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8305 (VINSERTI128rr VR256:$src1, VR128:$src2,
8306 (INSERT_get_vinsert128_imm VR256:$ins))>;
8307 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8309 (VINSERTI128rr VR256:$src1, VR128:$src2,
8310 (INSERT_get_vinsert128_imm VR256:$ins))>;
8311 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8313 (VINSERTI128rr VR256:$src1, VR128:$src2,
8314 (INSERT_get_vinsert128_imm VR256:$ins))>;
8315 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8317 (VINSERTI128rr VR256:$src1, VR128:$src2,
8318 (INSERT_get_vinsert128_imm VR256:$ins))>;
8320 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
8322 (VINSERTI128rm VR256:$src1, addr:$src2,
8323 (INSERT_get_vinsert128_imm VR256:$ins))>;
8324 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8325 (bc_v4i32 (memopv2i64 addr:$src2)),
8327 (VINSERTI128rm VR256:$src1, addr:$src2,
8328 (INSERT_get_vinsert128_imm VR256:$ins))>;
8329 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8330 (bc_v16i8 (memopv2i64 addr:$src2)),
8332 (VINSERTI128rm VR256:$src1, addr:$src2,
8333 (INSERT_get_vinsert128_imm VR256:$ins))>;
8334 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8335 (bc_v8i16 (memopv2i64 addr:$src2)),
8337 (VINSERTI128rm VR256:$src1, addr:$src2,
8338 (INSERT_get_vinsert128_imm VR256:$ins))>;
8341 //===----------------------------------------------------------------------===//
8342 // VEXTRACTI128 - Extract packed integer values
8344 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8345 (ins VR256:$src1, i8imm:$src2),
8346 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8348 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8350 let neverHasSideEffects = 1, mayStore = 1 in
8351 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8352 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8353 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8356 let Predicates = [HasAVX2] in {
8357 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8358 (v2i64 (VEXTRACTI128rr
8359 (v4i64 VR256:$src1),
8360 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8361 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8362 (v4i32 (VEXTRACTI128rr
8363 (v8i32 VR256:$src1),
8364 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8365 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8366 (v8i16 (VEXTRACTI128rr
8367 (v16i16 VR256:$src1),
8368 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8369 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8370 (v16i8 (VEXTRACTI128rr
8371 (v32i8 VR256:$src1),
8372 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8374 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8375 (iPTR imm))), addr:$dst),
8376 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8377 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8378 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8379 (iPTR imm))), addr:$dst),
8380 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8381 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8382 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8383 (iPTR imm))), addr:$dst),
8384 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8385 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8386 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8387 (iPTR imm))), addr:$dst),
8388 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8389 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8392 //===----------------------------------------------------------------------===//
8393 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8395 multiclass avx2_pmovmask<string OpcodeStr,
8396 Intrinsic IntLd128, Intrinsic IntLd256,
8397 Intrinsic IntSt128, Intrinsic IntSt256> {
8398 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8399 (ins VR128:$src1, i128mem:$src2),
8400 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8401 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8402 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8403 (ins VR256:$src1, i256mem:$src2),
8404 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8405 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8407 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8408 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8409 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8410 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8411 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8412 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8414 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8417 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8418 int_x86_avx2_maskload_d,
8419 int_x86_avx2_maskload_d_256,
8420 int_x86_avx2_maskstore_d,
8421 int_x86_avx2_maskstore_d_256>;
8422 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8423 int_x86_avx2_maskload_q,
8424 int_x86_avx2_maskload_q_256,
8425 int_x86_avx2_maskstore_q,
8426 int_x86_avx2_maskstore_q_256>, VEX_W;
8429 //===----------------------------------------------------------------------===//
8430 // Variable Bit Shifts
8432 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8433 ValueType vt128, ValueType vt256> {
8434 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8435 (ins VR128:$src1, VR128:$src2),
8436 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8438 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8440 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8441 (ins VR128:$src1, i128mem:$src2),
8442 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8444 (vt128 (OpNode VR128:$src1,
8445 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8447 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8448 (ins VR256:$src1, VR256:$src2),
8449 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8451 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8453 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8454 (ins VR256:$src1, i256mem:$src2),
8455 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8457 (vt256 (OpNode VR256:$src1,
8458 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8462 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8463 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8464 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8465 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8466 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8468 //===----------------------------------------------------------------------===//
8469 // VGATHER - GATHER Operations
8470 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8471 X86MemOperand memop128, X86MemOperand memop256> {
8472 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8473 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8474 !strconcat(OpcodeStr,
8475 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8477 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8478 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8479 !strconcat(OpcodeStr,
8480 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8481 []>, VEX_4VOp3, VEX_L;
8484 let mayLoad = 1, Constraints
8485 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8487 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8488 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8489 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8490 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8491 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8492 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8493 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8494 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;