1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def X86aesimc : SDNode<"X86ISD::AESIMC", SDTIntBinOp>;
73 def X86aesenc : SDNode<"X86ISD::AESENC", SDTIntBinOp>;
74 def X86aesenclast : SDNode<"X86ISD::AESENCLAST", SDTIntBinOp>;
75 def X86aesdec : SDNode<"X86ISD::AESDEC", SDTIntBinOp>;
76 def X86aesdeclast : SDNode<"X86ISD::AESDECLAST", SDTIntBinOp>;
78 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
81 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
83 //===----------------------------------------------------------------------===//
84 // SSE Complex Patterns
85 //===----------------------------------------------------------------------===//
87 // These are 'extloads' from a scalar to the low element of a vector, zeroing
88 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
90 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
91 [SDNPHasChain, SDNPMayLoad]>;
92 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
93 [SDNPHasChain, SDNPMayLoad]>;
95 def ssmem : Operand<v4f32> {
96 let PrintMethod = "printf32mem";
97 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
98 let ParserMatchClass = X86MemAsmOperand;
100 def sdmem : Operand<v2f64> {
101 let PrintMethod = "printf64mem";
102 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
103 let ParserMatchClass = X86MemAsmOperand;
106 //===----------------------------------------------------------------------===//
107 // SSE pattern fragments
108 //===----------------------------------------------------------------------===//
110 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
111 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
112 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
113 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
115 // Like 'store', but always requires vector alignment.
116 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
117 (store node:$val, node:$ptr), [{
118 return cast<StoreSDNode>(N)->getAlignment() >= 16;
121 // Like 'load', but always requires vector alignment.
122 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
123 return cast<LoadSDNode>(N)->getAlignment() >= 16;
126 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
127 (f32 (alignedload node:$ptr))>;
128 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
129 (f64 (alignedload node:$ptr))>;
130 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
131 (v4f32 (alignedload node:$ptr))>;
132 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
133 (v2f64 (alignedload node:$ptr))>;
134 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
135 (v4i32 (alignedload node:$ptr))>;
136 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
137 (v2i64 (alignedload node:$ptr))>;
139 // Like 'load', but uses special alignment checks suitable for use in
140 // memory operands in most SSE instructions, which are required to
141 // be naturally aligned on some targets but not on others. If the subtarget
142 // allows unaligned accesses, match any load, though this may require
143 // setting a feature bit in the processor (on startup, for example).
144 // Opteron 10h and later implement such a feature.
145 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
146 return Subtarget->hasVectorUAMem()
147 || cast<LoadSDNode>(N)->getAlignment() >= 16;
150 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
151 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
152 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
153 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
154 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
155 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
156 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
158 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
160 // FIXME: 8 byte alignment for mmx reads is not required
161 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
162 return cast<LoadSDNode>(N)->getAlignment() >= 8;
165 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
166 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
167 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
168 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
171 // Like 'store', but requires the non-temporal bit to be set
172 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
173 (st node:$val, node:$ptr), [{
174 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
175 return ST->isNonTemporal();
179 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
180 (st node:$val, node:$ptr), [{
181 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
182 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
183 ST->getAddressingMode() == ISD::UNINDEXED &&
184 ST->getAlignment() >= 16;
188 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
189 (st node:$val, node:$ptr), [{
190 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
191 return ST->isNonTemporal() &&
192 ST->getAlignment() < 16;
196 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
197 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
198 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
199 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
200 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
201 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
203 def vzmovl_v2i64 : PatFrag<(ops node:$src),
204 (bitconvert (v2i64 (X86vzmovl
205 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
206 def vzmovl_v4i32 : PatFrag<(ops node:$src),
207 (bitconvert (v4i32 (X86vzmovl
208 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
210 def vzload_v2i64 : PatFrag<(ops node:$src),
211 (bitconvert (v2i64 (X86vzload node:$src)))>;
214 def fp32imm0 : PatLeaf<(f32 fpimm), [{
215 return N->isExactlyValue(+0.0);
218 // BYTE_imm - Transform bit immediates into byte immediates.
219 def BYTE_imm : SDNodeXForm<imm, [{
220 // Transformation function: imm >> 3
221 return getI32Imm(N->getZExtValue() >> 3);
224 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
226 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShuffleSHUFImmediate(N));
230 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
236 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
242 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
244 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
245 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
248 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
251 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
254 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
255 (vector_shuffle node:$lhs, node:$rhs), [{
256 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
259 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
260 (vector_shuffle node:$lhs, node:$rhs), [{
261 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
264 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
265 (vector_shuffle node:$lhs, node:$rhs), [{
266 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
269 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
270 (vector_shuffle node:$lhs, node:$rhs), [{
271 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
274 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
275 (vector_shuffle node:$lhs, node:$rhs), [{
276 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
279 def movl : PatFrag<(ops node:$lhs, node:$rhs),
280 (vector_shuffle node:$lhs, node:$rhs), [{
281 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
284 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
285 (vector_shuffle node:$lhs, node:$rhs), [{
286 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
289 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
290 (vector_shuffle node:$lhs, node:$rhs), [{
291 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
294 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
295 (vector_shuffle node:$lhs, node:$rhs), [{
296 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
299 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
300 (vector_shuffle node:$lhs, node:$rhs), [{
301 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
304 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
305 (vector_shuffle node:$lhs, node:$rhs), [{
306 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
309 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
310 (vector_shuffle node:$lhs, node:$rhs), [{
311 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
314 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
315 (vector_shuffle node:$lhs, node:$rhs), [{
316 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
317 }], SHUFFLE_get_shuf_imm>;
319 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
320 (vector_shuffle node:$lhs, node:$rhs), [{
321 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
322 }], SHUFFLE_get_shuf_imm>;
324 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
325 (vector_shuffle node:$lhs, node:$rhs), [{
326 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
327 }], SHUFFLE_get_pshufhw_imm>;
329 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
330 (vector_shuffle node:$lhs, node:$rhs), [{
331 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
332 }], SHUFFLE_get_pshuflw_imm>;
334 def palign : PatFrag<(ops node:$lhs, node:$rhs),
335 (vector_shuffle node:$lhs, node:$rhs), [{
336 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
337 }], SHUFFLE_get_palign_imm>;
339 //===----------------------------------------------------------------------===//
340 // SSE scalar FP Instructions
341 //===----------------------------------------------------------------------===//
343 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
344 // instruction selection into a branch sequence.
345 let Uses = [EFLAGS], usesCustomInserter = 1 in {
346 def CMOV_FR32 : I<0, Pseudo,
347 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
348 "#CMOV_FR32 PSEUDO!",
349 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
351 def CMOV_FR64 : I<0, Pseudo,
352 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
353 "#CMOV_FR64 PSEUDO!",
354 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
356 def CMOV_V4F32 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V4F32 PSEUDO!",
360 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2F64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2F64 PSEUDO!",
366 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
368 def CMOV_V2I64 : I<0, Pseudo,
369 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
370 "#CMOV_V2I64 PSEUDO!",
372 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
376 //===----------------------------------------------------------------------===//
378 //===----------------------------------------------------------------------===//
380 // Move Instructions. Register-to-register movss is not used for FR32
381 // register copies because it's a partial register update; FsMOVAPSrr is
382 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
383 // because INSERT_SUBREG requires that the insert be implementable in terms of
384 // a copy, and just mentioned, we don't use movss for copies.
385 let Constraints = "$src1 = $dst" in
386 def MOVSSrr : SSI<0x10, MRMSrcReg,
387 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
388 "movss\t{$src2, $dst|$dst, $src2}",
389 [(set (v4f32 VR128:$dst),
390 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
392 // Extract the low 32-bit value from one vector and insert it into another.
393 let AddedComplexity = 15 in
394 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
395 (MOVSSrr (v4f32 VR128:$src1),
396 (EXTRACT_SUBREG (v4f32 VR128:$src2), x86_subreg_ss))>;
398 // Implicitly promote a 32-bit scalar to a vector.
399 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
400 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, x86_subreg_ss)>;
402 // Loading from memory automatically zeroing upper bits.
403 let canFoldAsLoad = 1, isReMaterializable = 1 in
404 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
405 "movss\t{$src, $dst|$dst, $src}",
406 [(set FR32:$dst, (loadf32 addr:$src))]>;
408 // MOVSSrm zeros the high parts of the register; represent this
409 // with SUBREG_TO_REG.
410 let AddedComplexity = 20 in {
411 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
412 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
413 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
414 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
415 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
416 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
419 // Store scalar value to memory.
420 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
421 "movss\t{$src, $dst|$dst, $src}",
422 [(store FR32:$src, addr:$dst)]>;
424 // Extract and store.
425 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
428 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
430 // Conversion instructions
431 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
432 "cvttss2si\t{$src, $dst|$dst, $src}",
433 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
434 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
435 "cvttss2si\t{$src, $dst|$dst, $src}",
436 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
437 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
438 "cvtsi2ss\t{$src, $dst|$dst, $src}",
439 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
440 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
441 "cvtsi2ss\t{$src, $dst|$dst, $src}",
442 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
444 // Match intrinsics which expect XMM operand(s).
445 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
446 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
447 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
448 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
450 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
451 "cvtss2si\t{$src, $dst|$dst, $src}",
452 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
453 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
454 "cvtss2si\t{$src, $dst|$dst, $src}",
455 [(set GR32:$dst, (int_x86_sse_cvtss2si
456 (load addr:$src)))]>;
458 // Match intrinisics which expect MM and XMM operand(s).
459 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
460 "cvtps2pi\t{$src, $dst|$dst, $src}",
461 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
462 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
463 "cvtps2pi\t{$src, $dst|$dst, $src}",
464 [(set VR64:$dst, (int_x86_sse_cvtps2pi
465 (load addr:$src)))]>;
466 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
467 "cvttps2pi\t{$src, $dst|$dst, $src}",
468 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
469 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
470 "cvttps2pi\t{$src, $dst|$dst, $src}",
471 [(set VR64:$dst, (int_x86_sse_cvttps2pi
472 (load addr:$src)))]>;
473 let Constraints = "$src1 = $dst" in {
474 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
475 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
476 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
477 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
479 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
480 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
481 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
482 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
483 (load addr:$src2)))]>;
486 // Aliases for intrinsics
487 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
488 "cvttss2si\t{$src, $dst|$dst, $src}",
490 (int_x86_sse_cvttss2si VR128:$src))]>;
491 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
492 "cvttss2si\t{$src, $dst|$dst, $src}",
494 (int_x86_sse_cvttss2si(load addr:$src)))]>;
496 let Constraints = "$src1 = $dst" in {
497 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
498 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
499 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
500 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
502 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
503 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
504 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
505 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
506 (loadi32 addr:$src2)))]>;
509 // Comparison instructions
510 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
511 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
512 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
513 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
515 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
516 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
517 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
520 let Defs = [EFLAGS] in {
521 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
522 "ucomiss\t{$src2, $src1|$src1, $src2}",
523 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
524 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
525 "ucomiss\t{$src2, $src1|$src1, $src2}",
526 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
528 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
529 "comiss\t{$src2, $src1|$src1, $src2}", []>;
530 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
531 "comiss\t{$src2, $src1|$src1, $src2}", []>;
535 // Aliases to match intrinsics which expect XMM operand(s).
536 let Constraints = "$src1 = $dst" in {
537 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
539 (ins VR128:$src1, VR128:$src, SSECC:$cc),
540 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
541 [(set VR128:$dst, (int_x86_sse_cmp_ss
543 VR128:$src, imm:$cc))]>;
544 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
546 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
547 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
548 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
549 (load addr:$src), imm:$cc))]>;
552 let Defs = [EFLAGS] in {
553 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
554 "ucomiss\t{$src2, $src1|$src1, $src2}",
555 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
557 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
558 "ucomiss\t{$src2, $src1|$src1, $src2}",
559 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
560 (load addr:$src2)))]>;
562 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
563 "comiss\t{$src2, $src1|$src1, $src2}",
564 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
566 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
567 "comiss\t{$src2, $src1|$src1, $src2}",
568 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
569 (load addr:$src2)))]>;
572 // Aliases of packed SSE1 instructions for scalar use. These all have names
573 // that start with 'Fs'.
575 // Alias instructions that map fld0 to pxor for sse.
576 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
578 // FIXME: Set encoding to pseudo!
579 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
580 [(set FR32:$dst, fp32imm0)]>,
581 Requires<[HasSSE1]>, TB, OpSize;
583 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
585 let neverHasSideEffects = 1 in
586 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
587 "movaps\t{$src, $dst|$dst, $src}", []>;
589 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
591 let canFoldAsLoad = 1, isReMaterializable = 1 in
592 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
593 "movaps\t{$src, $dst|$dst, $src}",
594 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
596 // Alias bitwise logical operations using SSE logical ops on packed FP values.
597 let Constraints = "$src1 = $dst" in {
598 let isCommutable = 1 in {
599 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
600 (ins FR32:$src1, FR32:$src2),
601 "andps\t{$src2, $dst|$dst, $src2}",
602 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
603 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
604 (ins FR32:$src1, FR32:$src2),
605 "orps\t{$src2, $dst|$dst, $src2}",
606 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
607 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
608 (ins FR32:$src1, FR32:$src2),
609 "xorps\t{$src2, $dst|$dst, $src2}",
610 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
613 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
614 (ins FR32:$src1, f128mem:$src2),
615 "andps\t{$src2, $dst|$dst, $src2}",
616 [(set FR32:$dst, (X86fand FR32:$src1,
617 (memopfsf32 addr:$src2)))]>;
618 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
619 (ins FR32:$src1, f128mem:$src2),
620 "orps\t{$src2, $dst|$dst, $src2}",
621 [(set FR32:$dst, (X86for FR32:$src1,
622 (memopfsf32 addr:$src2)))]>;
623 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
624 (ins FR32:$src1, f128mem:$src2),
625 "xorps\t{$src2, $dst|$dst, $src2}",
626 [(set FR32:$dst, (X86fxor FR32:$src1,
627 (memopfsf32 addr:$src2)))]>;
629 let neverHasSideEffects = 1 in {
630 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
631 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
632 "andnps\t{$src2, $dst|$dst, $src2}", []>;
634 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
635 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
636 "andnps\t{$src2, $dst|$dst, $src2}", []>;
640 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
642 /// In addition, we also have a special variant of the scalar form here to
643 /// represent the associated intrinsic operation. This form is unlike the
644 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
645 /// and leaves the top elements unmodified (therefore these cannot be commuted).
647 /// These three forms can each be reg+reg or reg+mem, so there are a total of
648 /// six "instructions".
650 let Constraints = "$src1 = $dst" in {
651 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
652 SDNode OpNode, Intrinsic F32Int,
653 bit Commutable = 0> {
654 // Scalar operation, reg+reg.
655 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
656 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
657 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
658 let isCommutable = Commutable;
661 // Scalar operation, reg+mem.
662 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
663 (ins FR32:$src1, f32mem:$src2),
664 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
665 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
667 // Vector operation, reg+reg.
668 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
669 (ins VR128:$src1, VR128:$src2),
670 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
671 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
672 let isCommutable = Commutable;
675 // Vector operation, reg+mem.
676 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
677 (ins VR128:$src1, f128mem:$src2),
678 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
679 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
681 // Intrinsic operation, reg+reg.
682 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
683 (ins VR128:$src1, VR128:$src2),
684 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
685 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
687 // Intrinsic operation, reg+mem.
688 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
689 (ins VR128:$src1, ssmem:$src2),
690 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
691 [(set VR128:$dst, (F32Int VR128:$src1,
692 sse_load_f32:$src2))]>;
696 // Arithmetic instructions
697 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
698 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
699 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
700 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
702 /// sse1_fp_binop_rm - Other SSE1 binops
704 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
705 /// instructions for a full-vector intrinsic form. Operations that map
706 /// onto C operators don't use this form since they just use the plain
707 /// vector form instead of having a separate vector intrinsic form.
709 /// This provides a total of eight "instructions".
711 let Constraints = "$src1 = $dst" in {
712 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
716 bit Commutable = 0> {
718 // Scalar operation, reg+reg.
719 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
720 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
721 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
722 let isCommutable = Commutable;
725 // Scalar operation, reg+mem.
726 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
727 (ins FR32:$src1, f32mem:$src2),
728 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
729 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
731 // Vector operation, reg+reg.
732 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
733 (ins VR128:$src1, VR128:$src2),
734 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
735 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
736 let isCommutable = Commutable;
739 // Vector operation, reg+mem.
740 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
741 (ins VR128:$src1, f128mem:$src2),
742 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
743 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
745 // Intrinsic operation, reg+reg.
746 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
747 (ins VR128:$src1, VR128:$src2),
748 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
749 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
750 let isCommutable = Commutable;
753 // Intrinsic operation, reg+mem.
754 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
755 (ins VR128:$src1, ssmem:$src2),
756 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
757 [(set VR128:$dst, (F32Int VR128:$src1,
758 sse_load_f32:$src2))]>;
760 // Vector intrinsic operation, reg+reg.
761 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
762 (ins VR128:$src1, VR128:$src2),
763 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
764 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
765 let isCommutable = Commutable;
768 // Vector intrinsic operation, reg+mem.
769 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
770 (ins VR128:$src1, f128mem:$src2),
771 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
772 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
776 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
777 int_x86_sse_max_ss, int_x86_sse_max_ps>;
778 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
779 int_x86_sse_min_ss, int_x86_sse_min_ps>;
781 //===----------------------------------------------------------------------===//
782 // SSE packed FP Instructions
785 let neverHasSideEffects = 1 in
786 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
787 "movaps\t{$src, $dst|$dst, $src}", []>;
788 let canFoldAsLoad = 1, isReMaterializable = 1 in
789 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
790 "movaps\t{$src, $dst|$dst, $src}",
791 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
793 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
794 "movaps\t{$src, $dst|$dst, $src}",
795 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
797 let neverHasSideEffects = 1 in
798 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
799 "movups\t{$src, $dst|$dst, $src}", []>;
800 let canFoldAsLoad = 1, isReMaterializable = 1 in
801 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
802 "movups\t{$src, $dst|$dst, $src}",
803 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
804 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
805 "movups\t{$src, $dst|$dst, $src}",
806 [(store (v4f32 VR128:$src), addr:$dst)]>;
808 // Intrinsic forms of MOVUPS load and store
809 let canFoldAsLoad = 1, isReMaterializable = 1 in
810 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
811 "movups\t{$src, $dst|$dst, $src}",
812 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
813 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
814 "movups\t{$src, $dst|$dst, $src}",
815 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
817 let Constraints = "$src1 = $dst" in {
818 let AddedComplexity = 20 in {
819 def MOVLPSrm : PSI<0x12, MRMSrcMem,
820 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
821 "movlps\t{$src2, $dst|$dst, $src2}",
824 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
825 def MOVHPSrm : PSI<0x16, MRMSrcMem,
826 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
827 "movhps\t{$src2, $dst|$dst, $src2}",
829 (movlhps VR128:$src1,
830 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
832 } // Constraints = "$src1 = $dst"
835 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
836 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
838 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
839 "movlps\t{$src, $dst|$dst, $src}",
840 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
841 (iPTR 0))), addr:$dst)]>;
843 // v2f64 extract element 1 is always custom lowered to unpack high to low
844 // and extract element 0 so the non-store version isn't too horrible.
845 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
846 "movhps\t{$src, $dst|$dst, $src}",
847 [(store (f64 (vector_extract
848 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
849 (undef)), (iPTR 0))), addr:$dst)]>;
851 let Constraints = "$src1 = $dst" in {
852 let AddedComplexity = 20 in {
853 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
854 (ins VR128:$src1, VR128:$src2),
855 "movlhps\t{$src2, $dst|$dst, $src2}",
857 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
859 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
860 (ins VR128:$src1, VR128:$src2),
861 "movhlps\t{$src2, $dst|$dst, $src2}",
863 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
865 } // Constraints = "$src1 = $dst"
867 let AddedComplexity = 20 in {
868 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
869 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
870 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
871 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
878 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
880 /// In addition, we also have a special variant of the scalar form here to
881 /// represent the associated intrinsic operation. This form is unlike the
882 /// plain scalar form, in that it takes an entire vector (instead of a
883 /// scalar) and leaves the top elements undefined.
885 /// And, we have a special variant form for a full-vector intrinsic form.
887 /// These four forms can each have a reg or a mem operand, so there are a
888 /// total of eight "instructions".
890 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
894 bit Commutable = 0> {
895 // Scalar operation, reg.
896 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
897 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
898 [(set FR32:$dst, (OpNode FR32:$src))]> {
899 let isCommutable = Commutable;
902 // Scalar operation, mem.
903 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
904 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
905 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
906 Requires<[HasSSE1, OptForSize]>;
908 // Vector operation, reg.
909 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
910 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
911 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
912 let isCommutable = Commutable;
915 // Vector operation, mem.
916 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
917 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
918 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
920 // Intrinsic operation, reg.
921 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
922 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
923 [(set VR128:$dst, (F32Int VR128:$src))]> {
924 let isCommutable = Commutable;
927 // Intrinsic operation, mem.
928 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
929 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
930 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
932 // Vector intrinsic operation, reg
933 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
934 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
935 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
936 let isCommutable = Commutable;
939 // Vector intrinsic operation, mem
940 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
941 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
942 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
946 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
947 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
949 // Reciprocal approximations. Note that these typically require refinement
950 // in order to obtain suitable precision.
951 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
952 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
953 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
954 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
957 let Constraints = "$src1 = $dst" in {
958 let isCommutable = 1 in {
959 def ANDPSrr : PSI<0x54, MRMSrcReg,
960 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
961 "andps\t{$src2, $dst|$dst, $src2}",
962 [(set VR128:$dst, (v2i64
963 (and VR128:$src1, VR128:$src2)))]>;
964 def ORPSrr : PSI<0x56, MRMSrcReg,
965 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
966 "orps\t{$src2, $dst|$dst, $src2}",
967 [(set VR128:$dst, (v2i64
968 (or VR128:$src1, VR128:$src2)))]>;
969 def XORPSrr : PSI<0x57, MRMSrcReg,
970 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
971 "xorps\t{$src2, $dst|$dst, $src2}",
972 [(set VR128:$dst, (v2i64
973 (xor VR128:$src1, VR128:$src2)))]>;
976 def ANDPSrm : PSI<0x54, MRMSrcMem,
977 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
978 "andps\t{$src2, $dst|$dst, $src2}",
979 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
980 (memopv2i64 addr:$src2)))]>;
981 def ORPSrm : PSI<0x56, MRMSrcMem,
982 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
983 "orps\t{$src2, $dst|$dst, $src2}",
984 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
985 (memopv2i64 addr:$src2)))]>;
986 def XORPSrm : PSI<0x57, MRMSrcMem,
987 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
988 "xorps\t{$src2, $dst|$dst, $src2}",
989 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
990 (memopv2i64 addr:$src2)))]>;
991 def ANDNPSrr : PSI<0x55, MRMSrcReg,
992 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
993 "andnps\t{$src2, $dst|$dst, $src2}",
995 (v2i64 (and (xor VR128:$src1,
996 (bc_v2i64 (v4i32 immAllOnesV))),
998 def ANDNPSrm : PSI<0x55, MRMSrcMem,
999 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1000 "andnps\t{$src2, $dst|$dst, $src2}",
1002 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1003 (bc_v2i64 (v4i32 immAllOnesV))),
1004 (memopv2i64 addr:$src2))))]>;
1007 let Constraints = "$src1 = $dst" in {
1008 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1009 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1010 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1011 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1012 VR128:$src, imm:$cc))]>;
1013 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1014 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1015 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1016 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1017 (memop addr:$src), imm:$cc))]>;
1019 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1020 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1021 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1022 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1024 // Shuffle and unpack instructions
1025 let Constraints = "$src1 = $dst" in {
1026 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1027 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1028 (outs VR128:$dst), (ins VR128:$src1,
1029 VR128:$src2, i8imm:$src3),
1030 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1032 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1033 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1034 (outs VR128:$dst), (ins VR128:$src1,
1035 f128mem:$src2, i8imm:$src3),
1036 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1039 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1041 let AddedComplexity = 10 in {
1042 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1043 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1044 "unpckhps\t{$src2, $dst|$dst, $src2}",
1046 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1047 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1048 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1049 "unpckhps\t{$src2, $dst|$dst, $src2}",
1051 (v4f32 (unpckh VR128:$src1,
1052 (memopv4f32 addr:$src2))))]>;
1054 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1055 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1056 "unpcklps\t{$src2, $dst|$dst, $src2}",
1058 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1059 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1060 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1061 "unpcklps\t{$src2, $dst|$dst, $src2}",
1063 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1064 } // AddedComplexity
1065 } // Constraints = "$src1 = $dst"
1068 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1069 "movmskps\t{$src, $dst|$dst, $src}",
1070 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1071 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1072 "movmskpd\t{$src, $dst|$dst, $src}",
1073 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1075 // Prefetch intrinsic.
1076 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1077 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1078 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1079 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1080 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1081 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1082 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1083 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1085 // Non-temporal stores
1086 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1087 "movntps\t{$src, $dst|$dst, $src}",
1088 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1090 let AddedComplexity = 400 in { // Prefer non-temporal versions
1091 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1092 "movntps\t{$src, $dst|$dst, $src}",
1093 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1095 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1096 "movntdq\t{$src, $dst|$dst, $src}",
1097 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1099 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1100 "movnti\t{$src, $dst|$dst, $src}",
1101 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1102 TB, Requires<[HasSSE2]>;
1104 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1105 "movnti\t{$src, $dst|$dst, $src}",
1106 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1107 TB, Requires<[HasSSE2]>;
1110 // Load, store, and memory fence
1111 def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
1114 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1115 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1116 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1117 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1119 // Alias instructions that map zero vector to pxor / xorp* for sse.
1120 // We set canFoldAsLoad because this can be converted to a constant-pool
1121 // load of an all-zeros value if folding it would be beneficial.
1122 // FIXME: Change encoding to pseudo!
1123 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1124 isCodeGenOnly = 1 in
1125 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1126 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1128 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1129 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1130 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1131 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1132 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1134 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1135 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
1137 //===---------------------------------------------------------------------===//
1138 // SSE2 Instructions
1139 //===---------------------------------------------------------------------===//
1141 // Move Instructions. Register-to-register movsd is not used for FR64
1142 // register copies because it's a partial register update; FsMOVAPDrr is
1143 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1144 // because INSERT_SUBREG requires that the insert be implementable in terms of
1145 // a copy, and just mentioned, we don't use movsd for copies.
1146 let Constraints = "$src1 = $dst" in
1147 def MOVSDrr : SDI<0x10, MRMSrcReg,
1148 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1149 "movsd\t{$src2, $dst|$dst, $src2}",
1150 [(set (v2f64 VR128:$dst),
1151 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1153 // Extract the low 64-bit value from one vector and insert it into another.
1154 let AddedComplexity = 15 in
1155 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1156 (MOVSDrr (v2f64 VR128:$src1),
1157 (EXTRACT_SUBREG (v2f64 VR128:$src2), x86_subreg_sd))>;
1159 // Implicitly promote a 64-bit scalar to a vector.
1160 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1161 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, x86_subreg_sd)>;
1163 // Loading from memory automatically zeroing upper bits.
1164 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1165 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1166 "movsd\t{$src, $dst|$dst, $src}",
1167 [(set FR64:$dst, (loadf64 addr:$src))]>;
1169 // MOVSDrm zeros the high parts of the register; represent this
1170 // with SUBREG_TO_REG.
1171 let AddedComplexity = 20 in {
1172 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1173 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1174 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1175 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1176 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1177 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1178 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1179 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1180 def : Pat<(v2f64 (X86vzload addr:$src)),
1181 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1184 // Store scalar value to memory.
1185 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1186 "movsd\t{$src, $dst|$dst, $src}",
1187 [(store FR64:$src, addr:$dst)]>;
1189 // Extract and store.
1190 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1193 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
1195 // Conversion instructions
1196 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1197 "cvttsd2si\t{$src, $dst|$dst, $src}",
1198 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1199 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1200 "cvttsd2si\t{$src, $dst|$dst, $src}",
1201 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1202 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1203 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1204 [(set FR32:$dst, (fround FR64:$src))]>;
1205 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1206 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1207 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1208 Requires<[HasSSE2, OptForSize]>;
1209 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1210 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1211 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1212 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1213 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1214 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1216 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1217 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1218 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1219 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1220 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1221 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1222 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1223 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1224 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1225 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1226 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1227 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1228 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1229 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1230 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1231 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1232 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1233 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1234 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1235 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1237 // SSE2 instructions with XS prefix
1238 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1239 "cvtss2sd\t{$src, $dst|$dst, $src}",
1240 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1241 Requires<[HasSSE2]>;
1242 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1243 "cvtss2sd\t{$src, $dst|$dst, $src}",
1244 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1245 Requires<[HasSSE2, OptForSize]>;
1247 def : Pat<(extloadf32 addr:$src),
1248 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1249 Requires<[HasSSE2, OptForSpeed]>;
1251 // Match intrinsics which expect XMM operand(s).
1252 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1253 "cvtsd2si\t{$src, $dst|$dst, $src}",
1254 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1255 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1256 "cvtsd2si\t{$src, $dst|$dst, $src}",
1257 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1258 (load addr:$src)))]>;
1260 // Match intrinisics which expect MM and XMM operand(s).
1261 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1262 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1263 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1264 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1265 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1266 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1267 (memop addr:$src)))]>;
1268 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1269 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1270 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1271 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1272 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1273 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1274 (memop addr:$src)))]>;
1275 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1276 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1277 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1278 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1279 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1280 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1281 (load addr:$src)))]>;
1283 // Aliases for intrinsics
1284 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1285 "cvttsd2si\t{$src, $dst|$dst, $src}",
1287 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1288 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1289 "cvttsd2si\t{$src, $dst|$dst, $src}",
1290 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1291 (load addr:$src)))]>;
1293 // Comparison instructions
1294 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1295 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1296 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1297 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1299 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1300 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1301 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1304 let Defs = [EFLAGS] in {
1305 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1306 "ucomisd\t{$src2, $src1|$src1, $src2}",
1307 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
1308 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1309 "ucomisd\t{$src2, $src1|$src1, $src2}",
1310 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
1311 } // Defs = [EFLAGS]
1313 // Aliases to match intrinsics which expect XMM operand(s).
1314 let Constraints = "$src1 = $dst" in {
1315 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1317 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1318 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1319 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1320 VR128:$src, imm:$cc))]>;
1321 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1323 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1324 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1325 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1326 (load addr:$src), imm:$cc))]>;
1329 let Defs = [EFLAGS] in {
1330 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1331 "ucomisd\t{$src2, $src1|$src1, $src2}",
1332 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1334 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1335 "ucomisd\t{$src2, $src1|$src1, $src2}",
1336 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1337 (load addr:$src2)))]>;
1339 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1340 "comisd\t{$src2, $src1|$src1, $src2}",
1341 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1343 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1344 "comisd\t{$src2, $src1|$src1, $src2}",
1345 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1346 (load addr:$src2)))]>;
1347 } // Defs = [EFLAGS]
1349 // Aliases of packed SSE2 instructions for scalar use. These all have names
1350 // that start with 'Fs'.
1352 // Alias instructions that map fld0 to pxor for sse.
1353 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1354 canFoldAsLoad = 1 in
1355 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1356 [(set FR64:$dst, fpimm0)]>,
1357 Requires<[HasSSE2]>, TB, OpSize;
1359 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1361 let neverHasSideEffects = 1 in
1362 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1363 "movapd\t{$src, $dst|$dst, $src}", []>;
1365 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1367 let canFoldAsLoad = 1, isReMaterializable = 1 in
1368 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1369 "movapd\t{$src, $dst|$dst, $src}",
1370 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1372 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1373 let Constraints = "$src1 = $dst" in {
1374 let isCommutable = 1 in {
1375 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1376 (ins FR64:$src1, FR64:$src2),
1377 "andpd\t{$src2, $dst|$dst, $src2}",
1378 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1379 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1380 (ins FR64:$src1, FR64:$src2),
1381 "orpd\t{$src2, $dst|$dst, $src2}",
1382 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1383 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1384 (ins FR64:$src1, FR64:$src2),
1385 "xorpd\t{$src2, $dst|$dst, $src2}",
1386 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1389 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1390 (ins FR64:$src1, f128mem:$src2),
1391 "andpd\t{$src2, $dst|$dst, $src2}",
1392 [(set FR64:$dst, (X86fand FR64:$src1,
1393 (memopfsf64 addr:$src2)))]>;
1394 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1395 (ins FR64:$src1, f128mem:$src2),
1396 "orpd\t{$src2, $dst|$dst, $src2}",
1397 [(set FR64:$dst, (X86for FR64:$src1,
1398 (memopfsf64 addr:$src2)))]>;
1399 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1400 (ins FR64:$src1, f128mem:$src2),
1401 "xorpd\t{$src2, $dst|$dst, $src2}",
1402 [(set FR64:$dst, (X86fxor FR64:$src1,
1403 (memopfsf64 addr:$src2)))]>;
1405 let neverHasSideEffects = 1 in {
1406 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1407 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1408 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1410 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1411 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1412 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1416 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1418 /// In addition, we also have a special variant of the scalar form here to
1419 /// represent the associated intrinsic operation. This form is unlike the
1420 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1421 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1423 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1424 /// six "instructions".
1426 let Constraints = "$src1 = $dst" in {
1427 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1428 SDNode OpNode, Intrinsic F64Int,
1429 bit Commutable = 0> {
1430 // Scalar operation, reg+reg.
1431 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1432 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1433 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1434 let isCommutable = Commutable;
1437 // Scalar operation, reg+mem.
1438 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1439 (ins FR64:$src1, f64mem:$src2),
1440 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1441 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1443 // Vector operation, reg+reg.
1444 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1445 (ins VR128:$src1, VR128:$src2),
1446 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1447 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1448 let isCommutable = Commutable;
1451 // Vector operation, reg+mem.
1452 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1453 (ins VR128:$src1, f128mem:$src2),
1454 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1455 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1457 // Intrinsic operation, reg+reg.
1458 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1459 (ins VR128:$src1, VR128:$src2),
1460 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1461 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1463 // Intrinsic operation, reg+mem.
1464 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1465 (ins VR128:$src1, sdmem:$src2),
1466 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1467 [(set VR128:$dst, (F64Int VR128:$src1,
1468 sse_load_f64:$src2))]>;
1472 // Arithmetic instructions
1473 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1474 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1475 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1476 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1478 /// sse2_fp_binop_rm - Other SSE2 binops
1480 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1481 /// instructions for a full-vector intrinsic form. Operations that map
1482 /// onto C operators don't use this form since they just use the plain
1483 /// vector form instead of having a separate vector intrinsic form.
1485 /// This provides a total of eight "instructions".
1487 let Constraints = "$src1 = $dst" in {
1488 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1492 bit Commutable = 0> {
1494 // Scalar operation, reg+reg.
1495 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1496 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1497 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1498 let isCommutable = Commutable;
1501 // Scalar operation, reg+mem.
1502 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1503 (ins FR64:$src1, f64mem:$src2),
1504 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1505 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1507 // Vector operation, reg+reg.
1508 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1509 (ins VR128:$src1, VR128:$src2),
1510 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1511 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1512 let isCommutable = Commutable;
1515 // Vector operation, reg+mem.
1516 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1517 (ins VR128:$src1, f128mem:$src2),
1518 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1519 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1521 // Intrinsic operation, reg+reg.
1522 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1523 (ins VR128:$src1, VR128:$src2),
1524 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1525 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1526 let isCommutable = Commutable;
1529 // Intrinsic operation, reg+mem.
1530 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1531 (ins VR128:$src1, sdmem:$src2),
1532 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1533 [(set VR128:$dst, (F64Int VR128:$src1,
1534 sse_load_f64:$src2))]>;
1536 // Vector intrinsic operation, reg+reg.
1537 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1538 (ins VR128:$src1, VR128:$src2),
1539 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1540 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1541 let isCommutable = Commutable;
1544 // Vector intrinsic operation, reg+mem.
1545 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1546 (ins VR128:$src1, f128mem:$src2),
1547 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1548 [(set VR128:$dst, (V2F64Int VR128:$src1,
1549 (memopv2f64 addr:$src2)))]>;
1553 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1554 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1555 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1556 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1558 //===---------------------------------------------------------------------===//
1559 // SSE packed FP Instructions
1561 // Move Instructions
1562 let neverHasSideEffects = 1 in
1563 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1564 "movapd\t{$src, $dst|$dst, $src}", []>;
1565 let canFoldAsLoad = 1, isReMaterializable = 1 in
1566 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1567 "movapd\t{$src, $dst|$dst, $src}",
1568 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1570 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1571 "movapd\t{$src, $dst|$dst, $src}",
1572 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1574 let neverHasSideEffects = 1 in
1575 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1576 "movupd\t{$src, $dst|$dst, $src}", []>;
1577 let canFoldAsLoad = 1 in
1578 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1579 "movupd\t{$src, $dst|$dst, $src}",
1580 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1581 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1582 "movupd\t{$src, $dst|$dst, $src}",
1583 [(store (v2f64 VR128:$src), addr:$dst)]>;
1585 // Intrinsic forms of MOVUPD load and store
1586 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1587 "movupd\t{$src, $dst|$dst, $src}",
1588 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1589 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1590 "movupd\t{$src, $dst|$dst, $src}",
1591 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1593 let Constraints = "$src1 = $dst" in {
1594 let AddedComplexity = 20 in {
1595 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1596 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1597 "movlpd\t{$src2, $dst|$dst, $src2}",
1599 (v2f64 (movlp VR128:$src1,
1600 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1601 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1602 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1603 "movhpd\t{$src2, $dst|$dst, $src2}",
1605 (v2f64 (movlhps VR128:$src1,
1606 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1607 } // AddedComplexity
1608 } // Constraints = "$src1 = $dst"
1610 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1611 "movlpd\t{$src, $dst|$dst, $src}",
1612 [(store (f64 (vector_extract (v2f64 VR128:$src),
1613 (iPTR 0))), addr:$dst)]>;
1615 // v2f64 extract element 1 is always custom lowered to unpack high to low
1616 // and extract element 0 so the non-store version isn't too horrible.
1617 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1618 "movhpd\t{$src, $dst|$dst, $src}",
1619 [(store (f64 (vector_extract
1620 (v2f64 (unpckh VR128:$src, (undef))),
1621 (iPTR 0))), addr:$dst)]>;
1623 // SSE2 instructions without OpSize prefix
1624 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1625 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1626 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1627 TB, Requires<[HasSSE2]>;
1628 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1629 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1630 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1631 (bitconvert (memopv2i64 addr:$src))))]>,
1632 TB, Requires<[HasSSE2]>;
1634 // SSE2 instructions with XS prefix
1635 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1636 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1637 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1638 XS, Requires<[HasSSE2]>;
1639 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1640 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1641 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1642 (bitconvert (memopv2i64 addr:$src))))]>,
1643 XS, Requires<[HasSSE2]>;
1645 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1646 "cvtps2dq\t{$src, $dst|$dst, $src}",
1647 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1648 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1649 "cvtps2dq\t{$src, $dst|$dst, $src}",
1650 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1651 (memop addr:$src)))]>;
1652 // SSE2 packed instructions with XS prefix
1653 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1654 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1655 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1656 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1658 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1659 "cvttps2dq\t{$src, $dst|$dst, $src}",
1661 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1662 XS, Requires<[HasSSE2]>;
1663 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1664 "cvttps2dq\t{$src, $dst|$dst, $src}",
1665 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1666 (memop addr:$src)))]>,
1667 XS, Requires<[HasSSE2]>;
1669 // SSE2 packed instructions with XD prefix
1670 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1671 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1672 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1673 XD, Requires<[HasSSE2]>;
1674 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1675 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1676 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1677 (memop addr:$src)))]>,
1678 XD, Requires<[HasSSE2]>;
1680 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1681 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1682 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1683 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1684 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1685 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1686 (memop addr:$src)))]>;
1688 // SSE2 instructions without OpSize prefix
1689 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1690 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1691 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1692 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1694 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1695 "cvtps2pd\t{$src, $dst|$dst, $src}",
1696 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1697 TB, Requires<[HasSSE2]>;
1698 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1699 "cvtps2pd\t{$src, $dst|$dst, $src}",
1700 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1701 (load addr:$src)))]>,
1702 TB, Requires<[HasSSE2]>;
1704 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1705 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1706 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1707 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1710 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1711 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1712 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1713 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1714 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1715 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1716 (memop addr:$src)))]>;
1718 // Match intrinsics which expect XMM operand(s).
1719 // Aliases for intrinsics
1720 let Constraints = "$src1 = $dst" in {
1721 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1722 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1723 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1724 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1726 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1727 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1728 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1729 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1730 (loadi32 addr:$src2)))]>;
1731 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1732 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1733 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1734 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1736 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1737 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1738 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1739 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1740 (load addr:$src2)))]>;
1741 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1742 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1743 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1744 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1745 VR128:$src2))]>, XS,
1746 Requires<[HasSSE2]>;
1747 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1748 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1749 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1750 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1751 (load addr:$src2)))]>, XS,
1752 Requires<[HasSSE2]>;
1757 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1759 /// In addition, we also have a special variant of the scalar form here to
1760 /// represent the associated intrinsic operation. This form is unlike the
1761 /// plain scalar form, in that it takes an entire vector (instead of a
1762 /// scalar) and leaves the top elements undefined.
1764 /// And, we have a special variant form for a full-vector intrinsic form.
1766 /// These four forms can each have a reg or a mem operand, so there are a
1767 /// total of eight "instructions".
1769 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1773 bit Commutable = 0> {
1774 // Scalar operation, reg.
1775 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1776 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1777 [(set FR64:$dst, (OpNode FR64:$src))]> {
1778 let isCommutable = Commutable;
1781 // Scalar operation, mem.
1782 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1783 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1784 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1786 // Vector operation, reg.
1787 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1788 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1789 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1790 let isCommutable = Commutable;
1793 // Vector operation, mem.
1794 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1795 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1796 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1798 // Intrinsic operation, reg.
1799 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1800 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1801 [(set VR128:$dst, (F64Int VR128:$src))]> {
1802 let isCommutable = Commutable;
1805 // Intrinsic operation, mem.
1806 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1807 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1808 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1810 // Vector intrinsic operation, reg
1811 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1812 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1813 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1814 let isCommutable = Commutable;
1817 // Vector intrinsic operation, mem
1818 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1819 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1820 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1824 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1825 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1827 // There is no f64 version of the reciprocal approximation instructions.
1830 let Constraints = "$src1 = $dst" in {
1831 let isCommutable = 1 in {
1832 def ANDPDrr : PDI<0x54, MRMSrcReg,
1833 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1834 "andpd\t{$src2, $dst|$dst, $src2}",
1836 (and (bc_v2i64 (v2f64 VR128:$src1)),
1837 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1838 def ORPDrr : PDI<0x56, MRMSrcReg,
1839 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1840 "orpd\t{$src2, $dst|$dst, $src2}",
1842 (or (bc_v2i64 (v2f64 VR128:$src1)),
1843 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1844 def XORPDrr : PDI<0x57, MRMSrcReg,
1845 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1846 "xorpd\t{$src2, $dst|$dst, $src2}",
1848 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1849 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1852 def ANDPDrm : PDI<0x54, MRMSrcMem,
1853 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1854 "andpd\t{$src2, $dst|$dst, $src2}",
1856 (and (bc_v2i64 (v2f64 VR128:$src1)),
1857 (memopv2i64 addr:$src2)))]>;
1858 def ORPDrm : PDI<0x56, MRMSrcMem,
1859 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1860 "orpd\t{$src2, $dst|$dst, $src2}",
1862 (or (bc_v2i64 (v2f64 VR128:$src1)),
1863 (memopv2i64 addr:$src2)))]>;
1864 def XORPDrm : PDI<0x57, MRMSrcMem,
1865 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1866 "xorpd\t{$src2, $dst|$dst, $src2}",
1868 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1869 (memopv2i64 addr:$src2)))]>;
1870 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1871 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1872 "andnpd\t{$src2, $dst|$dst, $src2}",
1874 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1875 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1876 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1877 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1878 "andnpd\t{$src2, $dst|$dst, $src2}",
1880 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1881 (memopv2i64 addr:$src2)))]>;
1884 let Constraints = "$src1 = $dst" in {
1885 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1886 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1887 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1888 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1889 VR128:$src, imm:$cc))]>;
1890 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1891 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1892 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1893 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1894 (memop addr:$src), imm:$cc))]>;
1896 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1897 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1898 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1899 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1901 // Shuffle and unpack instructions
1902 let Constraints = "$src1 = $dst" in {
1903 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1904 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1905 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1907 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1908 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1909 (outs VR128:$dst), (ins VR128:$src1,
1910 f128mem:$src2, i8imm:$src3),
1911 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1914 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1916 let AddedComplexity = 10 in {
1917 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1918 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1919 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1921 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1922 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1923 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1924 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1926 (v2f64 (unpckh VR128:$src1,
1927 (memopv2f64 addr:$src2))))]>;
1929 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1930 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1931 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1933 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1934 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1935 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1936 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1938 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1939 } // AddedComplexity
1940 } // Constraints = "$src1 = $dst"
1943 //===---------------------------------------------------------------------===//
1944 // SSE integer instructions
1945 let ExeDomain = SSEPackedInt in {
1947 // Move Instructions
1948 let neverHasSideEffects = 1 in
1949 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1950 "movdqa\t{$src, $dst|$dst, $src}", []>;
1951 let canFoldAsLoad = 1, mayLoad = 1 in
1952 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1953 "movdqa\t{$src, $dst|$dst, $src}",
1954 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1956 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1957 "movdqa\t{$src, $dst|$dst, $src}",
1958 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1959 let canFoldAsLoad = 1, mayLoad = 1 in
1960 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1961 "movdqu\t{$src, $dst|$dst, $src}",
1962 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1963 XS, Requires<[HasSSE2]>;
1965 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1966 "movdqu\t{$src, $dst|$dst, $src}",
1967 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1968 XS, Requires<[HasSSE2]>;
1970 // Intrinsic forms of MOVDQU load and store
1971 let canFoldAsLoad = 1 in
1972 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1973 "movdqu\t{$src, $dst|$dst, $src}",
1974 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1975 XS, Requires<[HasSSE2]>;
1976 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1977 "movdqu\t{$src, $dst|$dst, $src}",
1978 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1979 XS, Requires<[HasSSE2]>;
1981 let Constraints = "$src1 = $dst" in {
1983 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1984 bit Commutable = 0> {
1985 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1986 (ins VR128:$src1, VR128:$src2),
1987 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1988 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1989 let isCommutable = Commutable;
1991 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1992 (ins VR128:$src1, i128mem:$src2),
1993 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1994 [(set VR128:$dst, (IntId VR128:$src1,
1995 (bitconvert (memopv2i64
1999 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2001 Intrinsic IntId, Intrinsic IntId2> {
2002 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2003 (ins VR128:$src1, VR128:$src2),
2004 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2005 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2006 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2007 (ins VR128:$src1, i128mem:$src2),
2008 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2009 [(set VR128:$dst, (IntId VR128:$src1,
2010 (bitconvert (memopv2i64 addr:$src2))))]>;
2011 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2012 (ins VR128:$src1, i32i8imm:$src2),
2013 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2014 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2017 /// PDI_binop_rm - Simple SSE2 binary operator.
2018 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2019 ValueType OpVT, bit Commutable = 0> {
2020 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2021 (ins VR128:$src1, VR128:$src2),
2022 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2023 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
2024 let isCommutable = Commutable;
2026 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2027 (ins VR128:$src1, i128mem:$src2),
2028 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2029 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2030 (bitconvert (memopv2i64 addr:$src2)))))]>;
2033 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2035 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2036 /// to collapse (bitconvert VT to VT) into its operand.
2038 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2039 bit Commutable = 0> {
2040 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2041 (ins VR128:$src1, VR128:$src2),
2042 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2043 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
2044 let isCommutable = Commutable;
2046 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2047 (ins VR128:$src1, i128mem:$src2),
2048 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2049 [(set VR128:$dst, (OpNode VR128:$src1,
2050 (memopv2i64 addr:$src2)))]>;
2053 } // Constraints = "$src1 = $dst"
2054 } // ExeDomain = SSEPackedInt
2056 // 128-bit Integer Arithmetic
2058 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2059 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2060 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2061 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2063 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2064 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2065 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2066 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2068 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2069 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2070 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2071 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2073 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2074 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2075 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2076 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2078 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2080 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2081 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
2082 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2084 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2086 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2087 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2090 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2091 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2092 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2093 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2094 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2097 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2098 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2099 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2100 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2101 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2102 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2104 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2105 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2106 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2107 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2108 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2109 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2111 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2112 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2113 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2114 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2116 // 128-bit logical shifts.
2117 let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
2118 ExeDomain = SSEPackedInt in {
2119 def PSLLDQri : PDIi8<0x73, MRM7r,
2120 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2121 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2122 def PSRLDQri : PDIi8<0x73, MRM3r,
2123 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2124 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2125 // PSRADQri doesn't exist in SSE[1-3].
2128 let Predicates = [HasSSE2] in {
2129 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2130 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2131 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2132 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2133 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2134 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2135 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2136 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2137 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2138 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2140 // Shift up / down and insert zero's.
2141 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2142 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2143 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2144 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2148 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2149 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2150 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2152 let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
2153 def PANDNrr : PDI<0xDF, MRMSrcReg,
2154 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2155 "pandn\t{$src2, $dst|$dst, $src2}",
2156 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2159 def PANDNrm : PDI<0xDF, MRMSrcMem,
2160 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2161 "pandn\t{$src2, $dst|$dst, $src2}",
2162 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2163 (memopv2i64 addr:$src2))))]>;
2166 // SSE2 Integer comparison
2167 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2168 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2169 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2170 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2171 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2172 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2174 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2175 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2176 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2177 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2178 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2179 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2180 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2181 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2182 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2183 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2184 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2185 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2187 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2188 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2189 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2190 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2191 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2192 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2193 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2194 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2195 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2196 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2197 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2198 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2201 // Pack instructions
2202 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2203 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2204 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2206 let ExeDomain = SSEPackedInt in {
2208 // Shuffle and unpack instructions
2209 let AddedComplexity = 5 in {
2210 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2211 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2212 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2213 [(set VR128:$dst, (v4i32 (pshufd:$src2
2214 VR128:$src1, (undef))))]>;
2215 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2216 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2217 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2218 [(set VR128:$dst, (v4i32 (pshufd:$src2
2219 (bc_v4i32 (memopv2i64 addr:$src1)),
2223 // SSE2 with ImmT == Imm8 and XS prefix.
2224 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2225 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2226 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2227 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2229 XS, Requires<[HasSSE2]>;
2230 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2231 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2232 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2233 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2234 (bc_v8i16 (memopv2i64 addr:$src1)),
2236 XS, Requires<[HasSSE2]>;
2238 // SSE2 with ImmT == Imm8 and XD prefix.
2239 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2240 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2241 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2242 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2244 XD, Requires<[HasSSE2]>;
2245 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2246 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2247 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2248 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2249 (bc_v8i16 (memopv2i64 addr:$src1)),
2251 XD, Requires<[HasSSE2]>;
2254 let Constraints = "$src1 = $dst" in {
2255 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2256 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2257 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2259 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2260 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2261 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2262 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2264 (unpckl VR128:$src1,
2265 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2266 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2267 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2268 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2270 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2271 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2272 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2273 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2275 (unpckl VR128:$src1,
2276 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2277 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2278 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2279 "punpckldq\t{$src2, $dst|$dst, $src2}",
2281 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2282 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2283 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2284 "punpckldq\t{$src2, $dst|$dst, $src2}",
2286 (unpckl VR128:$src1,
2287 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2288 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2289 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2290 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2292 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2293 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2294 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2295 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2297 (v2i64 (unpckl VR128:$src1,
2298 (memopv2i64 addr:$src2))))]>;
2300 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2301 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2302 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2304 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2305 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2306 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2307 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2309 (unpckh VR128:$src1,
2310 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2311 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2312 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2313 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2315 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2316 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2317 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2318 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2320 (unpckh VR128:$src1,
2321 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2322 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2323 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2324 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2326 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2327 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2328 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2329 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2331 (unpckh VR128:$src1,
2332 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2333 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2334 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2335 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2337 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2338 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2339 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2340 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2342 (v2i64 (unpckh VR128:$src1,
2343 (memopv2i64 addr:$src2))))]>;
2347 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2348 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2349 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2350 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2352 let Constraints = "$src1 = $dst" in {
2353 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2354 (outs VR128:$dst), (ins VR128:$src1,
2355 GR32:$src2, i32i8imm:$src3),
2356 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2358 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2359 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2360 (outs VR128:$dst), (ins VR128:$src1,
2361 i16mem:$src2, i32i8imm:$src3),
2362 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2364 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2369 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2370 "pmovmskb\t{$src, $dst|$dst, $src}",
2371 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2373 // Conditional store
2375 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2376 "maskmovdqu\t{$mask, $src|$src, $mask}",
2377 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2380 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2381 "maskmovdqu\t{$mask, $src|$src, $mask}",
2382 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2384 } // ExeDomain = SSEPackedInt
2386 // Non-temporal stores
2387 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2388 "movntpd\t{$src, $dst|$dst, $src}",
2389 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2390 let ExeDomain = SSEPackedInt in
2391 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2392 "movntdq\t{$src, $dst|$dst, $src}",
2393 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2394 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2395 "movnti\t{$src, $dst|$dst, $src}",
2396 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2397 TB, Requires<[HasSSE2]>;
2399 let AddedComplexity = 400 in { // Prefer non-temporal versions
2400 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2401 "movntpd\t{$src, $dst|$dst, $src}",
2402 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2404 let ExeDomain = SSEPackedInt in
2405 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2406 "movntdq\t{$src, $dst|$dst, $src}",
2407 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2411 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2412 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2413 TB, Requires<[HasSSE2]>;
2415 // Load, store, and memory fence
2416 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2417 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2418 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2419 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2421 //TODO: custom lower this so as to never even generate the noop
2422 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2424 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2425 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2426 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2429 // Alias instructions that map zero vector to pxor / xorp* for sse.
2430 // We set canFoldAsLoad because this can be converted to a constant-pool
2431 // load of an all-ones value if folding it would be beneficial.
2432 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2433 isCodeGenOnly = 1 in
2434 // FIXME: Change encoding to pseudo.
2435 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2436 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2438 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2439 "movd\t{$src, $dst|$dst, $src}",
2441 (v4i32 (scalar_to_vector GR32:$src)))]>;
2442 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2443 "movd\t{$src, $dst|$dst, $src}",
2445 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2447 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2448 "movd\t{$src, $dst|$dst, $src}",
2449 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2451 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2452 "movd\t{$src, $dst|$dst, $src}",
2453 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2455 // SSE2 instructions with XS prefix
2456 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2457 "movq\t{$src, $dst|$dst, $src}",
2459 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2460 Requires<[HasSSE2]>;
2461 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2462 "movq\t{$src, $dst|$dst, $src}",
2463 [(store (i64 (vector_extract (v2i64 VR128:$src),
2464 (iPTR 0))), addr:$dst)]>;
2466 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2467 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
2469 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2470 "movd\t{$src, $dst|$dst, $src}",
2471 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2473 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2474 "movd\t{$src, $dst|$dst, $src}",
2475 [(store (i32 (vector_extract (v4i32 VR128:$src),
2476 (iPTR 0))), addr:$dst)]>;
2478 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2479 "movd\t{$src, $dst|$dst, $src}",
2480 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2481 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2482 "movd\t{$src, $dst|$dst, $src}",
2483 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2485 // Store / copy lower 64-bits of a XMM register.
2486 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2487 "movq\t{$src, $dst|$dst, $src}",
2488 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2490 // movd / movq to XMM register zero-extends
2491 let AddedComplexity = 15 in {
2492 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2493 "movd\t{$src, $dst|$dst, $src}",
2494 [(set VR128:$dst, (v4i32 (X86vzmovl
2495 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2496 // This is X86-64 only.
2497 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2498 "mov{d|q}\t{$src, $dst|$dst, $src}",
2499 [(set VR128:$dst, (v2i64 (X86vzmovl
2500 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2503 let AddedComplexity = 20 in {
2504 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2505 "movd\t{$src, $dst|$dst, $src}",
2507 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2508 (loadi32 addr:$src))))))]>;
2510 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2511 (MOVZDI2PDIrm addr:$src)>;
2512 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2513 (MOVZDI2PDIrm addr:$src)>;
2514 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2515 (MOVZDI2PDIrm addr:$src)>;
2517 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2518 "movq\t{$src, $dst|$dst, $src}",
2520 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2521 (loadi64 addr:$src))))))]>, XS,
2522 Requires<[HasSSE2]>;
2524 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2525 (MOVZQI2PQIrm addr:$src)>;
2526 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2527 (MOVZQI2PQIrm addr:$src)>;
2528 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2531 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2532 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2533 let AddedComplexity = 15 in
2534 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2535 "movq\t{$src, $dst|$dst, $src}",
2536 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2537 XS, Requires<[HasSSE2]>;
2539 let AddedComplexity = 20 in {
2540 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2541 "movq\t{$src, $dst|$dst, $src}",
2542 [(set VR128:$dst, (v2i64 (X86vzmovl
2543 (loadv2i64 addr:$src))))]>,
2544 XS, Requires<[HasSSE2]>;
2546 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2547 (MOVZPQILo2PQIrm addr:$src)>;
2550 // Instructions for the disassembler
2551 // xr = XMM register
2554 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2555 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2557 //===---------------------------------------------------------------------===//
2558 // SSE3 Instructions
2559 //===---------------------------------------------------------------------===//
2561 // Move Instructions
2562 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2563 "movshdup\t{$src, $dst|$dst, $src}",
2564 [(set VR128:$dst, (v4f32 (movshdup
2565 VR128:$src, (undef))))]>;
2566 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2567 "movshdup\t{$src, $dst|$dst, $src}",
2568 [(set VR128:$dst, (movshdup
2569 (memopv4f32 addr:$src), (undef)))]>;
2571 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2572 "movsldup\t{$src, $dst|$dst, $src}",
2573 [(set VR128:$dst, (v4f32 (movsldup
2574 VR128:$src, (undef))))]>;
2575 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2576 "movsldup\t{$src, $dst|$dst, $src}",
2577 [(set VR128:$dst, (movsldup
2578 (memopv4f32 addr:$src), (undef)))]>;
2580 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2581 "movddup\t{$src, $dst|$dst, $src}",
2582 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2583 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2584 "movddup\t{$src, $dst|$dst, $src}",
2586 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2589 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2591 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2593 let AddedComplexity = 5 in {
2594 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2595 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2596 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2597 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2598 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2599 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2600 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2601 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2605 let Constraints = "$src1 = $dst" in {
2606 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2607 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2608 "addsubps\t{$src2, $dst|$dst, $src2}",
2609 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2611 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2612 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2613 "addsubps\t{$src2, $dst|$dst, $src2}",
2614 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2615 (memop addr:$src2)))]>;
2616 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2617 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2618 "addsubpd\t{$src2, $dst|$dst, $src2}",
2619 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2621 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2622 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2623 "addsubpd\t{$src2, $dst|$dst, $src2}",
2624 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2625 (memop addr:$src2)))]>;
2628 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2629 "lddqu\t{$src, $dst|$dst, $src}",
2630 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2633 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2634 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2635 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2636 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2637 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2638 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2639 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2640 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2641 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2642 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2643 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2644 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2645 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2646 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2647 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2648 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2650 let Constraints = "$src1 = $dst" in {
2651 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2652 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2653 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2654 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2655 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2656 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2657 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2658 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2661 // Thread synchronization
2662 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2663 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2664 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2665 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2667 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2668 let AddedComplexity = 15 in
2669 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2670 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2671 let AddedComplexity = 20 in
2672 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2673 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2675 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2676 let AddedComplexity = 15 in
2677 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2678 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2679 let AddedComplexity = 20 in
2680 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2681 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2683 //===---------------------------------------------------------------------===//
2684 // SSSE3 Instructions
2685 //===---------------------------------------------------------------------===//
2687 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2688 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2689 Intrinsic IntId64, Intrinsic IntId128> {
2690 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2691 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2692 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2694 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2695 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2697 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2699 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2701 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2702 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2705 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2707 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2710 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2713 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2714 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2715 Intrinsic IntId64, Intrinsic IntId128> {
2716 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2718 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2719 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2721 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2723 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2726 (bitconvert (memopv4i16 addr:$src))))]>;
2728 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2730 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2731 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2734 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2736 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2739 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2742 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2743 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2744 Intrinsic IntId64, Intrinsic IntId128> {
2745 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2747 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2748 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2750 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2752 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2755 (bitconvert (memopv2i32 addr:$src))))]>;
2757 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2759 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2760 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2763 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2765 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2768 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2771 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2772 int_x86_ssse3_pabs_b,
2773 int_x86_ssse3_pabs_b_128>;
2774 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2775 int_x86_ssse3_pabs_w,
2776 int_x86_ssse3_pabs_w_128>;
2777 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2778 int_x86_ssse3_pabs_d,
2779 int_x86_ssse3_pabs_d_128>;
2781 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2782 let Constraints = "$src1 = $dst" in {
2783 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2784 Intrinsic IntId64, Intrinsic IntId128,
2785 bit Commutable = 0> {
2786 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2787 (ins VR64:$src1, VR64:$src2),
2788 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2789 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2790 let isCommutable = Commutable;
2792 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2793 (ins VR64:$src1, i64mem:$src2),
2794 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2796 (IntId64 VR64:$src1,
2797 (bitconvert (memopv8i8 addr:$src2))))]>;
2799 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2800 (ins VR128:$src1, VR128:$src2),
2801 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2802 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2804 let isCommutable = Commutable;
2806 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2807 (ins VR128:$src1, i128mem:$src2),
2808 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2810 (IntId128 VR128:$src1,
2811 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2815 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2816 let Constraints = "$src1 = $dst" in {
2817 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2818 Intrinsic IntId64, Intrinsic IntId128,
2819 bit Commutable = 0> {
2820 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2821 (ins VR64:$src1, VR64:$src2),
2822 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2823 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2824 let isCommutable = Commutable;
2826 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2827 (ins VR64:$src1, i64mem:$src2),
2828 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2830 (IntId64 VR64:$src1,
2831 (bitconvert (memopv4i16 addr:$src2))))]>;
2833 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2834 (ins VR128:$src1, VR128:$src2),
2835 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2836 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2838 let isCommutable = Commutable;
2840 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2841 (ins VR128:$src1, i128mem:$src2),
2842 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2844 (IntId128 VR128:$src1,
2845 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2849 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2850 let Constraints = "$src1 = $dst" in {
2851 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2852 Intrinsic IntId64, Intrinsic IntId128,
2853 bit Commutable = 0> {
2854 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2855 (ins VR64:$src1, VR64:$src2),
2856 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2857 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2858 let isCommutable = Commutable;
2860 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2861 (ins VR64:$src1, i64mem:$src2),
2862 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2864 (IntId64 VR64:$src1,
2865 (bitconvert (memopv2i32 addr:$src2))))]>;
2867 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2868 (ins VR128:$src1, VR128:$src2),
2869 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2870 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2872 let isCommutable = Commutable;
2874 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2875 (ins VR128:$src1, i128mem:$src2),
2876 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2878 (IntId128 VR128:$src1,
2879 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2883 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2884 int_x86_ssse3_phadd_w,
2885 int_x86_ssse3_phadd_w_128>;
2886 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2887 int_x86_ssse3_phadd_d,
2888 int_x86_ssse3_phadd_d_128>;
2889 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2890 int_x86_ssse3_phadd_sw,
2891 int_x86_ssse3_phadd_sw_128>;
2892 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2893 int_x86_ssse3_phsub_w,
2894 int_x86_ssse3_phsub_w_128>;
2895 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2896 int_x86_ssse3_phsub_d,
2897 int_x86_ssse3_phsub_d_128>;
2898 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2899 int_x86_ssse3_phsub_sw,
2900 int_x86_ssse3_phsub_sw_128>;
2901 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2902 int_x86_ssse3_pmadd_ub_sw,
2903 int_x86_ssse3_pmadd_ub_sw_128>;
2904 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2905 int_x86_ssse3_pmul_hr_sw,
2906 int_x86_ssse3_pmul_hr_sw_128, 1>;
2907 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2908 int_x86_ssse3_pshuf_b,
2909 int_x86_ssse3_pshuf_b_128>;
2910 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2911 int_x86_ssse3_psign_b,
2912 int_x86_ssse3_psign_b_128>;
2913 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2914 int_x86_ssse3_psign_w,
2915 int_x86_ssse3_psign_w_128>;
2916 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2917 int_x86_ssse3_psign_d,
2918 int_x86_ssse3_psign_d_128>;
2920 let Constraints = "$src1 = $dst" in {
2921 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2922 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2923 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2925 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2926 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2927 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2930 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2931 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2932 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2934 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2935 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2936 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2940 // palignr patterns.
2941 def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)),
2942 (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>,
2943 Requires<[HasSSSE3]>;
2944 def : Pat<(int_x86_ssse3_palign_r VR64:$src1,
2945 (memop64 addr:$src2),
2947 (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2948 Requires<[HasSSSE3]>;
2950 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)),
2951 (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>,
2952 Requires<[HasSSSE3]>;
2953 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1,
2954 (memopv2i64 addr:$src2),
2956 (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2957 Requires<[HasSSSE3]>;
2959 let AddedComplexity = 5 in {
2960 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2961 (PALIGNR128rr VR128:$src2, VR128:$src1,
2962 (SHUFFLE_get_palign_imm VR128:$src3))>,
2963 Requires<[HasSSSE3]>;
2964 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2965 (PALIGNR128rr VR128:$src2, VR128:$src1,
2966 (SHUFFLE_get_palign_imm VR128:$src3))>,
2967 Requires<[HasSSSE3]>;
2968 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2969 (PALIGNR128rr VR128:$src2, VR128:$src1,
2970 (SHUFFLE_get_palign_imm VR128:$src3))>,
2971 Requires<[HasSSSE3]>;
2972 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2973 (PALIGNR128rr VR128:$src2, VR128:$src1,
2974 (SHUFFLE_get_palign_imm VR128:$src3))>,
2975 Requires<[HasSSSE3]>;
2978 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2979 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2980 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2981 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2983 //===---------------------------------------------------------------------===//
2984 // Non-Instruction Patterns
2985 //===---------------------------------------------------------------------===//
2987 // extload f32 -> f64. This matches load+fextend because we have a hack in
2988 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2990 // Since these loads aren't folded into the fextend, we have to match it
2992 let Predicates = [HasSSE2] in
2993 def : Pat<(fextend (loadf32 addr:$src)),
2994 (CVTSS2SDrm addr:$src)>;
2997 let Predicates = [HasSSE2] in {
2998 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2999 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3000 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3001 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3002 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3003 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3004 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3005 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3006 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3007 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3008 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3009 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3010 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3011 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3012 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3013 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3014 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3015 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3016 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3017 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3018 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3019 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3020 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3021 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3022 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3023 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3024 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3025 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3026 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3027 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3030 // Move scalar to XMM zero-extended
3031 // movd to XMM register zero-extends
3032 let AddedComplexity = 15 in {
3033 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3034 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3035 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
3036 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3037 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
3038 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3039 (MOVSSrr (v4f32 (V_SET0)),
3040 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss)))>;
3041 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3042 (MOVSSrr (v4i32 (V_SET0)),
3043 (EXTRACT_SUBREG (v4i32 VR128:$src), x86_subreg_ss))>;
3046 // Splat v2f64 / v2i64
3047 let AddedComplexity = 10 in {
3048 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3049 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3050 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3051 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3052 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3053 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3054 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3055 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3058 // Special unary SHUFPSrri case.
3059 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3060 (SHUFPSrri VR128:$src1, VR128:$src1,
3061 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3062 let AddedComplexity = 5 in
3063 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3064 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3065 Requires<[HasSSE2]>;
3066 // Special unary SHUFPDrri case.
3067 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3068 (SHUFPDrri VR128:$src1, VR128:$src1,
3069 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3070 Requires<[HasSSE2]>;
3071 // Special unary SHUFPDrri case.
3072 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3073 (SHUFPDrri VR128:$src1, VR128:$src1,
3074 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3075 Requires<[HasSSE2]>;
3076 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3077 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3078 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3079 Requires<[HasSSE2]>;
3081 // Special binary v4i32 shuffle cases with SHUFPS.
3082 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3083 (SHUFPSrri VR128:$src1, VR128:$src2,
3084 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3085 Requires<[HasSSE2]>;
3086 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3087 (SHUFPSrmi VR128:$src1, addr:$src2,
3088 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3089 Requires<[HasSSE2]>;
3090 // Special binary v2i64 shuffle cases using SHUFPDrri.
3091 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3092 (SHUFPDrri VR128:$src1, VR128:$src2,
3093 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3094 Requires<[HasSSE2]>;
3096 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3097 let AddedComplexity = 15 in {
3098 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3099 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3100 Requires<[OptForSpeed, HasSSE2]>;
3101 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3102 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3103 Requires<[OptForSpeed, HasSSE2]>;
3105 let AddedComplexity = 10 in {
3106 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3107 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3108 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3109 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3110 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3111 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3112 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3113 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3116 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3117 let AddedComplexity = 15 in {
3118 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3119 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3120 Requires<[OptForSpeed, HasSSE2]>;
3121 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3122 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3123 Requires<[OptForSpeed, HasSSE2]>;
3125 let AddedComplexity = 10 in {
3126 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3127 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3128 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3129 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3130 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3131 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3132 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3133 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3136 let AddedComplexity = 20 in {
3137 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3138 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3139 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3141 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3142 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3143 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3145 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3146 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3147 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3148 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3149 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3152 let AddedComplexity = 20 in {
3153 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3154 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3155 (MOVLPSrm VR128:$src1, addr:$src2)>;
3156 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3157 (MOVLPDrm VR128:$src1, addr:$src2)>;
3158 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3159 (MOVLPSrm VR128:$src1, addr:$src2)>;
3160 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3161 (MOVLPDrm VR128:$src1, addr:$src2)>;
3164 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3165 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3166 (MOVLPSmr addr:$src1, VR128:$src2)>;
3167 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3168 (MOVLPDmr addr:$src1, VR128:$src2)>;
3169 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3171 (MOVLPSmr addr:$src1, VR128:$src2)>;
3172 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3173 (MOVLPDmr addr:$src1, VR128:$src2)>;
3175 let AddedComplexity = 15 in {
3176 // Setting the lowest element in the vector.
3177 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3178 (MOVSSrr (v4i32 VR128:$src1),
3179 (EXTRACT_SUBREG (v4i32 VR128:$src2), x86_subreg_ss))>;
3180 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3181 (MOVSDrr (v2i64 VR128:$src1),
3182 (EXTRACT_SUBREG (v2i64 VR128:$src2), x86_subreg_sd))>;
3184 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3185 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3186 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3187 Requires<[HasSSE2]>;
3188 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3189 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3190 Requires<[HasSSE2]>;
3193 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3194 // fall back to this for SSE1)
3195 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3196 (SHUFPSrri VR128:$src2, VR128:$src1,
3197 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3199 // Set lowest element and zero upper elements.
3200 let AddedComplexity = 15 in
3201 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3202 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3204 // Some special case pandn patterns.
3205 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3207 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3208 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3210 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3211 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3213 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3215 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3216 (memop addr:$src2))),
3217 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3218 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3219 (memop addr:$src2))),
3220 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3221 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3222 (memop addr:$src2))),
3223 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3225 // vector -> vector casts
3226 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3227 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3228 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3229 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3230 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3231 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3232 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3233 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3235 // Use movaps / movups for SSE integer load / store (one byte shorter).
3236 def : Pat<(alignedloadv4i32 addr:$src),
3237 (MOVAPSrm addr:$src)>;
3238 def : Pat<(loadv4i32 addr:$src),
3239 (MOVUPSrm addr:$src)>;
3240 def : Pat<(alignedloadv2i64 addr:$src),
3241 (MOVAPSrm addr:$src)>;
3242 def : Pat<(loadv2i64 addr:$src),
3243 (MOVUPSrm addr:$src)>;
3245 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3246 (MOVAPSmr addr:$dst, VR128:$src)>;
3247 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3248 (MOVAPSmr addr:$dst, VR128:$src)>;
3249 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3250 (MOVAPSmr addr:$dst, VR128:$src)>;
3251 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3252 (MOVAPSmr addr:$dst, VR128:$src)>;
3253 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3254 (MOVUPSmr addr:$dst, VR128:$src)>;
3255 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3256 (MOVUPSmr addr:$dst, VR128:$src)>;
3257 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3258 (MOVUPSmr addr:$dst, VR128:$src)>;
3259 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3260 (MOVUPSmr addr:$dst, VR128:$src)>;
3262 //===----------------------------------------------------------------------===//
3263 // SSE4.1 Instructions
3264 //===----------------------------------------------------------------------===//
3266 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3269 Intrinsic V2F64Int> {
3270 // Intrinsic operation, reg.
3271 // Vector intrinsic operation, reg
3272 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3273 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3274 !strconcat(OpcodeStr,
3275 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3276 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3279 // Vector intrinsic operation, mem
3280 def PSm_Int : Ii8<opcps, MRMSrcMem,
3281 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3282 !strconcat(OpcodeStr,
3283 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3285 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3287 Requires<[HasSSE41]>;
3289 // Vector intrinsic operation, reg
3290 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3291 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3292 !strconcat(OpcodeStr,
3293 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3294 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3297 // Vector intrinsic operation, mem
3298 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3299 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3300 !strconcat(OpcodeStr,
3301 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3303 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3307 let Constraints = "$src1 = $dst" in {
3308 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3312 // Intrinsic operation, reg.
3313 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3315 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3316 !strconcat(OpcodeStr,
3317 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3319 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3322 // Intrinsic operation, mem.
3323 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3325 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3326 !strconcat(OpcodeStr,
3327 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3329 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3332 // Intrinsic operation, reg.
3333 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3335 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3336 !strconcat(OpcodeStr,
3337 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3339 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3342 // Intrinsic operation, mem.
3343 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3345 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3346 !strconcat(OpcodeStr,
3347 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3349 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3354 // FP round - roundss, roundps, roundsd, roundpd
3355 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3356 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3357 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3358 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3360 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3361 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3362 Intrinsic IntId128> {
3363 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3365 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3366 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3367 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3369 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3372 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3375 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3376 int_x86_sse41_phminposuw>;
3378 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3379 let Constraints = "$src1 = $dst" in {
3380 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3381 Intrinsic IntId128, bit Commutable = 0> {
3382 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3383 (ins VR128:$src1, VR128:$src2),
3384 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3385 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3387 let isCommutable = Commutable;
3389 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3390 (ins VR128:$src1, i128mem:$src2),
3391 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3393 (IntId128 VR128:$src1,
3394 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3398 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3399 int_x86_sse41_pcmpeqq, 1>;
3400 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3401 int_x86_sse41_packusdw, 0>;
3402 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3403 int_x86_sse41_pminsb, 1>;
3404 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3405 int_x86_sse41_pminsd, 1>;
3406 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3407 int_x86_sse41_pminud, 1>;
3408 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3409 int_x86_sse41_pminuw, 1>;
3410 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3411 int_x86_sse41_pmaxsb, 1>;
3412 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3413 int_x86_sse41_pmaxsd, 1>;
3414 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3415 int_x86_sse41_pmaxud, 1>;
3416 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3417 int_x86_sse41_pmaxuw, 1>;
3419 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3421 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3422 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3423 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3424 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3426 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3427 let Constraints = "$src1 = $dst" in {
3428 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3429 SDNode OpNode, Intrinsic IntId128,
3430 bit Commutable = 0> {
3431 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3432 (ins VR128:$src1, VR128:$src2),
3433 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3434 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3435 VR128:$src2))]>, OpSize {
3436 let isCommutable = Commutable;
3438 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3439 (ins VR128:$src1, VR128:$src2),
3440 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3441 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3443 let isCommutable = Commutable;
3445 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3446 (ins VR128:$src1, i128mem:$src2),
3447 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3449 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3450 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3451 (ins VR128:$src1, i128mem:$src2),
3452 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3454 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3458 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3459 int_x86_sse41_pmulld, 1>;
3461 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3462 let Constraints = "$src1 = $dst" in {
3463 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3464 Intrinsic IntId128, bit Commutable = 0> {
3465 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3466 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3467 !strconcat(OpcodeStr,
3468 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3470 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3472 let isCommutable = Commutable;
3474 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3475 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3476 !strconcat(OpcodeStr,
3477 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3479 (IntId128 VR128:$src1,
3480 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3485 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3486 int_x86_sse41_blendps, 0>;
3487 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3488 int_x86_sse41_blendpd, 0>;
3489 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3490 int_x86_sse41_pblendw, 0>;
3491 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3492 int_x86_sse41_dpps, 1>;
3493 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3494 int_x86_sse41_dppd, 1>;
3495 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3496 int_x86_sse41_mpsadbw, 1>;
3499 /// SS41I_ternary_int - SSE 4.1 ternary operator
3500 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3501 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3502 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3503 (ins VR128:$src1, VR128:$src2),
3504 !strconcat(OpcodeStr,
3505 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3506 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3509 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3510 (ins VR128:$src1, i128mem:$src2),
3511 !strconcat(OpcodeStr,
3512 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3515 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3519 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3520 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3521 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3524 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3525 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3526 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3527 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3529 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3530 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3532 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3536 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3537 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3538 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3539 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3540 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3541 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3543 // Common patterns involving scalar load.
3544 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3545 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3546 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3547 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3549 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3550 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3551 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3552 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3554 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3555 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3556 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3557 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3559 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3560 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3561 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3562 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3564 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3565 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3566 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3567 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3569 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3570 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3571 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3572 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3575 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3576 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3577 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3578 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3580 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3581 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3583 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3587 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3588 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3589 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3590 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3592 // Common patterns involving scalar load
3593 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3594 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3595 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3596 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3598 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3599 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3600 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3601 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3604 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3605 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3606 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3607 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3609 // Expecting a i16 load any extended to i32 value.
3610 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3611 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3612 [(set VR128:$dst, (IntId (bitconvert
3613 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3617 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3618 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3620 // Common patterns involving scalar load
3621 def : Pat<(int_x86_sse41_pmovsxbq
3622 (bitconvert (v4i32 (X86vzmovl
3623 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3624 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3626 def : Pat<(int_x86_sse41_pmovzxbq
3627 (bitconvert (v4i32 (X86vzmovl
3628 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3629 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3632 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3633 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3634 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3635 (ins VR128:$src1, i32i8imm:$src2),
3636 !strconcat(OpcodeStr,
3637 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3638 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3640 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3641 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3642 !strconcat(OpcodeStr,
3643 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3646 // There's an AssertZext in the way of writing the store pattern
3647 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3650 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3653 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3654 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3655 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3656 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3657 !strconcat(OpcodeStr,
3658 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3661 // There's an AssertZext in the way of writing the store pattern
3662 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3665 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3668 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3669 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3670 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3671 (ins VR128:$src1, i32i8imm:$src2),
3672 !strconcat(OpcodeStr,
3673 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3675 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3676 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3677 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3678 !strconcat(OpcodeStr,
3679 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3680 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3681 addr:$dst)]>, OpSize;
3684 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3687 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3689 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3690 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3691 (ins VR128:$src1, i32i8imm:$src2),
3692 !strconcat(OpcodeStr,
3693 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3695 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3697 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3698 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3699 !strconcat(OpcodeStr,
3700 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3701 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3702 addr:$dst)]>, OpSize;
3705 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3707 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3708 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3711 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3712 Requires<[HasSSE41]>;
3714 let Constraints = "$src1 = $dst" in {
3715 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3716 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3717 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3718 !strconcat(OpcodeStr,
3719 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3721 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3722 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3723 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3724 !strconcat(OpcodeStr,
3725 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3727 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3728 imm:$src3))]>, OpSize;
3732 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3734 let Constraints = "$src1 = $dst" in {
3735 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3736 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3737 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3738 !strconcat(OpcodeStr,
3739 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3741 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3743 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3744 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3745 !strconcat(OpcodeStr,
3746 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3748 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3749 imm:$src3)))]>, OpSize;
3753 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3755 // insertps has a few different modes, there's the first two here below which
3756 // are optimized inserts that won't zero arbitrary elements in the destination
3757 // vector. The next one matches the intrinsic and could zero arbitrary elements
3758 // in the target vector.
3759 let Constraints = "$src1 = $dst" in {
3760 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3761 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3762 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3763 !strconcat(OpcodeStr,
3764 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3766 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3768 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3769 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3770 !strconcat(OpcodeStr,
3771 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3773 (X86insrtps VR128:$src1,
3774 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3775 imm:$src3))]>, OpSize;
3779 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3781 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3782 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3784 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3785 // the intel intrinsic that corresponds to this.
3786 let Defs = [EFLAGS] in {
3787 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3788 "ptest \t{$src2, $src1|$src1, $src2}",
3789 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
3791 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3792 "ptest \t{$src2, $src1|$src1, $src2}",
3793 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
3797 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3798 "movntdqa\t{$src, $dst|$dst, $src}",
3799 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3803 //===----------------------------------------------------------------------===//
3804 // SSE4.2 Instructions
3805 //===----------------------------------------------------------------------===//
3807 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3808 let Constraints = "$src1 = $dst" in {
3809 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3810 Intrinsic IntId128, bit Commutable = 0> {
3811 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3812 (ins VR128:$src1, VR128:$src2),
3813 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3814 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3816 let isCommutable = Commutable;
3818 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3819 (ins VR128:$src1, i128mem:$src2),
3820 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3822 (IntId128 VR128:$src1,
3823 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3827 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3829 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3830 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3831 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3832 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3834 defm AESIMC : SS42I_binop_rm_int<0xDB, "aesimc",
3835 int_x86_sse42_aesimc>;
3836 defm AESENC : SS42I_binop_rm_int<0xDC, "aesenc",
3837 int_x86_sse42_aesenc>;
3838 defm AESENCLAST : SS42I_binop_rm_int<0xDD, "aesenclast",
3839 int_x86_sse42_aesenclast>;
3840 defm AESDEC : SS42I_binop_rm_int<0xDE, "aesdec",
3841 int_x86_sse42_aesdec>;
3842 defm AESDECLAST : SS42I_binop_rm_int<0xDF, "aesdeclast",
3843 int_x86_sse42_aesdeclast>;
3845 def : Pat<(v2i64 (X86aesimc VR128:$src1, VR128:$src2)),
3846 (AESIMCrr VR128:$src1, VR128:$src2)>;
3847 def : Pat<(v2i64 (X86aesimc VR128:$src1, (memop addr:$src2))),
3848 (AESIMCrm VR128:$src1, addr:$src2)>;
3849 def : Pat<(v2i64 (X86aesenc VR128:$src1, VR128:$src2)),
3850 (AESENCrr VR128:$src1, VR128:$src2)>;
3851 def : Pat<(v2i64 (X86aesenc VR128:$src1, (memop addr:$src2))),
3852 (AESENCrm VR128:$src1, addr:$src2)>;
3853 def : Pat<(v2i64 (X86aesenclast VR128:$src1, VR128:$src2)),
3854 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
3855 def : Pat<(v2i64 (X86aesenclast VR128:$src1, (memop addr:$src2))),
3856 (AESENCLASTrm VR128:$src1, addr:$src2)>;
3857 def : Pat<(v2i64 (X86aesdec VR128:$src1, VR128:$src2)),
3858 (AESDECrr VR128:$src1, VR128:$src2)>;
3859 def : Pat<(v2i64 (X86aesdec VR128:$src1, (memop addr:$src2))),
3860 (AESDECrm VR128:$src1, addr:$src2)>;
3861 def : Pat<(v2i64 (X86aesdeclast VR128:$src1, VR128:$src2)),
3862 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
3863 def : Pat<(v2i64 (X86aesdeclast VR128:$src1, (memop addr:$src2))),
3864 (AESDECLASTrm VR128:$src1, addr:$src2)>;
3866 def AESKEYGENASSIST128rr : SS42AI<0xDF, MRMSrcReg, (outs),
3867 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3868 "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3869 def AESKEYGENASSIST128rm : SS42AI<0xDF, MRMSrcMem, (outs),
3870 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3871 "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3873 // crc intrinsic instruction
3874 // This set of instructions are only rm, the only difference is the size
3876 let Constraints = "$src1 = $dst" in {
3877 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3878 (ins GR32:$src1, i8mem:$src2),
3879 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3881 (int_x86_sse42_crc32_8 GR32:$src1,
3882 (load addr:$src2)))]>;
3883 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3884 (ins GR32:$src1, GR8:$src2),
3885 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3887 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3888 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3889 (ins GR32:$src1, i16mem:$src2),
3890 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3892 (int_x86_sse42_crc32_16 GR32:$src1,
3893 (load addr:$src2)))]>,
3895 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3896 (ins GR32:$src1, GR16:$src2),
3897 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3899 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3901 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3902 (ins GR32:$src1, i32mem:$src2),
3903 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3905 (int_x86_sse42_crc32_32 GR32:$src1,
3906 (load addr:$src2)))]>;
3907 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3908 (ins GR32:$src1, GR32:$src2),
3909 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3911 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3912 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3913 (ins GR64:$src1, i8mem:$src2),
3914 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3916 (int_x86_sse42_crc64_8 GR64:$src1,
3917 (load addr:$src2)))]>,
3919 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3920 (ins GR64:$src1, GR8:$src2),
3921 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3923 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3925 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3926 (ins GR64:$src1, i64mem:$src2),
3927 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3929 (int_x86_sse42_crc64_64 GR64:$src1,
3930 (load addr:$src2)))]>,
3932 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3933 (ins GR64:$src1, GR64:$src2),
3934 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3936 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3940 // String/text processing instructions.
3941 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3942 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3943 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3944 "#PCMPISTRM128rr PSEUDO!",
3945 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3946 imm:$src3))]>, OpSize;
3947 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3948 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3949 "#PCMPISTRM128rm PSEUDO!",
3950 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3951 imm:$src3))]>, OpSize;
3954 let Defs = [XMM0, EFLAGS] in {
3955 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3956 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3957 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3958 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3959 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3960 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3963 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3964 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3965 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3966 "#PCMPESTRM128rr PSEUDO!",
3968 (int_x86_sse42_pcmpestrm128
3969 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3971 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3972 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3973 "#PCMPESTRM128rm PSEUDO!",
3974 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3975 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3979 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3980 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3981 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3982 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3983 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3984 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3985 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3988 let Defs = [ECX, EFLAGS] in {
3989 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3990 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3991 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3992 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3993 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3994 (implicit EFLAGS)]>, OpSize;
3995 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3996 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3997 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3998 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3999 (implicit EFLAGS)]>, OpSize;
4003 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4004 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4005 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4006 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4007 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4008 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4010 let Defs = [ECX, EFLAGS] in {
4011 let Uses = [EAX, EDX] in {
4012 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
4013 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4014 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4015 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4016 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4017 (implicit EFLAGS)]>, OpSize;
4018 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4019 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4020 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4022 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4023 (implicit EFLAGS)]>, OpSize;
4028 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4029 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4030 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4031 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4032 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4033 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;